Merge drm/drm-next into drm-misc-next

We need commit f8f6ae5d077a ("mm: always have io_remap_pfn_range() set
pgprot_decrypted()") to be able to merge Jason's cleanup patch.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

911 files changed, 294963 insertions, 7213 deletions

diff --git a/Documentation/ABI/stable/sysfs-driver-dma-ioatdma b/Documentation/ABI/stable/sysfs-driver-dma-ioatdma
index 420c1d09e42f..3a4e2cd0ddcc 100644
--- a/Documentation/ABI/stable/sysfs-driver-dma-ioatdma
+++ b/Documentation/ABI/stable/sysfs-driver-dma-ioatdma
@@ -1,29 +1,29 @@
-What:           sys/devices/pciXXXX:XX/0000:XX:XX.X/dma/dma<n>chan<n>/quickdata/cap
+What:           /sys/devices/pciXXXX:XX/0000:XX:XX.X/dma/dma<n>chan<n>/quickdata/cap
 Date:           December 3, 2009
 KernelVersion:  2.6.32
 Contact:        dmaengine@vger.kernel.org
 Description:	Capabilities the DMA supports.Currently there are DMA_PQ, DMA_PQ_VAL,
 		DMA_XOR,DMA_XOR_VAL,DMA_INTERRUPT.
 
-What:           sys/devices/pciXXXX:XX/0000:XX:XX.X/dma/dma<n>chan<n>/quickdata/ring_active
+What:           /sys/devices/pciXXXX:XX/0000:XX:XX.X/dma/dma<n>chan<n>/quickdata/ring_active
 Date:           December 3, 2009
 KernelVersion:  2.6.32
 Contact:        dmaengine@vger.kernel.org
 Description:	The number of descriptors active in the ring.
 
-What:           sys/devices/pciXXXX:XX/0000:XX:XX.X/dma/dma<n>chan<n>/quickdata/ring_size
+What:           /sys/devices/pciXXXX:XX/0000:XX:XX.X/dma/dma<n>chan<n>/quickdata/ring_size
 Date:           December 3, 2009
 KernelVersion:  2.6.32
 Contact:        dmaengine@vger.kernel.org
 Description:	Descriptor ring size, total number of descriptors available.
 
-What:           sys/devices/pciXXXX:XX/0000:XX:XX.X/dma/dma<n>chan<n>/quickdata/version
+What:           /sys/devices/pciXXXX:XX/0000:XX:XX.X/dma/dma<n>chan<n>/quickdata/version
 Date:           December 3, 2009
 KernelVersion:  2.6.32
 Contact:        dmaengine@vger.kernel.org
 Description:	Version of ioatdma device.
 
-What:           sys/devices/pciXXXX:XX/0000:XX:XX.X/dma/dma<n>chan<n>/quickdata/intr_coalesce
+What:           /sys/devices/pciXXXX:XX/0000:XX:XX.X/dma/dma<n>chan<n>/quickdata/intr_coalesce
 Date:           August 8, 2017
 KernelVersion:  4.14
 Contact:        dmaengine@vger.kernel.org
diff --git a/Documentation/ABI/testing/sysfs-class-net b/Documentation/ABI/testing/sysfs-class-net
index 7670012ae9b6..1f2002df5ba2 100644
--- a/Documentation/ABI/testing/sysfs-class-net
+++ b/Documentation/ABI/testing/sysfs-class-net
@@ -152,7 +152,7 @@ Description:
 		When an interface is under test, it cannot be expected
 		to pass packets as normal.
 
-What:		/sys/clas/net/<iface>/duplex
+What:		/sys/class/net/<iface>/duplex
 Date:		October 2009
 KernelVersion:	2.6.33
 Contact:	netdev@vger.kernel.org
diff --git a/Documentation/Makefile b/Documentation/Makefile
index 6a59a13d3c53..61a7310b49e0 100644
--- a/Documentation/Makefile
+++ b/Documentation/Makefile
@@ -26,6 +26,10 @@ BUILDDIR      = $(obj)/output
 PDFLATEX      = xelatex
 LATEXOPTS     = -interaction=batchmode
 
+ifeq ($(KBUILD_VERBOSE),0)
+SPHINXOPTS    += "-q"
+endif
+
 # User-friendly check for sphinx-build
 HAVE_SPHINX := $(shell if which $(SPHINXBUILD) >/dev/null 2>&1; then echo 1; else echo 0; fi)
 
diff --git a/Documentation/admin-guide/LSM/SafeSetID.rst b/Documentation/admin-guide/LSM/SafeSetID.rst
index 17996c9070e2..0ec34863c674 100644
--- a/Documentation/admin-guide/LSM/SafeSetID.rst
+++ b/Documentation/admin-guide/LSM/SafeSetID.rst
@@ -107,7 +107,7 @@ for a UID/GID will prevent that UID/GID from obtaining auxiliary setid
 privileges, such as allowing a user to set up user namespace UID/GID mappings.
 
 Note on GID policies and setgroups()
-==================
+====================================
 In v5.9 we are adding support for limiting CAP_SETGID privileges as was done
 previously for CAP_SETUID. However, for compatibility with common sandboxing
 related code conventions in userspace, we currently allow arbitrary
diff --git a/Documentation/admin-guide/pm/cpuidle.rst b/Documentation/admin-guide/pm/cpuidle.rst
index 37940a0584ec..10fde58d0869 100644
--- a/Documentation/admin-guide/pm/cpuidle.rst
+++ b/Documentation/admin-guide/pm/cpuidle.rst
@@ -478,7 +478,7 @@ order to ask the hardware to enter that state.  Also, for each
 statistics of the given idle state.  That information is exposed by the kernel
 via ``sysfs``.
 
-For each CPU in the system, there is a :file:`/sys/devices/system/cpu<N>/cpuidle/`
+For each CPU in the system, there is a :file:`/sys/devices/system/cpu/cpu<N>/cpuidle/`
 directory in ``sysfs``, where the number ``<N>`` is assigned to the given
 CPU at the initialization time.  That directory contains a set of subdirectories
 called :file:`state0`, :file:`state1` and so on, up to the number of idle state
@@ -494,7 +494,7 @@ object corresponding to it, as follows:
 	residency.
 
 ``below``
-	Total number of times this idle state had been asked for, but cerainly
+	Total number of times this idle state had been asked for, but certainly
 	a deeper idle state would have been a better match for the observed idle
 	duration.
 
diff --git a/Documentation/admin-guide/sysctl/net.rst b/Documentation/admin-guide/sysctl/net.rst
index 57fd6ce68fe0..f2ab8a5b6a4b 100644
--- a/Documentation/admin-guide/sysctl/net.rst
+++ b/Documentation/admin-guide/sysctl/net.rst
@@ -300,6 +300,7 @@ Note:
       0:    0     1     2     3     4     5     6     7
   RSS hash key:
   84:50:f4:00:a8:15:d1:a7:e9:7f:1d:60:35:c7:47:25:42:97:74:ca:56:bb:b6:a1:d8:43:e3:c9:0c:fd:17:55:c2:3a:4d:69:ed:f1:42:89
+
 netdev_tstamp_prequeue
 ----------------------
 
diff --git a/Documentation/arm/sunxi.rst b/Documentation/arm/sunxi.rst
index 62b533d0ba94..0c536ae1d7c2 100644
--- a/Documentation/arm/sunxi.rst
+++ b/Documentation/arm/sunxi.rst
@@ -148,3 +148,13 @@ SunXi family
         * User Manual
 
           http://dl.linux-sunxi.org/A64/Allwinner%20A64%20User%20Manual%20v1.0.pdf
+
+      - Allwinner H6
+
+	* Datasheet
+
+	  https://linux-sunxi.org/images/5/5c/Allwinner_H6_V200_Datasheet_V1.1.pdf
+
+	* User Manual
+
+	  https://linux-sunxi.org/images/4/46/Allwinner_H6_V200_User_Manual_V1.1.pdf
diff --git a/Documentation/conf.py b/Documentation/conf.py
index 1e44983853a2..ed2b43ec7754 100644
--- a/Documentation/conf.py
+++ b/Documentation/conf.py
@@ -51,7 +51,7 @@ if major >= 3:
         support for Sphinx v3.0 and above is brand new. Be prepared for
         possible issues in the generated output.
         ''')
-    if minor > 0 or patch >= 2:
+    if (major > 3) or (minor > 0 or patch >= 2):
         # Sphinx c function parser is more pedantic with regards to type
         # checking. Due to that, having macros at c:function cause problems.
         # Those needed to be scaped by using c_id_attributes[] array
diff --git a/Documentation/dev-tools/kasan.rst b/Documentation/dev-tools/kasan.rst
index c09c9ca2ff1c..2b68addaadcd 100644
--- a/Documentation/dev-tools/kasan.rst
+++ b/Documentation/dev-tools/kasan.rst
@@ -295,11 +295,13 @@ print the number of the test and the status of the test:
 pass::
 
         ok 28 - kmalloc_double_kzfree
+
 or, if kmalloc failed::
 
         # kmalloc_large_oob_right: ASSERTION FAILED at lib/test_kasan.c:163
         Expected ptr is not null, but is
         not ok 4 - kmalloc_large_oob_right
+
 or, if a KASAN report was expected, but not found::
 
         # kmalloc_double_kzfree: EXPECTATION FAILED at lib/test_kasan.c:629
diff --git a/Documentation/dev-tools/kunit/start.rst b/Documentation/dev-tools/kunit/start.rst
index d23385e3e159..454f307813ea 100644
--- a/Documentation/dev-tools/kunit/start.rst
+++ b/Documentation/dev-tools/kunit/start.rst
@@ -197,7 +197,7 @@ Now add the following to ``drivers/misc/Kconfig``:
 
 	config MISC_EXAMPLE_TEST
 		bool "Test for my example"
-		depends on MISC_EXAMPLE && KUNIT
+		depends on MISC_EXAMPLE && KUNIT=y
 
 and the following to ``drivers/misc/Makefile``:
 
diff --git a/Documentation/dev-tools/kunit/usage.rst b/Documentation/dev-tools/kunit/usage.rst
index 961d3ea3ca19..62142a47488c 100644
--- a/Documentation/dev-tools/kunit/usage.rst
+++ b/Documentation/dev-tools/kunit/usage.rst
@@ -561,6 +561,11 @@ Once the kernel is built and installed, a simple
 
 ...will run the tests.
 
+.. note::
+   Note that you should make sure your test depends on ``KUNIT=y`` in Kconfig
+   if the test does not support module build.  Otherwise, it will trigger
+   compile errors if ``CONFIG_KUNIT`` is ``m``.
+
 Writing new tests for other architectures
 -----------------------------------------
 
diff --git a/Documentation/devicetree/bindings/clock/hi6220-clock.txt b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
index ef3deb7b86ea..17ac4a3dd26a 100644
--- a/Documentation/devicetree/bindings/clock/hi6220-clock.txt
+++ b/Documentation/devicetree/bindings/clock/hi6220-clock.txt
@@ -4,7 +4,7 @@ Clock control registers reside in different Hi6220 system controllers,
 please refer the following document to know more about the binding rules
 for these system controllers:
 
-Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
 
 Required Properties:
 
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
index f6c3fcc4bdfd..b5af12011499 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
@@ -32,6 +32,11 @@ description: |
                        | | vint  | bit  |  | 0 |.....|63| vintx  |
                        | +--------------+  +------------+        |
                        |                                         |
+                       |      Unmap                              |
+                       | +--------------+                        |
+  Unmapped events ---->| |   umapidx    |-------------------------> Globalevents
+                       | +--------------+                        |
+                       |                                         |
                        +-----------------------------------------+
 
   Configuration of these Intmap registers that maps global events to vint is
@@ -70,6 +75,11 @@ properties:
         - description: |
             "limit" specifies the limit for translation
 
+  ti,unmapped-event-sources:
+    $ref: /schemas/types.yaml#definitions/phandle-array
+    description:
+      Array of phandles to DMA controllers where the unmapped events originate.
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/net/can/can-controller.yaml b/Documentation/devicetree/bindings/net/can/can-controller.yaml
new file mode 100644
index 000000000000..9cf2ae097156
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/can-controller.yaml
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/can-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CAN Controller Generic Binding
+
+maintainers:
+  - Marc Kleine-Budde <mkl@pengutronix.de>
+
+properties:
+  $nodename:
+    pattern: "^can(@.*)?$"
+
+additionalProperties: true
+
+...
diff --git a/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml b/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml
new file mode 100644
index 000000000000..43df15ba8fa4
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/fsl,flexcan.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title:
+  Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
+
+maintainers:
+  - Marc Kleine-Budde <mkl@pengutronix.de>
+
+allOf:
+  - $ref: can-controller.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - fsl,imx8qm-flexcan
+          - fsl,imx8mp-flexcan
+          - fsl,imx6q-flexcan
+          - fsl,imx53-flexcan
+          - fsl,imx35-flexcan
+          - fsl,imx28-flexcan
+          - fsl,imx25-flexcan
+          - fsl,p1010-flexcan
+          - fsl,vf610-flexcan
+          - fsl,ls1021ar2-flexcan
+          - fsl,lx2160ar1-flexcan
+      - items:
+          - enum:
+              - fsl,imx7d-flexcan
+              - fsl,imx6ul-flexcan
+              - fsl,imx6sx-flexcan
+          - const: fsl,imx6q-flexcan
+      - items:
+          - enum:
+              - fsl,ls1028ar1-flexcan
+          - const: fsl,lx2160ar1-flexcan
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: ipg
+      - const: per
+
+  clock-frequency:
+    description: |
+      The oscillator frequency driving the flexcan device, filled in by the
+      boot loader. This property should only be used the used operating system
+      doesn't support the clocks and clock-names property.
+
+  xceiver-supply:
+    description: Regulator that powers the CAN transceiver.
+
+  big-endian:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description: |
+      This means the registers of FlexCAN controller are big endian. This is
+      optional property.i.e. if this property is not present in device tree
+      node then controller is assumed to be little endian. If this property is
+      present then controller is assumed to be big endian.
+
+  fsl,stop-mode:
+    description: |
+      Register bits of stop mode control.
+
+      The format should be as follows:
+      <gpr req_gpr req_bit>
+      gpr is the phandle to general purpose register node.
+      req_gpr is the gpr register offset of CAN stop request.
+      req_bit is the bit offset of CAN stop request.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - description: The 'gpr' is the phandle to general purpose register node.
+      - description: The 'req_gpr' is the gpr register offset of CAN stop request.
+        maximum: 0xff
+      - description: The 'req_bit' is the bit offset of CAN stop request.
+        maximum: 0x1f
+
+  fsl,clk-source:
+    description: |
+      Select the clock source to the CAN Protocol Engine (PE). It's SoC
+      implementation dependent. Refer to RM for detailed definition. If this
+      property is not set in device tree node then driver selects clock source 1
+      by default.
+      0: clock source 0 (oscillator clock)
+      1: clock source 1 (peripheral clock)
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 1
+    minimum: 0
+    maximum: 1
+
+  wakeup-source:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Enable CAN remote wakeup.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    can@1c000 {
+        compatible = "fsl,p1010-flexcan";
+        reg = <0x1c000 0x1000>;
+        interrupts = <48 0x2>;
+        interrupt-parent = <&mpic>;
+        clock-frequency = <200000000>;
+        fsl,clk-source = <0>;
+    };
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    can@2090000 {
+        compatible = "fsl,imx6q-flexcan";
+        reg = <0x02090000 0x4000>;
+        interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clks 1>, <&clks 2>;
+        clock-names = "ipg", "per";
+        fsl,stop-mode = <&gpr 0x34 28>;
+    };
diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
deleted file mode 100644
index e10b6eb955e1..000000000000
--- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
-
-Required properties:
-
-- compatible : Should be "fsl,<processor>-flexcan"
-
-  where <processor> is imx8qm, imx6q, imx28, imx53, imx35, imx25, p1010,
-  vf610, ls1021ar2, lx2160ar1, ls1028ar1.
-
-  The ls1028ar1 must be followed by lx2160ar1, e.g.
-   - "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"
-
-  An implementation should also claim any of the following compatibles
-  that it is fully backwards compatible with:
-
-  - fsl,p1010-flexcan
-
-- reg : Offset and length of the register set for this device
-- interrupts : Interrupt tuple for this device
-
-Optional properties:
-
-- clock-frequency : The oscillator frequency driving the flexcan device
-
-- xceiver-supply: Regulator that powers the CAN transceiver
-
-- big-endian: This means the registers of FlexCAN controller are big endian.
-              This is optional property.i.e. if this property is not present in
-              device tree node then controller is assumed to be little endian.
-              if this property is present then controller is assumed to be big
-              endian.
-
-- fsl,stop-mode: register bits of stop mode control, the format is
-		 <&gpr req_gpr req_bit>.
-		 gpr is the phandle to general purpose register node.
-		 req_gpr is the gpr register offset of CAN stop request.
-		 req_bit is the bit offset of CAN stop request.
-
-- fsl,clk-source: Select the clock source to the CAN Protocol Engine (PE).
-		  It's SoC Implementation dependent. Refer to RM for detailed
-		  definition. If this property is not set in device tree node
-		  then driver selects clock source 1 by default.
-		  0: clock source 0 (oscillator clock)
-		  1: clock source 1 (peripheral clock)
-
-- wakeup-source: enable CAN remote wakeup
-
-Example:
-
-	can@1c000 {
-		compatible = "fsl,p1010-flexcan";
-		reg = <0x1c000 0x1000>;
-		interrupts = <48 0x2>;
-		interrupt-parent = <&mpic>;
-		clock-frequency = <200000000>; // filled in by bootloader
-		fsl,clk-source = <0>; // select clock source 0 for PE
-	};
diff --git a/Documentation/filesystems/api-summary.rst b/Documentation/filesystems/api-summary.rst
index bbb0c1c0e5cf..a94f17d9b836 100644
--- a/Documentation/filesystems/api-summary.rst
+++ b/Documentation/filesystems/api-summary.rst
@@ -86,9 +86,6 @@ Other Functions
 .. kernel-doc:: fs/dax.c
    :export:
 
-.. kernel-doc:: fs/direct-io.c
-   :export:
-
 .. kernel-doc:: fs/libfs.c
    :export:
 
diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 1f9ea8221f80..2062a6023678 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -83,10 +83,6 @@ AMDGPU XGMI Support
 ===================
 
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
-   :doc: AMDGPU XGMI Support
-
-.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
-   :internal:
 
 AMDGPU RAS Support
 ==================
@@ -124,9 +120,6 @@ RAS VRAM Bad Pages sysfs Interface
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
    :doc: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
 
-.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
-   :internal:
-
 Sample Code
 -----------
 Sample code for testing error injection can be found here:
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index cff1f154b473..20868f3d0123 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -118,6 +118,12 @@ Atomic Plane Helpers
 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
    :internal:
 
+Asynchronous Page Flip
+----------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c
+   :doc: asynchronous flip implementation
+
 Output Probing
 --------------
 
diff --git a/Documentation/hwmon/adm1266.rst b/Documentation/hwmon/adm1266.rst
index 9257f8a48650..2b877011cfdf 100644
--- a/Documentation/hwmon/adm1266.rst
+++ b/Documentation/hwmon/adm1266.rst
@@ -20,7 +20,7 @@ ADM1266 is a sequencer that features voltage readback from 17 channels via an
 integrated 12 bit SAR ADC, accessed using a PMBus interface.
 
 The driver is a client driver to the core PMBus driver. Please see
-Documentation/hwmon/pmbus for details on PMBus client drivers.
+Documentation/hwmon/pmbus.rst for details on PMBus client drivers.
 
 
 Sysfs entries
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index e6b91ab12978..b797db738225 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -132,6 +132,7 @@ Hardware Monitoring Kernel Drivers
    mcp3021
    menf21bmc
    mlxreg-fan
+   mp2975
    nct6683
    nct6775
    nct7802
diff --git a/Documentation/hwmon/mp2975.rst b/Documentation/hwmon/mp2975.rst
index 5b0609c62f48..81d816b71490 100644
--- a/Documentation/hwmon/mp2975.rst
+++ b/Documentation/hwmon/mp2975.rst
@@ -20,6 +20,7 @@ This driver implements support for Monolithic Power Systems, Inc. (MPS)
 vendor dual-loop, digital, multi-phase controller MP2975.
 
 This device:
+
 - Supports up to two power rail.
 - Provides 8 pulse-width modulations (PWMs), and can be configured up
   to 8-phase operation for rail 1 and up to 4-phase operation for rail
@@ -32,10 +33,12 @@ This device:
   10-mV DAC, IMVP9 mode with 5-mV DAC.
 
 Device supports:
+
 - SVID interface.
 - AVSBus interface.
 
 Device complaint with:
+
 - PMBus rev 1.3 interface.
 
 Device supports direct format for reading output current, output voltage,
@@ -45,11 +48,14 @@ Device supports VID and direct formats for reading output voltage.
 The below VID modes are supported: VR12, VR13, IMVP9.
 
 The driver provides the next attributes for the current:
+
 - for current in: input, maximum alarm;
 - for current out input, maximum alarm and highest values;
 - for phase current: input and label.
-attributes.
+  attributes.
+
 The driver exports the following attributes via the 'sysfs' files, where
+
 - 'n' is number of telemetry pages (from 1 to 2);
 - 'k' is number of configured phases (from 1 to 8);
 - indexes 1, 1*n for "iin";
@@ -65,11 +71,14 @@ The driver exports the following attributes via the 'sysfs' files, where
 **curr[1-{2n+k}]_label**
 
 The driver provides the next attributes for the voltage:
+
 - for voltage in: input, high critical threshold, high critical alarm, all only
   from page 0;
 - for voltage out: input, low and high critical thresholds, low and high
   critical alarms, from pages 0 and 1;
+
 The driver exports the following attributes via the 'sysfs' files, where
+
 - 'n' is number of telemetry pages (from 1 to 2);
 - indexes 1 for "iin";
 - indexes n+1, n+2 for "vout";
@@ -87,9 +96,12 @@ The driver exports the following attributes via the 'sysfs' files, where
 **in[2-{n+1}1_lcrit_alarm**
 
 The driver provides the next attributes for the power:
+
 - for power in alarm and input.
 - for power out: highest and input.
+
 The driver exports the following attributes via the 'sysfs' files, where
+
 - 'n' is number of telemetry pages (from 1 to 2);
 - indexes 1 for "pin";
 - indexes n+1, n+2 for "pout";
diff --git a/Documentation/leds/index.rst b/Documentation/leds/index.rst
index 53e6090454af..e5d63b940045 100644
--- a/Documentation/leds/index.rst
+++ b/Documentation/leds/index.rst
@@ -25,3 +25,4 @@ LEDs
    leds-lp5562
    leds-lp55xx
    leds-mlxcpld
+   leds-sc27xx
diff --git a/Documentation/locking/lockdep-design.rst b/Documentation/locking/lockdep-design.rst
index cec03bd1294a..9f3cfca9f8a4 100644
--- a/Documentation/locking/lockdep-design.rst
+++ b/Documentation/locking/lockdep-design.rst
@@ -42,6 +42,7 @@ The validator tracks lock-class usage history and divides the usage into
 (4 usages * n STATEs + 1) categories:
 
 where the 4 usages can be:
+
 - 'ever held in STATE context'
 - 'ever held as readlock in STATE context'
 - 'ever held with STATE enabled'
@@ -49,10 +50,12 @@ where the 4 usages can be:
 
 where the n STATEs are coded in kernel/locking/lockdep_states.h and as of
 now they include:
+
 - hardirq
 - softirq
 
 where the last 1 category is:
+
 - 'ever used'                                       [ == !unused        ]
 
 When locking rules are violated, these usage bits are presented in the
@@ -96,9 +99,9 @@ exact case is for the lock as of the reporting time.
   +--------------+-------------+--------------+
   |              | irq enabled | irq disabled |
   +--------------+-------------+--------------+
-  | ever in irq  |      ?      |       -      |
+  | ever in irq  |     '?'     |      '-'     |
   +--------------+-------------+--------------+
-  | never in irq |      +      |       .      |
+  | never in irq |     '+'     |      '.'     |
   +--------------+-------------+--------------+
 
 The character '-' suggests irq is disabled because if otherwise the
@@ -216,7 +219,7 @@ looks like this::
        BD_MUTEX_PARTITION
   };
 
-mutex_lock_nested(&bdev->bd_contains->bd_mutex, BD_MUTEX_PARTITION);
+  mutex_lock_nested(&bdev->bd_contains->bd_mutex, BD_MUTEX_PARTITION);
 
 In this case the locking is done on a bdev object that is known to be a
 partition.
@@ -334,7 +337,7 @@ Troubleshooting:
 ----------------
 
 The validator tracks a maximum of MAX_LOCKDEP_KEYS number of lock classes.
-Exceeding this number will trigger the following lockdep warning:
+Exceeding this number will trigger the following lockdep warning::
 
 	(DEBUG_LOCKS_WARN_ON(id >= MAX_LOCKDEP_KEYS))
 
@@ -420,7 +423,8 @@ the critical section of another reader of the same lock instance.
 
 The difference between recursive readers and non-recursive readers is because:
 recursive readers get blocked only by a write lock *holder*, while non-recursive
-readers could get blocked by a write lock *waiter*. Considering the follow example:
+readers could get blocked by a write lock *waiter*. Considering the follow
+example::
 
 	TASK A:			TASK B:
 
@@ -448,20 +452,22 @@ There are simply four block conditions:
 
 Block condition matrix, Y means the row blocks the column, and N means otherwise.
 
-	    | E | r | R |
 	+---+---+---+---+
-	  E | Y | Y | Y |
+	|   | E | r | R |
+	+---+---+---+---+
+	| E | Y | Y | Y |
+	+---+---+---+---+
+	| r | Y | Y | N |
 	+---+---+---+---+
-	  r | Y | Y | N |
+	| R | Y | Y | N |
 	+---+---+---+---+
-	  R | Y | Y | N |
 
 	(W: writers, r: non-recursive readers, R: recursive readers)
 
 
 acquired recursively. Unlike non-recursive read locks, recursive read locks
 only get blocked by current write lock *holders* other than write lock
-*waiters*, for example:
+*waiters*, for example::
 
 	TASK A:			TASK B:
 
@@ -491,7 +497,7 @@ Recursive locks don't block each other, while non-recursive locks do (this is
 even true for two non-recursive read locks). A non-recursive lock can block the
 corresponding recursive lock, and vice versa.
 
-A deadlock case with recursive locks involved is as follow:
+A deadlock case with recursive locks involved is as follow::
 
 	TASK A:			TASK B:
 
@@ -510,7 +516,7 @@ because there are 3 types for lockers, there are, in theory, 9 types of lock
 dependencies, but we can show that 4 types of lock dependencies are enough for
 deadlock detection.
 
-For each lock dependency:
+For each lock dependency::
 
 	L1 -> L2
 
@@ -525,20 +531,25 @@ same types).
 With the above combination for simplification, there are 4 types of dependency edges
 in the lockdep graph:
 
-1) -(ER)->: exclusive writer to recursive reader dependency, "X -(ER)-> Y" means
+1) -(ER)->:
+	    exclusive writer to recursive reader dependency, "X -(ER)-> Y" means
 	    X -> Y and X is a writer and Y is a recursive reader.
 
-2) -(EN)->: exclusive writer to non-recursive locker dependency, "X -(EN)-> Y" means
+2) -(EN)->:
+	    exclusive writer to non-recursive locker dependency, "X -(EN)-> Y" means
 	    X -> Y and X is a writer and Y is either a writer or non-recursive reader.
 
-3) -(SR)->: shared reader to recursive reader dependency, "X -(SR)-> Y" means
+3) -(SR)->:
+	    shared reader to recursive reader dependency, "X -(SR)-> Y" means
 	    X -> Y and X is a reader (recursive or not) and Y is a recursive reader.
 
-4) -(SN)->: shared reader to non-recursive locker dependency, "X -(SN)-> Y" means
+4) -(SN)->:
+	    shared reader to non-recursive locker dependency, "X -(SN)-> Y" means
 	    X -> Y and X is a reader (recursive or not) and Y is either a writer or
 	    non-recursive reader.
 
-Note that given two locks, they may have multiple dependencies between them, for example:
+Note that given two locks, they may have multiple dependencies between them,
+for example::
 
 	TASK A:
 
@@ -592,11 +603,11 @@ circles that won't cause deadlocks.
 
 Proof for sufficiency (Lemma 1):
 
-Let's say we have a strong circle:
+Let's say we have a strong circle::
 
 	L1 -> L2 ... -> Ln -> L1
 
-, which means we have dependencies:
+, which means we have dependencies::
 
 	L1 -> L2
 	L2 -> L3
@@ -633,7 +644,7 @@ a lock held by P2, and P2 is waiting for a lock held by P3, ... and Pn is waitin
 for a lock held by P1. Let's name the lock Px is waiting as Lx, so since P1 is waiting
 for L1 and holding Ln, so we will have Ln -> L1 in the dependency graph. Similarly,
 we have L1 -> L2, L2 -> L3, ..., Ln-1 -> Ln in the dependency graph, which means we
-have a circle:
+have a circle::
 
 	Ln -> L1 -> L2 -> ... -> Ln
 
diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst
index 46072ce3d7ef..64420b3314fe 100644
--- a/Documentation/misc-devices/index.rst
+++ b/Documentation/misc-devices/index.rst
@@ -24,7 +24,6 @@ fit into other categories.
    isl29003
    lis3lv02d
    max6875
-   mic/index
    pci-endpoint-test
    spear-pcie-gadget
    uacce
diff --git a/Documentation/networking/devlink/ice.rst b/Documentation/networking/devlink/ice.rst
index b165181d5d4d..a432dc419fa4 100644
--- a/Documentation/networking/devlink/ice.rst
+++ b/Documentation/networking/devlink/ice.rst
@@ -70,6 +70,7 @@ The ``ice`` driver reports the following versions
         that both the name (as reported by ``fw.app.name``) and version are
         required to uniquely identify the package.
     * - ``fw.app.bundle_id``
+      - running
       - 0xc0000001
       - Unique identifier for the DDP package loaded in the device. Also
         referred to as the DDP Track ID. Can be used to uniquely identify
diff --git a/Documentation/networking/j1939.rst b/Documentation/networking/j1939.rst
index f5be243d250a..0a4b73b03b99 100644
--- a/Documentation/networking/j1939.rst
+++ b/Documentation/networking/j1939.rst
@@ -10,9 +10,9 @@ Overview / What Is J1939
 SAE J1939 defines a higher layer protocol on CAN. It implements a more
 sophisticated addressing scheme and extends the maximum packet size above 8
 bytes. Several derived specifications exist, which differ from the original
-J1939 on the application level, like MilCAN A, NMEA2000 and especially
+J1939 on the application level, like MilCAN A, NMEA2000, and especially
 ISO-11783 (ISOBUS). This last one specifies the so-called ETP (Extended
-Transport Protocol) which is has been included in this implementation. This
+Transport Protocol), which has been included in this implementation. This
 results in a maximum packet size of ((2 ^ 24) - 1) * 7 bytes == 111 MiB.
 
 Specifications used
@@ -32,15 +32,15 @@ sockets, we found some reasons to justify a kernel implementation for the
 addressing and transport methods used by J1939.
 
 * **Addressing:** when a process on an ECU communicates via J1939, it should
-  not necessarily know its source address. Although at least one process per
+  not necessarily know its source address. Although, at least one process per
   ECU should know the source address. Other processes should be able to reuse
   that address. This way, address parameters for different processes
   cooperating for the same ECU, are not duplicated. This way of working is
-  closely related to the UNIX concept where programs do just one thing, and do
+  closely related to the UNIX concept, where programs do just one thing and do
   it well.
 
 * **Dynamic addressing:** Address Claiming in J1939 is time critical.
-  Furthermore data transport should be handled properly during the address
+  Furthermore, data transport should be handled properly during the address
   negotiation. Putting this functionality in the kernel eliminates it as a
   requirement for _every_ user space process that communicates via J1939. This
   results in a consistent J1939 bus with proper addressing.
@@ -58,7 +58,7 @@ Therefore, these parts are left to user space.
 
 The J1939 sockets operate on CAN network devices (see SocketCAN). Any J1939
 user space library operating on CAN raw sockets will still operate properly.
-Since such library does not communicate with the in-kernel implementation, care
+Since such a library does not communicate with the in-kernel implementation, care
 must be taken that these two do not interfere. In practice, this means they
 cannot share ECU addresses. A single ECU (or virtual ECU) address is used by
 the library exclusively, or by the in-kernel system exclusively.
@@ -77,13 +77,13 @@ is composed as follows:
 8 bits : PS (PDU Specific)
 
 In J1939-21 distinction is made between PDU1 format (where PF < 240) and PDU2
-format (where PF >= 240). Furthermore, when using PDU2 format, the PS-field
+format (where PF >= 240). Furthermore, when using the PDU2 format, the PS-field
 contains a so-called Group Extension, which is part of the PGN. When using PDU2
 format, the Group Extension is set in the PS-field.
 
 On the other hand, when using PDU1 format, the PS-field contains a so-called
 Destination Address, which is _not_ part of the PGN. When communicating a PGN
-from user space to kernel (or visa versa) and PDU2 format is used, the PS-field
+from user space to kernel (or vice versa) and PDU2 format is used, the PS-field
 of the PGN shall be set to zero. The Destination Address shall be set
 elsewhere.
 
@@ -96,15 +96,15 @@ Addressing
 
 Both static and dynamic addressing methods can be used.
 
-For static addresses, no extra checks are made by the kernel, and provided
+For static addresses, no extra checks are made by the kernel and provided
 addresses are considered right. This responsibility is for the OEM or system
 integrator.
 
 For dynamic addressing, so-called Address Claiming, extra support is foreseen
-in the kernel. In J1939 any ECU is known by it's 64-bit NAME. At the moment of
+in the kernel. In J1939 any ECU is known by its 64-bit NAME. At the moment of
 a successful address claim, the kernel keeps track of both NAME and source
 address being claimed. This serves as a base for filter schemes. By default,
-packets with a destination that is not locally, will be rejected.
+packets with a destination that is not locally will be rejected.
 
 Mixed mode packets (from a static to a dynamic address or vice versa) are
 allowed. The BSD sockets define separate API calls for getting/setting the
@@ -131,31 +131,31 @@ API Calls
 ---------
 
 On CAN, you first need to open a socket for communicating over a CAN network.
-To use J1939, #include <linux/can/j1939.h>. From there, <linux/can.h> will be
+To use J1939, ``#include <linux/can/j1939.h>``. From there, ``<linux/can.h>`` will be
 included too. To open a socket, use:
 
 .. code-block:: C
 
     s = socket(PF_CAN, SOCK_DGRAM, CAN_J1939);
 
-J1939 does use SOCK_DGRAM sockets. In the J1939 specification, connections are
+J1939 does use ``SOCK_DGRAM`` sockets. In the J1939 specification, connections are
 mentioned in the context of transport protocol sessions. These still deliver
-packets to the other end (using several CAN packets). SOCK_STREAM is not
+packets to the other end (using several CAN packets). ``SOCK_STREAM`` is not
 supported.
 
-After the successful creation of the socket, you would normally use the bind(2)
-and/or connect(2) system call to bind the socket to a CAN interface.  After
-binding and/or connecting the socket, you can read(2) and write(2) from/to the
-socket or use send(2), sendto(2), sendmsg(2) and the recv*() counterpart
+After the successful creation of the socket, you would normally use the ``bind(2)``
+and/or ``connect(2)`` system call to bind the socket to a CAN interface. After
+binding and/or connecting the socket, you can ``read(2)`` and ``write(2)`` from/to the
+socket or use ``send(2)``, ``sendto(2)``, ``sendmsg(2)`` and the ``recv*()`` counterpart
 operations on the socket as usual. There are also J1939 specific socket options
 described below.
 
-In order to send data, a bind(2) must have been successful. bind(2) assigns a
+In order to send data, a ``bind(2)`` must have been successful. ``bind(2)`` assigns a
 local address to a socket.
 
-Different from CAN is that the payload data is just the data that get send,
-without it's header info. The header info is derived from the sockaddr supplied
-to bind(2), connect(2), sendto(2) and recvfrom(2). A write(2) with size 4 will
+Different from CAN is that the payload data is just the data that get sends,
+without its header info. The header info is derived from the sockaddr supplied
+to ``bind(2)``, ``connect(2)``, ``sendto(2)`` and ``recvfrom(2)``. A ``write(2)`` with size 4 will
 result in a packet with 4 bytes.
 
 The sockaddr structure has extensions for use with J1939 as specified below:
@@ -180,47 +180,47 @@ The sockaddr structure has extensions for use with J1939 as specified below:
          } can_addr;
       }
 
-can_family & can_ifindex serve the same purpose as for other SocketCAN sockets.
+``can_family`` & ``can_ifindex`` serve the same purpose as for other SocketCAN sockets.
 
-can_addr.j1939.pgn specifies the PGN (max 0x3ffff). Individual bits are
+``can_addr.j1939.pgn`` specifies the PGN (max 0x3ffff). Individual bits are
 specified above.
 
-can_addr.j1939.name contains the 64-bit J1939 NAME.
+``can_addr.j1939.name`` contains the 64-bit J1939 NAME.
 
-can_addr.j1939.addr contains the address.
+``can_addr.j1939.addr`` contains the address.
 
-The bind(2) system call assigns the local address, i.e. the source address when
-sending packages. If a PGN during bind(2) is set, it's used as a RX filter.
-I.e.  only packets with a matching PGN are received. If an ADDR or NAME is set
+The ``bind(2)`` system call assigns the local address, i.e. the source address when
+sending packages. If a PGN during ``bind(2)`` is set, it's used as a RX filter.
+I.e. only packets with a matching PGN are received. If an ADDR or NAME is set
 it is used as a receive filter, too. It will match the destination NAME or ADDR
 of the incoming packet. The NAME filter will work only if appropriate Address
 Claiming for this name was done on the CAN bus and registered/cached by the
 kernel.
 
-On the other hand connect(2) assigns the remote address, i.e. the destination
-address. The PGN from connect(2) is used as the default PGN when sending
+On the other hand ``connect(2)`` assigns the remote address, i.e. the destination
+address. The PGN from ``connect(2)`` is used as the default PGN when sending
 packets. If ADDR or NAME is set it will be used as the default destination ADDR
-or NAME. Further a set ADDR or NAME during connect(2) is used as a receive
+or NAME. Further a set ADDR or NAME during ``connect(2)`` is used as a receive
 filter. It will match the source NAME or ADDR of the incoming packet.
 
-Both write(2) and send(2) will send a packet with local address from bind(2) and
-the remote address from connect(2). Use sendto(2) to overwrite the destination
+Both ``write(2)`` and ``send(2)`` will send a packet with local address from ``bind(2)`` and the
+remote address from ``connect(2)``. Use ``sendto(2)`` to overwrite the destination
 address.
 
-If can_addr.j1939.name is set (!= 0) the NAME is looked up by the kernel and
-the corresponding ADDR is used. If can_addr.j1939.name is not set (== 0),
-can_addr.j1939.addr is used.
+If ``can_addr.j1939.name`` is set (!= 0) the NAME is looked up by the kernel and
+the corresponding ADDR is used. If ``can_addr.j1939.name`` is not set (== 0),
+``can_addr.j1939.addr`` is used.
 
 When creating a socket, reasonable defaults are set. Some options can be
-modified with setsockopt(2) & getsockopt(2).
+modified with ``setsockopt(2)`` & ``getsockopt(2)``.
 
 RX path related options:
 
-- SO_J1939_FILTER - configure array of filters
-- SO_J1939_PROMISC - disable filters set by bind(2) and connect(2)
+- ``SO_J1939_FILTER`` - configure array of filters
+- ``SO_J1939_PROMISC`` - disable filters set by ``bind(2)`` and ``connect(2)``
 
 By default no broadcast packets can be send or received. To enable sending or
-receiving broadcast packets use the socket option SO_BROADCAST:
+receiving broadcast packets use the socket option ``SO_BROADCAST``:
 
 .. code-block:: C
 
@@ -261,26 +261,26 @@ The following diagram illustrates the RX path:
      +---------------------------+
 
 TX path related options:
-SO_J1939_SEND_PRIO - change default send priority for the socket
+``SO_J1939_SEND_PRIO`` - change default send priority for the socket
 
 Message Flags during send() and Related System Calls
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-send(2), sendto(2) and sendmsg(2) take a 'flags' argument. Currently
+``send(2)``, ``sendto(2)`` and ``sendmsg(2)`` take a 'flags' argument. Currently
 supported flags are:
 
-* MSG_DONTWAIT, i.e. non-blocking operation.
+* ``MSG_DONTWAIT``, i.e. non-blocking operation.
 
 recvmsg(2)
 ^^^^^^^^^^
 
-In most cases recvmsg(2) is needed if you want to extract more information than
-recvfrom(2) can provide. For example package priority and timestamp. The
+In most cases ``recvmsg(2)`` is needed if you want to extract more information than
+``recvfrom(2)`` can provide. For example package priority and timestamp. The
 Destination Address, name and packet priority (if applicable) are attached to
-the msghdr in the recvmsg(2) call. They can be extracted using cmsg(3) macros,
-with cmsg_level == SOL_J1939 && cmsg_type == SCM_J1939_DEST_ADDR,
-SCM_J1939_DEST_NAME or SCM_J1939_PRIO. The returned data is a uint8_t for
-priority and dst_addr, and uint64_t for dst_name.
+the msghdr in the ``recvmsg(2)`` call. They can be extracted using ``cmsg(3)`` macros,
+with ``cmsg_level == SOL_J1939 && cmsg_type == SCM_J1939_DEST_ADDR``,
+``SCM_J1939_DEST_NAME`` or ``SCM_J1939_PRIO``. The returned data is a ``uint8_t`` for
+``priority`` and ``dst_addr``, and ``uint64_t`` for ``dst_name``.
 
 .. code-block:: C
 
@@ -305,12 +305,12 @@ Dynamic Addressing
 
 Distinction has to be made between using the claimed address and doing an
 address claim. To use an already claimed address, one has to fill in the
-j1939.name member and provide it to bind(2). If the name had claimed an address
+``j1939.name`` member and provide it to ``bind(2)``. If the name had claimed an address
 earlier, all further messages being sent will use that address. And the
-j1939.addr member will be ignored.
+``j1939.addr`` member will be ignored.
 
 An exception on this is PGN 0x0ee00. This is the "Address Claim/Cannot Claim
-Address" message and the kernel will use the j1939.addr member for that PGN if
+Address" message and the kernel will use the ``j1939.addr`` member for that PGN if
 necessary.
 
 To claim an address following code example can be used:
@@ -371,12 +371,12 @@ NAME can send packets.
 
 If another ECU claims the address, the kernel will mark the NAME-SA expired.
 No socket bound to the NAME can send packets (other than address claims). To
-claim another address, some socket bound to NAME, must bind(2) again, but with
-only j1939.addr changed to the new SA, and must then send a valid address claim
+claim another address, some socket bound to NAME, must ``bind(2)`` again, but with
+only ``j1939.addr`` changed to the new SA, and must then send a valid address claim
 packet. This restarts the state machine in the kernel (and any other
 participant on the bus) for this NAME.
 
-can-utils also include the jacd tool, so it can be used as code example or as
+``can-utils`` also include the ``j1939acd`` tool, so it can be used as code example or as
 default Address Claiming daemon.
 
 Send Examples
@@ -403,8 +403,8 @@ Bind:
 
 	bind(sock, (struct sockaddr *)&baddr, sizeof(baddr));
 
-Now, the socket 'sock' is bound to the SA 0x20. Since no connect(2) was called,
-at this point we can use only sendto(2) or sendmsg(2).
+Now, the socket 'sock' is bound to the SA 0x20. Since no ``connect(2)`` was called,
+at this point we can use only ``sendto(2)`` or ``sendmsg(2)``.
 
 Send:
 
@@ -414,8 +414,8 @@ Send:
 		.can_family = AF_CAN,
 		.can_addr.j1939 = {
 			.name = J1939_NO_NAME;
-			.pgn = 0x30,
-			.addr = 0x12300,
+			.addr = 0x30,
+			.pgn = 0x12300,
 		},
 	};
 
diff --git a/Documentation/networking/statistics.rst b/Documentation/networking/statistics.rst
index 8e15bc98830b..234abedc29b2 100644
--- a/Documentation/networking/statistics.rst
+++ b/Documentation/networking/statistics.rst
@@ -175,5 +175,4 @@ The following structures are internal to the kernel, their members are
 translated to netlink attributes when dumped. Drivers must not overwrite
 the statistics they don't report with 0.
 
-.. kernel-doc:: include/linux/ethtool.h
-    :identifiers: ethtool_pause_stats
+- ethtool_pause_stats()
diff --git a/Documentation/sphinx/automarkup.py b/Documentation/sphinx/automarkup.py
index 409dbc4100de..3e81ebab26ed 100644
--- a/Documentation/sphinx/automarkup.py
+++ b/Documentation/sphinx/automarkup.py
@@ -16,28 +16,36 @@ import re
 from itertools import chain
 
 #
+# Python 2 lacks re.ASCII...
+#
+try:
+    ascii_p3 = re.ASCII
+except AttributeError:
+    ascii_p3 = 0
+
+#
 # Regex nastiness.  Of course.
 # Try to identify "function()" that's not already marked up some
 # other way.  Sphinx doesn't like a lot of stuff right after a
 # :c:func: block (i.e. ":c:func:`mmap()`s" flakes out), so the last
 # bit tries to restrict matches to things that won't create trouble.
 #
-RE_function = re.compile(r'\b(([a-zA-Z_]\w+)\(\))', flags=re.ASCII)
+RE_function = re.compile(r'\b(([a-zA-Z_]\w+)\(\))', flags=ascii_p3)
 
 #
 # Sphinx 2 uses the same :c:type role for struct, union, enum and typedef
 #
 RE_generic_type = re.compile(r'\b(struct|union|enum|typedef)\s+([a-zA-Z_]\w+)',
-                             flags=re.ASCII)
+                             flags=ascii_p3)
 
 #
 # Sphinx 3 uses a different C role for each one of struct, union, enum and
 # typedef
 #
-RE_struct = re.compile(r'\b(struct)\s+([a-zA-Z_]\w+)', flags=re.ASCII)
-RE_union = re.compile(r'\b(union)\s+([a-zA-Z_]\w+)', flags=re.ASCII)
-RE_enum = re.compile(r'\b(enum)\s+([a-zA-Z_]\w+)', flags=re.ASCII)
-RE_typedef = re.compile(r'\b(typedef)\s+([a-zA-Z_]\w+)', flags=re.ASCII)
+RE_struct = re.compile(r'\b(struct)\s+([a-zA-Z_]\w+)', flags=ascii_p3)
+RE_union = re.compile(r'\b(union)\s+([a-zA-Z_]\w+)', flags=ascii_p3)
+RE_enum = re.compile(r'\b(enum)\s+([a-zA-Z_]\w+)', flags=ascii_p3)
+RE_typedef = re.compile(r'\b(typedef)\s+([a-zA-Z_]\w+)', flags=ascii_p3)
 
 #
 # Detects a reference to a documentation page of the form Documentation/... with
diff --git a/Documentation/userspace-api/index.rst b/Documentation/userspace-api/index.rst
index 69fc5167e648..acd2cc2a538d 100644
--- a/Documentation/userspace-api/index.rst
+++ b/Documentation/userspace-api/index.rst
@@ -22,6 +22,7 @@ place where this information is gathered.
    spec_ctrl
    accelerators/ocxl
    ioctl/index
+   iommu
    media/index
 
 .. only::  subproject and html
diff --git a/MAINTAINERS b/MAINTAINERS
index c82ea765df88..970d9cee509d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -934,7 +934,7 @@ M:	Evan Quan <evan.quan@amd.com>
 L:	amd-gfx@lists.freedesktop.org
 S:	Supported
 T:	git git://people.freedesktop.org/~agd5f/linux
-F:	drivers/gpu/drm/amd/powerplay/
+F:	drivers/gpu/drm/amd/pm/powerplay/
 
 AMD SEATTLE DEVICE TREE SUPPORT
 M:	Brijesh Singh <brijeshkumar.singh@amd.com>
@@ -978,7 +978,7 @@ M:	Michael Hennerich <Michael.Hennerich@analog.com>
 L:	linux-iio@vger.kernel.org
 S:	Supported
 W:	http://ez.analog.com/community/linux-device-drivers
-F:	Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.txt
+F:	Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
 F:	drivers/iio/adc/ad7768-1.c
 
 ANALOG DEVICES INC AD7780 DRIVER
@@ -3857,7 +3857,7 @@ M:	Roger Quadros <rogerq@ti.com>
 L:	linux-usb@vger.kernel.org
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/usb.git
-F:	Documentation/devicetree/bindings/usb/cdns-usb3.txt
+F:	Documentation/devicetree/bindings/usb/cdns,usb3.yaml
 F:	drivers/usb/cdns3/
 
 CADET FM/AM RADIO RECEIVER DRIVER
@@ -7923,7 +7923,7 @@ HISILICON LPC BUS DRIVER
 M:	john.garry@huawei.com
 S:	Maintained
 W:	http://www.hisilicon.com
-F:	Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt
+F:	Documentation/devicetree/bindings/arm/hisilicon/low-pin-count.yaml
 F:	drivers/bus/hisi_lpc.c
 
 HISILICON NETWORK SUBSYSTEM 3 DRIVER (HNS3)
@@ -11177,7 +11177,7 @@ F:	Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt
 F:	drivers/input/touchscreen/melfas_mip4.c
 
 MELLANOX BLUEFIELD I2C DRIVER
-M:	Khalil Blaiech <kblaiech@mellanox.com>
+M:	Khalil Blaiech <kblaiech@nvidia.com>
 L:	linux-i2c@vger.kernel.org
 S:	Supported
 F:	drivers/i2c/busses/i2c-mlxbf.c
@@ -14541,6 +14541,14 @@ F:	Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
 F:	drivers/mailbox/qcom-ipcc.c
 F:	include/dt-bindings/mailbox/qcom-ipcc.h
 
+QUALCOMM IPQ4019 VQMMC REGULATOR DRIVER
+M:	Robert Marko <robert.marko@sartura.hr>
+M:	Luka Perkov <luka.perkov@sartura.hr>
+L:	linux-arm-msm@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/regulator/vqmmc-ipq4019-regulator.yaml
+F:	drivers/regulator/vqmmc-ipq4019-regulator.c
+
 QUALCOMM RMNET DRIVER
 M:	Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
 M:	Sean Tranchetti <stranche@codeaurora.org>
@@ -14896,7 +14904,6 @@ RENESAS ETHERNET DRIVERS
 R:	Sergei Shtylyov <sergei.shtylyov@gmail.com>
 L:	netdev@vger.kernel.org
 L:	linux-renesas-soc@vger.kernel.org
-F:	Documentation/devicetree/bindings/net/renesas,*.txt
 F:	Documentation/devicetree/bindings/net/renesas,*.yaml
 F:	drivers/net/ethernet/renesas/
 F:	include/linux/sh_eth.h
@@ -18097,7 +18104,7 @@ M:	Yu Chen <chenyu56@huawei.com>
 M:	Binghui Wang <wangbinghui@hisilicon.com>
 L:	linux-usb@vger.kernel.org
 S:	Maintained
-F:	Documentation/devicetree/bindings/phy/phy-hi3660-usb3.txt
+F:	Documentation/devicetree/bindings/phy/hisilicon,hi3660-usb3.yaml
 F:	drivers/phy/hisilicon/phy-hi3660-usb3.c
 
 USB ISP116X DRIVER
diff --git a/Makefile b/Makefile
index 9e7fd6a065a7..008aba5f1a20 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
 VERSION = 5
 PATCHLEVEL = 10
 SUBLEVEL = 0
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 NAME = Kleptomaniac Octopus
 
 # *DOCUMENTATION*
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 17fd1ed700cc..9152782444b5 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -67,7 +67,22 @@
 	sr	r5, [ARC_REG_LPB_CTRL]
 1:
 #endif /* CONFIG_ARC_LPB_DISABLE */
-#endif
+
+	/* On HSDK, CCMs need to remapped super early */
+#ifdef CONFIG_ARC_SOC_HSDK
+	mov	r6, 0x60000000
+	lr	r5, [ARC_REG_ICCM_BUILD]
+	breq	r5, 0, 1f
+	sr	r6, [ARC_REG_AUX_ICCM]
+1:
+	lr	r5, [ARC_REG_DCCM_BUILD]
+	breq	r5, 0, 2f
+	sr	r6, [ARC_REG_AUX_DCCM]
+2:
+#endif	/* CONFIG_ARC_SOC_HSDK */
+
+#endif	/* CONFIG_ISA_ARCV2 */
+
 	; Config DSP_CTRL properly, so kernel may use integer multiply,
 	; multiply-accumulate, and divide operations
 	DSP_EARLY_INIT
diff --git a/arch/arc/kernel/stacktrace.c b/arch/arc/kernel/stacktrace.c
index feba91c9d969..b23986f98450 100644
--- a/arch/arc/kernel/stacktrace.c
+++ b/arch/arc/kernel/stacktrace.c
@@ -112,7 +112,7 @@ arc_unwind_core(struct task_struct *tsk, struct pt_regs *regs,
 		int (*consumer_fn) (unsigned int, void *), void *arg)
 {
 #ifdef CONFIG_ARC_DW2_UNWIND
-	int ret = 0;
+	int ret = 0, cnt = 0;
 	unsigned int address;
 	struct unwind_frame_info frame_info;
 
@@ -132,6 +132,11 @@ arc_unwind_core(struct task_struct *tsk, struct pt_regs *regs,
 			break;
 
 		frame_info.regs.r63 = frame_info.regs.r31;
+
+		if (cnt++ > 128) {
+			printk("unwinder looping too long, aborting !\n");
+			return 0;
+		}
 	}
 
 	return address;		/* return the last address it saw */
diff --git a/arch/arc/plat-hsdk/platform.c b/arch/arc/plat-hsdk/platform.c
index 0b63fc095b99..b3ea1fa11f87 100644
--- a/arch/arc/plat-hsdk/platform.c
+++ b/arch/arc/plat-hsdk/platform.c
@@ -17,22 +17,6 @@ int arc_hsdk_axi_dmac_coherent __section(".data") = 0;
 
 #define ARC_CCM_UNUSED_ADDR	0x60000000
 
-static void __init hsdk_init_per_cpu(unsigned int cpu)
-{
-	/*
-	 * By default ICCM is mapped to 0x7z while this area is used for
-	 * kernel virtual mappings, so move it to currently unused area.
-	 */
-	if (cpuinfo_arc700[cpu].iccm.sz)
-		write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR);
-
-	/*
-	 * By default DCCM is mapped to 0x8z while this area is used by kernel,
-	 * so move it to currently unused area.
-	 */
-	if (cpuinfo_arc700[cpu].dccm.sz)
-		write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR);
-}
 
 #define ARC_PERIPHERAL_BASE	0xf0000000
 #define CREG_BASE		(ARC_PERIPHERAL_BASE + 0x1000)
@@ -339,5 +323,4 @@ static const char *hsdk_compat[] __initconst = {
 MACHINE_START(SIMULATION, "hsdk")
 	.dt_compat	= hsdk_compat,
 	.init_early     = hsdk_init_early,
-	.init_per_cpu	= hsdk_init_per_cpu,
 MACHINE_END
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index d57112a276f5..c23dbf8bebee 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -354,8 +354,8 @@ static void __init free_highpages(void)
 	/* set highmem page free */
 	for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE,
 				&range_start, &range_end, NULL) {
-		unsigned long start = PHYS_PFN(range_start);
-		unsigned long end = PHYS_PFN(range_end);
+		unsigned long start = PFN_UP(range_start);
+		unsigned long end = PFN_DOWN(range_end);
 
 		/* Ignore complete lowmem entries */
 		if (end <= max_low)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1d466addb078..1515f6f153a0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1002,7 +1002,7 @@ config NUMA
 config NODES_SHIFT
 	int "Maximum NUMA Nodes (as a power of 2)"
 	range 1 10
-	default "2"
+	default "4"
 	depends on NEED_MULTIPLE_NODES
 	help
 	  Specify the maximum number of NUMA Nodes available on the target
diff --git a/arch/arm64/include/asm/brk-imm.h b/arch/arm64/include/asm/brk-imm.h
index e3d47b52161d..ec7720dbe2c8 100644
--- a/arch/arm64/include/asm/brk-imm.h
+++ b/arch/arm64/include/asm/brk-imm.h
@@ -10,6 +10,7 @@
  * #imm16 values used for BRK instruction generation
  * 0x004: for installing kprobes
  * 0x005: for installing uprobes
+ * 0x006: for kprobe software single-step
  * Allowed values for kgdb are 0x400 - 0x7ff
  * 0x100: for triggering a fault on purpose (reserved)
  * 0x400: for dynamic BRK instruction
@@ -19,6 +20,7 @@
  */
 #define KPROBES_BRK_IMM			0x004
 #define UPROBES_BRK_IMM			0x005
+#define KPROBES_BRK_SS_IMM		0x006
 #define FAULT_BRK_IMM			0x100
 #define KGDB_DYN_DBG_BRK_IMM		0x400
 #define KGDB_COMPILED_DBG_BRK_IMM	0x401
diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h
index 0b298f48f5bf..657c921fd784 100644
--- a/arch/arm64/include/asm/debug-monitors.h
+++ b/arch/arm64/include/asm/debug-monitors.h
@@ -53,6 +53,7 @@
 
 /* kprobes BRK opcodes with ESR encoding  */
 #define BRK64_OPCODE_KPROBES	(AARCH64_BREAK_MON | (KPROBES_BRK_IMM << 5))
+#define BRK64_OPCODE_KPROBES_SS	(AARCH64_BREAK_MON | (KPROBES_BRK_SS_IMM << 5))
 /* uprobes BRK opcodes with ESR encoding  */
 #define BRK64_OPCODE_UPROBES	(AARCH64_BREAK_MON | (UPROBES_BRK_IMM << 5))
 
diff --git a/arch/arm64/include/asm/kprobes.h b/arch/arm64/include/asm/kprobes.h
index 97e511d645a2..8699ce30f587 100644
--- a/arch/arm64/include/asm/kprobes.h
+++ b/arch/arm64/include/asm/kprobes.h
@@ -16,7 +16,7 @@
 #include <linux/percpu.h>
 
 #define __ARCH_WANT_KPROBES_INSN_SLOT
-#define MAX_INSN_SIZE			1
+#define MAX_INSN_SIZE			2
 
 #define flush_insn_slot(p)		do { } while (0)
 #define kretprobe_blacklist_size	0
diff --git a/arch/arm64/kernel/kexec_image.c b/arch/arm64/kernel/kexec_image.c
index af9987c154ca..66adee8b5fc8 100644
--- a/arch/arm64/kernel/kexec_image.c
+++ b/arch/arm64/kernel/kexec_image.c
@@ -43,7 +43,7 @@ static void *image_load(struct kimage *image,
 	u64 flags, value;
 	bool be_image, be_kernel;
 	struct kexec_buf kbuf;
-	unsigned long text_offset;
+	unsigned long text_offset, kernel_segment_number;
 	struct kexec_segment *kernel_segment;
 	int ret;
 
@@ -88,11 +88,37 @@ static void *image_load(struct kimage *image,
 	/* Adjust kernel segment with TEXT_OFFSET */
 	kbuf.memsz += text_offset;
 
-	ret = kexec_add_buffer(&kbuf);
-	if (ret)
+	kernel_segment_number = image->nr_segments;
+
+	/*
+	 * The location of the kernel segment may make it impossible to satisfy
+	 * the other segment requirements, so we try repeatedly to find a
+	 * location that will work.
+	 */
+	while ((ret = kexec_add_buffer(&kbuf)) == 0) {
+		/* Try to load additional data */
+		kernel_segment = &image->segment[kernel_segment_number];
+		ret = load_other_segments(image, kernel_segment->mem,
+					  kernel_segment->memsz, initrd,
+					  initrd_len, cmdline);
+		if (!ret)
+			break;
+
+		/*
+		 * We couldn't find space for the other segments; erase the
+		 * kernel segment and try the next available hole.
+		 */
+		image->nr_segments -= 1;
+		kbuf.buf_min = kernel_segment->mem + kernel_segment->memsz;
+		kbuf.mem = KEXEC_BUF_MEM_UNKNOWN;
+	}
+
+	if (ret) {
+		pr_err("Could not find any suitable kernel location!");
 		return ERR_PTR(ret);
+	}
 
-	kernel_segment = &image->segment[image->nr_segments - 1];
+	kernel_segment = &image->segment[kernel_segment_number];
 	kernel_segment->mem += text_offset;
 	kernel_segment->memsz -= text_offset;
 	image->start = kernel_segment->mem;
@@ -101,12 +127,7 @@ static void *image_load(struct kimage *image,
 				kernel_segment->mem, kbuf.bufsz,
 				kernel_segment->memsz);
 
-	/* Load additional data */
-	ret = load_other_segments(image,
-				kernel_segment->mem, kernel_segment->memsz,
-				initrd, initrd_len, cmdline);
-
-	return ERR_PTR(ret);
+	return 0;
 }
 
 #ifdef CONFIG_KEXEC_IMAGE_VERIFY_SIG
diff --git a/arch/arm64/kernel/machine_kexec_file.c b/arch/arm64/kernel/machine_kexec_file.c
index 5b0e67b93cdc..03210f644790 100644
--- a/arch/arm64/kernel/machine_kexec_file.c
+++ b/arch/arm64/kernel/machine_kexec_file.c
@@ -240,6 +240,11 @@ static int prepare_elf_headers(void **addr, unsigned long *sz)
 	return ret;
 }
 
+/*
+ * Tries to add the initrd and DTB to the image. If it is not possible to find
+ * valid locations, this function will undo changes to the image and return non
+ * zero.
+ */
 int load_other_segments(struct kimage *image,
 			unsigned long kernel_load_addr,
 			unsigned long kernel_size,
@@ -248,7 +253,8 @@ int load_other_segments(struct kimage *image,
 {
 	struct kexec_buf kbuf;
 	void *headers, *dtb = NULL;
-	unsigned long headers_sz, initrd_load_addr = 0, dtb_len;
+	unsigned long headers_sz, initrd_load_addr = 0, dtb_len,
+		      orig_segments = image->nr_segments;
 	int ret = 0;
 
 	kbuf.image = image;
@@ -334,6 +340,7 @@ int load_other_segments(struct kimage *image,
 	return 0;
 
 out_err:
+	image->nr_segments = orig_segments;
 	vfree(dtb);
 	return ret;
 }
diff --git a/arch/arm64/kernel/probes/kprobes.c b/arch/arm64/kernel/probes/kprobes.c
index deba738142ed..f11a1a1f7026 100644
--- a/arch/arm64/kernel/probes/kprobes.c
+++ b/arch/arm64/kernel/probes/kprobes.c
@@ -36,25 +36,16 @@ DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
 static void __kprobes
 post_kprobe_handler(struct kprobe_ctlblk *, struct pt_regs *);
 
-static int __kprobes patch_text(kprobe_opcode_t *addr, u32 opcode)
-{
-	void *addrs[1];
-	u32 insns[1];
-
-	addrs[0] = addr;
-	insns[0] = opcode;
-
-	return aarch64_insn_patch_text(addrs, insns, 1);
-}
-
 static void __kprobes arch_prepare_ss_slot(struct kprobe *p)
 {
+	kprobe_opcode_t *addr = p->ainsn.api.insn;
+	void *addrs[] = {addr, addr + 1};
+	u32 insns[] = {p->opcode, BRK64_OPCODE_KPROBES_SS};
+
 	/* prepare insn slot */
-	patch_text(p->ainsn.api.insn, p->opcode);
+	aarch64_insn_patch_text(addrs, insns, 2);
 
-	flush_icache_range((uintptr_t) (p->ainsn.api.insn),
-			   (uintptr_t) (p->ainsn.api.insn) +
-			   MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
+	flush_icache_range((uintptr_t)addr, (uintptr_t)(addr + MAX_INSN_SIZE));
 
 	/*
 	 * Needs restoring of return address after stepping xol.
@@ -128,13 +119,18 @@ void *alloc_insn_page(void)
 /* arm kprobe: install breakpoint in text */
 void __kprobes arch_arm_kprobe(struct kprobe *p)
 {
-	patch_text(p->addr, BRK64_OPCODE_KPROBES);
+	void *addr = p->addr;
+	u32 insn = BRK64_OPCODE_KPROBES;
+
+	aarch64_insn_patch_text(&addr, &insn, 1);
 }
 
 /* disarm kprobe: remove breakpoint from text */
 void __kprobes arch_disarm_kprobe(struct kprobe *p)
 {
-	patch_text(p->addr, p->opcode);
+	void *addr = p->addr;
+
+	aarch64_insn_patch_text(&addr, &p->opcode, 1);
 }
 
 void __kprobes arch_remove_kprobe(struct kprobe *p)
@@ -163,20 +159,15 @@ static void __kprobes set_current_kprobe(struct kprobe *p)
 }
 
 /*
- * Interrupts need to be disabled before single-step mode is set, and not
- * reenabled until after single-step mode ends.
- * Without disabling interrupt on local CPU, there is a chance of
- * interrupt occurrence in the period of exception return and  start of
- * out-of-line single-step, that result in wrongly single stepping
- * into the interrupt handler.
+ * Mask all of DAIF while executing the instruction out-of-line, to keep things
+ * simple and avoid nesting exceptions. Interrupts do have to be disabled since
+ * the kprobe state is per-CPU and doesn't get migrated.
  */
 static void __kprobes kprobes_save_local_irqflag(struct kprobe_ctlblk *kcb,
 						struct pt_regs *regs)
 {
 	kcb->saved_irqflag = regs->pstate & DAIF_MASK;
-	regs->pstate |= PSR_I_BIT;
-	/* Unmask PSTATE.D for enabling software step exceptions. */
-	regs->pstate &= ~PSR_D_BIT;
+	regs->pstate |= DAIF_MASK;
 }
 
 static void __kprobes kprobes_restore_local_irqflag(struct kprobe_ctlblk *kcb,
@@ -219,10 +210,7 @@ static void __kprobes setup_singlestep(struct kprobe *p,
 		slot = (unsigned long)p->ainsn.api.insn;
 
 		set_ss_context(kcb, slot);	/* mark pending ss */
-
-		/* IRQs and single stepping do not mix well. */
 		kprobes_save_local_irqflag(kcb, regs);
-		kernel_enable_single_step(regs);
 		instruction_pointer_set(regs, slot);
 	} else {
 		/* insn simulation */
@@ -273,12 +261,8 @@ post_kprobe_handler(struct kprobe_ctlblk *kcb, struct pt_regs *regs)
 	}
 	/* call post handler */
 	kcb->kprobe_status = KPROBE_HIT_SSDONE;
-	if (cur->post_handler)	{
-		/* post_handler can hit breakpoint and single step
-		 * again, so we enable D-flag for recursive exception.
-		 */
+	if (cur->post_handler)
 		cur->post_handler(cur, regs, 0);
-	}
 
 	reset_current_kprobe();
 }
@@ -302,8 +286,6 @@ int __kprobes kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr)
 		if (!instruction_pointer(regs))
 			BUG();
 
-		kernel_disable_single_step();
-
 		if (kcb->kprobe_status == KPROBE_REENTER)
 			restore_previous_kprobe(kcb);
 		else
@@ -365,10 +347,6 @@ static void __kprobes kprobe_handler(struct pt_regs *regs)
 			 * pre-handler and it returned non-zero, it will
 			 * modify the execution path and no need to single
 			 * stepping. Let's just reset current kprobe and exit.
-			 *
-			 * pre_handler can hit a breakpoint and can step thru
-			 * before return, keep PSTATE D-flag enabled until
-			 * pre_handler return back.
 			 */
 			if (!p->pre_handler || !p->pre_handler(p, regs)) {
 				setup_singlestep(p, regs, kcb, 0);
@@ -399,7 +377,7 @@ kprobe_ss_hit(struct kprobe_ctlblk *kcb, unsigned long addr)
 }
 
 static int __kprobes
-kprobe_single_step_handler(struct pt_regs *regs, unsigned int esr)
+kprobe_breakpoint_ss_handler(struct pt_regs *regs, unsigned int esr)
 {
 	struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
 	int retval;
@@ -409,16 +387,15 @@ kprobe_single_step_handler(struct pt_regs *regs, unsigned int esr)
 
 	if (retval == DBG_HOOK_HANDLED) {
 		kprobes_restore_local_irqflag(kcb, regs);
-		kernel_disable_single_step();
-
 		post_kprobe_handler(kcb, regs);
 	}
 
 	return retval;
 }
 
-static struct step_hook kprobes_step_hook = {
-	.fn = kprobe_single_step_handler,
+static struct break_hook kprobes_break_ss_hook = {
+	.imm = KPROBES_BRK_SS_IMM,
+	.fn = kprobe_breakpoint_ss_handler,
 };
 
 static int __kprobes
@@ -486,7 +463,7 @@ int __kprobes arch_trampoline_kprobe(struct kprobe *p)
 int __init arch_init_kprobes(void)
 {
 	register_kernel_break_hook(&kprobes_break_hook);
-	register_kernel_step_hook(&kprobes_step_hook);
+	register_kernel_break_hook(&kprobes_break_ss_hook);
 
 	return 0;
 }
diff --git a/arch/powerpc/include/asm/nohash/32/kup-8xx.h b/arch/powerpc/include/asm/nohash/32/kup-8xx.h
index 85ed2390fb99..567cdc557402 100644
--- a/arch/powerpc/include/asm/nohash/32/kup-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/kup-8xx.h
@@ -63,7 +63,7 @@ static inline void restore_user_access(unsigned long flags)
 static inline bool
 bad_kuap_fault(struct pt_regs *regs, unsigned long address, bool is_write)
 {
-	return WARN(!((regs->kuap ^ MD_APG_KUAP) & 0xf0000000),
+	return WARN(!((regs->kuap ^ MD_APG_KUAP) & 0xff000000),
 		    "Bug: fault blocked by AP register !");
 }
 
diff --git a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
index 1d9ac0f9c794..0bd1b144eb76 100644
--- a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
@@ -33,19 +33,18 @@
  * respectively NA for All or X for Supervisor and no access for User.
  * Then we use the APG to say whether accesses are according to Page rules or
  * "all Supervisor" rules (Access to all)
- * Therefore, we define 2 APG groups. lsb is _PMD_USER
- * 0 => Kernel => 01 (all accesses performed according to page definition)
- * 1 => User => 00 (all accesses performed as supervisor iaw page definition)
- * 2-15 => Not Used
- */
-#define MI_APG_INIT	0x40000000
-
-/*
- * 0 => Kernel => 01 (all accesses performed according to page definition)
- * 1 => User => 10 (all accesses performed according to swaped page definition)
- * 2-15 => Not Used
- */
-#define MI_APG_KUEP	0x60000000
+ * _PAGE_ACCESSED is also managed via APG. When _PAGE_ACCESSED is not set, say
+ * "all User" rules, that will lead to NA for all.
+ * Therefore, we define 4 APG groups. lsb is _PAGE_ACCESSED
+ * 0 => Kernel => 11 (all accesses performed according as user iaw page definition)
+ * 1 => Kernel+Accessed => 01 (all accesses performed according to page definition)
+ * 2 => User => 11 (all accesses performed according as user iaw page definition)
+ * 3 => User+Accessed => 00 (all accesses performed as supervisor iaw page definition) for INIT
+ *                    => 10 (all accesses performed according to swaped page definition) for KUEP
+ * 4-15 => Not Used
+ */
+#define MI_APG_INIT	0xdc000000
+#define MI_APG_KUEP	0xde000000
 
 /* The effective page number register.  When read, contains the information
  * about the last instruction TLB miss.  When MI_RPN is written, bits in
@@ -106,25 +105,9 @@
 #define MD_Ks		0x80000000	/* Should not be set */
 #define MD_Kp		0x40000000	/* Should always be set */
 
-/*
- * All pages' PP data bits are set to either 000 or 011 or 001, which means
- * respectively RW for Supervisor and no access for User, or RO for
- * Supervisor and no access for user and NA for ALL.
- * Then we use the APG to say whether accesses are according to Page rules or
- * "all Supervisor" rules (Access to all)
- * Therefore, we define 2 APG groups. lsb is _PMD_USER
- * 0 => Kernel => 01 (all accesses performed according to page definition)
- * 1 => User => 00 (all accesses performed as supervisor iaw page definition)
- * 2-15 => Not Used
- */
-#define MD_APG_INIT	0x40000000
-
-/*
- * 0 => No user => 01 (all accesses performed according to page definition)
- * 1 => User => 10 (all accesses performed according to swaped page definition)
- * 2-15 => Not Used
- */
-#define MD_APG_KUAP	0x60000000
+/* See explanation above at the definition of MI_APG_INIT */
+#define MD_APG_INIT	0xdc000000
+#define MD_APG_KUAP	0xde000000
 
 /* The effective page number register.  When read, contains the information
  * about the last instruction TLB miss.  When MD_RPN is written, bits in
diff --git a/arch/powerpc/include/asm/nohash/32/pte-8xx.h b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
index 66f403a7da44..1581204467e1 100644
--- a/arch/powerpc/include/asm/nohash/32/pte-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
@@ -39,9 +39,9 @@
  * into the TLB.
  */
 #define _PAGE_GUARDED	0x0010	/* Copied to L1 G entry in DTLB */
-#define _PAGE_SPECIAL	0x0020	/* SW entry */
+#define _PAGE_ACCESSED	0x0020	/* Copied to L1 APG 1 entry in I/DTLB */
 #define _PAGE_EXEC	0x0040	/* Copied to PP (bit 21) in ITLB */
-#define _PAGE_ACCESSED	0x0080	/* software: page referenced */
+#define _PAGE_SPECIAL	0x0080	/* SW entry */
 
 #define _PAGE_NA	0x0200	/* Supervisor NA, User no access */
 #define _PAGE_RO	0x0600	/* Supervisor RO, User no access */
@@ -59,11 +59,12 @@
 
 #define _PMD_PRESENT	0x0001
 #define _PMD_PRESENT_MASK	_PMD_PRESENT
-#define _PMD_BAD	0x0fd0
+#define _PMD_BAD	0x0f90
 #define _PMD_PAGE_MASK	0x000c
 #define _PMD_PAGE_8M	0x000c
 #define _PMD_PAGE_512K	0x0004
-#define _PMD_USER	0x0020	/* APG 1 */
+#define _PMD_ACCESSED	0x0020	/* APG 1 */
+#define _PMD_USER	0x0040	/* APG 2 */
 
 #define _PTE_NONE_MASK	0
 
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index 8728590f514a..3beeb030cd78 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -6,6 +6,7 @@
 
 struct device;
 struct device_node;
+struct drmem_lmb;
 
 #ifdef CONFIG_NUMA
 
@@ -61,6 +62,9 @@ static inline int early_cpu_to_node(int cpu)
 	 */
 	return (nid < 0) ? 0 : nid;
 }
+
+int of_drconf_to_nid_single(struct drmem_lmb *lmb);
+
 #else
 
 static inline int early_cpu_to_node(int cpu) { return 0; }
@@ -84,10 +88,12 @@ static inline int cpu_distance(__be32 *cpu1_assoc, __be32 *cpu2_assoc)
 	return 0;
 }
 
-#endif /* CONFIG_NUMA */
+static inline int of_drconf_to_nid_single(struct drmem_lmb *lmb)
+{
+	return first_online_node;
+}
 
-struct drmem_lmb;
-int of_drconf_to_nid_single(struct drmem_lmb *lmb);
+#endif /* CONFIG_NUMA */
 
 #if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR)
 extern int find_and_online_cpu_nid(int cpu);
diff --git a/arch/powerpc/include/asm/uaccess.h b/arch/powerpc/include/asm/uaccess.h
index ef5bbb705c08..501c9a79038c 100644
--- a/arch/powerpc/include/asm/uaccess.h
+++ b/arch/powerpc/include/asm/uaccess.h
@@ -178,7 +178,7 @@ do {								\
  * are no aliasing issues.
  */
 #define __put_user_asm_goto(x, addr, label, op)			\
-	asm volatile goto(					\
+	asm_volatile_goto(					\
 		"1:	" op "%U1%X1 %0,%1	# put_user\n"	\
 		EX_TABLE(1b, %l2)				\
 		:						\
@@ -191,7 +191,7 @@ do {								\
 	__put_user_asm_goto(x, ptr, label, "std")
 #else /* __powerpc64__ */
 #define __put_user_asm2_goto(x, addr, label)			\
-	asm volatile goto(					\
+	asm_volatile_goto(					\
 		"1:	stw%X1 %0, %1\n"			\
 		"2:	stw%X1 %L0, %L1\n"			\
 		EX_TABLE(1b, %l2)				\
diff --git a/arch/powerpc/kernel/eeh_cache.c b/arch/powerpc/kernel/eeh_cache.c
index 6b50bf15d8c1..bf3270426d82 100644
--- a/arch/powerpc/kernel/eeh_cache.c
+++ b/arch/powerpc/kernel/eeh_cache.c
@@ -264,8 +264,9 @@ static int eeh_addr_cache_show(struct seq_file *s, void *v)
 {
 	struct pci_io_addr_range *piar;
 	struct rb_node *n;
+	unsigned long flags;
 
-	spin_lock(&pci_io_addr_cache_root.piar_lock);
+	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
 	for (n = rb_first(&pci_io_addr_cache_root.rb_root); n; n = rb_next(n)) {
 		piar = rb_entry(n, struct pci_io_addr_range, rb_node);
 
@@ -273,7 +274,7 @@ static int eeh_addr_cache_show(struct seq_file *s, void *v)
 		       (piar->flags & IORESOURCE_IO) ? "i/o" : "mem",
 		       &piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev));
 	}
-	spin_unlock(&pci_io_addr_cache_root.piar_lock);
+	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
 
 	return 0;
 }
diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
index 44c9018aed1b..a1ae00689e0f 100644
--- a/arch/powerpc/kernel/head_40x.S
+++ b/arch/powerpc/kernel/head_40x.S
@@ -284,11 +284,7 @@ _ENTRY(saved_ksp_limit)
 
 	rlwimi	r11, r10, 22, 20, 29	/* Compute PTE address */
 	lwz	r11, 0(r11)		/* Get Linux PTE */
-#ifdef CONFIG_SWAP
 	li	r9, _PAGE_PRESENT | _PAGE_ACCESSED
-#else
-	li	r9, _PAGE_PRESENT
-#endif
 	andc.	r9, r9, r11		/* Check permission */
 	bne	5f
 
@@ -369,11 +365,7 @@ _ENTRY(saved_ksp_limit)
 
 	rlwimi	r11, r10, 22, 20, 29	/* Compute PTE address */
 	lwz	r11, 0(r11)		/* Get Linux PTE */
-#ifdef CONFIG_SWAP
 	li	r9, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
-#else
-	li	r9, _PAGE_PRESENT | _PAGE_EXEC
-#endif
 	andc.	r9, r9, r11		/* Check permission */
 	bne	5f
 
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 9f359d3fba74..ee0bfebc375f 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -202,9 +202,7 @@ SystemCall:
 
 InstructionTLBMiss:
 	mtspr	SPRN_SPRG_SCRATCH0, r10
-#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) || defined(CONFIG_HUGETLBFS)
 	mtspr	SPRN_SPRG_SCRATCH1, r11
-#endif
 
 	/* If we are faulting a kernel address, we have to use the
 	 * kernel page tables.
@@ -224,25 +222,13 @@ InstructionTLBMiss:
 3:
 	mtcr	r11
 #endif
-#if defined(CONFIG_HUGETLBFS) || !defined(CONFIG_PIN_TLB_TEXT)
 	lwz	r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10)	/* Get level 1 entry */
 	mtspr	SPRN_MD_TWC, r11
-#else
-	lwz	r10, (swapper_pg_dir-PAGE_OFFSET)@l(r10)	/* Get level 1 entry */
-	mtspr	SPRN_MI_TWC, r10	/* Set segment attributes */
-	mtspr	SPRN_MD_TWC, r10
-#endif
 	mfspr	r10, SPRN_MD_TWC
 	lwz	r10, 0(r10)	/* Get the pte */
-#if defined(CONFIG_HUGETLBFS) || !defined(CONFIG_PIN_TLB_TEXT)
+	rlwimi	r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED
 	rlwimi	r11, r10, 32 - 9, _PMD_PAGE_512K
 	mtspr	SPRN_MI_TWC, r11
-#endif
-#ifdef CONFIG_SWAP
-	rlwinm	r11, r10, 32-5, _PAGE_PRESENT
-	and	r11, r11, r10
-	rlwimi	r10, r11, 0, _PAGE_PRESENT
-#endif
 	/* The Linux PTE won't go exactly into the MMU TLB.
 	 * Software indicator bits 20 and 23 must be clear.
 	 * Software indicator bits 22, 24, 25, 26, and 27 must be
@@ -256,9 +242,7 @@ InstructionTLBMiss:
 
 	/* Restore registers */
 0:	mfspr	r10, SPRN_SPRG_SCRATCH0
-#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) || defined(CONFIG_HUGETLBFS)
 	mfspr	r11, SPRN_SPRG_SCRATCH1
-#endif
 	rfi
 	patch_site	0b, patch__itlbmiss_exit_1
 
@@ -268,9 +252,7 @@ InstructionTLBMiss:
 	addi	r10, r10, 1
 	stw	r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
 	mfspr	r10, SPRN_SPRG_SCRATCH0
-#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
 	mfspr	r11, SPRN_SPRG_SCRATCH1
-#endif
 	rfi
 #endif
 
@@ -297,30 +279,16 @@ DataStoreTLBMiss:
 	mfspr	r10, SPRN_MD_TWC
 	lwz	r10, 0(r10)	/* Get the pte */
 
-	/* Insert the Guarded flag into the TWC from the Linux PTE.
+	/* Insert Guarded and Accessed flags into the TWC from the Linux PTE.
 	 * It is bit 27 of both the Linux PTE and the TWC (at least
 	 * I got that right :-).  It will be better when we can put
 	 * this into the Linux pgd/pmd and load it in the operation
 	 * above.
 	 */
-	rlwimi	r11, r10, 0, _PAGE_GUARDED
+	rlwimi	r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED
 	rlwimi	r11, r10, 32 - 9, _PMD_PAGE_512K
 	mtspr	SPRN_MD_TWC, r11
 
-	/* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
-	 * We also need to know if the insn is a load/store, so:
-	 * Clear _PAGE_PRESENT and load that which will
-	 * trap into DTLB Error with store bit set accordinly.
-	 */
-	/* PRESENT=0x1, ACCESSED=0x20
-	 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
-	 * r10 = (r10 & ~PRESENT) | r11;
-	 */
-#ifdef CONFIG_SWAP
-	rlwinm	r11, r10, 32-5, _PAGE_PRESENT
-	and	r11, r11, r10
-	rlwimi	r10, r11, 0, _PAGE_PRESENT
-#endif
 	/* The Linux PTE won't go exactly into the MMU TLB.
 	 * Software indicator bits 24, 25, 26, and 27 must be
 	 * set.  All other Linux PTE bits control the behavior
@@ -711,7 +679,7 @@ initial_mmu:
 	li	r9, 4				/* up to 4 pages of 8M */
 	mtctr	r9
 	lis	r9, KERNELBASE@h		/* Create vaddr for TLB */
-	li	r10, MI_PS8MEG | MI_SVALID	/* Set 8M byte page */
+	li	r10, MI_PS8MEG | _PMD_ACCESSED | MI_SVALID
 	li	r11, MI_BOOTINIT		/* Create RPN for address 0 */
 1:
 	mtspr	SPRN_MI_CTR, r8	/* Set instruction MMU control */
@@ -775,7 +743,7 @@ _GLOBAL(mmu_pin_tlb)
 #ifdef CONFIG_PIN_TLB_TEXT
 	LOAD_REG_IMMEDIATE(r5, 28 << 8)
 	LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET)
-	LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG)
+	LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED)
 	LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT)
 	LOAD_REG_ADDR(r9, _sinittext)
 	li	r0, 4
@@ -797,7 +765,7 @@ _GLOBAL(mmu_pin_tlb)
 	LOAD_REG_IMMEDIATE(r5, 28 << 8 | MD_TWAM)
 #ifdef CONFIG_PIN_TLB_DATA
 	LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET)
-	LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG)
+	LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED)
 #ifdef CONFIG_PIN_TLB_IMMR
 	li	r0, 3
 #else
@@ -834,7 +802,7 @@ _GLOBAL(mmu_pin_tlb)
 #endif
 #ifdef CONFIG_PIN_TLB_IMMR
 	LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID)
-	LOAD_REG_IMMEDIATE(r7, MD_SVALID | MD_PS512K | MD_GUARDED)
+	LOAD_REG_IMMEDIATE(r7, MD_SVALID | MD_PS512K | MD_GUARDED | _PMD_ACCESSED)
 	mfspr   r8, SPRN_IMMR
 	rlwinm	r8, r8, 0, 0xfff80000
 	ori	r8, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \
diff --git a/arch/powerpc/kernel/head_book3s_32.S b/arch/powerpc/kernel/head_book3s_32.S
index 5eb9eedac920..2aa16d5368e1 100644
--- a/arch/powerpc/kernel/head_book3s_32.S
+++ b/arch/powerpc/kernel/head_book3s_32.S
@@ -457,11 +457,7 @@ InstructionTLBMiss:
 	cmplw	0,r1,r3
 #endif
 	mfspr	r2, SPRN_SPRG_PGDIR
-#ifdef CONFIG_SWAP
 	li	r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
-#else
-	li	r1,_PAGE_PRESENT | _PAGE_EXEC
-#endif
 #if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
 	bgt-	112f
 	lis	r2, (swapper_pg_dir - PAGE_OFFSET)@ha	/* if kernel address, use */
@@ -523,11 +519,7 @@ DataLoadTLBMiss:
 	lis	r1, TASK_SIZE@h		/* check if kernel address */
 	cmplw	0,r1,r3
 	mfspr	r2, SPRN_SPRG_PGDIR
-#ifdef CONFIG_SWAP
 	li	r1, _PAGE_PRESENT | _PAGE_ACCESSED
-#else
-	li	r1, _PAGE_PRESENT
-#endif
 	bgt-	112f
 	lis	r2, (swapper_pg_dir - PAGE_OFFSET)@ha	/* if kernel address, use */
 	addi	r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l	/* kernel page table */
@@ -603,11 +595,7 @@ DataStoreTLBMiss:
 	lis	r1, TASK_SIZE@h		/* check if kernel address */
 	cmplw	0,r1,r3
 	mfspr	r2, SPRN_SPRG_PGDIR
-#ifdef CONFIG_SWAP
 	li	r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
-#else
-	li	r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT
-#endif
 	bgt-	112f
 	lis	r2, (swapper_pg_dir - PAGE_OFFSET)@ha	/* if kernel address, use */
 	addi	r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l	/* kernel page table */
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 3c6b9822f978..8c2857cbd960 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -1393,13 +1393,14 @@ static void add_cpu_to_masks(int cpu)
 /* Activate a secondary processor. */
 void start_secondary(void *unused)
 {
-	unsigned int cpu = smp_processor_id();
+	unsigned int cpu = raw_smp_processor_id();
 
 	mmgrab(&init_mm);
 	current->active_mm = &init_mm;
 
 	smp_store_cpu_info(cpu);
 	set_dec(tb_ticks_per_jiffy);
+	rcu_cpu_starting(cpu);
 	preempt_disable();
 	cpu_callin_map[cpu] = 1;
 
diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h
index c47e6b35c551..824b2c9da75b 100644
--- a/arch/riscv/include/asm/uaccess.h
+++ b/arch/riscv/include/asm/uaccess.h
@@ -476,7 +476,7 @@ do {									\
 do {									\
 	long __kr_err;							\
 									\
-	__put_user_nocheck(*((type *)(dst)), (type *)(src), __kr_err);	\
+	__put_user_nocheck(*((type *)(src)), (type *)(dst), __kr_err);	\
 	if (unlikely(__kr_err))						\
 		goto err_label;						\
 } while (0)
diff --git a/arch/riscv/kernel/ftrace.c b/arch/riscv/kernel/ftrace.c
index 99e12faa5498..765b62434f30 100644
--- a/arch/riscv/kernel/ftrace.c
+++ b/arch/riscv/kernel/ftrace.c
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2013 Linaro Limited
  * Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 11e2a4fe66e0..7e849797c9c3 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -35,6 +35,10 @@ ENTRY(_start)
 	.word 0
 #endif
 	.balign 8
+#ifdef CONFIG_RISCV_M_MODE
+	/* Image load offset (0MB) from start of RAM for M-mode */
+	.dword 0
+#else
 #if __riscv_xlen == 64
 	/* Image load offset(2MB) from start of RAM */
 	.dword 0x200000
@@ -42,6 +46,7 @@ ENTRY(_start)
 	/* Image load offset(4MB) from start of RAM */
 	.dword 0x400000
 #endif
+#endif
 	/* Effective size of kernel image */
 	.dword _end - _start
 	.dword __HEAD_FLAGS
diff --git a/arch/riscv/kernel/vdso/.gitignore b/arch/riscv/kernel/vdso/.gitignore
index 11ebee9e4c1d..3a19def868ec 100644
--- a/arch/riscv/kernel/vdso/.gitignore
+++ b/arch/riscv/kernel/vdso/.gitignore
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 vdso.lds
 *.tmp
+vdso-syms.S
diff --git a/arch/riscv/kernel/vdso/Makefile b/arch/riscv/kernel/vdso/Makefile
index 7d6a94d45ec9..cb8f9e4cfcbf 100644
--- a/arch/riscv/kernel/vdso/Makefile
+++ b/arch/riscv/kernel/vdso/Makefile
@@ -43,19 +43,14 @@ $(obj)/vdso.o: $(obj)/vdso.so
 SYSCFLAGS_vdso.so.dbg = $(c_flags)
 $(obj)/vdso.so.dbg: $(src)/vdso.lds $(obj-vdso) FORCE
 	$(call if_changed,vdsold)
+SYSCFLAGS_vdso.so.dbg = -shared -s -Wl,-soname=linux-vdso.so.1 \
+	-Wl,--build-id -Wl,--hash-style=both
 
 # We also create a special relocatable object that should mirror the symbol
 # table and layout of the linked DSO. With ld --just-symbols we can then
 # refer to these symbols in the kernel code rather than hand-coded addresses.
-
-SYSCFLAGS_vdso.so.dbg = -shared -s -Wl,-soname=linux-vdso.so.1 \
-	-Wl,--build-id=sha1 -Wl,--hash-style=both
-$(obj)/vdso-dummy.o: $(src)/vdso.lds $(obj)/rt_sigreturn.o FORCE
-	$(call if_changed,vdsold)
-
-LDFLAGS_vdso-syms.o := -r --just-symbols
-$(obj)/vdso-syms.o: $(obj)/vdso-dummy.o FORCE
-	$(call if_changed,ld)
+$(obj)/vdso-syms.S: $(obj)/vdso.so FORCE
+	$(call if_changed,so2s)
 
 # strip rule for the .so file
 $(obj)/%.so: OBJCOPYFLAGS := -S
@@ -73,6 +68,11 @@ quiet_cmd_vdsold = VDSOLD  $@
                            $(patsubst %, -G __vdso_%, $(vdso-syms)) $@.tmp $@ && \
                    rm $@.tmp
 
+# Extracts symbol offsets from the VDSO, converting them into an assembly file
+# that contains the same symbols at the same offsets.
+quiet_cmd_so2s = SO2S    $@
+      cmd_so2s = $(NM) -D $< | $(srctree)/$(src)/so2s.sh > $@
+
 # install commands for the unstripped file
 quiet_cmd_vdso_install = INSTALL $@
       cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/$@
diff --git a/arch/riscv/kernel/vdso/so2s.sh b/arch/riscv/kernel/vdso/so2s.sh
new file mode 100755
index 000000000000..e64cb6d9440e
--- /dev/null
+++ b/arch/riscv/kernel/vdso/so2s.sh
@@ -0,0 +1,6 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2020 Palmer Dabbelt <palmerdabbelt@google.com>
+
+sed 's!\([0-9a-f]*\) T \([a-z0-9_]*\)\(@@LINUX_4.15\)*!.global \2\n.set \2,0x\1!' \
+| grep '^\.'
diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
index 1359e21c0c62..3c8b9e433c67 100644
--- a/arch/riscv/mm/fault.c
+++ b/arch/riscv/mm/fault.c
@@ -86,6 +86,7 @@ static inline void vmalloc_fault(struct pt_regs *regs, int code, unsigned long a
 	pmd_t *pmd, *pmd_k;
 	pte_t *pte_k;
 	int index;
+	unsigned long pfn;
 
 	/* User mode accesses just cause a SIGSEGV */
 	if (user_mode(regs))
@@ -100,7 +101,8 @@ static inline void vmalloc_fault(struct pt_regs *regs, int code, unsigned long a
 	 * of a task switch.
 	 */
 	index = pgd_index(addr);
-	pgd = (pgd_t *)pfn_to_virt(csr_read(CSR_SATP)) + index;
+	pfn = csr_read(CSR_SATP) & SATP_PPN;
+	pgd = (pgd_t *)pfn_to_virt(pfn) + index;
 	pgd_k = init_mm.pgd + index;
 
 	if (!pgd_present(*pgd_k)) {
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index ea933b789a88..8e577f14f120 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -154,9 +154,8 @@ disable:
 
 void __init setup_bootmem(void)
 {
-	phys_addr_t mem_size = 0;
-	phys_addr_t total_mem = 0;
-	phys_addr_t mem_start, start, end = 0;
+	phys_addr_t mem_start = 0;
+	phys_addr_t start, end = 0;
 	phys_addr_t vmlinux_end = __pa_symbol(&_end);
 	phys_addr_t vmlinux_start = __pa_symbol(&_start);
 	u64 i;
@@ -164,21 +163,18 @@ void __init setup_bootmem(void)
 	/* Find the memory region containing the kernel */
 	for_each_mem_range(i, &start, &end) {
 		phys_addr_t size = end - start;
-		if (!total_mem)
+		if (!mem_start)
 			mem_start = start;
 		if (start <= vmlinux_start && vmlinux_end <= end)
 			BUG_ON(size == 0);
-		total_mem = total_mem + size;
 	}
 
 	/*
-	 * Remove memblock from the end of usable area to the
-	 * end of region
+	 * The maximal physical memory size is -PAGE_OFFSET.
+	 * Make sure that any memory beyond mem_start + (-PAGE_OFFSET) is removed
+	 * as it is unusable by kernel.
 	 */
-	mem_size = min(total_mem, (phys_addr_t)-PAGE_OFFSET);
-	if (mem_start + mem_size < end)
-		memblock_remove(mem_start + mem_size,
-				end - mem_start - mem_size);
+	memblock_enforce_memory_limit(mem_start - PAGE_OFFSET);
 
 	/* Reserve from the start of the kernel to the end of the kernel */
 	memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start);
@@ -297,6 +293,7 @@ pmd_t fixmap_pmd[PTRS_PER_PMD] __page_aligned_bss;
 #define NUM_EARLY_PMDS		(1UL + MAX_EARLY_MAPPING_SIZE / PGDIR_SIZE)
 #endif
 pmd_t early_pmd[PTRS_PER_PMD * NUM_EARLY_PMDS] __initdata __aligned(PAGE_SIZE);
+pmd_t early_dtb_pmd[PTRS_PER_PMD] __initdata __aligned(PAGE_SIZE);
 
 static pmd_t *__init get_pmd_virt_early(phys_addr_t pa)
 {
@@ -494,6 +491,18 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
 				   load_pa + (va - PAGE_OFFSET),
 				   map_size, PAGE_KERNEL_EXEC);
 
+#ifndef __PAGETABLE_PMD_FOLDED
+	/* Setup early PMD for DTB */
+	create_pgd_mapping(early_pg_dir, DTB_EARLY_BASE_VA,
+			   (uintptr_t)early_dtb_pmd, PGDIR_SIZE, PAGE_TABLE);
+	/* Create two consecutive PMD mappings for FDT early scan */
+	pa = dtb_pa & ~(PMD_SIZE - 1);
+	create_pmd_mapping(early_dtb_pmd, DTB_EARLY_BASE_VA,
+			   pa, PMD_SIZE, PAGE_KERNEL);
+	create_pmd_mapping(early_dtb_pmd, DTB_EARLY_BASE_VA + PMD_SIZE,
+			   pa + PMD_SIZE, PMD_SIZE, PAGE_KERNEL);
+	dtb_early_va = (void *)DTB_EARLY_BASE_VA + (dtb_pa & (PMD_SIZE - 1));
+#else
 	/* Create two consecutive PGD mappings for FDT early scan */
 	pa = dtb_pa & ~(PGDIR_SIZE - 1);
 	create_pgd_mapping(early_pg_dir, DTB_EARLY_BASE_VA,
@@ -501,6 +510,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
 	create_pgd_mapping(early_pg_dir, DTB_EARLY_BASE_VA + PGDIR_SIZE,
 			   pa + PGDIR_SIZE, PGDIR_SIZE, PAGE_KERNEL);
 	dtb_early_va = (void *)DTB_EARLY_BASE_VA + (dtb_pa & (PGDIR_SIZE - 1));
+#endif
 	dtb_early_pa = dtb_pa;
 
 	/*
diff --git a/arch/s390/configs/debug_defconfig b/arch/s390/configs/debug_defconfig
index 0784bf3caf43..a4d3c578fbd8 100644
--- a/arch/s390/configs/debug_defconfig
+++ b/arch/s390/configs/debug_defconfig
@@ -93,9 +93,10 @@ CONFIG_CLEANCACHE=y
 CONFIG_FRONTSWAP=y
 CONFIG_CMA_DEBUG=y
 CONFIG_CMA_DEBUGFS=y
+CONFIG_CMA_AREAS=7
 CONFIG_MEM_SOFT_DIRTY=y
 CONFIG_ZSWAP=y
-CONFIG_ZSMALLOC=m
+CONFIG_ZSMALLOC=y
 CONFIG_ZSMALLOC_STAT=y
 CONFIG_DEFERRED_STRUCT_PAGE_INIT=y
 CONFIG_IDLE_PAGE_TRACKING=y
@@ -378,7 +379,6 @@ CONFIG_NETLINK_DIAG=m
 CONFIG_CGROUP_NET_PRIO=y
 CONFIG_BPF_JIT=y
 CONFIG_NET_PKTGEN=m
-# CONFIG_NET_DROP_MONITOR is not set
 CONFIG_PCI=y
 # CONFIG_PCIEASPM is not set
 CONFIG_PCI_DEBUG=y
@@ -386,7 +386,7 @@ CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_S390=y
 CONFIG_DEVTMPFS=y
 CONFIG_CONNECTOR=y
-CONFIG_ZRAM=m
+CONFIG_ZRAM=y
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_DRBD=m
@@ -689,6 +689,7 @@ CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_DH=m
 CONFIG_CRYPTO_ECDH=m
 CONFIG_CRYPTO_ECRDSA=m
+CONFIG_CRYPTO_SM2=m
 CONFIG_CRYPTO_CURVE25519=m
 CONFIG_CRYPTO_GCM=y
 CONFIG_CRYPTO_CHACHA20POLY1305=m
@@ -709,7 +710,6 @@ CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SM3=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_AES_TI=m
@@ -753,6 +753,7 @@ CONFIG_CRYPTO_DES_S390=m
 CONFIG_CRYPTO_AES_S390=m
 CONFIG_CRYPTO_GHASH_S390=m
 CONFIG_CRYPTO_CRC32_S390=y
+CONFIG_CRYPTO_DEV_VIRTIO=m
 CONFIG_CORDIC=m
 CONFIG_CRC32_SELFTEST=y
 CONFIG_CRC4=m
@@ -829,6 +830,7 @@ CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m
 CONFIG_FAULT_INJECTION=y
 CONFIG_FAILSLAB=y
 CONFIG_FAIL_PAGE_ALLOC=y
+CONFIG_FAULT_INJECTION_USERCOPY=y
 CONFIG_FAIL_MAKE_REQUEST=y
 CONFIG_FAIL_IO_TIMEOUT=y
 CONFIG_FAIL_FUTEX=y
diff --git a/arch/s390/configs/defconfig b/arch/s390/configs/defconfig
index 905bc8c4cfaf..17d5df2c1eff 100644
--- a/arch/s390/configs/defconfig
+++ b/arch/s390/configs/defconfig
@@ -87,9 +87,10 @@ CONFIG_KSM=y
 CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_CLEANCACHE=y
 CONFIG_FRONTSWAP=y
+CONFIG_CMA_AREAS=7
 CONFIG_MEM_SOFT_DIRTY=y
 CONFIG_ZSWAP=y
-CONFIG_ZSMALLOC=m
+CONFIG_ZSMALLOC=y
 CONFIG_ZSMALLOC_STAT=y
 CONFIG_DEFERRED_STRUCT_PAGE_INIT=y
 CONFIG_IDLE_PAGE_TRACKING=y
@@ -371,7 +372,6 @@ CONFIG_NETLINK_DIAG=m
 CONFIG_CGROUP_NET_PRIO=y
 CONFIG_BPF_JIT=y
 CONFIG_NET_PKTGEN=m
-# CONFIG_NET_DROP_MONITOR is not set
 CONFIG_PCI=y
 # CONFIG_PCIEASPM is not set
 CONFIG_HOTPLUG_PCI=y
@@ -379,7 +379,7 @@ CONFIG_HOTPLUG_PCI_S390=y
 CONFIG_UEVENT_HELPER=y
 CONFIG_DEVTMPFS=y
 CONFIG_CONNECTOR=y
-CONFIG_ZRAM=m
+CONFIG_ZRAM=y
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_DRBD=m
@@ -680,6 +680,7 @@ CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_DH=m
 CONFIG_CRYPTO_ECDH=m
 CONFIG_CRYPTO_ECRDSA=m
+CONFIG_CRYPTO_SM2=m
 CONFIG_CRYPTO_CURVE25519=m
 CONFIG_CRYPTO_GCM=y
 CONFIG_CRYPTO_CHACHA20POLY1305=m
@@ -701,7 +702,6 @@ CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
 CONFIG_CRYPTO_SHA3=m
-CONFIG_CRYPTO_SM3=m
 CONFIG_CRYPTO_TGR192=m
 CONFIG_CRYPTO_WP512=m
 CONFIG_CRYPTO_AES_TI=m
@@ -745,6 +745,7 @@ CONFIG_CRYPTO_DES_S390=m
 CONFIG_CRYPTO_AES_S390=m
 CONFIG_CRYPTO_GHASH_S390=m
 CONFIG_CRYPTO_CRC32_S390=y
+CONFIG_CRYPTO_DEV_VIRTIO=m
 CONFIG_CORDIC=m
 CONFIG_PRIME_NUMBERS=m
 CONFIG_CRC4=m
diff --git a/arch/s390/configs/zfcpdump_defconfig b/arch/s390/configs/zfcpdump_defconfig
index 8f67c55625f9..a302630341ef 100644
--- a/arch/s390/configs/zfcpdump_defconfig
+++ b/arch/s390/configs/zfcpdump_defconfig
@@ -17,11 +17,11 @@ CONFIG_HZ_100=y
 # CONFIG_CHSC_SCH is not set
 # CONFIG_SCM_BUS is not set
 CONFIG_CRASH_DUMP=y
-# CONFIG_SECCOMP is not set
 # CONFIG_PFAULT is not set
 # CONFIG_S390_HYPFS_FS is not set
 # CONFIG_VIRTUALIZATION is not set
 # CONFIG_S390_GUEST is not set
+# CONFIG_SECCOMP is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_IBM_PARTITION=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 6b8d8c69b1a1..b5dbae78969b 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -692,16 +692,6 @@ static inline int pud_large(pud_t pud)
 	return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
 }
 
-static inline unsigned long pud_pfn(pud_t pud)
-{
-	unsigned long origin_mask;
-
-	origin_mask = _REGION_ENTRY_ORIGIN;
-	if (pud_large(pud))
-		origin_mask = _REGION3_ENTRY_ORIGIN_LARGE;
-	return (pud_val(pud) & origin_mask) >> PAGE_SHIFT;
-}
-
 #define pmd_leaf	pmd_large
 static inline int pmd_large(pmd_t pmd)
 {
@@ -747,16 +737,6 @@ static inline int pmd_none(pmd_t pmd)
 	return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY;
 }
 
-static inline unsigned long pmd_pfn(pmd_t pmd)
-{
-	unsigned long origin_mask;
-
-	origin_mask = _SEGMENT_ENTRY_ORIGIN;
-	if (pmd_large(pmd))
-		origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE;
-	return (pmd_val(pmd) & origin_mask) >> PAGE_SHIFT;
-}
-
 #define pmd_write pmd_write
 static inline int pmd_write(pmd_t pmd)
 {
@@ -1238,11 +1218,39 @@ static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 
-#define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
-#define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
 #define p4d_deref(pud) (p4d_val(pud) & _REGION_ENTRY_ORIGIN)
 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
 
+static inline unsigned long pmd_deref(pmd_t pmd)
+{
+	unsigned long origin_mask;
+
+	origin_mask = _SEGMENT_ENTRY_ORIGIN;
+	if (pmd_large(pmd))
+		origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE;
+	return pmd_val(pmd) & origin_mask;
+}
+
+static inline unsigned long pmd_pfn(pmd_t pmd)
+{
+	return pmd_deref(pmd) >> PAGE_SHIFT;
+}
+
+static inline unsigned long pud_deref(pud_t pud)
+{
+	unsigned long origin_mask;
+
+	origin_mask = _REGION_ENTRY_ORIGIN;
+	if (pud_large(pud))
+		origin_mask = _REGION3_ENTRY_ORIGIN_LARGE;
+	return pud_val(pud) & origin_mask;
+}
+
+static inline unsigned long pud_pfn(pud_t pud)
+{
+	return pud_deref(pud) >> PAGE_SHIFT;
+}
+
 /*
  * The pgd_offset function *always* adds the index for the top-level
  * region/segment table. This is done to get a sequence like the
diff --git a/arch/s390/include/asm/vdso/vdso.h b/arch/s390/include/asm/vdso/vdso.h
deleted file mode 100644
index e69de29bb2d1..000000000000
--- a/arch/s390/include/asm/vdso/vdso.h
+++ /dev/null
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index ece58f2217cb..2012c1cf0853 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -61,14 +61,6 @@ int main(void)
 	BLANK();
 	OFFSET(__VDSO_GETCPU_VAL, vdso_per_cpu_data, getcpu_val);
 	BLANK();
-	/* constants used by the vdso */
-	DEFINE(__CLOCK_REALTIME, CLOCK_REALTIME);
-	DEFINE(__CLOCK_MONOTONIC, CLOCK_MONOTONIC);
-	DEFINE(__CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
-	DEFINE(__CLOCK_MONOTONIC_COARSE, CLOCK_MONOTONIC_COARSE);
-	DEFINE(__CLOCK_THREAD_CPUTIME_ID, CLOCK_THREAD_CPUTIME_ID);
-	DEFINE(__CLOCK_COARSE_RES, LOW_RES_NSEC);
-	BLANK();
 	/* idle data offsets */
 	OFFSET(__CLOCK_IDLE_ENTER, s390_idle_data, clock_idle_enter);
 	OFFSET(__CLOCK_IDLE_EXIT, s390_idle_data, clock_idle_exit);
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index ebfe86d097f0..390d97daa2b3 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -855,13 +855,14 @@ void __init smp_detect_cpus(void)
 
 static void smp_init_secondary(void)
 {
-	int cpu = smp_processor_id();
+	int cpu = raw_smp_processor_id();
 
 	S390_lowcore.last_update_clock = get_tod_clock();
 	restore_access_regs(S390_lowcore.access_regs_save_area);
 	set_cpu_flag(CIF_ASCE_PRIMARY);
 	set_cpu_flag(CIF_ASCE_SECONDARY);
 	cpu_init();
+	rcu_cpu_starting(cpu);
 	preempt_disable();
 	init_cpu_timer();
 	vtime_init();
diff --git a/arch/s390/pci/pci_event.c b/arch/s390/pci/pci_event.c
index d33f21545dfd..9a6bae503fe6 100644
--- a/arch/s390/pci/pci_event.c
+++ b/arch/s390/pci/pci_event.c
@@ -101,6 +101,10 @@ static void __zpci_event_availability(struct zpci_ccdf_avail *ccdf)
 		if (ret)
 			break;
 
+		/* the PCI function will be scanned once function 0 appears */
+		if (!zdev->zbus->bus)
+			break;
+
 		pdev = pci_scan_single_device(zdev->zbus->bus, zdev->devfn);
 		if (!pdev)
 			break;
diff --git a/arch/x86/boot/compressed/ident_map_64.c b/arch/x86/boot/compressed/ident_map_64.c
index a5e5db6ada3c..39b2eded7bc2 100644
--- a/arch/x86/boot/compressed/ident_map_64.c
+++ b/arch/x86/boot/compressed/ident_map_64.c
@@ -164,6 +164,7 @@ void initialize_identity_maps(void *rmode)
 	add_identity_map(cmdline, cmdline + COMMAND_LINE_SIZE);
 
 	/* Load the new page-table. */
+	sev_verify_cbit(top_level_pgt);
 	write_cr3(top_level_pgt);
 }
 
diff --git a/arch/x86/boot/compressed/mem_encrypt.S b/arch/x86/boot/compressed/mem_encrypt.S
index dd07e7b41b11..aa561795efd1 100644
--- a/arch/x86/boot/compressed/mem_encrypt.S
+++ b/arch/x86/boot/compressed/mem_encrypt.S
@@ -68,6 +68,9 @@ SYM_FUNC_START(get_sev_encryption_bit)
 SYM_FUNC_END(get_sev_encryption_bit)
 
 	.code64
+
+#include "../../kernel/sev_verify_cbit.S"
+
 SYM_FUNC_START(set_sev_encryption_mask)
 #ifdef CONFIG_AMD_MEM_ENCRYPT
 	push	%rbp
@@ -81,6 +84,19 @@ SYM_FUNC_START(set_sev_encryption_mask)
 
 	bts	%rax, sme_me_mask(%rip)	/* Create the encryption mask */
 
+	/*
+	 * Read MSR_AMD64_SEV again and store it to sev_status. Can't do this in
+	 * get_sev_encryption_bit() because this function is 32-bit code and
+	 * shared between 64-bit and 32-bit boot path.
+	 */
+	movl	$MSR_AMD64_SEV, %ecx	/* Read the SEV MSR */
+	rdmsr
+
+	/* Store MSR value in sev_status */
+	shlq	$32, %rdx
+	orq	%rdx, %rax
+	movq	%rax, sev_status(%rip)
+
 .Lno_sev_mask:
 	movq	%rbp, %rsp		/* Restore original stack pointer */
 
@@ -96,5 +112,7 @@ SYM_FUNC_END(set_sev_encryption_mask)
 
 #ifdef CONFIG_AMD_MEM_ENCRYPT
 	.balign	8
-SYM_DATA(sme_me_mask, .quad 0)
+SYM_DATA(sme_me_mask,		.quad 0)
+SYM_DATA(sev_status,		.quad 0)
+SYM_DATA(sev_check_data,	.quad 0)
 #endif
diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h
index 6d31f1b4c4d1..d9a631c5973c 100644
--- a/arch/x86/boot/compressed/misc.h
+++ b/arch/x86/boot/compressed/misc.h
@@ -159,4 +159,6 @@ void boot_page_fault(void);
 void boot_stage1_vc(void);
 void boot_stage2_vc(void);
 
+unsigned long sev_verify_cbit(unsigned long cr3);
+
 #endif /* BOOT_COMPRESSED_MISC_H */
diff --git a/arch/x86/hyperv/hv_apic.c b/arch/x86/hyperv/hv_apic.c
index 40e0e322161d..284e73661a18 100644
--- a/arch/x86/hyperv/hv_apic.c
+++ b/arch/x86/hyperv/hv_apic.c
@@ -273,11 +273,15 @@ void __init hv_apic_init(void)
 		pr_info("Hyper-V: Using enlightened APIC (%s mode)",
 			x2apic_enabled() ? "x2apic" : "xapic");
 		/*
-		 * With x2apic, architectural x2apic MSRs are equivalent to the
-		 * respective synthetic MSRs, so there's no need to override
-		 * the apic accessors.  The only exception is
-		 * hv_apic_eoi_write, because it benefits from lazy EOI when
-		 * available, but it works for both xapic and x2apic modes.
+		 * When in x2apic mode, don't use the Hyper-V specific APIC
+		 * accessors since the field layout in the ICR register is
+		 * different in x2apic mode. Furthermore, the architectural
+		 * x2apic MSRs function just as well as the Hyper-V
+		 * synthetic APIC MSRs, so there's no benefit in having
+		 * separate Hyper-V accessors for x2apic mode. The only
+		 * exception is hv_apic_eoi_write, because it benefits from
+		 * lazy EOI when available, but the same accessor works for
+		 * both xapic and x2apic because the field layout is the same.
 		 */
 		apic_set_eoi_write(hv_apic_eoi_write);
 		if (!x2apic_enabled()) {
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 714233cee0b5..3115caa7d7d0 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -290,6 +290,9 @@ static void __init uv_stringify(int len, char *to, char *from)
 {
 	/* Relies on 'to' being NULL chars so result will be NULL terminated */
 	strncpy(to, from, len-1);
+
+	/* Trim trailing spaces */
+	(void)strim(to);
 }
 
 /* Find UV arch type entry in UVsystab */
@@ -366,7 +369,7 @@ static int __init early_get_arch_type(void)
 	return ret;
 }
 
-static int __init uv_set_system_type(char *_oem_id)
+static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id)
 {
 	/* Save OEM_ID passed from ACPI MADT */
 	uv_stringify(sizeof(oem_id), oem_id, _oem_id);
@@ -386,13 +389,23 @@ static int __init uv_set_system_type(char *_oem_id)
 			/* (Not hubless), not a UV */
 			return 0;
 
+		/* Is UV hubless system */
+		uv_hubless_system = 0x01;
+
+		/* UV5 Hubless */
+		if (strncmp(uv_archtype, "NSGI5", 5) == 0)
+			uv_hubless_system |= 0x20;
+
 		/* UV4 Hubless: CH */
-		if (strncmp(uv_archtype, "NSGI4", 5) == 0)
-			uv_hubless_system = 0x11;
+		else if (strncmp(uv_archtype, "NSGI4", 5) == 0)
+			uv_hubless_system |= 0x10;
 
 		/* UV3 Hubless: UV300/MC990X w/o hub */
 		else
-			uv_hubless_system = 0x9;
+			uv_hubless_system |= 0x8;
+
+		/* Copy APIC type */
+		uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
 
 		pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n",
 			oem_id, oem_table_id, uv_system_type, uv_hubless_system);
@@ -456,7 +469,7 @@ static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
 	uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
 
 	/* If not UV, return. */
-	if (likely(uv_set_system_type(_oem_id) == 0))
+	if (uv_set_system_type(_oem_id, _oem_table_id) == 0)
 		return 0;
 
 	/* Save and Decode OEM Table ID */
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index d3f0db463f96..581fb7223ad0 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -1254,6 +1254,14 @@ static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
 	return 0;
 }
 
+static bool is_spec_ib_user_controlled(void)
+{
+	return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
+		spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
+		spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
+		spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
+}
+
 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
 {
 	switch (ctrl) {
@@ -1261,16 +1269,26 @@ static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
 		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
 		    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
 			return 0;
+
 		/*
-		 * Indirect branch speculation is always disabled in strict
-		 * mode. It can neither be enabled if it was force-disabled
-		 * by a  previous prctl call.
+		 * With strict mode for both IBPB and STIBP, the instruction
+		 * code paths avoid checking this task flag and instead,
+		 * unconditionally run the instruction. However, STIBP and IBPB
+		 * are independent and either can be set to conditionally
+		 * enabled regardless of the mode of the other.
+		 *
+		 * If either is set to conditional, allow the task flag to be
+		 * updated, unless it was force-disabled by a previous prctl
+		 * call. Currently, this is possible on an AMD CPU which has the
+		 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
+		 * kernel is booted with 'spectre_v2_user=seccomp', then
+		 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
+		 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
 		 */
-		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
-		    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
-		    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ||
+		if (!is_spec_ib_user_controlled() ||
 		    task_spec_ib_force_disable(task))
 			return -EPERM;
+
 		task_clear_spec_ib_disable(task);
 		task_update_spec_tif(task);
 		break;
@@ -1283,10 +1301,10 @@ static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
 		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
 		    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
 			return -EPERM;
-		if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
-		    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
-		    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
+
+		if (!is_spec_ib_user_controlled())
 			return 0;
+
 		task_set_spec_ib_disable(task);
 		if (ctrl == PR_SPEC_FORCE_DISABLE)
 			task_set_spec_ib_force_disable(task);
@@ -1351,20 +1369,17 @@ static int ib_prctl_get(struct task_struct *task)
 	if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
 	    spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
 		return PR_SPEC_ENABLE;
-	else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
-	    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
-	    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
-		return PR_SPEC_DISABLE;
-	else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
-	    spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
-	    spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
-	    spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP) {
+	else if (is_spec_ib_user_controlled()) {
 		if (task_spec_ib_force_disable(task))
 			return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
 		if (task_spec_ib_disable(task))
 			return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
 		return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
-	} else
+	} else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
+	    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
+	    spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
+		return PR_SPEC_DISABLE;
+	else
 		return PR_SPEC_NOT_AFFECTED;
 }
 
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 7eb2a1c87969..3c417734790f 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -161,6 +161,21 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
 
 	/* Setup early boot stage 4-/5-level pagetables. */
 	addq	phys_base(%rip), %rax
+
+	/*
+	 * For SEV guests: Verify that the C-bit is correct. A malicious
+	 * hypervisor could lie about the C-bit position to perform a ROP
+	 * attack on the guest by writing to the unencrypted stack and wait for
+	 * the next RET instruction.
+	 * %rsi carries pointer to realmode data and is callee-clobbered. Save
+	 * and restore it.
+	 */
+	pushq	%rsi
+	movq	%rax, %rdi
+	call	sev_verify_cbit
+	popq	%rsi
+
+	/* Switch to new page-table */
 	movq	%rax, %cr3
 
 	/* Ensure I am executing from virtual addresses */
@@ -279,6 +294,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
 SYM_CODE_END(secondary_startup_64)
 
 #include "verify_cpu.S"
+#include "sev_verify_cbit.S"
 
 #ifdef CONFIG_HOTPLUG_CPU
 /*
diff --git a/arch/x86/kernel/sev-es-shared.c b/arch/x86/kernel/sev-es-shared.c
index 5f83ccaab877..7d04b356d44d 100644
--- a/arch/x86/kernel/sev-es-shared.c
+++ b/arch/x86/kernel/sev-es-shared.c
@@ -178,6 +178,32 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code)
 		goto fail;
 	regs->dx = val >> 32;
 
+	/*
+	 * This is a VC handler and the #VC is only raised when SEV-ES is
+	 * active, which means SEV must be active too. Do sanity checks on the
+	 * CPUID results to make sure the hypervisor does not trick the kernel
+	 * into the no-sev path. This could map sensitive data unencrypted and
+	 * make it accessible to the hypervisor.
+	 *
+	 * In particular, check for:
+	 *	- Hypervisor CPUID bit
+	 *	- Availability of CPUID leaf 0x8000001f
+	 *	- SEV CPUID bit.
+	 *
+	 * The hypervisor might still report the wrong C-bit position, but this
+	 * can't be checked here.
+	 */
+
+	if ((fn == 1 && !(regs->cx & BIT(31))))
+		/* Hypervisor bit */
+		goto fail;
+	else if (fn == 0x80000000 && (regs->ax < 0x8000001f))
+		/* SEV leaf check */
+		goto fail;
+	else if ((fn == 0x8000001f && !(regs->ax & BIT(1))))
+		/* SEV bit */
+		goto fail;
+
 	/* Skip over the CPUID two-byte opcode */
 	regs->ip += 2;
 
diff --git a/arch/x86/kernel/sev-es.c b/arch/x86/kernel/sev-es.c
index 4a96726fbaf8..0bd1a0fc587e 100644
--- a/arch/x86/kernel/sev-es.c
+++ b/arch/x86/kernel/sev-es.c
@@ -374,8 +374,8 @@ fault:
 	return ES_EXCEPTION;
 }
 
-static bool vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
-				 unsigned long vaddr, phys_addr_t *paddr)
+static enum es_result vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
+					   unsigned long vaddr, phys_addr_t *paddr)
 {
 	unsigned long va = (unsigned long)vaddr;
 	unsigned int level;
@@ -394,15 +394,19 @@ static bool vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
 		if (user_mode(ctxt->regs))
 			ctxt->fi.error_code |= X86_PF_USER;
 
-		return false;
+		return ES_EXCEPTION;
 	}
 
+	if (WARN_ON_ONCE(pte_val(*pte) & _PAGE_ENC))
+		/* Emulated MMIO to/from encrypted memory not supported */
+		return ES_UNSUPPORTED;
+
 	pa = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT;
 	pa |= va & ~page_level_mask(level);
 
 	*paddr = pa;
 
-	return true;
+	return ES_OK;
 }
 
 /* Include code shared with pre-decompression boot stage */
@@ -731,6 +735,7 @@ static enum es_result vc_do_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
 {
 	u64 exit_code, exit_info_1, exit_info_2;
 	unsigned long ghcb_pa = __pa(ghcb);
+	enum es_result res;
 	phys_addr_t paddr;
 	void __user *ref;
 
@@ -740,11 +745,12 @@ static enum es_result vc_do_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
 
 	exit_code = read ? SVM_VMGEXIT_MMIO_READ : SVM_VMGEXIT_MMIO_WRITE;
 
-	if (!vc_slow_virt_to_phys(ghcb, ctxt, (unsigned long)ref, &paddr)) {
-		if (!read)
+	res = vc_slow_virt_to_phys(ghcb, ctxt, (unsigned long)ref, &paddr);
+	if (res != ES_OK) {
+		if (res == ES_EXCEPTION && !read)
 			ctxt->fi.error_code |= X86_PF_WRITE;
 
-		return ES_EXCEPTION;
+		return res;
 	}
 
 	exit_info_1 = paddr;
diff --git a/arch/x86/kernel/sev_verify_cbit.S b/arch/x86/kernel/sev_verify_cbit.S
new file mode 100644
index 000000000000..ee04941a6546
--- /dev/null
+++ b/arch/x86/kernel/sev_verify_cbit.S
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ *	sev_verify_cbit.S - Code for verification of the C-bit position reported
+ *			    by the Hypervisor when running with SEV enabled.
+ *
+ *	Copyright (c) 2020  Joerg Roedel (jroedel@suse.de)
+ *
+ * sev_verify_cbit() is called before switching to a new long-mode page-table
+ * at boot.
+ *
+ * Verify that the C-bit position is correct by writing a random value to
+ * an encrypted memory location while on the current page-table. Then it
+ * switches to the new page-table to verify the memory content is still the
+ * same. After that it switches back to the current page-table and when the
+ * check succeeded it returns. If the check failed the code invalidates the
+ * stack pointer and goes into a hlt loop. The stack-pointer is invalidated to
+ * make sure no interrupt or exception can get the CPU out of the hlt loop.
+ *
+ * New page-table pointer is expected in %rdi (first parameter)
+ *
+ */
+SYM_FUNC_START(sev_verify_cbit)
+#ifdef CONFIG_AMD_MEM_ENCRYPT
+	/* First check if a C-bit was detected */
+	movq	sme_me_mask(%rip), %rsi
+	testq	%rsi, %rsi
+	jz	3f
+
+	/* sme_me_mask != 0 could mean SME or SEV - Check also for SEV */
+	movq	sev_status(%rip), %rsi
+	testq	%rsi, %rsi
+	jz	3f
+
+	/* Save CR4 in %rsi */
+	movq	%cr4, %rsi
+
+	/* Disable Global Pages */
+	movq	%rsi, %rdx
+	andq	$(~X86_CR4_PGE), %rdx
+	movq	%rdx, %cr4
+
+	/*
+	 * Verified that running under SEV - now get a random value using
+	 * RDRAND. This instruction is mandatory when running as an SEV guest.
+	 *
+	 * Don't bail out of the loop if RDRAND returns errors. It is better to
+	 * prevent forward progress than to work with a non-random value here.
+	 */
+1:	rdrand	%rdx
+	jnc	1b
+
+	/* Store value to memory and keep it in %rdx */
+	movq	%rdx, sev_check_data(%rip)
+
+	/* Backup current %cr3 value to restore it later */
+	movq	%cr3, %rcx
+
+	/* Switch to new %cr3 - This might unmap the stack */
+	movq	%rdi, %cr3
+
+	/*
+	 * Compare value in %rdx with memory location. If C-bit is incorrect
+	 * this would read the encrypted data and make the check fail.
+	 */
+	cmpq	%rdx, sev_check_data(%rip)
+
+	/* Restore old %cr3 */
+	movq	%rcx, %cr3
+
+	/* Restore previous CR4 */
+	movq	%rsi, %cr4
+
+	/* Check CMPQ result */
+	je	3f
+
+	/*
+	 * The check failed, prevent any forward progress to prevent ROP
+	 * attacks, invalidate the stack and go into a hlt loop.
+	 */
+	xorq	%rsp, %rsp
+	subq	$0x1000, %rsp
+2:	hlt
+	jmp 2b
+3:
+#endif
+	/* Return page-table pointer */
+	movq	%rdi, %rax
+	ret
+SYM_FUNC_END(sev_verify_cbit)
diff --git a/arch/x86/lib/memcpy_64.S b/arch/x86/lib/memcpy_64.S
index 037faac46b0c..1e299ac73c86 100644
--- a/arch/x86/lib/memcpy_64.S
+++ b/arch/x86/lib/memcpy_64.S
@@ -16,8 +16,6 @@
  * to a jmp to memcpy_erms which does the REP; MOVSB mem copy.
  */
 
-.weak memcpy
-
 /*
  * memcpy - Copy a memory block.
  *
@@ -30,7 +28,7 @@
  * rax original destination
  */
 SYM_FUNC_START_ALIAS(__memcpy)
-SYM_FUNC_START_LOCAL(memcpy)
+SYM_FUNC_START_WEAK(memcpy)
 	ALTERNATIVE_2 "jmp memcpy_orig", "", X86_FEATURE_REP_GOOD, \
 		      "jmp memcpy_erms", X86_FEATURE_ERMS
 
diff --git a/arch/x86/lib/memmove_64.S b/arch/x86/lib/memmove_64.S
index 7ff00ea64e4f..41902fe8b859 100644
--- a/arch/x86/lib/memmove_64.S
+++ b/arch/x86/lib/memmove_64.S
@@ -24,9 +24,7 @@
  * Output:
  * rax: dest
  */
-.weak memmove
-
-SYM_FUNC_START_ALIAS(memmove)
+SYM_FUNC_START_WEAK(memmove)
 SYM_FUNC_START(__memmove)
 
 	mov %rdi, %rax
diff --git a/arch/x86/lib/memset_64.S b/arch/x86/lib/memset_64.S
index 9ff15ee404a4..0bfd26e4ca9e 100644
--- a/arch/x86/lib/memset_64.S
+++ b/arch/x86/lib/memset_64.S
@@ -6,8 +6,6 @@
 #include <asm/alternative-asm.h>
 #include <asm/export.h>
 
-.weak memset
-
 /*
  * ISO C memset - set a memory block to a byte value. This function uses fast
  * string to get better performance than the original function. The code is
@@ -19,7 +17,7 @@
  *
  * rax   original destination
  */
-SYM_FUNC_START_ALIAS(memset)
+SYM_FUNC_START_WEAK(memset)
 SYM_FUNC_START(__memset)
 	/*
 	 * Some CPUs support enhanced REP MOVSB/STOSB feature. It is recommended
diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c
index efbb3de472df..bc0833713be9 100644
--- a/arch/x86/mm/mem_encrypt.c
+++ b/arch/x86/mm/mem_encrypt.c
@@ -39,6 +39,7 @@
  */
 u64 sme_me_mask __section(".data") = 0;
 u64 sev_status __section(".data") = 0;
+u64 sev_check_data __section(".data") = 0;
 EXPORT_SYMBOL(sme_me_mask);
 DEFINE_STATIC_KEY_FALSE(sev_enable_key);
 EXPORT_SYMBOL_GPL(sev_enable_key);
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index c6fc83efee0c..8731b7ad9308 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -89,8 +89,8 @@ static void __init free_highpages(void)
 	/* set highmem page free */
 	for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE,
 				&range_start, &range_end, NULL) {
-		unsigned long start = PHYS_PFN(range_start);
-		unsigned long end = PHYS_PFN(range_end);
+		unsigned long start = PFN_UP(range_start);
+		unsigned long end = PFN_DOWN(range_end);
 
 		/* Ignore complete lowmem entries */
 		if (end <= max_low)
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 78114ddac755..d661ada1518f 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -773,8 +773,7 @@ static void __device_link_del(struct kref *kref)
 	dev_dbg(link->consumer, "Dropping the link to %s\n",
 		dev_name(link->supplier));
 
-	if (link->flags & DL_FLAG_PM_RUNTIME)
-		pm_runtime_drop_link(link->consumer);
+	pm_runtime_drop_link(link);
 
 	list_del_rcu(&link->s_node);
 	list_del_rcu(&link->c_node);
@@ -788,8 +787,7 @@ static void __device_link_del(struct kref *kref)
 	dev_info(link->consumer, "Dropping the link to %s\n",
 		 dev_name(link->supplier));
 
-	if (link->flags & DL_FLAG_PM_RUNTIME)
-		pm_runtime_drop_link(link->consumer);
+	pm_runtime_drop_link(link);
 
 	list_del(&link->s_node);
 	list_del(&link->c_node);
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index b42229b74fd6..148e81969e04 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -1117,6 +1117,8 @@ static void __device_release_driver(struct device *dev, struct device *parent)
 
 	drv = dev->driver;
 	if (drv) {
+		pm_runtime_get_sync(dev);
+
 		while (device_links_busy(dev)) {
 			__device_driver_unlock(dev, parent);
 
@@ -1128,13 +1130,12 @@ static void __device_release_driver(struct device *dev, struct device *parent)
 			 * have released the driver successfully while this one
 			 * was waiting, so check for that.
 			 */
-			if (dev->driver != drv)
+			if (dev->driver != drv) {
+				pm_runtime_put(dev);
 				return;
+			}
 		}
 
-		pm_runtime_get_sync(dev);
-		pm_runtime_clean_up_links(dev);
-
 		driver_sysfs_remove(dev);
 
 		if (dev->bus)
diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c
index 6f605f7820bb..bfda153b1a41 100644
--- a/drivers/base/power/runtime.c
+++ b/drivers/base/power/runtime.c
@@ -1643,42 +1643,6 @@ void pm_runtime_remove(struct device *dev)
 }
 
 /**
- * pm_runtime_clean_up_links - Prepare links to consumers for driver removal.
- * @dev: Device whose driver is going to be removed.
- *
- * Check links from this device to any consumers and if any of them have active
- * runtime PM references to the device, drop the usage counter of the device
- * (as many times as needed).
- *
- * Links with the DL_FLAG_MANAGED flag unset are ignored.
- *
- * Since the device is guaranteed to be runtime-active at the point this is
- * called, nothing else needs to be done here.
- *
- * Moreover, this is called after device_links_busy() has returned 'false', so
- * the status of each link is guaranteed to be DL_STATE_SUPPLIER_UNBIND and
- * therefore rpm_active can't be manipulated concurrently.
- */
-void pm_runtime_clean_up_links(struct device *dev)
-{
-	struct device_link *link;
-	int idx;
-
-	idx = device_links_read_lock();
-
-	list_for_each_entry_rcu(link, &dev->links.consumers, s_node,
-				device_links_read_lock_held()) {
-		if (!(link->flags & DL_FLAG_MANAGED))
-			continue;
-
-		while (refcount_dec_not_one(&link->rpm_active))
-			pm_runtime_put_noidle(dev);
-	}
-
-	device_links_read_unlock(idx);
-}
-
-/**
  * pm_runtime_get_suppliers - Resume and reference-count supplier devices.
  * @dev: Consumer device.
  */
@@ -1729,7 +1693,7 @@ void pm_runtime_new_link(struct device *dev)
 	spin_unlock_irq(&dev->power.lock);
 }
 
-void pm_runtime_drop_link(struct device *dev)
+static void pm_runtime_drop_link_count(struct device *dev)
 {
 	spin_lock_irq(&dev->power.lock);
 	WARN_ON(dev->power.links_count == 0);
@@ -1737,6 +1701,25 @@ void pm_runtime_drop_link(struct device *dev)
 	spin_unlock_irq(&dev->power.lock);
 }
 
+/**
+ * pm_runtime_drop_link - Prepare for device link removal.
+ * @link: Device link going away.
+ *
+ * Drop the link count of the consumer end of @link and decrement the supplier
+ * device's runtime PM usage counter as many times as needed to drop all of the
+ * PM runtime reference to it from the consumer.
+ */
+void pm_runtime_drop_link(struct device_link *link)
+{
+	if (!(link->flags & DL_FLAG_PM_RUNTIME))
+		return;
+
+	pm_runtime_drop_link_count(link->consumer);
+
+	while (refcount_dec_not_one(&link->rpm_active))
+		pm_runtime_put(link->supplier);
+}
+
 static bool pm_runtime_need_not_resume(struct device *dev)
 {
 	return atomic_read(&dev->power.usage_count) <= 1 &&
diff --git a/drivers/block/null_blk.h b/drivers/block/null_blk.h
index cfd00ad40355..c24d9b5ad81a 100644
--- a/drivers/block/null_blk.h
+++ b/drivers/block/null_blk.h
@@ -47,7 +47,7 @@ struct nullb_device {
 	unsigned int nr_zones_closed;
 	struct blk_zone *zones;
 	sector_t zone_size_sects;
-	spinlock_t zone_dev_lock;
+	spinlock_t zone_lock;
 	unsigned long *zone_locks;
 
 	unsigned long size; /* device size in MB */
diff --git a/drivers/block/null_blk_zoned.c b/drivers/block/null_blk_zoned.c
index 8775acbb4f8f..beb34b4f76b0 100644
--- a/drivers/block/null_blk_zoned.c
+++ b/drivers/block/null_blk_zoned.c
@@ -46,11 +46,20 @@ int null_init_zoned_dev(struct nullb_device *dev, struct request_queue *q)
 	if (!dev->zones)
 		return -ENOMEM;
 
-	spin_lock_init(&dev->zone_dev_lock);
-	dev->zone_locks = bitmap_zalloc(dev->nr_zones, GFP_KERNEL);
-	if (!dev->zone_locks) {
-		kvfree(dev->zones);
-		return -ENOMEM;
+	/*
+	 * With memory backing, the zone_lock spinlock needs to be temporarily
+	 * released to avoid scheduling in atomic context. To guarantee zone
+	 * information protection, use a bitmap to lock zones with
+	 * wait_on_bit_lock_io(). Sleeping on the lock is OK as memory backing
+	 * implies that the queue is marked with BLK_MQ_F_BLOCKING.
+	 */
+	spin_lock_init(&dev->zone_lock);
+	if (dev->memory_backed) {
+		dev->zone_locks = bitmap_zalloc(dev->nr_zones, GFP_KERNEL);
+		if (!dev->zone_locks) {
+			kvfree(dev->zones);
+			return -ENOMEM;
+		}
 	}
 
 	if (dev->zone_nr_conv >= dev->nr_zones) {
@@ -137,12 +146,17 @@ void null_free_zoned_dev(struct nullb_device *dev)
 
 static inline void null_lock_zone(struct nullb_device *dev, unsigned int zno)
 {
-	wait_on_bit_lock_io(dev->zone_locks, zno, TASK_UNINTERRUPTIBLE);
+	if (dev->memory_backed)
+		wait_on_bit_lock_io(dev->zone_locks, zno, TASK_UNINTERRUPTIBLE);
+	spin_lock_irq(&dev->zone_lock);
 }
 
 static inline void null_unlock_zone(struct nullb_device *dev, unsigned int zno)
 {
-	clear_and_wake_up_bit(zno, dev->zone_locks);
+	spin_unlock_irq(&dev->zone_lock);
+
+	if (dev->memory_backed)
+		clear_and_wake_up_bit(zno, dev->zone_locks);
 }
 
 int null_report_zones(struct gendisk *disk, sector_t sector,
@@ -322,7 +336,6 @@ static blk_status_t null_zone_write(struct nullb_cmd *cmd, sector_t sector,
 		return null_process_cmd(cmd, REQ_OP_WRITE, sector, nr_sectors);
 
 	null_lock_zone(dev, zno);
-	spin_lock(&dev->zone_dev_lock);
 
 	switch (zone->cond) {
 	case BLK_ZONE_COND_FULL:
@@ -375,9 +388,17 @@ static blk_status_t null_zone_write(struct nullb_cmd *cmd, sector_t sector,
 	if (zone->cond != BLK_ZONE_COND_EXP_OPEN)
 		zone->cond = BLK_ZONE_COND_IMP_OPEN;
 
-	spin_unlock(&dev->zone_dev_lock);
+	/*
+	 * Memory backing allocation may sleep: release the zone_lock spinlock
+	 * to avoid scheduling in atomic context. Zone operation atomicity is
+	 * still guaranteed through the zone_locks bitmap.
+	 */
+	if (dev->memory_backed)
+		spin_unlock_irq(&dev->zone_lock);
 	ret = null_process_cmd(cmd, REQ_OP_WRITE, sector, nr_sectors);
-	spin_lock(&dev->zone_dev_lock);
+	if (dev->memory_backed)
+		spin_lock_irq(&dev->zone_lock);
+
 	if (ret != BLK_STS_OK)
 		goto unlock;
 
@@ -392,7 +413,6 @@ static blk_status_t null_zone_write(struct nullb_cmd *cmd, sector_t sector,
 	ret = BLK_STS_OK;
 
 unlock:
-	spin_unlock(&dev->zone_dev_lock);
 	null_unlock_zone(dev, zno);
 
 	return ret;
@@ -516,9 +536,7 @@ static blk_status_t null_zone_mgmt(struct nullb_cmd *cmd, enum req_opf op,
 			null_lock_zone(dev, i);
 			zone = &dev->zones[i];
 			if (zone->cond != BLK_ZONE_COND_EMPTY) {
-				spin_lock(&dev->zone_dev_lock);
 				null_reset_zone(dev, zone);
-				spin_unlock(&dev->zone_dev_lock);
 				trace_nullb_zone_op(cmd, i, zone->cond);
 			}
 			null_unlock_zone(dev, i);
@@ -530,7 +548,6 @@ static blk_status_t null_zone_mgmt(struct nullb_cmd *cmd, enum req_opf op,
 	zone = &dev->zones[zone_no];
 
 	null_lock_zone(dev, zone_no);
-	spin_lock(&dev->zone_dev_lock);
 
 	switch (op) {
 	case REQ_OP_ZONE_RESET:
@@ -550,8 +567,6 @@ static blk_status_t null_zone_mgmt(struct nullb_cmd *cmd, enum req_opf op,
 		break;
 	}
 
-	spin_unlock(&dev->zone_dev_lock);
-
 	if (ret == BLK_STS_OK)
 		trace_nullb_zone_op(cmd, zone_no, zone->cond);
 
diff --git a/drivers/char/tpm/eventlog/efi.c b/drivers/char/tpm/eventlog/efi.c
index 6bb023de17f1..35229e5143ca 100644
--- a/drivers/char/tpm/eventlog/efi.c
+++ b/drivers/char/tpm/eventlog/efi.c
@@ -41,6 +41,11 @@ int tpm_read_log_efi(struct tpm_chip *chip)
 	log_size = log_tbl->size;
 	memunmap(log_tbl);
 
+	if (!log_size) {
+		pr_warn("UEFI TPM log area empty\n");
+		return -EIO;
+	}
+
 	log_tbl = memremap(efi.tpm_log, sizeof(*log_tbl) + log_size,
 			   MEMREMAP_WB);
 	if (!log_tbl) {
diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c
index 0b214963539d..4ed6e660273a 100644
--- a/drivers/char/tpm/tpm_tis.c
+++ b/drivers/char/tpm/tpm_tis.c
@@ -27,6 +27,7 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/kernel.h>
+#include <linux/dmi.h>
 #include "tpm.h"
 #include "tpm_tis_core.h"
 
@@ -49,8 +50,8 @@ static inline struct tpm_tis_tcg_phy *to_tpm_tis_tcg_phy(struct tpm_tis_data *da
 	return container_of(data, struct tpm_tis_tcg_phy, priv);
 }
 
-static bool interrupts = true;
-module_param(interrupts, bool, 0444);
+static int interrupts = -1;
+module_param(interrupts, int, 0444);
 MODULE_PARM_DESC(interrupts, "Enable interrupts");
 
 static bool itpm;
@@ -63,6 +64,28 @@ module_param(force, bool, 0444);
 MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry");
 #endif
 
+static int tpm_tis_disable_irq(const struct dmi_system_id *d)
+{
+	if (interrupts == -1) {
+		pr_notice("tpm_tis: %s detected: disabling interrupts.\n", d->ident);
+		interrupts = 0;
+	}
+
+	return 0;
+}
+
+static const struct dmi_system_id tpm_tis_dmi_table[] = {
+	{
+		.callback = tpm_tis_disable_irq,
+		.ident = "ThinkPad T490s",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+			DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T490s"),
+		},
+	},
+	{}
+};
+
 #if defined(CONFIG_PNP) && defined(CONFIG_ACPI)
 static int has_hid(struct acpi_device *dev, const char *hid)
 {
@@ -192,6 +215,8 @@ static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info)
 	int irq = -1;
 	int rc;
 
+	dmi_check_system(tpm_tis_dmi_table);
+
 	rc = check_acpi_tpm2(dev);
 	if (rc)
 		return rc;
diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c
index fa2f1b4fad7b..a94bf28f858a 100644
--- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c
+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-hash.c
@@ -7,7 +7,7 @@
  *
  * This file add support for MD5 and SHA1/SHA224/SHA256/SHA384/SHA512.
  *
- * You could find the datasheet in Documentation/arm/sunxi/README
+ * You could find the datasheet in Documentation/arm/sunxi.rst
  */
 #include <linux/dma-mapping.h>
 #include <linux/pm_runtime.h>
diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c
index 78503006949c..cfde9ee4356b 100644
--- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c
+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c
@@ -7,7 +7,7 @@
  *
  * This file handle the PRNG
  *
- * You could find a link for the datasheet in Documentation/arm/sunxi/README
+ * You could find a link for the datasheet in Documentation/arm/sunxi.rst
  */
 #include "sun8i-ce.h"
 #include <linux/dma-mapping.h>
diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-trng.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-trng.c
index 654328160d19..5b7af4498bd5 100644
--- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-trng.c
+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-trng.c
@@ -7,7 +7,7 @@
  *
  * This file handle the TRNG
  *
- * You could find a link for the datasheet in Documentation/arm/sunxi/README
+ * You could find a link for the datasheet in Documentation/arm/sunxi.rst
  */
 #include "sun8i-ce.h"
 #include <linux/dma-mapping.h>
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 39976c7b100c..6fde9a9d5e2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -55,7 +55,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
 	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
 	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
 	amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \
-	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o
+	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \
+	amdgpu_fw_attestation.o
 
 amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
 
@@ -69,7 +70,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce
 amdgpu-y += \
 	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
 	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
-	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o
+	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \
+	nbio_v7_2.o dimgrey_cavefish_reg_init.o
 
 # add DF block
 amdgpu-y += \
@@ -81,7 +83,7 @@ amdgpu-y += \
 	gmc_v7_0.o \
 	gmc_v8_0.o \
 	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
-	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o
+	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o
 
 # add UMC block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 87f095dc385c..183b09d71b64 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -623,6 +623,8 @@ struct amdgpu_asic_funcs {
 	bool (*supports_baco)(struct amdgpu_device *adev);
 	/* pre asic_init quirks */
 	void (*pre_asic_init)(struct amdgpu_device *adev);
+	/* enter/exit umd stable pstate */
+	int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
 };
 
 /*
@@ -723,6 +725,45 @@ struct amd_powerplay {
 	const struct amd_pm_funcs *pp_funcs;
 };
 
+/* polaris10 kickers */
+#define ASICID_IS_P20(did, rid)		(((did == 0x67DF) && \
+					 ((rid == 0xE3) || \
+					  (rid == 0xE4) || \
+					  (rid == 0xE5) || \
+					  (rid == 0xE7) || \
+					  (rid == 0xEF))) || \
+					 ((did == 0x6FDF) && \
+					 ((rid == 0xE7) || \
+					  (rid == 0xEF) || \
+					  (rid == 0xFF))))
+
+#define ASICID_IS_P30(did, rid)		((did == 0x67DF) && \
+					((rid == 0xE1) || \
+					 (rid == 0xF7)))
+
+/* polaris11 kickers */
+#define ASICID_IS_P21(did, rid)		(((did == 0x67EF) && \
+					 ((rid == 0xE0) || \
+					  (rid == 0xE5))) || \
+					 ((did == 0x67FF) && \
+					 ((rid == 0xCF) || \
+					  (rid == 0xEF) || \
+					  (rid == 0xFF))))
+
+#define ASICID_IS_P31(did, rid)		((did == 0x67EF) && \
+					((rid == 0xE2)))
+
+/* polaris12 kickers */
+#define ASICID_IS_P23(did, rid)		(((did == 0x6987) && \
+					 ((rid == 0xC0) || \
+					  (rid == 0xC1) || \
+					  (rid == 0xC3) || \
+					  (rid == 0xC7))) || \
+					 ((did == 0x6981) && \
+					 ((rid == 0x00) || \
+					  (rid == 0x01) || \
+					  (rid == 0x10))))
+
 #define AMDGPU_RESET_MAGIC_NUM 64
 #define AMDGPU_MAX_DF_PERFMONS 4
 struct amdgpu_device {
@@ -1165,6 +1206,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
+#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
+	((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
 
 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
 
@@ -1294,19 +1337,6 @@ bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
 
 #include "amdgpu_object.h"
 
-/* used by df_v3_6.c and amdgpu_pmu.c */
-#define AMDGPU_PMU_ATTR(_name, _object)					\
-static ssize_t								\
-_name##_show(struct device *dev,					\
-			       struct device_attribute *attr,		\
-			       char *page)				\
-{									\
-	BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1);			\
-	return sprintf(page, _object "\n");				\
-}									\
-									\
-static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
-
 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
 {
        return adev->gmc.tmz_enabled;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index d3e51d361179..1400957034a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -36,17 +36,17 @@
 
 #include "acp_gfx_if.h"
 
-#define ACP_TILE_ON_MASK                	0x03
-#define ACP_TILE_OFF_MASK               	0x02
-#define ACP_TILE_ON_RETAIN_REG_MASK     	0x1f
-#define ACP_TILE_OFF_RETAIN_REG_MASK    	0x20
+#define ACP_TILE_ON_MASK			0x03
+#define ACP_TILE_OFF_MASK			0x02
+#define ACP_TILE_ON_RETAIN_REG_MASK		0x1f
+#define ACP_TILE_OFF_RETAIN_REG_MASK		0x20
 
-#define ACP_TILE_P1_MASK                	0x3e
-#define ACP_TILE_P2_MASK                	0x3d
-#define ACP_TILE_DSP0_MASK              	0x3b
-#define ACP_TILE_DSP1_MASK              	0x37
+#define ACP_TILE_P1_MASK			0x3e
+#define ACP_TILE_P2_MASK			0x3d
+#define ACP_TILE_DSP0_MASK			0x3b
+#define ACP_TILE_DSP1_MASK			0x37
 
-#define ACP_TILE_DSP2_MASK              	0x2f
+#define ACP_TILE_DSP2_MASK			0x2f
 
 #define ACP_DMA_REGS_END			0x146c0
 #define ACP_I2S_PLAY_REGS_START			0x14840
@@ -75,8 +75,8 @@
 #define mmACP_CONTROL				0x5131
 #define mmACP_STATUS				0x5133
 #define mmACP_SOFT_RESET			0x5134
-#define ACP_CONTROL__ClkEn_MASK 		0x1
-#define ACP_SOFT_RESET__SoftResetAud_MASK 	0x100
+#define ACP_CONTROL__ClkEn_MASK			0x1
+#define ACP_SOFT_RESET__SoftResetAud_MASK	0x100
 #define ACP_SOFT_RESET__SoftResetAudDone_MASK	0x1000000
 #define ACP_CLOCK_EN_TIME_OUT_VALUE		0x000000FF
 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE	0x000000FF
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 0544460653b9..db96d69eb45e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -390,23 +390,17 @@ void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
 				      struct kfd_local_mem_info *mem_info)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
-	uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
-					     ~((1ULL << 32) - 1);
-	resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
 
 	memset(mem_info, 0, sizeof(*mem_info));
-	if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
-		mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
-		mem_info->local_mem_size_private = adev->gmc.real_vram_size -
-				adev->gmc.visible_vram_size;
-	} else {
-		mem_info->local_mem_size_public = 0;
-		mem_info->local_mem_size_private = adev->gmc.real_vram_size;
-	}
+
+	mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
+	mem_info->local_mem_size_private = adev->gmc.real_vram_size -
+						adev->gmc.visible_vram_size;
+
 	mem_info->vram_width = adev->gmc.vram_width;
 
-	pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
-			&adev->gmc.aper_base, &aper_limit,
+	pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
+			&adev->gmc.aper_base,
 			mem_info->local_mem_size_public,
 			mem_info->local_mem_size_private);
 
@@ -648,6 +642,13 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 
+	/* Temp workaround to fix the soft hang observed in certain compute
+	 * applications if GFXOFF is enabled.
+	 */
+	if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+		pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");
+		amdgpu_gfx_off_ctrl(adev, idle);
+	}
 	amdgpu_dpm_switch_power_profile(adev,
 					PP_SMC_POWER_PROFILE_COMPUTE,
 					!idle);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index 1afa8f122e7d..604757a1e440 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -304,4 +304,5 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = {
 				kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
 	.set_vm_context_page_table_base =
 				kgd_gfx_v9_set_vm_context_page_table_base,
+	.get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 43b18863a8b8..7d6c0013af35 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -799,7 +799,7 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx,
  *
  *  Reading registers referenced above involves programming GRBM appropriately
  */
-static void kgd_gfx_v9_get_cu_occupancy(struct kgd_dev *kgd, int pasid,
+void kgd_gfx_v9_get_cu_occupancy(struct kgd_dev *kgd, int pasid,
 		int *pasid_wave_cnt, int *max_waves_per_cu)
 {
 	int qidx;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
index fc8934b86d93..e64deba8900f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
@@ -63,3 +63,5 @@ bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
 
 void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd,
 			uint32_t vmid, uint64_t page_table_base);
+void kgd_gfx_v9_get_cu_occupancy(struct kgd_dev *kgd, int pasid,
+		int *pasid_wave_cnt, int *max_waves_per_cu);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 054a1c2d5054..1755386470e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -239,8 +239,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
 	if (!old)
 		return 0;
 
-	new = kmalloc(offsetof(typeof(*new), shared[old->shared_max]),
-		      GFP_KERNEL);
+	new = kmalloc(struct_size(new, shared, old->shared_max), GFP_KERNEL);
 	if (!new)
 		return -ENOMEM;
 
@@ -1115,19 +1114,19 @@ void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm)
 void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
-        struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
+	struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
 
 	if (WARN_ON(!kgd || !vm))
-                return;
+		return;
 
-        pr_debug("Releasing process vm %p\n", vm);
+	pr_debug("Releasing process vm %p\n", vm);
 
-        /* The original pasid of amdgpu vm has already been
-         * released during making a amdgpu vm to a compute vm
-         * The current pasid is managed by kfd and will be
-         * released on kfd process destroy. Set amdgpu pasid
-         * to 0 to avoid duplicate release.
-         */
+	/* The original pasid of amdgpu vm has already been
+	 * released during making a amdgpu vm to a compute vm
+	 * The current pasid is managed by kfd and will be
+	 * released on kfd process destroy. Set amdgpu pasid
+	 * to 0 to avoid duplicate release.
+	 */
 	amdgpu_vm_release_compute(adev, avm);
 }
 
@@ -1288,7 +1287,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
 	struct ttm_validate_buffer *bo_list_entry;
 	unsigned int mapped_to_gpu_memory;
 	int ret;
-	bool is_imported = 0;
+	bool is_imported = false;
 
 	mutex_lock(&mem->lock);
 	mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
@@ -1695,7 +1694,7 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
 
 	INIT_LIST_HEAD(&(*mem)->bo_va_list);
 	mutex_init(&(*mem)->lock);
-	
+
 	(*mem)->alloc_flags =
 		((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
 		KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 469352e2d6ec..86add0f4ea4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -1401,7 +1401,7 @@ static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOL
 {
 	u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
 	u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
-	u8 *start = (u8*)v3;
+	u8 *start = (u8 *)v3;
 
 	while (offset < size) {
 		ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index b4df6460e45a..306077884a67 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -70,7 +70,7 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 	struct atom_context *ctx = adev->mode_info.atom_context;
 	int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 						vram_usagebyfirmware);
-	struct vram_usagebyfirmware_v2_1 *	firmware_usage;
+	struct vram_usagebyfirmware_v2_1 *firmware_usage;
 	uint32_t start_addr, size;
 	uint16_t data_offset;
 	int usage_bytes = 0;
@@ -149,6 +149,10 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 		case LpDdr4MemType:
 			vram_type = AMDGPU_VRAM_TYPE_DDR4;
 			break;
+		case Ddr5MemType:
+		case LpDdr5MemType:
+			vram_type = AMDGPU_VRAM_TYPE_DDR5;
+			break;
 		default:
 			vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 			break;
@@ -544,6 +548,7 @@ int amdgpu_mem_train_support(struct amdgpu_device *adev)
 		case HW_REV(11, 0, 5):
 		case HW_REV(11, 0, 7):
 		case HW_REV(11, 0, 11):
+		case HW_REV(11, 0, 12):
 			ret = 1;
 			break;
 		default:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 78ac6dbe70d8..f1a050379190 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -352,17 +352,10 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
 				break;
 			case CHIP_POLARIS11:
 				if (type == CGS_UCODE_ID_SMU) {
-					if (((adev->pdev->device == 0x67ef) &&
-					     ((adev->pdev->revision == 0xe0) ||
-					      (adev->pdev->revision == 0xe5))) ||
-					    ((adev->pdev->device == 0x67ff) &&
-					     ((adev->pdev->revision == 0xcf) ||
-					      (adev->pdev->revision == 0xef) ||
-					      (adev->pdev->revision == 0xff)))) {
+					if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision)) {
 						info->is_kicker = true;
 						strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
-					} else if ((adev->pdev->device == 0x67ef) &&
-						   (adev->pdev->revision == 0xe2)) {
+					} else if (ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
 						info->is_kicker = true;
 						strcpy(fw_name, "amdgpu/polaris11_k2_smc.bin");
 					} else {
@@ -374,21 +367,10 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
 				break;
 			case CHIP_POLARIS10:
 				if (type == CGS_UCODE_ID_SMU) {
-					if (((adev->pdev->device == 0x67df) &&
-					     ((adev->pdev->revision == 0xe0) ||
-					      (adev->pdev->revision == 0xe3) ||
-					      (adev->pdev->revision == 0xe4) ||
-					      (adev->pdev->revision == 0xe5) ||
-					      (adev->pdev->revision == 0xe7) ||
-					      (adev->pdev->revision == 0xef))) ||
-					    ((adev->pdev->device == 0x6fdf) &&
-					     ((adev->pdev->revision == 0xef) ||
-					      (adev->pdev->revision == 0xff)))) {
+					if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision)) {
 						info->is_kicker = true;
 						strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
-					} else if ((adev->pdev->device == 0x67df) &&
-						   ((adev->pdev->revision == 0xe1) ||
-						    (adev->pdev->revision == 0xf7))) {
+					} else if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) {
 						info->is_kicker = true;
 						strcpy(fw_name, "amdgpu/polaris10_k2_smc.bin");
 					} else {
@@ -399,13 +381,7 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
 				}
 				break;
 			case CHIP_POLARIS12:
-				if (((adev->pdev->device == 0x6987) &&
-				     ((adev->pdev->revision == 0xc0) ||
-				      (adev->pdev->revision == 0xc3))) ||
-				    ((adev->pdev->device == 0x6981) &&
-				     ((adev->pdev->revision == 0x00) ||
-				      (adev->pdev->revision == 0x01) ||
-				      (adev->pdev->revision == 0x10)))) {
+				if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
 					info->is_kicker = true;
 					strcpy(fw_name, "amdgpu/polaris12_k_smc.bin");
 				} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 8466558d0d93..8d2878e950da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -326,7 +326,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 	increment_us = time_us - adev->mm_stats.last_update_us;
 	adev->mm_stats.last_update_us = time_us;
 	adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
-                                      us_upper_bound);
+				      us_upper_bound);
 
 	/* This prevents the short period of low performance when the VRAM
 	 * usage is low and the driver is in debt or doesn't have enough
@@ -1460,7 +1460,7 @@ int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
 		dma_fence_put(fence);
 		if (r)
 			return r;
-		r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
+		r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
 		drm_syncobj_put(syncobj);
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index c80d8339f58c..0350205c4897 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -100,7 +100,7 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip,
 	enum drm_sched_priority priority;
 	int r;
 
-	entity = kcalloc(1, offsetof(typeof(*entity), fences[amdgpu_sched_jobs]),
+	entity = kzalloc(struct_size(entity, fences, amdgpu_sched_jobs),
 			 GFP_KERNEL);
 	if (!entity)
 		return  -ENOMEM;
@@ -450,7 +450,7 @@ int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
 
 void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
 			  struct drm_sched_entity *entity,
-			  struct dma_fence *fence, uint64_t* handle)
+			  struct dma_fence *fence, uint64_t *handle)
 {
 	struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity);
 	uint64_t seq = centity->sequence;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 065937482239..5c1f3725c741 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -35,6 +35,7 @@
 #include "amdgpu_dm_debugfs.h"
 #include "amdgpu_ras.h"
 #include "amdgpu_rap.h"
+#include "amdgpu_fw_attestation.h"
 
 /**
  * amdgpu_debugfs_add_files - Add simple debugfs entries
@@ -169,14 +170,14 @@ static void amdgpu_debugfs_autodump_init(struct amdgpu_device *adev)
  *
  * Bit 62:  Indicates a GRBM bank switch is needed
  * Bit 61:  Indicates a SRBM bank switch is needed (implies bit 62 is
- * 			zero)
+ * 	    zero)
  * Bits 24..33: The SE or ME selector if needed
  * Bits 34..43: The SH (or SA) or PIPE selector if needed
  * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
  *
  * Bit 23:  Indicates that the PM power gating lock should be held
- * 			This is necessary to read registers that might be
- * 			unreliable during a power gating transistion.
+ * 	    This is necessary to read registers that might be
+ * 	    unreliable during a power gating transistion.
  *
  * The lower bits are the BYTE offset of the register to read.  This
  * allows reading multiple registers in a single call and having
@@ -864,7 +865,7 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
 {
 	struct amdgpu_device *adev = f->f_inode->i_private;
 	int r, x;
-	ssize_t result=0;
+	ssize_t result = 0;
 	uint32_t offset, se, sh, cu, wave, simd, data[32];
 
 	if (size & 3 || *pos & 3)
@@ -1210,7 +1211,7 @@ static const char *debugfs_regs_names[] = {
 
 /**
  * amdgpu_debugfs_regs_init -	Initialize debugfs entries that provide
- * 								register access.
+ * 				register access.
  *
  * @adev: The device to attach the debugfs entries to
  */
@@ -1338,11 +1339,41 @@ static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data)
 	return 0;
 }
 
+static int amdgpu_debugfs_vm_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *)m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_file *file;
+	int r;
+
+	r = mutex_lock_interruptible(&dev->filelist_mutex);
+	if (r)
+		return r;
+
+	list_for_each_entry(file, &dev->filelist, lhead) {
+		struct amdgpu_fpriv *fpriv = file->driver_priv;
+		struct amdgpu_vm *vm = &fpriv->vm;
+
+		seq_printf(m, "pid:%d\tProcess:%s ----------\n",
+				vm->task_info.pid, vm->task_info.process_name);
+		r = amdgpu_bo_reserve(vm->root.base.bo, true);
+		if (r)
+			break;
+		amdgpu_debugfs_vm_bo_info(vm, m);
+		amdgpu_bo_unreserve(vm->root.base.bo);
+	}
+
+	mutex_unlock(&dev->filelist_mutex);
+
+	return r;
+}
+
 static const struct drm_info_list amdgpu_debugfs_list[] = {
 	{"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump},
 	{"amdgpu_test_ib", &amdgpu_debugfs_test_ib},
 	{"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram},
 	{"amdgpu_evict_gtt", &amdgpu_debugfs_evict_gtt},
+	{"amdgpu_vm_info", &amdgpu_debugfs_vm_info},
 };
 
 static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring,
@@ -1638,6 +1669,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
 
 	amdgpu_rap_debugfs_init(adev);
 
+	amdgpu_fw_attestation_debugfs_init(adev);
+
 	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list,
 					ARRAY_SIZE(amdgpu_debugfs_list));
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 37da3537ba2e..7560b05e4ac1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -80,6 +80,8 @@ MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/green_sardine_gpu_info.bin");
 
 #define AMDGPU_RESUME_MS		2000
 
@@ -114,6 +116,8 @@ const char *amdgpu_asic_name[] = {
 	"NAVI12",
 	"SIENNA_CICHLID",
 	"NAVY_FLOUNDER",
+	"VANGOGH",
+	"DIMGREY_CAVEFISH",
 	"LAST",
 };
 
@@ -239,9 +243,11 @@ bool amdgpu_device_supports_baco(struct drm_device *dev)
 	return amdgpu_asic_supports_baco(adev);
 }
 
+/*
+ * VRAM access helper functions
+ */
+
 /**
- * VRAM access helper functions.
- *
  * amdgpu_device_vram_access - read/write a buffer in vram
  *
  * @adev: amdgpu_device pointer
@@ -705,7 +711,7 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
 /**
  * amdgpu_invalid_rreg - dummy reg read function
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  * @reg: offset of register
  *
  * Dummy register read function.  Used for register blocks
@@ -722,7 +728,7 @@ static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 /**
  * amdgpu_invalid_wreg - dummy reg write function
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  * @reg: offset of register
  * @v: value to write to the register
  *
@@ -739,7 +745,7 @@ static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32
 /**
  * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  * @reg: offset of register
  *
  * Dummy register read function.  Used for register blocks
@@ -756,7 +762,7 @@ static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
 /**
  * amdgpu_invalid_wreg64 - dummy reg write function
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  * @reg: offset of register
  * @v: value to write to the register
  *
@@ -773,7 +779,7 @@ static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint
 /**
  * amdgpu_block_invalid_rreg - dummy reg read function
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  * @block: offset of instance
  * @reg: offset of register
  *
@@ -793,7 +799,7 @@ static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 /**
  * amdgpu_block_invalid_wreg - dummy reg write function
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  * @block: offset of instance
  * @reg: offset of register
  * @v: value to write to the register
@@ -813,7 +819,7 @@ static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 /**
  * amdgpu_device_asic_init - Wrapper for atom asic_init
  *
- * @dev: drm_device pointer
+ * @adev: amdgpu_device pointer
  *
  * Does any asic specific work and then calls atom asic init.
  */
@@ -827,7 +833,7 @@ static int amdgpu_device_asic_init(struct amdgpu_device *adev)
 /**
  * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  *
  * Allocates a scratch page of VRAM for use by various things in the
  * driver.
@@ -844,7 +850,7 @@ static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 /**
  * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  *
  * Frees the VRAM scratch page.
  */
@@ -1370,13 +1376,6 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
 
 	amdgpu_gmc_tmz_set(adev);
 
-	if (amdgpu_num_kcq == -1) {
-		amdgpu_num_kcq = 8;
-	} else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
-		amdgpu_num_kcq = 8;
-		dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
-	}
-
 	amdgpu_gmc_noretry_set(adev);
 
 	return 0;
@@ -1783,6 +1782,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
 	case CHIP_VEGA20:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 	default:
 		return 0;
 	case CHIP_VEGA10:
@@ -1803,7 +1803,10 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
 		chip_name = "arcturus";
 		break;
 	case CHIP_RENOIR:
-		chip_name = "renoir";
+		if (adev->apu_flags & AMD_APU_IS_RENOIR)
+			chip_name = "renoir";
+		else
+			chip_name = "green_sardine";
 		break;
 	case CHIP_NAVI10:
 		chip_name = "navi10";
@@ -1814,6 +1817,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
 	case CHIP_NAVI12:
 		chip_name = "navi12";
 		break;
+	case CHIP_VANGOGH:
+		chip_name = "vangogh";
+		break;
 	}
 
 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
@@ -1988,7 +1994,12 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
 	case  CHIP_NAVI12:
 	case  CHIP_SIENNA_CICHLID:
 	case  CHIP_NAVY_FLOUNDER:
-		adev->family = AMDGPU_FAMILY_NV;
+	case  CHIP_DIMGREY_CAVEFISH:
+	case CHIP_VANGOGH:
+		if (adev->asic_type == CHIP_VANGOGH)
+			adev->family = AMDGPU_FAMILY_VGH;
+		else
+			adev->family = AMDGPU_FAMILY_NV;
 
 		r = nv_set_ip_blocks(adev);
 		if (r)
@@ -2993,10 +3004,10 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
 	case CHIP_NAVI14:
 	case CHIP_NAVI12:
 	case CHIP_RENOIR:
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_VANGOGH:
 #endif
 		return amdgpu_dc != 0;
 #endif
@@ -3011,7 +3022,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
 /**
  * amdgpu_device_has_dc_support - check if dc is supported
  *
- * @adev: amdgpu_device_pointer
+ * @adev: amdgpu_device pointer
  *
  * Returns true for supported, false for not supported
  */
@@ -4045,7 +4056,7 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
 /**
  * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  * @from_hypervisor: request from hypervisor
  *
  * do VF FLR and reinitialize Asic
@@ -4100,7 +4111,7 @@ error:
 /**
  * amdgpu_device_has_job_running - check if there is any job in mirror list
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  *
  * check if there is any job in mirror list
  */
@@ -4128,7 +4139,7 @@ bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
 /**
  * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  *
  * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
  * a hung GPU.
@@ -4477,7 +4488,7 @@ static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
 /**
  * amdgpu_device_gpu_recover - reset the asic and recover scheduler
  *
- * @adev: amdgpu device pointer
+ * @adev: amdgpu_device pointer
  * @job: which job trigger hang
  *
  * Attempt to reset the GPU if it has hung (all asics).
@@ -4497,7 +4508,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 	bool need_emergency_restart = false;
 	bool audio_suspended = false;
 
-	/**
+	/*
 	 * Special case: RAS triggered and full reset isn't supported
 	 */
 	need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h
index 373cdebe0e2f..52488bb45112 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_df.h
@@ -44,11 +44,11 @@ struct amdgpu_df_funcs {
 	void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
 					    bool enable);
 	int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
-					 int is_add);
+					 int counter_idx, int is_add);
 	int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
-					 int is_remove);
+					 int counter_idx, int is_remove);
 	void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
-					 uint64_t *count);
+					 int counter_idx, uint64_t *count);
 	uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
 	void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
 			 uint32_t ficadl_val, uint32_t ficadh_val);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index b25faaee6f0e..2e8a8b57639f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -38,6 +38,7 @@
 #include <drm/drm_edid.h>
 #include <drm/drm_gem_framebuffer_helper.h>
 #include <drm/drm_fb_helper.h>
+#include <drm/drm_fourcc.h>
 #include <drm/drm_vblank.h>
 
 static void amdgpu_display_flip_callback(struct dma_fence *f,
@@ -524,6 +525,10 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 			    (adev->apu_flags & AMD_APU_IS_PICASSO))
 				domain |= AMDGPU_GEM_DOMAIN_GTT;
 			break;
+		case CHIP_RENOIR:
+			domain |= AMDGPU_GEM_DOMAIN_GTT;
+			break;
+
 		default:
 			break;
 		}
@@ -533,6 +538,154 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 	return domain;
 }
 
+static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
+{
+	struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
+	uint64_t modifier = 0;
+
+	if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
+		modifier = DRM_FORMAT_MOD_LINEAR;
+	} else {
+		int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
+		bool has_xor = swizzle >= 16;
+		int block_size_bits;
+		int version;
+		int pipe_xor_bits = 0;
+		int bank_xor_bits = 0;
+		int packers = 0;
+		uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
+
+		switch (swizzle >> 2) {
+		case 0: /* 256B */
+			block_size_bits = 8;
+			break;
+		case 1: /* 4KiB */
+		case 5: /* 4KiB _X */
+			block_size_bits = 12;
+			break;
+		case 2: /* 64KiB */
+		case 4: /* 64 KiB _T */
+		case 6: /* 64 KiB _X */
+			block_size_bits = 16;
+			break;
+		default:
+			/* RESERVED or VAR */
+			return -EINVAL;
+		}
+
+		if (adev->asic_type >= CHIP_SIENNA_CICHLID)
+			version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
+		else if (adev->family == AMDGPU_FAMILY_NV)
+			version = AMD_FMT_MOD_TILE_VER_GFX10;
+		else
+			version = AMD_FMT_MOD_TILE_VER_GFX9;
+
+		switch (swizzle & 3) {
+		case 0: /* Z microtiling */
+			return -EINVAL;
+		case 1: /* S microtiling */
+			if (!has_xor)
+				version = AMD_FMT_MOD_TILE_VER_GFX9;
+			break;
+		case 2:
+			if (!has_xor && afb->base.format->cpp[0] != 4)
+				version = AMD_FMT_MOD_TILE_VER_GFX9;
+			break;
+		case 3:
+			break;
+		}
+
+		if (has_xor) {
+			switch (version) {
+			case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
+				pipe_xor_bits = min(block_size_bits - 8,
+						    ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes));
+				packers = min(block_size_bits - 8 - pipe_xor_bits,
+					      ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
+				break;
+			case AMD_FMT_MOD_TILE_VER_GFX10:
+				pipe_xor_bits = min(block_size_bits - 8,
+						    ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes));
+				break;
+			case AMD_FMT_MOD_TILE_VER_GFX9:
+				pipe_xor_bits = min(block_size_bits - 8,
+						    ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes) +
+						    ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
+				bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
+						    ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
+				break;
+			}
+		}
+
+		modifier = AMD_FMT_MOD |
+			   AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
+			   AMD_FMT_MOD_SET(TILE_VERSION, version) |
+			   AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+			   AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
+			   AMD_FMT_MOD_SET(PACKERS, packers);
+
+		if (dcc_offset != 0) {
+			bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
+			bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
+
+			/* Enable constant encode on RAVEN2 and later. */
+			bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
+						   (adev->asic_type == CHIP_RAVEN &&
+						    adev->external_rev_id >= 0x81);
+
+			int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
+					      dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
+					      AMD_FMT_MOD_DCC_BLOCK_256B;
+
+			modifier |= AMD_FMT_MOD_SET(DCC, 1) |
+				    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
+				    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
+				    AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
+				    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
+
+			afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
+			afb->base.pitches[1] = AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
+		}
+	}
+
+	afb->base.modifier = modifier;
+	afb->base.flags |= DRM_MODE_FB_MODIFIERS;
+	return 0;
+}
+
+static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
+				      uint64_t *tiling_flags, bool *tmz_surface)
+{
+	struct amdgpu_bo *rbo;
+	int r;
+
+	if (!amdgpu_fb) {
+		*tiling_flags = 0;
+		*tmz_surface = false;
+		return 0;
+	}
+
+	rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
+	r = amdgpu_bo_reserve(rbo, false);
+
+	if (unlikely(r)) {
+		/* Don't show error message when returning -ERESTARTSYS */
+		if (r != -ERESTARTSYS)
+			DRM_ERROR("Unable to reserve buffer: %d\n", r);
+		return r;
+	}
+
+	if (tiling_flags)
+		amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
+
+	if (tmz_surface)
+		*tmz_surface = amdgpu_bo_encrypted(rbo);
+
+	amdgpu_bo_unreserve(rbo);
+
+	return r;
+}
+
 int amdgpu_display_framebuffer_init(struct drm_device *dev,
 				    struct amdgpu_framebuffer *rfb,
 				    const struct drm_mode_fb_cmd2 *mode_cmd,
@@ -542,11 +695,25 @@ int amdgpu_display_framebuffer_init(struct drm_device *dev,
 	rfb->base.obj[0] = obj;
 	drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
 	ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
-	if (ret) {
-		rfb->base.obj[0] = NULL;
-		return ret;
+	if (ret)
+		goto fail;
+
+	ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
+	if (ret)
+		goto fail;
+
+	if (dev->mode_config.allow_fb_modifiers &&
+	    !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
+		ret = convert_tiling_flags_to_modifier(rfb);
+		if (ret)
+			goto fail;
 	}
+
 	return 0;
+
+fail:
+	rfb->base.obj[0] = NULL;
+	return ret;
 }
 
 struct drm_framebuffer *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d6fced7a9a03..1dfea15bbec3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -95,16 +95,16 @@
 #define KMS_DRIVER_MINOR	40
 #define KMS_DRIVER_PATCHLEVEL	0
 
-int amdgpu_vram_limit = 0;
-int amdgpu_vis_vram_limit = 0;
+int amdgpu_vram_limit;
+int amdgpu_vis_vram_limit;
 int amdgpu_gart_size = -1; /* auto */
 int amdgpu_gtt_size = -1; /* auto */
 int amdgpu_moverate = -1; /* auto */
-int amdgpu_benchmarking = 0;
-int amdgpu_testing = 0;
+int amdgpu_benchmarking;
+int amdgpu_testing;
 int amdgpu_audio = -1;
-int amdgpu_disp_priority = 0;
-int amdgpu_hw_i2c = 0;
+int amdgpu_disp_priority;
+int amdgpu_hw_i2c;
 int amdgpu_pcie_gen2 = -1;
 int amdgpu_msi = -1;
 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
@@ -114,19 +114,19 @@ int amdgpu_aspm = -1;
 int amdgpu_runtime_pm = -1;
 uint amdgpu_ip_block_mask = 0xffffffff;
 int amdgpu_bapm = -1;
-int amdgpu_deep_color = 0;
+int amdgpu_deep_color;
 int amdgpu_vm_size = -1;
 int amdgpu_vm_fragment_size = -1;
 int amdgpu_vm_block_size = -1;
-int amdgpu_vm_fault_stop = 0;
-int amdgpu_vm_debug = 0;
+int amdgpu_vm_fault_stop;
+int amdgpu_vm_debug;
 int amdgpu_vm_update_mode = -1;
-int amdgpu_exp_hw_support = 0;
+int amdgpu_exp_hw_support;
 int amdgpu_dc = -1;
 int amdgpu_sched_jobs = 32;
 int amdgpu_sched_hw_submission = 2;
-uint amdgpu_pcie_gen_cap = 0;
-uint amdgpu_pcie_lane_cap = 0;
+uint amdgpu_pcie_gen_cap;
+uint amdgpu_pcie_lane_cap;
 uint amdgpu_cg_mask = 0xffffffff;
 uint amdgpu_pg_mask = 0xffffffff;
 uint amdgpu_sdma_phase_quantum = 32;
@@ -134,23 +134,31 @@ char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
 /* OverDrive(bit 14) disabled by default*/
 uint amdgpu_pp_feature_mask = 0xffffbfff;
-uint amdgpu_force_long_training = 0;
-int amdgpu_job_hang_limit = 0;
+uint amdgpu_force_long_training;
+int amdgpu_job_hang_limit;
 int amdgpu_lbpw = -1;
 int amdgpu_compute_multipipe = -1;
 int amdgpu_gpu_recovery = -1; /* auto */
-int amdgpu_emu_mode = 0;
-uint amdgpu_smu_memory_pool_size = 0;
-/* FBC (bit 0) disabled by default*/
-uint amdgpu_dc_feature_mask = 0;
-uint amdgpu_dc_debug_mask = 0;
+int amdgpu_emu_mode;
+uint amdgpu_smu_memory_pool_size;
+/*
+ * FBC (bit 0) disabled by default
+ * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
+ *   - With this, for multiple monitors in sync(e.g. with the same model),
+ *     mclk switching will be allowed. And the mclk will be not foced to the
+ *     highest. That helps saving some idle power.
+ * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
+ * PSR (bit 3) disabled by default
+ */
+uint amdgpu_dc_feature_mask = 2;
+uint amdgpu_dc_debug_mask;
 int amdgpu_async_gfx_ring = 1;
-int amdgpu_mcbp = 0;
+int amdgpu_mcbp;
 int amdgpu_discovery = -1;
-int amdgpu_mes = 0;
+int amdgpu_mes;
 int amdgpu_noretry = -1;
 int amdgpu_force_asic_type = -1;
-int amdgpu_tmz = 0;
+int amdgpu_tmz;
 int amdgpu_reset_method = -1; /* auto */
 int amdgpu_num_kcq = -1;
 
@@ -272,7 +280,7 @@ module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_
 /**
  * DOC: dpm (int)
  * Override for dynamic power management setting
- * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20)
+ * (0 = disable, 1 = enable)
  * The default is -1 (auto).
  */
 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
@@ -765,7 +773,7 @@ module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
  * Defaults to 0, or disabled. Userspace can still override this level later
  * after boot.
  */
-uint amdgpu_dm_abm_level = 0;
+uint amdgpu_dm_abm_level;
 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
 
@@ -1090,6 +1098,9 @@ static const struct pci_device_id pciidlist[] = {
 	{0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
 	{0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
 
+	/* Van Gogh */
+	{0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
+
 	{0, 0, 0}
 };
 
@@ -1496,7 +1507,7 @@ static const struct file_operations amdgpu_driver_kms_fops = {
 
 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
 {
-        struct drm_file *file;
+	struct drm_file *file;
 
 	if (!filp)
 		return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index e2c2eb45a793..0bf7d36c6686 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -207,6 +207,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
 	int ret;
 	unsigned long tmp;
 
+	memset(&mode_cmd, 0, sizeof(mode_cmd));
 	mode_cmd.width = sizes->surface_width;
 	mode_cmd.height = sizes->surface_height;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c
new file mode 100644
index 000000000000..c6947d6c7ff5
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/debugfs.h>
+#include <linux/firmware.h>
+#include <linux/dma-mapping.h>
+
+#include "amdgpu.h"
+#include "amdgpu_psp.h"
+#include "amdgpu_ucode.h"
+#include "soc15_common.h"
+
+#define FW_ATTESTATION_DB_COOKIE        0x143b6a37
+#define FW_ATTESTATION_RECORD_VALID  	1
+#define FW_ATTESTATION_MAX_SIZE		4096
+
+typedef struct FW_ATT_DB_HEADER
+{
+	uint32_t AttDbVersion;           /* version of the fwar feature */
+	uint32_t AttDbCookie;            /* cookie as an extra check for corrupt data */
+} FW_ATT_DB_HEADER;
+
+typedef struct FW_ATT_RECORD
+{
+	uint16_t AttFwIdV1;              /* Legacy FW Type field */
+	uint16_t AttFwIdV2;              /* V2 FW ID field */
+	uint32_t AttFWVersion;           /* FW Version */
+	uint16_t AttFWActiveFunctionID;  /* The VF ID (only in VF Attestation Table) */
+	uint16_t AttSource;              /* FW source indicator */
+	uint16_t RecordValid;            /* Indicates whether the record is a valid entry */
+	uint8_t  AttFwTaId;              /* Ta ID (only in TA Attestation Table) */
+	uint8_t  Reserved;
+} FW_ATT_RECORD;
+
+static ssize_t amdgpu_fw_attestation_debugfs_read(struct file *f,
+						  char __user *buf,
+						  size_t size,
+						  loff_t *pos)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
+	uint64_t records_addr = 0;
+	uint64_t vram_pos = 0;
+	FW_ATT_DB_HEADER fw_att_hdr = {0};
+	FW_ATT_RECORD fw_att_record = {0};
+
+	if (size < sizeof(FW_ATT_RECORD)) {
+		DRM_WARN("FW attestation input buffer not enough memory");
+		return -EINVAL;
+	}
+
+	if ((*pos + sizeof(FW_ATT_DB_HEADER)) >= FW_ATTESTATION_MAX_SIZE) {
+		DRM_WARN("FW attestation out of bounds");
+		return 0;
+	}
+
+	if (psp_get_fw_attestation_records_addr(&adev->psp, &records_addr)) {
+		DRM_WARN("Failed to get FW attestation record address");
+		return -EINVAL;
+	}
+
+	vram_pos =  records_addr - adev->gmc.vram_start;
+
+	if (*pos == 0) {
+		amdgpu_device_vram_access(adev,
+					  vram_pos,
+					  (uint32_t*)&fw_att_hdr,
+					  sizeof(FW_ATT_DB_HEADER),
+					  false);
+
+		if (fw_att_hdr.AttDbCookie != FW_ATTESTATION_DB_COOKIE) {
+			DRM_WARN("Invalid FW attestation cookie");
+			return -EINVAL;
+		}
+
+		DRM_INFO("FW attestation version = 0x%X", fw_att_hdr.AttDbVersion);
+	}
+
+	amdgpu_device_vram_access(adev,
+				  vram_pos + sizeof(FW_ATT_DB_HEADER) + *pos,
+				  (uint32_t*)&fw_att_record,
+				  sizeof(FW_ATT_RECORD),
+				  false);
+
+	if (fw_att_record.RecordValid != FW_ATTESTATION_RECORD_VALID)
+		return 0;
+
+	if (copy_to_user(buf, (void*)&fw_att_record, sizeof(FW_ATT_RECORD)))
+		return -EINVAL;
+
+	*pos += sizeof(FW_ATT_RECORD);
+
+	return sizeof(FW_ATT_RECORD);
+}
+
+static const struct file_operations amdgpu_fw_attestation_debugfs_ops = {
+	.owner = THIS_MODULE,
+	.read = amdgpu_fw_attestation_debugfs_read,
+	.write = NULL,
+	.llseek = default_llseek
+};
+
+static int amdgpu_is_fw_attestation_supported(struct amdgpu_device *adev)
+{
+	if (adev->asic_type >= CHIP_SIENNA_CICHLID)
+		return 1;
+
+	return 0;
+}
+
+void amdgpu_fw_attestation_debugfs_init(struct amdgpu_device *adev)
+{
+#if defined(CONFIG_DEBUG_FS)
+	if (!amdgpu_is_fw_attestation_supported(adev))
+		return;
+
+	debugfs_create_file("amdgpu_fw_attestation",
+			    S_IRUSR,
+			    adev_to_drm(adev)->primary->debugfs_root,
+			    adev,
+			    &amdgpu_fw_attestation_debugfs_ops);
+#endif
+}
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.h
new file mode 100644
index 000000000000..90af4fe58c99
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _AMDGPU_FW_ATTESTATION_H
+#define _AMDGPU_FW_ATTESTATION_H
+
+#include "amdgpu.h"
+
+void amdgpu_fw_attestation_debugfs_init(struct amdgpu_device *adev);
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index a6142ede78fb..c9f94fbeb018 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -850,67 +850,6 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 }
 
 #if defined(CONFIG_DEBUG_FS)
-
-#define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag)	\
-	if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) {	\
-		seq_printf((m), " " #flag);		\
-	}
-
-static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
-{
-	struct drm_gem_object *gobj = ptr;
-	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
-	struct seq_file *m = data;
-
-	struct dma_buf_attachment *attachment;
-	struct dma_buf *dma_buf;
-	unsigned domain;
-	const char *placement;
-	unsigned pin_count;
-
-	domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
-	switch (domain) {
-	case AMDGPU_GEM_DOMAIN_VRAM:
-		placement = "VRAM";
-		break;
-	case AMDGPU_GEM_DOMAIN_GTT:
-		placement = " GTT";
-		break;
-	case AMDGPU_GEM_DOMAIN_CPU:
-	default:
-		placement = " CPU";
-		break;
-	}
-	seq_printf(m, "\t0x%08x: %12ld byte %s",
-		   id, amdgpu_bo_size(bo), placement);
-
-	pin_count = READ_ONCE(bo->tbo.pin_count);
-	if (pin_count)
-		seq_printf(m, " pin count %d", pin_count);
-
-	dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
-	attachment = READ_ONCE(bo->tbo.base.import_attach);
-
-	if (attachment)
-		seq_printf(m, " imported from %p%s", dma_buf,
-			   attachment->peer2peer ? " P2P" : "");
-	else if (dma_buf)
-		seq_printf(m, " exported as %p", dma_buf);
-
-	amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
-	amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS);
-	amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC);
-	amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED);
-	amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW);
-	amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
-	amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID);
-	amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC);
-
-	seq_printf(m, "\n");
-
-	return 0;
-}
-
 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 {
 	struct drm_info_node *node = (struct drm_info_node *)m->private;
@@ -924,6 +863,8 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 
 	list_for_each_entry(file, &dev->filelist, lhead) {
 		struct task_struct *task;
+		struct drm_gem_object *gobj;
+		int id;
 
 		/*
 		 * Although we have a valid reference on file->pid, that does
@@ -938,7 +879,11 @@ static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
 		rcu_read_unlock();
 
 		spin_lock(&file->table_lock);
-		idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
+		idr_for_each_entry(&file->object_idr, gobj, id) {
+			struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
+
+			amdgpu_bo_print_info(id, bo, m);
+		}
 		spin_unlock(&file->table_lock);
 	}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 8c9bacfdbc30..e584f48f3b54 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -804,3 +804,14 @@ failed_undo:
 failed_kiq_write:
 	dev_err(adev->dev, "failed to write reg:%x\n", reg);
 }
+
+int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
+{
+	if (amdgpu_num_kcq == -1) {
+		return 8;
+	} else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
+		dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
+		return 8;
+	}
+	return amdgpu_num_kcq;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 258498cbf1eb..786eb4aa7314 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -218,6 +218,7 @@ struct amdgpu_gfx_funcs {
 	void (*reset_ras_error_count) (struct amdgpu_device *adev);
 	void (*init_spm_golden)(struct amdgpu_device *adev);
 	void (*query_ras_error_status) (struct amdgpu_device *adev);
+	void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
 };
 
 struct sq_work {
@@ -392,4 +393,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 				  struct amdgpu_iv_entry *entry);
 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
+int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index cc86f431a3d4..056cb87d09ea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -389,6 +389,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
 	case CHIP_NAVI10:
 	case CHIP_NAVI14:
 	case CHIP_NAVI12:
+	case CHIP_VANGOGH:
 		/* Don't enable it by default yet.
 		 */
 		if (amdgpu_tmz < 1) {
@@ -421,20 +422,30 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)
 	struct amdgpu_gmc *gmc = &adev->gmc;
 
 	switch (adev->asic_type) {
-	case CHIP_RAVEN:
-		/* Raven currently has issues with noretry
-		 * regardless of what we decide for other
-		 * asics, we should leave raven with
-		 * noretry = 0 until we root cause the
-		 * issues.
+	case CHIP_VEGA20:
+	case CHIP_NAVI10:
+	case CHIP_NAVI14:
+	case CHIP_SIENNA_CICHLID:
+	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
+		/*
+		 * noretry = 0 will cause kfd page fault tests fail
+		 * for some ASICs, so set default to 1 for these ASICs.
 		 */
 		if (amdgpu_noretry == -1)
-			gmc->noretry = 0;
+			gmc->noretry = 1;
 		else
 			gmc->noretry = amdgpu_noretry;
 		break;
+	case CHIP_RAVEN:
 	default:
-		/* default this to 0 for now, but we may want
+		/* Raven currently has issues with noretry
+		 * regardless of what we decide for other
+		 * asics, we should leave raven with
+		 * noretry = 0 until we root cause the
+		 * issues.
+		 *
+		 * default this to 0 for now, but we may want
 		 * to change this in the future for certain
 		 * GPUs as it can increase performance in
 		 * certain cases.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 1721739def84..8980329cded0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -81,8 +81,8 @@ static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func;
 /**
  * amdgpu_gtt_mgr_init - init GTT manager and DRM MM
  *
- * @man: TTM memory type manager
- * @p_size: maximum size of GTT
+ * @adev: amdgpu_device pointer
+ * @gtt_size: maximum size of GTT
  *
  * Allocate and initialize the GTT manager.
  */
@@ -123,7 +123,7 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size)
 /**
  * amdgpu_gtt_mgr_fini - free and destroy GTT manager
  *
- * @man: TTM memory type manager
+ * @adev: amdgpu_device pointer
  *
  * Destroy and free the GTT manager, returns -EBUSY if ranges are still
  * allocated inside it.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index ab6d9f1186c2..4ad6d801bc25 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -324,6 +324,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 		fw_info->ver = adev->dm.dmcub_fw_version;
 		fw_info->feature = 0;
 		break;
+	case AMDGPU_INFO_FW_TOC:
+		fw_info->ver = adev->psp.toc_fw_version;
+		fw_info->feature = adev->psp.toc_feature_version;
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -1444,6 +1448,13 @@ static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
 	seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
 		   fw_info.feature, fw_info.ver);
 
+	/* TOC */
+	query_fw.fw_type = AMDGPU_INFO_FW_TOC;
+	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
+	if (ret)
+		return ret;
+	seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
+		   fw_info.feature, fw_info.ver);
 
 	seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index a04decb934b0..319cb19e1b99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -302,6 +302,9 @@ struct amdgpu_display_funcs {
 struct amdgpu_framebuffer {
 	struct drm_framebuffer base;
 
+	uint64_t tiling_flags;
+	bool tmz_surface;
+
 	/* caching for later use */
 	uint64_t address;
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index edaac242ff85..e62cc0e1a5ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -53,6 +53,8 @@ struct amdgpu_nbio_funcs {
 	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
 	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
 	u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
+	u32 (*get_pcie_port_index_offset)(struct amdgpu_device *adev);
+	u32 (*get_pcie_port_data_offset)(struct amdgpu_device *adev);
 	u32 (*get_rev_id)(struct amdgpu_device *adev);
 	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
 	void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
@@ -85,6 +87,8 @@ struct amdgpu_nbio_funcs {
 	void (*query_ras_error_count)(struct amdgpu_device *adev,
 					void *ras_error_status);
 	int (*ras_late_init)(struct amdgpu_device *adev);
+	void (*enable_aspm)(struct amdgpu_device *adev,
+			    bool enable);
 };
 
 struct amdgpu_nbio {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index e1f64ef8c765..c6c9723d3d8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1045,6 +1045,7 @@ static const char *amdgpu_vram_names[] = {
 	"DDR3",
 	"DDR4",
 	"GDDR6",
+	"DDR5"
 };
 
 /**
@@ -1507,3 +1508,77 @@ uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
 	}
 	return domain;
 }
+
+#if defined(CONFIG_DEBUG_FS)
+#define amdgpu_bo_print_flag(m, bo, flag)		        \
+	do {							\
+		if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) {	\
+			seq_printf((m), " " #flag);		\
+		}						\
+	} while (0)
+
+/**
+ * amdgpu_debugfs_print_bo_info - print BO info in debugfs file
+ *
+ * @id: Index or Id of the BO
+ * @bo: Requested BO for printing info
+ * @m: debugfs file
+ *
+ * Print BO information in debugfs file
+ *
+ * Returns:
+ * Size of the BO in bytes.
+ */
+u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
+{
+	struct dma_buf_attachment *attachment;
+	struct dma_buf *dma_buf;
+	unsigned int domain;
+	const char *placement;
+	unsigned int pin_count;
+	u64 size;
+
+	domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
+	switch (domain) {
+	case AMDGPU_GEM_DOMAIN_VRAM:
+		placement = "VRAM";
+		break;
+	case AMDGPU_GEM_DOMAIN_GTT:
+		placement = " GTT";
+		break;
+	case AMDGPU_GEM_DOMAIN_CPU:
+	default:
+		placement = " CPU";
+		break;
+	}
+
+	size = amdgpu_bo_size(bo);
+	seq_printf(m, "\t\t0x%08x: %12lld byte %s",
+			id, size, placement);
+
+	pin_count = READ_ONCE(bo->tbo.pin_count);
+	if (pin_count)
+		seq_printf(m, " pin count %d", pin_count);
+
+	dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
+	attachment = READ_ONCE(bo->tbo.base.import_attach);
+
+	if (attachment)
+		seq_printf(m, " imported from %p", dma_buf);
+	else if (dma_buf)
+		seq_printf(m, " exported as %p", dma_buf);
+
+	amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
+	amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
+	amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
+	amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
+	amdgpu_bo_print_flag(m, bo, SHADOW);
+	amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
+	amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
+	amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
+
+	seq_puts(m, "\n");
+
+	return size;
+}
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 01296ef0d673..ed47cbac4f75 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -328,6 +328,7 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev,
 #if defined(CONFIG_DEBUG_FS)
 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
 					 struct seq_file *m);
+u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);
 #endif
 int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
index 69af462db34d..19c0a3655228 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
@@ -19,17 +19,29 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Author: Jonathan Kim <jonathan.kim@amd.com>
- *
  */
 
 #include <linux/perf_event.h>
 #include <linux/init.h>
 #include "amdgpu.h"
 #include "amdgpu_pmu.h"
-#include "df_v3_6.h"
 
 #define PMU_NAME_SIZE 32
+#define NUM_FORMATS_AMDGPU_PMU		4
+#define NUM_FORMATS_DF_VEGA20		3
+#define NUM_EVENTS_DF_VEGA20		8
+#define NUM_EVENT_TYPES_VEGA20		1
+#define NUM_EVENTS_VEGA20_XGMI		2
+#define NUM_EVENTS_VEGA20_MAX		NUM_EVENTS_VEGA20_XGMI
+#define NUM_EVENT_TYPES_ARCTURUS	1
+#define NUM_EVENTS_ARCTURUS_XGMI	6
+#define NUM_EVENTS_ARCTURUS_MAX		NUM_EVENTS_ARCTURUS_XGMI
+
+struct amdgpu_pmu_event_attribute {
+	struct device_attribute attr;
+	const char *event_str;
+	unsigned int type;
+};
 
 /* record to keep track of pmu entry per pmu type per device */
 struct amdgpu_pmu_entry {
@@ -37,11 +49,162 @@ struct amdgpu_pmu_entry {
 	struct amdgpu_device *adev;
 	struct pmu pmu;
 	unsigned int pmu_perf_type;
+	char *pmu_type_name;
+	char *pmu_file_prefix;
+	struct attribute_group fmt_attr_group;
+	struct amdgpu_pmu_event_attribute *fmt_attr;
+	struct attribute_group evt_attr_group;
+	struct amdgpu_pmu_event_attribute *evt_attr;
 };
 
+static ssize_t amdgpu_pmu_event_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct amdgpu_pmu_event_attribute *amdgpu_pmu_attr;
+
+	amdgpu_pmu_attr = container_of(attr, struct amdgpu_pmu_event_attribute,
+									attr);
+
+	if (!amdgpu_pmu_attr->type)
+		return sprintf(buf, "%s\n", amdgpu_pmu_attr->event_str);
+
+	return sprintf(buf, "%s,type=0x%x\n",
+			amdgpu_pmu_attr->event_str, amdgpu_pmu_attr->type);
+}
+
 static LIST_HEAD(amdgpu_pmu_list);
 
 
+struct amdgpu_pmu_attr {
+	const char *name;
+	const char *config;
+};
+
+struct amdgpu_pmu_type {
+	const unsigned int type;
+	const unsigned int num_of_type;
+};
+
+struct amdgpu_pmu_config {
+	struct amdgpu_pmu_attr *formats;
+	unsigned int num_formats;
+	struct amdgpu_pmu_attr *events;
+	unsigned int num_events;
+	struct amdgpu_pmu_type *types;
+	unsigned int num_types;
+};
+
+/*
+ * Events fall under two categories:
+ *  - PMU typed
+ *    Events in /sys/bus/event_source/devices/amdgpu_<pmu_type>_<dev_num> have
+ *    performance counter operations handled by one IP <pmu_type>.  Formats and
+ *    events should be defined by <pmu_type>_<asic_type>_formats and
+ *    <pmu_type>_<asic_type>_events respectively.
+ *
+ *  - Event config typed
+ *    Events in /sys/bus/event_source/devices/amdgpu_<dev_num> have performance
+ *    counter operations that can be handled by multiple IPs dictated by their
+ *    "type" format field.  Formats and events should be defined by
+ *    amdgpu_pmu_formats and <asic_type>_events respectively.  Format field
+ *    "type" is generated in amdgpu_pmu_event_show and defined in
+ *    <asic_type>_event_config_types.
+ */
+
+static struct amdgpu_pmu_attr amdgpu_pmu_formats[NUM_FORMATS_AMDGPU_PMU] = {
+	{ .name = "event", .config = "config:0-7" },
+	{ .name = "instance", .config = "config:8-15" },
+	{ .name = "umask", .config = "config:16-23"},
+	{ .name = "type", .config = "config:56-63"}
+};
+
+/* Vega20 events */
+static struct amdgpu_pmu_attr vega20_events[NUM_EVENTS_VEGA20_MAX] = {
+	{ .name = "xgmi_link0_data_outbound",
+			.config = "event=0x7,instance=0x46,umask=0x2" },
+	{ .name = "xgmi_link1_data_outbound",
+			.config = "event=0x7,instance=0x47,umask=0x2" }
+};
+
+static struct amdgpu_pmu_type vega20_types[NUM_EVENT_TYPES_VEGA20] = {
+	{ .type = AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI,
+					.num_of_type = NUM_EVENTS_VEGA20_XGMI }
+};
+
+static struct amdgpu_pmu_config vega20_config = {
+	.formats = amdgpu_pmu_formats,
+	.num_formats = ARRAY_SIZE(amdgpu_pmu_formats),
+	.events = vega20_events,
+	.num_events = ARRAY_SIZE(vega20_events),
+	.types = vega20_types,
+	.num_types = ARRAY_SIZE(vega20_types)
+};
+
+/* Vega20 data fabric (DF) events */
+static struct amdgpu_pmu_attr df_vega20_formats[NUM_FORMATS_DF_VEGA20] = {
+	{ .name = "event", .config = "config:0-7" },
+	{ .name = "instance", .config = "config:8-15" },
+	{ .name = "umask", .config = "config:16-23"}
+};
+
+static struct amdgpu_pmu_attr df_vega20_events[NUM_EVENTS_DF_VEGA20] = {
+	{ .name = "cake0_pcsout_txdata",
+			.config = "event=0x7,instance=0x46,umask=0x2" },
+	{ .name = "cake1_pcsout_txdata",
+			.config = "event=0x7,instance=0x47,umask=0x2" },
+	{ .name = "cake0_pcsout_txmeta",
+			.config = "event=0x7,instance=0x46,umask=0x4" },
+	{ .name = "cake1_pcsout_txmeta",
+			.config = "event=0x7,instance=0x47,umask=0x4" },
+	{ .name = "cake0_ftiinstat_reqalloc",
+			.config = "event=0xb,instance=0x46,umask=0x4" },
+	{ .name = "cake1_ftiinstat_reqalloc",
+			.config = "event=0xb,instance=0x47,umask=0x4" },
+	{ .name = "cake0_ftiinstat_rspalloc",
+			.config = "event=0xb,instance=0x46,umask=0x8" },
+	{ .name = "cake1_ftiinstat_rspalloc",
+			.config = "event=0xb,instance=0x47,umask=0x8" }
+};
+
+static struct amdgpu_pmu_config df_vega20_config = {
+	.formats = df_vega20_formats,
+	.num_formats = ARRAY_SIZE(df_vega20_formats),
+	.events = df_vega20_events,
+	.num_events = ARRAY_SIZE(df_vega20_events),
+	.types = NULL,
+	.num_types = 0
+};
+
+/* Arcturus events */
+static struct amdgpu_pmu_attr arcturus_events[NUM_EVENTS_ARCTURUS_MAX] = {
+	{ .name = "xgmi_link0_data_outbound",
+			.config = "event=0x7,instance=0x4b,umask=0x2" },
+	{ .name = "xgmi_link1_data_outbound",
+			.config = "event=0x7,instance=0x4c,umask=0x2" },
+	{ .name = "xgmi_link2_data_outbound",
+			.config = "event=0x7,instance=0x4d,umask=0x2" },
+	{ .name = "xgmi_link3_data_outbound",
+			.config = "event=0x7,instance=0x4e,umask=0x2" },
+	{ .name = "xgmi_link4_data_outbound",
+			.config = "event=0x7,instance=0x4f,umask=0x2" },
+	{ .name = "xgmi_link5_data_outbound",
+			.config = "event=0x7,instance=0x50,umask=0x2" }
+};
+
+static struct amdgpu_pmu_type arcturus_types[NUM_EVENT_TYPES_ARCTURUS] = {
+	{ .type = AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI,
+				.num_of_type = NUM_EVENTS_ARCTURUS_XGMI }
+};
+
+static struct amdgpu_pmu_config arcturus_config = {
+	.formats = amdgpu_pmu_formats,
+	.num_formats = ARRAY_SIZE(amdgpu_pmu_formats),
+	.events = arcturus_events,
+	.num_events = ARRAY_SIZE(arcturus_events),
+	.types = arcturus_types,
+	.num_types = ARRAY_SIZE(arcturus_types)
+};
+
 /* initialize perf counter */
 static int amdgpu_perf_event_init(struct perf_event *event)
 {
@@ -53,6 +216,7 @@ static int amdgpu_perf_event_init(struct perf_event *event)
 
 	/* update the hw_perf_event struct with config data */
 	hwc->config = event->attr.config;
+	hwc->config_base = AMDGPU_PMU_PERF_TYPE_NONE;
 
 	return 0;
 }
@@ -64,6 +228,7 @@ static void amdgpu_perf_start(struct perf_event *event, int flags)
 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,
 						  struct amdgpu_pmu_entry,
 						  pmu);
+	int target_cntr = 0;
 
 	if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
 		return;
@@ -71,19 +236,27 @@ static void amdgpu_perf_start(struct perf_event *event, int flags)
 	WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 	hwc->state = 0;
 
-	switch (pe->pmu_perf_type) {
-	case PERF_TYPE_AMDGPU_DF:
-		if (!(flags & PERF_EF_RELOAD))
-			pe->adev->df.funcs->pmc_start(pe->adev, hwc->config, 1);
+	switch (hwc->config_base) {
+	case AMDGPU_PMU_EVENT_CONFIG_TYPE_DF:
+	case AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI:
+		if (!(flags & PERF_EF_RELOAD)) {
+			target_cntr = pe->adev->df.funcs->pmc_start(pe->adev,
+						hwc->config, 0 /* unused */,
+						1 /* add counter */);
+			if (target_cntr < 0)
+				break;
+
+			hwc->idx = target_cntr;
+		}
 
-		pe->adev->df.funcs->pmc_start(pe->adev, hwc->config, 0);
+		pe->adev->df.funcs->pmc_start(pe->adev, hwc->config,
+								hwc->idx, 0);
 		break;
 	default:
 		break;
 	}
 
 	perf_event_update_userpage(event);
-
 }
 
 /* read perf counter */
@@ -93,16 +266,16 @@ static void amdgpu_perf_read(struct perf_event *event)
 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,
 						  struct amdgpu_pmu_entry,
 						  pmu);
-
 	u64 count, prev;
 
 	do {
 		prev = local64_read(&hwc->prev_count);
 
-		switch (pe->pmu_perf_type) {
-		case PERF_TYPE_AMDGPU_DF:
-			pe->adev->df.funcs->pmc_get_count(pe->adev, hwc->config,
-							  &count);
+		switch (hwc->config_base) {
+		case AMDGPU_PMU_EVENT_CONFIG_TYPE_DF:
+		case AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI:
+			pe->adev->df.funcs->pmc_get_count(pe->adev,
+						hwc->config, hwc->idx, &count);
 			break;
 		default:
 			count = 0;
@@ -124,9 +297,11 @@ static void amdgpu_perf_stop(struct perf_event *event, int flags)
 	if (hwc->state & PERF_HES_UPTODATE)
 		return;
 
-	switch (pe->pmu_perf_type) {
-	case PERF_TYPE_AMDGPU_DF:
-		pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, 0);
+	switch (hwc->config_base) {
+	case AMDGPU_PMU_EVENT_CONFIG_TYPE_DF:
+	case AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI:
+		pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, hwc->idx,
+									0);
 		break;
 	default:
 		break;
@@ -142,22 +317,39 @@ static void amdgpu_perf_stop(struct perf_event *event, int flags)
 	hwc->state |= PERF_HES_UPTODATE;
 }
 
-/* add perf counter  */
+/* add perf counter */
 static int amdgpu_perf_add(struct perf_event *event, int flags)
 {
 	struct hw_perf_event *hwc = &event->hw;
-	int retval;
-
+	int retval = 0, target_cntr;
 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,
 						  struct amdgpu_pmu_entry,
 						  pmu);
 
+	switch (pe->pmu_perf_type) {
+	case AMDGPU_PMU_PERF_TYPE_DF:
+		hwc->config_base = AMDGPU_PMU_EVENT_CONFIG_TYPE_DF;
+		break;
+	case AMDGPU_PMU_PERF_TYPE_ALL:
+		hwc->config_base = (hwc->config >>
+					AMDGPU_PMU_EVENT_CONFIG_TYPE_SHIFT) &
+					AMDGPU_PMU_EVENT_CONFIG_TYPE_MASK;
+		break;
+	}
+
 	event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 
-	switch (pe->pmu_perf_type) {
-	case PERF_TYPE_AMDGPU_DF:
-		retval = pe->adev->df.funcs->pmc_start(pe->adev,
-						       hwc->config, 1);
+	switch (hwc->config_base) {
+	case AMDGPU_PMU_EVENT_CONFIG_TYPE_DF:
+	case AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI:
+		target_cntr = pe->adev->df.funcs->pmc_start(pe->adev,
+						hwc->config, 0 /* unused */,
+						1 /* add counter */);
+		if (target_cntr < 0)
+			retval = target_cntr;
+		else
+			hwc->idx = target_cntr;
+
 		break;
 	default:
 		return 0;
@@ -170,7 +362,6 @@ static int amdgpu_perf_add(struct perf_event *event, int flags)
 		amdgpu_perf_start(event, PERF_EF_RELOAD);
 
 	return retval;
-
 }
 
 /* delete perf counter  */
@@ -183,9 +374,11 @@ static void amdgpu_perf_del(struct perf_event *event, int flags)
 
 	amdgpu_perf_stop(event, PERF_EF_UPDATE);
 
-	switch (pe->pmu_perf_type) {
-	case PERF_TYPE_AMDGPU_DF:
-		pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, 1);
+	switch (hwc->config_base) {
+	case AMDGPU_PMU_EVENT_CONFIG_TYPE_DF:
+	case AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI:
+		pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, hwc->idx,
+									1);
 		break;
 	default:
 		break;
@@ -194,25 +387,92 @@ static void amdgpu_perf_del(struct perf_event *event, int flags)
 	perf_event_update_userpage(event);
 }
 
-/* vega20 pmus */
+static void amdgpu_pmu_create_event_attrs_by_type(
+				struct attribute_group *attr_group,
+				struct amdgpu_pmu_event_attribute *pmu_attr,
+				struct amdgpu_pmu_attr events[],
+				int s_offset,
+				int e_offset,
+				unsigned int type)
+{
+	int i;
+
+	pmu_attr += s_offset;
+
+	for (i = s_offset; i < e_offset; i++) {
+		attr_group->attrs[i] = &pmu_attr->attr.attr;
+		sysfs_attr_init(&pmu_attr->attr.attr);
+		pmu_attr->attr.attr.name = events[i].name;
+		pmu_attr->attr.attr.mode = 0444;
+		pmu_attr->attr.show = amdgpu_pmu_event_show;
+		pmu_attr->event_str = events[i].config;
+		pmu_attr->type = type;
+		pmu_attr++;
+	}
+}
 
-/* init pmu tracking per pmu type */
-static int init_pmu_by_type(struct amdgpu_device *adev,
-		  const struct attribute_group *attr_groups[],
-		  char *pmu_type_name, char *pmu_file_prefix,
-		  unsigned int pmu_perf_type,
-		  unsigned int num_counters)
+static void amdgpu_pmu_create_attrs(struct attribute_group *attr_group,
+				struct amdgpu_pmu_event_attribute *pmu_attr,
+				struct amdgpu_pmu_attr events[],
+				int num_events)
 {
-	char pmu_name[PMU_NAME_SIZE];
-	struct amdgpu_pmu_entry *pmu_entry;
-	int ret = 0;
+	amdgpu_pmu_create_event_attrs_by_type(attr_group, pmu_attr, events, 0,
+				num_events, AMDGPU_PMU_EVENT_CONFIG_TYPE_NONE);
+}
 
-	pmu_entry = kzalloc(sizeof(struct amdgpu_pmu_entry), GFP_KERNEL);
 
-	if (!pmu_entry)
+static int amdgpu_pmu_alloc_pmu_attrs(
+				struct attribute_group *fmt_attr_group,
+				struct amdgpu_pmu_event_attribute **fmt_attr,
+				struct attribute_group *evt_attr_group,
+				struct amdgpu_pmu_event_attribute **evt_attr,
+				struct amdgpu_pmu_config *config)
+{
+	*fmt_attr = kcalloc(config->num_formats, sizeof(**fmt_attr),
+								GFP_KERNEL);
+
+	if (!(*fmt_attr))
 		return -ENOMEM;
 
-	pmu_entry->adev = adev;
+	fmt_attr_group->attrs = kcalloc(config->num_formats + 1,
+				sizeof(*fmt_attr_group->attrs), GFP_KERNEL);
+
+	if (!fmt_attr_group->attrs)
+		goto err_fmt_attr_grp;
+
+	*evt_attr = kcalloc(config->num_events, sizeof(**evt_attr), GFP_KERNEL);
+
+	if (!(*evt_attr))
+		goto err_evt_attr;
+
+	evt_attr_group->attrs = kcalloc(config->num_events + 1,
+				sizeof(*evt_attr_group->attrs), GFP_KERNEL);
+
+	if (!evt_attr_group->attrs)
+		goto err_evt_attr_grp;
+
+	return 0;
+err_evt_attr_grp:
+	kfree(*evt_attr);
+err_evt_attr:
+	kfree(fmt_attr_group->attrs);
+err_fmt_attr_grp:
+	kfree(*fmt_attr);
+	return -ENOMEM;
+}
+
+/* init pmu tracking per pmu type */
+static int init_pmu_entry_by_type_and_add(struct amdgpu_pmu_entry *pmu_entry,
+			struct amdgpu_pmu_config *config)
+{
+	const struct attribute_group *attr_groups[] = {
+		&pmu_entry->fmt_attr_group,
+		&pmu_entry->evt_attr_group,
+		NULL
+	};
+	char pmu_name[PMU_NAME_SIZE];
+	int ret = 0, total_num_events = 0;
+
 	pmu_entry->pmu = (struct pmu){
 		.event_init = amdgpu_perf_event_init,
 		.add = amdgpu_perf_add,
@@ -223,59 +483,178 @@ static int init_pmu_by_type(struct amdgpu_device *adev,
 		.task_ctx_nr = perf_invalid_context,
 	};
 
-	pmu_entry->pmu.attr_groups = attr_groups;
-	pmu_entry->pmu_perf_type = pmu_perf_type;
-	snprintf(pmu_name, PMU_NAME_SIZE, "%s_%d",
-				pmu_file_prefix, adev_to_drm(adev)->primary->index);
+	ret = amdgpu_pmu_alloc_pmu_attrs(&pmu_entry->fmt_attr_group,
+					&pmu_entry->fmt_attr,
+					&pmu_entry->evt_attr_group,
+					&pmu_entry->evt_attr,
+					config);
+
+	if (ret)
+		goto err_out;
+
+	amdgpu_pmu_create_attrs(&pmu_entry->fmt_attr_group, pmu_entry->fmt_attr,
+					config->formats, config->num_formats);
+
+	if (pmu_entry->pmu_perf_type == AMDGPU_PMU_PERF_TYPE_ALL) {
+		int i;
+
+		for (i = 0; i < config->num_types; i++) {
+			amdgpu_pmu_create_event_attrs_by_type(
+					&pmu_entry->evt_attr_group,
+					pmu_entry->evt_attr,
+					config->events,
+					total_num_events,
+					total_num_events +
+						config->types[i].num_of_type,
+					config->types[i].type);
+			total_num_events += config->types[i].num_of_type;
+		}
+	} else {
+		amdgpu_pmu_create_attrs(&pmu_entry->evt_attr_group,
+					pmu_entry->evt_attr,
+					config->events, config->num_events);
+		total_num_events = config->num_events;
+	}
+
+	pmu_entry->pmu.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
+								GFP_KERNEL);
+
+	if (!pmu_entry->pmu.attr_groups)
+		goto err_attr_group;
+
+	snprintf(pmu_name, PMU_NAME_SIZE, "%s_%d", pmu_entry->pmu_file_prefix,
+				adev_to_drm(pmu_entry->adev)->primary->index);
 
 	ret = perf_pmu_register(&pmu_entry->pmu, pmu_name, -1);
 
-	if (ret) {
-		kfree(pmu_entry);
-		pr_warn("Error initializing AMDGPU %s PMUs.\n", pmu_type_name);
-		return ret;
-	}
+	if (ret)
+		goto err_register;
+
+	if (pmu_entry->pmu_perf_type != AMDGPU_PMU_PERF_TYPE_ALL)
+		pr_info("Detected AMDGPU %s Counters. # of Counters = %d.\n",
+				pmu_entry->pmu_type_name, total_num_events);
+	else
+		pr_info("Detected AMDGPU %d Perf Events.\n", total_num_events);
 
-	pr_info("Detected AMDGPU %s Counters. # of Counters = %d.\n",
-			pmu_type_name, num_counters);
 
 	list_add_tail(&pmu_entry->entry, &amdgpu_pmu_list);
 
 	return 0;
+err_register:
+	kfree(pmu_entry->pmu.attr_groups);
+err_attr_group:
+	kfree(pmu_entry->fmt_attr_group.attrs);
+	kfree(pmu_entry->fmt_attr);
+	kfree(pmu_entry->evt_attr_group.attrs);
+	kfree(pmu_entry->evt_attr);
+err_out:
+	pr_warn("Error initializing AMDGPU %s PMUs.\n",
+						pmu_entry->pmu_type_name);
+	return ret;
+}
+
+/* destroy all pmu data associated with target device */
+void amdgpu_pmu_fini(struct amdgpu_device *adev)
+{
+	struct amdgpu_pmu_entry *pe, *temp;
+
+	list_for_each_entry_safe(pe, temp, &amdgpu_pmu_list, entry) {
+		if (pe->adev != adev)
+			continue;
+		list_del(&pe->entry);
+		perf_pmu_unregister(&pe->pmu);
+		kfree(pe->pmu.attr_groups);
+		kfree(pe->fmt_attr_group.attrs);
+		kfree(pe->fmt_attr);
+		kfree(pe->evt_attr_group.attrs);
+		kfree(pe->evt_attr);
+		kfree(pe);
+	}
+}
+
+static struct amdgpu_pmu_entry *create_pmu_entry(struct amdgpu_device *adev,
+						unsigned int pmu_type,
+						char *pmu_type_name,
+						char *pmu_file_prefix)
+{
+	struct amdgpu_pmu_entry *pmu_entry;
+
+	pmu_entry = kzalloc(sizeof(struct amdgpu_pmu_entry), GFP_KERNEL);
+
+	if (!pmu_entry)
+		return pmu_entry;
+
+	pmu_entry->adev = adev;
+	pmu_entry->fmt_attr_group.name = "format";
+	pmu_entry->fmt_attr_group.attrs = NULL;
+	pmu_entry->evt_attr_group.name = "events";
+	pmu_entry->evt_attr_group.attrs = NULL;
+	pmu_entry->pmu_perf_type = pmu_type;
+	pmu_entry->pmu_type_name = pmu_type_name;
+	pmu_entry->pmu_file_prefix = pmu_file_prefix;
+
+	return pmu_entry;
 }
 
 /* init amdgpu_pmu */
 int amdgpu_pmu_init(struct amdgpu_device *adev)
 {
 	int ret = 0;
+	struct amdgpu_pmu_entry *pmu_entry, *pmu_entry_df;
 
 	switch (adev->asic_type) {
 	case CHIP_VEGA20:
-		/* init df */
-		ret = init_pmu_by_type(adev, df_v3_6_attr_groups,
-				       "DF", "amdgpu_df", PERF_TYPE_AMDGPU_DF,
-				       DF_V3_6_MAX_COUNTERS);
+		pmu_entry_df = create_pmu_entry(adev, AMDGPU_PMU_PERF_TYPE_DF,
+						"DF", "amdgpu_df");
 
-		/* other pmu types go here*/
-		break;
-	default:
-		return 0;
-	}
+		if (!pmu_entry_df)
+			return -ENOMEM;
 
-	return 0;
-}
+		ret = init_pmu_entry_by_type_and_add(pmu_entry_df,
+							&df_vega20_config);
 
+		if (ret) {
+			kfree(pmu_entry_df);
+			return ret;
+		}
 
-/* destroy all pmu data associated with target device */
-void amdgpu_pmu_fini(struct amdgpu_device *adev)
-{
-	struct amdgpu_pmu_entry *pe, *temp;
+		pmu_entry = create_pmu_entry(adev, AMDGPU_PMU_PERF_TYPE_ALL,
+						"", "amdgpu");
 
-	list_for_each_entry_safe(pe, temp, &amdgpu_pmu_list, entry) {
-		if (pe->adev == adev) {
-			list_del(&pe->entry);
-			perf_pmu_unregister(&pe->pmu);
-			kfree(pe);
+		if (!pmu_entry) {
+			amdgpu_pmu_fini(adev);
+			return -ENOMEM;
+		}
+
+		ret = init_pmu_entry_by_type_and_add(pmu_entry,
+							&vega20_config);
+
+		if (ret) {
+			kfree(pmu_entry);
+			amdgpu_pmu_fini(adev);
+			return ret;
+		}
+
+		break;
+	case CHIP_ARCTURUS:
+		pmu_entry = create_pmu_entry(adev, AMDGPU_PMU_PERF_TYPE_ALL,
+						"", "amdgpu");
+		if (!pmu_entry)
+			return -ENOMEM;
+
+		ret = init_pmu_entry_by_type_and_add(pmu_entry,
+							&arcturus_config);
+
+		if (ret) {
+			kfree(pmu_entry);
+			return -ENOMEM;
 		}
+
+		break;
+
+	default:
+		return 0;
 	}
+
+	return ret;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
index 7dddb7160a11..6882dc48c5d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
@@ -19,18 +19,38 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Author: Jonathan Kim <jonathan.kim@amd.com>
- *
  */
 
 #ifndef _AMDGPU_PMU_H_
 #define _AMDGPU_PMU_H_
 
+/* PMU types. */
 enum amdgpu_pmu_perf_type {
-	PERF_TYPE_AMDGPU_DF = 0,
-	PERF_TYPE_AMDGPU_MAX
+	AMDGPU_PMU_PERF_TYPE_NONE = 0,
+	AMDGPU_PMU_PERF_TYPE_DF,
+	AMDGPU_PMU_PERF_TYPE_ALL
 };
 
+/*
+ * PMU type AMDGPU_PMU_PERF_TYPE_ALL can hold events of different "type"
+ * configurations.  Event config types are parsed from the 64-bit raw
+ * config (See EVENT_CONFIG_TYPE_SHIFT and EVENT_CONFIG_TYPE_MASK) and
+ * are registered into the HW perf events config_base.
+ *
+ * PMU types with only a single event configuration type
+ * (non-AMDGPU_PMU_PERF_TYPE_ALL) have their event config type auto generated
+ * when the performance counter is added.
+ */
+enum amdgpu_pmu_event_config_type {
+	AMDGPU_PMU_EVENT_CONFIG_TYPE_NONE = 0,
+	AMDGPU_PMU_EVENT_CONFIG_TYPE_DF,
+	AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI,
+	AMDGPU_PMU_EVENT_CONFIG_TYPE_MAX
+};
+
+#define AMDGPU_PMU_EVENT_CONFIG_TYPE_SHIFT	56
+#define AMDGPU_PMU_EVENT_CONFIG_TYPE_MASK	0xff
+
 int amdgpu_pmu_init(struct amdgpu_device *adev);
 void amdgpu_pmu_fini(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 96a9699f87ba..2b0a2b93994b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -100,6 +100,8 @@ static int psp_early_init(void *handle)
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		psp_v11_0_set_psp_funcs(psp);
 		psp->autoload_supported = true;
 		break;
@@ -288,6 +290,8 @@ psp_cmd_submit_buf(struct psp_context *psp,
 	skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 		psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 
+	memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
+
 	/* In some cases, psp response status is not 0 even there is no
 	 * problem while the command is submitted. Some version of PSP FW
 	 * doesn't write 0 to that field.
@@ -308,9 +312,6 @@ psp_cmd_submit_buf(struct psp_context *psp,
 		}
 	}
 
-	/* get xGMI session id from response buffer */
-	cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
-
 	if (ucode) {
 		ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 		ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
@@ -509,6 +510,37 @@ static int psp_tmr_terminate(struct psp_context *psp)
 	return 0;
 }
 
+int psp_get_fw_attestation_records_addr(struct psp_context *psp,
+					uint64_t *output_ptr)
+{
+	int ret;
+	struct psp_gfx_cmd_resp *cmd;
+
+	if (!output_ptr)
+		return -EINVAL;
+
+	if (amdgpu_sriov_vf(psp->adev))
+		return 0;
+
+	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
+	if (!cmd)
+		return -ENOMEM;
+
+	cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
+
+	ret = psp_cmd_submit_buf(psp, NULL, cmd,
+				 psp->fence_buf_mc_addr);
+
+	if (!ret) {
+		*output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
+			      ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
+	}
+
+	kfree(cmd);
+
+	return ret;
+}
+
 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 				uint64_t asd_mc, uint32_t size)
 {
@@ -624,14 +656,14 @@ static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 				     uint64_t ta_shared_mc,
 				     uint32_t ta_shared_size)
 {
-	cmd->cmd_id 				= GFX_CMD_ID_LOAD_TA;
+	cmd->cmd_id				= GFX_CMD_ID_LOAD_TA;
 	cmd->cmd.cmd_load_ta.app_phy_addr_lo 	= lower_32_bits(ta_bin_mc);
-	cmd->cmd.cmd_load_ta.app_phy_addr_hi 	= upper_32_bits(ta_bin_mc);
-	cmd->cmd.cmd_load_ta.app_len 		= ta_bin_size;
+	cmd->cmd.cmd_load_ta.app_phy_addr_hi	= upper_32_bits(ta_bin_mc);
+	cmd->cmd.cmd_load_ta.app_len		= ta_bin_size;
 
 	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
 	cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
-	cmd->cmd.cmd_load_ta.cmd_buf_len 	 = ta_shared_size;
+	cmd->cmd.cmd_load_ta.cmd_buf_len	 = ta_shared_size;
 }
 
 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
@@ -655,9 +687,9 @@ static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 				       uint32_t ta_cmd_id,
 				       uint32_t session_id)
 {
-	cmd->cmd_id 				= GFX_CMD_ID_INVOKE_CMD;
-	cmd->cmd.cmd_invoke_cmd.session_id 	= session_id;
-	cmd->cmd.cmd_invoke_cmd.ta_cmd_id 	= ta_cmd_id;
+	cmd->cmd_id				= GFX_CMD_ID_INVOKE_CMD;
+	cmd->cmd.cmd_invoke_cmd.session_id	= session_id;
+	cmd->cmd.cmd_invoke_cmd.ta_cmd_id	= ta_cmd_id;
 }
 
 static int psp_ta_invoke(struct psp_context *psp,
@@ -806,7 +838,7 @@ int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 	struct ta_xgmi_shared_memory *xgmi_cmd;
 	int ret;
 
-	xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
+	xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 
 	xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
@@ -826,7 +858,7 @@ int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 	struct ta_xgmi_shared_memory *xgmi_cmd;
 	int ret;
 
-	xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
+	xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 
 	xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
@@ -854,7 +886,7 @@ int psp_xgmi_get_topology_info(struct psp_context *psp,
 	if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 		return -EINVAL;
 
-	xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
+	xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 
 	/* Fill in the shared memory with topology information as input */
@@ -898,7 +930,7 @@ int psp_xgmi_set_topology_info(struct psp_context *psp,
 	if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 		return -EINVAL;
 
-	xgmi_cmd = (struct ta_xgmi_shared_memory*)psp->xgmi_context.xgmi_shared_buf;
+	xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 	memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 
 	topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
@@ -962,7 +994,7 @@ static int psp_ras_load(struct psp_context *psp)
 	ret = psp_cmd_submit_buf(psp, NULL, cmd,
 			psp->fence_buf_mc_addr);
 
-	ras_cmd = (struct ta_ras_shared_memory*)psp->ras.ras_shared_buf;
+	ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
 
 	if (!ret) {
 		psp->ras.session_id = cmd->resp.session_id;
@@ -1884,7 +1916,7 @@ static int psp_execute_np_fw_load(struct psp_context *psp,
 static int psp_load_smu_fw(struct psp_context *psp)
 {
 	int ret;
-	struct amdgpu_device* adev = psp->adev;
+	struct amdgpu_device *adev = psp->adev;
 	struct amdgpu_firmware_info *ucode =
 			&adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 	struct amdgpu_ras *ras = psp->ras.ras;
@@ -1950,7 +1982,7 @@ static int psp_np_fw_load(struct psp_context *psp)
 {
 	int i, ret;
 	struct amdgpu_firmware_info *ucode;
-	struct amdgpu_device* adev = psp->adev;
+	struct amdgpu_device *adev = psp->adev;
 
 	if (psp->autoload_supported &&
 	    !psp->pmfw_centralized_cstate_management) {
@@ -1974,8 +2006,8 @@ static int psp_np_fw_load(struct psp_context *psp)
 			continue;
 
 		if (psp->autoload_supported &&
-		    (adev->asic_type == CHIP_SIENNA_CICHLID ||
-		     adev->asic_type == CHIP_NAVY_FLOUNDER) &&
+		    (adev->asic_type >= CHIP_SIENNA_CICHLID &&
+		     adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
 		    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
 		     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
 		     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
@@ -2390,7 +2422,7 @@ int psp_init_asd_microcode(struct psp_context *psp,
 			   const char *chip_name)
 {
 	struct amdgpu_device *adev = psp->adev;
-	char fw_name[30];
+	char fw_name[PSP_FW_NAME_LEN];
 	const struct psp_firmware_header_v1_0 *asd_hdr;
 	int err = 0;
 
@@ -2422,11 +2454,47 @@ out:
 	return err;
 }
 
-int psp_init_sos_microcode(struct psp_context *psp,
+int psp_init_toc_microcode(struct psp_context *psp,
 			   const char *chip_name)
 {
 	struct amdgpu_device *adev = psp->adev;
 	char fw_name[30];
+	const struct psp_firmware_header_v1_0 *toc_hdr;
+	int err = 0;
+
+	if (!chip_name) {
+		dev_err(adev->dev, "invalid chip name for toc microcode\n");
+		return -EINVAL;
+	}
+
+	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
+	err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
+	if (err)
+		goto out;
+
+	err = amdgpu_ucode_validate(adev->psp.toc_fw);
+	if (err)
+		goto out;
+
+	toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
+	adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
+	adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
+	adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
+	adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
+				le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
+	return 0;
+out:
+	dev_err(adev->dev, "fail to request/validate toc microcode\n");
+	release_firmware(adev->psp.toc_fw);
+	adev->psp.toc_fw = NULL;
+	return err;
+}
+
+int psp_init_sos_microcode(struct psp_context *psp,
+			   const char *chip_name)
+{
+	struct amdgpu_device *adev = psp->adev;
+	char fw_name[PSP_FW_NAME_LEN];
 	const struct psp_firmware_header_v1_0 *sos_hdr;
 	const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
 	const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
@@ -2520,10 +2588,11 @@ int parse_ta_bin_descriptor(struct psp_context *psp,
 
 	switch (desc->fw_type) {
 	case TA_FW_TYPE_PSP_ASD:
-		psp->asd_fw_version 	   = le32_to_cpu(desc->fw_version);
+		psp->asd_fw_version	   = le32_to_cpu(desc->fw_version);
 		psp->asd_feature_version   = le32_to_cpu(desc->fw_version);
-		psp->asd_ucode_size 	   = le32_to_cpu(desc->size_bytes);
+		psp->asd_ucode_size	   = le32_to_cpu(desc->size_bytes);
 		psp->asd_start_addr 	   = ucode_start_addr;
+		psp->asd_fw                = psp->ta_fw;
 		break;
 	case TA_FW_TYPE_PSP_XGMI:
 		psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 919d2fb7427b..da250bc1ac57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -41,6 +41,7 @@
 #define PSP_DTM_SHARED_MEM_SIZE	0x4000
 #define PSP_RAP_SHARED_MEM_SIZE	0x4000
 #define PSP_SHARED_MEM_SIZE		0x4000
+#define PSP_FW_NAME_LEN		0x24
 
 struct psp_context;
 struct psp_xgmi_node_info;
@@ -253,6 +254,11 @@ struct psp_context
 	uint32_t			asd_ucode_size;
 	uint8_t				*asd_start_addr;
 
+	/* toc firmware */
+	const struct firmware		*toc_fw;
+	uint32_t			toc_fw_version;
+	uint32_t			toc_feature_version;
+
 	/* fence buffer */
 	struct amdgpu_bo		*fence_buf_bo;
 	uint64_t			fence_buf_mc_addr;
@@ -386,8 +392,12 @@ int psp_ring_cmd_submit(struct psp_context *psp,
 			int index);
 int psp_init_asd_microcode(struct psp_context *psp,
 			   const char *chip_name);
+int psp_init_toc_microcode(struct psp_context *psp,
+			   const char *chip_name);
 int psp_init_sos_microcode(struct psp_context *psp,
 			   const char *chip_name);
 int psp_init_ta_microcode(struct psp_context *psp,
 			  const char *chip_name);
+int psp_get_fw_attestation_records_addr(struct psp_context *psp,
+					uint64_t *output_ptr);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 4e36551ab50b..b96267068a72 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -80,6 +80,8 @@ enum amdgpu_ras_retire_page_reservation {
 
 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 
+static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
+				uint64_t addr);
 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 				uint64_t addr);
 
@@ -516,9 +518,9 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 /* obj end */
 
 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
-				  const char* 		invoke_type,
-				  const char* 		block_name,
-				  enum ta_ras_status 	ret)
+					 const char* invoke_type,
+					 const char* block_name,
+					 enum ta_ras_status ret)
 {
 	switch (ret) {
 	case TA_RAS_STATUS__SUCCESS:
@@ -607,7 +609,7 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 	if (!con)
 		return -EINVAL;
 
-        info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
+	info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 	if (!info)
 		return -ENOMEM;
 
@@ -953,7 +955,7 @@ static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
 	case AMDGPU_RAS_RETIRE_PAGE_FAULT:
 	default:
 		return "F";
-	};
+	}
 }
 
 /**
@@ -1551,10 +1553,12 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
 			.size = AMDGPU_GPU_PAGE_SIZE,
 			.flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 		};
-
-		if (data->last_reserved <= i)
+		ret = amdgpu_vram_mgr_query_page_status(
+				ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
+				data->bps[i].retired_page);
+		if (ret == -EBUSY)
 			(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
-		else if (data->bps_bo[i] == NULL)
+		else if (ret == -ENOENT)
 			(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
 	}
 
@@ -1606,12 +1610,9 @@ static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
 	unsigned int new_space = old_space + pages;
 	unsigned int align_space = ALIGN(new_space, 512);
 	void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
-	struct amdgpu_bo **bps_bo =
-			kmalloc(align_space * sizeof(*data->bps_bo), GFP_KERNEL);
 
-	if (!bps || !bps_bo) {
+	if (!bps) {
 		kfree(bps);
-		kfree(bps_bo);
 		return -ENOMEM;
 	}
 
@@ -1620,14 +1621,8 @@ static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
 				data->count * sizeof(*data->bps));
 		kfree(data->bps);
 	}
-	if (data->bps_bo) {
-		memcpy(bps_bo, data->bps_bo,
-				data->count * sizeof(*data->bps_bo));
-		kfree(data->bps_bo);
-	}
 
 	data->bps = bps;
-	data->bps_bo = bps_bo;
 	data->space_left += align_space - old_space;
 	return 0;
 }
@@ -1639,6 +1634,7 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 	struct ras_err_handler_data *data;
 	int ret = 0;
+	uint32_t i;
 
 	if (!con || !con->eh_data || !bps || pages <= 0)
 		return 0;
@@ -1648,16 +1644,26 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
 	if (!data)
 		goto out;
 
-	if (data->space_left <= pages)
-		if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) {
+	for (i = 0; i < pages; i++) {
+		if (amdgpu_ras_check_bad_page_unlock(con,
+			bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
+			continue;
+
+		if (!data->space_left &&
+			amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
 			ret = -ENOMEM;
 			goto out;
 		}
 
-	memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps));
-	data->count += pages;
-	data->space_left -= pages;
+		amdgpu_vram_mgr_reserve_range(
+			ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
+			bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
+			AMDGPU_GPU_PAGE_SIZE);
 
+		memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
+		data->count++;
+		data->space_left--;
+	}
 out:
 	mutex_unlock(&con->recovery_lock);
 
@@ -1668,7 +1674,7 @@ out:
  * write error record array to eeprom, the function should be
  * protected by recovery_lock
  */
-static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
+int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
 {
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 	struct ras_err_handler_data *data;
@@ -1730,6 +1736,20 @@ out:
 	return ret;
 }
 
+static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
+				uint64_t addr)
+{
+	struct ras_err_handler_data *data = con->eh_data;
+	int i;
+
+	addr >>= AMDGPU_GPU_PAGE_SHIFT;
+	for (i = 0; i < data->count; i++)
+		if (addr == data->bps[i].retired_page)
+			return true;
+
+	return false;
+}
+
 /*
  * check if an address belongs to bad page
  *
@@ -1739,26 +1759,13 @@ static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 				uint64_t addr)
 {
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
-	struct ras_err_handler_data *data;
-	int i;
 	bool ret = false;
 
 	if (!con || !con->eh_data)
 		return ret;
 
 	mutex_lock(&con->recovery_lock);
-	data = con->eh_data;
-	if (!data)
-		goto out;
-
-	addr >>= AMDGPU_GPU_PAGE_SHIFT;
-	for (i = 0; i < data->count; i++)
-		if (addr == data->bps[i].retired_page) {
-			ret = true;
-			goto out;
-		}
-
-out:
+	ret = amdgpu_ras_check_bad_page_unlock(con, addr);
 	mutex_unlock(&con->recovery_lock);
 	return ret;
 }
@@ -1804,80 +1811,6 @@ static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
 	}
 }
 
-/* called in gpu recovery/init */
-int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev)
-{
-	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
-	struct ras_err_handler_data *data;
-	uint64_t bp;
-	struct amdgpu_bo *bo = NULL;
-	int i, ret = 0;
-
-	/* Not reserve bad page when amdgpu_bad_page_threshold == 0. */
-	if (!con || !con->eh_data || (amdgpu_bad_page_threshold == 0))
-		return 0;
-
-	mutex_lock(&con->recovery_lock);
-	data = con->eh_data;
-	if (!data)
-		goto out;
-	/* reserve vram at driver post stage. */
-	for (i = data->last_reserved; i < data->count; i++) {
-		bp = data->bps[i].retired_page;
-
-		/* There are two cases of reserve error should be ignored:
-		 * 1) a ras bad page has been allocated (used by someone);
-		 * 2) a ras bad page has been reserved (duplicate error injection
-		 *    for one page);
-		 */
-		if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,
-					       AMDGPU_GPU_PAGE_SIZE,
-					       AMDGPU_GEM_DOMAIN_VRAM,
-					       &bo, NULL))
-			dev_warn(adev->dev, "RAS WARN: reserve vram for "
-					"retired page %llx fail\n", bp);
-
-		data->bps_bo[i] = bo;
-		data->last_reserved = i + 1;
-		bo = NULL;
-	}
-
-	/* continue to save bad pages to eeprom even reesrve_vram fails */
-	ret = amdgpu_ras_save_bad_pages(adev);
-out:
-	mutex_unlock(&con->recovery_lock);
-	return ret;
-}
-
-/* called when driver unload */
-static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev)
-{
-	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
-	struct ras_err_handler_data *data;
-	struct amdgpu_bo *bo;
-	int i;
-
-	if (!con || !con->eh_data)
-		return 0;
-
-	mutex_lock(&con->recovery_lock);
-	data = con->eh_data;
-	if (!data)
-		goto out;
-
-	for (i = data->last_reserved - 1; i >= 0; i--) {
-		bo = data->bps_bo[i];
-
-		amdgpu_bo_free_kernel(&bo, NULL, NULL);
-
-		data->bps_bo[i] = bo;
-		data->last_reserved = i;
-	}
-out:
-	mutex_unlock(&con->recovery_lock);
-	return 0;
-}
-
 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
 {
 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
@@ -1917,18 +1850,12 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
 		ret = amdgpu_ras_load_bad_pages(adev);
 		if (ret)
 			goto free;
-		ret = amdgpu_ras_reserve_bad_pages(adev);
-		if (ret)
-			goto release;
 	}
 
 	return 0;
 
-release:
-	amdgpu_ras_release_bad_pages(adev);
 free:
 	kfree((*data)->bps);
-	kfree((*data)->bps_bo);
 	kfree(*data);
 	con->eh_data = NULL;
 out:
@@ -1956,12 +1883,10 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
 		return 0;
 
 	cancel_work_sync(&con->recovery_work);
-	amdgpu_ras_release_bad_pages(adev);
 
 	mutex_lock(&con->recovery_lock);
 	con->eh_data = NULL;
 	kfree(data->bps);
-	kfree(data->bps_bo);
 	kfree(data);
 	mutex_unlock(&con->recovery_lock);
 
@@ -2156,7 +2081,7 @@ void amdgpu_ras_late_fini(struct amdgpu_device *adev,
 
 	amdgpu_ras_sysfs_remove(adev, ras_block);
 	if (ih_info->cb)
-                amdgpu_ras_interrupt_remove_handler(adev, ih_info);
+		amdgpu_ras_interrupt_remove_handler(adev, ih_info);
 	amdgpu_ras_feature_enable(adev, ras_block, 0);
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
index 6b8d7bb83bb3..4667cce38582 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
@@ -33,7 +33,6 @@
 
 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS		(0x1 << 0)
 #define AMDGPU_RAS_FLAG_INIT_NEED_RESET		(0x1 << 1)
-#define AMDGPU_RAS_FLAG_SKIP_BAD_PAGE_RESV	(0x1 << 2)
 
 enum amdgpu_ras_block {
 	AMDGPU_RAS_BLOCK__UMC = 0,
@@ -363,14 +362,10 @@ struct ras_err_data {
 struct ras_err_handler_data {
 	/* point to bad page records array */
 	struct eeprom_table_record *bps;
-	/* point to reserved bo array */
-	struct amdgpu_bo **bps_bo;
 	/* the count of entries */
 	int count;
 	/* the space can place new entries */
 	int space_left;
-	/* last reserved entry's index + 1 */
-	int last_reserved;
 };
 
 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
@@ -506,22 +501,12 @@ bool amdgpu_ras_check_err_threshold(struct amdgpu_device *adev);
 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
 		struct eeprom_table_record *bps, int pages);
 
-int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev);
+int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev);
 
 static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
 {
 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 
-	/*
-	 * Save bad page to eeprom before gpu reset, i2c may be unstable
-	 * in gpu reset.
-	 *
-	 * Also, exclude the case when ras recovery issuer is
-	 * eeprom page write itself.
-	 */
-	if (!(ras->flags & AMDGPU_RAS_FLAG_SKIP_BAD_PAGE_RESV) && in_task())
-		amdgpu_ras_reserve_bad_pages(adev);
-
 	if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
 		schedule_work(&ras->recovery_work);
 	return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 0e64c39a2372..1dd040166c63 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -27,9 +27,9 @@
 #include <linux/bits.h>
 #include "atom.h"
 
-#define EEPROM_I2C_TARGET_ADDR_VEGA20    	0xA0
-#define EEPROM_I2C_TARGET_ADDR_ARCTURUS  	0xA8
-#define EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342  	0xA0
+#define EEPROM_I2C_TARGET_ADDR_VEGA20		0xA0
+#define EEPROM_I2C_TARGET_ADDR_ARCTURUS		0xA8
+#define EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342	0xA0
 
 /*
  * The 2 macros bellow represent the actual size in bytes that
@@ -124,11 +124,11 @@ static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_heade
 {
 	uint32_t *pp = (uint32_t *)buff;
 
-	hdr->header 	      = le32_to_cpu(pp[0]);
-	hdr->version 	      = le32_to_cpu(pp[1]);
+	hdr->header	      = le32_to_cpu(pp[0]);
+	hdr->version	      = le32_to_cpu(pp[1]);
 	hdr->first_rec_offset = le32_to_cpu(pp[2]);
-	hdr->tbl_size 	      = le32_to_cpu(pp[3]);
-	hdr->checksum 	      = le32_to_cpu(pp[4]);
+	hdr->tbl_size	      = le32_to_cpu(pp[3]);
+	hdr->checksum	      = le32_to_cpu(pp[4]);
 }
 
 static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
@@ -149,7 +149,11 @@ static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
 
 	msg.addr = control->i2c_address;
 
+	/* i2c may be unstable in gpu reset */
+	down_read(&adev->reset_sem);
 	ret = i2c_transfer(&adev->pm.smu_i2c, &msg, 1);
+	up_read(&adev->reset_sem);
+
 	if (ret < 1)
 		DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret);
 
@@ -475,7 +479,6 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
 	int i, ret = 0;
 	struct i2c_msg *msgs, *msg;
 	unsigned char *buffs, *buff;
-	bool sched_ras_recovery = false;
 	struct eeprom_table_record *record;
 	struct amdgpu_device *adev = to_amdgpu_device(control);
 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
@@ -513,7 +516,6 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
 			"Saved bad pages(%d) reaches threshold value(%d).\n",
 			control->num_recs + num, ras->bad_page_cnt_threshold);
 		control->tbl_hdr.header = EEPROM_TABLE_HDR_BAD;
-		sched_ras_recovery = true;
 	}
 
 	/* In case of overflow just start from beginning to not lose newest records */
@@ -557,7 +559,11 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
 		control->next_addr += EEPROM_TABLE_RECORD_SIZE;
 	}
 
+	/* i2c may be unstable in gpu reset */
+	down_read(&adev->reset_sem);
 	ret = i2c_transfer(&adev->pm.smu_i2c, msgs, num);
+	up_read(&adev->reset_sem);
+
 	if (ret < 1) {
 		DRM_ERROR("Failed to process EEPROM table records, ret:%d", ret);
 
@@ -595,20 +601,6 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
 		__update_tbl_checksum(control, records, num, old_hdr_byte_sum);
 
 		__update_table_header(control, buffs);
-
-		if (sched_ras_recovery) {
-			/*
-			 * Before scheduling ras recovery, assert the related
-			 * flag first, which shall bypass common bad page
-			 * reservation execution in amdgpu_ras_reset_gpu.
-			 */
-			amdgpu_ras_get_context(adev)->flags |=
-				AMDGPU_RAS_FLAG_SKIP_BAD_PAGE_RESV;
-
-			dev_warn(adev->dev, "Conduct ras recovery due to bad "
-				"page threshold reached.\n");
-			amdgpu_ras_reset_gpu(adev);
-		}
 	} else if (!__validate_tbl_checksum(control, records, num)) {
 		DRM_WARN("EEPROM Table checksum mismatch!");
 		/* TODO Uncomment when EEPROM read/write is relliable */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 15ee13c3bd9e..2697b250dc32 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -396,7 +396,7 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
 			return result;
 
 		value = ring->ring[(*pos - 12)/4];
-		r = put_user(value, (uint32_t*)buf);
+		r = put_user(value, (uint32_t *)buf);
 		if (r)
 			return r;
 		buf += 4;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index 0bd1d4ffc19e..524d10b21041 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -75,7 +75,7 @@ int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
 }
 
 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
-                              struct amdgpu_sa_manager *sa_manager)
+			       struct amdgpu_sa_manager *sa_manager)
 {
 	struct amdgpu_sa_bo *sa_bo, *tmp;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 250a309e4dee..de91d29c9d96 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -126,7 +126,7 @@ int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
 		goto free;
 	}
 
-        return 0;
+	return 0;
 
 late_fini:
 	amdgpu_ras_late_fini(adev, adev->sdma.ras_if, ih_info);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
index 2f4d5ca9894f..6042b3b81a4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
@@ -157,10 +157,10 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
 					  i, *vram_start, gart_start,
 					  (unsigned long long)
 					  (gart_addr - adev->gmc.gart_start +
-					   (void*)gart_start - gtt_map),
+					   (void *)gart_start - gtt_map),
 					  (unsigned long long)
 					  (vram_addr - adev->gmc.vram_start +
-					   (void*)gart_start - gtt_map));
+					   (void *)gart_start - gtt_map));
 				amdgpu_bo_kunmap(vram_obj);
 				goto out_lclean_unpin;
 			}
@@ -203,10 +203,10 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
 					  i, *gart_start, vram_start,
 					  (unsigned long long)
 					  (vram_addr - adev->gmc.vram_start +
-					   (void*)vram_start - vram_map),
+					   (void *)vram_start - vram_map),
 					  (unsigned long long)
 					  (gart_addr - adev->gmc.gart_start +
-					   (void*)vram_start - vram_map));
+					   (void *)vram_start - vram_map));
 				amdgpu_bo_kunmap(gtt_obj[i]);
 				goto out_lclean_unpin;
 			}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c01c060e4ac5..12aa35ac0eb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -70,10 +70,10 @@ static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
 
 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
 				    unsigned int type,
-				    uint64_t size)
+				    uint64_t size_in_page)
 {
 	return ttm_range_man_init(&adev->mman.bdev, type,
-				  false, size >> PAGE_SHIFT);
+				  false, size_in_page);
 }
 
 /**
@@ -1008,7 +1008,7 @@ void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 }
 
 /**
- * amdgpu_ttm_tt_pin_userptr - 	prepare the sg table with the user pages
+ * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
  *
  * Called by amdgpu_ttm_backend_bind()
  **/
@@ -1198,7 +1198,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 {
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 	struct ttm_operation_ctx ctx = { false, false };
-	struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
+	struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 	struct ttm_resource tmp;
 	struct ttm_placement placement;
 	struct ttm_place placements;
@@ -1449,7 +1449,7 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
 			return -ENOMEM;
 	}
 
-	gtt = (void*)bo->ttm;
+	gtt = (void *)bo->ttm;
 	gtt->userptr = addr;
 	gtt->userflags = flags;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index a87951b2f06d..bdca2970173e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -37,10 +37,17 @@
 
 #define AMDGPU_POISON	0xd0bed0be
 
+struct amdgpu_vram_reservation {
+	struct list_head node;
+	struct drm_mm_node mm_node;
+};
+
 struct amdgpu_vram_mgr {
 	struct ttm_resource_manager manager;
 	struct drm_mm mm;
 	spinlock_t lock;
+	struct list_head reservations_pending;
+	struct list_head reserved_pages;
 	atomic64_t usage;
 	atomic64_t vis_usage;
 };
@@ -54,7 +61,6 @@ struct amdgpu_gtt_mgr {
 
 struct amdgpu_mman {
 	struct ttm_bo_device		bdev;
-	bool				mem_global_referenced;
 	bool				initialized;
 	void __iomem			*aper_base_kaddr;
 
@@ -119,6 +125,10 @@ void amdgpu_vram_mgr_free_sgt(struct amdgpu_device *adev,
 			      struct sg_table *sgt);
 uint64_t amdgpu_vram_mgr_usage(struct ttm_resource_manager *man);
 uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_resource_manager *man);
+int amdgpu_vram_mgr_reserve_range(struct ttm_resource_manager *man,
+				  uint64_t start, uint64_t size);
+int amdgpu_vram_mgr_query_page_status(struct ttm_resource_manager *man,
+				      uint64_t start);
 
 int amdgpu_ttm_init(struct amdgpu_device *adev);
 void amdgpu_ttm_late_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index b313ce4c3e97..2b7c90b7a712 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -391,6 +391,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		if (!load_type)
 			return AMDGPU_FW_LOAD_DIRECT;
 		else
@@ -586,8 +588,8 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
 {
 	const struct gfx_firmware_header_v1_0 *header = NULL;
 	const struct common_firmware_header *comm_hdr = NULL;
-	uint8_t* src_addr = NULL;
-	uint8_t* dst_addr = NULL;
+	uint8_t *src_addr = NULL;
+	uint8_t *dst_addr = NULL;
 
 	if (NULL == ucode->fw)
 		return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
index 262baf0f61ea..a2975c8092a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
@@ -126,10 +126,11 @@ int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
 				err_data->ue_count);
 
 		if ((amdgpu_bad_page_threshold != 0) &&
-			err_data->err_addr_cnt &&
+			err_data->err_addr_cnt) {
 			amdgpu_ras_add_bad_pages(adev, err_data->err_addr,
-						err_data->err_addr_cnt))
-			dev_warn(adev->dev, "Failed to add ras bad page!\n");
+						err_data->err_addr_cnt);
+			amdgpu_ras_save_bad_pages(adev);
+		}
 
 		amdgpu_ras_reset_gpu(adev);
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index f3b7287e84c4..7e19a6656715 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -37,24 +37,30 @@
 #define FIRMWARE_RAVEN		"amdgpu/raven_vcn.bin"
 #define FIRMWARE_PICASSO	"amdgpu/picasso_vcn.bin"
 #define FIRMWARE_RAVEN2		"amdgpu/raven2_vcn.bin"
-#define FIRMWARE_ARCTURUS 	"amdgpu/arcturus_vcn.bin"
-#define FIRMWARE_RENOIR 	"amdgpu/renoir_vcn.bin"
-#define FIRMWARE_NAVI10 	"amdgpu/navi10_vcn.bin"
-#define FIRMWARE_NAVI14 	"amdgpu/navi14_vcn.bin"
-#define FIRMWARE_NAVI12 	"amdgpu/navi12_vcn.bin"
-#define FIRMWARE_SIENNA_CICHLID 	"amdgpu/sienna_cichlid_vcn.bin"
-#define FIRMWARE_NAVY_FLOUNDER 	"amdgpu/navy_flounder_vcn.bin"
+#define FIRMWARE_ARCTURUS	"amdgpu/arcturus_vcn.bin"
+#define FIRMWARE_RENOIR		"amdgpu/renoir_vcn.bin"
+#define FIRMWARE_GREEN_SARDINE	"amdgpu/green_sardine_vcn.bin"
+#define FIRMWARE_NAVI10		"amdgpu/navi10_vcn.bin"
+#define FIRMWARE_NAVI14		"amdgpu/navi14_vcn.bin"
+#define FIRMWARE_NAVI12		"amdgpu/navi12_vcn.bin"
+#define FIRMWARE_SIENNA_CICHLID	"amdgpu/sienna_cichlid_vcn.bin"
+#define FIRMWARE_NAVY_FLOUNDER	"amdgpu/navy_flounder_vcn.bin"
+#define FIRMWARE_VANGOGH	"amdgpu/vangogh_vcn.bin"
+#define FIRMWARE_DIMGREY_CAVEFISH	"amdgpu/dimgrey_cavefish_vcn.bin"
 
 MODULE_FIRMWARE(FIRMWARE_RAVEN);
 MODULE_FIRMWARE(FIRMWARE_PICASSO);
 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
 MODULE_FIRMWARE(FIRMWARE_RENOIR);
+MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
 MODULE_FIRMWARE(FIRMWARE_NAVI10);
 MODULE_FIRMWARE(FIRMWARE_NAVI14);
 MODULE_FIRMWARE(FIRMWARE_NAVI12);
 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
+MODULE_FIRMWARE(FIRMWARE_VANGOGH);
+MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
 
 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
 
@@ -89,7 +95,11 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 			adev->vcn.indirect_sram = true;
 		break;
 	case CHIP_RENOIR:
-		fw_name = FIRMWARE_RENOIR;
+		if (adev->apu_flags & AMD_APU_IS_RENOIR)
+			fw_name = FIRMWARE_RENOIR;
+		else
+			fw_name = FIRMWARE_GREEN_SARDINE;
+
 		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
 		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 			adev->vcn.indirect_sram = true;
@@ -124,6 +134,15 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 			adev->vcn.indirect_sram = true;
 		break;
+	case CHIP_VANGOGH:
+		fw_name = FIRMWARE_VANGOGH;
+		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		fw_name = FIRMWARE_DIMGREY_CAVEFISH;
+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+			adev->vcn.indirect_sram = true;
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -313,6 +332,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 		container_of(work, struct amdgpu_device, vcn.idle_work.work);
 	unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
 	unsigned int i, j;
+	int r = 0;
 
 	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 		if (adev->vcn.harvest_config & (1 << j))
@@ -339,8 +359,13 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 	}
 
 	if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
+		amdgpu_gfx_off_ctrl(adev, true);
 		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 		       AMD_PG_STATE_GATE);
+		r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
+				false);
+		if (r)
+			dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
 	} else {
 		schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
 	}
@@ -349,9 +374,17 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
+	int r = 0;
 
 	atomic_inc(&adev->vcn.total_submission_cnt);
-	cancel_delayed_work_sync(&adev->vcn.idle_work);
+
+	if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
+		amdgpu_gfx_off_ctrl(adev, false);
+		r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
+				true);
+		if (r)
+			dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
+	}
 
 	mutex_lock(&adev->vcn.vcn_pg_lock);
 	amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c
index 7f7097931c6f..f9d3d79f68b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.c
@@ -59,7 +59,7 @@ void amdgpu_vf_error_trans_all(struct amdgpu_device *adev)
 		return;
 	}
 /*
- 	TODO: Enable these code when pv2vf_info is merged
+	TODO: Enable these code when pv2vf_info is merged
 	AMDGPU_FW_VRAM_PF2VF_READ (adev, feature_flags, &pf2vf_flags);
 	if (!(pf2vf_flags & AMDGIM_FEATURE_ERROR_LOG_COLLECT)) {
 		return;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 38b59a4fc04c..0768c8686983 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -300,7 +300,7 @@ static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
 {
 	spin_lock(&vm_bo->vm->invalidated_lock);
-	list_del_init(&vm_bo->vm_status);
+	list_move(&vm_bo->vm_status, &vm_bo->vm->done);
 	spin_unlock(&vm_bo->vm->invalidated_lock);
 }
 
@@ -1570,7 +1570,8 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
 /**
  * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
  *
- * @adev: amdgpu_device pointer
+ * @adev: amdgpu_device pointer of the VM
+ * @bo_adev: amdgpu_device pointer of the mapped BO
  * @vm: requested vm
  * @immediate: immediate submission in a page fault
  * @unlocked: unlocked invalidation during MM callback
@@ -1578,7 +1579,8 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
  * @start: start of mapped range
  * @last: last mapped entry
  * @flags: flags for the entries
- * @addr: addr to set the area to
+ * @offset: offset into nodes and pages_addr
+ * @nodes: array of drm_mm_nodes with the MC addresses
  * @pages_addr: DMA addresses to use for mapping
  * @fence: optional resulting fence
  *
@@ -1588,15 +1590,18 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
  * 0 for success, -EINVAL for failure.
  */
 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
+				       struct amdgpu_device *bo_adev,
 				       struct amdgpu_vm *vm, bool immediate,
 				       bool unlocked, struct dma_resv *resv,
 				       uint64_t start, uint64_t last,
-				       uint64_t flags, uint64_t addr,
+				       uint64_t flags, uint64_t offset,
+				       struct drm_mm_node *nodes,
 				       dma_addr_t *pages_addr,
 				       struct dma_fence **fence)
 {
 	struct amdgpu_vm_update_params params;
 	enum amdgpu_sync_mode sync_mode;
+	uint64_t pfn;
 	int r;
 
 	memset(&params, 0, sizeof(params));
@@ -1614,6 +1619,14 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 	else
 		sync_mode = AMDGPU_SYNC_EXPLICIT;
 
+	pfn = offset >> PAGE_SHIFT;
+	if (nodes) {
+		while (pfn >= nodes->size) {
+			pfn -= nodes->size;
+			++nodes;
+		}
+	}
+
 	amdgpu_vm_eviction_lock(vm);
 	if (vm->evicting) {
 		r = -EBUSY;
@@ -1632,105 +1645,47 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 	if (r)
 		goto error_unlock;
 
-	r = amdgpu_vm_update_ptes(&params, start, last + 1, addr, flags);
-	if (r)
-		goto error_unlock;
-
-	r = vm->update_funcs->commit(&params, fence);
-
-error_unlock:
-	amdgpu_vm_eviction_unlock(vm);
-	return r;
-}
-
-/**
- * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
- *
- * @adev: amdgpu_device pointer
- * @resv: fences we need to sync to
- * @pages_addr: DMA addresses to use for mapping
- * @vm: requested vm
- * @mapping: mapped range and flags to use for the update
- * @flags: HW flags for the mapping
- * @bo_adev: amdgpu_device pointer that bo actually been allocated
- * @nodes: array of drm_mm_nodes with the MC addresses
- * @fence: optional resulting fence
- *
- * Split the mapping into smaller chunks so that each update fits
- * into a SDMA IB.
- *
- * Returns:
- * 0 for success, -EINVAL for failure.
- */
-static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
-				      struct dma_resv *resv,
-				      dma_addr_t *pages_addr,
-				      struct amdgpu_vm *vm,
-				      struct amdgpu_bo_va_mapping *mapping,
-				      uint64_t flags,
-				      struct amdgpu_device *bo_adev,
-				      struct drm_mm_node *nodes,
-				      struct dma_fence **fence)
-{
-	unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
-	uint64_t pfn, start = mapping->start;
-	int r;
-
-	/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
-	 * but in case of something, we filter the flags in first place
-	 */
-	if (!(mapping->flags & AMDGPU_PTE_READABLE))
-		flags &= ~AMDGPU_PTE_READABLE;
-	if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
-		flags &= ~AMDGPU_PTE_WRITEABLE;
-
-	/* Apply ASIC specific mapping flags */
-	amdgpu_gmc_get_vm_pte(adev, mapping, &flags);
-
-	trace_amdgpu_vm_bo_update(mapping);
-
-	pfn = mapping->offset >> PAGE_SHIFT;
-	if (nodes) {
-		while (pfn >= nodes->size) {
-			pfn -= nodes->size;
-			++nodes;
-		}
-	}
-
 	do {
-		dma_addr_t *dma_addr = NULL;
-		uint64_t max_entries;
-		uint64_t addr, last;
+		uint64_t tmp, num_entries, addr;
+
 
-		max_entries = mapping->last - start + 1;
+		num_entries = last - start + 1;
 		if (nodes) {
 			addr = nodes->start << PAGE_SHIFT;
-			max_entries = min((nodes->size - pfn) *
-				AMDGPU_GPU_PAGES_IN_CPU_PAGE, max_entries);
+			num_entries = min((nodes->size - pfn) *
+				AMDGPU_GPU_PAGES_IN_CPU_PAGE, num_entries);
 		} else {
 			addr = 0;
 		}
 
 		if (pages_addr) {
-			uint64_t count;
+			bool contiguous = true;
 
-			for (count = 1;
-			     count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
-			     ++count) {
-				uint64_t idx = pfn + count;
+			if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
+				uint64_t count;
 
-				if (pages_addr[idx] !=
-				    (pages_addr[idx - 1] + PAGE_SIZE))
-					break;
+				contiguous = pages_addr[pfn + 1] ==
+					pages_addr[pfn] + PAGE_SIZE;
+
+				tmp = num_entries /
+					AMDGPU_GPU_PAGES_IN_CPU_PAGE;
+				for (count = 2; count < tmp; ++count) {
+					uint64_t idx = pfn + count;
+
+					if (contiguous != (pages_addr[idx] ==
+					    pages_addr[idx - 1] + PAGE_SIZE))
+						break;
+				}
+				num_entries = count *
+					AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 			}
 
-			if (count < min_linear_pages) {
+			if (!contiguous) {
 				addr = pfn << PAGE_SHIFT;
-				dma_addr = pages_addr;
+				params.pages_addr = pages_addr;
 			} else {
 				addr = pages_addr[pfn];
-				max_entries = count *
-					AMDGPU_GPU_PAGES_IN_CPU_PAGE;
+				params.pages_addr = NULL;
 			}
 
 		} else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
@@ -1738,23 +1693,25 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
 			addr += pfn << PAGE_SHIFT;
 		}
 
-		last = start + max_entries - 1;
-		r = amdgpu_vm_bo_update_mapping(adev, vm, false, false, resv,
-						start, last, flags, addr,
-						dma_addr, fence);
+		tmp = start + num_entries;
+		r = amdgpu_vm_update_ptes(&params, start, tmp, addr, flags);
 		if (r)
-			return r;
+			goto error_unlock;
 
-		pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
+		pfn += num_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 		if (nodes && nodes->size == pfn) {
 			pfn = 0;
 			++nodes;
 		}
-		start = last + 1;
+		start = tmp;
 
-	} while (unlikely(start != mapping->last + 1));
+	} while (unlikely(start != last + 1));
 
-	return 0;
+	r = vm->update_funcs->commit(&params, fence);
+
+error_unlock:
+	amdgpu_vm_eviction_unlock(vm);
+	return r;
 }
 
 /**
@@ -1832,9 +1789,26 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
 	}
 
 	list_for_each_entry(mapping, &bo_va->invalids, list) {
-		r = amdgpu_vm_bo_split_mapping(adev, resv, pages_addr, vm,
-					       mapping, flags, bo_adev, nodes,
-					       last_update);
+		uint64_t update_flags = flags;
+
+		/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
+		 * but in case of something, we filter the flags in first place
+		 */
+		if (!(mapping->flags & AMDGPU_PTE_READABLE))
+			update_flags &= ~AMDGPU_PTE_READABLE;
+		if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
+			update_flags &= ~AMDGPU_PTE_WRITEABLE;
+
+		/* Apply ASIC specific mapping flags */
+		amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
+
+		trace_amdgpu_vm_bo_update(mapping);
+
+		r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false,
+						resv, mapping->start,
+						mapping->last, update_flags,
+						mapping->offset, nodes,
+						pages_addr, last_update);
 		if (r)
 			return r;
 	}
@@ -2042,9 +2016,10 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
 		    mapping->start < AMDGPU_GMC_HOLE_START)
 			init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
 
-		r = amdgpu_vm_bo_update_mapping(adev, vm, false, false, resv,
-						mapping->start, mapping->last,
-						init_pte_value, 0, NULL, &f);
+		r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false,
+						resv, mapping->start,
+						mapping->last, init_pte_value,
+						0, NULL, NULL, &f);
 		amdgpu_vm_free_mapping(adev, vm, mapping, f);
 		if (r) {
 			dma_fence_put(f);
@@ -2163,7 +2138,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
 
 
 /**
- * amdgpu_vm_bo_insert_mapping - insert a new mapping
+ * amdgpu_vm_bo_insert_map - insert a new mapping
  *
  * @adev: amdgpu_device pointer
  * @bo_va: bo_va to store the address
@@ -2820,7 +2795,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	INIT_LIST_HEAD(&vm->invalidated);
 	spin_lock_init(&vm->invalidated_lock);
 	INIT_LIST_HEAD(&vm->freed);
-
+	INIT_LIST_HEAD(&vm->done);
 
 	/* create scheduler entities for page table updates */
 	r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
@@ -3372,8 +3347,9 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
 		value = 0;
 	}
 
-	r = amdgpu_vm_bo_update_mapping(adev, vm, true, false, NULL, addr,
-					addr + 1, flags, value, NULL, NULL);
+	r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
+					addr, flags, value, NULL, NULL,
+					NULL);
 	if (r)
 		goto error_unlock;
 
@@ -3389,3 +3365,99 @@ error_unref:
 
 	return false;
 }
+
+#if defined(CONFIG_DEBUG_FS)
+/**
+ * amdgpu_debugfs_vm_bo_info  - print BO info for the VM
+ *
+ * @vm: Requested VM for printing BO info
+ * @m: debugfs file
+ *
+ * Print BO information in debugfs file for the VM
+ */
+void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
+{
+	struct amdgpu_bo_va *bo_va, *tmp;
+	u64 total_idle = 0;
+	u64 total_evicted = 0;
+	u64 total_relocated = 0;
+	u64 total_moved = 0;
+	u64 total_invalidated = 0;
+	u64 total_done = 0;
+	unsigned int total_idle_objs = 0;
+	unsigned int total_evicted_objs = 0;
+	unsigned int total_relocated_objs = 0;
+	unsigned int total_moved_objs = 0;
+	unsigned int total_invalidated_objs = 0;
+	unsigned int total_done_objs = 0;
+	unsigned int id = 0;
+
+	seq_puts(m, "\tIdle BOs:\n");
+	list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
+	}
+	total_idle_objs = id;
+	id = 0;
+
+	seq_puts(m, "\tEvicted BOs:\n");
+	list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
+	}
+	total_evicted_objs = id;
+	id = 0;
+
+	seq_puts(m, "\tRelocated BOs:\n");
+	list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
+	}
+	total_relocated_objs = id;
+	id = 0;
+
+	seq_puts(m, "\tMoved BOs:\n");
+	list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
+	}
+	total_moved_objs = id;
+	id = 0;
+
+	seq_puts(m, "\tInvalidated BOs:\n");
+	spin_lock(&vm->invalidated_lock);
+	list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		total_invalidated += amdgpu_bo_print_info(id++,	bo_va->base.bo, m);
+	}
+	total_invalidated_objs = id;
+	id = 0;
+
+	seq_puts(m, "\tDone BOs:\n");
+	list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
+		if (!bo_va->base.bo)
+			continue;
+		total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
+	}
+	spin_unlock(&vm->invalidated_lock);
+	total_done_objs = id;
+
+	seq_printf(m, "\tTotal idle size:        %12lld\tobjs:\t%d\n", total_idle,
+		   total_idle_objs);
+	seq_printf(m, "\tTotal evicted size:     %12lld\tobjs:\t%d\n", total_evicted,
+		   total_evicted_objs);
+	seq_printf(m, "\tTotal relocated size:   %12lld\tobjs:\t%d\n", total_relocated,
+		   total_relocated_objs);
+	seq_printf(m, "\tTotal moved size:       %12lld\tobjs:\t%d\n", total_moved,
+		   total_moved_objs);
+	seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
+		   total_invalidated_objs);
+	seq_printf(m, "\tTotal done size:        %12lld\tobjs:\t%d\n", total_done,
+		   total_done_objs);
+}
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 58c83a7ad0fd..ca2344beed81 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -76,6 +76,9 @@ struct amdgpu_bo_list_entry;
 /* PTE is handled as PDE for VEGA10 (Translate Further) */
 #define AMDGPU_PTE_TF		(1ULL << 56)
 
+/* MALL noalloc for sienna_cichlid, reserved for older ASICs  */
+#define AMDGPU_PTE_NOALLOC	(1ULL << 58)
+
 /* PDE Block Fragment Size for VEGA10 */
 #define AMDGPU_PDE_BFS(a)	((uint64_t)a << 59)
 
@@ -274,6 +277,9 @@ struct amdgpu_vm {
 	/* BO mappings freed, but not yet updated in the PT */
 	struct list_head	freed;
 
+	/* BOs which are invalidated, has been updated in the PTs */
+	struct list_head        done;
+
 	/* contains the page directory */
 	struct amdgpu_vm_pt     root;
 	struct dma_fence	*last_update;
@@ -441,4 +447,8 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
 				struct amdgpu_vm *vm);
 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
 
+#if defined(CONFIG_DEBUG_FS)
+void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
+#endif
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 7747be644dd0..c99c2180785f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -168,8 +168,7 @@ static const struct ttm_resource_manager_func amdgpu_vram_mgr_func;
 /**
  * amdgpu_vram_mgr_init - init VRAM manager and DRM MM
  *
- * @man: TTM memory type manager
- * @p_size: maximum size of VRAM
+ * @adev: amdgpu_device pointer
  *
  * Allocate and initialize the VRAM manager.
  */
@@ -185,6 +184,8 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev)
 
 	drm_mm_init(&mgr->mm, 0, man->size);
 	spin_lock_init(&mgr->lock);
+	INIT_LIST_HEAD(&mgr->reservations_pending);
+	INIT_LIST_HEAD(&mgr->reserved_pages);
 
 	/* Add the two VRAM-related sysfs files */
 	ret = sysfs_create_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes);
@@ -199,7 +200,7 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev)
 /**
  * amdgpu_vram_mgr_fini - free and destroy VRAM manager
  *
- * @man: TTM memory type manager
+ * @adev: amdgpu_device pointer
  *
  * Destroy and free the VRAM manager, returns -EBUSY if ranges are still
  * allocated inside it.
@@ -209,6 +210,7 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev)
 	struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr;
 	struct ttm_resource_manager *man = &mgr->manager;
 	int ret;
+	struct amdgpu_vram_reservation *rsv, *temp;
 
 	ttm_resource_manager_set_used(man, false);
 
@@ -217,6 +219,13 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev)
 		return;
 
 	spin_lock(&mgr->lock);
+	list_for_each_entry_safe(rsv, temp, &mgr->reservations_pending, node)
+		kfree(rsv);
+
+	list_for_each_entry_safe(rsv, temp, &mgr->reserved_pages, node) {
+		drm_mm_remove_node(&rsv->mm_node);
+		kfree(rsv);
+	}
 	drm_mm_takedown(&mgr->mm);
 	spin_unlock(&mgr->lock);
 
@@ -229,7 +238,7 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev)
 /**
  * amdgpu_vram_mgr_vis_size - Calculate visible node size
  *
- * @adev: amdgpu device structure
+ * @adev: amdgpu_device pointer
  * @node: MM node structure
  *
  * Calculate how many bytes of the MM node are inside visible VRAM
@@ -275,6 +284,101 @@ u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo)
 	return usage;
 }
 
+static void amdgpu_vram_mgr_do_reserve(struct ttm_resource_manager *man)
+{
+	struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
+	struct amdgpu_device *adev = to_amdgpu_device(mgr);
+	struct drm_mm *mm = &mgr->mm;
+	struct amdgpu_vram_reservation *rsv, *temp;
+	uint64_t vis_usage;
+
+	list_for_each_entry_safe(rsv, temp, &mgr->reservations_pending, node) {
+		if (drm_mm_reserve_node(mm, &rsv->mm_node))
+			continue;
+
+		dev_dbg(adev->dev, "Reservation 0x%llx - %lld, Succeeded\n",
+			rsv->mm_node.start, rsv->mm_node.size);
+
+		vis_usage = amdgpu_vram_mgr_vis_size(adev, &rsv->mm_node);
+		atomic64_add(vis_usage, &mgr->vis_usage);
+		atomic64_add(rsv->mm_node.size << PAGE_SHIFT, &mgr->usage);
+		list_move(&rsv->node, &mgr->reserved_pages);
+	}
+}
+
+/**
+ * amdgpu_vram_mgr_reserve_range - Reserve a range from VRAM
+ *
+ * @man: TTM memory type manager
+ * @start: start address of the range in VRAM
+ * @size: size of the range
+ *
+ * Reserve memory from start addess with the specified size in VRAM
+ */
+int amdgpu_vram_mgr_reserve_range(struct ttm_resource_manager *man,
+				  uint64_t start, uint64_t size)
+{
+	struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
+	struct amdgpu_vram_reservation *rsv;
+
+	rsv = kzalloc(sizeof(*rsv), GFP_KERNEL);
+	if (!rsv)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&rsv->node);
+	rsv->mm_node.start = start >> PAGE_SHIFT;
+	rsv->mm_node.size = size >> PAGE_SHIFT;
+
+	spin_lock(&mgr->lock);
+	list_add_tail(&mgr->reservations_pending, &rsv->node);
+	amdgpu_vram_mgr_do_reserve(man);
+	spin_unlock(&mgr->lock);
+
+	return 0;
+}
+
+/**
+ * amdgpu_vram_mgr_query_page_status - query the reservation status
+ *
+ * @man: TTM memory type manager
+ * @start: start address of a page in VRAM
+ *
+ * Returns:
+ *	-EBUSY: the page is still hold and in pending list
+ *	0: the page has been reserved
+ *	-ENOENT: the input page is not a reservation
+ */
+int amdgpu_vram_mgr_query_page_status(struct ttm_resource_manager *man,
+				      uint64_t start)
+{
+	struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
+	struct amdgpu_vram_reservation *rsv;
+	int ret;
+
+	spin_lock(&mgr->lock);
+
+	list_for_each_entry(rsv, &mgr->reservations_pending, node) {
+		if ((rsv->mm_node.start <= start) &&
+		    (start < (rsv->mm_node.start + rsv->mm_node.size))) {
+			ret = -EBUSY;
+			goto out;
+		}
+	}
+
+	list_for_each_entry(rsv, &mgr->reserved_pages, node) {
+		if ((rsv->mm_node.start <= start) &&
+		    (start < (rsv->mm_node.start + rsv->mm_node.size))) {
+			ret = 0;
+			goto out;
+		}
+	}
+
+	ret = -ENOENT;
+out:
+	spin_unlock(&mgr->lock);
+	return ret;
+}
+
 /**
  * amdgpu_vram_mgr_virt_start - update virtual start address
  *
@@ -445,6 +549,7 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man,
 		vis_usage += amdgpu_vram_mgr_vis_size(adev, nodes);
 		++nodes;
 	}
+	amdgpu_vram_mgr_do_reserve(man);
 	spin_unlock(&mgr->lock);
 
 	atomic64_sub(usage, &mgr->usage);
@@ -529,7 +634,7 @@ error_free:
 }
 
 /**
- * amdgpu_vram_mgr_alloc_sgt - allocate and fill a sg table
+ * amdgpu_vram_mgr_free_sgt - allocate and fill a sg table
  *
  * @adev: amdgpu device pointer
  * @sgt: sg table to free
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 1162913c8bf4..54c358e71f9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -246,7 +246,7 @@ static ssize_t amdgpu_xgmi_show_error(struct device *dev,
 
 	adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
 
-	return snprintf(buf, PAGE_SIZE, "%d\n", error_count);
+	return snprintf(buf, PAGE_SIZE, "%u\n", error_count);
 }
 
 
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
index 939eca63b094..66c183ddd43e 100644
--- a/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_1.c
@@ -74,6 +74,7 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		athub_v2_1_update_medium_grain_clock_gating(adev,
 				state == AMD_CG_STATE_GATE ? true : false);
 		athub_v2_1_update_medium_grain_light_sleep(adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c
index 4cfc786699c7..515890f4f5a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -66,13 +66,13 @@ typedef struct {
 	bool abort;
 } atom_exec_context;
 
-int amdgpu_atom_debug = 0;
-static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
-int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
+int amdgpu_atom_debug;
+static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params);
+int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params);
 
 static uint32_t atom_arg_mask[8] =
-    { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
-0xFF000000 };
+	{ 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
+	  0xFF000000 };
 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
 
 static int atom_dst_to_src[8][4] = {
@@ -88,7 +88,7 @@ static int atom_dst_to_src[8][4] = {
 };
 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
 
-static int debug_depth = 0;
+static int debug_depth;
 #ifdef ATOM_DEBUG
 static void debug_print_spaces(int n)
 {
@@ -1201,7 +1201,7 @@ static struct {
 	atom_op_div32, ATOM_ARG_WS},
 };
 
-static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
+static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params)
 {
 	int base = CU16(ctx->cmd_table + 4 + 2 * index);
 	int len, ws, ps, ptr;
@@ -1262,7 +1262,7 @@ free:
 	return ret;
 }
 
-int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
+int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params)
 {
 	int r;
 
@@ -1388,8 +1388,8 @@ void amdgpu_atom_destroy(struct atom_context *ctx)
 }
 
 bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
-			    uint16_t * size, uint8_t * frev, uint8_t * crev,
-			    uint16_t * data_start)
+			    uint16_t *size, uint8_t *frev, uint8_t *crev,
+			    uint16_t *data_start)
 {
 	int offset = index * 2 + 4;
 	int idx = CU16(ctx->data_table + offset);
@@ -1408,8 +1408,8 @@ bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
 	return true;
 }
 
-bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
-			   uint8_t * crev)
+bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev,
+			   uint8_t *crev)
 {
 	int offset = index * 2 + 4;
 	int idx = CU16(ctx->cmd_table + offset);
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
index 8339c8c3a328..fa817ebff980 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
@@ -499,10 +499,8 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder)
 		} else {
 			return ATOM_ENCODER_MODE_DVI;
 		}
-		break;
 	case DRM_MODE_CONNECTOR_LVDS:
 		return ATOM_ENCODER_MODE_LVDS;
-		break;
 	case DRM_MODE_CONNECTOR_DisplayPort:
 		dig_connector = amdgpu_connector->con_priv;
 		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
@@ -519,20 +517,16 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder)
 		} else {
 			return ATOM_ENCODER_MODE_DVI;
 		}
-		break;
 	case DRM_MODE_CONNECTOR_eDP:
 		return ATOM_ENCODER_MODE_DP;
 	case DRM_MODE_CONNECTOR_DVIA:
 	case DRM_MODE_CONNECTOR_VGA:
 		return ATOM_ENCODER_MODE_CRT;
-		break;
 	case DRM_MODE_CONNECTOR_Composite:
 	case DRM_MODE_CONNECTOR_SVIDEO:
 	case DRM_MODE_CONNECTOR_9PinDIN:
 		/* fix me */
 		return ATOM_ENCODER_MODE_TV;
-		/*return ATOM_ENCODER_MODE_CV;*/
-		break;
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
index 09a538465ffd..af0335535f82 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
@@ -159,7 +159,7 @@ u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap)
 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 }
 
-void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device* adev, u8 slave_addr, u8 line_number, u8 offset, u8 data)
+void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device *adev, u8 slave_addr, u8 line_number, u8 offset, u8 data)
 {
 	PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
 	int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 03ff8bd1fee8..5442df094102 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1336,11 +1336,13 @@ cik_asic_reset_method(struct amdgpu_device *adev)
 
 	switch (adev->asic_type) {
 	case CHIP_BONAIRE:
-	case CHIP_HAWAII:
 		/* disable baco reset until it works */
 		/* smu7_asic_get_baco_capability(adev, &baco_reset); */
 		baco_reset = false;
 		break;
+	case CHIP_HAWAII:
+		baco_reset = cik_asic_supports_baco(adev);
+		break;
 	default:
 		baco_reset = false;
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 20f108818b2b..1a6494ea5091 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -195,7 +195,7 @@ static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 
 	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
-		       	(lower_32_bits(ring->wptr) << 2) & 0x3fffc);
+	       (lower_32_bits(ring->wptr) << 2) & 0x3fffc);
 }
 
 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
@@ -1071,22 +1071,19 @@ static int cik_sdma_soft_reset(void *handle)
 {
 	u32 srbm_soft_reset = 0;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	u32 tmp = RREG32(mmSRBM_STATUS2);
+	u32 tmp;
 
-	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
-		/* sdma0 */
-		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
-		tmp |= SDMA0_F32_CNTL__HALT_MASK;
-		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
-		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
-	}
-	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
-		/* sdma1 */
-		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
-		tmp |= SDMA0_F32_CNTL__HALT_MASK;
-		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
-		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
-	}
+	/* sdma0 */
+	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
+	tmp |= SDMA0_F32_CNTL__HALT_MASK;
+	WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
+	srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
+
+	/* sdma1 */
+	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
+	tmp |= SDMA0_F32_CNTL__HALT_MASK;
+	WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
+	srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
 
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 5963cbe0d455..da240f8fafcf 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2202,22 +2202,18 @@ static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
 			return 1;
 		else
 			return 0;
-		break;
 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 		if (dig->linkb)
 			return 3;
 		else
 			return 2;
-		break;
 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 		if (dig->linkb)
 			return 5;
 		else
 			return 4;
-		break;
 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
 		return 6;
-		break;
 	default:
 		DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
 		return 0;
@@ -2677,7 +2673,7 @@ static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
 					 struct drm_framebuffer *fb,
 					 int x, int y, enum mode_set_atomic state)
 {
-       return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
+	return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
 }
 
 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 1954472c8e8f..c62c56a69fda 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2235,22 +2235,18 @@ static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
 			return 1;
 		else
 			return 0;
-		break;
 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 		if (dig->linkb)
 			return 3;
 		else
 			return 2;
-		break;
 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 		if (dig->linkb)
 			return 5;
 		else
 			return 4;
-		break;
 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
 		return 6;
-		break;
 	default:
 		DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
 		return 0;
@@ -2304,19 +2300,16 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
 				return ATOM_COMBOPHY_PLL1;
 			else
 				return ATOM_COMBOPHY_PLL0;
-			break;
 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 			if (dig->linkb)
 				return ATOM_COMBOPHY_PLL3;
 			else
 				return ATOM_COMBOPHY_PLL2;
-			break;
 		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 			if (dig->linkb)
 				return ATOM_COMBOPHY_PLL5;
 			else
 				return ATOM_COMBOPHY_PLL4;
-			break;
 		default:
 			DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
 			return ATOM_PPLL_INVALID;
@@ -2785,7 +2778,7 @@ static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
 					 struct drm_framebuffer *fb,
 					 int x, int y, enum mode_set_atomic state)
 {
-       return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
+	return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
 }
 
 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 3a44753a80d1..943976349346 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2567,7 +2567,7 @@ static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
 					 struct drm_framebuffer *fb,
 					 int x, int y, enum mode_set_atomic state)
 {
-       return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
+	return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
 }
 
 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 3603e5f13077..7973183fa335 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2498,7 +2498,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
 	case ATOM_PPLL2:
 		/* disable the ppll */
 		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
-                                                 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
+						 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
 		break;
 	case ATOM_PPLL0:
 		/* disable the ppll */
@@ -2585,7 +2585,7 @@ static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
 					 struct drm_framebuffer *fb,
 					 int x, int y, enum mode_set_atomic state)
 {
-       return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
+	return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
 }
 
 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
index d6aca1c08068..2d01ac0d4c11 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
@@ -41,7 +41,7 @@ static void df_v1_7_sw_fini(struct amdgpu_device *adev)
 }
 
 static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev,
-                                          bool enable)
+					  bool enable)
 {
 	u32 tmp;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index 7b89fd2aa44a..6b4b30a8dce5 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -30,71 +30,17 @@
 #define DF_3_6_SMN_REG_INST_DIST        0x8
 #define DF_3_6_INST_CNT                 8
 
-static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
-				       16, 32, 0, 0, 0, 2, 4, 8};
-
-/* init df format attrs */
-AMDGPU_PMU_ATTR(event,		"config:0-7");
-AMDGPU_PMU_ATTR(instance,	"config:8-15");
-AMDGPU_PMU_ATTR(umask,		"config:16-23");
-
-/* df format attributes  */
-static struct attribute *df_v3_6_format_attrs[] = {
-	&pmu_attr_event.attr,
-	&pmu_attr_instance.attr,
-	&pmu_attr_umask.attr,
-	NULL
-};
-
-/* df format attribute group */
-static struct attribute_group df_v3_6_format_attr_group = {
-	.name = "format",
-	.attrs = df_v3_6_format_attrs,
-};
-
-/* df event attrs */
-AMDGPU_PMU_ATTR(cake0_pcsout_txdata,
-		      "event=0x7,instance=0x46,umask=0x2");
-AMDGPU_PMU_ATTR(cake1_pcsout_txdata,
-		      "event=0x7,instance=0x47,umask=0x2");
-AMDGPU_PMU_ATTR(cake0_pcsout_txmeta,
-		      "event=0x7,instance=0x46,umask=0x4");
-AMDGPU_PMU_ATTR(cake1_pcsout_txmeta,
-		      "event=0x7,instance=0x47,umask=0x4");
-AMDGPU_PMU_ATTR(cake0_ftiinstat_reqalloc,
-		      "event=0xb,instance=0x46,umask=0x4");
-AMDGPU_PMU_ATTR(cake1_ftiinstat_reqalloc,
-		      "event=0xb,instance=0x47,umask=0x4");
-AMDGPU_PMU_ATTR(cake0_ftiinstat_rspalloc,
-		      "event=0xb,instance=0x46,umask=0x8");
-AMDGPU_PMU_ATTR(cake1_ftiinstat_rspalloc,
-		      "event=0xb,instance=0x47,umask=0x8");
-
-/* df event attributes  */
-static struct attribute *df_v3_6_event_attrs[] = {
-	&pmu_attr_cake0_pcsout_txdata.attr,
-	&pmu_attr_cake1_pcsout_txdata.attr,
-	&pmu_attr_cake0_pcsout_txmeta.attr,
-	&pmu_attr_cake1_pcsout_txmeta.attr,
-	&pmu_attr_cake0_ftiinstat_reqalloc.attr,
-	&pmu_attr_cake1_ftiinstat_reqalloc.attr,
-	&pmu_attr_cake0_ftiinstat_rspalloc.attr,
-	&pmu_attr_cake1_ftiinstat_rspalloc.attr,
-	NULL
-};
+/* Defined in global_features.h as FTI_PERFMON_VISIBLE */
+#define DF_V3_6_MAX_COUNTERS		4
 
-/* df event attribute group */
-static struct attribute_group df_v3_6_event_attr_group = {
-	.name = "events",
-	.attrs = df_v3_6_event_attrs
-};
+/* get flags from df perfmon config */
+#define DF_V3_6_GET_EVENT(x)		(x & 0xFFUL)
+#define DF_V3_6_GET_INSTANCE(x)		((x >> 8) & 0xFFUL)
+#define DF_V3_6_GET_UNITMASK(x)		((x >> 16) & 0xFFUL)
+#define DF_V3_6_PERFMON_OVERFLOW	0xFFFFFFFFFFFFULL
 
-/* df event attr groups  */
-const struct attribute_group *df_v3_6_attr_groups[] = {
-		&df_v3_6_format_attr_group,
-		&df_v3_6_event_attr_group,
-		NULL
-};
+static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
+				       16, 32, 0, 0, 0, 2, 4, 8};
 
 static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
 				 uint32_t ficaa_val)
@@ -391,33 +337,28 @@ static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
 }
 
 /* get assigned df perfmon ctr as int */
-static int df_v3_6_pmc_config_2_cntr(struct amdgpu_device *adev,
-				      uint64_t config)
+static bool df_v3_6_pmc_has_counter(struct amdgpu_device *adev,
+				      uint64_t config,
+				      int counter_idx)
 {
-	int i;
 
-	for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
-		if ((config & 0x0FFFFFFUL) ==
-					adev->df_perfmon_config_assign_mask[i])
-			return i;
-	}
+	return ((config & 0x0FFFFFFUL) ==
+			adev->df_perfmon_config_assign_mask[counter_idx]);
 
-	return -EINVAL;
 }
 
 /* get address based on counter assignment */
 static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev,
 				 uint64_t config,
+				 int counter_idx,
 				 int is_ctrl,
 				 uint32_t *lo_base_addr,
 				 uint32_t *hi_base_addr)
 {
-	int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
-
-	if (target_cntr < 0)
+	if (!df_v3_6_pmc_has_counter(adev, config, counter_idx))
 		return;
 
-	switch (target_cntr) {
+	switch (counter_idx) {
 
 	case 0:
 		*lo_base_addr = is_ctrl ? smnPerfMonCtlLo4 : smnPerfMonCtrLo4;
@@ -443,15 +384,18 @@ static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev,
 /* get read counter address */
 static void df_v3_6_pmc_get_read_settings(struct amdgpu_device *adev,
 					  uint64_t config,
+					  int counter_idx,
 					  uint32_t *lo_base_addr,
 					  uint32_t *hi_base_addr)
 {
-	df_v3_6_pmc_get_addr(adev, config, 0, lo_base_addr, hi_base_addr);
+	df_v3_6_pmc_get_addr(adev, config, counter_idx, 0, lo_base_addr,
+								hi_base_addr);
 }
 
 /* get control counter settings i.e. address and values to set */
 static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
 					  uint64_t config,
+					  int counter_idx,
 					  uint32_t *lo_base_addr,
 					  uint32_t *hi_base_addr,
 					  uint32_t *lo_val,
@@ -462,7 +406,8 @@ static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
 	uint32_t eventsel, instance, unitmask;
 	uint32_t instance_10, instance_5432, instance_76;
 
-	df_v3_6_pmc_get_addr(adev, config, 1, lo_base_addr, hi_base_addr);
+	df_v3_6_pmc_get_addr(adev, config, counter_idx, 1, lo_base_addr,
+				hi_base_addr);
 
 	if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) {
 		DRM_ERROR("[DF PMC] addressing not retrieved! Lo: %x, Hi: %x",
@@ -492,18 +437,13 @@ static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
 static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev,
 				   uint64_t config)
 {
-	int i, target_cntr;
-
-	target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
-
-	if (target_cntr >= 0)
-		return 0;
+	int i;
 
 	for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
 		if (adev->df_perfmon_config_assign_mask[i] == 0U) {
 			adev->df_perfmon_config_assign_mask[i] =
 							config & 0x0FFFFFFUL;
-			return 0;
+			return i;
 		}
 	}
 
@@ -512,59 +452,50 @@ static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev,
 
 #define DEFERRED_ARM_MASK	(1 << 31)
 static int df_v3_6_pmc_set_deferred(struct amdgpu_device *adev,
-				    uint64_t config, bool is_deferred)
+				    int counter_idx, uint64_t config,
+				    bool is_deferred)
 {
-	int target_cntr;
 
-	target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
-
-	if (target_cntr < 0)
+	if (!df_v3_6_pmc_has_counter(adev, config, counter_idx))
 		return -EINVAL;
 
 	if (is_deferred)
-		adev->df_perfmon_config_assign_mask[target_cntr] |=
+		adev->df_perfmon_config_assign_mask[counter_idx] |=
 							DEFERRED_ARM_MASK;
 	else
-		adev->df_perfmon_config_assign_mask[target_cntr] &=
+		adev->df_perfmon_config_assign_mask[counter_idx] &=
 							~DEFERRED_ARM_MASK;
 
 	return 0;
 }
 
 static bool df_v3_6_pmc_is_deferred(struct amdgpu_device *adev,
+				    int counter_idx,
 				    uint64_t config)
 {
-	int target_cntr;
-
-	target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
-
-	/*
-	 * we never get target_cntr < 0 since this funciton is only called in
-	 * pmc_count for now but we should check anyways.
-	 */
-	return (target_cntr >= 0 &&
-			(adev->df_perfmon_config_assign_mask[target_cntr]
-			& DEFERRED_ARM_MASK));
+	return	(df_v3_6_pmc_has_counter(adev, config, counter_idx) &&
+			(adev->df_perfmon_config_assign_mask[counter_idx]
+				& DEFERRED_ARM_MASK));
 
 }
 
 /* release performance counter */
 static void df_v3_6_pmc_release_cntr(struct amdgpu_device *adev,
-				     uint64_t config)
+				     uint64_t config,
+				     int counter_idx)
 {
-	int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
-
-	if (target_cntr >= 0)
-		adev->df_perfmon_config_assign_mask[target_cntr] = 0ULL;
+	if (df_v3_6_pmc_has_counter(adev, config, counter_idx))
+		adev->df_perfmon_config_assign_mask[counter_idx] = 0ULL;
 }
 
 
 static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev,
-					 uint64_t config)
+					 uint64_t config,
+					 int counter_idx)
 {
 	uint32_t lo_base_addr = 0, hi_base_addr = 0;
 
-	df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
+	df_v3_6_pmc_get_read_settings(adev, config, counter_idx, &lo_base_addr,
 				      &hi_base_addr);
 
 	if ((lo_base_addr == 0) || (hi_base_addr == 0))
@@ -573,21 +504,22 @@ static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev,
 	df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
 }
 
+/* return available counter if is_add == 1 otherwise return error status. */
 static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
-			     int is_add)
+			     int counter_idx, int is_add)
 {
 	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
 	int err = 0, ret = 0;
 
 	switch (adev->asic_type) {
 	case CHIP_VEGA20:
+	case CHIP_ARCTURUS:
 		if (is_add)
 			return df_v3_6_pmc_add_cntr(adev, config);
 
-		df_v3_6_reset_perfmon_cntr(adev, config);
-
 		ret = df_v3_6_pmc_get_ctrl_settings(adev,
 					config,
+					counter_idx,
 					&lo_base_addr,
 					&hi_base_addr,
 					&lo_val,
@@ -604,7 +536,8 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
 						     hi_val);
 
 		if (err)
-			ret = df_v3_6_pmc_set_deferred(adev, config, true);
+			ret = df_v3_6_pmc_set_deferred(adev, config,
+							counter_idx, true);
 
 		break;
 	default:
@@ -615,15 +548,17 @@ static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
 }
 
 static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
-			    int is_remove)
+			    int counter_idx, int is_remove)
 {
 	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
 	int ret = 0;
 
 	switch (adev->asic_type) {
 	case CHIP_VEGA20:
+	case CHIP_ARCTURUS:
 		ret = df_v3_6_pmc_get_ctrl_settings(adev,
 			config,
+			counter_idx,
 			&lo_base_addr,
 			&hi_base_addr,
 			&lo_val,
@@ -635,8 +570,8 @@ static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
 
 
 		if (is_remove) {
-			df_v3_6_reset_perfmon_cntr(adev, config);
-			df_v3_6_pmc_release_cntr(adev, config);
+			df_v3_6_reset_perfmon_cntr(adev, config, counter_idx);
+			df_v3_6_pmc_release_cntr(adev, config, counter_idx);
 		}
 
 		break;
@@ -649,6 +584,7 @@ static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
 
 static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
 				  uint64_t config,
+				  int counter_idx,
 				  uint64_t *count)
 {
 	uint32_t lo_base_addr = 0, hi_base_addr = 0, lo_val = 0, hi_val = 0;
@@ -656,14 +592,15 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
 
 	switch (adev->asic_type) {
 	case CHIP_VEGA20:
-		df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
-				      &hi_base_addr);
+	case CHIP_ARCTURUS:
+		df_v3_6_pmc_get_read_settings(adev, config, counter_idx,
+						&lo_base_addr, &hi_base_addr);
 
 		if ((lo_base_addr == 0) || (hi_base_addr == 0))
 			return;
 
 		/* rearm the counter or throw away count value on failure */
-		if (df_v3_6_pmc_is_deferred(adev, config)) {
+		if (df_v3_6_pmc_is_deferred(adev, config, counter_idx)) {
 			int rearm_err = df_v3_6_perfmon_arm_with_status(adev,
 							lo_base_addr, lo_val,
 							hi_base_addr, hi_val);
@@ -671,7 +608,8 @@ static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
 			if (rearm_err)
 				return;
 
-			df_v3_6_pmc_set_deferred(adev, config, false);
+			df_v3_6_pmc_set_deferred(adev, config, counter_idx,
+									false);
 		}
 
 		df_v3_6_perfmon_rreg(adev, lo_base_addr, &lo_val,
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.h b/drivers/gpu/drm/amd/amdgpu/df_v3_6.h
index 76998541bc30..2505c7ef258a 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.h
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.h
@@ -35,15 +35,6 @@ enum DF_V3_6_MGCG {
 	DF_V3_6_MGCG_ENABLE_63_CYCLE_DELAY = 15
 };
 
-/* Defined in global_features.h as FTI_PERFMON_VISIBLE */
-#define DF_V3_6_MAX_COUNTERS		4
-
-/* get flags from df perfmon config */
-#define DF_V3_6_GET_EVENT(x)		(x & 0xFFUL)
-#define DF_V3_6_GET_INSTANCE(x)		((x >> 8) & 0xFFUL)
-#define DF_V3_6_GET_UNITMASK(x)		((x >> 16) & 0xFFUL)
-#define DF_V3_6_PERFMON_OVERFLOW	0xFFFFFFFFFFFFULL
-
 extern const struct attribute_group *df_v3_6_attr_groups[];
 extern const struct amdgpu_df_funcs df_v3_6_funcs;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c b/drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c
new file mode 100755
index 000000000000..e9f177e9e3cf
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/dimgrey_cavefish_reg_init.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "dimgrey_cavefish_ip_offset.h"
+
+int dimgrey_cavefish_reg_base_init(struct amdgpu_device *adev)
+{
+	/* HW has more IP blocks,  only initialize the block needed by driver */
+	uint32_t i;
+	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN0_BASE.instance[i]));
+		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
+		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+	}
+	return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 56fdbe626d30..8c3bad3dfc01 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -99,6 +99,23 @@
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0
 
+#define mmSPI_CONFIG_CNTL_1_Vangogh		 0x2441
+#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX	 1
+#define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
+#define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
+#define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
+#define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
+#define mmVGT_TF_RING_SIZE_Vangogh               0x224e
+#define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
+#define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
+#define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
+#define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
+#define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
+#define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
+#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
+#define mmSPI_CONFIG_CNTL_Vangogh                0x2440
+#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
+
 #define mmCP_HYP_PFP_UCODE_ADDR			0x5814
 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX	1
 #define mmCP_HYP_PFP_UCODE_DATA			0x5815
@@ -112,6 +129,13 @@
 #define mmCP_HYP_ME_UCODE_DATA			0x5817
 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX		1
 
+#define mmCPG_PSP_DEBUG				0x5c10
+#define mmCPG_PSP_DEBUG_BASE_IDX		1
+#define mmCPC_PSP_DEBUG				0x5c11
+#define mmCPC_PSP_DEBUG_BASE_IDX		1
+#define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
+#define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK	0x00000008L
+
 //CC_GC_SA_UNIT_DISABLE
 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
@@ -128,6 +152,9 @@
 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 
+#define mmCGTT_SPI_CS_CLK_CTRL			0x507c
+#define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
+
 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -168,6 +195,20 @@ MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 
+MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
+
+MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
+MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
+MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
+MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
+MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
+MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 {
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@ -3094,6 +3135,7 @@ static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
 
 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
 {
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
@@ -3177,7 +3219,74 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
+
+	/* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
+};
+
+static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
+{
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
+};
+
+static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
+{
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000)
 };
 
 #define DEFAULT_SH_MEM_CONFIG \
@@ -3192,7 +3301,7 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
-                                 struct amdgpu_cu_info *cu_info);
+				 struct amdgpu_cu_info *cu_info);
 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 				   u32 sh_num, u32 instance);
@@ -3389,7 +3498,16 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
 						golden_settings_gc_10_3_2,
 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
 		break;
-
+	case CHIP_VANGOGH:
+		soc15_program_register_sequence(adev,
+						golden_settings_gc_10_3_vangogh,
+						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
+		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		soc15_program_register_sequence(adev,
+                                                golden_settings_gc_10_3_4,
+                                                (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
+		break;
 	default:
 		break;
 	}
@@ -3573,6 +3691,8 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
 		break;
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		adev->gfx.cp_fw_write_wait = true;
 		break;
 	default:
@@ -3640,7 +3760,7 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
 		if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		break;
-	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		break;
 	default:
@@ -3685,6 +3805,12 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
 	case CHIP_NAVY_FLOUNDER:
 		chip_name = "navy_flounder";
 		break;
+	case CHIP_VANGOGH:
+		chip_name = "vangogh";
+		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		chip_name = "dimgrey_cavefish";
+		break;
 	default:
 		BUG();
 	}
@@ -4200,11 +4326,26 @@ static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
 }
 
 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
-									  u32 me, u32 pipe, u32 q, u32 vm)
- {
-       nv_grbm_select(adev, me, pipe, q, vm);
- }
+				       u32 me, u32 pipe, u32 q, u32 vm)
+{
+	nv_grbm_select(adev, me, pipe, q, vm);
+}
 
+static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
+					  bool enable)
+{
+	uint32_t data, def;
+
+	data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
+
+	if (enable)
+		data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
+	else
+		data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
+
+	if (data != def)
+		WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
+}
 
 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
 	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
@@ -4214,6 +4355,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
 	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
 	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
 	.init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
+	.update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
 };
 
 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
@@ -4235,6 +4377,8 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
 		break;
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		adev->gfx.config.max_hw_contexts = 8;
 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4358,6 +4502,8 @@ static int gfx_v10_0_sw_init(void *handle)
 		break;
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		adev->gfx.me.num_me = 1;
 		adev->gfx.me.num_pipe_per_me = 1;
 		adev->gfx.me.num_queue_per_pipe = 1;
@@ -4617,8 +4763,7 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
 
 	/* for ASICs that integrates GFX v10.3
 	 * pa_sc_tile_steering_override should be set to 0 */
-	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-	    adev->asic_type == CHIP_NAVY_FLOUNDER)
+	if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 		return 0;
 
 	/* init num_sc */
@@ -5855,6 +6000,8 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
 				    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
@@ -5988,6 +6135,8 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
 		switch (adev->asic_type) {
 		case CHIP_SIENNA_CICHLID:
 		case CHIP_NAVY_FLOUNDER:
+		case CHIP_VANGOGH:
+		case CHIP_DIMGREY_CAVEFISH:
 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
 			break;
 		default:
@@ -5998,6 +6147,8 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
 		switch (adev->asic_type) {
 		case CHIP_SIENNA_CICHLID:
 		case CHIP_NAVY_FLOUNDER:
+		case CHIP_VANGOGH:
+		case CHIP_DIMGREY_CAVEFISH:
 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
@@ -6092,6 +6243,8 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
 		tmp &= 0xffffff00;
 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
@@ -6800,6 +6953,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
@@ -6812,6 +6966,8 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
 			return false;
 		}
 		break;
+	case CHIP_VANGOGH:
+		return true;
 	default:
 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
@@ -6839,6 +6995,8 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
@@ -6954,6 +7112,18 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
 }
 
+static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
+{
+	uint32_t data;
+	data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
+	data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
+	WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
+
+	data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
+	data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
+	WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
+}
+
 static int gfx_v10_0_hw_init(void *handle)
 {
 	int r;
@@ -6968,7 +7138,7 @@ static int gfx_v10_0_hw_init(void *handle)
 		 * loaded firstly, so in direct type, it has to load smc ucode
 		 * here before rlc.
 		 */
-		if (adev->smu.ppt_funcs != NULL) {
+		if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) {
 			r = smu_load_microcode(&adev->smu);
 			if (r)
 				return r;
@@ -6979,6 +7149,7 @@ static int gfx_v10_0_hw_init(void *handle)
 				return r;
 			}
 		}
+		gfx_v10_0_disable_gpa_mode(adev);
 	}
 
 	/* if GRBM CAM not remapped, set up the remapping */
@@ -7136,6 +7307,8 @@ static int gfx_v10_0_soft_reset(void *handle)
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
 							GRBM_SOFT_RESET,
@@ -7235,13 +7408,16 @@ static int gfx_v10_0_early_init(void *handle)
 		break;
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
 		break;
 	default:
 		break;
 	}
 
-	adev->gfx.num_compute_rings = amdgpu_num_kcq;
+	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+					  AMDGPU_MAX_COMPUTE_RINGS);
 
 	gfx_v10_0_set_kiq_pm4_funcs(adev);
 	gfx_v10_0_set_ring_funcs(adev);
@@ -7288,6 +7464,8 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
 
 		/* wait for RLC_SAFE_MODE */
@@ -7320,6 +7498,8 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
 		break;
 	default:
@@ -7344,6 +7524,7 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
 		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
+			  RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
 			  RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
@@ -7480,12 +7661,50 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
 	}
 }
 
+static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
+						      bool enable)
+{
+	uint32_t def, data;
+
+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
+		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
+		/* unset FGCG override */
+		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
+		/* update FGCG override bits */
+		if (def != data)
+			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
+
+		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
+		/* unset RLC SRAM CLK GATER override */
+		data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
+		/* update RLC SRAM CLK GATER override bits */
+		if (def != data)
+			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
+	} else {
+		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
+		/* reset FGCG bits */
+		data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
+		/* disable FGCG*/
+		if (def != data)
+			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
+
+		def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
+		/* reset RLC SRAM CLK GATER bits */
+		data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
+		/* disable RLC SRAM CLK*/
+		if (def != data)
+			WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
+	}
+}
+
 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 					    bool enable)
 {
 	amdgpu_gfx_rlc_enter_safe_mode(adev);
 
 	if (enable) {
+		/* enable FGCG firstly*/
+		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
 		/* CGCG/CGLS should be enabled after MGCG/MGLS
 		 * ===  MGCG + MGLS ===
 		 */
@@ -7503,6 +7722,8 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
 		gfx_v10_0_update_3d_clock_gating(adev, enable);
 		/* ===  MGCG + MGLS === */
 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
+		/* disable fgcg at last*/
+		gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
 	}
 
 	if (adev->cg_flags &
@@ -7564,6 +7785,27 @@ static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offse
 	return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
 }
 
+static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
+{
+	u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
+
+	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
+		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+	else
+		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+
+	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
+}
+
+static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
+{
+	amdgpu_gfx_rlc_enter_safe_mode(adev);
+
+	gfx_v10_cntl_power_gating(adev, enable);
+
+	amdgpu_gfx_rlc_exit_safe_mode(adev);
+}
+
 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
 	.set_safe_mode = gfx_v10_0_set_safe_mode,
@@ -7609,8 +7851,12 @@ static int gfx_v10_0_set_powergating_state(void *handle,
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		amdgpu_gfx_off_ctrl(adev, enable);
 		break;
+	case CHIP_VANGOGH:
+		gfx_v10_cntl_pg(adev, enable);
+		break;
 	default:
 		break;
 	}
@@ -7631,6 +7877,8 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		gfx_v10_0_update_gfx_clock_gating(adev,
 						 state == AMD_CG_STATE_GATE);
 		break;
@@ -7645,6 +7893,11 @@ static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	int data;
 
+	/* AMD_CG_SUPPORT_GFX_FGCG */
+	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
+	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
+		*flags |= AMD_CG_SUPPORT_GFX_FGCG;
+
 	/* AMD_CG_SUPPORT_GFX_MGCG */
 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
@@ -8733,6 +8986,8 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
 	case CHIP_NAVI14:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
 		break;
 	case CHIP_NAVI12:
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 79c52c7a02e3..671c46ebeced 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3064,7 +3064,8 @@ static int gfx_v6_0_early_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
-	adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
+	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+					  GFX6_NUM_COMPUTE_RINGS);
 	adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
 	adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs;
 	gfx_v6_0_set_ring_funcs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 04eaf3a8fddb..cb07bc21dcbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4238,7 +4238,8 @@ static int gfx_v7_0_early_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
-	adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
+	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+					  AMDGPU_MAX_COMPUTE_RINGS);
 	adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
 	adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
 	gfx_v7_0_set_ring_funcs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 94b7e0531d09..c3fff49e6514 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -729,8 +729,13 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 
+#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK                    0x0000007fL
+#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT                  0x00000000L
+
 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 {
+	uint32_t data;
+
 	switch (adev->asic_type) {
 	case CHIP_TOPAZ:
 		amdgpu_device_program_register_sequence(adev,
@@ -790,11 +795,14 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 		amdgpu_device_program_register_sequence(adev,
 							polaris10_golden_common_all,
 							ARRAY_SIZE(polaris10_golden_common_all));
-		WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
-		if (adev->pdev->revision == 0xc7 &&
+		data = RREG32_SMC(ixCG_ACLK_CNTL);
+		data &= ~CG_ACLK_CNTL__ACLK_DIVIDER_MASK;
+		data |= 0x18 << CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT;
+		WREG32_SMC(ixCG_ACLK_CNTL, data);
+		if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) &&
 		    ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
 		     (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
-		     (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1682))) {
+		     (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) {
 			amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
 			amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
 		}
@@ -5058,7 +5066,7 @@ static int gfx_v8_0_pre_soft_reset(void *handle)
 		gfx_v8_0_cp_compute_enable(adev, false);
 	}
 
-       return 0;
+	return 0;
 }
 
 static int gfx_v8_0_soft_reset(void *handle)
@@ -5295,7 +5303,8 @@ static int gfx_v8_0_early_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
-	adev->gfx.num_compute_rings = amdgpu_num_kcq;
+	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+					  AMDGPU_MAX_COMPUTE_RINGS);
 	adev->gfx.funcs = &gfx_v8_0_gfx_funcs;
 	gfx_v8_0_set_ring_funcs(adev);
 	gfx_v8_0_set_irq_funcs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6959aebae6d4..3d6fb5a514c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -117,6 +117,13 @@ MODULE_FIRMWARE("amdgpu/renoir_mec.bin");
 MODULE_FIRMWARE("amdgpu/renoir_mec2.bin");
 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
 
+MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin");
+MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin");
+MODULE_FIRMWARE("amdgpu/green_sardine_me.bin");
+MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin");
+MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin");
+MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin");
+
 #define mmTCP_CHAN_STEER_0_ARCT								0x0b03
 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX							0
 #define mmTCP_CHAN_STEER_1_ARCT								0x0b04
@@ -787,7 +794,7 @@ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
-                                 struct amdgpu_cu_info *cu_info);
+				struct amdgpu_cu_info *cu_info);
 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
@@ -1630,7 +1637,10 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 		chip_name = "arcturus";
 		break;
 	case CHIP_RENOIR:
-		chip_name = "renoir";
+		if (adev->apu_flags & AMD_APU_IS_RENOIR)
+			chip_name = "renoir";
+		else
+			chip_name = "green_sardine";
 		break;
 	default:
 		BUG();
@@ -4623,7 +4633,8 @@ static int gfx_v9_0_early_init(void *handle)
 		adev->gfx.num_gfx_rings = 0;
 	else
 		adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
-	adev->gfx.num_compute_rings = amdgpu_num_kcq;
+	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
+					  AMDGPU_MAX_COMPUTE_RINGS);
 	gfx_v9_0_set_kiq_pm4_funcs(adev);
 	gfx_v9_0_set_ring_funcs(adev);
 	gfx_v9_0_set_irq_funcs(adev);
@@ -5167,7 +5178,7 @@ static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 
 	if (ring->use_doorbell) {
 		/* XXX check if swapping is necessary on BE */
-		atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
 		WDOORBELL64(ring->doorbell_index, ring->wptr);
 	} else {
 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
@@ -5353,7 +5364,7 @@ static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
 
 	/* XXX check if swapping is necessary on BE */
 	if (ring->use_doorbell) {
-		atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
+		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
 		WDOORBELL64(ring->doorbell_index, ring->wptr);
 	} else{
 		BUG(); /* only DOORBELL method supported on gfx9 now */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index fad887a66886..d83577b77a66 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -22,6 +22,7 @@
  */
 #include "amdgpu.h"
 #include "gfxhub_v1_0.h"
+#include "gfxhub_v1_1.h"
 
 #include "gc/gc_9_0_offset.h"
 #include "gc/gc_9_0_sh_mask.h"
@@ -412,4 +413,5 @@ const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = {
 	.gart_disable = gfxhub_v1_0_gart_disable,
 	.set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default,
 	.init = gfxhub_v1_0_init,
+	.get_xgmi_info = gfxhub_v1_1_get_xgmi_info,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
index 1e24b6d51e41..c0ab71df0d90 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c
@@ -21,7 +21,6 @@
  *
  */
 #include "amdgpu.h"
-#include "gfxhub_v1_0.h"
 #include "gfxhub_v1_1.h"
 
 #include "gc/gc_9_2_1_offset.h"
@@ -29,7 +28,7 @@
 
 #include "soc15_common.h"
 
-static int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
+int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
 {
 	u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
 	u32 max_region =
@@ -67,13 +66,3 @@ static int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
 
 	return 0;
 }
-
-const struct amdgpu_gfxhub_funcs gfxhub_v1_1_funcs = {
-	.get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset,
-	.setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs,
-	.gart_enable = gfxhub_v1_0_gart_enable,
-	.gart_disable = gfxhub_v1_0_gart_disable,
-	.set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default,
-	.init = gfxhub_v1_0_init,
-	.get_xgmi_info = gfxhub_v1_1_get_xgmi_info,
-};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h
index ae5759ffbee3..d753cf28a0a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.h
@@ -24,6 +24,6 @@
 #ifndef __GFXHUB_V1_1_H__
 #define __GFXHUB_V1_1_H__
 
-extern const struct amdgpu_gfxhub_funcs gfxhub_v1_1_funcs;
+int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev);
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index dbc8b76b9b78..d9399324be47 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -46,6 +46,7 @@
 #include "gfxhub_v2_0.h"
 #include "gfxhub_v2_1.h"
 #include "mmhub_v2_0.h"
+#include "mmhub_v2_3.h"
 #include "athub_v2_0.h"
 #include "athub_v2_1.h"
 
@@ -106,7 +107,8 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
 		 * be updated to avoid reading an incorrect value due to
 		 * the new fast GRBM interface.
 		 */
-		if (entry->vmid_src == AMDGPU_GFXHUB_0)
+		if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
+		    (adev->asic_type < CHIP_SIENNA_CICHLID))
 			RREG32(hub->vm_l2_pro_fault_status);
 
 		status = RREG32(hub->vm_l2_pro_fault_status);
@@ -145,7 +147,7 @@ static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
 	.process = amdgpu_umc_process_ecc_irq,
 };
 
- static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
+static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
 {
 	adev->gmc.vm_fault.num_types = 1;
 	adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
@@ -231,7 +233,8 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 	 * Issue a dummy read to wait for the ACK register to be cleared
 	 * to avoid a false ACK due to the new fast GRBM interface.
 	 */
-	if (vmhub == AMDGPU_GFXHUB_0)
+	if ((vmhub == AMDGPU_GFXHUB_0) &&
+	    (adev->asic_type < CHIP_SIENNA_CICHLID))
 		RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng);
 
 	/* Wait for ACK with a delay.*/
@@ -483,7 +486,8 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid
 /*
  * PTE format on NAVI 10:
  * 63:59 reserved
- * 58:57 reserved
+ * 58 reserved and for sienna_cichlid is used for MALL noalloc
+ * 57 reserved
  * 56 F
  * 55 L
  * 54 reserved
@@ -631,7 +635,14 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
 
 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
 {
-	adev->mmhub.funcs = &mmhub_v2_0_funcs;
+	switch (adev->asic_type) {
+	case CHIP_VANGOGH:
+		adev->mmhub.funcs = &mmhub_v2_3_funcs;
+		break;
+	default:
+		adev->mmhub.funcs = &mmhub_v2_0_funcs;
+		break;
+	}
 }
 
 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
@@ -639,6 +650,8 @@ static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
 		break;
 	default:
@@ -733,6 +746,13 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 
+#ifdef CONFIG_X86_64
+	if (adev->flags & AMD_IS_APU) {
+		adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
+		adev->gmc.aper_size = adev->gmc.real_vram_size;
+	}
+#endif
+
 	/* In case the PCI BAR is larger than the actual amount of vram */
 	adev->gmc.visible_vram_size = adev->gmc.aper_size;
 	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
@@ -746,6 +766,8 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 		case CHIP_NAVI12:
 		case CHIP_SIENNA_CICHLID:
 		case CHIP_NAVY_FLOUNDER:
+		case CHIP_VANGOGH:
+		case CHIP_DIMGREY_CAVEFISH:
 		default:
 			adev->gmc.gart_size = 512ULL << 20;
 			break;
@@ -790,7 +812,10 @@ static int gmc_v10_0_sw_init(void *handle)
 
 	spin_lock_init(&adev->gmc.invalidate_lock);
 
-	if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) {
+	if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
+		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
+		adev->gmc.vram_width = 64;
+	} else if (amdgpu_emu_mode == 1) {
 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 		adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
 	} else {
@@ -808,6 +833,8 @@ static int gmc_v10_0_sw_init(void *handle)
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		adev->num_vmhubs = 2;
 		/*
 		 * To fulfill 4-level page support,
@@ -921,6 +948,8 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		break;
 	default:
 		break;
@@ -1081,8 +1110,8 @@ static int gmc_v10_0_set_clockgating_state(void *handle,
 	if (r)
 		return r;
 
-	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-	    adev->asic_type == CHIP_NAVY_FLOUNDER)
+	if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
+	    adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
 		return athub_v2_1_set_clockgating(adev, state);
 	else
 		return athub_v2_0_set_clockgating(adev, state);
@@ -1094,8 +1123,8 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
 
 	adev->mmhub.funcs->get_clockgating(adev, flags);
 
-	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-	    adev->asic_type == CHIP_NAVY_FLOUNDER)
+	if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
+	    adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
 		athub_v2_1_get_clockgating(adev, flags);
 	else
 		athub_v2_0_get_clockgating(adev, flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9ab65ca7df77..0f32a8002c3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -230,36 +230,20 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 		chip_name = "tonga";
 		break;
 	case CHIP_POLARIS11:
-		if (((adev->pdev->device == 0x67ef) &&
-		     ((adev->pdev->revision == 0xe0) ||
-		      (adev->pdev->revision == 0xe5))) ||
-		    ((adev->pdev->device == 0x67ff) &&
-		     ((adev->pdev->revision == 0xcf) ||
-		      (adev->pdev->revision == 0xef) ||
-		      (adev->pdev->revision == 0xff))))
-			chip_name = "polaris11_k";
-		else if ((adev->pdev->device == 0x67ef) &&
-			 (adev->pdev->revision == 0xe2))
+		if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
+		    ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
 			chip_name = "polaris11_k";
 		else
 			chip_name = "polaris11";
 		break;
 	case CHIP_POLARIS10:
-		if ((adev->pdev->device == 0x67df) &&
-		    ((adev->pdev->revision == 0xe1) ||
-		     (adev->pdev->revision == 0xf7)))
+		if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
 			chip_name = "polaris10_k";
 		else
 			chip_name = "polaris10";
 		break;
 	case CHIP_POLARIS12:
-		if (((adev->pdev->device == 0x6987) &&
-		     ((adev->pdev->revision == 0xc0) ||
-		      (adev->pdev->revision == 0xc3))) ||
-		    ((adev->pdev->device == 0x6981) &&
-		     ((adev->pdev->revision == 0x00) ||
-		      (adev->pdev->revision == 0x01) ||
-		      (adev->pdev->revision == 0x10))))
+		if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision))
 			chip_name = "polaris12_k";
 		else
 			chip_name = "polaris12";
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 3ebbddb63705..0c3421d587e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -510,15 +510,16 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 }
 
 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
-				struct amdgpu_irq_src *source,
-				struct amdgpu_iv_entry *entry)
+				      struct amdgpu_irq_src *source,
+				      struct amdgpu_iv_entry *entry)
 {
-	struct amdgpu_vmhub *hub;
 	bool retry_fault = !!(entry->src_data[1] & 0x80);
 	uint32_t status = 0, cid = 0, rw = 0;
-	u64 addr;
-	char hub_name[10];
+	struct amdgpu_task_info task_info;
+	struct amdgpu_vmhub *hub;
 	const char *mmhub_cid;
+	const char *hub_name;
+	u64 addr;
 
 	addr = (u64)entry->src_data[0] << 12;
 	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
@@ -527,105 +528,103 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 						    entry->timestamp))
 		return 1; /* This also prevents sending it to KFD */
 
+	/* If it's the first fault for this address, process it normally */
+	if (retry_fault && !in_interrupt() &&
+	    amdgpu_vm_handle_fault(adev, entry->pasid, addr))
+		return 1; /* This also prevents sending it to KFD */
+
+	if (!printk_ratelimit())
+		return 0;
+
 	if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
-		snprintf(hub_name, sizeof(hub_name), "mmhub0");
+		hub_name = "mmhub0";
 		hub = &adev->vmhub[AMDGPU_MMHUB_0];
 	} else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
-		snprintf(hub_name, sizeof(hub_name), "mmhub1");
+		hub_name = "mmhub1";
 		hub = &adev->vmhub[AMDGPU_MMHUB_1];
 	} else {
-		snprintf(hub_name, sizeof(hub_name), "gfxhub0");
+		hub_name = "gfxhub0";
 		hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 	}
 
-	/* If it's the first fault for this address, process it normally */
-	if (retry_fault && !in_interrupt() &&
-	    amdgpu_vm_handle_fault(adev, entry->pasid, addr))
-		return 1; /* This also prevents sending it to KFD */
+	memset(&task_info, 0, sizeof(struct amdgpu_task_info));
+	amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 
-	if (!amdgpu_sriov_vf(adev)) {
-		/*
-		 * Issue a dummy read to wait for the status register to
-		 * be updated to avoid reading an incorrect value due to
-		 * the new fast GRBM interface.
-		 */
-		if (entry->vmid_src == AMDGPU_GFXHUB_0)
-			RREG32(hub->vm_l2_pro_fault_status);
-
-		status = RREG32(hub->vm_l2_pro_fault_status);
-		cid = REG_GET_FIELD(status,
-				    VM_L2_PROTECTION_FAULT_STATUS, CID);
-		rw = REG_GET_FIELD(status,
-				   VM_L2_PROTECTION_FAULT_STATUS, RW);
-		WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
-	}
+	dev_err(adev->dev,
+		"[%s] %s page fault (src_id:%u ring:%u vmid:%u "
+		"pasid:%u, for process %s pid %d thread %s pid %d)\n",
+		hub_name, retry_fault ? "retry" : "no-retry",
+		entry->src_id, entry->ring_id, entry->vmid,
+		entry->pasid, task_info.process_name, task_info.tgid,
+		task_info.task_name, task_info.pid);
+	dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
+		addr, entry->client_id);
 
-	if (printk_ratelimit()) {
-		struct amdgpu_task_info task_info;
-
-		memset(&task_info, 0, sizeof(struct amdgpu_task_info));
-		amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
-
-		dev_err(adev->dev,
-			"[%s] %s page fault (src_id:%u ring:%u vmid:%u "
-			"pasid:%u, for process %s pid %d thread %s pid %d)\n",
-			hub_name, retry_fault ? "retry" : "no-retry",
-			entry->src_id, entry->ring_id, entry->vmid,
-			entry->pasid, task_info.process_name, task_info.tgid,
-			task_info.task_name, task_info.pid);
-		dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
-			addr, entry->client_id);
-		if (!amdgpu_sriov_vf(adev)) {
-			dev_err(adev->dev,
-				"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
-				status);
-			if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) {
-				dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
-					cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
-					cid);
-			} else {
-				switch (adev->asic_type) {
-				case CHIP_VEGA10:
-					mmhub_cid = mmhub_client_ids_vega10[cid][rw];
-					break;
-				case CHIP_VEGA12:
-					mmhub_cid = mmhub_client_ids_vega12[cid][rw];
-					break;
-				case CHIP_VEGA20:
-					mmhub_cid = mmhub_client_ids_vega20[cid][rw];
-					break;
-				case CHIP_ARCTURUS:
-					mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
-					break;
-				case CHIP_RAVEN:
-					mmhub_cid = mmhub_client_ids_raven[cid][rw];
-					break;
-				case CHIP_RENOIR:
-					mmhub_cid = mmhub_client_ids_renoir[cid][rw];
-					break;
-				default:
-					mmhub_cid = NULL;
-					break;
-				}
-				dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
-					mmhub_cid ? mmhub_cid : "unknown", cid);
-			}
-			dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
-				REG_GET_FIELD(status,
-				VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
-			dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
-				REG_GET_FIELD(status,
-				VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
-			dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
-				REG_GET_FIELD(status,
-				VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
-			dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
-				REG_GET_FIELD(status,
-				VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
-			dev_err(adev->dev, "\t RW: 0x%x\n", rw);
+	if (amdgpu_sriov_vf(adev))
+		return 0;
+
+	/*
+	 * Issue a dummy read to wait for the status register to
+	 * be updated to avoid reading an incorrect value due to
+	 * the new fast GRBM interface.
+	 */
+	if (entry->vmid_src == AMDGPU_GFXHUB_0)
+		RREG32(hub->vm_l2_pro_fault_status);
+
+	status = RREG32(hub->vm_l2_pro_fault_status);
+	cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
+	rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
+	WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
+
+
+	dev_err(adev->dev,
+		"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
+		status);
+	if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) {
+		dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
+			cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
+			gfxhub_client_ids[cid],
+			cid);
+	} else {
+		switch (adev->asic_type) {
+		case CHIP_VEGA10:
+			mmhub_cid = mmhub_client_ids_vega10[cid][rw];
+			break;
+		case CHIP_VEGA12:
+			mmhub_cid = mmhub_client_ids_vega12[cid][rw];
+			break;
+		case CHIP_VEGA20:
+			mmhub_cid = mmhub_client_ids_vega20[cid][rw];
+			break;
+		case CHIP_ARCTURUS:
+			mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
+			break;
+		case CHIP_RAVEN:
+			mmhub_cid = mmhub_client_ids_raven[cid][rw];
+			break;
+		case CHIP_RENOIR:
+			mmhub_cid = mmhub_client_ids_renoir[cid][rw];
+			break;
+		default:
+			mmhub_cid = NULL;
+			break;
 		}
+		dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
+			mmhub_cid ? mmhub_cid : "unknown", cid);
 	}
-
+	dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
+		REG_GET_FIELD(status,
+		VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
+	dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
+		REG_GET_FIELD(status,
+		VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
+	dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
+		REG_GET_FIELD(status,
+		VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
+	dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
+		REG_GET_FIELD(status,
+		VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
+	dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 	return 0;
 }
 
@@ -1166,15 +1165,7 @@ static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
 
 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 {
-	switch (adev->asic_type) {
-	case CHIP_ARCTURUS:
-	case CHIP_VEGA20:
-		adev->gfxhub.funcs = &gfxhub_v1_1_funcs;
-		break;
-	default:
-		adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
-		break;
-	}
+	adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
 }
 
 static int gmc_v9_0_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index 94caf5204c8b..6b80dcea80ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -32,19 +32,19 @@
 #include "vcn/vcn_2_0_0_sh_mask.h"
 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
 
-#define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 			0x1bfff
+#define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET				0x1bfff
 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET				0x4029
 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET				0x402a
 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET				0x402b
 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ea
-#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x40eb
+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40eb
 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET				0x40cf
 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET				0x40d1
-#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 		0x40e8
+#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET			0x40e8
 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40e9
 #define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET				0x4082
 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ec
-#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x40ed
+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40ed
 #define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET			0x4085
 #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET				0x4084
 #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET				0x4089
@@ -247,7 +247,7 @@ static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
 	return 0;
 }
 
-static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev)
+static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev)
 {
 	if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
 		uint32_t data;
@@ -274,7 +274,7 @@ static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev)
 	return 0;
 }
 
-static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device* adev)
+static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev)
 {
 	uint32_t data;
 
@@ -297,7 +297,7 @@ static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device* adev)
 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
 }
 
-static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device* adev)
+static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev)
 {
 	uint32_t data;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index 845306f63cdb..c6724a0e0c43 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -247,7 +247,7 @@ static int jpeg_v2_5_resume(void *handle)
 	return r;
 }
 
-static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device* adev, int inst)
+static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
 {
 	uint32_t data;
 
@@ -276,7 +276,7 @@ static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device* adev, int inst)
 	WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
 }
 
-static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device* adev, int inst)
+static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
 {
 	uint32_t data;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 3a0dff53654d..e8fbb2a0de34 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -213,7 +213,7 @@ static int jpeg_v3_0_resume(void *handle)
 	return r;
 }
 
-static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device* adev)
+static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device *adev)
 {
 	uint32_t data = 0;
 
@@ -243,7 +243,7 @@ static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device* adev)
 	WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
 }
 
-static void jpeg_v3_0_enable_clock_gating(struct amdgpu_device* adev)
+static void jpeg_v3_0_enable_clock_gating(struct amdgpu_device *adev)
 {
 	uint32_t data = 0;
 
@@ -286,7 +286,7 @@ static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev)
 	return 0;
 }
 
-static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device* adev)
+static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device *adev)
 {
 	/* enable anti hang mechanism */
 	WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
index 1c22d8393b21..985e454463e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
@@ -46,7 +46,7 @@ static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 
 	if (ring->use_doorbell) {
-		atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs],
+		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs],
 			     ring->wptr);
 		WDOORBELL64(ring->doorbell_index, ring->wptr);
 	} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index f84701c562bf..0309d84c887d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -409,7 +409,7 @@ static void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool
 				CRASH_ON_NO_RETRY_FAULT, 1);
 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 				CRASH_ON_RETRY_FAULT, 1);
-    }
+	}
 
 	WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 }
@@ -712,7 +712,7 @@ static int mmhub_v1_0_get_ras_error_count(struct amdgpu_device *adev,
 	uint32_t sec_cnt, ded_cnt;
 
 	for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_ras_fields); i++) {
-		if(mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset)
+		if (mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset)
 			continue;
 
 		sec_cnt = (value &
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 2063700f0bc6..4ac8ac0c56c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -543,6 +543,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 		def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
 		break;
@@ -576,6 +577,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		if (def != data)
 			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
 		if (def1 != data1)
@@ -598,6 +600,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 		break;
 	default:
@@ -614,6 +617,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade
 		switch (adev->asic_type) {
 		case CHIP_SIENNA_CICHLID:
 		case CHIP_NAVY_FLOUNDER:
+		case CHIP_DIMGREY_CAVEFISH:
 			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
 			break;
 		default:
@@ -635,6 +639,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		mmhub_v2_0_update_medium_grain_clock_gating(adev,
 				state == AMD_CG_STATE_GATE);
 		mmhub_v2_0_update_medium_grain_light_sleep(adev,
@@ -657,6 +662,7 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 		data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
new file mode 100644
index 000000000000..3a248c8cd0b9
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -0,0 +1,589 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "mmhub_v2_3.h"
+
+#include "mmhub/mmhub_2_3_0_offset.h"
+#include "mmhub/mmhub_2_3_0_sh_mask.h"
+#include "mmhub/mmhub_2_3_0_default.h"
+#include "navi10_enum.h"
+
+#include "soc15_common.h"
+
+static const char *mmhub_client_ids_vangogh[][2] = {
+	[0][0] = "MP0",
+	[1][0] = "MP1",
+	[2][0] = "DCEDMC",
+	[3][0] = "DCEVGA",
+	[13][0] = "UTCL2",
+	[26][0] = "OSS",
+	[27][0] = "HDP",
+	[28][0] = "VCN",
+	[29][0] = "VCNU",
+	[30][0] = "JPEG",
+	[0][1] = "MP0",
+	[1][1] = "MP1",
+	[2][1] = "DCEDMC",
+	[3][1] = "DCEVGA",
+	[4][1] = "DCEDWB",
+	[5][1] = "XDP",
+	[26][1] = "OSS",
+	[27][1] = "HDP",
+	[28][1] = "VCN",
+	[29][1] = "VCNU",
+	[30][1] = "JPEG",
+};
+
+static uint32_t mmhub_v2_3_get_invalidate_req(unsigned int vmid,
+					      uint32_t flush_type)
+{
+	u32 req = 0;
+
+	/* invalidate using legacy mode on vmid*/
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
+			    PER_VMID_INVALIDATE_REQ, 1 << vmid);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
+	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
+			    CLEAR_PROTECTION_FAULT_STATUS_ADDR,	0);
+
+	return req;
+}
+
+static void
+mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
+					     uint32_t status)
+{
+	uint32_t cid, rw;
+	const char *mmhub_cid = NULL;
+
+	cid = REG_GET_FIELD(status,
+			    MMVM_L2_PROTECTION_FAULT_STATUS, CID);
+	rw = REG_GET_FIELD(status,
+			   MMVM_L2_PROTECTION_FAULT_STATUS, RW);
+
+	dev_err(adev->dev,
+		"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
+		status);
+	switch (adev->asic_type) {
+	case CHIP_VANGOGH:
+		mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
+		break;
+	default:
+		mmhub_cid = NULL;
+		break;
+	}
+	dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
+		mmhub_cid ? mmhub_cid : "unknown", cid);
+	dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
+	dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
+	dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
+	dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
+		REG_GET_FIELD(status,
+		MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
+	dev_err(adev->dev, "\t RW: 0x%x\n", rw);
+}
+
+static void mmhub_v2_3_setup_vm_pt_regs(struct amdgpu_device *adev,
+					uint32_t vmid,
+					uint64_t page_table_base)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+
+	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+			    hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
+
+	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+			    hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));
+}
+
+static void mmhub_v2_3_init_gart_aperture_regs(struct amdgpu_device *adev)
+{
+	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
+
+	mmhub_v2_3_setup_vm_pt_regs(adev, 0, pt_base);
+
+	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+		     (u32)(adev->gmc.gart_start >> 12));
+	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+		     (u32)(adev->gmc.gart_start >> 44));
+
+	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+		     (u32)(adev->gmc.gart_end >> 12));
+	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+		     (u32)(adev->gmc.gart_end >> 44));
+}
+
+static void mmhub_v2_3_init_system_aperture_regs(struct amdgpu_device *adev)
+{
+	uint64_t value;
+	uint32_t tmp;
+
+	/* Disable AGP. */
+	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
+	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0);
+	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF);
+
+	/* Program the system aperture low logical page number. */
+	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
+		     adev->gmc.vram_start >> 18);
+	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+		     adev->gmc.vram_end >> 18);
+
+	/* Set default page address. */
+	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
+		adev->vm_manager.vram_base_offset;
+	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
+		     (u32)(value >> 12));
+	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
+		     (u32)(value >> 44));
+
+	/* Program "protection fault". */
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
+		     (u32)(adev->dummy_page_addr >> 12));
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
+		     (u32)((u64)adev->dummy_page_addr >> 44));
+
+	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
+			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
+}
+
+static void mmhub_v2_3_init_tlb_regs(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* Setup TLB control */
+	tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
+
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    MTYPE, MTYPE_UC); /* UC, uncached */
+
+	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
+}
+
+static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* Setup L2 cache */
+	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
+			    ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
+	/* XXX for emulation, Refer to closed source code.*/
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
+			    0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
+
+	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
+
+	tmp = mmMMVM_L2_CNTL3_DEFAULT;
+	if (adev->gmc.translate_further) {
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
+	} else {
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
+				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
+	}
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
+
+	tmp = mmMMVM_L2_CNTL4_DEFAULT;
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
+
+	tmp = mmMMVM_L2_CNTL5_DEFAULT;
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
+	WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
+}
+
+static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
+	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
+			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
+}
+
+static void mmhub_v2_3_disable_identity_aperture(struct amdgpu_device *adev)
+{
+	WREG32_SOC15(MMHUB, 0,
+		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
+		     0xFFFFFFFF);
+	WREG32_SOC15(MMHUB, 0,
+		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
+		     0x0000000F);
+
+	WREG32_SOC15(MMHUB, 0,
+		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
+	WREG32_SOC15(MMHUB, 0,
+		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
+
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
+		     0);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
+		     0);
+}
+
+static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+	int i;
+	uint32_t tmp;
+
+	for (i = 0; i <= 14; i++) {
+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
+				    adev->vm_manager.num_level);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
+				    1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    PAGE_TABLE_BLOCK_SIZE,
+				    adev->vm_manager.block_size - 9);
+		/* Send no-retry XNACK on fault to suppress VM fault storm. */
+		tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
+				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
+				    !amdgpu_noretry);
+		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
+				    i * hub->ctx_distance, tmp);
+		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
+				    i * hub->ctx_addr_distance, 0);
+		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
+				    i * hub->ctx_addr_distance, 0);
+		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
+				    i * hub->ctx_addr_distance,
+				    lower_32_bits(adev->vm_manager.max_pfn - 1));
+		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
+				    i * hub->ctx_addr_distance,
+				    upper_32_bits(adev->vm_manager.max_pfn - 1));
+	}
+}
+
+static void mmhub_v2_3_program_invalidation(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+	unsigned i;
+
+	for (i = 0; i < 18; ++i) {
+		WREG32_SOC15_OFFSET(MMHUB, 0,
+				    mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
+				    i * hub->eng_addr_distance, 0xffffffff);
+		WREG32_SOC15_OFFSET(MMHUB, 0,
+				    mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
+				    i * hub->eng_addr_distance, 0x1f);
+	}
+}
+
+static int mmhub_v2_3_gart_enable(struct amdgpu_device *adev)
+{
+	if (amdgpu_sriov_vf(adev)) {
+		/*
+		 * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+		 * VF copy registers so vbios post doesn't program them, for
+		 * SRIOV driver need to program them
+		 */
+		WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE,
+			     adev->gmc.vram_start >> 24);
+		WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP,
+			     adev->gmc.vram_end >> 24);
+	}
+
+	/* GART Enable. */
+	mmhub_v2_3_init_gart_aperture_regs(adev);
+	mmhub_v2_3_init_system_aperture_regs(adev);
+	mmhub_v2_3_init_tlb_regs(adev);
+	mmhub_v2_3_init_cache_regs(adev);
+
+	mmhub_v2_3_enable_system_domain(adev);
+	mmhub_v2_3_disable_identity_aperture(adev);
+	mmhub_v2_3_setup_vmid_config(adev);
+	mmhub_v2_3_program_invalidation(adev);
+
+	return 0;
+}
+
+static void mmhub_v2_3_gart_disable(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+	u32 tmp;
+	u32 i;
+
+	/* Disable all tables */
+	for (i = 0; i < 16; i++)
+		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
+				    i * hub->ctx_distance, 0);
+
+	/* Setup TLB control */
+	tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
+	tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
+			    ENABLE_ADVANCED_DRIVER_MODEL, 0);
+	WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
+
+	/* Setup L2 cache */
+	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
+}
+
+/**
+ * mmhub_v2_3_set_fault_enable_default - update GART/VM fault handling
+ *
+ * @adev: amdgpu_device pointer
+ * @value: true redirects VM faults to the default page
+ */
+static void mmhub_v2_3_set_fault_enable_default(struct amdgpu_device *adev,
+						bool value)
+{
+	u32 tmp;
+	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
+			    value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+			    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+	if (!value) {
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+				CRASH_ON_NO_RETRY_FAULT, 1);
+		tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
+				CRASH_ON_RETRY_FAULT, 1);
+	}
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
+}
+
+static const struct amdgpu_vmhub_funcs mmhub_v2_3_vmhub_funcs = {
+	.print_l2_protection_fault_status = mmhub_v2_3_print_l2_protection_fault_status,
+	.get_invalidate_req = mmhub_v2_3_get_invalidate_req,
+};
+
+static void mmhub_v2_3_init(struct amdgpu_device *adev)
+{
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
+
+	hub->ctx0_ptb_addr_lo32 =
+		SOC15_REG_OFFSET(MMHUB, 0,
+				 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
+	hub->ctx0_ptb_addr_hi32 =
+		SOC15_REG_OFFSET(MMHUB, 0,
+				 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
+	hub->vm_inv_eng0_sem =
+		SOC15_REG_OFFSET(MMHUB, 0,
+				 mmMMVM_INVALIDATE_ENG0_SEM);
+	hub->vm_inv_eng0_req =
+		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
+	hub->vm_inv_eng0_ack =
+		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
+	hub->vm_context0_cntl =
+		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
+	hub->vm_l2_pro_fault_status =
+		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
+	hub->vm_l2_pro_fault_cntl =
+		SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
+
+	hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL;
+	hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
+		mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+	hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ -
+		mmMMVM_INVALIDATE_ENG0_REQ;
+	hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
+		mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
+
+	hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
+		MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
+
+	hub->vmhub_funcs = &mmhub_v2_3_vmhub_funcs;
+}
+
+static void
+mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+					    bool enable)
+{
+	uint32_t def, data, def1, data1;
+
+	def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
+	def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
+
+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
+		data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
+
+		data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+		           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+		           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+		           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+		           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+		           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+
+	} else {
+		data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
+
+		data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+			  DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+			  DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+			  DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+			  DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+			  DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+	}
+
+	if (def != data)
+		WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
+	if (def1 != data1)
+		WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
+}
+
+static void
+mmhub_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+					   bool enable)
+{
+	uint32_t def, data;
+
+	def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
+
+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
+		data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+	else
+		data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+
+	if (def != data)
+		WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
+}
+
+static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev,
+				      enum amd_clockgating_state state)
+{
+	if (amdgpu_sriov_vf(adev))
+		return 0;
+
+	mmhub_v2_3_update_medium_grain_clock_gating(adev,
+			state == AMD_CG_STATE_GATE ? true : false);
+	mmhub_v2_3_update_medium_grain_light_sleep(adev,
+			state == AMD_CG_STATE_GATE ? true : false);
+
+	return 0;
+}
+
+static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+{
+	int data, data1;
+
+	if (amdgpu_sriov_vf(adev))
+		*flags = 0;
+
+	data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
+	data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
+
+	/* AMD_CG_SUPPORT_MC_MGCG */
+	if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
+	    !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+		       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+		       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+		       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+		       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
+		*flags |= AMD_CG_SUPPORT_MC_MGCG;
+
+	/* AMD_CG_SUPPORT_MC_LS */
+	if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
+		*flags |= AMD_CG_SUPPORT_MC_LS;
+}
+
+const struct amdgpu_mmhub_funcs mmhub_v2_3_funcs = {
+	.ras_late_init = amdgpu_mmhub_ras_late_init,
+	.init = mmhub_v2_3_init,
+	.gart_enable = mmhub_v2_3_gart_enable,
+	.set_fault_enable_default = mmhub_v2_3_set_fault_enable_default,
+	.gart_disable = mmhub_v2_3_gart_disable,
+	.set_clockgating = mmhub_v2_3_set_clockgating,
+	.get_clockgating = mmhub_v2_3_get_clockgating,
+	.setup_vm_pt_regs = mmhub_v2_3_setup_vm_pt_regs,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.h
new file mode 100644
index 000000000000..2926d21dea8b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __MMHUB_V2_3_H__
+#define __MMHUB_V2_3_H__
+
+extern const struct amdgpu_mmhub_funcs mmhub_v2_3_funcs;
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 74b1e7dc49a9..837769fcb35b 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -314,6 +314,8 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
 			switch (adev->asic_type) {
 			case CHIP_SIENNA_CICHLID:
 			case CHIP_NAVY_FLOUNDER:
+			case CHIP_VANGOGH:
+			case CHIP_DIMGREY_CAVEFISH:
 				ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
 				ih_chicken = REG_SET_FIELD(ih_chicken,
 						IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
@@ -660,8 +662,11 @@ static int navi10_ih_sw_init(void *handle)
 	/* use gpu virtual address for ih ring
 	 * until ih_checken is programmed to allow
 	 * use bus address for ih ring by psp bl */
-	use_bus_addr =
-		(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
+	if ((adev->flags & AMD_IS_APU) ||
+	    (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+		use_bus_addr = false;
+	else
+		use_bus_addr = true;
 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
 	if (r)
 		return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 7429f30398b9..e0048806afaa 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -28,10 +28,12 @@
 #include "nbio/nbio_2_3_offset.h"
 #include "nbio/nbio_2_3_sh_mask.h"
 #include <uapi/linux/kfd_ioctl.h>
+#include <linux/pci.h>
 
 #define smnPCIE_CONFIG_CNTL	0x11180044
 #define smnCPM_CONTROL		0x11180460
 #define smnPCIE_CNTL2		0x11180070
+#define smnPCIE_LC_CNTL		0x11140280
 
 #define mmBIF_SDMA2_DOORBELL_RANGE		0x01d6
 #define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX	2
@@ -312,6 +314,42 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
 		WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
 }
 
+#define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT		0x00000000 // off by default, no gains over L1
+#define NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT		0x00000009 // 1=1us, 9=1ms
+#define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT	0x0000000E // 4ms
+
+static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,
+				  bool enable)
+{
+	uint32_t def, data;
+
+	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
+
+	if (enable) {
+		/* Disable ASPM L0s/L1 first */
+		data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);
+
+		data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
+
+		if (pci_is_thunderbolt_attached(adev->pdev))
+			data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT  << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+		else
+			data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
+
+		data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+	} else {
+		/* Disbale ASPM L1 */
+		data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
+		/* Disable ASPM TxL0s */
+		data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
+		/* Disable ACPI L1 */
+		data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
+	}
+
+	if (def != data)
+		WREG32_PCIE(smnPCIE_LC_CNTL, data);
+}
+
 const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
 	.get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
 	.get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
@@ -332,4 +370,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
 	.ih_control = nbio_v2_3_ih_control,
 	.init_registers = nbio_v2_3_init_registers,
 	.remap_hdp_registers = nbio_v2_3_remap_hdp_registers,
+	.enable_aspm = nbio_v2_3_enable_aspm,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 7b2fb050407d..d2f1fe55d388 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -32,7 +32,7 @@
 
 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
 {
-        u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+	u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
 
 	tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
 	tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
@@ -114,7 +114,7 @@ static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *ad
 static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
 					bool use_doorbell, int doorbell_index)
 {
-	u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
+	u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);
 
 	if (use_doorbell) {
 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index d34628e113fc..ae685813c419 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -43,7 +43,7 @@ static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
 
 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 {
-        u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+	u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
 
 	tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
 	tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
@@ -126,7 +126,7 @@ static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *ad
 static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
 					bool use_doorbell, int doorbell_index)
 {
-	u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
+	u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);
 
 	if (use_doorbell) {
 		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
new file mode 100644
index 000000000000..aa36022670f9
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
@@ -0,0 +1,341 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "amdgpu_atombios.h"
+#include "nbio_v7_2.h"
+
+#include "nbio/nbio_7_2_0_offset.h"
+#include "nbio/nbio_7_2_0_sh_mask.h"
+#include <uapi/linux/kfd_ioctl.h>
+
+static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
+{
+	WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+	WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
+		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+}
+
+static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
+{
+	u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
+
+	tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
+	tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
+
+	return tmp;
+}
+
+static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
+{
+	if (enable)
+		WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
+			     BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
+			     BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
+	else
+		WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
+}
+
+static void nbio_v7_2_hdp_flush(struct amdgpu_device *adev,
+				struct amdgpu_ring *ring)
+{
+	if (!ring || !ring->funcs->emit_wreg)
+		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+	else
+		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+}
+
+static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
+{
+	return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
+}
+
+static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
+					  bool use_doorbell, int doorbell_index,
+					  int doorbell_size)
+{
+	u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
+	u32 doorbell_range = RREG32_PCIE_PORT(reg);
+
+	if (use_doorbell) {
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC0_BIF_SDMA0_DOORBELL_RANGE,
+					       OFFSET, doorbell_index);
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC0_BIF_SDMA0_DOORBELL_RANGE,
+					       SIZE, doorbell_size);
+	} else {
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC0_BIF_SDMA0_DOORBELL_RANGE,
+					       SIZE, 0);
+	}
+
+	WREG32_PCIE_PORT(reg, doorbell_range);
+}
+
+static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
+					 int doorbell_index, int instance)
+{
+	u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
+	u32 doorbell_range = RREG32_PCIE_PORT(reg);
+
+	if (use_doorbell) {
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
+					       doorbell_index);
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
+	} else {
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
+	}
+
+	WREG32_PCIE_PORT(reg, doorbell_range);
+}
+
+static void nbio_v7_2_enable_doorbell_aperture(struct amdgpu_device *adev,
+					       bool enable)
+{
+	u32 reg;
+
+	reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
+	reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
+			    BIF_DOORBELL_APER_EN, enable ? 1 : 0);
+
+	WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
+}
+
+static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
+							bool enable)
+{
+	u32 tmp = 0;
+
+	if (enable) {
+		tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+				    DOORBELL_SELFRING_GPA_APER_EN, 1) |
+		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+				    DOORBELL_SELFRING_GPA_APER_MODE, 1) |
+		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+				    DOORBELL_SELFRING_GPA_APER_SIZE, 0);
+
+		WREG32_SOC15(NBIO, 0,
+			     regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
+			     lower_32_bits(adev->doorbell.base));
+		WREG32_SOC15(NBIO, 0,
+			     regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
+			     upper_32_bits(adev->doorbell.base));
+	}
+
+	WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+		     tmp);
+}
+
+
+static void nbio_v7_2_ih_doorbell_range(struct amdgpu_device *adev,
+					bool use_doorbell, int doorbell_index)
+{
+	u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE));
+
+	if (use_doorbell) {
+		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+						  GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
+						  doorbell_index);
+		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+						  GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
+						  2);
+	} else {
+		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+						  GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
+						  0);
+	}
+
+	WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE),
+			 ih_doorbell_range);
+}
+
+static void nbio_v7_2_ih_control(struct amdgpu_device *adev)
+{
+	u32 interrupt_cntl;
+
+	/* setup interrupt control */
+	WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2,
+		     adev->dummy_page_addr >> 8);
+
+	interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
+	/*
+	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
+	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
+	 */
+	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
+				       IH_DUMMY_RD_OVERRIDE, 0);
+
+	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
+	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
+				       IH_REQ_NONSNOOP_EN, 0);
+
+	WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
+}
+
+static void nbio_v7_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+						       bool enable)
+{
+	uint32_t def, data;
+
+	def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
+		data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
+			 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
+			 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
+			 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
+			 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
+			 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
+	} else {
+		data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
+			  CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
+			  CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
+			  CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
+			  CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
+			  CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
+	}
+
+	if (def != data)
+		WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data);
+}
+
+static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+						      bool enable)
+{
+	uint32_t def, data;
+
+	def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
+		data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
+			 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
+			 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+	} else {
+		data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
+			  PCIE_CNTL2__MST_MEM_LS_EN_MASK |
+			  PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+	}
+
+	if (def != data)
+		WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
+}
+
+static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,
+					    u32 *flags)
+{
+	int data;
+
+	/* AMD_CG_SUPPORT_BIF_MGCG */
+	data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL));
+	if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
+		*flags |= AMD_CG_SUPPORT_BIF_MGCG;
+
+	/* AMD_CG_SUPPORT_BIF_LS */
+	data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
+	if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
+		*flags |= AMD_CG_SUPPORT_BIF_LS;
+}
+
+static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev)
+{
+	return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
+}
+
+static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev)
+{
+	return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
+}
+
+static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev)
+{
+	return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
+}
+
+static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev)
+{
+	return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
+}
+
+static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev)
+{
+	return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
+}
+
+static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev)
+{
+	return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
+}
+
+const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
+	.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
+	.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
+	.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
+	.ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
+	.ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
+	.ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
+	.ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
+	.ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
+	.ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
+	.ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
+	.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
+	.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
+};
+
+static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
+{
+	uint32_t def, data;
+
+	def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
+	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
+	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
+
+	if (def != data)
+		WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL),
+				 data);
+}
+
+const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
+	.get_hdp_flush_req_offset = nbio_v7_2_get_hdp_flush_req_offset,
+	.get_hdp_flush_done_offset = nbio_v7_2_get_hdp_flush_done_offset,
+	.get_pcie_index_offset = nbio_v7_2_get_pcie_index_offset,
+	.get_pcie_data_offset = nbio_v7_2_get_pcie_data_offset,
+	.get_pcie_port_index_offset = nbio_v7_2_get_pcie_port_index_offset,
+	.get_pcie_port_data_offset = nbio_v7_2_get_pcie_port_data_offset,
+	.get_rev_id = nbio_v7_2_get_rev_id,
+	.mc_access_enable = nbio_v7_2_mc_access_enable,
+	.hdp_flush = nbio_v7_2_hdp_flush,
+	.get_memsize = nbio_v7_2_get_memsize,
+	.sdma_doorbell_range = nbio_v7_2_sdma_doorbell_range,
+	.vcn_doorbell_range = nbio_v7_2_vcn_doorbell_range,
+	.enable_doorbell_aperture = nbio_v7_2_enable_doorbell_aperture,
+	.enable_doorbell_selfring_aperture = nbio_v7_2_enable_doorbell_selfring_aperture,
+	.ih_doorbell_range = nbio_v7_2_ih_doorbell_range,
+	.update_medium_grain_clock_gating = nbio_v7_2_update_medium_grain_clock_gating,
+	.update_medium_grain_light_sleep = nbio_v7_2_update_medium_grain_light_sleep,
+	.get_clockgating_state = nbio_v7_2_get_clockgating_state,
+	.ih_control = nbio_v7_2_ih_control,
+	.init_registers = nbio_v7_2_init_registers,
+	.remap_hdp_registers = nbio_v7_2_remap_hdp_registers,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.h
new file mode 100644
index 000000000000..a8e8e65648a0
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __NBIO_V7_2_H__
+#define __NBIO_V7_2_H__
+
+#include "soc15_common.h"
+
+extern const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg;
+extern const struct amdgpu_nbio_funcs nbio_v7_2_funcs;
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 03462c857498..e33d8022cc32 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -49,6 +49,7 @@
 #include "gfxhub_v2_0.h"
 #include "mmhub_v2_0.h"
 #include "nbio_v2_3.h"
+#include "nbio_v7_2.h"
 #include "nv.h"
 #include "navi10_ih.h"
 #include "gfx_v10_0.h"
@@ -95,6 +96,21 @@ static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 	return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 }
 
+static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
+{
+	unsigned long flags, address, data;
+	u32 r;
+	address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
+	data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
+
+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+	WREG32(address, reg * 4);
+	(void)RREG32(address);
+	r = RREG32(data);
+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+	return r;
+}
+
 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 {
 	unsigned long address, data;
@@ -105,6 +121,21 @@ static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 	amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 }
 
+static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+	unsigned long flags, address, data;
+
+	address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
+	data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
+
+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+	WREG32(address, reg * 4);
+	(void)RREG32(address);
+	WREG32(data, v);
+	(void)RREG32(data);
+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+}
+
 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 {
 	unsigned long flags, address, data;
@@ -254,7 +285,8 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 	*value = 0;
 	for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 		en = &nv_allowed_read_registers[i];
-		if (reg_offset !=
+		if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
+		    reg_offset !=
 		    (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 			continue;
 
@@ -443,6 +475,12 @@ legacy_init:
 	case CHIP_NAVY_FLOUNDER:
 		sienna_cichlid_reg_base_init(adev);
 		break;
+	case CHIP_VANGOGH:
+		vangogh_reg_base_init(adev);
+		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		dimgrey_cavefish_reg_base_init(adev);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -455,10 +493,11 @@ void nv_set_virt_ops(struct amdgpu_device *adev)
 	adev->virt.ops = &xgpu_nv_virt_ops;
 }
 
-static bool nv_is_blockchain_sku(struct pci_dev *pdev)
+static bool nv_is_headless_sku(struct pci_dev *pdev)
 {
-	if (pdev->device == 0x731E &&
-	    (pdev->revision == 0xC6 || pdev->revision == 0xC7))
+	if ((pdev->device == 0x731E &&
+	    (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
+	    (pdev->device == 0x7340 && pdev->revision == 0xC9))
 		return true;
 	return false;
 }
@@ -467,8 +506,13 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 {
 	int r;
 
-	adev->nbio.funcs = &nbio_v2_3_funcs;
-	adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+	if (adev->flags & AMD_IS_APU) {
+		adev->nbio.funcs = &nbio_v7_2_funcs;
+		adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
+	} else {
+		adev->nbio.funcs = &nbio_v2_3_funcs;
+		adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+	}
 
 	if (adev->asic_type == CHIP_SIENNA_CICHLID)
 		adev->gmc.xgmi.supported = true;
@@ -492,7 +536,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
 		else if (amdgpu_device_has_dc_support(adev) &&
-			 !nv_is_blockchain_sku(adev->pdev))
+			 !nv_is_headless_sku(adev->pdev))
 			amdgpu_device_ip_block_add(adev, &dm_ip_block);
 #endif
 		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
@@ -500,7 +544,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 		    !amdgpu_sriov_vf(adev))
 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
-		if (!nv_is_blockchain_sku(adev->pdev))
+		if (!nv_is_headless_sku(adev->pdev))
 			amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 		amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 		if (adev->enable_mes)
@@ -575,6 +619,44 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 		    is_support_sw_smu(adev))
 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 		break;
+	case CHIP_VANGOGH:
+		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC)
+		else if (amdgpu_device_has_dc_support(adev))
+			amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
+		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
+		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
+		    is_support_sw_smu(adev))
+			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC)
+                else if (amdgpu_device_has_dc_support(adev))
+                        amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
+		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -671,6 +753,29 @@ static void nv_pre_asic_init(struct amdgpu_device *adev)
 {
 }
 
+static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
+				       bool enter)
+{
+	if (enter)
+		amdgpu_gfx_rlc_enter_safe_mode(adev);
+	else
+		amdgpu_gfx_rlc_exit_safe_mode(adev);
+
+	if (adev->gfx.funcs->update_perfmon_mgcg)
+		adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
+
+	/*
+	 * The ASPM function is not fully enabled and verified on
+	 * Navi yet. Temporarily skip this until ASPM enabled.
+	 */
+#if 0
+	if (adev->nbio.funcs->enable_aspm)
+		adev->nbio.funcs->enable_aspm(adev, !enter);
+#endif
+
+	return 0;
+}
+
 static const struct amdgpu_asic_funcs nv_asic_funcs =
 {
 	.read_disabled_bios = &nv_read_disabled_bios,
@@ -691,6 +796,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
 	.get_pcie_replay_count = &nv_get_pcie_replay_count,
 	.supports_baco = &nv_asic_supports_baco,
 	.pre_asic_init = &nv_pre_asic_init,
+	.update_umd_stable_pstate = &nv_update_umd_stable_pstate,
 };
 
 static int nv_common_early_init(void *handle)
@@ -706,6 +812,8 @@ static int nv_common_early_init(void *handle)
 	adev->pcie_wreg = &nv_pcie_wreg;
 	adev->pcie_rreg64 = &nv_pcie_rreg64;
 	adev->pcie_wreg64 = &nv_pcie_wreg64;
+	adev->pciep_rreg = &nv_pcie_port_rreg;
+	adev->pciep_wreg = &nv_pcie_port_wreg;
 
 	/* TODO: will add them during VCN v2 implementation */
 	adev->uvd_ctx_rreg = NULL;
@@ -833,6 +941,46 @@ static int nv_common_early_init(void *handle)
 		adev->external_rev_id = adev->rev_id + 0x32;
 		break;
 
+	case CHIP_VANGOGH:
+		adev->apu_flags |= AMD_APU_IS_VANGOGH;
+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+			AMD_CG_SUPPORT_GFX_MGLS |
+			AMD_CG_SUPPORT_GFX_CP_LS |
+			AMD_CG_SUPPORT_GFX_RLC_LS |
+			AMD_CG_SUPPORT_GFX_CGCG |
+			AMD_CG_SUPPORT_GFX_CGLS |
+			AMD_CG_SUPPORT_GFX_3D_CGCG |
+			AMD_CG_SUPPORT_GFX_3D_CGLS |
+			AMD_CG_SUPPORT_MC_MGCG |
+			AMD_CG_SUPPORT_MC_LS |
+			AMD_CG_SUPPORT_GFX_FGCG |
+			AMD_CG_SUPPORT_VCN_MGCG |
+			AMD_CG_SUPPORT_JPEG_MGCG;
+		adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
+			AMD_PG_SUPPORT_VCN |
+			AMD_PG_SUPPORT_VCN_DPG |
+			AMD_PG_SUPPORT_JPEG;
+		if (adev->apu_flags & AMD_APU_IS_VANGOGH)
+			adev->external_rev_id = adev->rev_id + 0x01;
+		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+			AMD_CG_SUPPORT_GFX_CGCG |
+			AMD_CG_SUPPORT_GFX_3D_CGCG |
+			AMD_CG_SUPPORT_VCN_MGCG |
+			AMD_CG_SUPPORT_JPEG_MGCG |
+			AMD_CG_SUPPORT_MC_MGCG |
+			AMD_CG_SUPPORT_MC_LS |
+			AMD_CG_SUPPORT_HDP_MGCG |
+			AMD_CG_SUPPORT_HDP_LS |
+			AMD_CG_SUPPORT_IH_CG;
+		adev->pg_flags = AMD_PG_SUPPORT_VCN |
+			AMD_PG_SUPPORT_VCN_DPG |
+			AMD_PG_SUPPORT_JPEG |
+			AMD_PG_SUPPORT_ATHUB |
+			AMD_PG_SUPPORT_MMHUB;
+		adev->external_rev_id = adev->rev_id + 0x3c;
+		break;
 	default:
 		/* FIXME: not supported yet */
 		return -EINVAL;
@@ -1060,6 +1208,7 @@ static int nv_common_set_clockgating_state(void *handle,
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		adev->nbio.funcs->update_medium_grain_clock_gating(adev,
 				state == AMD_CG_STATE_GATE);
 		adev->nbio.funcs->update_medium_grain_light_sleep(adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
index aeef50a6a54b..515d67bf249f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/nv.h
@@ -34,4 +34,6 @@ int navi10_reg_base_init(struct amdgpu_device *adev);
 int navi14_reg_base_init(struct amdgpu_device *adev);
 int navi12_reg_base_init(struct amdgpu_device *adev);
 int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
+void vangogh_reg_base_init(struct amdgpu_device *adev);
+int dimgrey_cavefish_reg_base_init(struct amdgpu_device *adev);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index 4137dc710aaf..d65a5339d354 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -86,21 +86,22 @@ struct psp_gfx_ctrl
 /* TEE Gfx Command IDs for the ring buffer interface. */
 enum psp_gfx_cmd_id
 {
-    GFX_CMD_ID_LOAD_TA      = 0x00000001,   /* load TA */
-    GFX_CMD_ID_UNLOAD_TA    = 0x00000002,   /* unload TA */
-    GFX_CMD_ID_INVOKE_CMD   = 0x00000003,   /* send command to TA */
-    GFX_CMD_ID_LOAD_ASD     = 0x00000004,   /* load ASD Driver */
-    GFX_CMD_ID_SETUP_TMR    = 0x00000005,   /* setup TMR region */
-    GFX_CMD_ID_LOAD_IP_FW   = 0x00000006,   /* load HW IP FW */
-    GFX_CMD_ID_DESTROY_TMR  = 0x00000007,   /* destroy TMR region */
-    GFX_CMD_ID_SAVE_RESTORE = 0x00000008,   /* save/restore HW IP FW */
-    GFX_CMD_ID_SETUP_VMR    = 0x00000009,   /* setup VMR region */
-    GFX_CMD_ID_DESTROY_VMR  = 0x0000000A,   /* destroy VMR region */
-    GFX_CMD_ID_PROG_REG     = 0x0000000B,   /* program regs */
-    GFX_CMD_ID_CLEAR_VF_FW  = 0x0000000D,   /* Clear VF FW, to be used on VF shutdown. */
+    GFX_CMD_ID_LOAD_TA            = 0x00000001,   /* load TA */
+    GFX_CMD_ID_UNLOAD_TA          = 0x00000002,   /* unload TA */
+    GFX_CMD_ID_INVOKE_CMD         = 0x00000003,   /* send command to TA */
+    GFX_CMD_ID_LOAD_ASD           = 0x00000004,   /* load ASD Driver */
+    GFX_CMD_ID_SETUP_TMR          = 0x00000005,   /* setup TMR region */
+    GFX_CMD_ID_LOAD_IP_FW         = 0x00000006,   /* load HW IP FW */
+    GFX_CMD_ID_DESTROY_TMR        = 0x00000007,   /* destroy TMR region */
+    GFX_CMD_ID_SAVE_RESTORE       = 0x00000008,   /* save/restore HW IP FW */
+    GFX_CMD_ID_SETUP_VMR          = 0x00000009,   /* setup VMR region */
+    GFX_CMD_ID_DESTROY_VMR        = 0x0000000A,   /* destroy VMR region */
+    GFX_CMD_ID_PROG_REG           = 0x0000000B,   /* program regs */
+    GFX_CMD_ID_CLEAR_VF_FW        = 0x0000000D,   /* Clear VF FW, to be used on VF shutdown. */
+    GFX_CMD_ID_GET_FW_ATTESTATION = 0x0000000F,   /* Query GPUVA of the Fw Attestation DB */
     /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */
-    GFX_CMD_ID_LOAD_TOC     = 0x00000020,   /* Load TOC and obtain TMR size */
-    GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021,   /* Indicates all graphics fw loaded, start RLC autoload */
+    GFX_CMD_ID_LOAD_TOC           = 0x00000020,   /* Load TOC and obtain TMR size */
+    GFX_CMD_ID_AUTOLOAD_RLC       = 0x00000021,   /* Indicates all graphics fw loaded, start RLC autoload */
 };
 
 /* Command to load Trusted Application binary into PSP OS. */
@@ -285,6 +286,25 @@ union psp_gfx_commands
     struct psp_gfx_cmd_load_toc         cmd_load_toc;
 };
 
+struct psp_gfx_uresp_reserved
+{
+    uint32_t reserved[8];
+};
+
+/* Command-specific response for Fw Attestation Db */
+struct psp_gfx_uresp_fwar_db_info
+{
+    uint32_t fwar_db_addr_lo;
+    uint32_t fwar_db_addr_hi;
+};
+
+/* Union of command-specific responses for GPCOM ring. */
+union psp_gfx_uresp
+{
+    struct psp_gfx_uresp_reserved reserved;
+    struct psp_gfx_uresp_fwar_db_info fwar_db_info;
+};
+
 /* Structure of GFX Response buffer.
 * For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
 * it is separate buffer.
@@ -297,9 +317,11 @@ struct psp_gfx_resp
     uint32_t	fw_addr_hi;	/* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
     uint32_t	tmr_size;	/* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */
 
-    uint32_t	reserved[3];
+    uint32_t	reserved[11];
+
+    union psp_gfx_uresp uresp;      /* +64 response union containing command-specific responses */
 
-    /* total 32 bytes */
+    /* total 96 bytes */
 };
 
 /* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 6c5d9612abcb..03e88dbf92be 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -59,6 +59,10 @@ MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
+MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
+MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
+MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_asd.bin");
 
 /* address block */
 #define smnMP1_FIRMWARE_FLAGS		0x3010024
@@ -77,7 +81,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
 {
 	struct amdgpu_device *adev = psp->adev;
 	const char *chip_name;
-	char fw_name[30];
+	char fw_name[PSP_FW_NAME_LEN];
 	int err = 0;
 	const struct ta_firmware_header_v1_0 *ta_hdr;
 
@@ -105,24 +109,26 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
 	case CHIP_NAVY_FLOUNDER:
 		chip_name = "navy_flounder";
 		break;
+	case CHIP_VANGOGH:
+		chip_name = "vangogh";
+		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		chip_name = "dimgrey_cavefish";
+		break;
 	default:
 		BUG();
 	}
 
-	err = psp_init_sos_microcode(psp, chip_name);
-	if (err)
-		return err;
-
-	if (adev->asic_type != CHIP_SIENNA_CICHLID &&
-	    adev->asic_type != CHIP_NAVY_FLOUNDER) {
-		err = psp_init_asd_microcode(psp, chip_name);
-		if (err)
-			return err;
-	}
 
 	switch (adev->asic_type) {
 	case CHIP_VEGA20:
 	case CHIP_ARCTURUS:
+		err = psp_init_sos_microcode(psp, chip_name);
+		if (err)
+			return err;
+		err = psp_init_asd_microcode(psp, chip_name);
+		if (err)
+			return err;
 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
 		err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
 		if (err) {
@@ -150,6 +156,12 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
 	case CHIP_NAVI10:
 	case CHIP_NAVI14:
 	case CHIP_NAVI12:
+		err = psp_init_sos_microcode(psp, chip_name);
+		if (err)
+			return err;
+		err = psp_init_asd_microcode(psp, chip_name);
+		if (err)
+			return err;
 		if (amdgpu_sriov_vf(adev))
 			break;
 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
@@ -180,10 +192,26 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
 		break;
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+		err = psp_init_sos_microcode(psp, chip_name);
+		if (err)
+			return err;
 		err = psp_init_ta_microcode(&adev->psp, chip_name);
 		if (err)
 			return err;
 		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		err = psp_init_sos_microcode(psp, chip_name);
+		if (err)
+			return err;
+		break;
+	case CHIP_VANGOGH:
+		err = psp_init_asd_microcode(psp, chip_name);
+		if (err)
+			return err;
+		err = psp_init_toc_microcode(psp, chip_name);
+		if (err)
+			return err;
+		break;
 	default:
 		BUG();
 	}
@@ -407,8 +435,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
 	struct amdgpu_device *adev = psp->adev;
 
 	if ((!amdgpu_sriov_vf(adev)) &&
-	    (adev->asic_type != CHIP_SIENNA_CICHLID) &&
-	    (adev->asic_type != CHIP_NAVY_FLOUNDER))
+	    !(adev->asic_type >= CHIP_SIENNA_CICHLID &&
+	    adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
 		psp_v11_0_reroute_ih(psp);
 
 	ring = &psp->km_ring;
@@ -615,7 +643,7 @@ static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
 {
 	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
-	uint32_t *pcache = (uint32_t*)ctx->sys_cache;
+	uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 	struct amdgpu_device *adev = psp->adev;
 	uint32_t p2c_header[4];
 	uint32_t sz;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
index 75489313dbad..dff5c15b4858 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
@@ -39,6 +39,7 @@
 
 MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
 MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
+MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
 
 /* address block */
 #define smnMP1_FIRMWARE_FLAGS		0x3010024
@@ -54,7 +55,10 @@ static int psp_v12_0_init_microcode(struct psp_context *psp)
 
 	switch (adev->asic_type) {
 	case CHIP_RENOIR:
-		chip_name = "renoir";
+		if (adev->apu_flags & AMD_APU_IS_RENOIR)
+			chip_name = "renoir";
+		else
+			chip_name = "green_sardine";
 		break;
 	default:
 		BUG();
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 86fb1eddf5a6..dc74ca2aa892 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -69,6 +69,7 @@ MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
+MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin");
 
 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
@@ -568,7 +569,7 @@ static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
 			break;
 	}
 
-	memset((void*)adev->sdma.instance, 0,
+	memset((void *)adev->sdma.instance, 0,
 		sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 }
 
@@ -619,7 +620,10 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 		chip_name = "arcturus";
 		break;
 	case CHIP_RENOIR:
-		chip_name = "renoir";
+		if (adev->apu_flags & AMD_APU_IS_RENOIR)
+			chip_name = "renoir";
+		else
+			chip_name = "green_sardine";
 		break;
 	default:
 		BUG();
@@ -639,8 +643,8 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 		if (adev->asic_type == CHIP_ARCTURUS) {
 			/* Acturus will leverage the same FW memory
 			   for every SDMA instance */
-			memcpy((void*)&adev->sdma.instance[i],
-			       (void*)&adev->sdma.instance[0],
+			memcpy((void *)&adev->sdma.instance[i],
+			       (void *)&adev->sdma.instance[0],
 			       sizeof(struct amdgpu_sdma_instance));
 		}
 		else {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 9f3952723c63..cb5a6f1437f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -46,6 +46,9 @@
 
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
+MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
+
+MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
 
 #define SDMA1_REG_OFFSET 0x600
 #define SDMA3_REG_OFFSET 0x400
@@ -87,6 +90,8 @@ static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		break;
 	default:
 		break;
@@ -124,7 +129,7 @@ static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 			break;
 	}
 
-	memset((void*)adev->sdma.instance, 0,
+	memset((void *)adev->sdma.instance, 0,
 	       sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 }
 
@@ -160,6 +165,12 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 	case CHIP_NAVY_FLOUNDER:
 		chip_name = "navy_flounder";
 		break;
+	case CHIP_VANGOGH:
+		chip_name = "vangogh";
+		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		chip_name = "dimgrey_cavefish";
+		break;
 	default:
 		BUG();
 	}
@@ -175,10 +186,10 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 		goto out;
 
 	for (i = 1; i < adev->sdma.num_instances; i++) {
-		if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-		    adev->asic_type == CHIP_NAVY_FLOUNDER) {
-			memcpy((void*)&adev->sdma.instance[i],
-			       (void*)&adev->sdma.instance[0],
+		if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
+		    adev->asic_type <= CHIP_DIMGREY_CAVEFISH) {
+			memcpy((void *)&adev->sdma.instance[i],
+			       (void *)&adev->sdma.instance[0],
 			       sizeof(struct amdgpu_sdma_instance));
 		} else {
 			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
@@ -696,7 +707,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 		temp &= 0xFF0FFF;
 		temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 			 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
-			 0x01000000);
+			 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 
 		if (!amdgpu_sriov_vf(adev)) {
@@ -1169,8 +1180,12 @@ static int sdma_v5_2_early_init(void *handle)
 		adev->sdma.num_instances = 4;
 		break;
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		adev->sdma.num_instances = 2;
 		break;
+	case CHIP_VANGOGH:
+		adev->sdma.num_instances = 1;
+		break;
 	default:
 		break;
 	}
@@ -1567,6 +1582,8 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		sdma_v5_2_update_medium_grain_clock_gating(adev,
 				state == AMD_CG_STATE_GATE ? true : false);
 		sdma_v5_2_update_medium_grain_light_sleep(adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index e5e336fd9e94..3cf0589bfea5 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1350,7 +1350,7 @@ static void si_vga_set_state(struct amdgpu_device *adev, bool state)
 
 static u32 si_get_xclk(struct amdgpu_device *adev)
 {
-        u32 reference_clock = adev->clock.spll.reference_freq;
+	u32 reference_clock = adev->clock.spll.reference_freq;
 	u32 tmp;
 
 	tmp = RREG32(CG_CLKPIN_CNTL_2);
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 621727d7fd18..51880f6ef634 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -43,7 +43,7 @@ static void si_ih_enable_interrupts(struct amdgpu_device *adev)
 	WREG32(IH_RB_CNTL, ih_rb_cntl);
 	adev->irq.ih.enabled = true;
 }
-  
+
 static void si_ih_disable_interrupts(struct amdgpu_device *adev)
 {
 	u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index afcccc6c0fc6..5b79ce9e0699 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -62,6 +62,7 @@
 #include "nbio_v7_0.h"
 #include "nbio_v7_4.h"
 #include "vega10_ih.h"
+#include "navi10_ih.h"
 #include "sdma_v4_0.h"
 #include "uvd_v7_0.h"
 #include "vce_v4_0.h"
@@ -734,9 +735,15 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 				else
 					amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 			}
-			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+			if (adev->asic_type == CHIP_VEGA20)
+				amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+			else
+				amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 		} else {
-			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+			if (adev->asic_type == CHIP_VEGA20)
+				amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+			else
+				amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
 				if (adev->asic_type == CHIP_VEGA20)
 					amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
@@ -787,9 +794,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 		if (amdgpu_sriov_vf(adev)) {
 			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
-			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 		} else {
-			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 		}
@@ -822,7 +829,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
                 else if (amdgpu_device_has_dc_support(adev))
-                        amdgpu_device_ip_block_add(adev, &dm_ip_block);
+			amdgpu_device_ip_block_add(adev, &dm_ip_block);
 #endif
 		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 		amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
@@ -1195,8 +1202,7 @@ static int soc15_common_early_init(void *handle)
 
 			adev->pg_flags = AMD_PG_SUPPORT_SDMA |
 				AMD_PG_SUPPORT_MMHUB |
-				AMD_PG_SUPPORT_VCN |
-				AMD_PG_SUPPORT_VCN_DPG;
+				AMD_PG_SUPPORT_VCN;
 		} else {
 			adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 				AMD_CG_SUPPORT_GFX_MGLS |
@@ -1243,7 +1249,15 @@ static int soc15_common_early_init(void *handle)
 		break;
 	case CHIP_RENOIR:
 		adev->asic_funcs = &soc15_asic_funcs;
-		adev->apu_flags |= AMD_APU_IS_RENOIR;
+		if (adev->pdev->device == 0x1636)
+			adev->apu_flags |= AMD_APU_IS_RENOIR;
+		else
+			adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
+
+		if (adev->apu_flags & AMD_APU_IS_RENOIR)
+			adev->external_rev_id = adev->rev_id + 0x91;
+		else
+			adev->external_rev_id = adev->rev_id + 0xa1;
 		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 				 AMD_CG_SUPPORT_GFX_MGLS |
 				 AMD_CG_SUPPORT_GFX_3D_CGCG |
@@ -1268,7 +1282,6 @@ static int soc15_common_early_init(void *handle)
 				 AMD_PG_SUPPORT_VCN |
 				 AMD_PG_SUPPORT_JPEG |
 				 AMD_PG_SUPPORT_VCN_DPG;
-		adev->external_rev_id = adev->rev_id + 0x91;
 		break;
 	default:
 		/* FIXME: not supported yet */
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
index 5288617ca552..96d7769609f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
@@ -253,7 +253,7 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev
 static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
 					   void *ras_error_status)
 {
-	struct ras_err_data* err_data = (struct ras_err_data*)ras_error_status;
+	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 
 	uint32_t umc_inst        = 0;
 	uint32_t ch_inst         = 0;
@@ -368,7 +368,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
 static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
 					     void *ras_error_status)
 {
-	struct ras_err_data* err_data = (struct ras_err_data*)ras_error_status;
+	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 
 	uint32_t umc_inst        = 0;
 	uint32_t ch_inst         = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
index 5665c77a9d58..a064c097690c 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
@@ -170,7 +170,7 @@ static void umc_v8_7_querry_uncorrectable_error_count(struct amdgpu_device *adev
 static void umc_v8_7_query_ras_error_count(struct amdgpu_device *adev,
 					   void *ras_error_status)
 {
-	struct ras_err_data* err_data = (struct ras_err_data*)ras_error_status;
+	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 
 	uint32_t umc_inst        = 0;
 	uint32_t ch_inst         = 0;
@@ -260,7 +260,7 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev,
 static void umc_v8_7_query_ras_error_address(struct amdgpu_device *adev,
 					     void *ras_error_status)
 {
-	struct ras_err_data* err_data = (struct ras_err_data*)ras_error_status;
+	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 
 	uint32_t umc_inst        = 0;
 	uint32_t ch_inst         = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
new file mode 100644
index 000000000000..d64d681a05dc
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vangogh_reg_init.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "vangogh_ip_offset.h"
+
+void vangogh_reg_base_init(struct amdgpu_device *adev)
+{
+	/* HW has more IP blocks,  only initialized the blocke needed by driver */
+	uint32_t i;
+	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+		adev->reg_offset[GC_HWIP][i]     = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[HDP_HWIP][i]    = (uint32_t *)(&(HDP_BASE.instance[i]));
+		adev->reg_offset[MMHUB_HWIP][i]  = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+		adev->reg_offset[ATHUB_HWIP][i]  = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+		adev->reg_offset[NBIO_HWIP][i]   = (uint32_t *)(&(NBIO_BASE.instance[i]));
+		adev->reg_offset[MP0_HWIP][i]    = (uint32_t *)(&(MP0_BASE.instance[i]));
+		adev->reg_offset[MP1_HWIP][i]    = (uint32_t *)(&(MP1_BASE.instance[i]));
+		adev->reg_offset[VCN_HWIP][i]    = (uint32_t *)(&(VCN_BASE.instance[i]));
+		adev->reg_offset[DF_HWIP][i]     = (uint32_t *)(&(DF_BASE.instance[i]));
+		adev->reg_offset[DCE_HWIP][i]    = (uint32_t *)(&(DCN_BASE.instance[i]));
+		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+		adev->reg_offset[SDMA0_HWIP][i]  = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[SMUIO_HWIP][i]  = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+		adev->reg_offset[THM_HWIP][i]    = (uint32_t *)(&(THM_BASE.instance[i]));
+	}
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index e5d29dee0c88..e285f9c9d460 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -45,7 +45,7 @@
 #define mmUVD_SCRATCH9_INTERNAL_OFFSET				0xc01d
 
 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET			0x1e1
-#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x5a6
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x5a6
 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET		0x5a7
 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x1e2
 
@@ -800,7 +800,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
 	WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
 
 	if (indirect)
-		adev->vcn.inst->dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst->dpg_sram_cpu_addr;
+		adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr;
 
 	/* enable clock gating */
 	vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 0f1d3ef8baa7..b6e0f4ba6272 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -45,7 +45,7 @@
 
 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET			0x431
 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET		0x3b4
-#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x3b5
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x3b5
 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x25c
 
 #define VCN25_MAX_HW_INSTANCES_ARCTURUS			2
@@ -777,7 +777,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
 	WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
 
 	if (indirect)
-		adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
+		adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 
 	/* enable clock gating */
 	vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index e074f7ed388c..269002816109 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -44,10 +44,10 @@
 
 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET			0x431
 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET		0x3b4
-#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x3b5
+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x3b5
 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x25c
 
-#define VCN_INSTANCES_SIENNA_CICHLID	 				2
+#define VCN_INSTANCES_SIENNA_CICHLID				2
 
 static int amdgpu_ih_clientid_vcns[] = {
 	SOC15_IH_CLIENTID_VCN,
@@ -55,8 +55,8 @@ static int amdgpu_ih_clientid_vcns[] = {
 };
 
 static int amdgpu_ucode_id_vcns[] = {
-       AMDGPU_UCODE_ID_VCN,
-       AMDGPU_UCODE_ID_VCN1
+	AMDGPU_UCODE_ID_VCN,
+	AMDGPU_UCODE_ID_VCN1
 };
 
 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
@@ -915,7 +915,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
 	WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
 
 	if (indirect)
-		adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
+		adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 
 	/* enable clock gating */
 	vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
@@ -1371,7 +1371,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
 	}
 
 	/* Update init table header in memory */
-        size = sizeof(struct mmsch_v3_0_init_header);
+	size = sizeof(struct mmsch_v3_0_init_header);
 	table_loc = (uint32_t *)table->cpu_addr;
 	memcpy((void *)table_loc, &header, size);
 
diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
index dcb1d89d776e..fe14e473f026 100644
--- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
+++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
@@ -66,12 +66,12 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev,
 	vmid  = (ihre->ring_id & 0x0000ff00) >> 8;
 	if (vmid < dev->vm_info.first_vmid_kfd ||
 	    vmid > dev->vm_info.last_vmid_kfd)
-		return 0;
+		return false;
 
 	/* If there is no valid PASID, it's likely a firmware bug */
 	pasid = (ihre->ring_id & 0xffff0000) >> 16;
 	if (WARN_ONCE(pasid == 0, "FW bug: No PASID in KFD interrupt"))
-		return 0;
+		return false;
 
 	/* Interrupt types we care about: various signals and faults.
 	 * They will be forwarded to a work queue (see below).
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 5e2254b9e931..a0acf2310357 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -141,6 +141,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = {
 #define renoir_cache_info carrizo_cache_info
 /* TODO - check & update Navi10 cache details */
 #define navi10_cache_info carrizo_cache_info
+#define vangogh_cache_info carrizo_cache_info
 
 static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
 		struct crat_subtype_computeunit *cu)
@@ -680,9 +681,14 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
 	case CHIP_NAVI14:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		pcache_info = navi10_cache_info;
 		num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
 		break;
+	case CHIP_VANGOGH:
+		pcache_info = vangogh_cache_info;
+		num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -798,10 +804,10 @@ int kfd_create_crat_image_acpi(void **crat_image, size_t *size)
 	}
 
 	pcrat_image = kvmalloc(crat_table->length, GFP_KERNEL);
-	memcpy(pcrat_image, crat_table, crat_table->length);
 	if (!pcrat_image)
 		return -ENOMEM;
 
+	memcpy(pcrat_image, crat_table, crat_table->length);
 	*crat_image = pcrat_image;
 	*size = crat_table->length;
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 903170e59342..50922ff2927b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -76,6 +76,8 @@ static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
 	[CHIP_NAVI14] = &gfx_v10_kfd2kgd,
 	[CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
 	[CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
+	[CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd,
+	[CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd,
 };
 
 #ifdef KFD_SUPPORT_IOMMU_V2
@@ -498,6 +500,43 @@ static const struct kfd_device_info navy_flounder_device_info = {
 	.num_sdma_queues_per_engine = 8,
 };
 
+static const struct kfd_device_info vangogh_device_info = {
+	.asic_family = CHIP_VANGOGH,
+	.asic_name = "vangogh",
+	.max_pasid_bits = 16,
+	.max_no_of_hqd  = 24,
+	.doorbell_size  = 8,
+	.ih_ring_entry_size = 8 * sizeof(uint32_t),
+	.event_interrupt_class = &event_interrupt_class_v9,
+	.num_of_watch_points = 4,
+	.mqd_size_aligned = MQD_SIZE_ALIGNED,
+	.needs_iommu_device = false,
+	.supports_cwsr = true,
+	.needs_pci_atomics = false,
+	.num_sdma_engines = 1,
+	.num_xgmi_sdma_engines = 0,
+	.num_sdma_queues_per_engine = 2,
+};
+
+static const struct kfd_device_info dimgrey_cavefish_device_info = {
+	.asic_family = CHIP_DIMGREY_CAVEFISH,
+	.asic_name = "dimgrey_cavefish",
+	.max_pasid_bits = 16,
+	.max_no_of_hqd  = 24,
+	.doorbell_size  = 8,
+	.ih_ring_entry_size = 8 * sizeof(uint32_t),
+	.event_interrupt_class = &event_interrupt_class_v9,
+	.num_of_watch_points = 4,
+	.mqd_size_aligned = MQD_SIZE_ALIGNED,
+	.needs_iommu_device = false,
+	.supports_cwsr = true,
+	.needs_pci_atomics = false,
+	.num_sdma_engines = 2,
+	.num_xgmi_sdma_engines = 0,
+	.num_sdma_queues_per_engine = 8,
+};
+
+
 /* For each entry, [0] is regular and [1] is virtualisation device. */
 static const struct kfd_device_info *kfd_supported_devices[][2] = {
 #ifdef KFD_SUPPORT_IOMMU_V2
@@ -522,6 +561,8 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = {
 	[CHIP_NAVI14] = {&navi14_device_info, NULL},
 	[CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info},
 	[CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
+	[CHIP_VANGOGH] = {&vangogh_device_info, NULL},
+	[CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info},
 };
 
 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
@@ -716,8 +757,6 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 
 	kfd->hive_id = amdgpu_amdkfd_get_hive_id(kfd->kgd);
 
-	kfd->unique_id = amdgpu_amdkfd_get_unique_id(kfd->kgd);
-
 	kfd->noretry = amdgpu_amdkfd_get_noretry(kfd->kgd);
 
 	if (kfd_interrupt_init(kfd)) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index c0ae04a08625..f0a6f6665c81 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1925,6 +1925,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
 	case CHIP_NAVI14:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		device_queue_manager_init_v10_navi10(&dqm->asic_ops);
 		break;
 	default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 3c22909470f2..98a5e1d719c8 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -417,6 +417,8 @@ int kfd_init_apertures(struct kfd_process *process)
 			case CHIP_NAVI14:
 			case CHIP_SIENNA_CICHLID:
 			case CHIP_NAVY_FLOUNDER:
+			case CHIP_VANGOGH:
+			case CHIP_DIMGREY_CAVEFISH:
 				kfd_init_apertures_v9(pdd, id);
 				break;
 			default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 47ee40fbbd86..5d541e0cc8ca 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -247,6 +247,8 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
 	case CHIP_NAVI14:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		pm->pmf = &kfd_v9_pm_funcs;
 		break;
 	default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index c77cf23032ac..09599efa41fc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -292,9 +292,6 @@ struct kfd_dev {
 	/* xGMI */
 	uint64_t hive_id;
 
-	/* UUID */
-	uint64_t unique_id;
-
 	bool pci_atomic_requested;
 
 	/* Use IOMMU v2 flag */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 2b31c3066aaa..a3fc23873819 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1340,7 +1340,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 		dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ?
 		amdgpu_amdkfd_get_num_gws(dev->gpu->kgd) : 0;
 	dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm);
-	dev->node_props.unique_id = gpu->unique_id;
+	dev->node_props.unique_id = amdgpu_amdkfd_get_unique_id(dev->gpu->kgd);
 
 	kfd_fill_mem_clk_max_info(dev);
 	kfd_fill_iolink_non_crat_info(dev);
@@ -1375,6 +1375,8 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 	case CHIP_NAVI14:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_VANGOGH:
+	case CHIP_DIMGREY_CAVEFISH:
 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index 60dfdd432aba..797b5d4b43e5 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -15,15 +15,7 @@ config DRM_AMD_DC
 config DRM_AMD_DC_DCN
 	def_bool n
 	help
-	  Raven, Navi and Renoir family support for display engine
-
-config DRM_AMD_DC_DCN3_0
-        bool "DCN 3.0 family"
-        depends on DRM_AMD_DC && X86
-        depends on DRM_AMD_DC_DCN
-        help
-            Choose this option if you want to have
-            sienna_cichlid support for display engine
+	  Raven, Navi, and newer family support for display engine
 
 config DRM_AMD_DC_HDCP
 	bool "Enable HDCP support in DC"
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 86fd4420f128..2855bb918535 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -34,6 +34,7 @@
 #include "dc/inc/hw/dmcu.h"
 #include "dc/inc/hw/abm.h"
 #include "dc/dc_dmub_srv.h"
+#include "amdgpu_dm_trace.h"
 
 #include "vid.h"
 #include "amdgpu.h"
@@ -94,12 +95,16 @@
 
 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
-#endif
+#define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
+#define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
+#define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 
 #define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -209,6 +214,9 @@ static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
 static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
 
+static const struct drm_format_info *
+amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
+
 /*
  * dm_vblank_get_counter
  *
@@ -583,7 +591,7 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 {
 	struct drm_device *dev = connector->dev;
 	struct amdgpu_device *adev = drm_to_adev(dev);
-	struct dm_comressor_info *compressor = &adev->dm.compressor;
+	struct dm_compressor_info *compressor = &adev->dm.compressor;
 	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 	struct drm_display_mode *mode;
 	unsigned long max_size = 0;
@@ -880,44 +888,60 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
 	return 0;
 }
 
-static void amdgpu_check_debugfs_connector_property_change(struct amdgpu_device *adev,
-							   struct drm_atomic_state *state)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
 {
-	struct drm_connector *connector;
-	struct drm_crtc *crtc;
-	struct amdgpu_dm_connector *amdgpu_dm_connector;
-	struct drm_connector_state *conn_state;
-	struct dm_crtc_state *acrtc_state;
-	struct drm_crtc_state *crtc_state;
-	struct dc_stream_state *stream;
-	struct drm_device *dev = adev_to_drm(adev);
+	uint64_t pt_base;
+	uint32_t logical_addr_low;
+	uint32_t logical_addr_high;
+	uint32_t agp_base, agp_bot, agp_top;
+	PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
 
-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+	logical_addr_low  = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
+	pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 
-		amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
-		conn_state = connector->state;
+	if (adev->apu_flags & AMD_APU_IS_RAVEN2)
+		/*
+		 * Raven2 has a HW issue that it is unable to use the vram which
+		 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
+		 * workaround that increase system aperture high address (add 1)
+		 * to get rid of the VM fault and hardware hang.
+		 */
+		logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
+	else
+		logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
 
-		if (!(conn_state && conn_state->crtc))
-			continue;
+	agp_base = 0;
+	agp_bot = adev->gmc.agp_start >> 24;
+	agp_top = adev->gmc.agp_end >> 24;
 
-		crtc = conn_state->crtc;
-		acrtc_state = to_dm_crtc_state(crtc->state);
 
-		if (!(acrtc_state && acrtc_state->stream))
-			continue;
+	page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
+	page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
+	page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
+	page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
+	page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
+	page_table_base.low_part = lower_32_bits(pt_base);
 
-		stream = acrtc_state->stream;
+	pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
+	pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
+
+	pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
+	pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
+	pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
+
+	pa_config->system_aperture.fb_base = adev->gmc.fb_start;
+	pa_config->system_aperture.fb_offset = adev->gmc.aper_base;
+	pa_config->system_aperture.fb_top = adev->gmc.fb_end;
+
+	pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
+	pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
+	pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
+
+	pa_config->is_hvm_enabled = 0;
 
-		if (amdgpu_dm_connector->dsc_settings.dsc_force_enable ||
-		    amdgpu_dm_connector->dsc_settings.dsc_num_slices_v ||
-		    amdgpu_dm_connector->dsc_settings.dsc_num_slices_h ||
-		    amdgpu_dm_connector->dsc_settings.dsc_bits_per_pixel) {
-			conn_state = drm_atomic_get_connector_state(state, connector);
-			crtc_state = drm_atomic_get_crtc_state(state, crtc);
-			crtc_state->mode_changed = true;
-		}
-	}
 }
+#endif
 
 static int amdgpu_dm_init(struct amdgpu_device *adev)
 {
@@ -973,6 +997,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 	case CHIP_RAVEN:
 	case CHIP_RENOIR:
 		init_data.flags.gpu_vm_support = true;
+		if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
+			init_data.flags.disable_dmcu = true;
 		break;
 	default:
 		break;
@@ -1026,6 +1052,17 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 
 	dc_hardware_init(adev->dm.dc);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	if (adev->asic_type == CHIP_RENOIR) {
+		struct dc_phy_addr_space_config pa_config;
+
+		mmhub_read_system_context(adev, &pa_config);
+
+		// Call the DC init_memory func
+		dc_setup_system_context(adev->dm.dc, &pa_config);
+	}
+#endif
+
 	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 	if (!adev->dm.freesync_module) {
 		DRM_ERROR(
@@ -1072,6 +1109,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 		goto error;
 	}
 
+
 	DRM_DEBUG_DRIVER("KMS initialized.\n");
 
 	return 0;
@@ -1168,10 +1206,10 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
 	case CHIP_NAVI10:
 	case CHIP_NAVI14:
 	case CHIP_RENOIR:
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
-#endif
+	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_VANGOGH:
 		return 0;
 	case CHIP_NAVI12:
 		fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@@ -1267,8 +1305,9 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
 	case CHIP_RENOIR:
 		dmub_asic = DMUB_ASIC_DCN21;
 		fw_name_dmub = FIRMWARE_RENOIR_DMUB;
+		if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
+			fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
 		break;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case CHIP_SIENNA_CICHLID:
 		dmub_asic = DMUB_ASIC_DCN30;
 		fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
@@ -1277,7 +1316,14 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
 		dmub_asic = DMUB_ASIC_DCN30;
 		fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
 		break;
-#endif
+	case CHIP_VANGOGH:
+		dmub_asic = DMUB_ASIC_DCN301;
+		fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
+		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		dmub_asic = DMUB_ASIC_DCN302;
+		fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
+		break;
 
 	default:
 		/* ASIC doesn't support DMUB. */
@@ -2095,6 +2141,7 @@ const struct amdgpu_ip_block_version dm_ip_block =
 
 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
 	.fb_create = amdgpu_display_user_framebuffer_create,
+	.get_format_info = amd_get_format_info,
 	.output_poll_changed = drm_fb_helper_output_poll_changed,
 	.atomic_check = amdgpu_dm_atomic_check,
 	.atomic_commit = amdgpu_dm_atomic_commit,
@@ -3396,10 +3443,10 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 	case CHIP_NAVI10:
 	case CHIP_NAVI14:
 	case CHIP_RENOIR:
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
-#endif
+	case CHIP_DIMGREY_CAVEFISH:
+	case CHIP_VANGOGH:
 		if (dcn10_register_irq_handlers(dm->adev)) {
 			DRM_ERROR("DM: Failed to initialize IRQ\n");
 			goto fail;
@@ -3558,31 +3605,27 @@ static int dm_early_init(void *handle)
 		break;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	case CHIP_RAVEN:
+	case CHIP_RENOIR:
+	case CHIP_VANGOGH:
 		adev->mode_info.num_crtc = 4;
 		adev->mode_info.num_hpd = 4;
 		adev->mode_info.num_dig = 4;
 		break;
-#endif
 	case CHIP_NAVI10:
 	case CHIP_NAVI12:
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
-#endif
 		adev->mode_info.num_crtc = 6;
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 6;
 		break;
 	case CHIP_NAVI14:
+	case CHIP_DIMGREY_CAVEFISH:
 		adev->mode_info.num_crtc = 5;
 		adev->mode_info.num_hpd = 5;
 		adev->mode_info.num_dig = 5;
 		break;
-	case CHIP_RENOIR:
-		adev->mode_info.num_crtc = 4;
-		adev->mode_info.num_hpd = 4;
-		adev->mode_info.num_dig = 4;
-		break;
+#endif
 	default:
 		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
 		return -EINVAL;
@@ -3686,78 +3729,84 @@ static int fill_dc_scaling_info(const struct drm_plane_state *state,
 	return 0;
 }
 
-static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
-		       uint64_t *tiling_flags, bool *tmz_surface)
+static void
+fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
+				 uint64_t tiling_flags)
 {
-	struct amdgpu_bo *rbo;
-	int r;
-
-	if (!amdgpu_fb) {
-		*tiling_flags = 0;
-		*tmz_surface = false;
-		return 0;
-	}
+	/* Fill GFX8 params */
+	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
+		unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
 
-	rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
-	r = amdgpu_bo_reserve(rbo, false);
+		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
+		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
+		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
+		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
+		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
 
-	if (unlikely(r)) {
-		/* Don't show error message when returning -ERESTARTSYS */
-		if (r != -ERESTARTSYS)
-			DRM_ERROR("Unable to reserve buffer: %d\n", r);
-		return r;
+		/* XXX fix me for VI */
+		tiling_info->gfx8.num_banks = num_banks;
+		tiling_info->gfx8.array_mode =
+				DC_ARRAY_2D_TILED_THIN1;
+		tiling_info->gfx8.tile_split = tile_split;
+		tiling_info->gfx8.bank_width = bankw;
+		tiling_info->gfx8.bank_height = bankh;
+		tiling_info->gfx8.tile_aspect = mtaspect;
+		tiling_info->gfx8.tile_mode =
+				DC_ADDR_SURF_MICRO_TILING_DISPLAY;
+	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
+			== DC_ARRAY_1D_TILED_THIN1) {
+		tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
 	}
 
-	if (tiling_flags)
-		amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
-
-	if (tmz_surface)
-		*tmz_surface = amdgpu_bo_encrypted(rbo);
-
-	amdgpu_bo_unreserve(rbo);
-
-	return r;
+	tiling_info->gfx8.pipe_config =
+			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
 }
 
-static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
-{
-	uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
-
-	return offset ? (address + offset * 256) : 0;
+static void
+fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
+				  union dc_tiling_info *tiling_info)
+{
+	tiling_info->gfx9.num_pipes =
+		adev->gfx.config.gb_addr_config_fields.num_pipes;
+	tiling_info->gfx9.num_banks =
+		adev->gfx.config.gb_addr_config_fields.num_banks;
+	tiling_info->gfx9.pipe_interleave =
+		adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
+	tiling_info->gfx9.num_shader_engines =
+		adev->gfx.config.gb_addr_config_fields.num_se;
+	tiling_info->gfx9.max_compressed_frags =
+		adev->gfx.config.gb_addr_config_fields.max_compress_frags;
+	tiling_info->gfx9.num_rb_per_se =
+		adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
+	tiling_info->gfx9.shaderEnable = 1;
+	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
+	    adev->asic_type == CHIP_NAVY_FLOUNDER ||
+	    adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
+	    adev->asic_type == CHIP_VANGOGH)
+		tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
 }
 
 static int
-fill_plane_dcc_attributes(struct amdgpu_device *adev,
-			  const struct amdgpu_framebuffer *afb,
-			  const enum surface_pixel_format format,
-			  const enum dc_rotation_angle rotation,
-			  const struct plane_size *plane_size,
-			  const union dc_tiling_info *tiling_info,
-			  const uint64_t info,
-			  struct dc_plane_dcc_param *dcc,
-			  struct dc_plane_address *address,
-			  bool force_disable_dcc)
+validate_dcc(struct amdgpu_device *adev,
+	     const enum surface_pixel_format format,
+	     const enum dc_rotation_angle rotation,
+	     const union dc_tiling_info *tiling_info,
+	     const struct dc_plane_dcc_param *dcc,
+	     const struct dc_plane_address *address,
+	     const struct plane_size *plane_size)
 {
 	struct dc *dc = adev->dm.dc;
 	struct dc_dcc_surface_param input;
 	struct dc_surface_dcc_cap output;
-	uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
-	uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
-	uint64_t dcc_address;
 
 	memset(&input, 0, sizeof(input));
 	memset(&output, 0, sizeof(output));
 
-	if (force_disable_dcc)
+	if (!dcc->enable)
 		return 0;
 
-	if (!offset)
-		return 0;
-
-	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
-		return 0;
-
-	if (!dc->cap_funcs.get_dcc_compression_cap)
+	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN ||
+	    !dc->cap_funcs.get_dcc_compression_cap)
 		return -EINVAL;
 
 	input.format = format;
@@ -3776,17 +3825,508 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
 	if (!output.capable)
 		return -EINVAL;
 
-	if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
+	if (dcc->independent_64b_blks == 0 &&
+	    output.grph.rgb.independent_64b_blks != 0)
 		return -EINVAL;
 
-	dcc->enable = 1;
-	dcc->meta_pitch =
-		AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
-	dcc->independent_64b_blks = i64b;
+	return 0;
+}
+
+static bool
+modifier_has_dcc(uint64_t modifier)
+{
+	return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
+}
+
+static unsigned
+modifier_gfx9_swizzle_mode(uint64_t modifier)
+{
+	if (modifier == DRM_FORMAT_MOD_LINEAR)
+		return 0;
+
+	return AMD_FMT_MOD_GET(TILE, modifier);
+}
+
+static const struct drm_format_info dcc_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
+	 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
+	   .has_alpha = true, },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
+	  .has_alpha = true, },
+	{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2,
+	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
+	  .has_alpha = true, },
+	{ .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2,
+	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2,
+	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2,
+	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
+	  .has_alpha = true, },
+	{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2,
+	  .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
+	  .has_alpha = true, },
+	{ .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2,
+	  .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
+};
+
+static const struct drm_format_info dcc_retile_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
+	 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
+	   .has_alpha = true, },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
+	  .has_alpha = true, },
+	{ .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3,
+	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
+	  .has_alpha = true, },
+	{ .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3,
+	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3,
+	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3,
+	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
+	  .has_alpha = true, },
+	{ .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3,
+	  .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1,
+	  .has_alpha = true, },
+	{ .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3,
+	  .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, },
+};
+
+
+static const struct drm_format_info *
+lookup_format_info(const struct drm_format_info formats[],
+		  int num_formats, u32 format)
+{
+	int i;
+
+	for (i = 0; i < num_formats; i++) {
+		if (formats[i].format == format)
+			return &formats[i];
+	}
+
+	return NULL;
+}
+
+static const struct drm_format_info *
+amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
+{
+	uint64_t modifier = cmd->modifier[0];
+
+	if (!IS_AMD_FMT_MOD(modifier))
+		return NULL;
+
+	if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
+		return lookup_format_info(dcc_retile_formats,
+					  ARRAY_SIZE(dcc_retile_formats),
+					  cmd->pixel_format);
 
-	dcc_address = get_dcc_address(afb->address, info);
-	address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
-	address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
+	if (AMD_FMT_MOD_GET(DCC, modifier))
+		return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats),
+					  cmd->pixel_format);
+
+	/* returning NULL will cause the default format structs to be used. */
+	return NULL;
+}
+
+static void
+fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
+				    union dc_tiling_info *tiling_info,
+				    uint64_t modifier)
+{
+	unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
+	unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
+	unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
+	unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits);
+
+	fill_gfx9_tiling_info_from_device(adev, tiling_info);
+
+	if (!IS_AMD_FMT_MOD(modifier))
+		return;
+
+	tiling_info->gfx9.num_pipes = 1u << pipes_log2;
+	tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2);
+
+	if (adev->family >= AMDGPU_FAMILY_NV) {
+		tiling_info->gfx9.num_pkrs = 1u << pkrs_log2;
+	} else {
+		tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits;
+
+		/* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */
+	}
+}
+
+enum dm_micro_swizzle {
+	MICRO_SWIZZLE_Z = 0,
+	MICRO_SWIZZLE_S = 1,
+	MICRO_SWIZZLE_D = 2,
+	MICRO_SWIZZLE_R = 3
+};
+
+static bool dm_plane_format_mod_supported(struct drm_plane *plane,
+					  uint32_t format,
+					  uint64_t modifier)
+{
+	struct amdgpu_device *adev = drm_to_adev(plane->dev);
+	const struct drm_format_info *info = drm_format_info(format);
+
+	enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
+
+	if (!info)
+		return false;
+
+	/*
+	 * We always have to allow this modifier, because core DRM still
+	 * checks LINEAR support if userspace does not provide modifers.
+	 */
+	if (modifier == DRM_FORMAT_MOD_LINEAR)
+		return true;
+
+	/*
+	 * The arbitrary tiling support for multiplane formats has not been hooked
+	 * up.
+	 */
+	if (info->num_planes > 1)
+		return false;
+
+	/*
+	 * For D swizzle the canonical modifier depends on the bpp, so check
+	 * it here.
+	 */
+	if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 &&
+	    adev->family >= AMDGPU_FAMILY_NV) {
+		if (microtile == MICRO_SWIZZLE_D && info->cpp[0] == 4)
+			return false;
+	}
+
+	if (adev->family >= AMDGPU_FAMILY_RV && microtile == MICRO_SWIZZLE_D &&
+	    info->cpp[0] < 8)
+		return false;
+
+	if (modifier_has_dcc(modifier)) {
+		/* Per radeonsi comments 16/64 bpp are more complicated. */
+		if (info->cpp[0] != 4)
+			return false;
+	}
+
+	return true;
+}
+
+static void
+add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod)
+{
+	if (!*mods)
+		return;
+
+	if (*cap - *size < 1) {
+		uint64_t new_cap = *cap * 2;
+		uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL);
+
+		if (!new_mods) {
+			kfree(*mods);
+			*mods = NULL;
+			return;
+		}
+
+		memcpy(new_mods, *mods, sizeof(uint64_t) * *size);
+		kfree(*mods);
+		*mods = new_mods;
+		*cap = new_cap;
+	}
+
+	(*mods)[*size] = mod;
+	*size += 1;
+}
+
+static void
+add_gfx9_modifiers(const struct amdgpu_device *adev,
+		   uint64_t **mods, uint64_t *size, uint64_t *capacity)
+{
+	int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
+	int pipe_xor_bits = min(8, pipes +
+				ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
+	int bank_xor_bits = min(8 - pipe_xor_bits,
+				ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
+	int rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
+		 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
+
+
+	if (adev->family == AMDGPU_FAMILY_RV) {
+		/* Raven2 and later */
+		bool has_constant_encode = adev->asic_type > CHIP_RAVEN || adev->external_rev_id >= 0x81;
+
+		/*
+		 * No _D DCC swizzles yet because we only allow 32bpp, which
+		 * doesn't support _D on DCN
+		 */
+
+		if (has_constant_encode) {
+			add_modifier(mods, size, capacity, AMD_FMT_MOD |
+				    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
+				    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
+				    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+				    AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
+				    AMD_FMT_MOD_SET(DCC, 1) |
+				    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+				    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
+				    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1));
+		}
+
+		add_modifier(mods, size, capacity, AMD_FMT_MOD |
+			    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
+			    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
+			    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+			    AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
+			    AMD_FMT_MOD_SET(DCC, 1) |
+			    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+			    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
+			    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0));
+
+		if (has_constant_encode) {
+			add_modifier(mods, size, capacity, AMD_FMT_MOD |
+				    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
+				    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
+				    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+				    AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
+				    AMD_FMT_MOD_SET(DCC, 1) |
+				    AMD_FMT_MOD_SET(DCC_RETILE, 1) |
+				    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+				    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
+
+				    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
+				    AMD_FMT_MOD_SET(RB, rb) |
+				    AMD_FMT_MOD_SET(PIPE, pipes));
+		}
+
+		add_modifier(mods, size, capacity, AMD_FMT_MOD |
+			    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
+			    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
+			    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+			    AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
+			    AMD_FMT_MOD_SET(DCC, 1) |
+			    AMD_FMT_MOD_SET(DCC_RETILE, 1) |
+			    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+			    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
+			    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) |
+			    AMD_FMT_MOD_SET(RB, rb) |
+			    AMD_FMT_MOD_SET(PIPE, pipes));
+	}
+
+	/*
+	 * Only supported for 64bpp on Raven, will be filtered on format in
+	 * dm_plane_format_mod_supported.
+	 */
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
+		    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+		    AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
+
+	if (adev->family == AMDGPU_FAMILY_RV) {
+		add_modifier(mods, size, capacity, AMD_FMT_MOD |
+			    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
+			    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
+			    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+			    AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
+	}
+
+	/*
+	 * Only supported for 64bpp on Raven, will be filtered on format in
+	 * dm_plane_format_mod_supported.
+	 */
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
+
+	if (adev->family == AMDGPU_FAMILY_RV) {
+		add_modifier(mods, size, capacity, AMD_FMT_MOD |
+			    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
+			    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
+	}
+}
+
+static void
+add_gfx10_1_modifiers(const struct amdgpu_device *adev,
+		      uint64_t **mods, uint64_t *size, uint64_t *capacity)
+{
+	int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
+		    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+		    AMD_FMT_MOD_SET(DCC, 1) |
+		    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
+		    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+		    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
+		    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+		    AMD_FMT_MOD_SET(DCC, 1) |
+		    AMD_FMT_MOD_SET(DCC_RETILE, 1) |
+		    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
+		    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+		    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
+		    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
+		    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
+
+
+	/* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
+}
+
+static void
+add_gfx10_3_modifiers(const struct amdgpu_device *adev,
+		      uint64_t **mods, uint64_t *size, uint64_t *capacity)
+{
+	int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
+	int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
+		    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+		    AMD_FMT_MOD_SET(PACKERS, pkrs) |
+		    AMD_FMT_MOD_SET(DCC, 1) |
+		    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
+		    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+		    AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+		    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
+		    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+		    AMD_FMT_MOD_SET(PACKERS, pkrs) |
+		    AMD_FMT_MOD_SET(DCC, 1) |
+		    AMD_FMT_MOD_SET(DCC_RETILE, 1) |
+		    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
+		    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+		    AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+		    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
+		    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+		    AMD_FMT_MOD_SET(PACKERS, pkrs));
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
+		    AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+		    AMD_FMT_MOD_SET(PACKERS, pkrs));
+
+	/* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
+
+	add_modifier(mods, size, capacity, AMD_FMT_MOD |
+		    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
+		    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
+}
+
+static int
+get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
+{
+	uint64_t size = 0, capacity = 128;
+	*mods = NULL;
+
+	/* We have not hooked up any pre-GFX9 modifiers. */
+	if (adev->family < AMDGPU_FAMILY_AI)
+		return 0;
+
+	*mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL);
+
+	if (plane_type == DRM_PLANE_TYPE_CURSOR) {
+		add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
+		add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
+		return *mods ? 0 : -ENOMEM;
+	}
+
+	switch (adev->family) {
+	case AMDGPU_FAMILY_AI:
+	case AMDGPU_FAMILY_RV:
+		add_gfx9_modifiers(adev, mods, &size, &capacity);
+		break;
+	case AMDGPU_FAMILY_NV:
+	case AMDGPU_FAMILY_VGH:
+		if (adev->asic_type >= CHIP_SIENNA_CICHLID)
+			add_gfx10_3_modifiers(adev, mods, &size, &capacity);
+		else
+			add_gfx10_1_modifiers(adev, mods, &size, &capacity);
+		break;
+	}
+
+	add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
+
+	/* INVALID marks the end of the list. */
+	add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
+
+	if (!*mods)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int
+fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
+					  const struct amdgpu_framebuffer *afb,
+					  const enum surface_pixel_format format,
+					  const enum dc_rotation_angle rotation,
+					  const struct plane_size *plane_size,
+					  union dc_tiling_info *tiling_info,
+					  struct dc_plane_dcc_param *dcc,
+					  struct dc_plane_address *address,
+					  const bool force_disable_dcc)
+{
+	const uint64_t modifier = afb->base.modifier;
+	int ret;
+
+	fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
+	tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier);
+
+	if (modifier_has_dcc(modifier) && !force_disable_dcc) {
+		uint64_t dcc_address = afb->address + afb->base.offsets[1];
+
+		dcc->enable = 1;
+		dcc->meta_pitch = afb->base.pitches[1];
+		dcc->independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
+
+		address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
+		address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
+	}
+
+	ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
+	if (ret)
+		return ret;
 
 	return 0;
 }
@@ -3815,6 +4355,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
 	address->tmz_surface = tmz_surface;
 
 	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
+		uint64_t addr = afb->address + fb->offsets[0];
+
 		plane_size->surface_size.x = 0;
 		plane_size->surface_size.y = 0;
 		plane_size->surface_size.width = fb->width;
@@ -3823,9 +4365,10 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
 			fb->pitches[0] / fb->format->cpp[0];
 
 		address->type = PLN_ADDR_TYPE_GRAPHICS;
-		address->grph.addr.low_part = lower_32_bits(afb->address);
-		address->grph.addr.high_part = upper_32_bits(afb->address);
+		address->grph.addr.low_part = lower_32_bits(addr);
+		address->grph.addr.high_part = upper_32_bits(addr);
 	} else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
+		uint64_t luma_addr = afb->address + fb->offsets[0];
 		uint64_t chroma_addr = afb->address + fb->offsets[1];
 
 		plane_size->surface_size.x = 0;
@@ -3846,83 +4389,25 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
 
 		address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
 		address->video_progressive.luma_addr.low_part =
-			lower_32_bits(afb->address);
+			lower_32_bits(luma_addr);
 		address->video_progressive.luma_addr.high_part =
-			upper_32_bits(afb->address);
+			upper_32_bits(luma_addr);
 		address->video_progressive.chroma_addr.low_part =
 			lower_32_bits(chroma_addr);
 		address->video_progressive.chroma_addr.high_part =
 			upper_32_bits(chroma_addr);
 	}
 
-	/* Fill GFX8 params */
-	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
-		unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
-
-		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
-		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
-		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
-		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
-		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
-
-		/* XXX fix me for VI */
-		tiling_info->gfx8.num_banks = num_banks;
-		tiling_info->gfx8.array_mode =
-				DC_ARRAY_2D_TILED_THIN1;
-		tiling_info->gfx8.tile_split = tile_split;
-		tiling_info->gfx8.bank_width = bankw;
-		tiling_info->gfx8.bank_height = bankh;
-		tiling_info->gfx8.tile_aspect = mtaspect;
-		tiling_info->gfx8.tile_mode =
-				DC_ADDR_SURF_MICRO_TILING_DISPLAY;
-	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
-			== DC_ARRAY_1D_TILED_THIN1) {
-		tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
-	}
-
-	tiling_info->gfx8.pipe_config =
-			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
-
-	if (adev->asic_type == CHIP_VEGA10 ||
-	    adev->asic_type == CHIP_VEGA12 ||
-	    adev->asic_type == CHIP_VEGA20 ||
-	    adev->asic_type == CHIP_NAVI10 ||
-	    adev->asic_type == CHIP_NAVI14 ||
-	    adev->asic_type == CHIP_NAVI12 ||
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-		adev->asic_type == CHIP_SIENNA_CICHLID ||
-		adev->asic_type == CHIP_NAVY_FLOUNDER ||
-#endif
-	    adev->asic_type == CHIP_RENOIR ||
-	    adev->asic_type == CHIP_RAVEN) {
-		/* Fill GFX9 params */
-		tiling_info->gfx9.num_pipes =
-			adev->gfx.config.gb_addr_config_fields.num_pipes;
-		tiling_info->gfx9.num_banks =
-			adev->gfx.config.gb_addr_config_fields.num_banks;
-		tiling_info->gfx9.pipe_interleave =
-			adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
-		tiling_info->gfx9.num_shader_engines =
-			adev->gfx.config.gb_addr_config_fields.num_se;
-		tiling_info->gfx9.max_compressed_frags =
-			adev->gfx.config.gb_addr_config_fields.max_compress_frags;
-		tiling_info->gfx9.num_rb_per_se =
-			adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
-		tiling_info->gfx9.swizzle =
-			AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
-		tiling_info->gfx9.shaderEnable = 1;
-
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
-		if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-		    adev->asic_type == CHIP_NAVY_FLOUNDER)
-			tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
-#endif
-		ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
-						plane_size, tiling_info,
-						tiling_flags, dcc, address,
-						force_disable_dcc);
+	if (adev->family >= AMDGPU_FAMILY_AI) {
+		ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
+								rotation, plane_size,
+								tiling_info, dcc,
+								address,
+								force_disable_dcc);
 		if (ret)
 			return ret;
+	} else {
+		fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
 	}
 
 	return 0;
@@ -4122,7 +4607,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
 				    struct drm_crtc_state *crtc_state)
 {
 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
-	struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
+	struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
 	struct dc_scaling_info scaling_info;
 	struct dc_plane_info plane_info;
 	int ret;
@@ -4139,10 +4624,10 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
 
 	force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
 	ret = fill_dc_plane_info_and_addr(adev, plane_state,
-					  dm_plane_state->tiling_flags,
+					  afb->tiling_flags,
 					  &plane_info,
 					  &dc_plane_state->address,
-					  dm_plane_state->tmz_surface,
+					  afb->tmz_surface,
 					  force_disable_dcc);
 	if (ret)
 		return ret;
@@ -4732,6 +5217,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
 			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
 						  &dsc_caps,
 						  aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
+						  0,
 						  link_bandwidth_kbps,
 						  &stream->timing,
 						  &stream->timing.dsc_cfg))
@@ -5310,7 +5796,8 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec
 
 	dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
 
-	if (dc_sink == NULL) {
+	if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
+				aconnector->base.force != DRM_FORCE_ON) {
 		DRM_ERROR("dc_sink is NULL!\n");
 		goto fail;
 	}
@@ -5416,6 +5903,8 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
 	struct drm_crtc_state *new_crtc_state;
 	int ret;
 
+	trace_amdgpu_dm_connector_atomic_check(new_con_state);
+
 	if (!crtc)
 		return 0;
 
@@ -5523,6 +6012,8 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
 	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
 	int ret = -EINVAL;
 
+	trace_amdgpu_dm_crtc_atomic_check(crtc_state);
+
 	dm_update_crtc_active_planes(crtc, crtc_state);
 
 	if (unlikely(!dm_crtc_state->stream &&
@@ -5739,10 +6230,6 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane)
 		dc_plane_state_retain(dm_plane_state->dc_state);
 	}
 
-	/* Framebuffer hasn't been updated yet, so retain old flags. */
-	dm_plane_state->tiling_flags = old_dm_plane_state->tiling_flags;
-	dm_plane_state->tmz_surface = old_dm_plane_state->tmz_surface;
-
 	return &dm_plane_state->base;
 }
 
@@ -5764,6 +6251,7 @@ static const struct drm_plane_funcs dm_plane_funcs = {
 	.reset = dm_drm_plane_reset,
 	.atomic_duplicate_state = dm_drm_plane_duplicate_state,
 	.atomic_destroy_state = dm_drm_plane_destroy_state,
+	.format_mod_supported = dm_plane_format_mod_supported,
 };
 
 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
@@ -5847,10 +6335,10 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
 
 		fill_plane_buffer_attributes(
 			adev, afb, plane_state->format, plane_state->rotation,
-			dm_plane_state_new->tiling_flags,
+			afb->tiling_flags,
 			&plane_state->tiling_info, &plane_state->plane_size,
 			&plane_state->dcc, &plane_state->address,
-			dm_plane_state_new->tmz_surface, force_disable_dcc);
+			afb->tmz_surface, force_disable_dcc);
 	}
 
 	return 0;
@@ -5898,6 +6386,8 @@ static int dm_plane_atomic_check(struct drm_plane *plane,
 	struct drm_crtc_state *new_crtc_state;
 	int ret;
 
+	trace_amdgpu_dm_plane_atomic_check(state);
+
 	dm_plane_state = to_dm_plane_state(state);
 
 	if (!dm_plane_state->dc_state)
@@ -5938,6 +6428,8 @@ static void dm_plane_atomic_async_update(struct drm_plane *plane,
 	struct drm_plane_state *old_state =
 		drm_atomic_get_old_plane_state(new_state->state, plane);
 
+	trace_amdgpu_dm_atomic_update_cursor(new_state);
+
 	swap(plane->state->fb, new_state->fb);
 
 	plane->state->src_x = new_state->src_x;
@@ -6056,13 +6548,19 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 	int num_formats;
 	int res = -EPERM;
 	unsigned int supported_rotations;
+	uint64_t *modifiers = NULL;
 
 	num_formats = get_plane_formats(plane, plane_cap, formats,
 					ARRAY_SIZE(formats));
 
+	res = get_plane_modifiers(dm->adev, plane->type, &modifiers);
+	if (res)
+		return res;
+
 	res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs,
 				       &dm_plane_funcs, formats, num_formats,
-				       NULL, plane->type, NULL);
+				       modifiers, plane->type, NULL);
+	kfree(modifiers);
 	if (res)
 		return res;
 
@@ -7109,6 +7607,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 		struct drm_crtc *crtc = new_plane_state->crtc;
 		struct drm_crtc_state *new_crtc_state;
 		struct drm_framebuffer *fb = new_plane_state->fb;
+		struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
 		bool plane_needs_flip;
 		struct dc_plane_state *dc_plane;
 		struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
@@ -7163,10 +7662,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 
 		fill_dc_plane_info_and_addr(
 			dm->adev, new_plane_state,
-			dm_new_plane_state->tiling_flags,
+			afb->tiling_flags,
 			&bundle->plane_infos[planes_count],
 			&bundle->flip_addrs[planes_count].address,
-			dm_new_plane_state->tmz_surface, false);
+			afb->tmz_surface, false);
 
 		DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",
 				 new_plane_state->plane->index,
@@ -7501,6 +8000,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 	int crtc_disable_count = 0;
 	bool mode_set_reset_required = false;
 
+	trace_amdgpu_dm_atomic_commit_tail_begin(state);
+
 	drm_atomic_helper_update_legacy_modeset_state(dev, state);
 	drm_atomic_helper_calc_timestamping_constants(state);
 
@@ -8306,8 +8807,7 @@ static bool should_reset_plane(struct drm_atomic_state *state,
 	 * TODO: Come up with a more elegant solution for this.
 	 */
 	for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
-		struct dm_plane_state *old_dm_plane_state, *new_dm_plane_state;
-
+		struct amdgpu_framebuffer *old_afb, *new_afb;
 		if (other->type == DRM_PLANE_TYPE_CURSOR)
 			continue;
 
@@ -8351,12 +8851,12 @@ static bool should_reset_plane(struct drm_atomic_state *state,
 		if (old_other_state->fb->format != new_other_state->fb->format)
 			return true;
 
-		old_dm_plane_state = to_dm_plane_state(old_other_state);
-		new_dm_plane_state = to_dm_plane_state(new_other_state);
+		old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
+		new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
 
 		/* Tiling and DCC changes also require bandwidth updates. */
-		if (old_dm_plane_state->tiling_flags !=
-		    new_dm_plane_state->tiling_flags)
+		if (old_afb->tiling_flags != new_afb->tiling_flags ||
+		    old_afb->base.modifier != new_afb->base.modifier)
 			return true;
 	}
 
@@ -8587,8 +9087,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 	enum dc_status status;
 	int ret, i;
 	bool lock_and_validation_needed = false;
+	struct dm_crtc_state *dm_old_crtc_state;
 
-	amdgpu_check_debugfs_connector_property_change(adev, state);
+	trace_amdgpu_dm_atomic_check_begin(state);
 
 	ret = drm_atomic_helper_check_modeset(dev, state);
 	if (ret)
@@ -8629,9 +9130,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 	}
 #endif
 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+
 		if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
 		    !new_crtc_state->color_mgmt_changed &&
-		    old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
+		    old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
+			dm_old_crtc_state->dsc_force_changed == false)
 			continue;
 
 		if (!new_crtc_state->enable)
@@ -8682,17 +9186,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 		}
 	}
 
-	/* Prepass for updating tiling flags on new planes. */
-	for_each_new_plane_in_state(state, plane, new_plane_state, i) {
-		struct dm_plane_state *new_dm_plane_state = to_dm_plane_state(new_plane_state);
-		struct amdgpu_framebuffer *new_afb = to_amdgpu_framebuffer(new_plane_state->fb);
-
-		ret = get_fb_info(new_afb, &new_dm_plane_state->tiling_flags,
-				  &new_dm_plane_state->tmz_surface);
-		if (ret)
-			goto fail;
-	}
-
 	/* Remove exiting planes if they are modified */
 	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
 		ret = dm_update_plane_state(dc, state, plane,
@@ -8886,6 +9379,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 
 	/* Must be success */
 	WARN_ON(ret);
+
+	trace_amdgpu_dm_atomic_check_finish(state, ret);
+
 	return ret;
 
 fail:
@@ -8896,6 +9392,8 @@ fail:
 	else
 		DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
 
+	trace_amdgpu_dm_atomic_check_finish(state, ret);
+
 	return ret;
 }
 
@@ -9160,3 +9658,41 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
 	}
 	mutex_unlock(&adev->dm.dc_lock);
 }
+
+void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
+		       uint32_t value, const char *func_name)
+{
+#ifdef DM_CHECK_ADDR_0
+	if (address == 0) {
+		DC_ERR("invalid register write. address = 0");
+		return;
+	}
+#endif
+	cgs_write_register(ctx->cgs_device, address, value);
+	trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
+}
+
+uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
+			  const char *func_name)
+{
+	uint32_t value;
+#ifdef DM_CHECK_ADDR_0
+	if (address == 0) {
+		DC_ERR("invalid register read; address = 0\n");
+		return 0;
+	}
+#endif
+
+	if (ctx->dmub_srv &&
+	    ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
+	    !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
+		ASSERT(false);
+		return 0;
+	}
+
+	value = cgs_read_register(ctx->cgs_device, address);
+
+	trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
+
+	return value;
+}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 34f6369bf51f..7798eb018257 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -86,7 +86,7 @@ struct irq_list_head {
  * @bo_ptr: Pointer to the buffer object
  * @gpu_addr: MMIO gpu addr
  */
-struct dm_comressor_info {
+struct dm_compressor_info {
 	void *cpu_addr;
 	struct amdgpu_bo *bo_ptr;
 	uint64_t gpu_addr;
@@ -148,7 +148,7 @@ struct amdgpu_dm_backlight_caps {
  * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
  * @cached_state: Caches device atomic state for suspend/resume
  * @cached_dc_state: Cached state of content streams
- * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info
+ * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
  * @force_timing_sync: set via debugfs. When set, indicates that all connected
  *		       displays will be forced to synchronize.
  */
@@ -324,7 +324,7 @@ struct amdgpu_display_manager {
 	struct drm_atomic_state *cached_state;
 	struct dc_state *cached_dc_state;
 
-	struct dm_comressor_info compressor;
+	struct dm_compressor_info compressor;
 
 	const struct firmware *fw_dmcu;
 	uint32_t dmcu_fw_version;
@@ -420,8 +420,6 @@ struct dc_plane_state;
 struct dm_plane_state {
 	struct drm_plane_state base;
 	struct dc_plane_state *dc_state;
-	uint64_t tiling_flags;
-	bool tmz_surface;
 };
 
 struct dm_crtc_state {
@@ -440,6 +438,7 @@ struct dm_crtc_state {
 	bool freesync_timing_changed;
 	bool freesync_vrr_info_changed;
 
+	bool dsc_force_changed;
 	bool vrr_supported;
 	struct mod_freesync_config freesync_config;
 	struct dc_info_packet vrr_infopacket;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index d0699e98db92..c29dc11619f7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -115,7 +115,7 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
 	/* Enable CRTC CRC generation if necessary. */
 	if (dm_is_crc_source_crtc(source)) {
 		if (!dc_stream_configure_crc(stream_state->ctx->dc,
-					     stream_state, enable, enable)) {
+					     stream_state, NULL, enable, enable)) {
 			ret = -EINVAL;
 			goto unlock;
 		}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 8cd646eef096..d31380ea57dc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -556,7 +556,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
 	bool disable_hpd = false;
 	bool valid_test_pattern = false;
 	uint8_t param_nums = 0;
-	/* init with defalut 80bit custom pattern */
+	/* init with default 80bit custom pattern */
 	uint8_t custom_pattern[10] = {
 			0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 			0x1f, 0x7c, 0xf0, 0xc1, 0x07
@@ -1253,6 +1253,10 @@ static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
 				     size_t size, loff_t *pos)
 {
 	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
+	struct drm_connector *connector = &aconnector->base;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc = NULL;
+	struct dm_crtc_state *dm_crtc_state = NULL;
 	struct pipe_ctx *pipe_ctx;
 	int i;
 	char *wr_buf = NULL;
@@ -1295,6 +1299,25 @@ static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
 	if (!pipe_ctx || !pipe_ctx->stream)
 		goto done;
 
+	// Get CRTC state
+	mutex_lock(&dev->mode_config.mutex);
+	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+
+	if (connector->state == NULL)
+		goto unlock;
+
+	crtc = connector->state->crtc;
+	if (crtc == NULL)
+		goto unlock;
+
+	drm_modeset_lock(&crtc->mutex, NULL);
+	if (crtc->state == NULL)
+		goto unlock;
+
+	dm_crtc_state = to_dm_crtc_state(crtc->state);
+	if (dm_crtc_state->stream == NULL)
+		goto unlock;
+
 	if (param[0] == 1)
 		aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
 	else if (param[0] == 2)
@@ -1302,6 +1325,14 @@ static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
 	else
 		aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
 
+	dm_crtc_state->dsc_force_changed = true;
+
+unlock:
+	if (crtc)
+		drm_modeset_unlock(&crtc->mutex);
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+	mutex_unlock(&dev->mode_config.mutex);
+
 done:
 	kfree(wr_buf);
 	return size;
@@ -1408,6 +1439,10 @@ static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
 {
 	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
 	struct pipe_ctx *pipe_ctx;
+	struct drm_connector *connector = &aconnector->base;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc = NULL;
+	struct dm_crtc_state *dm_crtc_state = NULL;
 	int i;
 	char *wr_buf = NULL;
 	uint32_t wr_buf_size = 42;
@@ -1449,6 +1484,25 @@ static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
 	if (!pipe_ctx || !pipe_ctx->stream)
 		goto done;
 
+	// Safely get CRTC state
+	mutex_lock(&dev->mode_config.mutex);
+	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+
+	if (connector->state == NULL)
+		goto unlock;
+
+	crtc = connector->state->crtc;
+	if (crtc == NULL)
+		goto unlock;
+
+	drm_modeset_lock(&crtc->mutex, NULL);
+	if (crtc->state == NULL)
+		goto unlock;
+
+	dm_crtc_state = to_dm_crtc_state(crtc->state);
+	if (dm_crtc_state->stream == NULL)
+		goto unlock;
+
 	if (param[0] > 0)
 		aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
 					pipe_ctx->stream->timing.h_addressable,
@@ -1456,6 +1510,14 @@ static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
 	else
 		aconnector->dsc_settings.dsc_num_slices_h = 0;
 
+	dm_crtc_state->dsc_force_changed = true;
+
+unlock:
+	if (crtc)
+		drm_modeset_unlock(&crtc->mutex);
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+	mutex_unlock(&dev->mode_config.mutex);
+
 done:
 	kfree(wr_buf);
 	return size;
@@ -1561,6 +1623,10 @@ static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
 				     size_t size, loff_t *pos)
 {
 	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
+	struct drm_connector *connector = &aconnector->base;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc = NULL;
+	struct dm_crtc_state *dm_crtc_state = NULL;
 	struct pipe_ctx *pipe_ctx;
 	int i;
 	char *wr_buf = NULL;
@@ -1603,6 +1669,25 @@ static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
 	if (!pipe_ctx || !pipe_ctx->stream)
 		goto done;
 
+	// Get CRTC state
+	mutex_lock(&dev->mode_config.mutex);
+	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+
+	if (connector->state == NULL)
+		goto unlock;
+
+	crtc = connector->state->crtc;
+	if (crtc == NULL)
+		goto unlock;
+
+	drm_modeset_lock(&crtc->mutex, NULL);
+	if (crtc->state == NULL)
+		goto unlock;
+
+	dm_crtc_state = to_dm_crtc_state(crtc->state);
+	if (dm_crtc_state->stream == NULL)
+		goto unlock;
+
 	if (param[0] > 0)
 		aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
 					pipe_ctx->stream->timing.v_addressable,
@@ -1610,6 +1695,14 @@ static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
 	else
 		aconnector->dsc_settings.dsc_num_slices_v = 0;
 
+	dm_crtc_state->dsc_force_changed = true;
+
+unlock:
+	if (crtc)
+		drm_modeset_unlock(&crtc->mutex);
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+	mutex_unlock(&dev->mode_config.mutex);
+
 done:
 	kfree(wr_buf);
 	return size;
@@ -1708,6 +1801,10 @@ static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *bu
 				     size_t size, loff_t *pos)
 {
 	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
+	struct drm_connector *connector = &aconnector->base;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc = NULL;
+	struct dm_crtc_state *dm_crtc_state = NULL;
 	struct pipe_ctx *pipe_ctx;
 	int i;
 	char *wr_buf = NULL;
@@ -1750,8 +1847,35 @@ static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *bu
 	if (!pipe_ctx || !pipe_ctx->stream)
 		goto done;
 
+	// Get CRTC state
+	mutex_lock(&dev->mode_config.mutex);
+	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+
+	if (connector->state == NULL)
+		goto unlock;
+
+	crtc = connector->state->crtc;
+	if (crtc == NULL)
+		goto unlock;
+
+	drm_modeset_lock(&crtc->mutex, NULL);
+	if (crtc->state == NULL)
+		goto unlock;
+
+	dm_crtc_state = to_dm_crtc_state(crtc->state);
+	if (dm_crtc_state->stream == NULL)
+		goto unlock;
+
 	aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
 
+	dm_crtc_state->dsc_force_changed = true;
+
+unlock:
+	if (crtc)
+		drm_modeset_unlock(&crtc->mutex);
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+	mutex_unlock(&dev->mode_config.mutex);
+
 done:
 	kfree(wr_buf);
 	return size;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index d839eb14e3f0..b7d7ec3ba00d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -627,7 +627,6 @@ void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
 {
 	/* TODO: something */
 }
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 
 void *dm_helpers_allocate_gpu_mem(
 		struct dc_context *ctx,
@@ -646,4 +645,3 @@ void dm_helpers_free_gpu_mem(
 {
 	// TODO
 }
-#endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index eee19edeeee5..6f975c16779d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -500,6 +500,7 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p
 					&params[i].sink->dsc_caps.dsc_dec_caps,
 					params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
 					0,
+					0,
 					params[i].timing,
 					&params[i].timing->dsc_cfg)) {
 			params[i].timing->flags.DSC = 1;
@@ -530,6 +531,7 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 			param.sink->ctx->dc->res_pool->dscs[0],
 			&param.sink->dsc_caps.dsc_dec_caps,
 			param.sink->ctx->dc->debug.dsc_min_slice_height_override,
+			0,
 			(int) kbps, param.timing, &dsc_config);
 
 	return dsc_config.bits_per_pixel;
@@ -734,7 +736,7 @@ static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 		params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
 		params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
 		params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
-		dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
+		dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
 		if (!dc_dsc_compute_bandwidth_range(
 				stream->sink->ctx->dc->res_pool->dscs[0],
 				stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 6e575ffe34d0..84065c12d4b8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -346,13 +346,6 @@ bool dm_pp_get_clock_levels_by_type(
 			get_default_clock_levels(clk_type, dc_clks);
 			return true;
 		}
-	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type) {
-		if (smu_get_clock_by_type(&adev->smu,
-					  dc_to_pp_clock_type(clk_type),
-					  &pp_clks)) {
-			get_default_clock_levels(clk_type, dc_clks);
-			return true;
-		}
 	}
 
 	pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
@@ -366,13 +359,6 @@ bool dm_pp_get_clock_levels_by_type(
 			validation_clks.memory_max_clock = 80000;
 			validation_clks.level = 0;
 		}
-	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_max_high_clocks) {
-		if (smu_get_max_high_clocks(&adev->smu, &validation_clks)) {
-			DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
-			validation_clks.engine_max_clock = 72000;
-			validation_clks.memory_max_clock = 80000;
-			validation_clks.level = 0;
-		}
 	}
 
 	DRM_INFO("DM_PPLIB: Validation clocks:\n");
@@ -461,11 +447,6 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
 						&pp_clk_info);
 		if (ret)
 			return false;
-	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_voltage) {
-		if (smu_get_clock_by_type_with_voltage(&adev->smu,
-						       dc_to_pp_clock_type(clk_type),
-						       &pp_clk_info))
-			return false;
 	}
 
 	pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type);
@@ -477,7 +458,21 @@ bool dm_pp_notify_wm_clock_changes(
 	const struct dc_context *ctx,
 	struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
 {
-	/* TODO: to be implemented */
+	struct amdgpu_device *adev = ctx->driver_context;
+	void *pp_handle = adev->powerplay.pp_handle;
+	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+	/*
+	 * Limit this watermark setting for Polaris for now
+	 * TODO: expand this to other ASICs
+	 */
+	if ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_VEGAM)
+	     && pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges) {
+		if (!pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
+						(void *)wm_with_clock_ranges))
+			return true;
+	}
+
 	return false;
 }
 
@@ -528,8 +523,6 @@ bool dm_pp_get_static_clocks(
 		ret = adev->powerplay.pp_funcs->get_current_clocks(
 			adev->powerplay.pp_handle,
 			&pp_clk_info);
-	else if (adev->smu.ppt_funcs)
-		ret = smu_get_current_clocks(&adev->smu, &pp_clk_info);
 	else
 		return false;
 	if (ret)
@@ -603,8 +596,6 @@ void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
 
 	if (pp_funcs && pp_funcs->notify_smu_enable_pwe)
 		pp_funcs->notify_smu_enable_pwe(pp_handle);
-	else if (adev->smu.ppt_funcs)
-		smu_notify_smu_enable_pwe(&adev->smu);
 }
 
 void pp_rv_set_active_display_count(struct pp_smu *pp, int count)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 51f57420fadd..d9e33c6bccd9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -33,18 +33,23 @@
 #include "amdgpu_dm.h"
 #include "amdgpu_dm_irq.h"
 #include "amdgpu_pm.h"
+#include "amdgpu_dm_trace.h"
 
-
-
-unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
-		unsigned long long current_time_stamp,
-		unsigned long long last_time_stamp)
+	unsigned long long
+	dm_get_elapse_time_in_ns(struct dc_context *ctx,
+				 unsigned long long current_time_stamp,
+				 unsigned long long last_time_stamp)
 {
 	return current_time_stamp - last_time_stamp;
 }
 
-void dm_perf_trace_timestamp(const char *func_name, unsigned int line)
+void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc_context *ctx)
 {
+	trace_amdgpu_dc_performance(ctx->perf_trace->read_count,
+				    ctx->perf_trace->write_count,
+				    &ctx->perf_trace->last_entry_read,
+				    &ctx->perf_trace->last_entry_write,
+				    func_name, line);
 }
 
 /**** power component interfaces ****/
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
index d898981684d5..86960476823c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
@@ -26,45 +26,46 @@
 #undef TRACE_SYSTEM
 #define TRACE_SYSTEM amdgpu_dm
 
-#if !defined(_AMDGPU_DM_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
+#if !defined(_AMDGPU_DM_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
 #define _AMDGPU_DM_TRACE_H_
 
 #include <linux/tracepoint.h>
+#include <drm/drm_connector.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_plane.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_encoder.h>
+#include <drm/drm_atomic.h>
 
-TRACE_EVENT(amdgpu_dc_rreg,
-	TP_PROTO(unsigned long *read_count, uint32_t reg, uint32_t value),
-	TP_ARGS(read_count, reg, value),
-	TP_STRUCT__entry(
-			__field(uint32_t, reg)
-			__field(uint32_t, value)
-		),
-	TP_fast_assign(
-			__entry->reg = reg;
-			__entry->value = value;
-			*read_count = *read_count + 1;
-		),
-	TP_printk("reg=0x%08lx, value=0x%08lx",
-			(unsigned long)__entry->reg,
-			(unsigned long)__entry->value)
-);
+#include "dc/inc/core_types.h"
 
-TRACE_EVENT(amdgpu_dc_wreg,
-	TP_PROTO(unsigned long *write_count, uint32_t reg, uint32_t value),
-	TP_ARGS(write_count, reg, value),
-	TP_STRUCT__entry(
-			__field(uint32_t, reg)
-			__field(uint32_t, value)
-		),
-	TP_fast_assign(
-			__entry->reg = reg;
-			__entry->value = value;
-			*write_count = *write_count + 1;
-		),
-	TP_printk("reg=0x%08lx, value=0x%08lx",
-			(unsigned long)__entry->reg,
-			(unsigned long)__entry->value)
+DECLARE_EVENT_CLASS(amdgpu_dc_reg_template,
+		    TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
+		    TP_ARGS(count, reg, value),
+
+		    TP_STRUCT__entry(
+				     __field(uint32_t, reg)
+				     __field(uint32_t, value)
+		    ),
+
+		    TP_fast_assign(
+				   __entry->reg = reg;
+				   __entry->value = value;
+				   *count = *count + 1;
+		    ),
+
+		    TP_printk("reg=0x%08lx, value=0x%08lx",
+			      (unsigned long)__entry->reg,
+			      (unsigned long)__entry->value)
 );
 
+DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_rreg,
+	     TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
+	     TP_ARGS(count, reg, value));
+
+DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_wreg,
+	     TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
+	     TP_ARGS(count, reg, value));
 
 TRACE_EVENT(amdgpu_dc_performance,
 	TP_PROTO(unsigned long read_count, unsigned long write_count,
@@ -96,6 +97,506 @@ TRACE_EVENT(amdgpu_dc_performance,
 			(unsigned long)__entry->write_delta,
 			(unsigned long)__entry->writes)
 );
+
+TRACE_EVENT(amdgpu_dm_connector_atomic_check,
+	    TP_PROTO(const struct drm_connector_state *state),
+	    TP_ARGS(state),
+
+	    TP_STRUCT__entry(
+			     __field(uint32_t, conn_id)
+			     __field(const struct drm_connector_state *, conn_state)
+			     __field(const struct drm_atomic_state *, state)
+			     __field(const struct drm_crtc_commit *, commit)
+			     __field(uint32_t, crtc_id)
+			     __field(uint32_t, best_encoder_id)
+			     __field(enum drm_link_status, link_status)
+			     __field(bool, self_refresh_aware)
+			     __field(enum hdmi_picture_aspect, picture_aspect_ratio)
+			     __field(unsigned int, content_type)
+			     __field(unsigned int, hdcp_content_type)
+			     __field(unsigned int, content_protection)
+			     __field(unsigned int, scaling_mode)
+			     __field(u32, colorspace)
+			     __field(u8, max_requested_bpc)
+			     __field(u8, max_bpc)
+	    ),
+
+	    TP_fast_assign(
+			   __entry->conn_id = state->connector->base.id;
+			   __entry->conn_state = state;
+			   __entry->state = state->state;
+			   __entry->commit = state->commit;
+			   __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;
+			   __entry->best_encoder_id = state->best_encoder ?
+						      state->best_encoder->base.id : 0;
+			   __entry->link_status = state->link_status;
+			   __entry->self_refresh_aware = state->self_refresh_aware;
+			   __entry->picture_aspect_ratio = state->picture_aspect_ratio;
+			   __entry->content_type = state->content_type;
+			   __entry->hdcp_content_type = state->hdcp_content_type;
+			   __entry->content_protection = state->content_protection;
+			   __entry->scaling_mode = state->scaling_mode;
+			   __entry->colorspace = state->colorspace;
+			   __entry->max_requested_bpc = state->max_requested_bpc;
+			   __entry->max_bpc = state->max_bpc;
+	    ),
+
+	    TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u "
+		      "best_encoder_id=%u link_status=%d self_refresh_aware=%d "
+		      "picture_aspect_ratio=%d content_type=%u "
+		      "hdcp_content_type=%u content_protection=%u scaling_mode=%u "
+		      "colorspace=%u max_requested_bpc=%u max_bpc=%u",
+		      __entry->conn_id, __entry->conn_state, __entry->state,
+		      __entry->commit, __entry->crtc_id, __entry->best_encoder_id,
+		      __entry->link_status, __entry->self_refresh_aware,
+		      __entry->picture_aspect_ratio, __entry->content_type,
+		      __entry->hdcp_content_type, __entry->content_protection,
+		      __entry->scaling_mode, __entry->colorspace,
+		      __entry->max_requested_bpc, __entry->max_bpc)
+);
+
+TRACE_EVENT(amdgpu_dm_crtc_atomic_check,
+	    TP_PROTO(const struct drm_crtc_state *state),
+	    TP_ARGS(state),
+
+	    TP_STRUCT__entry(
+			     __field(const struct drm_atomic_state *, state)
+			     __field(const struct drm_crtc_state *, crtc_state)
+			     __field(const struct drm_crtc_commit *, commit)
+			     __field(uint32_t, crtc_id)
+			     __field(bool, enable)
+			     __field(bool, active)
+			     __field(bool, planes_changed)
+			     __field(bool, mode_changed)
+			     __field(bool, active_changed)
+			     __field(bool, connectors_changed)
+			     __field(bool, zpos_changed)
+			     __field(bool, color_mgmt_changed)
+			     __field(bool, no_vblank)
+			     __field(bool, async_flip)
+			     __field(bool, vrr_enabled)
+			     __field(bool, self_refresh_active)
+			     __field(u32, plane_mask)
+			     __field(u32, connector_mask)
+			     __field(u32, encoder_mask)
+	    ),
+
+	    TP_fast_assign(
+			   __entry->state = state->state;
+			   __entry->crtc_state = state;
+			   __entry->crtc_id = state->crtc->base.id;
+			   __entry->commit = state->commit;
+			   __entry->enable = state->enable;
+			   __entry->active = state->active;
+			   __entry->planes_changed = state->planes_changed;
+			   __entry->mode_changed = state->mode_changed;
+			   __entry->active_changed = state->active_changed;
+			   __entry->connectors_changed = state->connectors_changed;
+			   __entry->zpos_changed = state->zpos_changed;
+			   __entry->color_mgmt_changed = state->color_mgmt_changed;
+			   __entry->no_vblank = state->no_vblank;
+			   __entry->async_flip = state->async_flip;
+			   __entry->vrr_enabled = state->vrr_enabled;
+			   __entry->self_refresh_active = state->self_refresh_active;
+			   __entry->plane_mask = state->plane_mask;
+			   __entry->connector_mask = state->connector_mask;
+			   __entry->encoder_mask = state->encoder_mask;
+	    ),
+
+	    TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed("
+		      "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) "
+		      "state(enable=%d active=%d async_flip=%d vrr_enabled=%d "
+		      "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x "
+		      "enc=%x)",
+		      __entry->crtc_id, __entry->crtc_state, __entry->state,
+		      __entry->commit, __entry->planes_changed,
+		      __entry->mode_changed, __entry->active_changed,
+		      __entry->connectors_changed, __entry->zpos_changed,
+		      __entry->color_mgmt_changed, __entry->enable, __entry->active,
+		      __entry->async_flip, __entry->vrr_enabled,
+		      __entry->self_refresh_active, __entry->no_vblank,
+		      __entry->plane_mask, __entry->connector_mask,
+		      __entry->encoder_mask)
+);
+
+DECLARE_EVENT_CLASS(amdgpu_dm_plane_state_template,
+	    TP_PROTO(const struct drm_plane_state *state),
+	    TP_ARGS(state),
+	    TP_STRUCT__entry(
+			     __field(uint32_t, plane_id)
+			     __field(enum drm_plane_type, plane_type)
+			     __field(const struct drm_plane_state *, plane_state)
+			     __field(const struct drm_atomic_state *, state)
+			     __field(uint32_t, crtc_id)
+			     __field(uint32_t, fb_id)
+			     __field(uint32_t, fb_format)
+			     __field(uint8_t, fb_planes)
+			     __field(uint64_t, fb_modifier)
+			     __field(const struct dma_fence *, fence)
+			     __field(int32_t, crtc_x)
+			     __field(int32_t, crtc_y)
+			     __field(uint32_t, crtc_w)
+			     __field(uint32_t, crtc_h)
+			     __field(uint32_t, src_x)
+			     __field(uint32_t, src_y)
+			     __field(uint32_t, src_w)
+			     __field(uint32_t, src_h)
+			     __field(u32, alpha)
+			     __field(uint32_t, pixel_blend_mode)
+			     __field(unsigned int, rotation)
+			     __field(unsigned int, zpos)
+			     __field(unsigned int, normalized_zpos)
+			     __field(enum drm_color_encoding, color_encoding)
+			     __field(enum drm_color_range, color_range)
+			     __field(bool, visible)
+	    ),
+
+	    TP_fast_assign(
+			   __entry->plane_id = state->plane->base.id;
+			   __entry->plane_type = state->plane->type;
+			   __entry->plane_state = state;
+			   __entry->state = state->state;
+			   __entry->crtc_id = state->crtc ? state->crtc->base.id : 0;
+			   __entry->fb_id = state->fb ? state->fb->base.id : 0;
+			   __entry->fb_format = state->fb ? state->fb->format->format : 0;
+			   __entry->fb_planes = state->fb ? state->fb->format->num_planes : 0;
+			   __entry->fb_modifier = state->fb ? state->fb->modifier : 0;
+			   __entry->fence = state->fence;
+			   __entry->crtc_x = state->crtc_x;
+			   __entry->crtc_y = state->crtc_y;
+			   __entry->crtc_w = state->crtc_w;
+			   __entry->crtc_h = state->crtc_h;
+			   __entry->src_x = state->src_x >> 16;
+			   __entry->src_y = state->src_y >> 16;
+			   __entry->src_w = state->src_w >> 16;
+			   __entry->src_h = state->src_h >> 16;
+			   __entry->alpha = state->alpha;
+			   __entry->pixel_blend_mode = state->pixel_blend_mode;
+			   __entry->rotation = state->rotation;
+			   __entry->zpos = state->zpos;
+			   __entry->normalized_zpos = state->normalized_zpos;
+			   __entry->color_encoding = state->color_encoding;
+			   __entry->color_range = state->color_range;
+			   __entry->visible = state->visible;
+	    ),
+
+	    TP_printk("plane_id=%u plane_type=%d plane_state=%p state=%p "
+		      "crtc_id=%u fb(id=%u fmt=%c%c%c%c planes=%u mod=%llu) "
+		      "fence=%p crtc_x=%d crtc_y=%d crtc_w=%u crtc_h=%u "
+		      "src_x=%u src_y=%u src_w=%u src_h=%u alpha=%u "
+		      "pixel_blend_mode=%u rotation=%u zpos=%u "
+		      "normalized_zpos=%u color_encoding=%d color_range=%d "
+		      "visible=%d",
+		      __entry->plane_id, __entry->plane_type, __entry->plane_state,
+		      __entry->state, __entry->crtc_id, __entry->fb_id,
+		      (__entry->fb_format & 0xff) ? (__entry->fb_format & 0xff) : 'N',
+		      ((__entry->fb_format >> 8) & 0xff) ? ((__entry->fb_format >> 8) & 0xff) : 'O',
+		      ((__entry->fb_format >> 16) & 0xff) ? ((__entry->fb_format >> 16) & 0xff) : 'N',
+		      ((__entry->fb_format >> 24) & 0x7f) ? ((__entry->fb_format >> 24) & 0x7f) : 'E',
+		      __entry->fb_planes,
+		      __entry->fb_modifier, __entry->fence, __entry->crtc_x,
+		      __entry->crtc_y, __entry->crtc_w, __entry->crtc_h,
+		      __entry->src_x, __entry->src_y, __entry->src_w, __entry->src_h,
+		      __entry->alpha, __entry->pixel_blend_mode, __entry->rotation,
+		      __entry->zpos, __entry->normalized_zpos,
+		      __entry->color_encoding, __entry->color_range,
+		      __entry->visible)
+);
+
+DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_plane_atomic_check,
+	     TP_PROTO(const struct drm_plane_state *state),
+	     TP_ARGS(state));
+
+DEFINE_EVENT(amdgpu_dm_plane_state_template, amdgpu_dm_atomic_update_cursor,
+	     TP_PROTO(const struct drm_plane_state *state),
+	     TP_ARGS(state));
+
+TRACE_EVENT(amdgpu_dm_atomic_state_template,
+	    TP_PROTO(const struct drm_atomic_state *state),
+	    TP_ARGS(state),
+
+	    TP_STRUCT__entry(
+			     __field(const struct drm_atomic_state *, state)
+			     __field(bool, allow_modeset)
+			     __field(bool, legacy_cursor_update)
+			     __field(bool, async_update)
+			     __field(bool, duplicated)
+			     __field(int, num_connector)
+			     __field(int, num_private_objs)
+	    ),
+
+	    TP_fast_assign(
+			   __entry->state = state;
+			   __entry->allow_modeset = state->allow_modeset;
+			   __entry->legacy_cursor_update = state->legacy_cursor_update;
+			   __entry->async_update = state->async_update;
+			   __entry->duplicated = state->duplicated;
+			   __entry->num_connector = state->num_connector;
+			   __entry->num_private_objs = state->num_private_objs;
+	    ),
+
+	    TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d "
+		      "async_update=%d duplicated=%d num_connector=%d "
+		      "num_private_objs=%d",
+		      __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update,
+		      __entry->async_update, __entry->duplicated, __entry->num_connector,
+		      __entry->num_private_objs)
+);
+
+DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_begin,
+	     TP_PROTO(const struct drm_atomic_state *state),
+	     TP_ARGS(state));
+
+DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_commit_tail_finish,
+	     TP_PROTO(const struct drm_atomic_state *state),
+	     TP_ARGS(state));
+
+DEFINE_EVENT(amdgpu_dm_atomic_state_template, amdgpu_dm_atomic_check_begin,
+	     TP_PROTO(const struct drm_atomic_state *state),
+	     TP_ARGS(state));
+
+TRACE_EVENT(amdgpu_dm_atomic_check_finish,
+	    TP_PROTO(const struct drm_atomic_state *state, int res),
+	    TP_ARGS(state, res),
+
+	    TP_STRUCT__entry(
+			     __field(const struct drm_atomic_state *, state)
+			     __field(int, res)
+			     __field(bool, async_update)
+			     __field(bool, allow_modeset)
+	    ),
+
+	    TP_fast_assign(
+			   __entry->state = state;
+			   __entry->res = res;
+			   __entry->async_update = state->async_update;
+			   __entry->allow_modeset = state->allow_modeset;
+	    ),
+
+	    TP_printk("state=%p res=%d async_update=%d allow_modeset=%d",
+		      __entry->state, __entry->res,
+		      __entry->async_update, __entry->allow_modeset)
+);
+
+TRACE_EVENT(amdgpu_dm_dc_pipe_state,
+	    TP_PROTO(int pipe_idx, const struct dc_plane_state *plane_state,
+		     const struct dc_stream_state *stream,
+		     const struct plane_resource *plane_res,
+		     int update_flags),
+	    TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
+
+	    TP_STRUCT__entry(
+			     __field(int, pipe_idx)
+			     __field(const void *, stream)
+			     __field(int, stream_w)
+			     __field(int, stream_h)
+			     __field(int, dst_x)
+			     __field(int, dst_y)
+			     __field(int, dst_w)
+			     __field(int, dst_h)
+			     __field(int, src_x)
+			     __field(int, src_y)
+			     __field(int, src_w)
+			     __field(int, src_h)
+			     __field(int, clip_x)
+			     __field(int, clip_y)
+			     __field(int, clip_w)
+			     __field(int, clip_h)
+			     __field(int, recout_x)
+			     __field(int, recout_y)
+			     __field(int, recout_w)
+			     __field(int, recout_h)
+			     __field(int, viewport_x)
+			     __field(int, viewport_y)
+			     __field(int, viewport_w)
+			     __field(int, viewport_h)
+			     __field(int, flip_immediate)
+			     __field(int, surface_pitch)
+			     __field(int, format)
+			     __field(int, swizzle)
+			     __field(unsigned int, update_flags)
+	),
+
+	TP_fast_assign(
+		       __entry->pipe_idx = pipe_idx;
+		       __entry->stream = stream;
+		       __entry->stream_w = stream->timing.h_addressable;
+		       __entry->stream_h = stream->timing.v_addressable;
+		       __entry->dst_x = plane_state->dst_rect.x;
+		       __entry->dst_y = plane_state->dst_rect.y;
+		       __entry->dst_w = plane_state->dst_rect.width;
+		       __entry->dst_h = plane_state->dst_rect.height;
+		       __entry->src_x = plane_state->src_rect.x;
+		       __entry->src_y = plane_state->src_rect.y;
+		       __entry->src_w = plane_state->src_rect.width;
+		       __entry->src_h = plane_state->src_rect.height;
+		       __entry->clip_x = plane_state->clip_rect.x;
+		       __entry->clip_y = plane_state->clip_rect.y;
+		       __entry->clip_w = plane_state->clip_rect.width;
+		       __entry->clip_h = plane_state->clip_rect.height;
+		       __entry->recout_x = plane_res->scl_data.recout.x;
+		       __entry->recout_y = plane_res->scl_data.recout.y;
+		       __entry->recout_w = plane_res->scl_data.recout.width;
+		       __entry->recout_h = plane_res->scl_data.recout.height;
+		       __entry->viewport_x = plane_res->scl_data.viewport.x;
+		       __entry->viewport_y = plane_res->scl_data.viewport.y;
+		       __entry->viewport_w = plane_res->scl_data.viewport.width;
+		       __entry->viewport_h = plane_res->scl_data.viewport.height;
+		       __entry->flip_immediate = plane_state->flip_immediate;
+		       __entry->surface_pitch = plane_state->plane_size.surface_pitch;
+		       __entry->format = plane_state->format;
+		       __entry->swizzle = plane_state->tiling_info.gfx9.swizzle;
+		       __entry->update_flags = update_flags;
+	),
+	TP_printk("pipe_idx=%d stream=%p rct(%d,%d) dst=(%d,%d,%d,%d) "
+		  "src=(%d,%d,%d,%d) clip=(%d,%d,%d,%d) recout=(%d,%d,%d,%d) "
+		  "viewport=(%d,%d,%d,%d) flip_immediate=%d pitch=%d "
+		  "format=%d swizzle=%d update_flags=%x",
+		  __entry->pipe_idx,
+		  __entry->stream,
+		  __entry->stream_w,
+		  __entry->stream_h,
+		  __entry->dst_x,
+		  __entry->dst_y,
+		  __entry->dst_w,
+		  __entry->dst_h,
+		  __entry->src_x,
+		  __entry->src_y,
+		  __entry->src_w,
+		  __entry->src_h,
+		  __entry->clip_x,
+		  __entry->clip_y,
+		  __entry->clip_w,
+		  __entry->clip_h,
+		  __entry->recout_x,
+		  __entry->recout_y,
+		  __entry->recout_w,
+		  __entry->recout_h,
+		  __entry->viewport_x,
+		  __entry->viewport_y,
+		  __entry->viewport_w,
+		  __entry->viewport_h,
+		  __entry->flip_immediate,
+		  __entry->surface_pitch,
+		  __entry->format,
+		  __entry->swizzle,
+		  __entry->update_flags
+	)
+);
+
+TRACE_EVENT(amdgpu_dm_dc_clocks_state,
+	    TP_PROTO(const struct dc_clocks *clk),
+	    TP_ARGS(clk),
+
+	    TP_STRUCT__entry(
+			     __field(int, dispclk_khz)
+			     __field(int, dppclk_khz)
+			     __field(int, disp_dpp_voltage_level_khz)
+			     __field(int, dcfclk_khz)
+			     __field(int, socclk_khz)
+			     __field(int, dcfclk_deep_sleep_khz)
+			     __field(int, fclk_khz)
+			     __field(int, phyclk_khz)
+			     __field(int, dramclk_khz)
+			     __field(int, p_state_change_support)
+			     __field(int, prev_p_state_change_support)
+			     __field(int, pwr_state)
+			     __field(int, dtm_level)
+			     __field(int, max_supported_dppclk_khz)
+			     __field(int, max_supported_dispclk_khz)
+			     __field(int, bw_dppclk_khz)
+			     __field(int, bw_dispclk_khz)
+	    ),
+	    TP_fast_assign(
+			   __entry->dispclk_khz = clk->dispclk_khz;
+			   __entry->dppclk_khz = clk->dppclk_khz;
+			   __entry->dcfclk_khz = clk->dcfclk_khz;
+			   __entry->socclk_khz = clk->socclk_khz;
+			   __entry->dcfclk_deep_sleep_khz = clk->dcfclk_deep_sleep_khz;
+			   __entry->fclk_khz = clk->fclk_khz;
+			   __entry->phyclk_khz = clk->phyclk_khz;
+			   __entry->dramclk_khz = clk->dramclk_khz;
+			   __entry->p_state_change_support = clk->p_state_change_support;
+			   __entry->prev_p_state_change_support = clk->prev_p_state_change_support;
+			   __entry->pwr_state = clk->pwr_state;
+			   __entry->prev_p_state_change_support = clk->prev_p_state_change_support;
+			   __entry->dtm_level = clk->dtm_level;
+			   __entry->max_supported_dppclk_khz = clk->max_supported_dppclk_khz;
+			   __entry->max_supported_dispclk_khz = clk->max_supported_dispclk_khz;
+			   __entry->bw_dppclk_khz = clk->bw_dppclk_khz;
+			   __entry->bw_dispclk_khz = clk->bw_dispclk_khz;
+	    ),
+	    TP_printk("dispclk_khz=%d dppclk_khz=%d disp_dpp_voltage_level_khz=%d dcfclk_khz=%d socclk_khz=%d "
+		      "dcfclk_deep_sleep_khz=%d fclk_khz=%d phyclk_khz=%d "
+		      "dramclk_khz=%d p_state_change_support=%d "
+		      "prev_p_state_change_support=%d pwr_state=%d prev_p_state_change_support=%d "
+		      "dtm_level=%d max_supported_dppclk_khz=%d max_supported_dispclk_khz=%d "
+		      "bw_dppclk_khz=%d bw_dispclk_khz=%d ",
+		      __entry->dispclk_khz,
+		      __entry->dppclk_khz,
+		      __entry->disp_dpp_voltage_level_khz,
+		      __entry->dcfclk_khz,
+		      __entry->socclk_khz,
+		      __entry->dcfclk_deep_sleep_khz,
+		      __entry->fclk_khz,
+		      __entry->phyclk_khz,
+		      __entry->dramclk_khz,
+		      __entry->p_state_change_support,
+		      __entry->prev_p_state_change_support,
+		      __entry->pwr_state,
+		      __entry->prev_p_state_change_support,
+		      __entry->dtm_level,
+		      __entry->max_supported_dppclk_khz,
+		      __entry->max_supported_dispclk_khz,
+		      __entry->bw_dppclk_khz,
+		      __entry->bw_dispclk_khz
+	    )
+);
+
+TRACE_EVENT(amdgpu_dm_dce_clocks_state,
+	    TP_PROTO(const struct dce_bw_output *clk),
+	    TP_ARGS(clk),
+
+	    TP_STRUCT__entry(
+			     __field(bool, cpuc_state_change_enable)
+			     __field(bool, cpup_state_change_enable)
+			     __field(bool, stutter_mode_enable)
+			     __field(bool, nbp_state_change_enable)
+			     __field(bool, all_displays_in_sync)
+			     __field(int, sclk_khz)
+			     __field(int, sclk_deep_sleep_khz)
+			     __field(int, yclk_khz)
+			     __field(int, dispclk_khz)
+			     __field(int, blackout_recovery_time_us)
+	    ),
+	    TP_fast_assign(
+			   __entry->cpuc_state_change_enable = clk->cpuc_state_change_enable;
+			   __entry->cpup_state_change_enable = clk->cpup_state_change_enable;
+			   __entry->stutter_mode_enable = clk->stutter_mode_enable;
+			   __entry->nbp_state_change_enable = clk->nbp_state_change_enable;
+			   __entry->all_displays_in_sync = clk->all_displays_in_sync;
+			   __entry->sclk_khz = clk->sclk_khz;
+			   __entry->sclk_deep_sleep_khz = clk->sclk_deep_sleep_khz;
+			   __entry->yclk_khz = clk->yclk_khz;
+			   __entry->dispclk_khz = clk->dispclk_khz;
+			   __entry->blackout_recovery_time_us = clk->blackout_recovery_time_us;
+	    ),
+	    TP_printk("cpuc_state_change_enable=%d cpup_state_change_enable=%d stutter_mode_enable=%d "
+		      "nbp_state_change_enable=%d all_displays_in_sync=%d sclk_khz=%d sclk_deep_sleep_khz=%d "
+		      "yclk_khz=%d dispclk_khz=%d blackout_recovery_time_us=%d",
+		      __entry->cpuc_state_change_enable,
+		      __entry->cpup_state_change_enable,
+		      __entry->stutter_mode_enable,
+		      __entry->nbp_state_change_enable,
+		      __entry->all_displays_in_sync,
+		      __entry->sclk_khz,
+		      __entry->sclk_deep_sleep_khz,
+		      __entry->yclk_khz,
+		      __entry->dispclk_khz,
+		      __entry->blackout_recovery_time_us
+	    )
+);
+
 #endif /* _AMDGPU_DM_TRACE_H_ */
 
 #undef TRACE_INCLUDE_PATH
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 047b1e2dd8f1..bf8fe0471b8f 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -30,10 +30,9 @@ DC_LIBS += dcn20
 DC_LIBS += dsc
 DC_LIBS += dcn10 dml
 DC_LIBS += dcn21
-endif
-
-ifdef CONFIG_DRM_AMD_DC_DCN3_0
 DC_LIBS += dcn30
+DC_LIBS += dcn301
+DC_LIBS += dcn302
 endif
 
 DC_LIBS += dce120
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 29d64e7e304f..43922fa358a9 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1230,12 +1230,8 @@ static enum bp_result bios_parser_get_firmware_info(
 				result = get_firmware_info_v3_1(bp, info);
 				break;
 			case 2:
-				result = get_firmware_info_v3_2(bp, info);
-				break;
 			case 3:
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 			case 4:
-#endif
 				result = get_firmware_info_v3_2(bp, info);
 				break;
 			default:
@@ -1743,6 +1739,165 @@ static enum bp_result get_integrated_info_v11(
 	return BP_RESULT_OK;
 }
 
+static enum bp_result get_integrated_info_v2_1(
+	struct bios_parser *bp,
+	struct integrated_info *info)
+{
+	struct atom_integrated_system_info_v2_1 *info_v2_1;
+	uint32_t i;
+
+	info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1,
+					DATA_TABLES(integratedsysteminfo));
+
+	if (info_v2_1 == NULL)
+		return BP_RESULT_BADBIOSTABLE;
+
+	info->gpu_cap_info =
+	le32_to_cpu(info_v2_1->gpucapinfo);
+	/*
+	* system_config: Bit[0] = 0 : PCIE power gating disabled
+	*                       = 1 : PCIE power gating enabled
+	*                Bit[1] = 0 : DDR-PLL shut down disabled
+	*                       = 1 : DDR-PLL shut down enabled
+	*                Bit[2] = 0 : DDR-PLL power down disabled
+	*                       = 1 : DDR-PLL power down enabled
+	*/
+	info->system_config = le32_to_cpu(info_v2_1->system_config);
+	info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo);
+	info->memory_type = info_v2_1->memorytype;
+	info->ma_channel_number = info_v2_1->umachannelnumber;
+	info->dp_ss_control =
+		le16_to_cpu(info_v2_1->reserved1);
+
+	for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
+		info->ext_disp_conn_info.gu_id[i] =
+				info_v2_1->extdispconninfo.guid[i];
+	}
+
+	for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
+		info->ext_disp_conn_info.path[i].device_connector_id =
+		object_id_from_bios_object_id(
+		le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid));
+
+		info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
+		object_id_from_bios_object_id(
+			le16_to_cpu(
+			info_v2_1->extdispconninfo.path[i].ext_encoder_objid));
+
+		info->ext_disp_conn_info.path[i].device_tag =
+			le16_to_cpu(
+				info_v2_1->extdispconninfo.path[i].device_tag);
+		info->ext_disp_conn_info.path[i].device_acpi_enum =
+		le16_to_cpu(
+			info_v2_1->extdispconninfo.path[i].device_acpi_enum);
+		info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
+			info_v2_1->extdispconninfo.path[i].auxddclut_index;
+		info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
+			info_v2_1->extdispconninfo.path[i].hpdlut_index;
+		info->ext_disp_conn_info.path[i].channel_mapping.raw =
+			info_v2_1->extdispconninfo.path[i].channelmapping;
+		info->ext_disp_conn_info.path[i].caps =
+				le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
+	}
+
+	info->ext_disp_conn_info.checksum =
+		info_v2_1->extdispconninfo.checksum;
+	info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr;
+	info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum;
+	for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
+		info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
+				info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+		info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
+				info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+	}
+	info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum;
+	for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
+		info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+				info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+		info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
+				info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
+	}
+	info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr;
+	info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum;
+	for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
+		info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
+				info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+		info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
+				info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+	}
+	info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum;
+	for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
+		info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+				info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+		info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
+				info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
+	}
+	info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr;
+	info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum;
+	for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
+		info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
+				info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+		info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
+				info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+	}
+	info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum;
+	for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
+		info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+				info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+		info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
+				info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
+	}
+	info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr;
+	info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum;
+	for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
+		info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
+				info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
+		info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
+				info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
+	}
+	info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum;
+	for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
+		info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
+				info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
+		info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
+				info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
+	}
+
+	info->edp1_info.edp_backlight_pwm_hz =
+	le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz);
+	info->edp1_info.edp_ss_percentage =
+	le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage);
+	info->edp1_info.edp_ss_rate_10hz =
+	le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz);
+	info->edp1_info.edp_pwr_on_off_delay =
+		info_v2_1->edp1_info.edp_pwr_on_off_delay;
+	info->edp1_info.edp_pwr_on_vary_bl_to_blon =
+		info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon;
+	info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
+		info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
+	info->edp1_info.edp_panel_bpc =
+		info_v2_1->edp1_info.edp_panel_bpc;
+	info->edp1_info.edp_bootup_bl_level =
+
+	info->edp2_info.edp_backlight_pwm_hz =
+	le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz);
+	info->edp2_info.edp_ss_percentage =
+	le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage);
+	info->edp2_info.edp_ss_rate_10hz =
+	le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz);
+	info->edp2_info.edp_pwr_on_off_delay =
+		info_v2_1->edp2_info.edp_pwr_on_off_delay;
+	info->edp2_info.edp_pwr_on_vary_bl_to_blon =
+		info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon;
+	info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
+		info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
+	info->edp2_info.edp_panel_bpc =
+		info_v2_1->edp2_info.edp_panel_bpc;
+	info->edp2_info.edp_bootup_bl_level =
+		info_v2_1->edp2_info.edp_bootup_bl_level;
+
+	return BP_RESULT_OK;
+}
 
 /*
  * construct_integrated_info
@@ -1775,11 +1930,25 @@ static enum bp_result construct_integrated_info(
 
 		get_atom_data_table_revision(header, &revision);
 
-		/* Don't need to check major revision as they are all 1 */
-		switch (revision.minor) {
-		case 11:
-		case 12:
-			result = get_integrated_info_v11(bp, info);
+		switch (revision.major) {
+		case 1:
+			switch (revision.minor) {
+			case 11:
+			case 12:
+				result = get_integrated_info_v11(bp, info);
+				break;
+			default:
+				return result;
+			}
+			break;
+		case 2:
+			switch (revision.minor) {
+			case 1:
+				result = get_integrated_info_v2_1(bp, info);
+				break;
+			default:
+				return result;
+			}
 			break;
 		default:
 			return result;
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 74c498b6774d..7736c92d55c4 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -70,15 +70,12 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
 	case DCN_VERSION_1_01:
 	case DCN_VERSION_2_0:
 	case DCN_VERSION_2_1:
-		*h = dal_cmd_tbl_helper_dce112_get_table2();
-		return true;
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case DCN_VERSION_3_0:
+	case DCN_VERSION_3_01:
+	case DCN_VERSION_3_02:
 		*h = dal_cmd_tbl_helper_dce112_get_table2();
 		return true;
 #endif
-
 	default:
 		/* Unsupported DCE */
 		BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
index bf0affef893f..755b6e33140a 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
@@ -388,43 +388,3 @@ const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table2(void)
 {
 	return &command_table_helper_funcs;
 }
-
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-/* function table */
-static const struct command_table_helper command_table_helper_funcs_dcn2x = {
-	.controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom2,
-	.encoder_action_to_atom = encoder_action_to_atom,
-	.engine_bp_to_atom = engine_bp_to_atom,
-	.clock_source_id_to_atom = clock_source_id_to_atom,
-	.clock_source_id_to_atom_phy_clk_src_id =
-			clock_source_id_to_atom_phy_clk_src_id,
-	.signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
-	.hpd_sel_to_atom = hpd_sel_to_atom,
-	.dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
-	.phy_id_to_atom = phy_id_to_atom,
-	.disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
-	.clock_source_id_to_ref_clk_src = NULL,
-	.transmitter_bp_to_atom = NULL,
-	.encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom2,
-	.encoder_mode_bp_to_atom =
-			dal_cmd_table_helper_encoder_mode_bp_to_atom2,
-	.dc_clock_type_to_atom = dc_clock_type_to_atom,
-	.transmitter_color_depth_to_atom = transmitter_color_depth_to_atom,
-
-};
-
-/*
- * dal_cmd_tbl_helper_dce110_get_table
- *
- * @brief
- * Initialize command table helper functions
- *
- * @param
- * const struct command_table_helper **h - [out] struct of functions
- *
- */
-const struct command_table_helper *dal_cmd_tbl_helper_dcn2_get_table2(void)
-{
-	return &command_table_helper_funcs_dcn2x;
-}
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
index 2d9e9f3c579d..abf28a06f5bc 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
@@ -30,8 +30,5 @@ struct command_table_helper;
 
 /* Initialize command table helper functions */
 const struct command_table_helper *dal_cmd_tbl_helper_dce112_get_table2(void);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-const struct command_table_helper *dal_cmd_tbl_helper_dcn2_get_table2(void);
-#endif
 
 #endif /* __DAL_COMMAND_TABLE_HELPER_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 2c6db379afae..ef41b287cbe2 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -1364,13 +1364,10 @@ static void calculate_bandwidth(
 	/*if stutter and dram clock state change are gated before cursor then the cursor latency hiding does not limit stutter or dram clock state change*/
 	for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 		if (data->enable[i]) {
-			if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1) {
-				data->maximum_latency_hiding[i] = bw_add(data->minimum_latency_hiding[i], bw_mul(bw_frc_to_fixed(5, 10), data->total_dmifmc_urgent_latency));
-			}
-			else {
-				/*maximum_latency_hiding(i) = minimum_latency_hiding(i) + 1 / vsr(i) * h_total(i) / pixel_rate(i) + 0.5 * total_dmifmc_urgent_latency*/
-				data->maximum_latency_hiding[i] = bw_add(data->minimum_latency_hiding[i], bw_mul(bw_frc_to_fixed(5, 10), data->total_dmifmc_urgent_latency));
-			}
+			/*maximum_latency_hiding(i) = minimum_latency_hiding(i) + 1 / vsr(i) **/
+			/*      h_total(i) / pixel_rate(i) + 0.5 * total_dmifmc_urgent_latency*/
+			data->maximum_latency_hiding[i] = bw_add(data->minimum_latency_hiding[i],
+				bw_mul(bw_frc_to_fixed(5, 10), data->total_dmifmc_urgent_latency));
 			data->maximum_latency_hiding_with_cursor[i] = bw_min2(data->maximum_latency_hiding[i], data->cursor_latency_hiding[i]);
 		}
 	}
@@ -1980,7 +1977,7 @@ static void calculate_bandwidth(
 	else {
 		data->latency_for_non_mcifwr_clients = bw_int_to_fixed(0);
 	}
-	/*dmif mc urgent latency suppported in high sclk and yclk*/
+	/*dmif mc urgent latency supported in high sclk and yclk*/
 	data->dmifmc_urgent_latency_supported_in_high_sclk_and_yclk = bw_div((bw_sub(data->min_read_buffer_size_in_time, data->dmif_burst_time[high][s_high])), data->total_dmifmc_urgent_trips);
 	/*dram speed/p-state change margin*/
 	/*in the multi-display case the nb p-state change watermark cannot exceed the average lb size plus the dmif size or the cursor dcp buffer size*/
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 51397b565ddf..d4df4da5b81a 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -381,13 +381,11 @@ static void pipe_ctx_to_e2e_pipe_params (
 		input->src.viewport_width_c    = input->src.viewport_width;
 		input->src.viewport_height_c   = input->src.viewport_height;
 		break;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 		input->src.source_format = dm_rgbe_alpha;
 		input->src.viewport_width_c    = input->src.viewport_width;
 		input->src.viewport_height_c   = input->src.viewport_height;
 		break;
-#endif
 	default:
 		input->src.source_format = dm_444_32;
 		input->src.viewport_width_c    = input->src.viewport_width;
@@ -736,10 +734,11 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v,
 		hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
 }
 
-unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev, uint32_t pci_revision_id)
+unsigned int get_highest_allowed_voltage_level(uint32_t chip_family, uint32_t hw_internal_rev, uint32_t pci_revision_id)
 {
 	/* for low power RV2 variants, the highest voltage level we want is 0 */
-	if (ASICREV_IS_RAVEN2(hw_internal_rev))
+	if ((chip_family == FAMILY_RV) &&
+	     ASICREV_IS_RAVEN2(hw_internal_rev))
 		switch (pci_revision_id) {
 		case PRID_DALI_DE:
 		case PRID_DALI_DF:
@@ -1324,6 +1323,7 @@ bool dcn_validate_bandwidth(
 	BW_VAL_TRACE_FINISH();
 
 	if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(
+							dc->ctx->asic_id.chip_family,
 							dc->ctx->asic_id.hw_internal_rev,
 							dc->ctx->asic_id.pci_revision_id))
 		return true;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 1a495759a034..d59b380e7b7f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -114,14 +114,46 @@ endif
 AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)
-endif
-ifdef CONFIG_DRM_AMD_DC_DCN3_0
 ###############################################################################
 # DCN30
 ###############################################################################
 CLK_MGR_DCN30 = dcn30_clk_mgr.o dcn30_clk_mgr_smu_msg.o
 
+# prevent build errors regarding soft-float vs hard-float FP ABI tags
+# this code is currently unused on ppc64, as it applies to VanGogh APUs only
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn30/dcn30_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)
+endif
+
+# prevent build errors:
+# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types
+# this file is unused on arm64, just like on ppc64
+ifdef CONFIG_ARM64
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/clk_mgr/dcn30/dcn30_clk_mgr.o := -mgeneral-regs-only
+endif
+
 AMD_DAL_CLK_MGR_DCN30 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn30/,$(CLK_MGR_DCN30))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)
+###############################################################################
+# DCN301
+###############################################################################
+CLK_MGR_DCN301 = vg_clk_mgr.o dcn301_smu.o
+
+# prevent build errors regarding soft-float vs hard-float FP ABI tags
+# this code is currently unused on ppc64, as it applies to VanGogh APUs only
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn301/vg_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)
+endif
+
+# prevent build errors:
+# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types
+# this file is unused on arm64, just like on ppc64
+ifdef CONFIG_ARM64
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/clk_mgr/dcn301/vg_clk_mgr.o := -mgeneral-regs-only
+endif
+
+AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)
 endif
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index efb909ef7a0f..73c91027572b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -39,9 +39,8 @@
 #include "dcn10/rv2_clk_mgr.h"
 #include "dcn20/dcn20_clk_mgr.h"
 #include "dcn21/rn_clk_mgr.h"
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #include "dcn30/dcn30_clk_mgr.h"
-#endif
+#include "dcn301/vg_clk_mgr.h"
 
 
 int clk_mgr_helper_get_active_display_cnt(
@@ -166,6 +165,11 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
 			rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 			break;
 		}
+
+		if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
+			rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+			break;
+		}
 		if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
 			rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
 			break;
@@ -178,16 +182,22 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
 		break;
 
 	case FAMILY_NV:
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 		if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) {
 			dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 			break;
 		}
-#endif
+		if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) {
+			dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+			break;
+		}
 		dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
 		break;
-#endif	/* Family RV and NV*/
 
+	case FAMILY_VGH:
+		if (ASICREV_IS_VANGOGH(asic_id.hw_internal_rev))
+			vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+		break;
+#endif
 	default:
 		ASSERT(0); /* Unknown Asic */
 		break;
@@ -199,14 +209,22 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
 {
 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 
+#ifdef CONFIG_DRM_AMD_DC_DCN
 	switch (clk_mgr_base->ctx->asic_id.chip_family) {
 	case FAMILY_NV:
 		if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
 			dcn3_clk_mgr_destroy(clk_mgr);
-			break;
 		}
+		break;
+
+	case FAMILY_VGH:
+		if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev))
+			vg_clk_mgr_destroy(clk_mgr);
+		break;
+
+	default:
+		break;
 	}
 #endif
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index b1e657e137a9..78df96882d6e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -195,7 +195,8 @@ void dce11_pplib_apply_display_requirements(
 	 * , then change minimum memory clock based on real-time bandwidth
 	 * limitation.
 	 */
-	if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
+	if ((dc->ctx->asic_id.chip_family == FAMILY_AI) &&
+	     ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
 		pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz,
 							   (uint32_t) div64_s64(
 								   div64_s64(dc->bw_vbios->high_yclk.value,
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
index 807dca8f7d7a..934e6423dc1a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
@@ -100,7 +100,9 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
 	/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
 	dce_clk_params.target_clock_frequency = 0;
 	dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
-	if (!ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))
+
+	if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) &&
+	       ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)))
 		dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
 			(dce_clk_params.pll_id ==
 					CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
@@ -176,7 +178,8 @@ int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr)
 	dce_clk_params.target_clock_frequency = 0;
 	dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
 	dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
-	if (!ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev))
+	if (!((clk_mgr->base.ctx->asic_id.chip_family == FAMILY_AI) &&
+	       ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev)))
 		dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
 			(dce_clk_params.pll_id ==
 					CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index e133edc587d3..75b8240ed059 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -187,6 +187,17 @@ static void ramp_up_dispclk_with_dpp(
 	clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
 }
 
+static bool is_mpo_enabled(struct dc_state *context)
+{
+	int i;
+
+	for (i = 0; i < context->stream_count; i++) {
+		if (context->stream_status[i].plane_count > 1)
+			return true;
+	}
+	return false;
+}
+
 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 			struct dc_state *context,
 			bool safe_to_lower)
@@ -284,9 +295,22 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 		if (pp_smu->set_hard_min_fclk_by_freq &&
 				pp_smu->set_hard_min_dcfclk_by_freq &&
 				pp_smu->set_min_deep_sleep_dcfclk) {
-			pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
-			pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
-			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+			// Only increase clocks when display is active and MPO is enabled
+			if (display_count && is_mpo_enabled(context)) {
+				pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
+						((new_clocks->fclk_khz / 1000) *  101) / 100);
+				pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
+						((new_clocks->dcfclk_khz / 1000) * 101) / 100);
+				pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
+						(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+			} else {
+				pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
+						new_clocks->fclk_khz / 1000);
+				pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
+						new_clocks->dcfclk_khz / 1000);
+				pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
+						(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
+			}
 		}
 	}
 }
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 2f8fee05547a..c42d2f4e81e8 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -124,7 +124,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
 	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
 	 * also if safe to lower is false, we just go in the higher state
 	 */
-	if (safe_to_lower) {
+	if (safe_to_lower && !dc->debug.disable_48mhz_pwrdwn) {
 		/* check that we're not already in lower */
 		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h
index 5ed03287aaaf..fa09c594fd36 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dalsmc.h
@@ -53,6 +53,7 @@
 #define DALSMC_MSG_GetDcModeMaxDpmFreq            0xC
 #define DALSMC_MSG_SetMinDeepSleepDcefclk         0xD
 #define DALSMC_MSG_NumOfDisplays                  0xE
+#define DALSMC_MSG_SetDisplayRefreshFromMall      0xF
 #define DALSMC_MSG_SetExternalClientDfCstateAllow 0x10
 #define DALSMC_MSG_BacoAudioD3PME                 0x11
 #define DALSMC_Message_Count                      0x12
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index b0e9b0509568..82cb688ba5e0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -104,7 +104,7 @@ static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk
 	}
 }
 
-static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
+static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
 {
 	/* defaults */
 	double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
@@ -145,6 +145,16 @@ static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
 
+	/* Set D - MALL - SR enter and exit times adjusted for MALL */
+//	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
+//	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us;
+//	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2;
+//	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4;
+//	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
+//	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0;
+//	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
+//	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
+//	clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
 }
 
 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
@@ -201,7 +211,9 @@ void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
 	clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
 
 	/* WM range table */
+	DC_FP_START();
 	dcn3_build_wm_range_table(clk_mgr);
+	DC_FP_END();
 }
 
 static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
index 7ee3ec5a8af8..8ecc708bcd9e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
@@ -297,6 +297,15 @@ void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t nu
 			DALSMC_MSG_NumOfDisplays, num_displays, NULL);
 }
 
+void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale)
+{
+	/* bits 8:7 for cache timer scale, bits 6:1 for cache timer delay, bit 0 = 1 for enable, = 0 for disable */
+	uint32_t param = (cache_timer_scale << 7) | (cache_timer_delay << 1) | (enable ? 1 : 0);
+
+	dcn30_smu_send_msg_with_param(clk_mgr,
+			DALSMC_MSG_SetDisplayRefreshFromMall, param, NULL);
+}
+
 void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable)
 {
 	smu_print("SMU Set external client df cstate allow: enable = %d\n", enable);
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
index 236f20ec90d4..dd2640a3ce5d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h
@@ -70,6 +70,7 @@ typedef enum {
 typedef enum {
 	WATERMARKS_CLOCK_RANGE = 0,
 	WATERMARKS_DUMMY_PSTATE,
+	WATERMARKS_MALL,
 	WATERMARKS_COUNT,
 } WATERMARKS_FLAGS_e;
 
@@ -102,6 +103,7 @@ unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, P
 unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk);
 void         dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz);
 void         dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays);
+void         dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale);
 void         dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable);
 void         dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr);
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
new file mode 100644
index 000000000000..cfa8e02cf103
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "core_types.h"
+#include "clk_mgr_internal.h"
+#include "reg_helper.h"
+#include <linux/delay.h>
+
+#include "dcn301_smu.h"
+
+#include "vangogh_ip_offset.h"
+
+#include "mp/mp_11_5_0_offset.h"
+#include "mp/mp_11_5_0_sh_mask.h"
+
+#define REG(reg_name) \
+	(MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
+
+#define FN(reg_name, field) \
+	FD(reg_name##__##field)
+
+#define VBIOSSMC_MSG_GetSmuVersion                0x2
+#define VBIOSSMC_MSG_SetDispclkFreq               0x4
+#define VBIOSSMC_MSG_SetDprefclkFreq              0x5
+#define VBIOSSMC_MSG_SetDppclkFreq                0x6
+#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq       0x7
+#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk        0x8
+//#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq       0xA
+#define VBIOSSMC_MSG_GetFclkFrequency             0xA
+//#define VBIOSSMC_MSG_SetDisplayCount              0xC
+//#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD
+#define VBIOSSMC_MSG_UpdatePmeRestore			  0xD
+#define VBIOSSMC_MSG_SetVbiosDramAddrHigh         0xE   //Used for WM table txfr
+#define VBIOSSMC_MSG_SetVbiosDramAddrLow          0xF
+#define VBIOSSMC_MSG_TransferTableSmu2Dram        0x10
+#define VBIOSSMC_MSG_TransferTableDram2Smu        0x11
+#define VBIOSSMC_MSG_SetDisplayIdleOptimizations  0x12
+
+#define VBIOSSMC_Status_BUSY                      0x0
+#define VBIOSSMC_Result_OK                        0x1
+#define VBIOSSMC_Result_Failed                    0xFF
+#define VBIOSSMC_Result_UnknownCmd                0xFE
+#define VBIOSSMC_Result_CmdRejectedPrereq         0xFD
+#define VBIOSSMC_Result_CmdRejectedBusy           0xFC
+
+/*
+ * Function to be used instead of REG_WAIT macro because the wait ends when
+ * the register is NOT EQUAL to zero, and because the translation in msg_if.h
+ * won't work with REG_WAIT.
+ */
+static uint32_t dcn301_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
+{
+	uint32_t res_val = VBIOSSMC_Status_BUSY;
+
+	do {
+		res_val = REG_READ(MP1_SMN_C2PMSG_91);
+		if (res_val != VBIOSSMC_Status_BUSY)
+			break;
+
+		if (delay_us >= 1000)
+			msleep(delay_us/1000);
+		else if (delay_us > 0)
+			udelay(delay_us);
+	} while (max_retries--);
+
+	return res_val;
+}
+
+int dcn301_smu_send_msg_with_param(
+		struct clk_mgr_internal *clk_mgr,
+		unsigned int msg_id, unsigned int param)
+{
+	uint32_t result;
+
+	/* First clear response register */
+	REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
+
+	/* Set the parameter register for the SMU message, unit is Mhz */
+	REG_WRITE(MP1_SMN_C2PMSG_83, param);
+
+	/* Trigger the message transaction by writing the message ID */
+	REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
+
+	result = dcn301_smu_wait_for_response(clk_mgr, 10, 1000);
+
+	ASSERT(result == VBIOSSMC_Result_OK);
+
+	/* Actual dispclk set is returned in the parameter register */
+	return REG_READ(MP1_SMN_C2PMSG_83);
+}
+
+int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
+{
+	return dcn301_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_GetSmuVersion,
+			0);
+}
+
+
+int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+{
+	int actual_dispclk_set_mhz = -1;
+
+	/*  Unit of SMU msg parameter is Mhz */
+	actual_dispclk_set_mhz = dcn301_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDispclkFreq,
+			requested_dispclk_khz / 1000);
+
+	return actual_dispclk_set_mhz * 1000;
+}
+
+int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
+{
+	int actual_dprefclk_set_mhz = -1;
+
+	actual_dprefclk_set_mhz = dcn301_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDprefclkFreq,
+			clk_mgr->base.dprefclk_khz / 1000);
+
+	/* TODO: add code for programing DP DTO, currently this is down by command table */
+
+	return actual_dprefclk_set_mhz * 1000;
+}
+
+int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
+{
+	int actual_dcfclk_set_mhz = -1;
+
+	actual_dcfclk_set_mhz = dcn301_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
+			requested_dcfclk_khz / 1000);
+
+	return actual_dcfclk_set_mhz * 1000;
+}
+
+int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
+{
+	int actual_min_ds_dcfclk_mhz = -1;
+
+	actual_min_ds_dcfclk_mhz = dcn301_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
+			requested_min_ds_dcfclk_khz / 1000);
+
+	return actual_min_ds_dcfclk_mhz * 1000;
+}
+
+int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
+{
+	int actual_dppclk_set_mhz = -1;
+
+	actual_dppclk_set_mhz = dcn301_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDppclkFreq,
+			requested_dpp_khz / 1000);
+
+	return actual_dppclk_set_mhz * 1000;
+}
+
+void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
+{
+	//TODO: Work with smu team to define optimization options.
+
+	dcn301_smu_send_msg_with_param(
+		clk_mgr,
+		VBIOSSMC_MSG_SetDisplayIdleOptimizations,
+		idle_info);
+}
+
+void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
+{
+	union display_idle_optimization_u idle_info = { 0 };
+
+	if (enable) {
+		idle_info.idle_info.df_request_disabled = 1;
+		idle_info.idle_info.phy_ref_clk_off = 1;
+	}
+
+	dcn301_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDisplayIdleOptimizations,
+			idle_info.data);
+}
+
+void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
+{
+	dcn301_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_UpdatePmeRestore,
+			0);
+}
+
+void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
+{
+	dcn301_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
+}
+
+void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
+{
+	dcn301_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
+}
+
+void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
+{
+	dcn301_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
+}
+
+void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
+{
+	dcn301_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h
new file mode 100644
index 000000000000..b640df85a17f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DAL_DC_301_SMU_H_
+#define DAL_DC_301_SMU_H_
+
+#define SMU13_DRIVER_IF_VERSION 2
+
+typedef struct {
+	uint32_t fclk;
+	uint32_t memclk;
+	uint32_t voltage;
+} df_pstate_t;
+
+typedef struct {
+	uint32_t vclk;
+	uint32_t dclk;
+} vcn_clk_t;
+
+typedef enum {
+	DSPCLK_DCFCLK = 0,
+	DSPCLK_DISPCLK,
+	DSPCLK_PIXCLK,
+	DSPCLK_PHYCLK,
+	DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+	uint16_t Freq; // in MHz
+	uint16_t Vid;  // min voltage in SVI2 VID
+} DisplayClockTable_t;
+
+typedef struct {
+	uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
+	uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
+	uint16_t MinMclk;
+	uint16_t MaxMclk;
+
+	uint8_t  WmSetting;
+	uint8_t  WmType;  // Used for normal pstate change or memory retraining
+	uint8_t  Padding[2];
+} WatermarkRowGeneric_t;
+
+
+#define NUM_WM_RANGES 4
+
+typedef enum {
+	WM_SOCCLK = 0,
+	WM_DCFCLK,
+	WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+  // Watermarks
+	WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+	uint32_t     MmHubPadding[7]; // SMU internal use
+} Watermarks_t;
+
+
+#define TABLE_WATERMARKS         1
+#define TABLE_DPMCLOCKS          4 // Called by Driver
+
+
+#define VG_NUM_DCFCLK_DPM_LEVELS   7
+#define VG_NUM_DISPCLK_DPM_LEVELS  7
+#define VG_NUM_DPPCLK_DPM_LEVELS   7
+#define VG_NUM_SOCCLK_DPM_LEVELS   7
+#define VG_NUM_ISPICLK_DPM_LEVELS  7
+#define VG_NUM_ISPXCLK_DPM_LEVELS  7
+#define VG_NUM_VCN_DPM_LEVELS      5
+#define VG_NUM_FCLK_DPM_LEVELS     4
+#define VG_NUM_SOC_VOLTAGE_LEVELS  8
+
+// copy from vgh/vangogh/pmfw_driver_if.h
+struct vg_dpm_clocks {
+	uint32_t DcfClocks[VG_NUM_DCFCLK_DPM_LEVELS];
+	uint32_t DispClocks[VG_NUM_DISPCLK_DPM_LEVELS];
+	uint32_t DppClocks[VG_NUM_DPPCLK_DPM_LEVELS];
+	uint32_t SocClocks[VG_NUM_SOCCLK_DPM_LEVELS];
+	uint32_t IspiClocks[VG_NUM_ISPICLK_DPM_LEVELS];
+	uint32_t IspxClocks[VG_NUM_ISPXCLK_DPM_LEVELS];
+	vcn_clk_t VcnClocks[VG_NUM_VCN_DPM_LEVELS];
+
+	uint32_t SocVoltage[VG_NUM_SOC_VOLTAGE_LEVELS];
+
+	df_pstate_t DfPstateTable[VG_NUM_FCLK_DPM_LEVELS];
+
+	uint32_t MinGfxClk;
+	uint32_t MaxGfxClk;
+
+	uint8_t NumDfPstatesEnabled;
+	uint8_t NumDcfclkLevelsEnabled;
+	uint8_t NumDispClkLevelsEnabled;  //applies to both dispclk and dppclk
+	uint8_t NumSocClkLevelsEnabled;
+
+	uint8_t IspClkLevelsEnabled;  //applies to both ispiclk and ispxclk
+	uint8_t VcnClkLevelsEnabled;  //applies to both vclk/dclk
+	uint8_t spare[2];
+};
+
+struct smu_dpm_clks {
+	struct vg_dpm_clocks *dpm_clks;
+	union large_integer mc_address;
+};
+
+struct watermarks {
+  // Watermarks
+	WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+	uint32_t     MmHubPadding[7]; // SMU internal use
+};
+
+
+struct display_idle_optimization {
+	unsigned int df_request_disabled : 1;
+	unsigned int phy_ref_clk_off     : 1;
+	unsigned int s0i2_rdy            : 1;
+	unsigned int reserved            : 29;
+};
+
+union display_idle_optimization_u {
+	struct display_idle_optimization idle_info;
+	uint32_t data;
+};
+
+
+int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
+int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
+int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
+int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
+int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
+int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
+void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
+void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
+void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
+void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
+void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
+void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
+void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
+
+#endif /* DAL_DC_301_SMU_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
new file mode 100644
index 000000000000..98cbb0ac095c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -0,0 +1,834 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dccg.h"
+#include "clk_mgr_internal.h"
+
+// For dce12_get_dp_ref_freq_khz
+#include "dce100/dce_clk_mgr.h"
+
+// For dcn20_update_clocks_update_dpp_dto
+#include "dcn20/dcn20_clk_mgr.h"
+
+#include "vg_clk_mgr.h"
+
+#include "dcn301_smu.h"
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dm_helpers.h"
+
+#include "atomfirmware.h"
+#include "vangogh_ip_offset.h"
+#include "clk/clk_11_5_0_offset.h"
+#include "clk/clk_11_5_0_sh_mask.h"
+
+/* Constants */
+
+#define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
+
+/* Macros */
+
+#define REG(reg_name) \
+	(CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
+
+/* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
+int vg_get_active_display_cnt_wa(
+		struct dc *dc,
+		struct dc_state *context)
+{
+	int i, display_count;
+	bool tmds_present = false;
+
+	display_count = 0;
+	for (i = 0; i < context->stream_count; i++) {
+		const struct dc_stream_state *stream = context->streams[i];
+
+		if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
+				stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
+				stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
+			tmds_present = true;
+	}
+
+	for (i = 0; i < dc->link_count; i++) {
+		const struct dc_link *link = dc->links[i];
+
+		/*
+		 * Only notify active stream or virtual stream.
+		 * Need to notify virtual stream to work around
+		 * headless case. HPD does not fire when system is in
+		 * S0i2.
+		 */
+		/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
+		if (link->connector_signal == SIGNAL_TYPE_VIRTUAL ||
+				link->link_enc->funcs->is_dig_enabled(link->link_enc))
+			display_count++;
+	}
+
+	/* WA for hang on HDMI after display off back back on*/
+	if (display_count == 0 && tmds_present)
+		display_count = 1;
+
+	return display_count;
+}
+
+void vg_update_clocks(struct clk_mgr *clk_mgr_base,
+			struct dc_state *context,
+			bool safe_to_lower)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
+	struct dc *dc = clk_mgr_base->ctx->dc;
+	int display_count;
+	bool update_dppclk = false;
+	bool update_dispclk = false;
+	bool dpp_clock_lowered = false;
+
+	if (dc->work_arounds.skip_clock_update)
+		return;
+
+	/*
+	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
+	 * also if safe to lower is false, we just go in the higher state
+	 */
+	if (safe_to_lower) {
+		/* check that we're not already in lower */
+		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
+
+			display_count = vg_get_active_display_cnt_wa(dc, context);
+			/* if we can go lower, go lower */
+			if (display_count == 0) {
+				union display_idle_optimization_u idle_info = { 0 };
+
+				idle_info.idle_info.df_request_disabled = 1;
+				idle_info.idle_info.phy_ref_clk_off = 1;
+
+				dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
+				/* update power state */
+				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
+			}
+		}
+	} else {
+		/* check that we're not already in D0 */
+		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
+			union display_idle_optimization_u idle_info = { 0 };
+
+			dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
+			/* update power state */
+			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
+		}
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
+		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
+		dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
+	}
+
+	if (should_set_clock(safe_to_lower,
+			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
+		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
+		dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
+	}
+
+	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
+	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+		if (new_clocks->dppclk_khz < 100000)
+			new_clocks->dppclk_khz = 100000;
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
+		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
+			dpp_clock_lowered = true;
+		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
+		update_dppclk = true;
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
+		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
+		dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
+
+		update_dispclk = true;
+	}
+
+	if (dpp_clock_lowered) {
+		// increase per DPP DTO before lowering global dppclk
+		dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+		dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+	} else {
+		// increase global DPPCLK before lowering per DPP DTO
+		if (update_dppclk || update_dispclk)
+			dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+		// always update dtos unless clock is lowered and not safe to lower
+		if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
+			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
+	}
+}
+
+
+static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
+{
+	/* get FbMult value */
+	struct fixed31_32 pll_req;
+	unsigned int fbmult_frac_val = 0;
+	unsigned int fbmult_int_val = 0;
+
+
+	/*
+	 * Register value of fbmult is in 8.16 format, we are converting to 31.32
+	 * to leverage the fix point operations available in driver
+	 */
+
+	REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
+	REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
+
+	pll_req = dc_fixpt_from_int(fbmult_int_val);
+
+	/*
+	 * since fractional part is only 16 bit in register definition but is 32 bit
+	 * in our fix point definiton, need to shift left by 16 to obtain correct value
+	 */
+	pll_req.value |= fbmult_frac_val << 16;
+
+	/* multiply by REFCLK period */
+	pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
+
+	/* integer part is now VCO frequency in kHz */
+	return dc_fixpt_floor(pll_req);
+}
+
+static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+	internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT);
+	internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL);
+
+	internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL);	//dcf deep sleep divider
+	internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS);
+
+	internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT);
+	internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL);
+
+	internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT);
+	internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL);
+
+	internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT);
+	internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK0_BYPASS_CNTL);
+}
+
+/* This function collect raw clk register values */
+static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
+		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
+{
+	struct dcn301_clk_internal internal = {0};
+	char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
+	unsigned int chars_printed = 0;
+	unsigned int remaining_buffer = log_info->bufSize;
+
+	vg_dump_clk_registers_internal(&internal, clk_mgr_base);
+
+	regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
+	regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
+	regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
+	regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
+	regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
+	regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
+
+	regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
+	if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
+		regs_and_bypass->dppclk_bypass = 0;
+	regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
+	if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
+		regs_and_bypass->dcfclk_bypass = 0;
+	regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
+	if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
+		regs_and_bypass->dispclk_bypass = 0;
+	regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
+	if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
+		regs_and_bypass->dprefclk_bypass = 0;
+
+	if (log_info->enabled) {
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
+			regs_and_bypass->dcfclk,
+			regs_and_bypass->dcf_deep_sleep_divider,
+			regs_and_bypass->dcf_deep_sleep_allow,
+			bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
+			regs_and_bypass->dprefclk,
+			bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
+			regs_and_bypass->dispclk,
+			bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		//split
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		// REGISTER VALUES
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
+				internal.CLK1_CLK3_CURRENT_CNT);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
+					internal.CLK1_CLK3_DS_CNTL);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
+					internal.CLK1_CLK3_ALLOW_DS);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
+					internal.CLK1_CLK2_CURRENT_CNT);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
+					internal.CLK1_CLK0_CURRENT_CNT);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
+					internal.CLK1_CLK1_CURRENT_CNT);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
+					internal.CLK1_CLK3_BYPASS_CNTL);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
+					internal.CLK1_CLK2_BYPASS_CNTL);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
+					internal.CLK1_CLK0_BYPASS_CNTL);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+
+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
+					internal.CLK1_CLK1_BYPASS_CNTL);
+		remaining_buffer -= chars_printed;
+		*log_info->sum_chars_printed += chars_printed;
+		log_info->pBuf += chars_printed;
+	}
+}
+
+/* This function produce translated logical clk state values*/
+void vg_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
+{
+
+	struct clk_state_registers_and_bypass sb = { 0 };
+	struct clk_log_info log_info = { 0 };
+
+	vg_dump_clk_registers(&sb, clk_mgr_base, &log_info);
+
+	s->dprefclk_khz = sb.dprefclk * 1000;
+}
+
+void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+	dcn301_smu_enable_pme_wa(clk_mgr);
+}
+
+void vg_init_clocks(struct clk_mgr *clk_mgr)
+{
+	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
+	// Assumption is that boot state always supports pstate
+	clk_mgr->clks.p_state_change_support = true;
+	clk_mgr->clks.prev_p_state_change_support = true;
+	clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
+}
+
+static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table)
+{
+	int i, num_valid_sets;
+
+	num_valid_sets = 0;
+
+	for (i = 0; i < WM_SET_COUNT; i++) {
+		/* skip empty entries, the smu array has no holes*/
+		if (!bw_params->wm_table.entries[i].valid)
+			continue;
+
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+		/* We will not select WM based on fclk, so leave it as unconstrained */
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
+
+		if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
+			if (i == 0)
+				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
+			else {
+				/* add 1 to make it non-overlapping with next lvl */
+				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
+						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+			}
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
+					bw_params->clk_table.entries[i].dcfclk_mhz;
+
+		} else {
+			/* unconstrained for memory retraining */
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
+
+			/* Modify previous watermark range to cover up to max */
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
+		}
+		num_valid_sets++;
+	}
+
+	ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
+
+	/* modify the min and max to make sure we cover the whole range*/
+	table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
+	table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
+	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
+	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
+
+	/* This is for writeback only, does not matter currently as no writeback support*/
+	table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
+	table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
+	table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
+	table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
+	table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
+}
+
+
+void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct watermarks *table = clk_mgr_base->smu_wm_set.wm_set;
+
+	if (!clk_mgr->smu_ver)
+		return;
+
+	if (!table || clk_mgr_base->smu_wm_set.mc_address.quad_part == 0)
+		return;
+
+	memset(table, 0, sizeof(*table));
+
+	vg_build_watermark_ranges(clk_mgr_base->bw_params, table);
+
+	dcn301_smu_set_dram_addr_high(clk_mgr,
+			clk_mgr_base->smu_wm_set.mc_address.high_part);
+	dcn301_smu_set_dram_addr_low(clk_mgr,
+			clk_mgr_base->smu_wm_set.mc_address.low_part);
+	dcn301_smu_transfer_wm_table_dram_2_smu(clk_mgr);
+}
+
+static bool vg_are_clock_states_equal(struct dc_clocks *a,
+		struct dc_clocks *b)
+{
+	if (a->dispclk_khz != b->dispclk_khz)
+		return false;
+	else if (a->dppclk_khz != b->dppclk_khz)
+		return false;
+	else if (a->dcfclk_khz != b->dcfclk_khz)
+		return false;
+	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
+		return false;
+
+	return true;
+}
+
+
+static struct clk_mgr_funcs vg_funcs = {
+	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+	.update_clocks = vg_update_clocks,
+	.init_clocks = vg_init_clocks,
+	.enable_pme_wa = vg_enable_pme_wa,
+	.are_clock_states_equal = vg_are_clock_states_equal,
+	.notify_wm_ranges = vg_notify_wm_ranges
+};
+
+static struct clk_bw_params vg_bw_params = {
+	.vram_type = Ddr4MemType,
+	.num_channels = 1,
+	.clk_table = {
+		.entries = {
+			{
+				.voltage = 0,
+				.dcfclk_mhz = 400,
+				.fclk_mhz = 400,
+				.memclk_mhz = 800,
+				.socclk_mhz = 0,
+			},
+			{
+				.voltage = 0,
+				.dcfclk_mhz = 483,
+				.fclk_mhz = 800,
+				.memclk_mhz = 1600,
+				.socclk_mhz = 0,
+			},
+			{
+				.voltage = 0,
+				.dcfclk_mhz = 602,
+				.fclk_mhz = 1067,
+				.memclk_mhz = 1067,
+				.socclk_mhz = 0,
+			},
+			{
+				.voltage = 0,
+				.dcfclk_mhz = 738,
+				.fclk_mhz = 1333,
+				.memclk_mhz = 1600,
+				.socclk_mhz = 0,
+			},
+		},
+
+		.num_entries = 4,
+	},
+
+};
+
+static struct wm_table ddr4_wm_table = {
+	.entries = {
+		{
+			.wm_inst = WM_A,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 6.09,
+			.sr_enter_plus_exit_time_us = 7.14,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_B,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 10.12,
+			.sr_enter_plus_exit_time_us = 11.48,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_C,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 10.12,
+			.sr_enter_plus_exit_time_us = 11.48,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_D,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 10.12,
+			.sr_enter_plus_exit_time_us = 11.48,
+			.valid = true,
+		},
+	}
+};
+
+static struct wm_table lpddr5_wm_table = {
+	.entries = {
+		{
+			.wm_inst = WM_A,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 5.32,
+			.sr_enter_plus_exit_time_us = 6.38,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_B,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 9.82,
+			.sr_enter_plus_exit_time_us = 11.196,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_C,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 9.89,
+			.sr_enter_plus_exit_time_us = 11.24,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_D,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 9.748,
+			.sr_enter_plus_exit_time_us = 11.102,
+			.valid = true,
+		},
+	}
+};
+
+
+static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks *clock_table,
+		unsigned int voltage)
+{
+	int i;
+
+	for (i = 0; i < VG_NUM_SOC_VOLTAGE_LEVELS; i++) {
+		if (clock_table->SocVoltage[i] == voltage)
+			return clock_table->DcfClocks[i];
+	}
+
+	ASSERT(0);
+	return 0;
+}
+
+static void vg_clk_mgr_helper_populate_bw_params(
+		struct clk_mgr_internal *clk_mgr,
+		struct integrated_info *bios_info,
+		const struct vg_dpm_clocks *clock_table)
+{
+	int i, j;
+	struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
+
+	j = -1;
+
+	ASSERT(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
+
+	/* Find lowest DPM, FCLK is filled in reverse order*/
+
+	for (i = VG_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
+		if (clock_table->DfPstateTable[i].fclk != 0) {
+			j = i;
+			break;
+		}
+	}
+
+	if (j == -1) {
+		/* clock table is all 0s, just use our own hardcode */
+		ASSERT(0);
+		return;
+	}
+
+	bw_params->clk_table.num_entries = j + 1;
+
+	for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
+		bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
+		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
+		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
+		bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage);
+	}
+
+	bw_params->vram_type = bios_info->memory_type;
+	bw_params->num_channels = bios_info->ma_channel_number;
+
+	for (i = 0; i < WM_SET_COUNT; i++) {
+		bw_params->wm_table.entries[i].wm_inst = i;
+
+		if (i >= bw_params->clk_table.num_entries) {
+			bw_params->wm_table.entries[i].valid = false;
+			continue;
+		}
+
+		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
+		bw_params->wm_table.entries[i].valid = true;
+	}
+
+	if (bw_params->vram_type == LpDdr4MemType) {
+		/*
+		 * WM set D will be re-purposed for memory retraining
+		 */
+		bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
+		bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
+		bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
+		bw_params->wm_table.entries[WM_D].valid = true;
+	}
+
+}
+
+/* Temporary Place holder until we can get them from fuse */
+static struct vg_dpm_clocks dummy_clocks = {
+		.DcfClocks = { 201, 403, 403, 403, 403, 403, 403 },
+		.SocClocks = { 400, 600, 600, 600, 600, 600, 600 },
+		.SocVoltage = { 2800, 2860, 2860, 2860, 2860, 2860, 2860, 2860 },
+		.DfPstateTable = {
+				{ .fclk = 400,  .memclk = 400, .voltage = 2800 },
+				{ .fclk = 400,  .memclk = 400, .voltage = 2800 },
+				{ .fclk = 400,  .memclk = 400, .voltage = 2800 },
+				{ .fclk = 400,  .memclk = 400, .voltage = 2800 }
+		}
+};
+
+static struct watermarks dummy_wms = { 0 };
+
+static void vg_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
+		struct smu_dpm_clks *smu_dpm_clks)
+{
+	struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks;
+
+	if (!clk_mgr->smu_ver)
+		return;
+
+	if (!table || smu_dpm_clks->mc_address.quad_part == 0)
+		return;
+
+	memset(table, 0, sizeof(*table));
+
+	dcn301_smu_set_dram_addr_high(clk_mgr,
+			smu_dpm_clks->mc_address.high_part);
+	dcn301_smu_set_dram_addr_low(clk_mgr,
+			smu_dpm_clks->mc_address.low_part);
+	dcn301_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
+}
+
+void vg_clk_mgr_construct(
+		struct dc_context *ctx,
+		struct clk_mgr_internal *clk_mgr,
+		struct pp_smu_funcs *pp_smu,
+		struct dccg *dccg)
+{
+	struct smu_dpm_clks smu_dpm_clks = { 0 };
+
+	clk_mgr->base.ctx = ctx;
+	clk_mgr->base.funcs = &vg_funcs;
+
+	clk_mgr->pp_smu = pp_smu;
+
+	clk_mgr->dccg = dccg;
+	clk_mgr->dfs_bypass_disp_clk = 0;
+
+	clk_mgr->dprefclk_ss_percentage = 0;
+	clk_mgr->dprefclk_ss_divider = 1000;
+	clk_mgr->ss_on_dprefclk = false;
+	clk_mgr->dfs_ref_freq_khz = 48000;
+
+	clk_mgr->base.smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem(
+				clk_mgr->base.ctx,
+				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				sizeof(struct watermarks),
+				&clk_mgr->base.smu_wm_set.mc_address.quad_part);
+
+	if (clk_mgr->base.smu_wm_set.wm_set == 0) {
+		clk_mgr->base.smu_wm_set.wm_set = &dummy_wms;
+		clk_mgr->base.smu_wm_set.mc_address.quad_part = 0;
+	}
+	ASSERT(clk_mgr->base.smu_wm_set.wm_set);
+
+	smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem(
+				clk_mgr->base.ctx,
+				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				sizeof(struct vg_dpm_clocks),
+				&smu_dpm_clks.mc_address.quad_part);
+
+	if (smu_dpm_clks.dpm_clks == NULL) {
+		smu_dpm_clks.dpm_clks = &dummy_clocks;
+		smu_dpm_clks.mc_address.quad_part = 0;
+	}
+
+	ASSERT(smu_dpm_clks.dpm_clks);
+
+	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+		vg_funcs.update_clocks = dcn2_update_clocks_fpga;
+		clk_mgr->base.dentist_vco_freq_khz = 3600000;
+	} else {
+		struct clk_log_info log_info = {0};
+
+		clk_mgr->smu_ver = dcn301_smu_get_smu_version(clk_mgr);
+
+		if (clk_mgr->smu_ver)
+			clk_mgr->smu_present = true;
+
+		/* TODO: Check we get what we expect during bringup */
+		clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
+
+		/* in case we don't get a value from the register, use default */
+		if (clk_mgr->base.dentist_vco_freq_khz == 0)
+			clk_mgr->base.dentist_vco_freq_khz = 3600000;
+
+		if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
+			vg_bw_params.wm_table = lpddr5_wm_table;
+		} else {
+			vg_bw_params.wm_table = ddr4_wm_table;
+		}
+		/* Saved clocks configured at boot for debug purposes */
+		vg_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
+	}
+
+	clk_mgr->base.dprefclk_khz = 600000;
+	dce_clock_read_ss_info(clk_mgr);
+
+	clk_mgr->base.bw_params = &vg_bw_params;
+
+	vg_get_dpm_table_from_smu(clk_mgr, &smu_dpm_clks);
+	if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
+		vg_clk_mgr_helper_populate_bw_params(
+				clk_mgr,
+				ctx->dc_bios->integrated_info,
+				smu_dpm_clks.dpm_clks);
+	}
+
+	if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
+		dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				smu_dpm_clks.dpm_clks);
+/*
+	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver) {
+		 enable powerfeatures when displaycount goes to 0
+		dcn301_smu_enable_phy_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
+	}
+*/
+}
+
+void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
+{
+	if (clk_mgr->base.smu_wm_set.wm_set && clk_mgr->base.smu_wm_set.mc_address.quad_part != 0)
+		dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				clk_mgr->base.smu_wm_set.wm_set);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h
new file mode 100644
index 000000000000..80497df20ba7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __VG_CLK_MGR_H__
+#define __VG_CLK_MGR_H__
+
+int vg_get_active_display_cnt_wa(
+		struct dc *dc,
+		struct dc_state *context);
+
+void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base);
+
+void vg_clk_mgr_construct(struct dc_context *ctx,
+		struct clk_mgr_internal *clk_mgr,
+		struct pp_smu_funcs *pp_smu,
+		struct dccg *dccg);
+
+void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
+
+void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base);
+#endif //__VG_CLK_MGR_H__
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 45ad05f6e03b..5951f7d4022f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -70,6 +70,8 @@
 
 #include "dce/dmub_hw_lock_mgr.h"
 
+#include "dc_trace.h"
+
 #define CTX \
 	dc->ctx
 
@@ -344,7 +346,7 @@ bool dc_stream_get_crtc_position(struct dc *dc,
  * calculate the crc.
  */
 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
-			     bool enable, bool continuous)
+			     struct crc_params *crc_window, bool enable, bool continuous)
 {
 	int i;
 	struct pipe_ctx *pipe;
@@ -360,7 +362,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 	if (i == MAX_PIPES)
 		return false;
 
-	/* Always capture the full frame */
+	/* By default, capture the full frame */
 	param.windowa_x_start = 0;
 	param.windowa_y_start = 0;
 	param.windowa_x_end = pipe->stream->timing.h_addressable;
@@ -370,6 +372,17 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 	param.windowb_x_end = pipe->stream->timing.h_addressable;
 	param.windowb_y_end = pipe->stream->timing.v_addressable;
 
+	if (crc_window) {
+		param.windowa_x_start = crc_window->windowa_x_start;
+		param.windowa_y_start = crc_window->windowa_y_start;
+		param.windowa_x_end = crc_window->windowa_x_end;
+		param.windowa_y_end = crc_window->windowa_y_end;
+		param.windowb_x_start = crc_window->windowb_x_start;
+		param.windowb_y_start = crc_window->windowb_y_start;
+		param.windowb_x_end = crc_window->windowb_x_end;
+		param.windowb_y_end = crc_window->windowb_y_end;
+	}
+
 	param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 	param.odm_mode = pipe->next_odm_pipe ? 1:0;
 
@@ -731,7 +744,7 @@ static bool dc_construct(struct dc *dc,
 	dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 	if (!dc->clk_mgr)
 		goto fail;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+#ifdef CONFIG_DRM_AMD_DC_DCN
 	dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
 #endif
 
@@ -763,7 +776,7 @@ fail:
 	return false;
 }
 
-static bool disable_all_writeback_pipes_for_stream(
+static void disable_all_writeback_pipes_for_stream(
 		const struct dc *dc,
 		struct dc_stream_state *stream,
 		struct dc_state *context)
@@ -772,8 +785,6 @@ static bool disable_all_writeback_pipes_for_stream(
 
 	for (i = 0; i < stream->num_wb_info; i++)
 		stream->writeback_info[i].wb_enabled = false;
-
-	return true;
 }
 
 void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream, bool lock)
@@ -861,12 +872,16 @@ static void disable_vbios_mode_if_required(
 		if (stream == NULL)
 			continue;
 
+		// only looking for first odm pipe
+		if (pipe->prev_odm_pipe)
+			continue;
+
 		if (stream->link->local_sink &&
 			stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
 			link = stream->link;
 		}
 
-		if (link != NULL) {
+		if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
 			unsigned int enc_inst, tg_inst = 0;
 			unsigned int pix_clk_100hz;
 
@@ -1266,16 +1281,19 @@ bool dc_validate_seamless_boot_timing(const struct dc *dc,
 			return false;
 	}
 
+	if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
+		return false;
+	}
+
 	return true;
 }
 
-bool dc_enable_stereo(
+void dc_enable_stereo(
 	struct dc *dc,
 	struct dc_state *context,
 	struct dc_stream_state *streams[],
 	uint8_t stream_count)
 {
-	bool ret = true;
 	int i, j;
 	struct pipe_ctx *pipe;
 
@@ -1290,8 +1308,6 @@ bool dc_enable_stereo(
 				dc->hwss.setup_stereo(pipe, dc);
 		}
 	}
-
-	return ret;
 }
 
 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
@@ -1327,7 +1343,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 	int i, k, l;
 	struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	dc_allow_idle_optimizations(dc, false);
 #endif
 
@@ -1434,6 +1450,11 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 		dc->hwss.optimize_bandwidth(dc, context);
 	}
 
+	if (dc->ctx->dce_version >= DCE_VERSION_MAX)
+		TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
+	else
+		TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
+
 	context->stream_mask = get_stream_mask(dc, context);
 
 	if (context->stream_mask != dc->current_state->stream_mask)
@@ -1473,7 +1494,7 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context)
 	return (result == DC_OK);
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 bool dc_acquire_release_mpc_3dlut(
 		struct dc *dc, bool acquire,
 		struct dc_stream_state *stream,
@@ -1530,18 +1551,18 @@ static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
 	return false;
 }
 
-bool dc_post_update_surfaces_to_stream(struct dc *dc)
+void dc_post_update_surfaces_to_stream(struct dc *dc)
 {
 	int i;
 	struct dc_state *context = dc->current_state;
 
 	if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0)
-		return true;
+		return;
 
 	post_surface_trace(dc);
 
 	if (is_flip_pending_in_pipes(dc, context))
-		return true;
+		return;
 
 	for (i = 0; i < dc->res_pool->pipe_count; i++)
 		if (context->res_ctx.pipe_ctx[i].stream == NULL ||
@@ -1554,8 +1575,6 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 
 	dc->optimized_required = false;
 	dc->wm_optimized_required = false;
-
-	return true;
 }
 
 static void init_state(struct dc *dc, struct dc_state *context)
@@ -1929,7 +1948,7 @@ static enum surface_update_type check_update_surfaces_for_stream(
 	int i;
 	enum surface_update_type overall_type = UPDATE_TYPE_FAST;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	if (dc->idle_optimizations_allowed)
 		overall_type = UPDATE_TYPE_FULL;
 
@@ -2383,7 +2402,6 @@ static void commit_planes_for_stream(struct dc *dc,
 		enum surface_update_type update_type,
 		struct dc_state *context)
 {
-	bool mpcc_disconnected = false;
 	int i, j;
 	struct pipe_ctx *top_pipe_to_program = NULL;
 
@@ -2404,7 +2422,7 @@ static void commit_planes_for_stream(struct dc *dc,
 	}
 
 	if (update_type == UPDATE_TYPE_FULL) {
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 		dc_allow_idle_optimizations(dc, false);
 
 #endif
@@ -2414,15 +2432,6 @@ static void commit_planes_for_stream(struct dc *dc,
 		context_clock_trace(dc, context);
 	}
 
-	if (update_type != UPDATE_TYPE_FAST && dc->hwss.interdependent_update_lock &&
-		dc->hwss.disconnect_pipes && dc->hwss.wait_for_pending_cleared){
-		dc->hwss.interdependent_update_lock(dc, context, true);
-		mpcc_disconnected = dc->hwss.disconnect_pipes(dc, context);
-		dc->hwss.interdependent_update_lock(dc, context, false);
-		if (mpcc_disconnected)
-			dc->hwss.wait_for_pending_cleared(dc, context);
-	}
-
 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
 
@@ -2461,7 +2470,6 @@ static void commit_planes_for_stream(struct dc *dc,
 		 */
 		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
 
-
 	// Stream updates
 	if (stream_update)
 		commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
@@ -2641,9 +2649,8 @@ static void commit_planes_for_stream(struct dc *dc,
 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
 
-		if (pipe_ctx->bottom_pipe ||
-				!pipe_ctx->stream ||
-				pipe_ctx->stream != stream ||
+		if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
+				!pipe_ctx->stream || pipe_ctx->stream != stream ||
 				!pipe_ctx->plane_state->update_flags.bits.addr_update)
 			continue;
 
@@ -2724,6 +2731,8 @@ void dc_commit_updates_for_stream(struct dc *dc,
 		}
 	}
 
+	TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
+
 	commit_planes_for_stream(
 				dc,
 				srf_updates,
@@ -2748,9 +2757,15 @@ void dc_commit_updates_for_stream(struct dc *dc,
 		}
 	}
 	/*let's use current_state to update watermark etc*/
-	if (update_type >= UPDATE_TYPE_FULL)
+	if (update_type >= UPDATE_TYPE_FULL) {
 		dc_post_update_surfaces_to_stream(dc);
 
+		if (dc_ctx->dce_version >= DCE_VERSION_MAX)
+			TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
+		else
+			TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
+	}
+
 	return;
 
 }
@@ -3052,7 +3067,7 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable)
 	return true;
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 
 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
 {
@@ -3104,4 +3119,11 @@ bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc,
 {
 	return false;
 }
+
+/* cleanup on driver unload */
+void dc_hardware_release(struct dc *dc)
+{
+	if (dc->hwss.hardware_release)
+		dc->hwss.hardware_release(dc);
+}
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 87d89449b9af..21be2a684393 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -418,6 +418,10 @@ char *dc_status_to_str(enum dc_status status)
 		return "Fail clk below minimum";
 	case DC_FAIL_CLK_BELOW_CFG_REQUIRED:
 		return "Fail clk below required CFG (hard_min in PPLIB)";
+	case DC_NOT_SUPPORTED:
+		return "The operation is not supported.";
+	case DC_UNSUPPORTED_VALUE:
+		return "The value specified is not supported.";
 	case DC_ERROR_UNEXPECTED:
 		return "Unexpected error";
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fec87a2e210c..ea9c459c9130 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -854,6 +854,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
 	struct dpcd_caps prev_dpcd_caps;
 	bool same_dpcd = true;
 	enum dc_connection_type new_connection_type = dc_connection_none;
+	enum dc_connection_type pre_connection_type = dc_connection_none;
 	bool perform_dp_seamless_boot = false;
 	const uint32_t post_oui_delay = 30; // 30ms
 
@@ -889,6 +890,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
 
 	link_disconnect_sink(link);
 	if (new_connection_type != dc_connection_none) {
+		pre_connection_type = link->type;
 		link->type = new_connection_type;
 		link->link_state_valid = false;
 
@@ -962,6 +964,12 @@ static bool dc_link_detect_helper(struct dc_link *link,
 				return true;
 			}
 
+			// link switch from MST to non-MST stop topology manager
+			if (pre_connection_type == dc_connection_mst_branch &&
+				link->type != dc_connection_mst_branch) {
+				dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
+			}
+
 			if (link->type == dc_connection_mst_branch) {
 				LINK_INFO("link=%d, mst branch is now Connected\n",
 					  link->link_index);
@@ -2732,7 +2740,8 @@ bool dc_link_setup_psr(struct dc_link *link,
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	/*skip power down the single pipe since it blocks the cstate*/
-	if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
+	if ((link->ctx->asic_id.chip_family == FAMILY_RV) &&
+	     ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
 		psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
 #endif
 
@@ -2943,6 +2952,10 @@ enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
 
 	/* slot X.Y for only current stream */
 	pbn_per_slot = get_pbn_per_slot(stream);
+	if (pbn_per_slot.value == 0) {
+		DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
+		return DC_UNSUPPORTED_VALUE;
+	}
 	pbn = get_pbn_from_timing(pipe_ctx);
 	avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
 
@@ -3106,7 +3119,7 @@ void core_link_enable_stream(
 	struct dc *dc = pipe_ctx->stream->ctx->dc;
 	struct dc_stream_state *stream = pipe_ctx->stream;
 	enum dc_status status;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
 #endif
 	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
@@ -3142,7 +3155,7 @@ void core_link_enable_stream(
 
 	pipe_ctx->stream->link->link_state_valid = true;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
 		pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
 #endif
@@ -3283,8 +3296,9 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
 			dc_is_virtual_signal(pipe_ctx->stream->signal))
 		return;
 
-	if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
-		core_link_set_avmute(pipe_ctx, true);
+	if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
+		if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
+			core_link_set_avmute(pipe_ctx, true);
 	}
 
 #if defined(CONFIG_DRM_AMD_DC_HDCP)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index dec12de37642..54beda4d4e85 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -39,6 +39,7 @@
 
 #define AUX_POWER_UP_WA_DELAY 500
 #define I2C_OVER_AUX_DEFER_WA_DELAY 70
+#define I2C_OVER_AUX_DEFER_WA_DELAY_1MS 1
 
 /* CV smart dongle slave address for retrieving supported HDTV modes*/
 #define CV_SMART_DONGLE_ADDRESS 0x20
@@ -282,11 +283,17 @@ static uint32_t defer_delay_converter_wa(
 	struct dc_link *link = ddc->link;
 
 	if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
-		!memcmp(link->dpcd_caps.branch_dev_name,
-			DP_DVI_CONVERTER_ID_4,
-			sizeof(link->dpcd_caps.branch_dev_name)))
+	    !memcmp(link->dpcd_caps.branch_dev_name,
+		    DP_DVI_CONVERTER_ID_4,
+		    sizeof(link->dpcd_caps.branch_dev_name)))
 		return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
 			defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
+	if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 &&
+	    !memcmp(link->dpcd_caps.branch_dev_name,
+		    DP_DVI_CONVERTER_ID_5,
+		    sizeof(link->dpcd_caps.branch_dev_name)))
+		return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY_1MS ?
+			I2C_OVER_AUX_DEFER_WA_DELAY_1MS : defer_delay;
 
 	return defer_delay;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index ff1e9963ec7a..8a7c4de49a4b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -17,16 +17,16 @@
 
 #define DC_LOGGER \
 	link->ctx->logger
-
+#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
 
 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
 
-/* maximum pre emphasis level allowed for each voltage swing level*/
-static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
-		PRE_EMPHASIS_LEVEL3,
-		PRE_EMPHASIS_LEVEL2,
-		PRE_EMPHASIS_LEVEL1,
-		PRE_EMPHASIS_DISABLED };
+	/* maximum pre emphasis level allowed for each voltage swing level*/
+	static const enum dc_pre_emphasis
+	voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
+					    PRE_EMPHASIS_LEVEL2,
+					    PRE_EMPHASIS_LEVEL1,
+					    PRE_EMPHASIS_DISABLED };
 
 enum {
 	POST_LT_ADJ_REQ_LIMIT = 6,
@@ -183,6 +183,16 @@ static void dpcd_set_link_settings(
 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 			lt_settings->link_settings.use_link_rate_set == true) {
 		rate = 0;
+		/* WA for some MUX chips that will power down with eDP and lose supported
+		 * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
+		 * MUX chip gets link rate set back before link training.
+		 */
+		if (link->connector_signal == SIGNAL_TYPE_EDP) {
+			uint8_t supported_link_rates[16];
+
+			core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
+					supported_link_rates, sizeof(supported_link_rates));
+		}
 		core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 		core_link_write_dpcd(link, DP_LINK_RATE_SET,
 				&lt_settings->link_settings.link_rate_set, 1);
@@ -3848,7 +3858,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
 		if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
 			pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
 				controller_test_pattern, color_depth);
-		else if (opp->funcs->opp_set_disp_pattern_generator) {
+		else if (link->dc->hwss.set_disp_pattern_generator) {
 			struct pipe_ctx *odm_pipe;
 			enum controller_dp_color_space controller_color_space;
 			int opp_cnt = 1;
@@ -3878,26 +3888,29 @@ static void set_crtc_test_pattern(struct dc_link *link,
 			dpg_width = width / opp_cnt;
 			offset = dpg_width;
 
-			opp->funcs->opp_set_disp_pattern_generator(opp,
-				controller_test_pattern,
-				controller_color_space,
-				color_depth,
-				NULL,
-				dpg_width,
-				height,
-				0);
-
-			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
-				struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
-				odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
-				odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
+			link->dc->hwss.set_disp_pattern_generator(link->dc,
+					pipe_ctx,
 					controller_test_pattern,
 					controller_color_space,
 					color_depth,
 					NULL,
 					dpg_width,
 					height,
-					offset);
+					0);
+
+			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
+				struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
+
+				odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
+				link->dc->hwss.set_disp_pattern_generator(link->dc,
+						odm_pipe,
+						controller_test_pattern,
+						controller_color_space,
+						color_depth,
+						NULL,
+						dpg_width,
+						height,
+						offset);
 				offset += offset;
 			}
 		}
@@ -3913,7 +3926,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
 			pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
 				CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
 				color_depth);
-		else if (opp->funcs->opp_set_disp_pattern_generator) {
+		else if (link->dc->hwss.set_disp_pattern_generator) {
 			struct pipe_ctx *odm_pipe;
 			int opp_cnt = 1;
 			int dpg_width = width;
@@ -3926,7 +3939,18 @@ static void set_crtc_test_pattern(struct dc_link *link,
 				struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
 
 				odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
-				odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
+				link->dc->hwss.set_disp_pattern_generator(link->dc,
+						odm_pipe,
+						CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+						CONTROLLER_DP_COLOR_SPACE_UDEFINED,
+						color_depth,
+						NULL,
+						dpg_width,
+						height,
+						0);
+			}
+			link->dc->hwss.set_disp_pattern_generator(link->dc,
+					pipe_ctx,
 					CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
 					CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 					color_depth,
@@ -3934,15 +3958,6 @@ static void set_crtc_test_pattern(struct dc_link *link,
 					dpg_width,
 					height,
 					0);
-			}
-			opp->funcs->opp_set_disp_pattern_generator(opp,
-				CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
-				CONTROLLER_DP_COLOR_SPACE_UDEFINED,
-				color_depth,
-				NULL,
-				dpg_width,
-				height,
-				0);
 		}
 	}
 	break;
@@ -3977,10 +3992,7 @@ bool dc_link_dp_set_test_pattern(
 		}
 	}
 
-	/* Reset CRTC Test Pattern if it is currently running and request
-	 * is VideoMode Reset DP Phy Test Pattern if it is currently running
-	 * and request is VideoMode
-	 */
+	/* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
 	if (link->test_pattern_enabled && test_pattern ==
 			DP_TEST_PATTERN_VIDEO_MODE) {
 		/* Set CRTC Test Pattern */
@@ -4230,7 +4242,7 @@ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
 
 		if (edp_config_set.bits.PANEL_MODE_EDP
 			!= panel_mode_edp) {
-			enum ddc_result result = DDC_RESULT_UNKNOWN;
+			enum dc_status result = DC_ERROR_UNEXPECTED;
 
 			edp_config_set.bits.PANEL_MODE_EDP =
 			panel_mode_edp;
@@ -4240,7 +4252,7 @@ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
 				&edp_config_set.raw,
 				sizeof(edp_config_set.raw));
 
-			ASSERT(result == DDC_RESULT_SUCESSFULL);
+			ASSERT(result == DC_OK);
 		}
 	}
 	DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
@@ -4372,6 +4384,7 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
 void dpcd_set_source_specific_data(struct dc_link *link)
 {
 	if (!link->dc->vendor_signature.is_valid) {
+		enum dc_status result_write_min_hblank = DC_NOT_SUPPORTED;
 		struct dpcd_amd_signature amd_signature;
 		amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
 		amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
@@ -4390,6 +4403,30 @@ void dpcd_set_source_specific_data(struct dc_link *link)
 				(uint8_t *)(&amd_signature),
 				sizeof(amd_signature));
 
+		if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
+			link->dc->caps.min_horizontal_blanking_period != 0) {
+
+			uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
+
+			result_write_min_hblank = core_link_write_dpcd(link,
+				DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
+				sizeof(hblank_size));
+		}
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
+							WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
+							"result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
+							result_write_min_hblank,
+							link->link_index,
+							link->ctx->dce_version,
+							DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
+							link->dc->caps.min_horizontal_blanking_period,
+							link->dpcd_caps.branch_dev_id,
+							link->dpcd_caps.branch_dev_name[0],
+							link->dpcd_caps.branch_dev_name[1],
+							link->dpcd_caps.branch_dev_name[2],
+							link->dpcd_caps.branch_dev_name[3],
+							link->dpcd_caps.branch_dev_name[4],
+							link->dpcd_caps.branch_dev_name[5]);
 	} else {
 		core_link_write_dpcd(link, DP_SOURCE_OUI,
 				link->dc->vendor_signature.data.raw,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 11a619befb42..124ce215fca5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -156,6 +156,13 @@ void dp_enable_link_phy(
 	dp_receiver_power_ctrl(link, true);
 }
 
+void edp_add_delay_for_T9(struct dc_link *link)
+{
+	if (link->local_sink &&
+			link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
+		udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
+}
+
 bool edp_receiver_ready_T9(struct dc_link *link)
 {
 	unsigned int tries = 0;
@@ -165,7 +172,7 @@ bool edp_receiver_ready_T9(struct dc_link *link)
 
 	result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
 
-     /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
+    /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
 	if (result == DC_OK && edpRev >= DP_EDP_12) {
 		do {
 			sinkstatus = 1;
@@ -178,10 +185,6 @@ bool edp_receiver_ready_T9(struct dc_link *link)
 		} while (++tries < 50);
 	}
 
-	if (link->local_sink &&
-			link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
-		udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
-
 	return result;
 }
 bool edp_receiver_ready_T7(struct dc_link *link)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index e430148e47cf..07c22556480b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -54,9 +54,9 @@
 #include "dcn10/dcn10_resource.h"
 #include "dcn20/dcn20_resource.h"
 #include "dcn21/dcn21_resource.h"
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-#include "../dcn30/dcn30_resource.h"
+#include "dcn30/dcn30_resource.h"
+#include "dcn301/dcn301_resource.h"
+#include "dcn302/dcn302_resource.h"
 #endif
 
 #define DC_LOGGER_INIT(logger)
@@ -120,16 +120,22 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
 			dc_version = DCN_VERSION_1_01;
 		if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
 			dc_version = DCN_VERSION_2_1;
+		if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
+			dc_version = DCN_VERSION_2_1;
 		break;
-#endif
 
 	case FAMILY_NV:
 		dc_version = DCN_VERSION_2_0;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 		if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
 			dc_version = DCN_VERSION_3_0;
-#endif
+		if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
+			dc_version = DCN_VERSION_3_02;
 		break;
+
+	case FAMILY_VGH:
+		dc_version = DCN_VERSION_3_01;
+		break;
+#endif
 	default:
 		dc_version = DCE_VERSION_UNKNOWN;
 		break;
@@ -195,21 +201,22 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
 	case DCN_VERSION_1_01:
 		res_pool = dcn10_create_resource_pool(init_data, dc);
 		break;
-
-
 	case DCN_VERSION_2_0:
 		res_pool = dcn20_create_resource_pool(init_data, dc);
 		break;
 	case DCN_VERSION_2_1:
 		res_pool = dcn21_create_resource_pool(init_data, dc);
 		break;
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case DCN_VERSION_3_0:
 		res_pool = dcn30_create_resource_pool(init_data, dc);
 		break;
+	case DCN_VERSION_3_01:
+		res_pool = dcn301_create_resource_pool(init_data, dc);
+		break;
+	case DCN_VERSION_3_02:
+		res_pool = dcn302_create_resource_pool(init_data, dc);
+		break;
 #endif
-
 	default:
 		break;
 	}
@@ -323,7 +330,7 @@ bool resource_construct(
 		}
 	}
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	for (i = 0; i < caps->num_mpc_3dlut; i++) {
 		pool->mpc_lut[i] = dc_create_3dlut_func();
 		if (pool->mpc_lut[i] == NULL)
@@ -794,6 +801,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
 	} else
 		data->recout.x = 0;
 
+	if (stream->src.x > surf_clip.x)
+		surf_clip.width -= stream->src.x - surf_clip.x;
 	data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
 	if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
 		data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
@@ -802,6 +811,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
 	if (stream->src.y < surf_clip.y)
 		data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
 						/ stream->src.height;
+	else if (stream->src.y > surf_clip.y)
+		surf_clip.height -= stream->src.y - surf_clip.y;
 
 	data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
 	if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
@@ -1479,6 +1490,14 @@ bool dc_add_plane_to_context(
 			free_pipe->clock_source = tail_pipe->clock_source;
 			free_pipe->top_pipe = tail_pipe;
 			tail_pipe->bottom_pipe = free_pipe;
+			if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
+				free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe;
+				tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe;
+			}
+			if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) {
+				free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
+				tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe;
+			}
 		}
 		head_pipe = head_pipe->next_odm_pipe;
 	}
@@ -2128,7 +2147,7 @@ enum dc_status resource_map_pool_resources(
 
 	/* Add ABM to the resource if on EDP */
 	if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 		if (pool->abm)
 			pipe_ctx->stream_res.abm = pool->abm;
 		else
@@ -2953,7 +2972,7 @@ unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
index 9e16af22e4aa..a249a0e5edd0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
@@ -54,7 +54,6 @@ static bool dc_sink_construct(struct dc_sink *sink, const struct dc_sink_init_da
 	sink->ctx = link->ctx;
 	sink->dongle_max_pix_clk = init_params->dongle_max_pix_clk;
 	sink->converter_disable_audio = init_params->converter_disable_audio;
-	sink->is_mst_legacy = init_params->sink_is_legacy;
 	sink->dc_container_id = NULL;
 	sink->sink_id = init_params->link->ctx->dc_sink_id_count;
 	// increment dc_sink_id_count because we don't want two sinks with same ID
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index d48fd87d3b95..c103f858375d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -272,7 +272,7 @@ bool dc_stream_set_cursor_attributes(
 	struct dc  *dc;
 	struct resource_context *res_ctx;
 	struct pipe_ctx *pipe_to_program = NULL;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool reset_idle_optimizations = false;
 #endif
 
@@ -294,7 +294,7 @@ bool dc_stream_set_cursor_attributes(
 	res_ctx = &dc->current_state->res_ctx;
 	stream->cursor_attributes = *attributes;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	/* disable idle optimizations while updating cursor */
 	if (dc->idle_optimizations_allowed) {
 		dc_allow_idle_optimizations(dc, false);
@@ -322,7 +322,7 @@ bool dc_stream_set_cursor_attributes(
 	if (pipe_to_program)
 		dc->hwss.cursor_lock(dc, pipe_to_program, false);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	/* re-enable idle optimizations if necessary */
 	if (reset_idle_optimizations)
 		dc_allow_idle_optimizations(dc, true);
@@ -339,7 +339,7 @@ bool dc_stream_set_cursor_position(
 	struct dc  *dc;
 	struct resource_context *res_ctx;
 	struct pipe_ctx *pipe_to_program = NULL;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool reset_idle_optimizations = false;
 #endif
 
@@ -355,7 +355,7 @@ bool dc_stream_set_cursor_position(
 
 	dc = stream->ctx->dc;
 	res_ctx = &dc->current_state->res_ctx;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 
 	/* disable idle optimizations if enabling cursor */
 	if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
@@ -387,7 +387,7 @@ bool dc_stream_set_cursor_position(
 	if (pipe_to_program)
 		dc->hwss.cursor_lock(dc, pipe_to_program, false);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	/* re-enable idle optimizations if necessary */
 	if (reset_idle_optimizations)
 		dc_allow_idle_optimizations(dc, true);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 82fe0ab56e3a..65aabf25cdec 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,7 +42,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.104"
+#define DC_VER "3.2.110"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
@@ -152,9 +152,11 @@ struct dc_caps {
 	uint32_t max_planes;
 	uint32_t max_downscale_ratio;
 	uint32_t i2c_speed_in_khz;
+	uint32_t i2c_speed_in_khz_hdcp;
 	uint32_t dmdata_alloc_size;
 	unsigned int max_cursor_size;
 	unsigned int max_video_width;
+	unsigned int min_horizontal_blanking_period;
 	int linear_pitch_alignment;
 	bool dcc_const_color;
 	bool dynamic_audio;
@@ -189,7 +191,7 @@ struct dc_dcc_setting {
 	unsigned int max_compressed_blk_size;
 	unsigned int max_uncompressed_blk_size;
 	bool independent_64b_blks;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	//These bitfields to be used starting with DCN 3.0
 	struct {
 		uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)
@@ -290,7 +292,7 @@ struct dc_config {
 	bool multi_mon_pp_mclk_switch;
 	bool disable_dmcu;
 	bool enable_4to1MPC;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool clamp_min_dcfclk;
 #endif
 };
@@ -412,6 +414,14 @@ struct dc_bw_validation_profile {
 			} \
 		}
 
+union mem_low_power_enable_options {
+	struct {
+		bool mpc: 1;
+		bool optc: 1;
+	} bits;
+	uint32_t u32All;
+};
+
 struct dc_debug_options {
 	enum visual_confirm visual_confirm;
 	bool sanity_checks;
@@ -472,14 +482,14 @@ struct dc_debug_options {
 	bool edid_read_retry_times;
 	bool remove_disconnect_edp;
 	unsigned int force_odm_combine; //bit vector based on otg inst
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
 #endif
 	unsigned int force_fclk_khz;
 	bool enable_tri_buf;
 	bool dmub_offload_enabled;
 	bool dmcub_emulation;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool disable_idle_power_optimizations;
 #endif
 	bool dmub_command_table; /* for testing only */
@@ -490,7 +500,7 @@ struct dc_debug_options {
 	 * watermarks are not affected.
 	 */
 	unsigned int force_min_dcfclk_mhz;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	int dwb_fi_phase;
 #endif
 	bool disable_timing_sync;
@@ -504,6 +514,7 @@ struct dc_debug_options {
 	bool disable_dsc;
 	bool enable_dram_clock_change_one_display_vactive;
 	bool force_ignore_link_settings;
+	union mem_low_power_enable_options enable_mem_low_power;
 };
 
 struct dc_debug_data {
@@ -599,7 +610,7 @@ struct dc {
 	/* Require to optimize clocks and bandwidth for added/removed planes */
 	bool optimized_required;
 	bool wm_optimized_required;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool idle_optimizations_allowed;
 #endif
 
@@ -658,7 +669,7 @@ struct dc_init_data {
 	 */
 	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
 	struct dpcd_vendor_signature vendor_signature;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool force_smu_not_present;
 #endif
 	bool force_ignore_link_settings;
@@ -853,7 +864,7 @@ struct dc_plane_state {
 	struct dc_transfer_func *in_shaper_func;
 	struct dc_transfer_func *blend_tf;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	struct dc_transfer_func *gamcor_tf;
 #endif
 	enum surface_pixel_format format;
@@ -962,7 +973,7 @@ struct dc_flip_addrs {
 	bool triplebuffer_flips;
 };
 
-bool dc_post_update_surfaces_to_stream(
+void dc_post_update_surfaces_to_stream(
 		struct dc *dc);
 
 #include "dc_stream.h"
@@ -1001,7 +1012,7 @@ void dc_resource_state_construct(
 		const struct dc *dc,
 		struct dc_state *dst_ctx);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 bool dc_acquire_release_mpc_3dlut(
 		struct dc *dc, bool acquire,
 		struct dc_stream_state *stream,
@@ -1129,7 +1140,7 @@ struct hdcp_caps {
 
 #include "dc_link.h"
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
 
 #endif
@@ -1173,7 +1184,7 @@ struct dc_sink {
 	void *priv;
 	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
 	bool converter_disable_audio;
-	bool is_mst_legacy;
+
 	struct dc_sink_dsc_caps dsc_caps;
 	struct dc_sink_fec_caps fec_caps;
 
@@ -1200,7 +1211,6 @@ struct dc_sink_init_data {
 	struct dc_link *link;
 	uint32_t dongle_max_pix_clk;
 	bool converter_disable_audio;
-	bool sink_is_legacy;
 };
 
 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
@@ -1248,7 +1258,7 @@ bool dc_is_dmcu_initialized(struct dc *dc);
 
 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 
 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
 						 struct dc_plane_state *plane);
@@ -1267,6 +1277,9 @@ void dc_unlock_memory_clock_frequency(struct dc *dc);
  */
 void dc_lock_memory_clock_frequency(struct dc *dc);
 
+/* cleanup on driver unload */
+void dc_hardware_release(struct dc *dc);
+
 #endif
 
 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index 768ab38d41cf..ec55b77727d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -61,9 +61,9 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
 
 bool dc_dsc_compute_bandwidth_range(
 		const struct display_stream_compressor *dsc,
-		const uint32_t dsc_min_slice_height_override,
-		const uint32_t min_bpp,
-		const uint32_t max_bpp,
+		uint32_t dsc_min_slice_height_override,
+		uint32_t min_bpp,
+		uint32_t max_bpp,
 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
 		const struct dc_crtc_timing *timing,
 		struct dc_dsc_bw_range *range);
@@ -71,12 +71,14 @@ bool dc_dsc_compute_bandwidth_range(
 bool dc_dsc_compute_config(
 		const struct display_stream_compressor *dsc,
 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
-		const uint32_t dsc_min_slice_height_override,
+		uint32_t dsc_min_slice_height_override,
+		uint32_t max_target_bpp_limit_override,
 		uint32_t target_bandwidth_kbps,
 		const struct dc_crtc_timing *timing,
 		struct dc_dsc_config *dsc_cfg);
 
 void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
+		uint32_t max_target_bpp_limit_override,
 		struct dc_dsc_policy *policy);
 
 void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 85a0170be544..57edb25fc381 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -296,32 +296,6 @@ uint32_t generic_reg_set_ex(const struct dc_context *ctx,
 	return reg_val;
 }
 
-uint32_t dm_read_reg_func(
-	const struct dc_context *ctx,
-	uint32_t address,
-	const char *func_name)
-{
-	uint32_t value;
-#ifdef DM_CHECK_ADDR_0
-	if (address == 0) {
-		DC_ERR("invalid register read; address = 0\n");
-		return 0;
-	}
-#endif
-
-	if (ctx->dmub_srv &&
-	    ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
-	    !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
-		ASSERT(false);
-		return 0;
-	}
-
-	value = cgs_read_register(ctx->cgs_device, address);
-	trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
-
-	return value;
-}
-
 uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
 		uint8_t shift, uint32_t mask, uint32_t *field_value)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 1a87bc3da826..701aa7178a89 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -62,9 +62,7 @@ enum dc_plane_addr_type {
 	PLN_ADDR_TYPE_GRAPHICS = 0,
 	PLN_ADDR_TYPE_GRPH_STEREO,
 	PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	PLN_ADDR_TYPE_RGBEA
-#endif
 };
 
 struct dc_plane_address {
@@ -87,7 +85,6 @@ struct dc_plane_address {
 			PHYSICAL_ADDRESS_LOC right_meta_addr;
 			union large_integer right_dcc_const_color;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 			PHYSICAL_ADDRESS_LOC left_alpha_addr;
 			PHYSICAL_ADDRESS_LOC left_alpha_meta_addr;
 			union large_integer left_alpha_dcc_const_color;
@@ -95,7 +92,6 @@ struct dc_plane_address {
 			PHYSICAL_ADDRESS_LOC right_alpha_addr;
 			PHYSICAL_ADDRESS_LOC right_alpha_meta_addr;
 			union large_integer right_alpha_dcc_const_color;
-#endif
 
 		} grph_stereo;
 
@@ -110,7 +106,6 @@ struct dc_plane_address {
 			union large_integer chroma_dcc_const_color;
 		} video_progressive;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 		struct {
 			PHYSICAL_ADDRESS_LOC addr;
 			PHYSICAL_ADDRESS_LOC meta_addr;
@@ -120,7 +115,6 @@ struct dc_plane_address {
 			PHYSICAL_ADDRESS_LOC alpha_meta_addr;
 			union large_integer alpha_dcc_const_color;
 		} rgbea;
-#endif
 	};
 
 	union large_integer page_table_base;
@@ -156,15 +150,11 @@ struct dc_plane_dcc_param {
 
 	int meta_pitch;
 	bool independent_64b_blks;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	uint8_t dcc_ind_blk;
-#endif
 
 	int meta_pitch_c;
 	bool independent_64b_blks_c;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	uint8_t dcc_ind_blk_c;
-#endif
 };
 
 /*Displayable pixel format in fb*/
@@ -200,10 +190,8 @@ enum surface_pixel_format {
 	SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX,
 	SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT,
 	SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT,
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	SURFACE_PIXEL_FORMAT_GRPH_RGBE,
 	SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA,
-#endif
 	SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
 	SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
 		SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
@@ -856,8 +844,6 @@ enum dwb_stereo_type {
 	DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3,	/* Frame sequential */
 };
 
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
-
 enum dwb_out_format {
 	DWB_OUT_FORMAT_32BPP_ARGB = 0,
 	DWB_OUT_FORMAT_32BPP_RGBA = 1,
@@ -890,8 +876,6 @@ struct mcif_warmup_params {
 	unsigned int		p_vmid;
 };
 
-#endif
-
 #define MCIF_BUF_COUNT	4
 
 struct mcif_buf_params {
@@ -901,9 +885,7 @@ struct mcif_buf_params {
 	unsigned int		chroma_pitch;
 	unsigned int		warmup_pitch;
 	unsigned int		swlock;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	unsigned int		p_vmid;
-#endif
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index c246af7c584b..bf090afc2f70 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -45,6 +45,7 @@ struct dc_stream_status {
 	int audio_inst;
 	struct timing_sync_info timing_sync_info;
 	struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
+	bool is_abm_supported;
 };
 
 // TODO: References to this needs to be removed..
@@ -87,13 +88,11 @@ struct dc_writeback_info {
 	int dwb_pipe_inst;
 	struct dc_dwb_params dwb_params;
 	struct mcif_buf_params mcif_buf_params;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	struct mcif_warmup_params mcif_warmup_params;
 	/* the plane that is the input to TOP_MUX for MPCC that is the DWB source */
 	struct dc_plane_state *writeback_source_plane;
 	/* source MPCC instance.  for use by internally by dc */
 	int mpcc_inst;
-#endif
 };
 
 struct dc_writeback_update {
@@ -207,10 +206,8 @@ struct dc_stream_state {
 	/* writeback */
 	unsigned int num_wb_info;
 	struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	const struct dc_transfer_func *func_shaper;
 	const struct dc_3dlut *lut3d_func;
-#endif
 	/* Computed state bits */
 	bool mode_changed : 1;
 
@@ -262,10 +259,8 @@ struct dc_stream_update {
 
 	struct dc_writeback_update *wb_update;
 	struct dc_dsc_config *dsc_config;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	struct dc_transfer_func *func_shaper;
 	struct dc_3dlut *lut3d_func;
-#endif
 };
 
 bool dc_is_stream_unchanged(
@@ -391,7 +386,7 @@ enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
  * Enable stereo when commit_streams is not required,
  * for example, frame alternate.
  */
-bool dc_enable_stereo(
+void dc_enable_stereo(
 	struct dc *dc,
 	struct dc_state *context,
 	struct dc_stream_state *streams[],
@@ -456,6 +451,7 @@ bool dc_stream_get_crtc_position(struct dc *dc,
 
 bool dc_stream_configure_crc(struct dc *dc,
 			     struct dc_stream_state *stream,
+			     struct crc_params *crc_window,
 			     bool enable,
 			     bool continuous);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_trace.h b/drivers/gpu/drm/amd/display/dc/dc_trace.h
new file mode 100644
index 000000000000..d2615357269b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dc_trace.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu_dm_trace.h"
+
+#define TRACE_DC_PIPE_STATE(pipe_ctx, index, max_pipes) \
+	for (index = 0; index < max_pipes; ++index) { \
+		struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \
+		if (pipe_ctx->plane_state) \
+			trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \
+						      pipe_ctx->stream, &pipe_ctx->plane_res, \
+						      pipe_ctx->update_flags.raw); \
+	}
+
+#define TRACE_DCE_CLOCK_STATE(dce_clocks) \
+	trace_amdgpu_dm_dce_clocks_state(dce_clocks)
+
+#define TRACE_DCN_CLOCK_STATE(dcn_clocks) \
+	trace_amdgpu_dm_dc_clocks_state(dcn_clocks)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index c47a19719de2..53c29d811493 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -234,6 +234,8 @@ struct dc_panel_patch {
 	unsigned int delay_ignore_msa;
 	unsigned int disable_fec;
 	unsigned int extra_t3_ms;
+	unsigned int max_dsc_target_bpp_limit;
+	unsigned int skip_avmute;
 };
 
 struct dc_edid_caps {
@@ -479,7 +481,6 @@ enum display_content_type {
 	DISPLAY_CONTENT_TYPE_GAME = 8
 };
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 enum cm_gamut_adjust_type {
 	CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
 	CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */
@@ -491,7 +492,7 @@ struct cm_grph_csc_adjustment {
 	enum cm_gamut_adjust_type gamut_adjust_type;
 	enum cm_gamut_coef_format gamut_coef_format;
 };
-#endif
+
 /* writeback */
 struct dwb_stereo_params {
 	bool				stereo_enabled;		/* false: normal mode, true: 3D stereo */
@@ -509,21 +510,17 @@ struct dc_dwb_cnv_params {
 	unsigned int		crop_x;		/* cropped window start x value at cnv output */
 	unsigned int		crop_y;		/* cropped window start y value at cnv output */
 	enum dwb_cnv_out_bpc cnv_out_bpc;	/* cnv output pixel depth - 8bpc or 10bpc */
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	enum dwb_out_format	fc_out_format;	/* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */
 	enum dwb_out_denorm	out_denorm_mode;/* dwb output denormalization mode */
 	unsigned int		out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */
 	unsigned int		out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */
-#endif
 };
 
 struct dc_dwb_params {
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	unsigned int			dwbscl_black_color; /* must be in FP1.5.10 */
 	unsigned int			hdr_mult;	/* must be in FP1.6.12 */
 	struct cm_grph_csc_adjustment	csc_params;
 	struct dwb_stereo_params	stereo_params;
-#endif
 	struct dc_dwb_cnv_params	cnv_params;	/* CNV source size and cropping window parameters */
 	unsigned int			dest_width;	/* Destination width */
 	unsigned int			dest_height;	/* Destination height */
@@ -904,8 +901,6 @@ struct dc_golden_table {
 	uint32_t dc_gpio_aux_ctrl_5_val;
 };
 
-
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 enum dc_gpu_mem_alloc_type {
 	DC_MEM_ALLOC_TYPE_GART,
 	DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
@@ -913,7 +908,6 @@ enum dc_gpu_mem_alloc_type {
 	DC_MEM_ALLOC_TYPE_AGP
 };
 
-#endif
 enum dc_psr_version {
 	DC_PSR_VERSION_1			= 0,
 	DC_PSR_VERSION_UNSUPPORTED		= 0xFFFFFFFF,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index e84d21605854..456fadbbfac7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -82,7 +82,20 @@
 	SR(DC_ABM1_ACE_THRES_12), \
 	NBIO_SR(BIOS_SCRATCH_2)
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#define ABM_DCN301_REG_LIST(id)\
+	ABM_COMMON_REG_LIST_DCE_BASE(), \
+	SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
+	SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
+	SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
+	SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
+	SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
+	SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
+	SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
+	SRI(BL1_PWM_USER_LEVEL, ABM, id), \
+	SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
+	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
+	NBIO_SR(BIOS_SCRATCH_2)
+
 #define ABM_DCN30_REG_LIST(id)\
 	ABM_COMMON_REG_LIST_DCE_BASE(), \
 	SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
@@ -98,7 +111,6 @@
 	SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
 	SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
 	NBIO_SR(BIOS_SCRATCH_2)
-#endif
 
 #define ABM_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -173,9 +185,7 @@
 
 #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-#define ABM_MASK_SH_LIST_DCN301(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
-#endif
+#define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
 
 #define ABM_REG_FIELD_LIST(type) \
 	type ABM1_HG_NUM_OF_BINS_SEL; \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 743042d5905a..cda5fd0464bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -652,8 +652,10 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
 				} else {
 					if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
 						(*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
-						if (payload->defer_delay > 0)
+						if (payload->defer_delay > 1)
 							msleep(payload->defer_delay);
+						else if (payload->defer_delay <= 1)
+							udelay(payload->defer_delay * 1000);
 					}
 				}
 				break;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
index 29d69dfc9848..1435d7bc1f21 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
@@ -317,7 +317,9 @@ int dce112_set_clock(struct clk_mgr *clk_mgr, int requested_clk_khz)
 	/*VBIOS will determine DPREFCLK frequency, so we don't set it*/
 	dce_clk_params.target_clock_frequency = 0;
 	dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
-	if (!ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev))
+
+	if (!((clk_mgr->ctx->asic_id.chip_family == FAMILY_AI) &&
+	       ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev)))
 		dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
 			(dce_clk_params.pll_id ==
 					CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 49ae5ff12da6..fb733f573715 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1004,7 +1004,7 @@ static bool get_pixel_clk_frequency_100hz(
 	return false;
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
 const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = {
 	// /1.001 rates
@@ -1073,7 +1073,7 @@ static const struct clock_source_funcs dcn20_clk_src_funcs = {
 	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
 };
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 static bool dcn3_program_pix_clk(
 		struct clock_source *clock_source,
 		struct pixel_clk_params *pix_clk_params,
@@ -1538,7 +1538,7 @@ bool dcn20_clk_src_construct(
 	return ret;
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 bool dcn3_clk_src_construct(
 	struct dce110_clk_src *clk_src,
 	struct dc_context *ctx,
@@ -1555,3 +1555,21 @@ bool dcn3_clk_src_construct(
 	return ret;
 }
 #endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+bool dcn301_clk_src_construct(
+	struct dce110_clk_src *clk_src,
+	struct dc_context *ctx,
+	struct dc_bios *bios,
+	enum clock_source_id id,
+	const struct dce110_clk_src_regs *regs,
+	const struct dce110_clk_src_shift *cs_shift,
+	const struct dce110_clk_src_mask *cs_mask)
+{
+	bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
+
+	clk_src->base.funcs = &dcn3_clk_src_funcs;
+
+	return ret;
+}
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index 69b904ab8151..7fe5a07e2233 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -91,7 +91,7 @@
 		SRII(PIXEL_RATE_CNTL, OTG, 2),\
 		SRII(PIXEL_RATE_CNTL, OTG, 3)
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 #define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \
 		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
 		SRII(PHASE, DP_DTO, 0),\
@@ -106,8 +106,43 @@
 		SRII(PIXEL_RATE_CNTL, OTG, 1),\
 		SRII(PIXEL_RATE_CNTL, OTG, 2),\
 		SRII(PIXEL_RATE_CNTL, OTG, 3)
+
+#define CS_COMMON_REG_LIST_DCN3_01(index, pllid) \
+		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
+		SRII(PHASE, DP_DTO, 0),\
+		SRII(PHASE, DP_DTO, 1),\
+		SRII(PHASE, DP_DTO, 2),\
+		SRII(PHASE, DP_DTO, 3),\
+		SRII(MODULO, DP_DTO, 0),\
+		SRII(MODULO, DP_DTO, 1),\
+		SRII(MODULO, DP_DTO, 2),\
+		SRII(MODULO, DP_DTO, 3),\
+		SRII(PIXEL_RATE_CNTL, OTG, 0),\
+		SRII(PIXEL_RATE_CNTL, OTG, 1),\
+		SRII(PIXEL_RATE_CNTL, OTG, 2),\
+		SRII(PIXEL_RATE_CNTL, OTG, 3)
 #endif
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+#define CS_COMMON_REG_LIST_DCN3_02(index, pllid) \
+		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
+		SRII(PHASE, DP_DTO, 0),\
+		SRII(PHASE, DP_DTO, 1),\
+		SRII(PHASE, DP_DTO, 2),\
+		SRII(PHASE, DP_DTO, 3),\
+		SRII(PHASE, DP_DTO, 4),\
+		SRII(MODULO, DP_DTO, 0),\
+		SRII(MODULO, DP_DTO, 1),\
+		SRII(MODULO, DP_DTO, 2),\
+		SRII(MODULO, DP_DTO, 3),\
+		SRII(MODULO, DP_DTO, 4),\
+		SRII(PIXEL_RATE_CNTL, OTG, 0),\
+		SRII(PIXEL_RATE_CNTL, OTG, 1),\
+		SRII(PIXEL_RATE_CNTL, OTG, 2),\
+		SRII(PIXEL_RATE_CNTL, OTG, 3),\
+		SRII(PIXEL_RATE_CNTL, OTG, 4)
+
+#endif
 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
 	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
 	CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
@@ -221,7 +256,7 @@ bool dcn20_clk_src_construct(
 	const struct dce110_clk_src_shift *cs_shift,
 	const struct dce110_clk_src_mask *cs_mask);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 bool dcn3_clk_src_construct(
 	struct dce110_clk_src *clk_src,
 	struct dc_context *ctx,
@@ -230,6 +265,15 @@ bool dcn3_clk_src_construct(
 	const struct dce110_clk_src_regs *regs,
 	const struct dce110_clk_src_shift *cs_shift,
 	const struct dce110_clk_src_mask *cs_mask);
+
+bool dcn301_clk_src_construct(
+	struct dce110_clk_src *clk_src,
+	struct dc_context *ctx,
+	struct dc_bios *bios,
+	enum clock_source_id id,
+	const struct dce110_clk_src_regs *regs,
+	const struct dce110_clk_src_shift *cs_shift,
+	const struct dce110_clk_src_mask *cs_mask);
 #endif
 
 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
@@ -241,9 +285,10 @@ struct pixel_rate_range_table_entry {
 	unsigned short div_factor;
 };
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[];
 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
 		unsigned int pixel_rate_khz);
 #endif
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 70bbc1311327..ad0ae1f7b513 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -78,7 +78,6 @@
 	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
 	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #define HWSEQ_PIXEL_RATE_REG_LIST_3(blk) \
 	SRII(PIXEL_RATE_CNTL, blk, 0), \
 	SRII(PIXEL_RATE_CNTL, blk, 1),\
@@ -94,7 +93,6 @@
 	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
 	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
 	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
-#endif
 
 #define HWSEQ_DCE11_REG_LIST_BASE() \
 	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
@@ -224,28 +222,6 @@
 	SR(VGA_TEST_CONTROL), \
 	SR(DC_IP_REQUEST_CNTL)
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-#define HWSEQ_DCN30_REG_LIST()\
-	HWSEQ_DCN2_REG_LIST(),\
-	HWSEQ_DCN_REG_LIST(), \
-	HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \
-	HWSEQ_PHYPLL_REG_LIST_3(OTG), \
-	SR(MICROSECOND_TIME_BASE_DIV), \
-	SR(MILLISECOND_TIME_BASE_DIV), \
-	SR(DISPCLK_FREQ_CHANGE_CNTL), \
-	SR(RBBMIF_TIMEOUT_DIS), \
-	SR(RBBMIF_TIMEOUT_DIS_2), \
-	SR(DCHUBBUB_CRC_CTRL), \
-	SR(DPP_TOP0_DPP_CRC_CTRL), \
-	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
-	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
-	SR(MPC_CRC_CTRL), \
-	SR(MPC_CRC_RESULT_GB), \
-	SR(MPC_CRC_RESULT_C), \
-	SR(MPC_CRC_RESULT_AR), \
-	SR(AZALIA_AUDIO_DTO), \
-	SR(AZALIA_CONTROLLER_CLOCK_GATING)
-#endif
 #define HWSEQ_DCN2_REG_LIST()\
 	HWSEQ_DCN_REG_LIST(), \
 	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
@@ -361,6 +337,163 @@
 	SR(D6VGA_CONTROL), \
 	SR(DC_IP_REQUEST_CNTL)
 
+#define HWSEQ_DCN30_REG_LIST()\
+	HWSEQ_DCN2_REG_LIST(),\
+	HWSEQ_DCN_REG_LIST(), \
+	HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \
+	HWSEQ_PHYPLL_REG_LIST_3(OTG), \
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+	SR(MPC_CRC_CTRL), \
+	SR(MPC_CRC_RESULT_GB), \
+	SR(MPC_CRC_RESULT_C), \
+	SR(MPC_CRC_RESULT_AR), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING)
+
+#define HWSEQ_DCN301_REG_LIST()\
+	SR(REFCLK_CNTL), \
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DIO_MEM_PWR_CTRL), \
+	SR(DCCG_GATE_DISABLE_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL2), \
+	SR(DCFCLK_CNTL),\
+	SR(DCFCLK_CNTL), \
+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+	SRII(PIXEL_RATE_CNTL, OTG, 0), \
+	SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+	SR(MPC_CRC_CTRL), \
+	SR(MPC_CRC_RESULT_GB), \
+	SR(MPC_CRC_RESULT_C), \
+	SR(MPC_CRC_RESULT_AR), \
+	SR(DOMAIN0_PG_CONFIG), \
+	SR(DOMAIN1_PG_CONFIG), \
+	SR(DOMAIN2_PG_CONFIG), \
+	SR(DOMAIN3_PG_CONFIG), \
+	SR(DOMAIN4_PG_CONFIG), \
+	SR(DOMAIN5_PG_CONFIG), \
+	SR(DOMAIN6_PG_CONFIG), \
+	SR(DOMAIN7_PG_CONFIG), \
+	SR(DOMAIN16_PG_CONFIG), \
+	SR(DOMAIN17_PG_CONFIG), \
+	SR(DOMAIN18_PG_CONFIG), \
+	SR(DOMAIN0_PG_STATUS), \
+	SR(DOMAIN1_PG_STATUS), \
+	SR(DOMAIN2_PG_STATUS), \
+	SR(DOMAIN3_PG_STATUS), \
+	SR(DOMAIN4_PG_STATUS), \
+	SR(DOMAIN5_PG_STATUS), \
+	SR(DOMAIN6_PG_STATUS), \
+	SR(DOMAIN7_PG_STATUS), \
+	SR(DOMAIN16_PG_STATUS), \
+	SR(DOMAIN17_PG_STATUS), \
+	SR(DOMAIN18_PG_STATUS), \
+	SR(D1VGA_CONTROL), \
+	SR(D2VGA_CONTROL), \
+	SR(D3VGA_CONTROL), \
+	SR(D4VGA_CONTROL), \
+	SR(D5VGA_CONTROL), \
+	SR(D6VGA_CONTROL), \
+	SR(DC_IP_REQUEST_CNTL), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING)
+
+#define HWSEQ_DCN302_REG_LIST()\
+	HWSEQ_DCN_REG_LIST(), \
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+	SR(MPC_CRC_CTRL), \
+	SR(MPC_CRC_RESULT_GB), \
+	SR(MPC_CRC_RESULT_C), \
+	SR(MPC_CRC_RESULT_AR), \
+	SR(DOMAIN0_PG_CONFIG), \
+	SR(DOMAIN1_PG_CONFIG), \
+	SR(DOMAIN2_PG_CONFIG), \
+	SR(DOMAIN3_PG_CONFIG), \
+	SR(DOMAIN4_PG_CONFIG), \
+	SR(DOMAIN5_PG_CONFIG), \
+	SR(DOMAIN6_PG_CONFIG), \
+	SR(DOMAIN7_PG_CONFIG), \
+	SR(DOMAIN8_PG_CONFIG), \
+	SR(DOMAIN9_PG_CONFIG), \
+	SR(DOMAIN16_PG_CONFIG), \
+	SR(DOMAIN17_PG_CONFIG), \
+	SR(DOMAIN18_PG_CONFIG), \
+	SR(DOMAIN19_PG_CONFIG), \
+	SR(DOMAIN20_PG_CONFIG), \
+	SR(DOMAIN0_PG_STATUS), \
+	SR(DOMAIN1_PG_STATUS), \
+	SR(DOMAIN2_PG_STATUS), \
+	SR(DOMAIN3_PG_STATUS), \
+	SR(DOMAIN4_PG_STATUS), \
+	SR(DOMAIN5_PG_STATUS), \
+	SR(DOMAIN6_PG_STATUS), \
+	SR(DOMAIN7_PG_STATUS), \
+	SR(DOMAIN8_PG_STATUS), \
+	SR(DOMAIN9_PG_STATUS), \
+	SR(DOMAIN16_PG_STATUS), \
+	SR(DOMAIN17_PG_STATUS), \
+	SR(DOMAIN18_PG_STATUS), \
+	SR(DOMAIN19_PG_STATUS), \
+	SR(DOMAIN20_PG_STATUS), \
+	SR(D1VGA_CONTROL), \
+	SR(D2VGA_CONTROL), \
+	SR(D3VGA_CONTROL), \
+	SR(D4VGA_CONTROL), \
+	SR(D5VGA_CONTROL), \
+	SR(D6VGA_CONTROL), \
+	SR(DC_IP_REQUEST_CNTL), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING)
+
+#define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \
+	SRII(PIXEL_RATE_CNTL, blk, 0), \
+	SRII(PIXEL_RATE_CNTL, blk, 1),\
+	SRII(PIXEL_RATE_CNTL, blk, 2),\
+	SRII(PIXEL_RATE_CNTL, blk, 3), \
+	SRII(PIXEL_RATE_CNTL, blk, 4)
+
+#define HWSEQ_PHYPLL_REG_LIST_302(blk) \
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4)
+
 struct dce_hwseq_registers {
 	uint32_t DCFE_CLOCK_CONTROL[6];
 	uint32_t DCFEV_CLOCK_CONTROL;
@@ -462,6 +595,8 @@ struct dce_hwseq_registers {
 	uint32_t MC_VM_XGMI_LFB_CNTL;
 	uint32_t AZALIA_AUDIO_DTO;
 	uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
+	uint32_t HPO_TOP_CLOCK_CONTROL;
+	uint32_t ODM_MEM_PWR_CTRL3;
 };
  /* set field name */
 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -598,12 +733,6 @@ struct dce_hwseq_registers {
 	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
 	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-#define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
-	HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
-	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
-#endif
-
 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
 	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
@@ -703,6 +832,106 @@ struct dce_hwseq_registers {
 	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
 	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)
 
+#define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
+	HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)
+
+#define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\
+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+	HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\
+	HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\
+	HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\
+	HWS_SF(, PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh),\
+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
+
+#define HWSEQ_DCN302_MASK_SH_LIST(mask_sh)\
+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
+
 #define HWSEQ_REG_FIELD_LIST(type) \
 	type DCFE_CLOCK_ENABLE; \
 	type DCFEV_CLOCK_ENABLE; \
@@ -815,16 +1044,31 @@ struct dce_hwseq_registers {
 	type D2VGA_MODE_ENABLE; \
 	type D3VGA_MODE_ENABLE; \
 	type D4VGA_MODE_ENABLE; \
-	type AZALIA_AUDIO_DTO_MODULE;
+	type AZALIA_AUDIO_DTO_MODULE; \
+	type ODM_MEM_UNASSIGNED_PWR_MODE; \
+	type ODM_MEM_VBLANK_PWR_MODE;
+
+#define HWSEQ_DCN3_REG_FIELD_LIST(type) \
+	type HPO_HDMISTREAMCLK_GATE_DIS;
+
+#define HWSEQ_DCN301_REG_FIELD_LIST(type) \
+	type PANEL_BLON;\
+	type PANEL_DIGON;\
+	type PANEL_DIGON_OVRD;\
+	type PANEL_PWRSEQ_TARGET_STATE_R;
 
 struct dce_hwseq_shift {
 	HWSEQ_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
+	HWSEQ_DCN3_REG_FIELD_LIST(uint8_t)
+	HWSEQ_DCN301_REG_FIELD_LIST(uint8_t)
 };
 
 struct dce_hwseq_mask {
 	HWSEQ_REG_FIELD_LIST(uint32_t)
 	HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
+	HWSEQ_DCN3_REG_FIELD_LIST(uint32_t)
+	HWSEQ_DCN301_REG_FIELD_LIST(uint32_t)
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 24adec407972..3e34afe8c504 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -299,8 +299,12 @@ static bool setup_engine(
 	/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
 	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
 
+	/*set SW requested I2c speed to default, if API calls in it will be override later*/
+	set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz);
+
 	if (dce_i2c_hw->setup_limit != 0)
 		i2c_setup_limit = dce_i2c_hw->setup_limit;
+
 	/* Program pin select */
 	REG_UPDATE_6(DC_I2C_CONTROL,
 		     DC_I2C_GO, 0,
@@ -339,8 +343,6 @@ static void release_engine(
 {
 	bool safe_to_reset;
 
-	/* Restore original HW engine speed */
-	set_speed(dce_i2c_hw, dce_i2c_hw->default_speed);
 
 	/* Reset HW engine */
 	{
@@ -360,6 +362,9 @@ static void release_engine(
 	/* HW I2c engine - clock gating feature */
 	if (!dce_i2c_hw->engine_keep_power_up_count)
 		REG_UPDATE_N(SETUP, 1, FN(SETUP, DC_I2C_DDC1_ENABLE), 0);
+
+	/*for HW HDCP Ri polling failure w/a test*/
+	set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz_hdcp);
 	/* Release I2C after reset, so HW or DMCU could use it */
 	REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1,
 		DC_I2C_SW_USE_I2C_REG_REQ, 0);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 2a32b66959ba..130a0a0c8332 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -1330,7 +1330,6 @@ static bool configure_graphics_mode(
 			REG_SET(OUTPUT_CSC_CONTROL, 0,
 				OUTPUT_CSC_GRPH_MODE, 0);
 			break;
-			break;
 		case COLOR_SPACE_SRGB_LIMITED:
 			/* TV RGB */
 			REG_SET(OUTPUT_CSC_CONTROL, 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index a28c4ae0f259..8ab9d6c79808 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -418,25 +418,18 @@ static int map_transmitter_id_to_phy_instance(
 	switch (transmitter) {
 	case TRANSMITTER_UNIPHY_A:
 		return 0;
-	break;
 	case TRANSMITTER_UNIPHY_B:
 		return 1;
-	break;
 	case TRANSMITTER_UNIPHY_C:
 		return 2;
-	break;
 	case TRANSMITTER_UNIPHY_D:
 		return 3;
-	break;
 	case TRANSMITTER_UNIPHY_E:
 		return 4;
-	break;
 	case TRANSMITTER_UNIPHY_F:
 		return 5;
-	break;
 	case TRANSMITTER_UNIPHY_G:
 		return 6;
-	break;
 	default:
 		ASSERT(0);
 		return 0;
@@ -1071,7 +1064,9 @@ static bool dce100_resource_construct(
 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 40;
+	dc->caps.i2c_speed_in_khz = 40;
 	dc->caps.max_cursor_size = 128;
+	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.dual_link_dvi = true;
 	dc->caps.disable_dp_clk_share = true;
 	dc->caps.extended_aux_timeout_support = false;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 3ac6c7b65a45..9f56887029ca 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -992,8 +992,6 @@ void dce110_edp_backlight_control(
 
 	link_transmitter_control(ctx->dc_bios, &cntl);
 
-
-
 	if (enable && link->dpcd_sink_ext_caps.bits.oled)
 		msleep(OLED_POST_T7_DELAY);
 
@@ -1004,7 +1002,7 @@ void dce110_edp_backlight_control(
 
 	/*edp 1.2*/
 	if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
-		edp_receiver_ready_T9(link);
+		edp_add_delay_for_T9(link);
 
 	if (!enable && link->dpcd_sink_ext_caps.bits.oled)
 		msleep(OLED_PRE_T11_DELAY);
@@ -1145,12 +1143,14 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
 	if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
 		pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
 
-		/*
-		 * After output is idle pattern some sinks need time to recognize the stream
-		 * has changed or they enter protection state and hang.
-		 */
-		if (!dc_is_embedded_signal(pipe_ctx->stream->signal))
+		if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
+			/*
+			 * After output is idle pattern some sinks need time to recognize the stream
+			 * has changed or they enter protection state and hang.
+			 */
 			msleep(60);
+		} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
+			edp_receiver_ready_T9(link);
 	}
 
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 1d5385072a39..3f63822b8e28 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -471,25 +471,18 @@ static int map_transmitter_id_to_phy_instance(
 	switch (transmitter) {
 	case TRANSMITTER_UNIPHY_A:
 		return 0;
-	break;
 	case TRANSMITTER_UNIPHY_B:
 		return 1;
-	break;
 	case TRANSMITTER_UNIPHY_C:
 		return 2;
-	break;
 	case TRANSMITTER_UNIPHY_D:
 		return 3;
-	break;
 	case TRANSMITTER_UNIPHY_E:
 		return 4;
-	break;
 	case TRANSMITTER_UNIPHY_F:
 		return 5;
-	break;
 	case TRANSMITTER_UNIPHY_G:
 		return 6;
-	break;
 	default:
 		ASSERT(0);
 		return 0;
@@ -1372,8 +1365,10 @@ static bool dce110_resource_construct(
 	pool->base.underlay_pipe_index = pool->base.pipe_count;
 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
 	dc->caps.max_downscale_ratio = 150;
-	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz = 40;
+	dc->caps.i2c_speed_in_khz_hdcp = 40;
 	dc->caps.max_cursor_size = 128;
+	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.is_apu = true;
 	dc->caps.extended_aux_timeout_support = false;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 0853bc9917c7..f99b1c084590 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -446,25 +446,18 @@ static int map_transmitter_id_to_phy_instance(
 	switch (transmitter) {
 	case TRANSMITTER_UNIPHY_A:
 		return 0;
-	break;
 	case TRANSMITTER_UNIPHY_B:
 		return 1;
-	break;
 	case TRANSMITTER_UNIPHY_C:
 		return 2;
-	break;
 	case TRANSMITTER_UNIPHY_D:
 		return 3;
-	break;
 	case TRANSMITTER_UNIPHY_E:
 		return 4;
-	break;
 	case TRANSMITTER_UNIPHY_F:
 		return 5;
-	break;
 	case TRANSMITTER_UNIPHY_G:
 		return 6;
-	break;
 	default:
 		ASSERT(0);
 		return 0;
@@ -865,7 +858,7 @@ static struct clock_source *find_matching_pll(
 		return pool->clock_sources[DCE112_CLK_SRC_PLL5];
 	default:
 		return NULL;
-	};
+	}
 
 	return 0;
 }
@@ -1240,7 +1233,9 @@ static bool dce112_resource_construct(
 	pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
 	dc->caps.max_cursor_size = 128;
+	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.dual_link_dvi = true;
 	dc->caps.extended_aux_timeout_support = false;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 8f362e8c1787..f1e3d2888eac 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -383,25 +383,18 @@ static int map_transmitter_id_to_phy_instance(
 	switch (transmitter) {
 	case TRANSMITTER_UNIPHY_A:
 		return 0;
-	break;
 	case TRANSMITTER_UNIPHY_B:
 		return 1;
-	break;
 	case TRANSMITTER_UNIPHY_C:
 		return 2;
-	break;
 	case TRANSMITTER_UNIPHY_D:
 		return 3;
-	break;
 	case TRANSMITTER_UNIPHY_E:
 		return 4;
-	break;
 	case TRANSMITTER_UNIPHY_F:
 		return 5;
-	break;
 	case TRANSMITTER_UNIPHY_G:
 		return 6;
-	break;
 	default:
 		ASSERT(0);
 		return 0;
@@ -1080,7 +1073,9 @@ static bool dce120_resource_construct(
 
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
 	dc->caps.max_cursor_size = 128;
+	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.dual_link_dvi = true;
 	dc->caps.psp_setup_panel_mode = true;
 	dc->caps.extended_aux_timeout_support = false;
diff --git a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
index 5a5a9cb77acb..e9dd78c484d6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c
@@ -453,25 +453,18 @@ static int map_transmitter_id_to_phy_instance(
 	switch (transmitter) {
 	case TRANSMITTER_UNIPHY_A:
 		return 0;
-	break;
 	case TRANSMITTER_UNIPHY_B:
 		return 1;
-	break;
 	case TRANSMITTER_UNIPHY_C:
 		return 2;
-	break;
 	case TRANSMITTER_UNIPHY_D:
 		return 3;
-	break;
 	case TRANSMITTER_UNIPHY_E:
 		return 4;
-	break;
 	case TRANSMITTER_UNIPHY_F:
 		return 5;
-	break;
 	case TRANSMITTER_UNIPHY_G:
 		return 6;
-	break;
 	default:
 		ASSERT(0);
 		return 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index a19be9de2df7..390a0fa37239 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -458,25 +458,18 @@ static int map_transmitter_id_to_phy_instance(
 	switch (transmitter) {
 	case TRANSMITTER_UNIPHY_A:
 		return 0;
-	break;
 	case TRANSMITTER_UNIPHY_B:
 		return 1;
-	break;
 	case TRANSMITTER_UNIPHY_C:
 		return 2;
-	break;
 	case TRANSMITTER_UNIPHY_D:
 		return 3;
-	break;
 	case TRANSMITTER_UNIPHY_E:
 		return 4;
-	break;
 	case TRANSMITTER_UNIPHY_F:
 		return 5;
-	break;
 	case TRANSMITTER_UNIPHY_G:
 		return 6;
-	break;
 	default:
 		ASSERT(0);
 		return 0;
@@ -970,7 +963,9 @@ static bool dce80_construct(
 	pool->base.timing_generator_count = res_cap.num_timing_generator;
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 40;
+	dc->caps.i2c_speed_in_khz_hdcp = 40;
 	dc->caps.max_cursor_size = 128;
+	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.dual_link_dvi = true;
 	dc->caps.extended_aux_timeout_support = false;
 
@@ -1168,7 +1163,9 @@ static bool dce81_construct(
 	pool->base.timing_generator_count = res_cap_81.num_timing_generator;
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 40;
+	dc->caps.i2c_speed_in_khz_hdcp = 40;
 	dc->caps.max_cursor_size = 128;
+	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.is_apu = true;
 
 	/*************************************************
@@ -1365,7 +1362,9 @@ static bool dce83_construct(
 	pool->base.timing_generator_count = res_cap_83.num_timing_generator;
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 40;
+	dc->caps.i2c_speed_in_khz_hdcp = 40;
 	dc->caps.max_cursor_size = 128;
+	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.is_apu = true;
 
 	/*************************************************
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index fce37c527a0b..878b53d85694 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -656,7 +656,7 @@ static void dpp1_dscl_set_recout(
 			 RECOUT_WIDTH, recout->width,
 		/* Number of RECOUT vertical lines */
 			 RECOUT_HEIGHT, recout->height
-			 - visual_confirm_on * 4 * (dpp->base.inst + 1));
+			 - visual_confirm_on * 2 * (dpp->base.inst + 1));
 }
 
 /* Main function to program scaler and line buffer in manual scaling mode */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index db5615a51fea..41679ad531c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -326,7 +326,6 @@ void hubp1_program_pixel_format(
 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
 				SURFACE_PIXEL_FORMAT, 119);
 		break;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 				SURFACE_PIXEL_FORMAT, 116,
@@ -337,7 +336,6 @@ void hubp1_program_pixel_format(
 				SURFACE_PIXEL_FORMAT, 116,
 				ALPHA_PLANE_EN, 1);
 		break;
-#endif
 	default:
 		BREAK_TO_DEBUGGER();
 		break;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d0f3bf953d02..8eb88a50af51 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -52,6 +52,7 @@
 #include "dpcd_defs.h"
 #include "dsc.h"
 #include "dce/dmub_hw_lock_mgr.h"
+#include "dc_trace.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -1020,15 +1021,17 @@ static bool dcn10_hw_wa_force_recovery(struct dc *dc)
 
 }
 
-
 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 {
 	static bool should_log_hw_state; /* prevent hw state log by default */
 
 	if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
-		if (should_log_hw_state) {
+		int i = 0;
+
+		if (should_log_hw_state)
 			dcn10_log_hw_state(dc, NULL);
-		}
+
+		TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
 		BREAK_TO_DEBUGGER();
 		if (dcn10_hw_wa_force_recovery(dc)) {
 		/*check again*/
@@ -1434,12 +1437,6 @@ void dcn10_init_hw(struct dc *dc)
 
 	if (dc->clk_mgr->funcs->notify_wm_ranges)
 		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
-
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
-	if (dc->clk_mgr->funcs->set_hard_max_memclk)
-		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
-#endif
-
 }
 
 /* In headless boot cases, DIG may be turned
@@ -1541,6 +1538,8 @@ static bool patch_address_for_sbs_tb_stereo(
 			plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
 			plane_state->address.grph_stereo.right_addr =
 			plane_state->address.grph_stereo.left_addr;
+			plane_state->address.grph_stereo.right_meta_addr =
+			plane_state->address.grph_stereo.left_meta_addr;
 		}
 	}
 	return false;
@@ -1851,10 +1850,20 @@ void dcn10_enable_timing_synchronization(
 	struct pipe_ctx *grouped_pipes[])
 {
 	struct dc_context *dc_ctx = dc->ctx;
-	int i;
+	struct output_pixel_processor *opp;
+	struct timing_generator *tg;
+	int i, width, height;
 
 	DC_SYNC_INFO("Setting up OTG reset trigger\n");
 
+	for (i = 1; i < group_size; i++) {
+		opp = grouped_pipes[i]->stream_res.opp;
+		tg = grouped_pipes[i]->stream_res.tg;
+		tg->funcs->get_otg_active_size(tg, &width, &height);
+		if (opp->funcs->opp_program_dpg_dimensions)
+			opp->funcs->opp_program_dpg_dimensions(opp, width, 2*(height) + 1);
+	}
+
 	for (i = 1; i < group_size; i++)
 		grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
 				grouped_pipes[i]->stream_res.tg,
@@ -1871,6 +1880,14 @@ void dcn10_enable_timing_synchronization(
 		grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
 				grouped_pipes[i]->stream_res.tg);
 
+	for (i = 1; i < group_size; i++) {
+		opp = grouped_pipes[i]->stream_res.opp;
+		tg = grouped_pipes[i]->stream_res.tg;
+		tg->funcs->get_otg_active_size(tg, &width, &height);
+		if (opp->funcs->opp_program_dpg_dimensions)
+			opp->funcs->opp_program_dpg_dimensions(opp, width, height);
+	}
+
 	DC_SYNC_INFO("Sync complete\n");
 }
 
@@ -2761,122 +2778,6 @@ static struct pipe_ctx *dcn10_find_top_pipe_for_stream(
 	return NULL;
 }
 
-bool dcn10_disconnect_pipes(
-		struct dc *dc,
-		struct dc_state *context)
-{
-		bool found_pipe = false;
-		int i, j;
-		struct dce_hwseq *hws = dc->hwseq;
-		struct dc_state *old_ctx = dc->current_state;
-		bool mpcc_disconnected = false;
-		struct pipe_ctx *old_pipe;
-		struct pipe_ctx *new_pipe;
-		DC_LOGGER_INIT(dc->ctx->logger);
-
-		/* Set pipe update flags and lock pipes */
-		for (i = 0; i < dc->res_pool->pipe_count; i++) {
-			old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
-			new_pipe = &context->res_ctx.pipe_ctx[i];
-			new_pipe->update_flags.raw = 0;
-
-			if (!old_pipe->plane_state && !new_pipe->plane_state)
-				continue;
-
-			if (old_pipe->plane_state && !new_pipe->plane_state)
-				new_pipe->update_flags.bits.disable = 1;
-
-			/* Check for scl update */
-			if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
-					new_pipe->update_flags.bits.scaler = 1;
-
-			/* Check for vp update */
-			if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
-					|| memcmp(&old_pipe->plane_res.scl_data.viewport_c,
-						&new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
-				new_pipe->update_flags.bits.viewport = 1;
-
-		}
-
-		if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
-			/* Disconnect mpcc here only if losing pipe split*/
-			for (i = 0; i < dc->res_pool->pipe_count; i++) {
-				if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable &&
-					old_ctx->res_ctx.pipe_ctx[i].top_pipe) {
-
-					/* Find the top pipe in the new ctx for the bottom pipe that we
-					 * want to remove by comparing the streams and planes. If both
-					 * pipes are being disabled then do it in the regular pipe
-					 * programming sequence
-					 */
-					for (j = 0; j < dc->res_pool->pipe_count; j++) {
-						if (old_ctx->res_ctx.pipe_ctx[i].top_pipe->stream == context->res_ctx.pipe_ctx[j].stream &&
-							old_ctx->res_ctx.pipe_ctx[i].top_pipe->plane_state == context->res_ctx.pipe_ctx[j].plane_state &&
-							!context->res_ctx.pipe_ctx[j].top_pipe &&
-							!context->res_ctx.pipe_ctx[j].update_flags.bits.disable) {
-							found_pipe = true;
-							break;
-						}
-					}
-
-					// Disconnect if the top pipe lost it's pipe split
-					if (found_pipe && !context->res_ctx.pipe_ctx[j].bottom_pipe) {
-						hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
-						DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
-						mpcc_disconnected = true;
-					}
-				}
-				found_pipe = false;
-			}
-		}
-
-		if (mpcc_disconnected) {
-			for (i = 0; i < dc->res_pool->pipe_count; i++) {
-				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-				struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
-				struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-				struct hubp *hubp = pipe_ctx->plane_res.hubp;
-
-				if (!pipe_ctx || !plane_state || !pipe_ctx->stream)
-					continue;
-
-				// Only update scaler and viewport here if we lose a pipe split.
-				// This is to prevent half the screen from being black when we
-				// unlock after disconnecting MPCC.
-				if (!(old_pipe && !pipe_ctx->top_pipe &&
-					!pipe_ctx->bottom_pipe && old_pipe->bottom_pipe))
-					continue;
-
-				if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) {
-					if (pipe_ctx->update_flags.bits.scaler ||
-						plane_state->update_flags.bits.scaling_change ||
-						plane_state->update_flags.bits.position_change ||
-						plane_state->update_flags.bits.per_pixel_alpha_change ||
-						pipe_ctx->stream->update_flags.bits.scaling) {
-
-						pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
-						ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
-						/* scaler configuration */
-						pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
-						pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
-					}
-
-					if (pipe_ctx->update_flags.bits.viewport ||
-						(context == dc->current_state && plane_state->update_flags.bits.position_change) ||
-						(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
-						(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
-
-						hubp->funcs->mem_program_viewport(
-							hubp,
-							&pipe_ctx->plane_res.scl_data.viewport,
-							&pipe_ctx->plane_res.scl_data.viewport_c);
-					}
-				}
-			}
-		}
-	return mpcc_disconnected;
-}
-
 void dcn10_wait_for_pending_cleared(struct dc *dc,
 		struct dc_state *context)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index b24c8ae8b1ec..254300b06b43 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -34,7 +34,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
 	.post_unlock_program_front_end = dcn10_post_unlock_program_front_end,
-	.disconnect_pipes = dcn10_disconnect_pipes,
 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
 	.update_plane_addr = dcn10_update_plane_addr,
 	.update_dchub = dcn10_update_dchub,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 04dabed5f1c5..d4caad670855 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -154,12 +154,10 @@ struct dcn10_link_enc_registers {
 	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
 	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
 	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	uint32_t TMDS_DCBALANCER_CONTROL;
 	uint32_t PHYA_LINK_CNTL2;
 	uint32_t PHYB_LINK_CNTL2;
 	uint32_t PHYC_LINK_CNTL2;
-#endif
 };
 
 #define LE_SF(reg_name, field_name, post_fix)\
@@ -449,14 +447,25 @@ struct dcn10_link_enc_registers {
 	type AUX_RX_TIMEOUT_LEN;\
 	type AUX_RX_TIMEOUT_LEN_MUL
 
+#define DCN30_LINK_ENCODER_REG_FIELD_LIST(type) \
+	type TMDS_SYNC_DCBAL_EN;\
+	type PHY_HPO_DIG_SRC_SEL;\
+	type PHY_HPO_ENC_SRC_SEL;\
+	type DPCS_TX_HDMI_FRL_MODE;\
+	type DPCS_TX_DATA_SWAP_10_BIT;\
+	type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\
+	type RDPCS_TX_CLK_EN
+
 struct dcn10_link_enc_shift {
 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 };
 
 struct dcn10_link_enc_mask {
 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 };
 
 struct dcn10_link_encoder {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index d79718fde5a6..d54d731415d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -403,6 +403,7 @@ static const struct opp_funcs dcn10_opp_funcs = {
 		.opp_program_stereo = opp1_program_stereo,
 		.opp_pipe_clock_control = opp1_pipe_clock_control,
 		.opp_set_disp_pattern_generator = NULL,
+		.opp_program_dpg_dimensions = NULL,
 		.dpg_is_blanked = NULL,
 		.opp_destroy = opp1_destroy
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 800be2693fac..a125d3f05c81 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -299,16 +299,13 @@ void optc1_program_timing(
 		REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
 	}
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
 		if (optc1->opp_count == 4)
 			h_div = H_TIMING_DIV_BY4;
 
 		REG_UPDATE(OTG_H_TIMING_CNTL,
 		OTG_H_TIMING_DIV_MODE, h_div);
-	} else
-#endif
-	{
+	} else {
 		REG_UPDATE(OTG_H_TIMING_CNTL,
 		OTG_H_TIMING_DIV_BY2, h_div);
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index b38475285835..344eb487219e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -171,7 +171,6 @@ struct dcn_optc_registers {
 	uint32_t OPTC_DATA_FORMAT_CONTROL;
 	uint32_t OPTC_BYTES_PER_PIXEL;
 	uint32_t OPTC_WIDTH_CONTROL;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	uint32_t OTG_BLANK_DATA_COLOR;
 	uint32_t OTG_BLANK_DATA_COLOR_EXT;
 	uint32_t OTG_DRR_TRIGGER_WINDOW;
@@ -179,7 +178,6 @@ struct dcn_optc_registers {
 	uint32_t OTG_M_CONST_DTO1;
 	uint32_t OTG_DRR_V_TOTAL_CHANGE;
 	uint32_t OTG_GLOBAL_CONTROL4;
-#endif
 };
 
 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
@@ -474,8 +472,6 @@ struct dcn_optc_registers {
 	type MANUAL_FLOW_CONTROL;\
 	type MANUAL_FLOW_CONTROL_SEL;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-
 #define TG_REG_FIELD_LIST(type) \
 	TG_REG_FIELD_LIST_DCN1_0(type)\
 	type OTG_V_SYNC_MODE;\
@@ -517,33 +513,6 @@ struct dcn_optc_registers {
 	type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
 	type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
 	type OTG_CRC_DATA_FORMAT;
-#else
-
-#define TG_REG_FIELD_LIST(type) \
-	TG_REG_FIELD_LIST_DCN1_0(type)\
-	type MASTER_UPDATE_LOCK_DB_X;\
-	type MASTER_UPDATE_LOCK_DB_Y;\
-	type MASTER_UPDATE_LOCK_DB_EN;\
-	type GLOBAL_UPDATE_LOCK_EN;\
-	type DIG_UPDATE_LOCATION;\
-	type OTG_DSC_START_POSITION_X;\
-	type OTG_DSC_START_POSITION_LINE_NUM;\
-	type OPTC_NUM_OF_INPUT_SEGMENT;\
-	type OPTC_SEG0_SRC_SEL;\
-	type OPTC_SEG1_SRC_SEL;\
-	type OPTC_MEM_SEL;\
-	type OPTC_DATA_FORMAT;\
-	type OPTC_DSC_MODE;\
-	type OPTC_DSC_BYTES_PER_PIXEL;\
-	type OPTC_DSC_SLICE_WIDTH;\
-	type OPTC_SEGMENT_WIDTH;\
-	type OPTC_DWB0_SOURCE_SELECT;\
-	type OPTC_DWB1_SOURCE_SELECT;\
-	type OTG_CRC_DSC_MODE;\
-	type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
-	type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
-	type OTG_CRC_DATA_FORMAT;
-#endif
 
 
 struct dcn_optc_shift {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index a78712caf124..e74bb2735885 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1416,7 +1416,9 @@ static bool dcn10_resource_construct(
 	dc->caps.max_video_width = 3840;
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
 	dc->caps.max_cursor_size = 256;
+	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.max_slave_planes = 1;
 	dc->caps.is_apu = true;
 	dc->caps.post_blend_color_processing = false;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index b99d2527cf03..9e38c37c1d73 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -169,14 +169,12 @@ struct dcn10_stream_enc_registers {
 	uint32_t DP_SEC_METADATA_TRANSMISSION;
 	uint32_t HDMI_METADATA_PACKET_CONTROL;
 	uint32_t DP_SEC_FRAMING4;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	uint32_t DP_GSP11_CNTL;
 	uint32_t HDMI_GENERIC_PACKET_CONTROL6;
 	uint32_t HDMI_GENERIC_PACKET_CONTROL7;
 	uint32_t HDMI_GENERIC_PACKET_CONTROL8;
 	uint32_t HDMI_GENERIC_PACKET_CONTROL9;
 	uint32_t HDMI_GENERIC_PACKET_CONTROL10;
-#endif
 	uint32_t DIG_CLOCK_PATTERN;
 };
 
@@ -505,7 +503,6 @@ struct dcn10_stream_enc_registers {
 	type DP_PIXEL_COMBINE;\
 	type DP_SST_SDP_SPLITTING
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #define SE_REG_FIELD_LIST_DCN3_0(type) \
 	type HDMI_GENERIC8_CONT;\
 	type HDMI_GENERIC8_SEND;\
@@ -531,22 +528,17 @@ struct dcn10_stream_enc_registers {
 	type DP_SEC_GSP11_PPS;\
 	type DP_SEC_GSP11_ENABLE;\
 	type DP_SEC_GSP11_LINE_NUM
-#endif
 
 struct dcn10_stream_encoder_shift {
 	SE_REG_FIELD_LIST_DCN1_0(uint8_t);
 	SE_REG_FIELD_LIST_DCN2_0(uint8_t);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	SE_REG_FIELD_LIST_DCN3_0(uint8_t);
-#endif
 };
 
 struct dcn10_stream_encoder_mask {
 	SE_REG_FIELD_LIST_DCN1_0(uint32_t);
 	SE_REG_FIELD_LIST_DCN2_0(uint32_t);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	SE_REG_FIELD_LIST_DCN3_0(uint32_t);
-#endif
 };
 
 struct dcn10_stream_encoder {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index 06daf35bb587..d407f33308b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -76,7 +76,6 @@
 	type REFCLK_CLOCK_EN;\
 	type REFCLK_SRC_SEL;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #define DCCG3_REG_FIELD_LIST(type) \
 	type PHYASYMCLK_FORCE_EN;\
 	type PHYASYMCLK_FORCE_SRC_SEL;\
@@ -84,32 +83,25 @@
 	type PHYBSYMCLK_FORCE_SRC_SEL;\
 	type PHYCSYMCLK_FORCE_EN;\
 	type PHYCSYMCLK_FORCE_SRC_SEL;
-#endif
 
 struct dccg_shift {
 	DCCG_REG_FIELD_LIST(uint8_t)
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	DCCG3_REG_FIELD_LIST(uint8_t)
-#endif
 };
 
 struct dccg_mask {
 	DCCG_REG_FIELD_LIST(uint32_t)
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	DCCG3_REG_FIELD_LIST(uint32_t)
-#endif
 };
 
 struct dccg_registers {
 	uint32_t DPPCLK_DTO_CTRL;
 	uint32_t DPPCLK_DTO_PARAM[6];
 	uint32_t REFCLK_CNTL;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	uint32_t HDMICHARCLK_CLOCK_CNTL[6];
 	uint32_t PHYASYMCLK_CLOCK_CNTL;
 	uint32_t PHYBSYMCLK_CLOCK_CNTL;
 	uint32_t PHYCSYMCLK_CLOCK_CNTL;
-#endif
 };
 
 struct dcn_dccg {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
index 69d49551ab5d..6d03d98fca22 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
@@ -153,10 +153,8 @@ bool hubbub2_dcc_support_pixel_format(
 	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
 	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
 	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
-#endif
 		*bytes_per_element = 4;
 		return true;
 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
@@ -343,11 +341,9 @@ static enum dcn_hubbub_page_table_block_size page_table_block_size_to_hw(unsigne
 	case 65536:
 		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_64KB;
 		break;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case 32768:
 		block_size = DCN_PAGE_TABLE_BLOCK_SIZE_32KB;
 		break;
-#endif
 	default:
 		ASSERT(false);
 		block_size = page_table_block_size;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index 368818d2dfc6..b7e44e53a342 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -336,10 +336,8 @@ void hubp2_program_size(
 	 */
 	use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
 		&& format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	use_pitch_c = use_pitch_c
 		|| (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
-#endif
 	if (use_pitch_c) {
 		ASSERT(plane_size->chroma_pitch != 0);
 		/* Chroma pitch zero can cause system hang! */
@@ -364,10 +362,8 @@ void hubp2_program_size(
 			PITCH, pitch, META_PITCH, meta_pitch);
 
 	use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	use_pitch_c = use_pitch_c
 		|| (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
-#endif
 	if (use_pitch_c)
 		REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
 			PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
@@ -513,7 +509,6 @@ void hubp2_program_pixel_format(
 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
 				SURFACE_PIXEL_FORMAT, 119);
 		break;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 				SURFACE_PIXEL_FORMAT, 116,
@@ -524,7 +519,6 @@ void hubp2_program_pixel_format(
 				SURFACE_PIXEL_FORMAT, 116,
 				ALPHA_PLANE_EN, 1);
 		break;
-#endif
 	default:
 		BREAK_TO_DEBUGGER();
 		break;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index 4a2c93087459..f501c02c244b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -157,11 +157,9 @@
 	uint32_t VBLANK_PARAMETERS_5;\
 	uint32_t VBLANK_PARAMETERS_6
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #define DCN30_HUBP_REG_COMMON_VARIABLE_LIST \
 	DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\
 	uint32_t DCN_DMDATA_VM_CNTL
-#endif
 
 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
 	DCN_HUBP_REG_FIELD_BASE_LIST(type); \
@@ -198,7 +196,6 @@
 	type REFCYC_PER_META_CHUNK_FLIP_C; \
 	type VM_GROUP_SIZE
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \
 	DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\
 	type PRIMARY_SURFACE_DCC_IND_BLK;\
@@ -218,32 +215,17 @@
 	type PACK_3TO2_ELEMENT_DISABLE; \
 	type ROW_TTU_MODE; \
 	type NUM_PKRS
-#endif
 
 struct dcn_hubp2_registers {
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;
-#else
-	DCN21_HUBP_REG_COMMON_VARIABLE_LIST;
-#endif
 };
 
 struct dcn_hubp2_shift {
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
-#else
-	DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
-#endif
-
 };
 
 struct dcn_hubp2_mask {
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
-#else
-	DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
-#endif
-
 };
 
 struct dcn20_hubp {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 01530e686f43..d8d45d860cb7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -611,7 +611,6 @@ void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 					pipe_ctx->pipe_idx);
 }
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
 		int opp_cnt)
 {
@@ -634,7 +633,6 @@ static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
 
 	return flow_ctrl_cnt;
 }
-#endif
 
 enum dc_status dcn20_enable_stream_timing(
 		struct pipe_ctx *pipe_ctx,
@@ -648,16 +646,12 @@ enum dc_status dcn20_enable_stream_timing(
 	struct pipe_ctx *odm_pipe;
 	int opp_cnt = 1;
 	int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
-
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	bool interlace = stream->timing.flags.INTERLACE;
 	int i;
-
 	struct mpc_dwb_flow_control flow_control;
 	struct mpc *mpc = dc->res_pool->mpc;
 	bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
 
-#endif
 	/* by upper caller loop, pipe0 is parent pipe and be called first.
 	 * back end is set up by for pipe0. Other children pipe share back end
 	 * with pipe 0. No program is needed.
@@ -704,7 +698,6 @@ enum dc_status dcn20_enable_stream_timing(
 			pipe_ctx->stream->signal,
 			true);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
 	flow_control.flow_ctrl_mode = 0;
 	flow_control.flow_ctrl_cnt0 = 0x80;
@@ -718,7 +711,7 @@ enum dc_status dcn20_enable_stream_timing(
 					&flow_control);
 		}
 	}
-#endif
+
 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 				odm_pipe->stream_res.opp,
@@ -1030,8 +1023,8 @@ void dcn20_blank_pixel_data(
 		test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
 	}
 
-	stream_res->opp->funcs->opp_set_disp_pattern_generator(
-			stream_res->opp,
+	dc->hwss.set_disp_pattern_generator(dc,
+			pipe_ctx,
 			test_pattern,
 			test_pattern_color_space,
 			stream->timing.display_color_depth,
@@ -1041,8 +1034,8 @@ void dcn20_blank_pixel_data(
 			0);
 
 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
-		odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
-				odm_pipe->stream_res.opp,
+		dc->hwss.set_disp_pattern_generator(dc,
+				odm_pipe,
 				dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
 						CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
 				test_pattern_color_space,
@@ -1158,6 +1151,7 @@ void dcn20_pipe_control_lock(
 	struct pipe_ctx *pipe,
 	bool lock)
 {
+	struct pipe_ctx *temp_pipe;
 	bool flip_immediate = false;
 
 	/* use TG master update lock to lock everything on the TG
@@ -1169,6 +1163,13 @@ void dcn20_pipe_control_lock(
 	if (pipe->plane_state != NULL)
 		flip_immediate = pipe->plane_state->flip_immediate;
 
+	temp_pipe = pipe->bottom_pipe;
+	while (!flip_immediate && temp_pipe) {
+	    if (temp_pipe->plane_state != NULL)
+		flip_immediate = temp_pipe->plane_state->flip_immediate;
+	    temp_pipe = temp_pipe->bottom_pipe;
+	}
+
 	if (flip_immediate && lock) {
 		const int TIMEOUT_FOR_FLIP_PENDING = 100000;
 		int i;
@@ -1191,11 +1192,25 @@ void dcn20_pipe_control_lock(
 	/* In flip immediate and pipe splitting case, we need to use GSL
 	 * for synchronization. Only do setup on locking and on flip type change.
 	 */
-	if (lock && pipe->bottom_pipe != NULL)
+	if (lock && (pipe->bottom_pipe != NULL || !flip_immediate))
 		if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
 		    (!flip_immediate && pipe->stream_res.gsl_group > 0))
 			dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
 
+	if (pipe->plane_state != NULL)
+		flip_immediate = pipe->plane_state->flip_immediate;
+
+	temp_pipe = pipe->bottom_pipe;
+	while (flip_immediate && temp_pipe) {
+	    if (temp_pipe->plane_state != NULL)
+		flip_immediate = temp_pipe->plane_state->flip_immediate;
+	    temp_pipe = temp_pipe->bottom_pipe;
+	}
+
+	if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state &&
+		!flip_immediate)
+	    dcn20_setup_gsl_group_as_lock(dc, pipe, false);
+
 	if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) {
 		union dmub_hw_lock_flags hw_locks = { 0 };
 		struct dmub_hw_lock_inst_flags inst_flags = { 0 };
@@ -1478,7 +1493,6 @@ static void dcn20_update_dchubp_dpp(
 	if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
 			|| pipe_ctx->stream->update_flags.bits.gamut_remap
 			|| pipe_ctx->stream->update_flags.bits.out_csc) {
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 		struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 
 		if (mpc->funcs->set_gamut_remap) {
@@ -1509,7 +1523,6 @@ static void dcn20_update_dchubp_dpp(
 			}
 			mpc->funcs->set_gamut_remap(mpc, mpcc_id, &adjust);
 		} else
-#endif
 			/* dpp/cm gamut remap*/
 			dc->hwss.program_gamut_remap(pipe_ctx);
 
@@ -2034,6 +2047,8 @@ static bool patch_address_for_sbs_tb_stereo(
 		plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
 		plane_state->address.grph_stereo.right_addr =
 				plane_state->address.grph_stereo.left_addr;
+		plane_state->address.grph_stereo.right_meta_addr =
+				plane_state->address.grph_stereo.left_meta_addr;
 	}
 	return false;
 }
@@ -2282,11 +2297,9 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	blnd_cfg.bottom_inside_gain = 0x1f000;
 	blnd_cfg.bottom_outside_gain = 0x1f000;
 	blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	if (pipe_ctx->plane_state->format
 			== SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
 		blnd_cfg.pre_multiplied_alpha = false;
-#endif
 
 	/*
 	 * TODO: remove hack
@@ -2545,3 +2558,15 @@ bool dcn20_optimize_timing_for_fsft(struct dc *dc,
 	return true;
 }
 #endif
+
+void dcn20_set_disp_pattern_generator(const struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		enum controller_dp_test_pattern test_pattern,
+		enum controller_dp_color_space color_space,
+		enum dc_color_depth color_depth,
+		const struct tg_color *solid_color,
+		int width, int height, int offset)
+{
+	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
+			color_space, color_depth, solid_color, width, height, offset);
+}
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index 83220e34c1a9..c69f766a40ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -137,5 +137,14 @@ bool dcn20_optimize_timing_for_fsft(struct dc *dc,
 		struct dc_crtc_timing *timing,
 		unsigned int max_input_rate_in_khz);
 #endif
+
+void dcn20_set_disp_pattern_generator(const struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		enum controller_dp_test_pattern test_pattern,
+		enum controller_dp_color_space color_space,
+		enum dc_color_depth color_depth,
+		const struct tg_color *solid_color,
+		int width, int height, int offset);
+
 #endif /* __DC_HWSS_DCN20_H__ */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index 072193c5ffe6..de9dcbeea150 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -34,7 +34,6 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 	.apply_ctx_for_surface = NULL,
 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
-	.disconnect_pipes = dcn10_disconnect_pipes,
 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
 	.update_plane_addr = dcn20_update_plane_addr,
@@ -94,6 +93,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
 #ifndef TRIM_FSFT
 	.optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,
 #endif
+	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
 };
 
 static const struct hwseq_private_funcs dcn20_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
index 864acd695cbb..b2b266953d18 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
@@ -276,10 +276,8 @@ struct mpll_cfg {
 	bool dp_tx1_vergdrv_byp;
 	bool dp_tx2_vergdrv_byp;
 	bool dp_tx3_vergdrv_byp;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	uint32_t tx_peaking_lvl;
 	uint32_t ctr_reqs_pll;
-#endif
 
 
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
index 138321e151eb..0784d0198661 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
@@ -290,6 +290,17 @@ void opp2_set_disp_pattern_generator(
 	}
 }
 
+void opp2_program_dpg_dimensions(
+		struct output_pixel_processor *opp,
+		int width, int height)
+{
+	struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
+
+	REG_SET_2(DPG_DIMENSIONS, 0,
+		DPG_ACTIVE_WIDTH, width,
+		DPG_ACTIVE_HEIGHT, height);
+}
+
 void opp2_dpg_set_blank_color(
 		struct output_pixel_processor *opp,
 		const struct tg_color *color)
@@ -350,6 +361,7 @@ static struct opp_funcs dcn20_opp_funcs = {
 		.opp_program_stereo = opp1_program_stereo,
 		.opp_pipe_clock_control = opp1_pipe_clock_control,
 		.opp_set_disp_pattern_generator = opp2_set_disp_pattern_generator,
+		.opp_program_dpg_dimensions = opp2_program_dpg_dimensions,
 		.dpg_is_blanked = opp2_dpg_is_blanked,
 		.opp_dpg_set_blank_color = opp2_dpg_set_blank_color,
 		.opp_destroy = opp1_destroy,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
index 64c5b429c79a..3ab221bdd27d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
@@ -153,6 +153,10 @@ void opp2_set_disp_pattern_generator(
 	int height,
 	int offset);
 
+void opp2_program_dpg_dimensions(
+		struct output_pixel_processor *opp,
+		int width, int height);
+
 bool opp2_dpg_is_blanked(struct output_pixel_processor *opp);
 
 void opp2_dpg_set_blank_color(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d50a9c370637..3fcc31d75792 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1882,9 +1882,16 @@ bool dcn20_split_stream_for_odm(
 		next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
 		next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
 	}
+	if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {
+		prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;
+		next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;
+	}
+	if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {
+		prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;
+		next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;
+	}
 	prev_odm_pipe->next_odm_pipe = next_odm_pipe;
 	next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
-	ASSERT(next_odm_pipe->top_pipe == NULL);
 
 	if (prev_odm_pipe->plane_state) {
 		struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
@@ -1922,7 +1929,10 @@ bool dcn20_split_stream_for_odm(
 				sd->ratios.horz_c, sd->h_active - sd->recout.x));
 		sd->recout.x = 0;
 	}
-	next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
+	if (!next_odm_pipe->top_pipe)
+		next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
+	else
+		next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;
 	if (next_odm_pipe->stream->timing.flags.DSC == 1) {
 		dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
 		ASSERT(next_odm_pipe->stream_res.dsc);
@@ -2033,10 +2043,8 @@ int dcn20_populate_dml_pipes_from_context(
 		unsigned int v_total;
 		unsigned int front_porch;
 		int output_bpc;
-
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 		struct audio_check aud_check = {0};
-#endif
+
 		if (!res_ctx->pipe_ctx[i].stream)
 			continue;
 
@@ -2091,11 +2099,9 @@ int dcn20_populate_dml_pipes_from_context(
 		case 1:
 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
 			break;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 		case 3:
 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
 			break;
-#endif
 		default:
 			pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
 		}
@@ -2201,11 +2207,9 @@ int dcn20_populate_dml_pipes_from_context(
 
 		/* todo: default max for now, until there is logic reflecting this in dc*/
 		pipes[pipe_cnt].dout.output_bpc = 12;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 		/*fill up the audio sample rate (unit in kHz)*/
 		get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
 		pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
-#endif
 		/*
 		 * For graphic plane, cursor number is 1, nv12 is 0
 		 * bw calculations due to cursor on/off
@@ -2252,13 +2256,10 @@ int dcn20_populate_dml_pipes_from_context(
 			if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
 				pipes[pipe_cnt].pipe.src.viewport_width /= 2;
 				pipes[pipe_cnt].pipe.dest.recout_width /= 2;
-			}
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-			else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
+			} else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
 				pipes[pipe_cnt].pipe.src.viewport_width /= 4;
 				pipes[pipe_cnt].pipe.dest.recout_width /= 4;
 			}
-#endif
 		} else {
 			struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
 			struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
@@ -2287,12 +2288,8 @@ int dcn20_populate_dml_pipes_from_context(
 			pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
 			pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
 			pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 			if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
 					|| pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-#else
-			if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-#endif
 				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
 				pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
 				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
@@ -2308,10 +2305,8 @@ int dcn20_populate_dml_pipes_from_context(
 			pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
 			if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
 				pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 			else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
 				pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
-#endif
 			else {
 				struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
 
@@ -2368,11 +2363,9 @@ int dcn20_populate_dml_pipes_from_context(
 			case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
 				pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
 				break;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 			case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 				pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
 				break;
-#endif
 			default:
 				pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
 				break;
@@ -2582,7 +2575,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
 	return secondary_pipe;
 }
 
-static void dcn20_merge_pipes_for_validate(
+void dcn20_merge_pipes_for_validate(
 		struct dc *dc,
 		struct dc_state *context)
 {
@@ -2749,7 +2742,6 @@ int dcn20_validate_apply_pipe_split_flags(
 			split[i] = 2;
 			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
 		}
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 		if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
 			split[i] = 4;
 			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
@@ -2759,7 +2751,6 @@ int dcn20_validate_apply_pipe_split_flags(
 				pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
 			split[i] = 4;
 		}
-#endif
 		v->ODMCombineEnabled[pipe_plane] =
 			v->ODMCombineEnablePerState[vlevel][pipe_plane];
 
@@ -3801,7 +3792,9 @@ static bool dcn20_resource_construct(
 
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
 	dc->caps.max_cursor_size = 256;
+	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.dmdata_alloc_size = 2048;
 
 	dc->caps.max_slave_planes = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index cdd39ee9761d..64bce14fefa3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -118,6 +118,9 @@ void dcn20_set_mcif_arb_params(
 		display_e2e_pipe_params_st *pipes,
 		int pipe_cnt);
 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
+void dcn20_merge_pipes_for_validate(
+		struct dc *dc,
+		struct dc_state *context);
 int dcn20_validate_apply_pipe_split_flags(
 		struct dc *dc,
 		struct dc_state *context,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
index 01f1d3d9a639..1fa193078803 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
@@ -223,3 +223,18 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
 	return true;
 }
 
+bool dcn21_is_abm_supported(struct dc *dc,
+		struct dc_state *context, struct dc_stream_state *stream)
+{
+	int i;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe_ctx->stream == stream &&
+				(pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))
+			return true;
+	}
+	return false;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
index 9e97747e57cd..9cee9bdb8de9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
@@ -52,5 +52,7 @@ void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);
 bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
 		uint32_t backlight_pwm_u16_16,
 		uint32_t frame_ramp);
+bool dcn21_is_abm_supported(struct dc *dc,
+		struct dc_state *context, struct dc_stream_state *stream);
 
 #endif /* __DC_HWSS_DCN21_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 2b7396c9fcb4..074e2713257f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -35,7 +35,6 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 	.apply_ctx_for_surface = NULL,
 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
-	.disconnect_pipes = dcn10_disconnect_pipes,
 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
 	.update_plane_addr = dcn20_update_plane_addr,
@@ -98,6 +97,8 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
 #ifndef TRIM_FSFT
 	.optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,
 #endif
+	.is_abm_supported = dcn21_is_abm_supported,
+	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
 };
 
 static const struct hwseq_private_funcs dcn21_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index e73785e74cba..5ae3419682c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -301,7 +301,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
 	.xfc_bus_transport_time_us = 4,
 	.xfc_xbuf_latency_tolerance_us = 4,
 	.use_urgent_burst_bw = 1,
-	.num_states = 8
+	.num_states = 8,
+	.allow_dram_self_refresh_or_dram_clock_change_in_vblank
+			= dm_allow_self_refresh_and_mclk_switch
 };
 
 #ifndef MAX
@@ -1154,12 +1156,12 @@ void dcn21_calculate_wm(
 						&context->bw_ctx.dml, pipes, pipe_cnt);
 	/* WM Set C */
 	table_entry = &bw_params->wm_table.entries[WM_C];
-	vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
+	vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
 						&context->bw_ctx.dml, pipes, pipe_cnt);
 	/* WM Set B */
 	table_entry = &bw_params->wm_table.entries[WM_B];
-	vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
+	vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
 						&context->bw_ctx.dml, pipes, pipe_cnt);
 
@@ -1171,6 +1173,138 @@ void dcn21_calculate_wm(
 }
 
 
+static bool dcn21_fast_validate_bw(
+		struct dc *dc,
+		struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int *pipe_cnt_out,
+		int *pipe_split_from,
+		int *vlevel_out)
+{
+	bool out = false;
+	int split[MAX_PIPES] = { 0 };
+	int pipe_cnt, i, pipe_idx, vlevel;
+
+	ASSERT(pipes);
+	if (!pipes)
+		return false;
+
+	dcn20_merge_pipes_for_validate(dc, context);
+
+	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
+
+	*pipe_cnt_out = pipe_cnt;
+
+	if (!pipe_cnt) {
+		out = true;
+		goto validate_out;
+	}
+
+	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+
+	if (vlevel > context->bw_ctx.dml.soc.num_states)
+		goto validate_fail;
+
+	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
+		struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
+
+		if (!pipe->stream)
+			continue;
+
+		/* We only support full screen mpo with ODM */
+		if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
+				&& pipe->plane_state && mpo_pipe
+				&& memcmp(&mpo_pipe->plane_res.scl_data.recout,
+						&pipe->plane_res.scl_data.recout,
+						sizeof(struct rect)) != 0) {
+			ASSERT(mpo_pipe->plane_state != pipe->plane_state);
+			goto validate_fail;
+		}
+		pipe_idx++;
+	}
+
+	/*initialize pipe_just_split_from to invalid idx*/
+	for (i = 0; i < MAX_PIPES; i++)
+		pipe_split_from[i] = -1;
+
+	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
+
+		if (!pipe->stream || pipe_split_from[i] >= 0)
+			continue;
+
+		pipe_idx++;
+
+		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
+			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
+			ASSERT(hsplit_pipe);
+			if (!dcn20_split_stream_for_odm(
+					dc, &context->res_ctx,
+					pipe, hsplit_pipe))
+				goto validate_fail;
+			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
+			dcn20_build_mapped_resource(dc, context, pipe->stream);
+		}
+
+		if (!pipe->plane_state)
+			continue;
+		/* Skip 2nd half of already split pipe */
+		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
+			continue;
+
+		if (split[i] == 2) {
+			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
+				/* pipe not split previously needs split */
+				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
+				ASSERT(hsplit_pipe);
+				if (!hsplit_pipe) {
+					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
+					continue;
+				}
+				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
+					if (!dcn20_split_stream_for_odm(
+							dc, &context->res_ctx,
+							pipe, hsplit_pipe))
+						goto validate_fail;
+					dcn20_build_mapped_resource(dc, context, pipe->stream);
+				} else {
+					dcn20_split_stream_for_mpc(
+							&context->res_ctx, dc->res_pool,
+							pipe, hsplit_pipe);
+					resource_build_scaling_params(pipe);
+					resource_build_scaling_params(hsplit_pipe);
+				}
+				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
+			}
+		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
+			/* merge should already have been done */
+			ASSERT(0);
+		}
+	}
+	/* Actual dsc count per stream dsc validation*/
+	if (!dcn20_validate_dsc(dc, context)) {
+		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
+				DML_FAIL_DSC_VALIDATION_FAILURE;
+		goto validate_fail;
+	}
+
+	*vlevel_out = vlevel;
+
+	out = true;
+	goto validate_out;
+
+validate_fail:
+	out = false;
+
+validate_out:
+	return out;
+}
+
 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
 		bool fast_validate)
 {
@@ -1189,7 +1323,7 @@ bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
 	/*Unsafe due to current pipe merge and split logic*/
 	ASSERT(context != dc->current_state);
 
-	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
+	out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
 
 	if (pipe_cnt == 0)
 		goto validate_out;
@@ -1385,95 +1519,89 @@ struct display_stream_compressor *dcn21_dsc_create(
 	return &dsc->base;
 }
 
+static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
+{
+	struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
+	int i;
+
+	low_pstate_lvl.state = 1;
+	low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
+	low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
+	low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
+	low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
+
+	low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz;
+	low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz;
+	low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps;
+	low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz;
+	low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz;
+	low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
+	low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
+
+	for (i = clk_table->num_entries; i > 1; i--)
+		clk_table->entries[i] = clk_table->entries[i-1];
+	clk_table->entries[1] = clk_table->entries[0];
+	clk_table->num_entries++;
+
+	return low_pstate_lvl;
+}
+
 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
 {
 	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
 	struct clk_limit_table *clk_table = &bw_params->clk_table;
 	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
-	unsigned int i, closest_clk_lvl;
+	unsigned int i, closest_clk_lvl = 0, k = 0;
 	int j;
 
-	// Default clock levels are used for diags, which may lead to overclocking.
-	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
-		dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
-		dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
-		dcn2_1_soc.num_chans = bw_params->num_channels;
-
-		ASSERT(clk_table->num_entries);
-		for (i = 0; i < clk_table->num_entries; i++) {
-			/* loop backwards*/
-			for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
-				if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
-					closest_clk_lvl = j;
-					break;
-				}
+	dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
+	dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
+	dcn2_1_soc.num_chans = bw_params->num_channels;
+
+	ASSERT(clk_table->num_entries);
+	for (i = 0; i < clk_table->num_entries; i++) {
+		/* loop backwards*/
+		for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
+			if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
+				closest_clk_lvl = j;
+				break;
 			}
-
-			clock_limits[i].state = i;
-			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
-			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
-			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
-			clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
-
-			clock_limits[i].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
-			clock_limits[i].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
-			clock_limits[i].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
-			clock_limits[i].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
-			clock_limits[i].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
-			clock_limits[i].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
-			clock_limits[i].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
-		}
-		for (i = 0; i < clk_table->num_entries; i++)
-			dcn2_1_soc.clock_limits[i] = clock_limits[i];
-		if (clk_table->num_entries) {
-			dcn2_1_soc.num_states = clk_table->num_entries;
-			/* duplicate last level */
-			dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
-			dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
 		}
+
+		/* clk_table[1] is reserved for min DF PState.  skip here to fill in later. */
+		if (i == 1)
+			k++;
+
+		clock_limits[k].state = k;
+		clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+		clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+		clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
+		clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
+
+		clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+		clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+		clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+		clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+		clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+		clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+		clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+
+		k++;
+	}
+	for (i = 0; i < clk_table->num_entries + 1; i++)
+		dcn2_1_soc.clock_limits[i] = clock_limits[i];
+	if (clk_table->num_entries) {
+		dcn2_1_soc.num_states = clk_table->num_entries + 1;
+		/* duplicate last level */
+		dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
+		dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
+		/* fill in min DF PState */
+		dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
 	}
 
 	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
 }
 
-/* Temporary Place holder until we can get them from fuse */
-static struct dpm_clocks dummy_clocks = {
-		.DcfClocks = {
-				{.Freq = 400, .Vol = 1},
-				{.Freq = 483, .Vol = 1},
-				{.Freq = 602, .Vol = 1},
-				{.Freq = 738, .Vol = 1} },
-		.SocClocks = {
-				{.Freq = 300, .Vol = 1},
-				{.Freq = 400, .Vol = 1},
-				{.Freq = 400, .Vol = 1},
-				{.Freq = 400, .Vol = 1} },
-		.FClocks = {
-				{.Freq = 400, .Vol = 1},
-				{.Freq = 800, .Vol = 1},
-				{.Freq = 1067, .Vol = 1},
-				{.Freq = 1600, .Vol = 1} },
-		.MemClocks = {
-				{.Freq = 800, .Vol = 1},
-				{.Freq = 1600, .Vol = 1},
-				{.Freq = 1067, .Vol = 1},
-				{.Freq = 1600, .Vol = 1} },
-
-};
-
-static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
-		struct pp_smu_wm_range_sets *ranges)
-{
-	return PP_SMU_RESULT_OK;
-}
-
-static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
-		struct dpm_clocks *clock_table)
-{
-	*clock_table = dummy_clocks;
-	return PP_SMU_RESULT_OK;
-}
-
 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
 {
 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
@@ -1481,17 +1609,11 @@ static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
 	if (!pp_smu)
 		return pp_smu;
 
-	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
-		pp_smu->ctx.ver = PP_SMU_VER_RN;
-		pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
-		pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
-	} else {
+	dm_pp_get_funcs(ctx, pp_smu);
 
-		dm_pp_get_funcs(ctx, pp_smu);
+	if (pp_smu->ctx.ver != PP_SMU_VER_RN)
+		pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
 
-		if (pp_smu->ctx.ver != PP_SMU_VER_RN)
-			pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
-	}
 
 	return pp_smu;
 }
@@ -1808,7 +1930,9 @@ static bool dcn21_resource_construct(
 
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
 	dc->caps.max_cursor_size = 256;
+	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.dmdata_alloc_size = 2048;
 
 	dc->caps.max_slave_planes = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
index bd2a068f9863..248c2711aace 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
@@ -52,6 +52,7 @@ IS_OLD_GCC = 1
 endif
 endif
 
+ifdef CONFIG_X86
 ifdef IS_OLD_GCC
 # Stack alignment mismatch, proceed with caution.
 # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
@@ -62,6 +63,7 @@ else
 CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o += -msse2
 CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o += -msse2
 endif
+endif
 
 AMD_DAL_DCN30 = $(addprefix $(AMDDALPATH)/dc/dcn30/,$(DCN30))
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index 0eb881f2e0d6..29231528f052 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -1358,16 +1358,9 @@ static struct dpp_funcs dcn30_dpp_funcs = {
 	.dpp_program_degamma_pwl	= NULL,
 	.dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
 	.dpp_program_cm_bias = dpp3_program_cm_bias,
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	.dpp_program_blnd_lut = dpp3_program_blnd_lut,
 	.dpp_program_shaper_lut = dpp3_program_shaper,
 	.dpp_program_3dlut = dpp3_program_3dlut,
-#else
-	.dpp_program_blnd_lut		= NULL,
-	.dpp_program_shaper_lut		= NULL,
-	.dpp_program_3dlut		= NULL,
-#endif
-
 	.dpp_program_bias_and_scale	= NULL,
 	.dpp_cnv_set_alpha_keyer	= dpp2_cnv_set_alpha_keyer,
 	.set_cursor_attributes		= dpp3_set_cursor_attributes,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index 7f6bedbc1ff1..81bf2ecc2831 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -585,7 +585,7 @@ void dpp3_cm_set_gamut_remap(
 		const struct dpp_grph_csc_adjustment *adjust);
 
 void dpp3_set_pre_degam(struct dpp *dpp_base,
-		uint32_t degamma_lut_selection);
+		enum dc_transfer_func_predefined tr);
 
 void dpp3_set_cursor_attributes(
 		struct dpp *dpp_base,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
index 982732dec133..c0980da6dc49 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
@@ -384,6 +384,58 @@ void hubbub3_force_wm_propagate_to_pipes(struct hubbub *hubbub)
 			DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value);
 }
 
+void hubbub3_force_pstate_change_control(struct hubbub *hubbub,
+		bool force, bool allow)
+{
+	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+
+	REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+			DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, allow,
+			DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, force);
+}
+
+/* Copy values from WM set A to all other sets */
+void hubbub3_init_watermarks(struct hubbub *hubbub)
+{
+	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t reg;
+
+	reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
+	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
+
+	reg = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, reg);
+	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg);
+}
+
 static const struct hubbub_funcs hubbub30_funcs = {
 	.update_dchub = hubbub2_update_dchub,
 	.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,
@@ -397,6 +449,8 @@ static const struct hubbub_funcs hubbub30_funcs = {
 	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
 	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
 	.force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,
+	.force_pstate_change_control = hubbub3_force_pstate_change_control,
+	.init_watermarks = hubbub3_init_watermarks,
 };
 
 void hubbub3_construct(struct dcn20_hubbub *hubbub3,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
index 790baa00672b..c0bd0fb09455 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
@@ -116,4 +116,9 @@ bool hubbub3_program_watermarks(
 		unsigned int refclk_mhz,
 		bool safe_to_lower);
 
+void hubbub3_force_pstate_change_control(struct hubbub *hubbub,
+		bool force, bool allow);
+
+void hubbub3_init_watermarks(struct hubbub *hubbub);
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
index fd1fb3c531d1..5fa150f34c60 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
@@ -251,6 +251,9 @@ bool hubp3_construct(
 		const struct dcn_hubp2_shift *hubp_shift,
 		const struct dcn_hubp2_mask *hubp_mask);
 
+void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
+	struct vm_system_aperture_param *apt);
+
 bool hubp3_program_surface_flip_and_addr(
 	struct hubp *hubp,
 	const struct dc_plane_address *address,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 204773ffc376..e76d6ab8d93a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -462,6 +462,12 @@ void dcn30_init_hw(struct dc *dc)
 		hws->funcs.disable_vga(dc->hwseq);
 	}
 
+	// Set default OPTC memory power states
+	if (dc->debug.enable_mem_low_power.bits.optc) {
+		// Shutdown when unassigned and light sleep in VBLANK
+		REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
+	}
+
 	if (dc->ctx->dc_bios->fw_info_valid) {
 		res_pool->ref_clocks.xtalin_clock_inKhz =
 				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
@@ -617,11 +623,18 @@ void dcn30_init_hw(struct dc *dc)
 	if (hws->funcs.enable_power_gating_plane)
 		hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 
+	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
+		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
+
 	if (dc->clk_mgr->funcs->notify_wm_ranges)
 		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 
 	if (dc->clk_mgr->funcs->set_hard_max_memclk)
 		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
+
+	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
+		dc->res_pool->hubbub->funcs->force_pstate_change_control(
+				dc->res_pool->hubbub, false, false);
 }
 
 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
@@ -689,6 +702,10 @@ void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
 
 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 {
+	union dmub_rb_cmd cmd;
+	unsigned int surface_size, refresh_hz, denom;
+	uint32_t tmr_delay = 0, tmr_scale = 0;
+
 	if (!dc->ctx->dmub_srv)
 		return false;
 
@@ -703,11 +720,110 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 					/* Fail eligibility on a visible stream */
 					break;
 			}
+
+			if (dc->current_state->stream_count == 1 // single display only
+			    && dc->current_state->stream_status[0].plane_count == 1 // single surface only
+			    && dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM
+			    // Only 8 and 16 bit formats
+			    && dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
+			    && dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) {
+				surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *
+					dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height *
+					(dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
+					 8 : 4);
+			} else {
+				// TODO: remove hard code size
+				surface_size = 128 * 1024 * 1024;
+			}
+
+			// TODO: remove hard code size
+			if (surface_size < 128 * 1024 * 1024) {
+				refresh_hz = div_u64((unsigned long long) dc->current_state->streams[0]->timing.pix_clk_100hz *
+						     100LL,
+						     (dc->current_state->streams[0]->timing.v_total *
+						      dc->current_state->streams[0]->timing.h_total));
+
+				/*
+				 * Delay_Us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
+				 * Delay_Us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
+				 * (Delay_Us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
+				 * MallFrameCacheTmrDly = ((Delay_Us / 65.28) / 2^MallFrameCacheTmrScale) - 64
+				 *                      = (1000000 / refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
+				 *                      = 1000000 / (refresh * 65.28 * 2^MallFrameCacheTmrScale) - 64
+				 *                      = (1000000 * 100) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
+				 *
+				 * need to round up the result of the division before the subtraction
+				 */
+				denom = refresh_hz * 6528;
+				tmr_delay = div_u64((100000000LL + denom - 1), denom) - 64LL;
+
+				/* scale should be increased until it fits into 6 bits */
+				while (tmr_delay & ~0x3F) {
+					tmr_scale++;
+
+					if (tmr_scale > 3) {
+						/* The delay exceeds the range of the hystersis timer */
+						ASSERT(false);
+						return false;
+					}
+
+					denom *= 2;
+					tmr_delay = div_u64((100000000LL + denom - 1), denom) - 64LL;
+				}
+
+				/* Enable MALL */
+				memset(&cmd, 0, sizeof(cmd));
+				cmd.mall.header.type = DMUB_CMD__MALL;
+				cmd.mall.header.sub_type =
+					DMUB_CMD__MALL_ACTION_ALLOW;
+				cmd.mall.header.payload_bytes =
+					sizeof(cmd.mall) -
+					sizeof(cmd.mall.header);
+				cmd.mall.tmr_delay = tmr_delay;
+				cmd.mall.tmr_scale = tmr_scale;
+
+				dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+				dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+
+				return true;
+			}
 		}
 
 		/* No applicable optimizations */
 		return false;
 	}
 
+	/* Disable MALL */
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.mall.header.type = DMUB_CMD__MALL;
+	cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
+	cmd.mall.header.payload_bytes =
+		sizeof(cmd.mall) - sizeof(cmd.mall.header);
+
+	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
+
 	return true;
 }
+
+void dcn30_hardware_release(struct dc *dc)
+{
+	/* if pstate unsupported, force it supported */
+	if (!dc->clk_mgr->clks.p_state_change_support &&
+			dc->res_pool->hubbub->funcs->force_pstate_change_control)
+		dc->res_pool->hubbub->funcs->force_pstate_change_control(
+				dc->res_pool->hubbub, true, true);
+}
+
+void dcn30_set_disp_pattern_generator(const struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		enum controller_dp_test_pattern test_pattern,
+		enum controller_dp_color_space color_space,
+		enum dc_color_depth color_depth,
+		const struct tg_color *solid_color,
+		int width, int height, int offset)
+{
+	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
+			color_space, color_depth, solid_color, width, height, 0);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
index a4989f5ac4e9..7d32c43aafe0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
@@ -67,4 +67,14 @@ void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
 
 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);
 
+void dcn30_hardware_release(struct dc *dc);
+
+void dcn30_set_disp_pattern_generator(const struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		enum controller_dp_test_pattern test_pattern,
+		enum controller_dp_color_space color_space,
+		enum dc_color_depth color_depth,
+		const struct tg_color *solid_color,
+		int width, int height, int offset);
+
 #endif /* __DC_HWSS_DCN30_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index 7c90c2222506..6125fe440ad0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -35,7 +35,6 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 	.apply_ctx_for_surface = NULL,
 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
-	.disconnect_pipes = dcn10_disconnect_pipes,
 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
 	.update_plane_addr = dcn20_update_plane_addr,
@@ -90,9 +89,13 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
 	.init_vm_ctx = dcn20_init_vm_ctx,
 	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
 	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+	.calc_vupdate_position = dcn10_calc_vupdate_position,
 	.apply_idle_power_optimizations = dcn30_apply_idle_power_optimizations,
 	.set_backlight_level = dcn21_set_backlight_level,
 	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
+	.hardware_release = dcn30_hardware_release,
+	.set_pipe = dcn21_set_pipe,
+	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
 };
 
 static const struct hwseq_private_funcs dcn30_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index 8fadd61a55ec..d7d053fc6e91 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -143,8 +143,16 @@ static void mpc3_power_on_ogam_lut(
 {
 	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
 
-	REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
-			MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
+	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
+		// Force power on
+		REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_DIS, power_on == true ? 1:0);
+		// Wait for confirmation when powering on
+		if (power_on)
+			REG_WAIT(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_STATE, 0, 10, 10);
+	} else {
+		REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
+				MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1);
+	}
 }
 
 static void mpc3_configure_ogam_lut(
@@ -360,6 +368,9 @@ void mpc3_set_output_gamma(
 	/*we need to program 2 fields here as apposed to 1*/
 	REG_UPDATE(MPCC_OGAM_CONTROL[mpcc_id],
 			MPCC_OGAM_SELECT, next_mode == LUT_RAM_A ? 0:1);
+
+	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
+		mpc3_power_on_ogam_lut(mpc, mpcc_id, false);
 }
 
 void mpc3_set_denorm(
@@ -801,16 +812,28 @@ static void mpc3_power_on_shaper_3dlut(
 	uint32_t power_status_shaper = 2;
 	uint32_t power_status_3dlut  = 2;
 	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+	int max_retries = 10;
 
 	if (rmu_idx == 0) {
 		REG_SET(MPC_RMU_MEM_PWR_CTRL, 0,
 			MPC_RMU0_MEM_PWR_DIS, power_on == true ? 1:0);
+		/* wait for memory to fully power up */
+		if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
+			REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
+			REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
+		}
+
 		/*read status is not mandatory, it is just for debugging*/
 		REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, &power_status_shaper);
 		REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
 	} else if (rmu_idx == 1) {
 		REG_SET(MPC_RMU_MEM_PWR_CTRL, 0,
 			MPC_RMU1_MEM_PWR_DIS, power_on == true ? 1:0);
+		if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
+			REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
+			REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
+		}
+
 		REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, &power_status_shaper);
 		REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
 	}
@@ -838,6 +861,10 @@ bool mpc3_program_shaper(
 		REG_SET(SHAPER_CONTROL[rmu_idx], 0, MPC_RMU_SHAPER_LUT_MODE, 0);
 		return false;
 	}
+
+	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
+		mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true);
+
 	current_mode = mpc3_get_shaper_current(mpc, rmu_idx);
 
 	if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
@@ -1196,6 +1223,9 @@ bool mpc3_program_3dlut(
 	mpc3_set_3dlut_mode(mpc, mode, is_12bits_color_channel,
 					is_17x17x17, rmu_idx);
 
+	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
+		mpc3_power_on_shaper_3dlut(mpc, rmu_idx, false);
+
 	return true;
 }
 
@@ -1349,11 +1379,31 @@ int mpcc3_release_rmu(struct mpc *mpc, int mpcc_id)
 
 }
 
+static void mpc3_mpc_init(struct mpc *mpc)
+{
+	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
+	int mpcc_id;
+
+	mpc1_mpc_init(mpc);
+
+	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
+		if (mpc30->mpc_mask->MPC_RMU0_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPC_RMU1_MEM_LOW_PWR_MODE) {
+			REG_UPDATE(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, 3);
+			REG_UPDATE(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_LOW_PWR_MODE, 3);
+		}
+
+		if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {
+			for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++)
+				REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);
+		}
+	}
+}
+
 const struct mpc_funcs dcn30_mpc_funcs = {
 	.read_mpcc_state = mpc1_read_mpcc_state,
 	.insert_plane = mpc1_insert_plane,
 	.remove_mpcc = mpc1_remove_mpcc,
-	.mpc_init = mpc1_mpc_init,
+	.mpc_init = mpc3_mpc_init,
 	.mpc_init_single_inst = mpc1_mpc_init_single_inst,
 	.update_blending = mpc2_update_blending,
 	.cursor_lock = mpc1_cursor_lock,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
index dfd3b9713df6..d1fd0b9aa0f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
@@ -300,6 +300,7 @@
 	SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
 	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
 	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
 	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
 	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
 	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
@@ -406,6 +407,8 @@
 	SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
 	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
 	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\
+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\
 	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
 	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
 	SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
@@ -492,10 +495,12 @@
 	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\
 	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\
 	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\
+	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\
 	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\
 	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\
 	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\
 	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\
+	SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_LOW_PWR_MODE, mask_sh),\
 	SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\
 	SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
 
@@ -519,10 +524,12 @@
 	type MPC_RMU1_MUX_STATUS; \
 	type MPC_RMU0_MEM_PWR_FORCE;\
 	type MPC_RMU0_MEM_PWR_DIS;\
+	type MPC_RMU0_MEM_LOW_PWR_MODE;\
 	type MPC_RMU0_SHAPER_MEM_PWR_STATE;\
 	type MPC_RMU0_3DLUT_MEM_PWR_STATE;\
 	type MPC_RMU1_MEM_PWR_FORCE;\
 	type MPC_RMU1_MEM_PWR_DIS;\
+	type MPC_RMU1_MEM_LOW_PWR_MODE;\
 	type MPC_RMU1_SHAPER_MEM_PWR_STATE;\
 	type MPC_RMU1_3DLUT_MEM_PWR_STATE;\
 	type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \
@@ -541,6 +548,8 @@
 	type MPCC_OGAM_LUT_CONFIG_MODE; \
 	type MPCC_OGAM_LUT_STATUS; \
 	type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\
+	type MPCC_OGAM_MEM_LOW_PWR_MODE;\
+	type MPCC_OGAM_MEM_PWR_STATE;\
 	type MPC_RMU_3DLUT_MODE; \
 	type MPC_RMU_3DLUT_SIZE; \
 	type MPC_RMU_3DLUT_MODE_CURRENT; \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 2455d210ccf6..01ac8b2921c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -60,6 +60,7 @@
 #include "dml/display_mode_vba.h"
 #include "dcn30/dcn30_dccg.h"
 #include "dcn10/dcn10_resource.h"
+#include "dc_link_ddc.h"
 #include "dce/dce_panel_cntl.h"
 
 #include "dcn30/dcn30_dwb.h"
@@ -354,11 +355,11 @@ static const struct dce_abm_registers abm_regs[] = {
 };
 
 static const struct dce_abm_shift abm_shift = {
-		ABM_MASK_SH_LIST_DCN301(__SHIFT)
+		ABM_MASK_SH_LIST_DCN30(__SHIFT)
 };
 
 static const struct dce_abm_mask abm_mask = {
-		ABM_MASK_SH_LIST_DCN301(_MASK)
+		ABM_MASK_SH_LIST_DCN30(_MASK)
 };
 
 
@@ -1321,6 +1322,9 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
 
 	if (pool->base.dccg != NULL)
 		dcn_dccg_destroy(&pool->base.dccg);
+
+	if (pool->base.oem_device != NULL)
+		dal_ddc_service_destroy(&pool->base.oem_device);
 }
 
 static struct hubp *dcn30_hubp_create(
@@ -1465,7 +1469,19 @@ int dcn30_populate_dml_pipes_from_context(
 	return pipe_cnt;
 }
 
-void dcn30_populate_dml_writeback_from_context(
+/*
+ * This must be noinline to ensure anything that deals with FP registers
+ * is contained within this call; previously our compiling with hard-float
+ * would result in fp instructions being emitted outside of the boundaries
+ * of the DC_FP_START/END macros, which makes sense as the compiler has no
+ * idea about what is wrapped and what is not
+ *
+ * This is largely just a workaround to avoid breakage introduced with 5.6,
+ * ideally all fp-using code should be moved into its own file, only that
+ * should be compiled with hard-float, and all code exported from there
+ * should be strictly wrapped with DC_FP_START/END
+ */
+static noinline void dcn30_populate_dml_writeback_from_context_fp(
 		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
 {
 	int pipe_cnt, i, j;
@@ -1554,6 +1570,14 @@ void dcn30_populate_dml_writeback_from_context(
 
 }
 
+void dcn30_populate_dml_writeback_from_context(
+		struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
+{
+	DC_FP_START();
+	dcn30_populate_dml_writeback_from_context_fp(dc, res_ctx, pipes);
+	DC_FP_END();
+}
+
 unsigned int dcn30_calc_max_scaled_time(
 		unsigned int time_per_pixel,
 		enum mmhubbub_wbif_mode mode,
@@ -1873,11 +1897,22 @@ static bool dcn30_split_stream_for_mpc_or_odm(
 			sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
 			sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
 		}
+		if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
+			pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
+			sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
+		}
+		if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
+			pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
+			sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
+		}
 		pri_pipe->next_odm_pipe = sec_pipe;
 		sec_pipe->prev_odm_pipe = pri_pipe;
 		ASSERT(sec_pipe->top_pipe == NULL);
 
-		sec_pipe->stream_res.opp = pool->opps[pipe_idx];
+		if (!sec_pipe->top_pipe)
+			sec_pipe->stream_res.opp = pool->opps[pipe_idx];
+		else
+			sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
 		if (sec_pipe->stream->timing.flags.DSC == 1) {
 			dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
 			ASSERT(sec_pipe->stream_res.dsc);
@@ -2005,20 +2040,6 @@ static bool dcn30_internal_validate_bw(
 
 	dml_log_mode_support_params(&context->bw_ctx.dml);
 
-	/* TODO: Need to check calculated vlevel why that fails validation of below resolutions */
-	if (context->res_ctx.pipe_ctx[0].stream != NULL) {
-		if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 640  && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 480)
-			vlevel = 0;
-		if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 800)
-			vlevel = 0;
-		if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 768)
-			vlevel = 0;
-		if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1024)
-			vlevel = 0;
-		if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 2048 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1536)
-			vlevel = 0;
-	}
-
 	if (vlevel == context->bw_ctx.dml.soc.num_states)
 		goto validate_fail;
 
@@ -2203,7 +2224,19 @@ validate_out:
 	return out;
 }
 
-void dcn30_calculate_wm_and_dlg(
+/*
+ * This must be noinline to ensure anything that deals with FP registers
+ * is contained within this call; previously our compiling with hard-float
+ * would result in fp instructions being emitted outside of the boundaries
+ * of the DC_FP_START/END macros, which makes sense as the compiler has no
+ * idea about what is wrapped and what is not
+ *
+ * This is largely just a workaround to avoid breakage introduced with 5.6,
+ * ideally all fp-using code should be moved into its own file, only that
+ * should be compiled with hard-float, and all code exported from there
+ * should be strictly wrapped with DC_FP_START/END
+ */
+static noinline void dcn30_calculate_wm_and_dlg_fp(
 		struct dc *dc, struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
 		int pipe_cnt,
@@ -2249,7 +2282,7 @@ void dcn30_calculate_wm_and_dlg(
 	/* Set D:
 	 * DCFCLK: Min Required
 	 * FCLK(proportional to UCLK): 1GHz or Max
-	 * sr_enter_exit = 4, sr_exit = 2us
+	 * MALL stutter, sr_enter_exit = 4, sr_exit = 2us
 	 */
 	/*
 	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
@@ -2304,7 +2337,7 @@ void dcn30_calculate_wm_and_dlg(
 		 * calculate DLG based on dummy p-state latency, and max out the set A p-state watermark
 		 */
 		context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
-		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0x13FFFF;
+		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
 	} else {
 		/* Set A:
 		 * DCFCLK: Min Required
@@ -2359,7 +2392,18 @@ void dcn30_calculate_wm_and_dlg(
 				dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
 }
 
-bool dcn30_validate_bandwidth(struct dc *dc,
+void dcn30_calculate_wm_and_dlg(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel)
+{
+	DC_FP_START();
+	dcn30_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
+	DC_FP_END();
+}
+
+static noinline bool dcn30_validate_bandwidth_fp(struct dc *dc,
 		struct dc_state *context,
 		bool fast_validate)
 {
@@ -2410,7 +2454,20 @@ validate_out:
 	return out;
 }
 
-static void get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
+bool dcn30_validate_bandwidth(struct dc *dc,
+		struct dc_state *context,
+		bool fast_validate)
+{
+	bool out;
+
+	DC_FP_START();
+	out = dcn30_validate_bandwidth_fp(dc, context, fast_validate);
+	DC_FP_END();
+
+	return out;
+}
+
+static noinline void get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
                                                        unsigned int *optimal_dcfclk,
                                                        unsigned int *optimal_fclk)
 {
@@ -2477,8 +2534,10 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
 
 		// Calculate optimal dcfclk for each uclk
 		for (i = 0; i < num_uclk_states; i++) {
+			DC_FP_START();
 			get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
 					&optimal_dcfclk_for_uclk[i], NULL);
+			DC_FP_END();
 			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
 				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
 			}
@@ -2580,6 +2639,9 @@ static bool dcn30_resource_construct(
 	int i;
 	struct dc_context *ctx = dc->ctx;
 	struct irq_service_init_data init_data;
+	struct ddc_service_init_data ddc_init_data;
+
+	DC_FP_START();
 
 	ctx->dc_bios->regs = &bios_regs;
 
@@ -2595,7 +2657,9 @@ static bool dcn30_resource_construct(
 	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
 	dc->caps.max_downscale_ratio = 600;
 	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
 	dc->caps.max_cursor_size = 256;
+	dc->caps.min_horizontal_blanking_period = 80;
 	dc->caps.dmdata_alloc_size = 2048;
 
 	dc->caps.max_slave_planes = 1;
@@ -2845,10 +2909,24 @@ static bool dcn30_resource_construct(
 
 	dc->cap_funcs = cap_funcs;
 
+	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
+		ddc_init_data.ctx = dc->ctx;
+		ddc_init_data.link = NULL;
+		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
+		ddc_init_data.id.enum_id = 0;
+		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
+		pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
+	} else {
+		pool->base.oem_device = NULL;
+	}
+
+	DC_FP_END();
+
 	return true;
 
 create_fail:
 
+	DC_FP_END();
 	dcn30_resource_destruct(pool);
 
 	return false;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/Makefile b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
new file mode 100644
index 000000000000..2fd5d34e4ba6
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/Makefile
@@ -0,0 +1,47 @@
+#
+# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved
+#
+#  All rights reserved.  This notice is intended as a precaution against
+#  inadvertent publication and does not imply publication or any waiver
+#  of confidentiality.  The year included in the foregoing notice is the
+#  year of creation of the work.
+#
+#  Authors: AMD
+#
+# Makefile for dcn30.
+
+DCN301 = dcn301_init.o dcn301_resource.o dcn301_dccg.o \
+		dcn301_dio_link_encoder.o dcn301_hwseq.o dcn301_panel_cntl.o dcn301_hubbub.o
+
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_ARM64
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -mgeneral-regs-only
+endif
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+endif
+
+ifdef CONFIG_X86
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o += -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o += -msse2
+endif
+endif
+
+AMD_DAL_DCN301 = $(addprefix $(AMDDALPATH)/dc/dcn301/,$(DCN301))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCN301)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
new file mode 100644
index 000000000000..420da414929c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dcn301_dccg.h"
+
+#define TO_DCN_DCCG(dccg)\
+	container_of(dccg, struct dcn_dccg, base)
+
+#define REG(reg) \
+	(dccg_dcn->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
+
+#define CTX \
+	dccg_dcn->base.ctx
+#define DC_LOGGER \
+	dccg->ctx->logger
+
+static const struct dccg_funcs dccg301_funcs = {
+	.update_dpp_dto = dccg2_update_dpp_dto,
+	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+	.dccg_init = dccg2_init
+};
+
+struct dccg *dccg301_create(
+	struct dc_context *ctx,
+	const struct dccg_registers *regs,
+	const struct dccg_shift *dccg_shift,
+	const struct dccg_mask *dccg_mask)
+{
+	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
+	struct dccg *base;
+
+	if (dccg_dcn == NULL) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	base = &dccg_dcn->base;
+	base->ctx = ctx;
+	base->funcs = &dccg301_funcs;
+
+	dccg_dcn->regs = regs;
+	dccg_dcn->dccg_shift = dccg_shift;
+	dccg_dcn->dccg_mask = dccg_mask;
+
+	return &dccg_dcn->base;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h
new file mode 100644
index 000000000000..73db962dbc03
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN301_DCCG_H__
+#define __DCN301_DCCG_H__
+
+#include "dcn20/dcn20_dccg.h"
+
+#define DCCG_REG_LIST_DCN301() \
+	SR(DPPCLK_DTO_CTRL),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
+	SR(REFCLK_CNTL)
+
+#define DCCG_MASK_SH_LIST_DCN301(mask_sh) \
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
+	DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
+	DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
+
+struct dccg *dccg301_create(
+	struct dc_context *ctx,
+	const struct dccg_registers *regs,
+	const struct dccg_shift *dccg_shift,
+	const struct dccg_mask *dccg_mask);
+
+struct dccg *dccg301_create(
+	struct dc_context *ctx,
+	const struct dccg_registers *regs,
+	const struct dccg_shift *dccg_shift,
+	const struct dccg_mask *dccg_mask);
+
+#endif //__DCN301_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c
new file mode 100644
index 000000000000..c9fbaed23965
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+
+#include "core_types.h"
+#include "link_encoder.h"
+#include "dcn301_dio_link_encoder.h"
+#include "stream_encoder.h"
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+#include "gpio_service_interface.h"
+
+#define CTX \
+	enc10->base.ctx
+#define DC_LOGGER \
+	enc10->base.ctx->logger
+
+#define REG(reg)\
+	(enc10->link_regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	enc10->link_shift->field_name, enc10->link_mask->field_name
+
+#define IND_REG(index) \
+	(enc10->link_regs->index)
+
+static const struct link_encoder_funcs dcn301_link_enc_funcs = {
+	.read_state = link_enc2_read_state,
+	.validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream,
+	.hw_init = enc3_hw_init,
+	.setup = dcn10_link_encoder_setup,
+	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+	.enable_dp_output = dcn20_link_encoder_enable_dp_output,
+	.enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
+	.disable_output = dcn10_link_encoder_disable_output,
+	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
+	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
+	.update_mst_stream_allocation_table = dcn10_link_encoder_update_mst_stream_allocation_table,
+	.psr_program_dp_dphy_fast_training = dcn10_psr_program_dp_dphy_fast_training,
+	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
+	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
+	.enable_hpd = dcn10_link_encoder_enable_hpd,
+	.disable_hpd = dcn10_link_encoder_disable_hpd,
+	.is_dig_enabled = dcn10_is_dig_enabled,
+	.destroy = dcn10_link_encoder_destroy,
+	.fec_set_enable = enc2_fec_set_enable,
+	.fec_set_ready = enc2_fec_set_ready,
+	.fec_is_active = enc2_fec_is_active,
+	.get_dig_frontend = dcn10_get_dig_frontend,
+	.get_dig_mode = dcn10_get_dig_mode,
+	.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
+	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
+};
+
+void dcn301_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask)
+{
+	struct bp_encoder_cap_info bp_cap_info = {0};
+	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+	enum bp_result result = BP_RESULT_OK;
+	struct dcn10_link_encoder *enc10 = &enc20->enc10;
+
+	enc10->base.funcs = &dcn301_link_enc_funcs;
+	enc10->base.ctx = init_data->ctx;
+	enc10->base.id = init_data->encoder;
+
+	enc10->base.hpd_source = init_data->hpd_source;
+	enc10->base.connector = init_data->connector;
+
+	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+
+	enc10->base.features = *enc_features;
+
+	enc10->base.transmitter = init_data->transmitter;
+
+	/* set the flag to indicate whether driver poll the I2C data pin
+	 * while doing the DP sink detect
+	 */
+
+/*	if (dal_adapter_service_is_feature_supported(as,
+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
+		enc10->base.features.flags.bits.
+			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
+
+	enc10->base.output_signals =
+		SIGNAL_TYPE_DVI_SINGLE_LINK |
+		SIGNAL_TYPE_DVI_DUAL_LINK |
+		SIGNAL_TYPE_LVDS |
+		SIGNAL_TYPE_DISPLAY_PORT |
+		SIGNAL_TYPE_DISPLAY_PORT_MST |
+		SIGNAL_TYPE_EDP |
+		SIGNAL_TYPE_HDMI_TYPE_A;
+
+	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
+	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
+	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
+	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
+	 * Prefer DIG assignment is decided by board design.
+	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
+	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
+	 * By this, adding DIGG should not hurt DCE 8.0.
+	 * This will let DCE 8.1 share DCE 8.0 as much as possible
+	 */
+
+	enc10->link_regs = link_regs;
+	enc10->aux_regs = aux_regs;
+	enc10->hpd_regs = hpd_regs;
+	enc10->link_shift = link_shift;
+	enc10->link_mask = link_mask;
+
+	switch (enc10->base.transmitter) {
+	case TRANSMITTER_UNIPHY_A:
+		enc10->base.preferred_engine = ENGINE_ID_DIGA;
+	break;
+	case TRANSMITTER_UNIPHY_B:
+		enc10->base.preferred_engine = ENGINE_ID_DIGB;
+	break;
+	case TRANSMITTER_UNIPHY_C:
+		enc10->base.preferred_engine = ENGINE_ID_DIGC;
+	break;
+	case TRANSMITTER_UNIPHY_D:
+		enc10->base.preferred_engine = ENGINE_ID_DIGD;
+	break;
+	case TRANSMITTER_UNIPHY_E:
+		enc10->base.preferred_engine = ENGINE_ID_DIGE;
+	break;
+	case TRANSMITTER_UNIPHY_F:
+		enc10->base.preferred_engine = ENGINE_ID_DIGF;
+	break;
+	case TRANSMITTER_UNIPHY_G:
+		enc10->base.preferred_engine = ENGINE_ID_DIGG;
+	break;
+	default:
+		ASSERT_CRITICAL(false);
+		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+	}
+
+	/* default to one to mirror Windows behavior */
+	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
+
+	result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
+						enc10->base.id, &bp_cap_info);
+
+	/* Override features with DCE-specific values */
+	if (result == BP_RESULT_OK) {
+		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
+				bp_cap_info.DP_HBR2_EN;
+		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
+				bp_cap_info.DP_HBR3_EN;
+		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
+		enc10->base.features.flags.bits.DP_IS_USB_C =
+				bp_cap_info.DP_IS_USB_C;
+	} else {
+		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
+				__func__,
+				result);
+	}
+	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
+		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h
new file mode 100644
index 000000000000..49f8d91d4951
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dio_link_encoder.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_LINK_ENCODER__DCN301_H__
+#define __DC_LINK_ENCODER__DCN301_H__
+
+#include "dcn20/dcn20_link_encoder.h"
+
+
+#define LE_DCN301_REG_LIST(id)\
+	SRI(DIG_BE_CNTL, DIG, id), \
+	SRI(DIG_BE_EN_CNTL, DIG, id), \
+	SRI(TMDS_CTL_BITS, DIG, id), \
+	SRI(TMDS_DCBALANCER_CONTROL, DIG, id), \
+	SRI(DP_CONFIG, DP, id), \
+	SRI(DP_DPHY_CNTL, DP, id), \
+	SRI(DP_DPHY_PRBS_CNTL, DP, id), \
+	SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
+	SRI(DP_DPHY_SYM0, DP, id), \
+	SRI(DP_DPHY_SYM1, DP, id), \
+	SRI(DP_DPHY_SYM2, DP, id), \
+	SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
+	SRI(DP_LINK_CNTL, DP, id), \
+	SRI(DP_LINK_FRAMING_CNTL, DP, id), \
+	SRI(DP_MSE_SAT0, DP, id), \
+	SRI(DP_MSE_SAT1, DP, id), \
+	SRI(DP_MSE_SAT2, DP, id), \
+	SRI(DP_MSE_SAT_UPDATE, DP, id), \
+	SRI(DP_SEC_CNTL, DP, id), \
+	SRI(DP_VID_STREAM_CNTL, DP, id), \
+	SRI(DP_DPHY_FAST_TRAINING, DP, id), \
+	SRI(DP_SEC_CNTL1, DP, id), \
+	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
+	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
+
+#define LINK_ENCODER_MASK_SH_LIST_DCN301(mask_sh) \
+	LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh),\
+	LE_SF(DIG0_TMDS_DCBALANCER_CONTROL, TMDS_SYNC_DCBAL_EN, mask_sh)
+
+#define DPCS_DCN301_MASK_SH_LIST(mask_sh)\
+	DPCS_DCN2_MASK_SH_LIST(mask_sh),\
+	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_HDMI_FRL_MODE, mask_sh),\
+	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_SWAP_10_BIT, mask_sh),\
+	LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT_18_BIT, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_TX_CLK_EN, mask_sh)
+
+void dcn301_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask);
+
+void enc3_hw_init(struct link_encoder *enc);
+
+#endif /* __DC_LINK_ENCODER__DCN301_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
new file mode 100644
index 000000000000..a0b96b3c083f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
@@ -0,0 +1,81 @@
+/*
+* Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dm_services.h"
+#include "dcn301_hubbub.h"
+#include "reg_helper.h"
+
+#define REG(reg)\
+	hubbub1->regs->reg
+#define DC_LOGGER \
+	hubbub1->base.ctx->logger
+#define CTX \
+	hubbub1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hubbub1->shifts->field_name, hubbub1->masks->field_name
+
+#define REG(reg)\
+	hubbub1->regs->reg
+
+#define CTX \
+	hubbub1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hubbub1->shifts->field_name, hubbub1->masks->field_name
+
+
+static const struct hubbub_funcs hubbub301_funcs = {
+	.update_dchub = hubbub2_update_dchub,
+	.init_dchub_sys_ctx = hubbub21_init_dchub,
+	.init_vm_ctx = hubbub2_init_vm_ctx,
+	.dcc_support_swizzle = hubbub3_dcc_support_swizzle,
+	.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
+	.get_dcc_compression_cap = hubbub3_get_dcc_compression_cap,
+	.wm_read_state = hubbub21_wm_read_state,
+	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
+	.program_watermarks = hubbub3_program_watermarks,
+	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
+	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
+	.force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,
+	.force_pstate_change_control = hubbub3_force_pstate_change_control,
+};
+
+void hubbub301_construct(struct dcn20_hubbub *hubbub3,
+	struct dc_context *ctx,
+	const struct dcn_hubbub_registers *hubbub_regs,
+	const struct dcn_hubbub_shift *hubbub_shift,
+	const struct dcn_hubbub_mask *hubbub_mask)
+{
+	hubbub3->base.ctx = ctx;
+	hubbub3->base.funcs = &hubbub301_funcs;
+	hubbub3->regs = hubbub_regs;
+	hubbub3->shifts = hubbub_shift;
+	hubbub3->masks = hubbub_mask;
+
+	hubbub3->debug_test_index_pstate = 0xB;
+	hubbub3->detile_buf_size = 184 * 1024; /* 184KB for DCN3 */
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.h
new file mode 100644
index 000000000000..b599f4475479
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef DAL_DC_DCN301_DCN301_HUBBUB_H_
+#define DAL_DC_DCN301_DCN301_HUBBUB_H_
+
+#include "dcn30/dcn30_hubbub.h"
+
+
+#define HUBBUB_REG_LIST_DCN301(id)\
+	HUBBUB_REG_LIST_DCN30(id), \
+	HUBBUB_HVM_REG_LIST()
+
+
+#define HUBBUB_MASK_SH_LIST_DCN301(mask_sh)\
+	HUBBUB_MASK_SH_LIST_DCN30(mask_sh), \
+	HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \
+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh), \
+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh), \
+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh), \
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh), \
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh), \
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh), \
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh), \
+	HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh), \
+	HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh), \
+	HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh), \
+	HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh), \
+	HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh), \
+	HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh)
+
+void hubbub301_construct(struct dcn20_hubbub *hubbub3,
+	struct dc_context *ctx,
+	const struct dcn_hubbub_registers *hubbub_regs,
+	const struct dcn_hubbub_shift *hubbub_shift,
+	const struct dcn_hubbub_mask *hubbub_mask);
+
+
+#endif /* DAL_DC_DCN301_DCN301_HUBBUB_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.c
new file mode 100644
index 000000000000..10bedb2ea62a
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "core_types.h"
+#include "dce/dce_hwseq.h"
+#include "dcn301_hwseq.h"
+#include "reg_helper.h"
+
+#define DC_LOGGER_INIT(logger)
+
+#define CTX \
+	hws->ctx
+#define REG(reg)\
+	hws->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hws->shifts->field_name, hws->masks->field_name
+
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.h
new file mode 100644
index 000000000000..aa3df3f77108
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hwseq.h
@@ -0,0 +1,32 @@
+/*
+* Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCN301_H__
+#define __DC_HWSS_DCN301_H__
+
+#include "hw_sequencer_private.h"
+
+
+#endif /* __DC_HWSS_DCN301_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
new file mode 100644
index 000000000000..bdad72140cbc
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn10/dcn10_hw_sequencer.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn21/dcn21_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dcn301_hwseq.h"
+
+static const struct hw_sequencer_funcs dcn301_funcs = {
+	.program_gamut_remap = dcn10_program_gamut_remap,
+	.init_hw = dcn10_init_hw,
+	.power_down_on_boot = dcn10_power_down_on_boot,
+	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+	.apply_ctx_for_surface = NULL,
+	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
+	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
+	.update_plane_addr = dcn20_update_plane_addr,
+	.update_dchub = dcn10_update_dchub,
+	.update_pending_status = dcn10_update_pending_status,
+	.program_output_csc = dcn20_program_output_csc,
+	.enable_accelerated_mode = dce110_enable_accelerated_mode,
+	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
+	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+	.update_info_frame = dcn30_update_info_frame,
+	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
+	.enable_stream = dcn20_enable_stream,
+	.disable_stream = dce110_disable_stream,
+	.unblank_stream = dcn20_unblank_stream,
+#ifdef FREESYNC_POWER_OPTIMIZE
+	.are_streams_coarse_grain_aligned = dcn20_are_streams_coarse_grain_aligned,
+#endif
+	.blank_stream = dce110_blank_stream,
+	.enable_audio_stream = dce110_enable_audio_stream,
+	.disable_audio_stream = dce110_disable_audio_stream,
+	.disable_plane = dcn20_disable_plane,
+	.pipe_control_lock = dcn20_pipe_control_lock,
+	.interdependent_update_lock = dcn10_lock_all_pipes,
+	.cursor_lock = dcn10_cursor_lock,
+	.prepare_bandwidth = dcn20_prepare_bandwidth,
+	.optimize_bandwidth = dcn20_optimize_bandwidth,
+	.update_bandwidth = dcn20_update_bandwidth,
+	.set_drr = dcn10_set_drr,
+	.get_position = dcn10_get_position,
+	.set_static_screen_control = dcn10_set_static_screen_control,
+	.setup_stereo = dcn10_setup_stereo,
+	.set_avmute = dcn30_set_avmute,
+	.log_hw_state = dcn10_log_hw_state,
+	.get_hw_state = dcn10_get_hw_state,
+	.clear_status_bits = dcn10_clear_status_bits,
+	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+	.edp_power_control = dce110_edp_power_control,
+	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+	.set_cursor_position = dcn10_set_cursor_position,
+	.set_cursor_attribute = dcn10_set_cursor_attribute,
+	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+	.set_clock = dcn10_set_clock,
+	.get_clock = dcn10_get_clock,
+	.program_triplebuffer = dcn20_program_triple_buffer,
+	.enable_writeback = dcn30_enable_writeback,
+	.disable_writeback = dcn30_disable_writeback,
+	.update_writeback = dcn30_update_writeback,
+	.mmhubbub_warmup = dcn30_mmhubbub_warmup,
+	.dmdata_status_done = dcn20_dmdata_status_done,
+	.program_dmdata_engine = dcn30_program_dmdata_engine,
+	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
+	.init_sys_ctx = dcn20_init_sys_ctx,
+	.init_vm_ctx = dcn20_init_vm_ctx,
+	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
+	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+	.calc_vupdate_position = dcn10_calc_vupdate_position,
+	.set_backlight_level = dcn21_set_backlight_level,
+	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
+	.set_pipe = dcn21_set_pipe,
+	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+};
+
+static const struct hwseq_private_funcs dcn301_private_funcs = {
+	.init_pipes = dcn10_init_pipes,
+	.update_plane_addr = dcn20_update_plane_addr,
+	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+	.update_mpcc = dcn20_update_mpcc,
+	.set_input_transfer_func = dcn30_set_input_transfer_func,
+	.set_output_transfer_func = dcn30_set_output_transfer_func,
+	.power_down = dce110_power_down,
+	.enable_display_power_gating = dcn10_dummy_display_power_gating,
+	.blank_pixel_data = dcn20_blank_pixel_data,
+	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
+	.enable_stream_timing = dcn20_enable_stream_timing,
+	.edp_backlight_control = dce110_edp_backlight_control,
+	.disable_stream_gating = dcn20_disable_stream_gating,
+	.enable_stream_gating = dcn20_enable_stream_gating,
+	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+	.did_underflow_occur = dcn10_did_underflow_occur,
+	.init_blank = dcn20_init_blank,
+	.disable_vga = dcn20_disable_vga,
+	.bios_golden_init = dcn10_bios_golden_init,
+	.plane_atomic_disable = dcn20_plane_atomic_disable,
+	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
+	.enable_power_gating_plane = dcn20_enable_power_gating_plane,
+	.dpp_pg_control = dcn20_dpp_pg_control,
+	.hubp_pg_control = dcn20_hubp_pg_control,
+	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
+	.update_odm = dcn20_update_odm,
+	.dsc_pg_control = dcn20_dsc_pg_control,
+	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
+	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
+	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
+	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
+	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
+	.dccg_init = dcn20_dccg_init,
+	.set_blend_lut = dcn30_set_blend_lut,
+	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
+};
+
+void dcn301_hw_sequencer_construct(struct dc *dc)
+{
+	dc->hwss = dcn301_funcs;
+	dc->hwseq->funcs = dcn301_private_funcs;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.h
new file mode 100644
index 000000000000..0bca48ccbfa2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DCN30_INIT_H__
+#define __DC_DCN30_INIT_H__
+
+struct dc;
+
+void dcn301_hw_sequencer_construct(struct dc *dc);
+
+#endif /* __DC_DCN30_INIT_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
new file mode 100644
index 000000000000..736bda30abc3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dc_dmub_srv.h"
+#include "dcn301_panel_cntl.h"
+#include "atom.h"
+
+#define TO_DCN301_PANEL_CNTL(panel_cntl)\
+	container_of(panel_cntl, struct dcn301_panel_cntl, base)
+
+#define CTX \
+	dcn301_panel_cntl->base.ctx
+
+#define DC_LOGGER \
+	dcn301_panel_cntl->base.ctx->logger
+
+#define REG(reg)\
+	dcn301_panel_cntl->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+	dcn301_panel_cntl->shift->field_name, dcn301_panel_cntl->mask->field_name
+
+static unsigned int dcn301_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
+{
+	uint64_t current_backlight;
+	uint32_t round_result;
+	uint32_t bl_period, bl_int_count;
+	uint32_t bl_pwm, fractional_duty_cycle_en;
+	uint32_t bl_period_mask, bl_pwm_mask;
+	struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
+
+	REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
+	REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
+
+	REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &bl_pwm);
+	REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
+
+	if (bl_int_count == 0)
+		bl_int_count = 16;
+
+	bl_period_mask = (1 << bl_int_count) - 1;
+	bl_period &= bl_period_mask;
+
+	bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
+
+	if (fractional_duty_cycle_en == 0)
+		bl_pwm &= bl_pwm_mask;
+	else
+		bl_pwm &= 0xFFFF;
+
+	current_backlight = (uint64_t)bl_pwm << (1 + bl_int_count);
+
+	if (bl_period == 0)
+		bl_period = 0xFFFF;
+
+	current_backlight = div_u64(current_backlight, bl_period);
+	current_backlight = (current_backlight + 1) >> 1;
+
+	current_backlight = (uint64_t)(current_backlight) * bl_period;
+
+	round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
+
+	round_result = (round_result >> (bl_int_count-1)) & 1;
+
+	current_backlight >>= bl_int_count;
+	current_backlight += round_result;
+
+	return (uint32_t)(current_backlight);
+}
+
+uint32_t dcn301_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
+{
+	struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
+	uint32_t value;
+	uint32_t current_backlight;
+
+	/* It must not be 0, so we have to restore them
+	 * Bios bug w/a - period resets to zero,
+	 * restoring to cache values which is always correct
+	 */
+	REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
+
+	if (value == 0 || value == 1) {
+		if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) {
+			REG_WRITE(BL_PWM_CNTL,
+					panel_cntl->stored_backlight_registers.BL_PWM_CNTL);
+			REG_WRITE(BL_PWM_CNTL2,
+					panel_cntl->stored_backlight_registers.BL_PWM_CNTL2);
+			REG_WRITE(BL_PWM_PERIOD_CNTL,
+					panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
+			REG_UPDATE(PWRSEQ_REF_DIV,
+				BL_PWM_REF_DIV,
+				panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
+		} else {
+			/* TODO: Note: This should not really happen since VBIOS
+			 * should have initialized PWM registers on boot.
+			 */
+			REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
+			REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
+		}
+	} else {
+		panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
+				REG_READ(BL_PWM_CNTL);
+		panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
+				REG_READ(BL_PWM_CNTL2);
+		panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
+				REG_READ(BL_PWM_PERIOD_CNTL);
+
+		REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
+				&panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
+	}
+
+	// Enable the backlight output
+	REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
+
+	// Unlock group 2 backlight registers
+	REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
+			BL_PWM_GRP1_REG_LOCK, 0);
+
+	current_backlight = dcn301_get_16_bit_backlight_from_pwm(panel_cntl);
+
+	return current_backlight;
+}
+
+void dcn301_panel_cntl_destroy(struct panel_cntl **panel_cntl)
+{
+	struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(*panel_cntl);
+
+	kfree(dcn301_panel_cntl);
+	*panel_cntl = NULL;
+}
+
+bool dcn301_is_panel_backlight_on(struct panel_cntl *panel_cntl)
+{
+	struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
+	uint32_t value;
+
+	REG_GET(PWRSEQ_CNTL, PANEL_BLON, &value);
+
+	return value;
+}
+
+bool dcn301_is_panel_powered_on(struct panel_cntl *panel_cntl)
+{
+	struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
+	uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
+
+	REG_GET(PWRSEQ_STATE, PANEL_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
+
+	REG_GET_2(PWRSEQ_CNTL, PANEL_DIGON, &dig_on, PANEL_DIGON_OVRD, &dig_on_ovrd);
+
+	return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
+}
+
+void dcn301_store_backlight_level(struct panel_cntl *panel_cntl)
+{
+	struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
+
+	panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
+		REG_READ(BL_PWM_CNTL);
+	panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
+		REG_READ(BL_PWM_CNTL2);
+	panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
+		REG_READ(BL_PWM_PERIOD_CNTL);
+
+	REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
+		&panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
+}
+
+static const struct panel_cntl_funcs dcn301_link_panel_cntl_funcs = {
+	.destroy = dcn301_panel_cntl_destroy,
+	.hw_init = dcn301_panel_cntl_hw_init,
+	.is_panel_backlight_on = dcn301_is_panel_backlight_on,
+	.is_panel_powered_on = dcn301_is_panel_powered_on,
+	.store_backlight_level = dcn301_store_backlight_level,
+	.get_current_backlight = dcn301_get_16_bit_backlight_from_pwm,
+};
+
+void dcn301_panel_cntl_construct(
+	struct dcn301_panel_cntl *dcn301_panel_cntl,
+	const struct panel_cntl_init_data *init_data,
+	const struct dce_panel_cntl_registers *regs,
+	const struct dcn301_panel_cntl_shift *shift,
+	const struct dcn301_panel_cntl_mask *mask)
+{
+	dcn301_panel_cntl->regs = regs;
+	dcn301_panel_cntl->shift = shift;
+	dcn301_panel_cntl->mask = mask;
+
+	dcn301_panel_cntl->base.funcs = &dcn301_link_panel_cntl_funcs;
+	dcn301_panel_cntl->base.ctx = init_data->ctx;
+	dcn301_panel_cntl->base.inst = init_data->inst;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h
new file mode 100644
index 000000000000..ffc875da7467
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_PANEL_CNTL__DCN301_H__
+#define __DC_PANEL_CNTL__DCN301_H__
+
+#include "panel_cntl.h"
+#include "dce/dce_panel_cntl.h"
+
+
+#define DCN301_PANEL_CNTL_REG_LIST(id)\
+	SRIR(PWRSEQ_CNTL, CNTL, PANEL_PWRSEQ, id), \
+	SRIR(PWRSEQ_STATE, STATE, PANEL_PWRSEQ, id), \
+	SRIR(PWRSEQ_REF_DIV, REF_DIV, PANEL_PWRSEQ, id), \
+	SRIR(BL_PWM_CNTL, CNTL, BL_PWM, id), \
+	SRIR(BL_PWM_CNTL2, CNTL2, BL_PWM, id), \
+	SRIR(BL_PWM_PERIOD_CNTL, PERIOD_CNTL, BL_PWM, id), \
+	SRIR(BL_PWM_GRP1_REG_LOCK, GRP1_REG_LOCK, BL_PWM, id)
+
+#define DCN301_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+#define DCN301_PANEL_CNTL_MASK_SH_LIST(mask_sh) \
+	DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\
+	DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\
+	DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\
+	DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh), \
+	DCN301_PANEL_CNTL_SF(PANEL_PWRSEQ0_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
+	DCN301_PANEL_CNTL_SF(BL_PWM0_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
+	DCN301_PANEL_CNTL_SF(BL_PWM0_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
+	DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
+	DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
+	DCN301_PANEL_CNTL_SF(BL_PWM0_CNTL, BL_PWM_EN, mask_sh), \
+	DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
+	DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
+	DCN301_PANEL_CNTL_SF(BL_PWM0_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh)
+
+#define DCN301_PANEL_CNTL_REG_FIELD_LIST(type) \
+	type PANEL_BLON;\
+	type PANEL_DIGON;\
+	type PANEL_DIGON_OVRD;\
+	type PANEL_PWRSEQ_TARGET_STATE_R; \
+	type BL_PWM_EN; \
+	type BL_ACTIVE_INT_FRAC_CNT; \
+	type BL_PWM_FRACTIONAL_EN; \
+	type BL_PWM_PERIOD; \
+	type BL_PWM_PERIOD_BITCNT; \
+	type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
+	type BL_PWM_GRP1_REG_LOCK; \
+	type BL_PWM_GRP1_REG_UPDATE_PENDING; \
+	type BL_PWM_REF_DIV
+
+struct dcn301_panel_cntl_shift {
+	DCN301_PANEL_CNTL_REG_FIELD_LIST(uint8_t);
+};
+
+struct dcn301_panel_cntl_mask {
+	DCN301_PANEL_CNTL_REG_FIELD_LIST(uint32_t);
+};
+
+struct dcn301_panel_cntl {
+	struct panel_cntl base;
+	const struct dce_panel_cntl_registers *regs;
+	const struct dcn301_panel_cntl_shift *shift;
+	const struct dcn301_panel_cntl_mask *mask;
+};
+
+void dcn301_panel_cntl_construct(
+	struct dcn301_panel_cntl *panel_cntl,
+	const struct panel_cntl_init_data *init_data,
+	const struct dce_panel_cntl_registers *regs,
+	const struct dcn301_panel_cntl_shift *shift,
+	const struct dcn301_panel_cntl_mask *mask);
+
+#endif /* __DC_PANEL_CNTL__DCN301_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
new file mode 100644
index 000000000000..5a47b4106b7b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -0,0 +1,2011 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dm_services.h"
+#include "dc.h"
+
+#include "dcn301_init.h"
+
+#include "resource.h"
+#include "include/irq_service_interface.h"
+#include "dcn30/dcn30_resource.h"
+#include "dcn301_resource.h"
+
+#include "dcn20/dcn20_resource.h"
+
+#include "dcn10/dcn10_ipp.h"
+#include "dcn301/dcn301_hubbub.h"
+#include "dcn30/dcn30_mpc.h"
+#include "dcn30/dcn30_hubp.h"
+#include "irq/dcn30/irq_service_dcn30.h"
+#include "dcn30/dcn30_dpp.h"
+#include "dcn30/dcn30_optc.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn30/dcn30_opp.h"
+#include "dcn20/dcn20_dsc.h"
+#include "dcn30/dcn30_vpg.h"
+#include "dcn30/dcn30_afmt.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
+#include "clk_mgr.h"
+#include "virtual/virtual_stream_encoder.h"
+#include "dce110/dce110_resource.h"
+#include "dml/display_mode_vba.h"
+#include "dcn301/dcn301_dccg.h"
+#include "dcn10/dcn10_resource.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn301/dcn301_dio_link_encoder.h"
+#include "dcn301_panel_cntl.h"
+
+#include "vangogh_ip_offset.h"
+
+#include "dcn30/dcn30_dwb.h"
+#include "dcn30/dcn30_mmhubbub.h"
+
+#include "dcn/dcn_3_0_1_offset.h"
+#include "dcn/dcn_3_0_1_sh_mask.h"
+
+#include "nbio/nbio_7_2_0_offset.h"
+
+#include "reg_helper.h"
+#include "dce/dmub_abm.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_i2c.h"
+
+#include "dml/dcn30/display_mode_vba_30.h"
+#include "vm_helper.h"
+#include "dcn20/dcn20_vmid.h"
+#include "amdgpu_socbb.h"
+
+#define TO_DCN301_RES_POOL(pool)\
+	container_of(pool, struct dcn301_resource_pool, base)
+
+#define DC_LOGGER_INIT(logger)
+
+struct _vcs_dpi_ip_params_st dcn3_01_ip = {
+	.odm_capable = 1,
+	.gpuvm_enable = 1,
+	.hostvm_enable = 1,
+	.gpuvm_max_page_table_levels = 1,
+	.hostvm_max_page_table_levels = 2,
+	.hostvm_cached_page_table_levels = 0,
+	.pte_group_size_bytes = 2048,
+	.num_dsc = 3,
+	.rob_buffer_size_kbytes = 184,
+	.det_buffer_size_kbytes = 184,
+	.dpte_buffer_size_in_pte_reqs_luma = 64,
+	.dpte_buffer_size_in_pte_reqs_chroma = 32,
+	.pde_proc_buffer_size_64k_reqs = 48,
+	.dpp_output_buffer_pixels = 2560,
+	.opp_output_buffer_lines = 1,
+	.pixel_chunk_size_kbytes = 8,
+	.meta_chunk_size_kbytes = 2,
+	.writeback_chunk_size_kbytes = 8,
+	.line_buffer_size_bits = 789504,
+	.is_line_buffer_bpp_fixed = 0,  // ?
+	.line_buffer_fixed_bpp = 48,     // ?
+	.dcc_supported = true,
+	.writeback_interface_buffer_size_kbytes = 90,
+	.writeback_line_buffer_buffer_size = 656640,
+	.max_line_buffer_lines = 12,
+	.writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
+	.writeback_chroma_buffer_size_kbytes = 8,
+	.writeback_chroma_line_buffer_width_pixels = 4,
+	.writeback_max_hscl_ratio = 1,
+	.writeback_max_vscl_ratio = 1,
+	.writeback_min_hscl_ratio = 1,
+	.writeback_min_vscl_ratio = 1,
+	.writeback_max_hscl_taps = 1,
+	.writeback_max_vscl_taps = 1,
+	.writeback_line_buffer_luma_buffer_size = 0,
+	.writeback_line_buffer_chroma_buffer_size = 14643,
+	.cursor_buffer_size = 8,
+	.cursor_chunk_size = 2,
+	.max_num_otg = 4,
+	.max_num_dpp = 4,
+	.max_num_wb = 1,
+	.max_dchub_pscl_bw_pix_per_clk = 4,
+	.max_pscl_lb_bw_pix_per_clk = 2,
+	.max_lb_vscl_bw_pix_per_clk = 4,
+	.max_vscl_hscl_bw_pix_per_clk = 4,
+	.max_hscl_ratio = 6,
+	.max_vscl_ratio = 6,
+	.hscl_mults = 4,
+	.vscl_mults = 4,
+	.max_hscl_taps = 8,
+	.max_vscl_taps = 8,
+	.dispclk_ramp_margin_percent = 1,
+	.underscan_factor = 1.11,
+	.min_vblank_lines = 32,
+	.dppclk_delay_subtotal = 46,
+	.dynamic_metadata_vm_enabled = true,
+	.dppclk_delay_scl_lb_only = 16,
+	.dppclk_delay_scl = 50,
+	.dppclk_delay_cnvc_formatter = 27,
+	.dppclk_delay_cnvc_cursor = 6,
+	.dispclk_delay_subtotal = 119,
+	.dcfclk_cstate_latency = 5.2, // SRExitTime
+	.max_inter_dcn_tile_repeaters = 8,
+	.max_num_hdmi_frl_outputs = 0,
+	.odm_combine_4to1_supported = true,
+
+	.xfc_supported = false,
+	.xfc_fill_bw_overhead_percent = 10.0,
+	.xfc_fill_constant_bytes = 0,
+	.gfx7_compat_tiling_supported = 0,
+	.number_of_cursors = 1,
+};
+
+struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
+	.clock_limits = {
+			/*TODO: fill out defaults once wm plociy is settled*/
+			{
+				.state = 0,
+				.dcfclk_mhz = 810.0,
+				.fabricclk_mhz = 1200.0,
+				.dispclk_mhz = 1015.0,
+				.dppclk_mhz = 1015.0,
+				.phyclk_mhz = 810.0,
+				.socclk_mhz = 1000.0,
+				.dscclk_mhz = 338.0,
+				.dram_speed_mts = 4266.0,
+			},
+			{
+				.state = 1,
+				.dcfclk_mhz = 810.0,
+				.fabricclk_mhz = 1200.0,
+				.dispclk_mhz = 1015.0,
+				.dppclk_mhz = 1015.0,
+				.phyclk_mhz = 810.0,
+				.socclk_mhz = 1000.0,
+				.dscclk_mhz = 338.0,
+				.dram_speed_mts = 4266.0,
+			}
+		},
+
+	.sr_exit_time_us = 9.0,
+	.sr_enter_plus_exit_time_us = 11.0,
+	.urgent_latency_us = 4.0,
+	.urgent_latency_pixel_data_only_us = 4.0,
+	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+	.urgent_latency_vm_data_only_us = 4.0,
+	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
+	.max_avg_sdp_bw_use_normal_percent = 60.0,
+	.max_avg_dram_bw_use_normal_percent = 60.0,
+	.writeback_latency_us = 12.0,
+	.max_request_size_bytes = 256,
+	.dram_channel_width_bytes = 4,
+	.fabric_datapath_to_dcn_data_return_bytes = 32,
+	.dcn_downspread_percent = 0.5,
+	.downspread_percent = 0.38,
+	.dram_page_open_time_ns = 50.0,
+	.dram_rw_turnaround_time_ns = 17.5,
+	.dram_return_buffer_per_channel_bytes = 8192,
+	.round_trip_ping_latency_dcfclk_cycles = 191,
+	.urgent_out_of_order_return_per_channel_bytes = 4096,
+	.channel_interleave_bytes = 256,
+	.num_banks = 8,
+	.num_chans = 4,
+	.gpuvm_min_page_size_bytes = 4096,
+	.hostvm_min_page_size_bytes = 4096,
+	.dram_clock_change_latency_us = 23.84,
+	.writeback_dram_clock_change_latency_us = 23.0,
+	.return_bus_width_bytes = 64,
+	.dispclk_dppclk_vco_speed_mhz = 3550,
+	.xfc_bus_transport_time_us = 20,      // ?
+	.xfc_xbuf_latency_tolerance_us = 4,  // ?
+	.use_urgent_burst_bw = 1,            // ?
+	.num_states = 2,
+	.do_urgent_latency_adjustment = false,
+	.urgent_latency_adjustment_fabric_clock_component_us = 0,
+	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
+};
+
+enum dcn301_clk_src_array_id {
+	DCN301_CLK_SRC_PLL0,
+	DCN301_CLK_SRC_PLL1,
+	DCN301_CLK_SRC_PLL2,
+	DCN301_CLK_SRC_PLL3,
+	DCN301_CLK_SRC_TOTAL
+};
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file
+ */
+
+/* DCN */
+/* TODO awful hack. fixup dcn20_dwb.h */
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
+					mm ## reg_name
+
+#define SRI(reg_name, block, id)\
+	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
+					mm ## reg_name
+
+#define SRIR(var_name, reg_name, block, id)\
+	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+#define SRII2(reg_name_pre, reg_name_post, id)\
+	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(mm ## reg_name_pre \
+			## id ## _ ## reg_name_post ## _BASE_IDX) + \
+			mm ## reg_name_pre ## id ## _ ## reg_name_post
+
+#define SRII_MPC_RMU(reg_name, block, id)\
+	.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+#define SRII_DWB(reg_name, temp_name, block, id)\
+	.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## temp_name
+
+#define DCCG_SRII(reg_name, block, id)\
+	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+#define VUPDATE_SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
+					mm ## reg_name ## _ ## block ## id
+
+/* NBIO */
+#define NBIO_BASE_INNER(seg) \
+	NBIO_BASE__INST0_SEG ## seg
+
+#define NBIO_BASE(seg) \
+	NBIO_BASE_INNER(seg)
+
+#define NBIO_SR(reg_name)\
+		.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
+					regBIF_BX0_ ## reg_name
+
+/* MMHUB */
+#define MMHUB_BASE_INNER(seg) \
+	MMHUB_BASE__INST0_SEG ## seg
+
+#define MMHUB_BASE(seg) \
+	MMHUB_BASE_INNER(seg)
+
+#define MMHUB_SR(reg_name)\
+		.reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
+					regMM ## reg_name
+
+/* CLOCK */
+#define CLK_BASE_INNER(seg) \
+	CLK_BASE__INST0_SEG ## seg
+
+#define CLK_BASE(seg) \
+	CLK_BASE_INNER(seg)
+
+#define CLK_SRI(reg_name, block, inst)\
+	.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## _ ## inst ## _ ## reg_name
+
+static const struct bios_registers bios_regs = {
+		NBIO_SR(BIOS_SCRATCH_3),
+		NBIO_SR(BIOS_SCRATCH_6)
+};
+
+#define clk_src_regs(index, pllid)\
+[index] = {\
+	CS_COMMON_REG_LIST_DCN3_01(index, pllid),\
+}
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+	clk_src_regs(0, A),
+	clk_src_regs(1, B),
+	clk_src_regs(2, C),
+	clk_src_regs(3, D)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+};
+
+#define abm_regs(id)\
+[id] = {\
+		ABM_DCN301_REG_LIST(id)\
+}
+
+static const struct dce_abm_registers abm_regs[] = {
+		abm_regs(0),
+		abm_regs(1),
+		abm_regs(2),
+		abm_regs(3),
+};
+
+static const struct dce_abm_shift abm_shift = {
+		ABM_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+		ABM_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define audio_regs(id)\
+[id] = {\
+		AUD_COMMON_REG_LIST(id)\
+}
+
+static const struct dce_audio_registers audio_regs[] = {
+	audio_regs(0),
+	audio_regs(1),
+	audio_regs(2),
+	audio_regs(3),
+	audio_regs(4),
+	audio_regs(5),
+	audio_regs(6)
+};
+
+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
+
+static const struct dce_audio_shift audio_shift = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_audio_mask audio_mask = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+#define vpg_regs(id)\
+[id] = {\
+	VPG_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_vpg_registers vpg_regs[] = {
+	vpg_regs(0),
+	vpg_regs(1),
+	vpg_regs(2),
+	vpg_regs(3),
+};
+
+static const struct dcn30_vpg_shift vpg_shift = {
+	DCN3_VPG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_vpg_mask vpg_mask = {
+	DCN3_VPG_MASK_SH_LIST(_MASK)
+};
+
+#define afmt_regs(id)\
+[id] = {\
+	AFMT_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_afmt_registers afmt_regs[] = {
+	afmt_regs(0),
+	afmt_regs(1),
+	afmt_regs(2),
+	afmt_regs(3),
+};
+
+static const struct dcn30_afmt_shift afmt_shift = {
+	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_afmt_mask afmt_mask = {
+	DCN3_AFMT_MASK_SH_LIST(_MASK)
+};
+
+#define stream_enc_regs(id)\
+[id] = {\
+	SE_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+	stream_enc_regs(0),
+	stream_enc_regs(1),
+	stream_enc_regs(2),
+	stream_enc_regs(3),
+};
+
+static const struct dcn10_stream_encoder_shift se_shift = {
+		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn10_stream_encoder_mask se_mask = {
+		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+
+#define aux_regs(id)\
+[id] = {\
+	DCN2_AUX_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
+		aux_regs(0),
+		aux_regs(1),
+		aux_regs(2),
+		aux_regs(3),
+};
+
+#define hpd_regs(id)\
+[id] = {\
+	HPD_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
+		hpd_regs(0),
+		hpd_regs(1),
+		hpd_regs(2),
+		hpd_regs(3),
+};
+
+#define link_regs(id, phyid)\
+[id] = {\
+	LE_DCN301_REG_LIST(id), \
+	UNIPHY_DCN2_REG_LIST(phyid), \
+}
+
+static const struct dce110_aux_registers_shift aux_shift = {
+	DCN_AUX_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce110_aux_registers_mask aux_mask = {
+	DCN_AUX_MASK_SH_LIST(_MASK)
+};
+
+static const struct dcn10_link_enc_registers link_enc_regs[] = {
+	link_regs(0, A),
+	link_regs(1, B),
+	link_regs(2, C),
+	link_regs(3, D),
+};
+
+static const struct dcn10_link_enc_shift le_shift = {
+	LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT)
+};
+
+static const struct dcn10_link_enc_mask le_mask = {
+	LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK)
+};
+
+#define panel_cntl_regs(id)\
+[id] = {\
+	DCN301_PANEL_CNTL_REG_LIST(id),\
+}
+
+static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
+	panel_cntl_regs(0),
+	panel_cntl_regs(1),
+};
+
+static const struct dcn301_panel_cntl_shift panel_cntl_shift = {
+	DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn301_panel_cntl_mask panel_cntl_mask = {
+	DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK)
+};
+
+#define dpp_regs(id)\
+[id] = {\
+	DPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn3_dpp_registers dpp_regs[] = {
+	dpp_regs(0),
+	dpp_regs(1),
+	dpp_regs(2),
+	dpp_regs(3),
+};
+
+static const struct dcn3_dpp_shift tf_shift = {
+		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
+};
+
+static const struct dcn3_dpp_mask tf_mask = {
+		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
+};
+
+#define opp_regs(id)\
+[id] = {\
+	OPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn20_opp_registers opp_regs[] = {
+	opp_regs(0),
+	opp_regs(1),
+	opp_regs(2),
+	opp_regs(3),
+};
+
+static const struct dcn20_opp_shift opp_shift = {
+	OPP_MASK_SH_LIST_DCN20(__SHIFT)
+};
+
+static const struct dcn20_opp_mask opp_mask = {
+	OPP_MASK_SH_LIST_DCN20(_MASK)
+};
+
+#define aux_engine_regs(id)\
+[id] = {\
+	AUX_COMMON_REG_LIST0(id), \
+	.AUXN_IMPCAL = 0, \
+	.AUXP_IMPCAL = 0, \
+	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+		aux_engine_regs(0),
+		aux_engine_regs(1),
+		aux_engine_regs(2),
+		aux_engine_regs(3),
+};
+
+#define dwbc_regs_dcn3(id)\
+[id] = {\
+	DWBC_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_dwbc_registers dwbc30_regs[] = {
+	dwbc_regs_dcn3(0),
+};
+
+static const struct dcn30_dwbc_shift dwbc30_shift = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_dwbc_mask dwbc30_mask = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define mcif_wb_regs_dcn3(id)\
+[id] = {\
+	MCIF_WB_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
+	mcif_wb_regs_dcn3(0)
+};
+
+static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define dsc_regsDCN20(id)\
+[id] = {\
+	DSC_REG_LIST_DCN20(id)\
+}
+
+static const struct dcn20_dsc_registers dsc_regs[] = {
+	dsc_regsDCN20(0),
+	dsc_regsDCN20(1),
+	dsc_regsDCN20(2),
+};
+
+static const struct dcn20_dsc_shift dsc_shift = {
+	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
+};
+
+static const struct dcn20_dsc_mask dsc_mask = {
+	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+};
+
+static const struct dcn30_mpc_registers mpc_regs = {
+		MPC_REG_LIST_DCN3_0(0),
+		MPC_REG_LIST_DCN3_0(1),
+		MPC_REG_LIST_DCN3_0(2),
+		MPC_REG_LIST_DCN3_0(3),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
+		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
+		MPC_RMU_REG_LIST_DCN3AG(0),
+		MPC_RMU_REG_LIST_DCN3AG(1),
+		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
+};
+
+static const struct dcn30_mpc_shift mpc_shift = {
+	MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_mpc_mask mpc_mask = {
+	MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define optc_regs(id)\
+[id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
+
+
+static const struct dcn_optc_registers optc_regs[] = {
+	optc_regs(0),
+	optc_regs(1),
+	optc_regs(2),
+	optc_regs(3),
+};
+
+static const struct dcn_optc_shift optc_shift = {
+	OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn_optc_mask optc_mask = {
+	OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define hubp_regs(id)\
+[id] = {\
+	HUBP_REG_LIST_DCN30(id)\
+}
+
+static const struct dcn_hubp2_registers hubp_regs[] = {
+		hubp_regs(0),
+		hubp_regs(1),
+		hubp_regs(2),
+		hubp_regs(3),
+};
+
+static const struct dcn_hubp2_shift hubp_shift = {
+		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn_hubp2_mask hubp_mask = {
+		HUBP_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static const struct dcn_hubbub_registers hubbub_reg = {
+		HUBBUB_REG_LIST_DCN301(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+		HUBBUB_MASK_SH_LIST_DCN301(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+		HUBBUB_MASK_SH_LIST_DCN301(_MASK)
+};
+
+static const struct dccg_registers dccg_regs = {
+		DCCG_REG_LIST_DCN301()
+};
+
+static const struct dccg_shift dccg_shift = {
+		DCCG_MASK_SH_LIST_DCN301(__SHIFT)
+};
+
+static const struct dccg_mask dccg_mask = {
+		DCCG_MASK_SH_LIST_DCN301(_MASK)
+};
+
+static const struct dce_hwseq_registers hwseq_reg = {
+		HWSEQ_DCN301_REG_LIST()
+};
+
+static const struct dce_hwseq_shift hwseq_shift = {
+		HWSEQ_DCN301_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+		HWSEQ_DCN301_MASK_SH_LIST(_MASK)
+};
+#define vmid_regs(id)\
+[id] = {\
+		DCN20_VMID_REG_LIST(id)\
+}
+
+static const struct dcn_vmid_registers vmid_regs[] = {
+	vmid_regs(0),
+	vmid_regs(1),
+	vmid_regs(2),
+	vmid_regs(3),
+	vmid_regs(4),
+	vmid_regs(5),
+	vmid_regs(6),
+	vmid_regs(7),
+	vmid_regs(8),
+	vmid_regs(9),
+	vmid_regs(10),
+	vmid_regs(11),
+	vmid_regs(12),
+	vmid_regs(13),
+	vmid_regs(14),
+	vmid_regs(15)
+};
+
+static const struct dcn20_vmid_shift vmid_shifts = {
+		DCN20_VMID_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn20_vmid_mask vmid_masks = {
+		DCN20_VMID_MASK_SH_LIST(_MASK)
+};
+
+static const struct resource_caps res_cap_dcn301 = {
+	.num_timing_generator = 4,
+	.num_opp = 4,
+	.num_video_plane = 4,
+	.num_audio = 4,
+	.num_stream_encoder = 4,
+	.num_pll = 4,
+	.num_dwb = 1,
+	.num_ddc = 4,
+	.num_vmid = 16,
+	.num_mpc_3dlut = 2,
+	.num_dsc = 3,
+};
+
+static const struct dc_plane_cap plane_cap = {
+	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
+	.blends_with_above = true,
+	.blends_with_below = true,
+	.per_pixel_alpha = true,
+
+	.pixel_format_support = {
+			.argb8888 = true,
+			.nv12 = true,
+			.fp16 = true,
+			.p010 = false,
+			.ayuv = false,
+	},
+
+	.max_upscale_factor = {
+			.argb8888 = 16000,
+			.nv12 = 16000,
+			.fp16 = 16000
+	},
+
+	.max_downscale_factor = {
+			.argb8888 = 600,
+			.nv12 = 600,
+			.fp16 = 600
+	},
+	64,
+	64
+};
+
+static const struct dc_debug_options debug_defaults_drv = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = false,
+	.clock_trace = true,
+	.disable_dpp_power_gate = true,
+	.disable_hubp_power_gate = true,
+	.disable_clock_gate = true,
+	.disable_pplib_clock_request = true,
+	.disable_pplib_wm_range = true,
+	.disable_stutter = true,
+	.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+	.force_single_disp_pipe_split = false,
+	.disable_dcc = DCC_ENABLE,
+	.vsr_support = true,
+	.performance_trace = false,
+	.max_downscale_src_width = 7680,/*upto 8K*/
+	.scl_reset_length10 = true,
+	.sanity_checks = false,
+	.underflow_assert_delay_us = 0xFFFFFFFF,
+	.dwb_fi_phase = -1, // -1 = disable
+	.dmub_command_table = true,
+};
+
+static const struct dc_debug_options debug_defaults_diags = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = true,
+	.clock_trace = true,
+	.disable_dpp_power_gate = true,
+	.disable_hubp_power_gate = true,
+	.disable_clock_gate = true,
+	.disable_pplib_clock_request = true,
+	.disable_pplib_wm_range = true,
+	.disable_stutter = true,
+	.scl_reset_length10 = true,
+	.dwb_fi_phase = -1, // -1 = disable
+	.dmub_command_table = true,
+};
+
+void dcn301_dpp_destroy(struct dpp **dpp)
+{
+	kfree(TO_DCN20_DPP(*dpp));
+	*dpp = NULL;
+}
+
+struct dpp *dcn301_dpp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn3_dpp *dpp =
+		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
+
+	if (!dpp)
+		return NULL;
+
+	if (dpp3_construct(dpp, ctx, inst,
+			&dpp_regs[inst], &tf_shift, &tf_mask))
+		return &dpp->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(dpp);
+	return NULL;
+}
+struct output_pixel_processor *dcn301_opp_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_opp *opp =
+		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+
+	if (!opp) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dcn20_opp_construct(opp, ctx, inst,
+			&opp_regs[inst], &opp_shift, &opp_mask);
+	return &opp->base;
+}
+
+struct dce_aux *dcn301_aux_engine_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct aux_engine_dce110 *aux_engine =
+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+	if (!aux_engine)
+		return NULL;
+
+	dce110_aux_engine_construct(aux_engine, ctx, inst,
+				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+				    &aux_engine_regs[inst],
+					&aux_mask,
+					&aux_shift,
+					ctx->dc->caps.extended_aux_timeout_support);
+
+	return &aux_engine->base;
+}
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
+
+static const struct dce_i2c_registers i2c_hw_regs[] = {
+		i2c_inst_regs(1),
+		i2c_inst_regs(2),
+		i2c_inst_regs(3),
+		i2c_inst_regs(4),
+};
+
+static const struct dce_i2c_shift i2c_shifts = {
+		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
+};
+
+static const struct dce_i2c_mask i2c_masks = {
+		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
+};
+
+struct dce_i2c_hw *dcn301_i2c_hw_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dce_i2c_hw *dce_i2c_hw =
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+
+	if (!dce_i2c_hw)
+		return NULL;
+
+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
+
+	return dce_i2c_hw;
+}
+static struct mpc *dcn301_mpc_create(
+		struct dc_context *ctx,
+		int num_mpcc,
+		int num_rmu)
+{
+	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
+					  GFP_KERNEL);
+
+	if (!mpc30)
+		return NULL;
+
+	dcn30_mpc_construct(mpc30, ctx,
+			&mpc_regs,
+			&mpc_shift,
+			&mpc_mask,
+			num_mpcc,
+			num_rmu);
+
+	return &mpc30->base;
+}
+
+struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
+{
+	int i;
+
+	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
+					  GFP_KERNEL);
+
+	if (!hubbub3)
+		return NULL;
+
+	hubbub301_construct(hubbub3, ctx,
+			&hubbub_reg,
+			&hubbub_shift,
+			&hubbub_mask);
+
+
+	for (i = 0; i < res_cap_dcn301.num_vmid; i++) {
+		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
+
+		vmid->ctx = ctx;
+
+		vmid->regs = &vmid_regs[i];
+		vmid->shifts = &vmid_shifts;
+		vmid->masks = &vmid_masks;
+	}
+
+	 hubbub3->num_vmid = res_cap_dcn301.num_vmid;
+
+	return &hubbub3->base;
+}
+
+struct timing_generator *dcn301_timing_generator_create(
+		struct dc_context *ctx,
+		uint32_t instance)
+{
+	struct optc *tgn10 =
+		kzalloc(sizeof(struct optc), GFP_KERNEL);
+
+	if (!tgn10)
+		return NULL;
+
+	tgn10->base.inst = instance;
+	tgn10->base.ctx = ctx;
+
+	tgn10->tg_regs = &optc_regs[instance];
+	tgn10->tg_shift = &optc_shift;
+	tgn10->tg_mask = &optc_mask;
+
+	dcn30_timing_generator_init(tgn10);
+
+	return &tgn10->base;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 600000,
+		.hdmi_ycbcr420_supported = true,
+		.dp_ycbcr420_supported = true,
+		.fec_supported = true,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_HBR3_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_TPS4_CAPABLE = true
+};
+
+struct link_encoder *dcn301_link_encoder_create(
+	const struct encoder_init_data *enc_init_data)
+{
+	struct dcn20_link_encoder *enc20 =
+		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+
+	if (!enc20)
+		return NULL;
+
+	dcn301_link_encoder_construct(enc20,
+			enc_init_data,
+			&link_enc_feature,
+			&link_enc_regs[enc_init_data->transmitter],
+			&link_enc_aux_regs[enc_init_data->channel - 1],
+			&link_enc_hpd_regs[enc_init_data->hpd_source],
+			&le_shift,
+			&le_mask);
+
+	return &enc20->enc10.base;
+}
+
+struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
+{
+	struct dcn301_panel_cntl *panel_cntl =
+		kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL);
+
+	if (!panel_cntl)
+		return NULL;
+
+	dcn301_panel_cntl_construct(panel_cntl,
+			init_data,
+			&panel_cntl_regs[init_data->inst],
+			&panel_cntl_shift,
+			&panel_cntl_mask);
+
+	return &panel_cntl->base;
+}
+
+
+#define CTX ctx
+
+#define REG(reg_name) \
+	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
+
+static uint32_t read_pipe_fuses(struct dc_context *ctx)
+{
+	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
+	/* RV1 support max 4 pipes */
+	value = value & 0xf;
+	return value;
+}
+
+
+static void read_dce_straps(
+	struct dc_context *ctx,
+	struct resource_straps *straps)
+{
+	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
+		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
+
+}
+
+static struct audio *dcn301_create_audio(
+		struct dc_context *ctx, unsigned int inst)
+{
+	return dce_audio_create(ctx, inst,
+			&audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+static struct vpg *dcn301_vpg_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
+
+	if (!vpg3)
+		return NULL;
+
+	vpg3_construct(vpg3, ctx, inst,
+			&vpg_regs[inst],
+			&vpg_shift,
+			&vpg_mask);
+
+	return &vpg3->base;
+}
+
+static struct afmt *dcn301_afmt_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
+
+	if (!afmt3)
+		return NULL;
+
+	afmt3_construct(afmt3, ctx, inst,
+			&afmt_regs[inst],
+			&afmt_shift,
+			&afmt_mask);
+
+	return &afmt3->base;
+}
+
+struct stream_encoder *dcn301_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dcn10_stream_encoder *enc1;
+	struct vpg *vpg;
+	struct afmt *afmt;
+	int vpg_inst;
+	int afmt_inst;
+
+	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
+	if (eng_id <= ENGINE_ID_DIGF) {
+		vpg_inst = eng_id;
+		afmt_inst = eng_id;
+	} else
+		return NULL;
+
+	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
+	vpg = dcn301_vpg_create(ctx, vpg_inst);
+	afmt = dcn301_afmt_create(ctx, afmt_inst);
+
+	if (!enc1 || !vpg || !afmt)
+		return NULL;
+
+	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
+					eng_id, vpg, afmt,
+					&stream_enc_regs[eng_id],
+					&se_shift, &se_mask);
+
+	return &enc1->base;
+}
+
+struct dce_hwseq *dcn301_hwseq_create(
+	struct dc_context *ctx)
+{
+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+	if (hws) {
+		hws->ctx = ctx;
+		hws->regs = &hwseq_reg;
+		hws->shifts = &hwseq_shift;
+		hws->masks = &hwseq_mask;
+	}
+	return hws;
+}
+static const struct resource_create_funcs res_create_funcs = {
+	.read_dce_straps = read_dce_straps,
+	.create_audio = dcn301_create_audio,
+	.create_stream_encoder = dcn301_stream_encoder_create,
+	.create_hwseq = dcn301_hwseq_create,
+};
+
+static const struct resource_create_funcs res_create_maximus_funcs = {
+	.read_dce_straps = NULL,
+	.create_audio = NULL,
+	.create_stream_encoder = NULL,
+	.create_hwseq = dcn301_hwseq_create,
+};
+
+static void dcn301_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
+
+static void dcn301_destruct(struct dcn301_resource_pool *pool)
+{
+	unsigned int i;
+
+	for (i = 0; i < pool->base.stream_enc_count; i++) {
+		if (pool->base.stream_enc[i] != NULL) {
+			if (pool->base.stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
+				pool->base.stream_enc[i]->vpg = NULL;
+			}
+			if (pool->base.stream_enc[i]->afmt != NULL) {
+				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
+				pool->base.stream_enc[i]->afmt = NULL;
+			}
+			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
+			pool->base.stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		if (pool->base.dscs[i] != NULL)
+			dcn20_dsc_destroy(&pool->base.dscs[i]);
+	}
+
+	if (pool->base.mpc != NULL) {
+		kfree(TO_DCN20_MPC(pool->base.mpc));
+		pool->base.mpc = NULL;
+	}
+	if (pool->base.hubbub != NULL) {
+		kfree(pool->base.hubbub);
+		pool->base.hubbub = NULL;
+	}
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		if (pool->base.dpps[i] != NULL)
+			dcn301_dpp_destroy(&pool->base.dpps[i]);
+
+		if (pool->base.ipps[i] != NULL)
+			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
+
+		if (pool->base.hubps[i] != NULL) {
+			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
+			pool->base.hubps[i] = NULL;
+		}
+
+		if (pool->base.irqs != NULL) {
+			dal_irq_service_destroy(&pool->base.irqs);
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		if (pool->base.engines[i] != NULL)
+			dce110_engine_destroy(&pool->base.engines[i]);
+		if (pool->base.hw_i2cs[i] != NULL) {
+			kfree(pool->base.hw_i2cs[i]);
+			pool->base.hw_i2cs[i] = NULL;
+		}
+		if (pool->base.sw_i2cs[i] != NULL) {
+			kfree(pool->base.sw_i2cs[i]);
+			pool->base.sw_i2cs[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+		if (pool->base.opps[i] != NULL)
+			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.timing_generators[i] != NULL)	{
+			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
+			pool->base.timing_generators[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+		if (pool->base.dwbc[i] != NULL) {
+			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
+			pool->base.dwbc[i] = NULL;
+		}
+		if (pool->base.mcif_wb[i] != NULL) {
+			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
+			pool->base.mcif_wb[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.audio_count; i++) {
+		if (pool->base.audios[i])
+			dce_aud_destroy(&pool->base.audios[i]);
+	}
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] != NULL) {
+			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
+			pool->base.clock_sources[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+		if (pool->base.mpc_lut[i] != NULL) {
+			dc_3dlut_func_release(pool->base.mpc_lut[i]);
+			pool->base.mpc_lut[i] = NULL;
+		}
+		if (pool->base.mpc_shaper[i] != NULL) {
+			dc_transfer_func_release(pool->base.mpc_shaper[i]);
+			pool->base.mpc_shaper[i] = NULL;
+		}
+	}
+
+	if (pool->base.dp_clock_source != NULL) {
+		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
+		pool->base.dp_clock_source = NULL;
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.multiple_abms[i] != NULL)
+			dce_abm_destroy(&pool->base.multiple_abms[i]);
+	}
+
+	if (pool->base.dccg != NULL)
+		dcn_dccg_destroy(&pool->base.dccg);
+
+	if (pool->base.pp_smu != NULL)
+		dcn301_pp_smu_destroy(&pool->base.pp_smu);
+}
+
+struct hubp *dcn301_hubp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn20_hubp *hubp2 =
+		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
+
+	if (!hubp2)
+		return NULL;
+
+	if (hubp3_construct(hubp2, ctx, inst,
+			&hubp_regs[inst], &hubp_shift, &hubp_mask))
+		return &hubp2->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(hubp2);
+	return NULL;
+}
+
+bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t pipe_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < pipe_count; i++) {
+		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
+						    GFP_KERNEL);
+
+		if (!dwbc30) {
+			dm_error("DC: failed to create dwbc30!\n");
+			return false;
+		}
+
+		dcn30_dwbc_construct(dwbc30, ctx,
+				&dwbc30_regs[i],
+				&dwbc30_shift,
+				&dwbc30_mask,
+				i);
+
+		pool->dwbc[i] = &dwbc30->base;
+	}
+	return true;
+}
+
+bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t pipe_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < pipe_count; i++) {
+		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
+						    GFP_KERNEL);
+
+		if (!mcif_wb30) {
+			dm_error("DC: failed to create mcif_wb30!\n");
+			return false;
+		}
+
+		dcn30_mmhubbub_construct(mcif_wb30, ctx,
+				&mcif_wb30_regs[i],
+				&mcif_wb30_shift,
+				&mcif_wb30_mask,
+				i);
+
+		pool->mcif_wb[i] = &mcif_wb30->base;
+	}
+	return true;
+}
+
+static struct display_stream_compressor *dcn301_dsc_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_dsc *dsc =
+		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
+
+	if (!dsc) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+	return &dsc->base;
+}
+
+
+static void dcn301_destroy_resource_pool(struct resource_pool **pool)
+{
+	struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool);
+
+	dcn301_destruct(dcn301_pool);
+	kfree(dcn301_pool);
+	*pool = NULL;
+}
+
+static struct clock_source *dcn301_clock_source_create(
+		struct dc_context *ctx,
+		struct dc_bios *bios,
+		enum clock_source_id id,
+		const struct dce110_clk_src_regs *regs,
+		bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src =
+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dcn301_clk_src_construct(clk_src, ctx, bios, id,
+			regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static struct dc_cap_funcs cap_funcs = {
+	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+};
+
+#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
+#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
+
+static bool is_soc_bounding_box_valid(struct dc *dc)
+{
+	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
+
+	if (ASICREV_IS_VANGOGH(hw_internal_rev))
+		return true;
+
+	return false;
+}
+
+static bool init_soc_bounding_box(struct dc *dc,
+				  struct dcn301_resource_pool *pool)
+{
+	const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
+	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc;
+	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip;
+
+	DC_LOGGER_INIT(dc->ctx->logger);
+
+	if (!bb && !is_soc_bounding_box_valid(dc)) {
+		DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+		return false;
+	}
+
+	if (bb && !is_soc_bounding_box_valid(dc)) {
+		int i;
+
+		dcn3_01_soc.sr_exit_time_us =
+				fixed16_to_double_to_cpu(bb->sr_exit_time_us);
+		dcn3_01_soc.sr_enter_plus_exit_time_us =
+				fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
+		dcn3_01_soc.urgent_latency_us =
+				fixed16_to_double_to_cpu(bb->urgent_latency_us);
+		dcn3_01_soc.urgent_latency_pixel_data_only_us =
+				fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
+		dcn3_01_soc.urgent_latency_pixel_mixed_with_vm_data_us =
+				fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
+		dcn3_01_soc.urgent_latency_vm_data_only_us =
+				fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
+		dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
+				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
+		dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
+				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
+		dcn3_01_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
+				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
+		dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
+				fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
+		dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
+				fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
+		dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
+				fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
+		dcn3_01_soc.max_avg_sdp_bw_use_normal_percent =
+				fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
+		dcn3_01_soc.max_avg_dram_bw_use_normal_percent =
+				fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
+		dcn3_01_soc.writeback_latency_us =
+				fixed16_to_double_to_cpu(bb->writeback_latency_us);
+		dcn3_01_soc.ideal_dram_bw_after_urgent_percent =
+				fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
+		dcn3_01_soc.max_request_size_bytes =
+				le32_to_cpu(bb->max_request_size_bytes);
+		dcn3_01_soc.dram_channel_width_bytes =
+				le32_to_cpu(bb->dram_channel_width_bytes);
+		dcn3_01_soc.fabric_datapath_to_dcn_data_return_bytes =
+				le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
+		dcn3_01_soc.dcn_downspread_percent =
+				fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
+		dcn3_01_soc.downspread_percent =
+				fixed16_to_double_to_cpu(bb->downspread_percent);
+		dcn3_01_soc.dram_page_open_time_ns =
+				fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
+		dcn3_01_soc.dram_rw_turnaround_time_ns =
+				fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
+		dcn3_01_soc.dram_return_buffer_per_channel_bytes =
+				le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
+		dcn3_01_soc.round_trip_ping_latency_dcfclk_cycles =
+				le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
+		dcn3_01_soc.urgent_out_of_order_return_per_channel_bytes =
+				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
+		dcn3_01_soc.channel_interleave_bytes =
+				le32_to_cpu(bb->channel_interleave_bytes);
+		dcn3_01_soc.num_banks =
+				le32_to_cpu(bb->num_banks);
+		dcn3_01_soc.num_chans =
+				le32_to_cpu(bb->num_chans);
+		dcn3_01_soc.gpuvm_min_page_size_bytes =
+				le32_to_cpu(bb->vmm_page_size_bytes);
+		dcn3_01_soc.dram_clock_change_latency_us =
+				fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
+		dcn3_01_soc.writeback_dram_clock_change_latency_us =
+				fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
+		dcn3_01_soc.return_bus_width_bytes =
+				le32_to_cpu(bb->return_bus_width_bytes);
+		dcn3_01_soc.dispclk_dppclk_vco_speed_mhz =
+				le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
+		dcn3_01_soc.xfc_bus_transport_time_us =
+				le32_to_cpu(bb->xfc_bus_transport_time_us);
+		dcn3_01_soc.xfc_xbuf_latency_tolerance_us =
+				le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
+		dcn3_01_soc.use_urgent_burst_bw =
+				le32_to_cpu(bb->use_urgent_burst_bw);
+		dcn3_01_soc.num_states =
+				le32_to_cpu(bb->num_states);
+
+		for (i = 0; i < dcn3_01_soc.num_states; i++) {
+			dcn3_01_soc.clock_limits[i].state =
+					le32_to_cpu(bb->clock_limits[i].state);
+			dcn3_01_soc.clock_limits[i].dcfclk_mhz =
+					fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
+			dcn3_01_soc.clock_limits[i].fabricclk_mhz =
+					fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
+			dcn3_01_soc.clock_limits[i].dispclk_mhz =
+					fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
+			dcn3_01_soc.clock_limits[i].dppclk_mhz =
+					fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
+			dcn3_01_soc.clock_limits[i].phyclk_mhz =
+					fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
+			dcn3_01_soc.clock_limits[i].socclk_mhz =
+					fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
+			dcn3_01_soc.clock_limits[i].dscclk_mhz =
+					fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
+			dcn3_01_soc.clock_limits[i].dram_speed_mts =
+					fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
+		}
+	}
+
+	if (pool->base.pp_smu) {
+		struct pp_smu_nv_clock_table max_clocks = {0};
+		unsigned int uclk_states[8] = {0};
+		unsigned int num_states = 0;
+		enum pp_smu_status status;
+		bool clock_limits_available = false;
+		bool uclk_states_available = false;
+
+		if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
+			status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
+				(&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
+
+			uclk_states_available = (status == PP_SMU_RESULT_OK);
+		}
+
+		if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
+			status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
+					(&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
+			/* SMU cannot set DCF clock to anything equal to or higher than SOC clock
+			 */
+			if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
+				max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
+			clock_limits_available = (status == PP_SMU_RESULT_OK);
+		}
+
+		if (clock_limits_available && uclk_states_available && num_states)
+			dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
+		else if (clock_limits_available)
+			dcn20_cap_soc_clocks(loaded_bb, max_clocks);
+	}
+
+	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
+	loaded_ip->max_num_dpp = pool->base.pipe_count;
+	dcn20_patch_bounding_box(dc, loaded_bb);
+
+	return true;
+}
+
+static void set_wm_ranges(
+		struct pp_smu_funcs *pp_smu,
+		struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
+{
+	struct pp_smu_wm_range_sets ranges = {0};
+	int i;
+
+	ranges.num_reader_wm_sets = 0;
+
+	if (loaded_bb->num_states == 1) {
+		ranges.reader_wm_sets[0].wm_inst = 0;
+		ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+		ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+		ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+		ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+
+		ranges.num_reader_wm_sets = 1;
+	} else if (loaded_bb->num_states > 1) {
+		for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
+			ranges.reader_wm_sets[i].wm_inst = i;
+			ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+			ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+			ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
+			ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
+
+			ranges.num_reader_wm_sets = i + 1;
+		}
+
+		ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+		ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+	}
+
+	ranges.num_writer_wm_sets = 1;
+
+	ranges.writer_wm_sets[0].wm_inst = 0;
+	ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+	ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+	ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
+	ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+
+	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
+	pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
+}
+
+static struct pp_smu_funcs *dcn301_pp_smu_create(struct dc_context *ctx)
+{
+	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
+
+	if (!pp_smu)
+		return pp_smu;
+
+	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && !IS_DIAG_DC(ctx->dce_environment)) {
+		dm_pp_get_funcs(ctx, pp_smu);
+
+		/* TODO: update once we have n21 smu*/
+		if (pp_smu->ctx.ver != PP_SMU_VER_NV)
+			pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
+	}
+
+	return pp_smu;
+}
+
+static void dcn301_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
+{
+	if (pp_smu && *pp_smu) {
+		kfree(*pp_smu);
+		*pp_smu = NULL;
+	}
+}
+
+static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+{
+	dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+}
+
+static struct resource_funcs dcn301_res_pool_funcs = {
+	.destroy = dcn301_destroy_resource_pool,
+	.link_enc_create = dcn301_link_encoder_create,
+	.panel_cntl_create = dcn301_panel_cntl_create,
+	.validate_bandwidth = dcn30_validate_bandwidth,
+	.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
+	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
+	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
+	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
+	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
+	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
+	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
+	.update_bw_bounding_box = dcn301_update_bw_bounding_box
+};
+
+static bool dcn301_resource_construct(
+	uint8_t num_virtual_links,
+	struct dc *dc,
+	struct dcn301_resource_pool *pool)
+{
+	int i, j;
+	struct dc_context *ctx = dc->ctx;
+	struct irq_service_init_data init_data;
+	uint32_t pipe_fuses = read_pipe_fuses(ctx);
+	uint32_t num_pipes = 0;
+
+	DC_LOGGER_INIT(dc->ctx->logger);
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->base.res_cap = &res_cap_dcn301;
+
+	pool->base.funcs = &dcn301_res_pool_funcs;
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
+	dc->caps.max_downscale_ratio = 600;
+	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.max_cursor_size = 256;
+	dc->caps.dmdata_alloc_size = 2048;
+	dc->caps.max_slave_planes = 1;
+	dc->caps.is_apu = true;
+	dc->caps.post_blend_color_processing = true;
+	dc->caps.force_dp_tps4_for_cp2520 = true;
+	dc->caps.extended_aux_timeout_support = true;
+#ifdef CONFIG_DRM_AMD_DC_DMUB
+	dc->caps.dmcub_support = true;
+#endif
+
+	/* Color pipeline capabilities */
+	dc->caps.color.dpp.dcn_arch = 1;
+	dc->caps.color.dpp.input_lut_shared = 0;
+	dc->caps.color.dpp.icsc = 1;
+	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
+	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
+	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
+	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
+	dc->caps.color.dpp.post_csc = 1;
+	dc->caps.color.dpp.gamma_corr = 1;
+
+	dc->caps.color.dpp.hw_3d_lut = 1;
+	dc->caps.color.dpp.ogam_ram = 1;
+	// no OGAM ROM on DCN301
+	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
+	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
+	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
+	dc->caps.color.dpp.ocsc = 0;
+
+	dc->caps.color.mpc.gamut_remap = 1;
+	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+	dc->caps.color.mpc.ogam_ram = 1;
+	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
+	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
+	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
+	dc->caps.color.mpc.ocsc = 1;
+
+	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+		dc->debug = debug_defaults_drv;
+	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
+		dc->debug = debug_defaults_diags;
+	} else
+		dc->debug = debug_defaults_diags;
+	// Init the vm_helper
+	if (dc->vm_helper)
+		vm_helper_init(dc->vm_helper, 16);
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	/* Clock Sources for Pixel Clock*/
+	pool->base.clock_sources[DCN301_CLK_SRC_PLL0] =
+			dcn301_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL0,
+				&clk_src_regs[0], false);
+	pool->base.clock_sources[DCN301_CLK_SRC_PLL1] =
+			dcn301_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL1,
+				&clk_src_regs[1], false);
+	pool->base.clock_sources[DCN301_CLK_SRC_PLL2] =
+			dcn301_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL2,
+				&clk_src_regs[2], false);
+	pool->base.clock_sources[DCN301_CLK_SRC_PLL3] =
+			dcn301_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL3,
+				&clk_src_regs[3], false);
+
+	pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL;
+
+	/* todo: not reuse phy_pll registers */
+	pool->base.dp_clock_source =
+			dcn301_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_ID_DP_DTO,
+				&clk_src_regs[0], true);
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* DCCG */
+	pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
+	if (pool->base.dccg == NULL) {
+		dm_error("DC: failed to create dccg!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* PP Lib and SMU interfaces */
+	pool->base.pp_smu = dcn301_pp_smu_create(ctx);
+	init_soc_bounding_box(dc, pool);
+	if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)
+		set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);
+
+	num_pipes = dcn3_01_ip.max_num_dpp;
+
+	for (i = 0; i < dcn3_01_ip.max_num_dpp; i++)
+		if (pipe_fuses & 1 << i)
+			num_pipes--;
+	dcn3_01_ip.max_num_dpp = num_pipes;
+	dcn3_01_ip.max_num_otg = num_pipes;
+
+
+	dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
+
+	/* IRQ */
+	init_data.ctx = dc->ctx;
+	pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
+	if (!pool->base.irqs)
+		goto create_fail;
+
+	/* HUBBUB */
+	pool->base.hubbub = dcn301_hubbub_create(ctx);
+	if (pool->base.hubbub == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create hubbub!\n");
+		goto create_fail;
+	}
+
+	j = 0;
+	/* HUBPs, DPPs, OPPs and TGs */
+	for (i = 0; i < pool->base.pipe_count; i++) {
+
+		/* if pipe is disabled, skip instance of HW pipe,
+		 * i.e, skip ASIC register instance
+		 */
+		if ((pipe_fuses & (1 << i)) != 0) {
+			DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i);
+			continue;
+		}
+
+		pool->base.hubps[j] = dcn301_hubp_create(ctx, i);
+		if (pool->base.hubps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create hubps!\n");
+			goto create_fail;
+		}
+
+		pool->base.dpps[j] = dcn301_dpp_create(ctx, i);
+		if (pool->base.dpps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create dpps!\n");
+			goto create_fail;
+		}
+
+		pool->base.opps[j] = dcn301_opp_create(ctx, i);
+		if (pool->base.opps[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create output pixel processor!\n");
+			goto create_fail;
+		}
+
+		pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i);
+		if (pool->base.timing_generators[j] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto create_fail;
+		}
+		j++;
+	}
+	pool->base.timing_generator_count = j;
+	pool->base.pipe_count = j;
+	pool->base.mpcc_count = j;
+
+	/* ABM (or ABMs for NV2x) */
+	/* TODO: */
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
+				&abm_regs[i],
+				&abm_shift,
+				&abm_mask);
+		if (pool->base.multiple_abms[i] == NULL) {
+			dm_error("DC: failed to create abm for pipe %d!\n", i);
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* MPC and DSC */
+	pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
+	if (pool->base.mpc == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mpc!\n");
+		goto create_fail;
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
+		if (pool->base.dscs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create display stream compressor %d!\n", i);
+			goto create_fail;
+		}
+	}
+
+	/* DWB and MMHUBBUB */
+	if (!dcn301_dwbc_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create dwbc!\n");
+		goto create_fail;
+	}
+
+	if (!dcn301_mmhubbub_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mcif_wb!\n");
+		goto create_fail;
+	}
+
+	/* AUX and I2C */
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
+		if (pool->base.engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create aux engine!!\n");
+			goto create_fail;
+		}
+		pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i);
+		if (pool->base.hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create hw i2c!!\n");
+			goto create_fail;
+		}
+		pool->base.sw_i2cs[i] = NULL;
+	}
+
+	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
+	if (!resource_construct(num_virtual_links, dc, &pool->base,
+			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
+			&res_create_funcs : &res_create_maximus_funcs)))
+			goto create_fail;
+
+	/* HW Sequencer and Plane caps */
+	dcn301_hw_sequencer_construct(dc);
+
+	dc->caps.max_planes =  pool->base.pipe_count;
+
+	for (i = 0; i < dc->caps.max_planes; ++i)
+		dc->caps.planes[i] = plane_cap;
+
+	dc->cap_funcs = cap_funcs;
+
+	return true;
+
+create_fail:
+
+	dcn301_destruct(pool);
+
+	return false;
+}
+
+struct resource_pool *dcn301_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc)
+{
+	struct dcn301_resource_pool *pool =
+		kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
+		return &pool->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(pool);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.h b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.h
new file mode 100644
index 000000000000..17e4e91ff4b8
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN301_RESOURCE_H_
+#define _DCN301_RESOURCE_H_
+
+#include "core_types.h"
+
+struct dc;
+struct resource_pool;
+struct _vcs_dpi_display_pipe_params_st;
+
+struct dcn301_resource_pool {
+	struct resource_pool base;
+};
+struct resource_pool *dcn301_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* _DCN301_RESOURCE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/Makefile b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
new file mode 100644
index 000000000000..36e44e1b07fa
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/Makefile
@@ -0,0 +1,46 @@
+#
+# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved
+#
+#  All rights reserved.  This notice is intended as a precaution against
+#  inadvertent publication and does not imply publication or any waiver
+#  of confidentiality.  The year included in the foregoing notice is the
+#  year of creation of the work.
+#
+#  Authors: AMD
+#
+# Makefile for dcn302.
+
+DCN3_02 = dcn302_init.o dcn302_hwseq.o dcn302_resource.o
+
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_ARM64
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mgeneral-regs-only
+endif
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+endif
+
+ifdef CONFIG_X86
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o += -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o += -msse2
+endif
+endif
+
+AMD_DAL_DCN3_02 = $(addprefix $(AMDDALPATH)/dc/dcn302/,$(DCN3_02))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCN3_02)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_dccg.h
new file mode 100644
index 000000000000..c884dde1bb25
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_dccg.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN302_DCCG_H__
+#define __DCN302_DCCG_H__
+
+#include "dcn30/dcn30_dccg.h"
+
+
+#define DCCG_REG_LIST_DCN3_02() \
+	DCCG_COMMON_REG_LIST_DCN_BASE(),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 4)
+
+#define DCCG_MASK_SH_LIST_DCN3_02(mask_sh) \
+	DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh)
+
+#endif //__DCN302_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
new file mode 100644
index 000000000000..e8580cccbebf
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn302_hwseq.h"
+
+#include "dce/dce_hwseq.h"
+
+#include "reg_helper.h"
+#include "dc.h"
+
+#define DC_LOGGER_INIT(logger)
+
+#define CTX \
+	hws->ctx
+#define REG(reg)\
+	hws->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hws->shifts->field_name, hws->masks->field_name
+
+
+void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on)
+{
+	uint32_t power_gate = power_on ? 0 : 1;
+	uint32_t pwr_status = power_on ? 0 : 2;
+
+	if (hws->ctx->dc->debug.disable_dpp_power_gate)
+		return;
+	if (REG(DOMAIN1_PG_CONFIG) == 0)
+		return;
+
+	switch (dpp_inst) {
+	case 0: /* DPP0 */
+		REG_UPDATE(DOMAIN1_PG_CONFIG,
+				DOMAIN1_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN1_PG_STATUS,
+				DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 1: /* DPP1 */
+		REG_UPDATE(DOMAIN3_PG_CONFIG,
+				DOMAIN3_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN3_PG_STATUS,
+				DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 2: /* DPP2 */
+		REG_UPDATE(DOMAIN5_PG_CONFIG,
+				DOMAIN5_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN5_PG_STATUS,
+				DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 3: /* DPP3 */
+		REG_UPDATE(DOMAIN7_PG_CONFIG,
+				DOMAIN7_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN7_PG_STATUS,
+				DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 4: /* DPP4 */
+		/*
+		 * Do not power gate DPP4, should be left at HW default, power on permanently.
+		 * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard
+		 * reset.
+		 * REG_UPDATE(DOMAIN9_PG_CONFIG,
+		 *		DOMAIN9_POWER_GATE, power_gate);
+		 *
+		 * REG_WAIT(DOMAIN9_PG_STATUS,
+		 *		DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
+		 *		1, 1000);
+		 */
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		break;
+	}
+}
+
+void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
+{
+	uint32_t power_gate = power_on ? 0 : 1;
+	uint32_t pwr_status = power_on ? 0 : 2;
+
+	if (hws->ctx->dc->debug.disable_hubp_power_gate)
+		return;
+	if (REG(DOMAIN0_PG_CONFIG) == 0)
+		return;
+
+	switch (hubp_inst) {
+	case 0: /* DCHUBP0 */
+		REG_UPDATE(DOMAIN0_PG_CONFIG,
+				DOMAIN0_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN0_PG_STATUS,
+				DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 1: /* DCHUBP1 */
+		REG_UPDATE(DOMAIN2_PG_CONFIG,
+				DOMAIN2_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN2_PG_STATUS,
+				DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 2: /* DCHUBP2 */
+		REG_UPDATE(DOMAIN4_PG_CONFIG,
+				DOMAIN4_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN4_PG_STATUS,
+				DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 3: /* DCHUBP3 */
+		REG_UPDATE(DOMAIN6_PG_CONFIG,
+				DOMAIN6_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN6_PG_STATUS,
+				DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 4: /* DCHUBP4 */
+		/*
+		 * Do not power gate DCHUB4, should be left at HW default, power on permanently.
+		 * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard
+		 * reset.
+		 * REG_UPDATE(DOMAIN8_PG_CONFIG,
+		 *		DOMAIN8_POWER_GATE, power_gate);
+		 *
+		 * REG_WAIT(DOMAIN8_PG_STATUS,
+		 *		DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
+		 *		1, 1000);
+		 */
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		break;
+	}
+}
+
+void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on)
+{
+	uint32_t power_gate = power_on ? 0 : 1;
+	uint32_t pwr_status = power_on ? 0 : 2;
+	uint32_t org_ip_request_cntl = 0;
+
+	if (hws->ctx->dc->debug.disable_dsc_power_gate)
+		return;
+
+	if (REG(DOMAIN16_PG_CONFIG) == 0)
+		return;
+
+	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
+
+	switch (dsc_inst) {
+	case 0: /* DSC0 */
+		REG_UPDATE(DOMAIN16_PG_CONFIG,
+				DOMAIN16_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN16_PG_STATUS,
+				DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 1: /* DSC1 */
+		REG_UPDATE(DOMAIN17_PG_CONFIG,
+				DOMAIN17_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN17_PG_STATUS,
+				DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 2: /* DSC2 */
+		REG_UPDATE(DOMAIN18_PG_CONFIG,
+				DOMAIN18_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN18_PG_STATUS,
+				DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 3: /* DSC3 */
+		REG_UPDATE(DOMAIN19_PG_CONFIG,
+				DOMAIN19_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN19_PG_STATUS,
+				DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 4: /* DSC4 */
+		REG_UPDATE(DOMAIN20_PG_CONFIG,
+				DOMAIN20_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN20_PG_STATUS,
+				DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		break;
+	}
+
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.h
new file mode 100644
index 000000000000..1e5126a0e695
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCN302_H__
+#define __DC_HWSS_DCN302_H__
+
+#include "hw_sequencer_private.h"
+
+void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
+void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
+void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
+
+#endif /* __DC_HWSS_DCN302_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.c
new file mode 100644
index 000000000000..d88b9011c502
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn302_hwseq.h"
+
+#include "dcn30/dcn30_init.h"
+
+#include "dc.h"
+
+void dcn302_hw_sequencer_construct(struct dc *dc)
+{
+	dcn30_hw_sequencer_construct(dc);
+
+	dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control;
+	dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control;
+	dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.h b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.h
new file mode 100644
index 000000000000..899587b93aa1
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_init.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DCN302_INIT_H__
+#define __DC_DCN302_INIT_H__
+
+struct dc;
+
+void dcn302_hw_sequencer_construct(struct dc *dc);
+
+#endif /* __DC_DCN302_INIT_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
new file mode 100644
index 000000000000..2345f12ceab3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -0,0 +1,1563 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn302_init.h"
+#include "dcn302_resource.h"
+#include "dcn302_dccg.h"
+#include "irq/dcn302/irq_service_dcn302.h"
+
+#include "dcn30/dcn30_dio_link_encoder.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn30/dcn30_dwb.h"
+#include "dcn30/dcn30_dpp.h"
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn30/dcn30_hubp.h"
+#include "dcn30/dcn30_mmhubbub.h"
+#include "dcn30/dcn30_mpc.h"
+#include "dcn30/dcn30_opp.h"
+#include "dcn30/dcn30_optc.h"
+#include "dcn30/dcn30_resource.h"
+
+#include "dcn20/dcn20_dsc.h"
+#include "dcn20/dcn20_resource.h"
+
+#include "dcn10/dcn10_resource.h"
+
+#include "dce/dce_abm.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_hwseq.h"
+#include "dce/dce_i2c_hw.h"
+#include "dce/dce_panel_cntl.h"
+#include "dce/dmub_abm.h"
+
+#include "hw_sequencer_private.h"
+#include "reg_helper.h"
+#include "resource.h"
+#include "vm_helper.h"
+
+#include "dimgrey_cavefish_ip_offset.h"
+#include "dcn/dcn_3_0_0_offset.h"
+#include "dcn/dcn_3_0_0_sh_mask.h"
+#include "dcn/dpcs_3_0_0_offset.h"
+#include "dcn/dpcs_3_0_0_sh_mask.h"
+#include "nbio/nbio_7_4_offset.h"
+#include "amdgpu_socbb.h"
+
+#define DC_LOGGER_INIT(logger)
+
+struct _vcs_dpi_ip_params_st dcn3_02_ip = {
+		.use_min_dcfclk = 0,
+		.clamp_min_dcfclk = 0,
+		.odm_capable = 1,
+		.gpuvm_enable = 1,
+		.hostvm_enable = 0,
+		.gpuvm_max_page_table_levels = 4,
+		.hostvm_max_page_table_levels = 4,
+		.hostvm_cached_page_table_levels = 0,
+		.pte_group_size_bytes = 2048,
+		.num_dsc = 5,
+		.rob_buffer_size_kbytes = 184,
+		.det_buffer_size_kbytes = 184,
+		.dpte_buffer_size_in_pte_reqs_luma = 64,
+		.dpte_buffer_size_in_pte_reqs_chroma = 34,
+		.pde_proc_buffer_size_64k_reqs = 48,
+		.dpp_output_buffer_pixels = 2560,
+		.opp_output_buffer_lines = 1,
+		.pixel_chunk_size_kbytes = 8,
+		.pte_enable = 1,
+		.max_page_table_levels = 2,
+		.pte_chunk_size_kbytes = 2,  // ?
+		.meta_chunk_size_kbytes = 2,
+		.writeback_chunk_size_kbytes = 8,
+		.line_buffer_size_bits = 789504,
+		.is_line_buffer_bpp_fixed = 0,  // ?
+		.line_buffer_fixed_bpp = 0,     // ?
+		.dcc_supported = true,
+		.writeback_interface_buffer_size_kbytes = 90,
+		.writeback_line_buffer_buffer_size = 0,
+		.max_line_buffer_lines = 12,
+		.writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
+		.writeback_chroma_buffer_size_kbytes = 8,
+		.writeback_chroma_line_buffer_width_pixels = 4,
+		.writeback_max_hscl_ratio = 1,
+		.writeback_max_vscl_ratio = 1,
+		.writeback_min_hscl_ratio = 1,
+		.writeback_min_vscl_ratio = 1,
+		.writeback_max_hscl_taps = 1,
+		.writeback_max_vscl_taps = 1,
+		.writeback_line_buffer_luma_buffer_size = 0,
+		.writeback_line_buffer_chroma_buffer_size = 14643,
+		.cursor_buffer_size = 8,
+		.cursor_chunk_size = 2,
+		.max_num_otg = 5,
+		.max_num_dpp = 5,
+		.max_num_wb = 1,
+		.max_dchub_pscl_bw_pix_per_clk = 4,
+		.max_pscl_lb_bw_pix_per_clk = 2,
+		.max_lb_vscl_bw_pix_per_clk = 4,
+		.max_vscl_hscl_bw_pix_per_clk = 4,
+		.max_hscl_ratio = 6,
+		.max_vscl_ratio = 6,
+		.hscl_mults = 4,
+		.vscl_mults = 4,
+		.max_hscl_taps = 8,
+		.max_vscl_taps = 8,
+		.dispclk_ramp_margin_percent = 1,
+		.underscan_factor = 1.11,
+		.min_vblank_lines = 32,
+		.dppclk_delay_subtotal = 46,
+		.dynamic_metadata_vm_enabled = true,
+		.dppclk_delay_scl_lb_only = 16,
+		.dppclk_delay_scl = 50,
+		.dppclk_delay_cnvc_formatter = 27,
+		.dppclk_delay_cnvc_cursor = 6,
+		.dispclk_delay_subtotal = 119,
+		.dcfclk_cstate_latency = 5.2, // SRExitTime
+		.max_inter_dcn_tile_repeaters = 8,
+		.max_num_hdmi_frl_outputs = 1,
+		.odm_combine_4to1_supported = true,
+
+		.xfc_supported = false,
+		.xfc_fill_bw_overhead_percent = 10.0,
+		.xfc_fill_constant_bytes = 0,
+		.gfx7_compat_tiling_supported = 0,
+		.number_of_cursors = 1,
+};
+
+struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = {
+		.clock_limits = {
+				{
+						.state = 0,
+						.dispclk_mhz = 562.0,
+						.dppclk_mhz = 300.0,
+						.phyclk_mhz = 300.0,
+						.phyclk_d18_mhz = 667.0,
+						.dscclk_mhz = 405.6,
+				},
+		},
+
+		.min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
+		.num_states = 1,
+		.sr_exit_time_us = 5.20,
+		.sr_enter_plus_exit_time_us = 9.60,
+		.urgent_latency_us = 4.0,
+		.urgent_latency_pixel_data_only_us = 4.0,
+		.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+		.urgent_latency_vm_data_only_us = 4.0,
+		.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
+		.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
+		.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
+		.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
+		.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
+		.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
+		.max_avg_sdp_bw_use_normal_percent = 60.0,
+		.max_avg_dram_bw_use_normal_percent = 40.0,
+		.writeback_latency_us = 12.0,
+		.max_request_size_bytes = 256,
+		.fabric_datapath_to_dcn_data_return_bytes = 64,
+		.dcn_downspread_percent = 0.5,
+		.downspread_percent = 0.38,
+		.dram_page_open_time_ns = 50.0,
+		.dram_rw_turnaround_time_ns = 17.5,
+		.dram_return_buffer_per_channel_bytes = 8192,
+		.round_trip_ping_latency_dcfclk_cycles = 156,
+		.urgent_out_of_order_return_per_channel_bytes = 4096,
+		.channel_interleave_bytes = 256,
+		.num_banks = 8,
+		.gpuvm_min_page_size_bytes = 4096,
+		.hostvm_min_page_size_bytes = 4096,
+		.dram_clock_change_latency_us = 350,
+		.dummy_pstate_latency_us = 5,
+		.writeback_dram_clock_change_latency_us = 23.0,
+		.return_bus_width_bytes = 64,
+		.dispclk_dppclk_vco_speed_mhz = 3650,
+		.xfc_bus_transport_time_us = 20,      // ?
+		.xfc_xbuf_latency_tolerance_us = 4,  // ?
+		.use_urgent_burst_bw = 1,            // ?
+		.do_urgent_latency_adjustment = true,
+		.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
+		.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
+};
+
+static const struct dc_debug_options debug_defaults_drv = {
+		.disable_dmcu = true,
+		.force_abm_enable = false,
+		.timing_trace = false,
+		.clock_trace = true,
+		.disable_pplib_clock_request = true,
+		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+		.force_single_disp_pipe_split = false,
+		.disable_dcc = DCC_ENABLE,
+		.vsr_support = true,
+		.performance_trace = false,
+		.max_downscale_src_width = 7680,/*upto 8K*/
+		.disable_pplib_wm_range = false,
+		.scl_reset_length10 = true,
+		.sanity_checks = false,
+		.underflow_assert_delay_us = 0xFFFFFFFF,
+		.dwb_fi_phase = -1, // -1 = disable,
+		.dmub_command_table = true,
+};
+
+static const struct dc_debug_options debug_defaults_diags = {
+		.disable_dmcu = true,
+		.force_abm_enable = false,
+		.timing_trace = true,
+		.clock_trace = true,
+		.disable_dpp_power_gate = true,
+		.disable_hubp_power_gate = true,
+		.disable_clock_gate = true,
+		.disable_pplib_clock_request = true,
+		.disable_pplib_wm_range = true,
+		.disable_stutter = false,
+		.scl_reset_length10 = true,
+		.dwb_fi_phase = -1, // -1 = disable
+		.dmub_command_table = true,
+		.enable_tri_buf = true,
+};
+
+enum dcn302_clk_src_array_id {
+	DCN302_CLK_SRC_PLL0,
+	DCN302_CLK_SRC_PLL1,
+	DCN302_CLK_SRC_PLL2,
+	DCN302_CLK_SRC_PLL3,
+	DCN302_CLK_SRC_PLL4,
+	DCN302_CLK_SRC_TOTAL
+};
+
+static const struct resource_caps res_cap_dcn302 = {
+		.num_timing_generator = 5,
+		.num_opp = 5,
+		.num_video_plane = 5,
+		.num_audio = 5,
+		.num_stream_encoder = 5,
+		.num_dwb = 1,
+		.num_ddc = 5,
+		.num_vmid = 16,
+		.num_mpc_3dlut = 2,
+		.num_dsc = 5,
+};
+
+static const struct dc_plane_cap plane_cap = {
+		.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
+		.blends_with_above = true,
+		.blends_with_below = true,
+		.per_pixel_alpha = true,
+		.pixel_format_support = {
+				.argb8888 = true,
+				.nv12 = true,
+				.fp16 = true,
+				.p010 = false,
+				.ayuv = false,
+		},
+		.max_upscale_factor = {
+				.argb8888 = 16000,
+				.nv12 = 16000,
+				.fp16 = 16000
+		},
+		.max_downscale_factor = {
+				.argb8888 = 600,
+				.nv12 = 600,
+				.fp16 = 600
+		},
+		16,
+		16
+};
+
+/* NBIO */
+#define NBIO_BASE_INNER(seg) \
+		NBIO_BASE__INST0_SEG ## seg
+
+#define NBIO_BASE(seg) \
+		NBIO_BASE_INNER(seg)
+
+#define NBIO_SR(reg_name)\
+		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
+		mm ## reg_name
+
+/* DCN */
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+		.field_name = reg_name ## __ ## field_name ## post_fix
+
+#define SRI(reg_name, block, id)\
+		.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
+
+#define SRII(reg_name, block, id)\
+		.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+		mm ## block ## id ## _ ## reg_name
+
+#define DCCG_SRII(reg_name, block, id)\
+		.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+		mm ## block ## id ## _ ## reg_name
+
+#define VUPDATE_SRII(reg_name, block, id)\
+		.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
+		mm ## reg_name ## _ ## block ## id
+
+#define SRII_DWB(reg_name, temp_name, block, id)\
+		.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
+		mm ## block ## id ## _ ## temp_name
+
+#define SRII_MPC_RMU(reg_name, block, id)\
+		.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+		mm ## block ## id ## _ ## reg_name
+
+static const struct dcn_hubbub_registers hubbub_reg = {
+		HUBBUB_REG_LIST_DCN30(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+		HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+		HUBBUB_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define vmid_regs(id)\
+		[id] = { DCN20_VMID_REG_LIST(id) }
+
+static const struct dcn_vmid_registers vmid_regs[] = {
+		vmid_regs(0),
+		vmid_regs(1),
+		vmid_regs(2),
+		vmid_regs(3),
+		vmid_regs(4),
+		vmid_regs(5),
+		vmid_regs(6),
+		vmid_regs(7),
+		vmid_regs(8),
+		vmid_regs(9),
+		vmid_regs(10),
+		vmid_regs(11),
+		vmid_regs(12),
+		vmid_regs(13),
+		vmid_regs(14),
+		vmid_regs(15)
+};
+
+static const struct dcn20_vmid_shift vmid_shifts = {
+		DCN20_VMID_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn20_vmid_mask vmid_masks = {
+		DCN20_VMID_MASK_SH_LIST(_MASK)
+};
+
+static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
+{
+	int i;
+
+	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
+
+	if (!hubbub3)
+		return NULL;
+
+	hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
+
+	for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
+		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
+
+		vmid->ctx = ctx;
+
+		vmid->regs = &vmid_regs[i];
+		vmid->shifts = &vmid_shifts;
+		vmid->masks = &vmid_masks;
+	}
+
+	return &hubbub3->base;
+}
+
+#define vpg_regs(id)\
+		[id] = { VPG_DCN3_REG_LIST(id) }
+
+static const struct dcn30_vpg_registers vpg_regs[] = {
+		vpg_regs(0),
+		vpg_regs(1),
+		vpg_regs(2),
+		vpg_regs(3),
+		vpg_regs(4),
+		vpg_regs(5)
+};
+
+static const struct dcn30_vpg_shift vpg_shift = {
+		DCN3_VPG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_vpg_mask vpg_mask = {
+		DCN3_VPG_MASK_SH_LIST(_MASK)
+};
+
+static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
+
+	if (!vpg3)
+		return NULL;
+
+	vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
+
+	return &vpg3->base;
+}
+
+#define afmt_regs(id)\
+		[id] = { AFMT_DCN3_REG_LIST(id) }
+
+static const struct dcn30_afmt_registers afmt_regs[] = {
+		afmt_regs(0),
+		afmt_regs(1),
+		afmt_regs(2),
+		afmt_regs(3),
+		afmt_regs(4),
+		afmt_regs(5)
+};
+
+static const struct dcn30_afmt_shift afmt_shift = {
+		DCN3_AFMT_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_afmt_mask afmt_mask = {
+		DCN3_AFMT_MASK_SH_LIST(_MASK)
+};
+
+static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
+
+	if (!afmt3)
+		return NULL;
+
+	afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
+
+	return &afmt3->base;
+}
+
+#define audio_regs(id)\
+		[id] = { AUD_COMMON_REG_LIST(id) }
+
+static const struct dce_audio_registers audio_regs[] = {
+		audio_regs(0),
+		audio_regs(1),
+		audio_regs(2),
+		audio_regs(3),
+		audio_regs(4),
+		audio_regs(5),
+		audio_regs(6)
+};
+
+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
+
+static const struct dce_audio_shift audio_shift = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_audio_mask audio_mask = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
+{
+	return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+#define stream_enc_regs(id)\
+		[id] = { SE_DCN3_REG_LIST(id) }
+
+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+		stream_enc_regs(0),
+		stream_enc_regs(1),
+		stream_enc_regs(2),
+		stream_enc_regs(3),
+		stream_enc_regs(4)
+};
+
+static const struct dcn10_stream_encoder_shift se_shift = {
+		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn10_stream_encoder_mask se_mask = {
+		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
+{
+	struct dcn10_stream_encoder *enc1;
+	struct vpg *vpg;
+	struct afmt *afmt;
+	int vpg_inst;
+	int afmt_inst;
+
+	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
+	if (eng_id <= ENGINE_ID_DIGE) {
+		vpg_inst = eng_id;
+		afmt_inst = eng_id;
+	} else
+		return NULL;
+
+	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
+	vpg = dcn302_vpg_create(ctx, vpg_inst);
+	afmt = dcn302_afmt_create(ctx, afmt_inst);
+
+	if (!enc1 || !vpg || !afmt)
+		return NULL;
+
+	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
+			&se_shift, &se_mask);
+
+	return &enc1->base;
+}
+
+#define clk_src_regs(index, pllid)\
+		[index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+		clk_src_regs(0, A),
+		clk_src_regs(1, B),
+		clk_src_regs(2, C),
+		clk_src_regs(3, D),
+		clk_src_regs(4, E)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+};
+
+static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
+		enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static const struct dce_hwseq_registers hwseq_reg = {
+		HWSEQ_DCN302_REG_LIST()
+};
+
+static const struct dce_hwseq_shift hwseq_shift = {
+		HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+		HWSEQ_DCN302_MASK_SH_LIST(_MASK)
+};
+
+static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
+{
+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+	if (hws) {
+		hws->ctx = ctx;
+		hws->regs = &hwseq_reg;
+		hws->shifts = &hwseq_shift;
+		hws->masks = &hwseq_mask;
+	}
+	return hws;
+}
+
+#define hubp_regs(id)\
+		[id] = { HUBP_REG_LIST_DCN30(id) }
+
+static const struct dcn_hubp2_registers hubp_regs[] = {
+		hubp_regs(0),
+		hubp_regs(1),
+		hubp_regs(2),
+		hubp_regs(3),
+		hubp_regs(4)
+};
+
+static const struct dcn_hubp2_shift hubp_shift = {
+		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn_hubp2_mask hubp_mask = {
+		HUBP_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
+
+	if (!hubp2)
+		return NULL;
+
+	if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
+		return &hubp2->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(hubp2);
+	return NULL;
+}
+
+#define dpp_regs(id)\
+		[id] = { DPP_REG_LIST_DCN30(id) }
+
+static const struct dcn3_dpp_registers dpp_regs[] = {
+		dpp_regs(0),
+		dpp_regs(1),
+		dpp_regs(2),
+		dpp_regs(3),
+		dpp_regs(4)
+};
+
+static const struct dcn3_dpp_shift tf_shift = {
+		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
+};
+
+static const struct dcn3_dpp_mask tf_mask = {
+		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
+};
+
+static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
+
+	if (!dpp)
+		return NULL;
+
+	if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
+		return &dpp->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(dpp);
+	return NULL;
+}
+
+#define opp_regs(id)\
+		[id] = { OPP_REG_LIST_DCN30(id) }
+
+static const struct dcn20_opp_registers opp_regs[] = {
+		opp_regs(0),
+		opp_regs(1),
+		opp_regs(2),
+		opp_regs(3),
+		opp_regs(4)
+};
+
+static const struct dcn20_opp_shift opp_shift = {
+		OPP_MASK_SH_LIST_DCN20(__SHIFT)
+};
+
+static const struct dcn20_opp_mask opp_mask = {
+		OPP_MASK_SH_LIST_DCN20(_MASK)
+};
+
+static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+
+	if (!opp) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
+	return &opp->base;
+}
+
+#define optc_regs(id)\
+		[id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
+
+static const struct dcn_optc_registers optc_regs[] = {
+		optc_regs(0),
+		optc_regs(1),
+		optc_regs(2),
+		optc_regs(3),
+		optc_regs(4)
+};
+
+static const struct dcn_optc_shift optc_shift = {
+		OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn_optc_mask optc_mask = {
+		OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
+{
+	struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
+
+	if (!tgn10)
+		return NULL;
+
+	tgn10->base.inst = instance;
+	tgn10->base.ctx = ctx;
+
+	tgn10->tg_regs = &optc_regs[instance];
+	tgn10->tg_shift = &optc_shift;
+	tgn10->tg_mask = &optc_mask;
+
+	dcn30_timing_generator_init(tgn10);
+
+	return &tgn10->base;
+}
+
+static const struct dcn30_mpc_registers mpc_regs = {
+		MPC_REG_LIST_DCN3_0(0),
+		MPC_REG_LIST_DCN3_0(1),
+		MPC_REG_LIST_DCN3_0(2),
+		MPC_REG_LIST_DCN3_0(3),
+		MPC_REG_LIST_DCN3_0(4),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(4),
+		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
+		MPC_RMU_REG_LIST_DCN3AG(0),
+		MPC_RMU_REG_LIST_DCN3AG(1),
+		MPC_RMU_REG_LIST_DCN3AG(2),
+		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
+};
+
+static const struct dcn30_mpc_shift mpc_shift = {
+		MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_mpc_mask mpc_mask = {
+		MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
+{
+	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
+
+	if (!mpc30)
+		return NULL;
+
+	dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
+
+	return &mpc30->base;
+}
+
+#define dsc_regsDCN20(id)\
+[id] = { DSC_REG_LIST_DCN20(id) }
+
+static const struct dcn20_dsc_registers dsc_regs[] = {
+		dsc_regsDCN20(0),
+		dsc_regsDCN20(1),
+		dsc_regsDCN20(2),
+		dsc_regsDCN20(3),
+		dsc_regsDCN20(4)
+};
+
+static const struct dcn20_dsc_shift dsc_shift = {
+		DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
+};
+
+static const struct dcn20_dsc_mask dsc_mask = {
+		DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+};
+
+static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
+
+	if (!dsc) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+	return &dsc->base;
+}
+
+#define dwbc_regs_dcn3(id)\
+[id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
+
+static const struct dcn30_dwbc_registers dwbc30_regs[] = {
+		dwbc_regs_dcn3(0)
+};
+
+static const struct dcn30_dwbc_shift dwbc30_shift = {
+		DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_dwbc_mask dwbc30_mask = {
+		DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t pipe_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < pipe_count; i++) {
+		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
+
+		if (!dwbc30) {
+			dm_error("DC: failed to create dwbc30!\n");
+			return false;
+		}
+
+		dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
+
+		pool->dwbc[i] = &dwbc30->base;
+	}
+	return true;
+}
+
+#define mcif_wb_regs_dcn3(id)\
+[id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
+
+static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
+		mcif_wb_regs_dcn3(0)
+};
+
+static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
+		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
+		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t pipe_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < pipe_count; i++) {
+		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
+
+		if (!mcif_wb30) {
+			dm_error("DC: failed to create mcif_wb30!\n");
+			return false;
+		}
+
+		dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
+
+		pool->mcif_wb[i] = &mcif_wb30->base;
+	}
+	return true;
+}
+
+#define aux_engine_regs(id)\
+[id] = {\
+		AUX_COMMON_REG_LIST0(id), \
+		.AUXN_IMPCAL = 0, \
+		.AUXP_IMPCAL = 0, \
+		.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+		aux_engine_regs(0),
+		aux_engine_regs(1),
+		aux_engine_regs(2),
+		aux_engine_regs(3),
+		aux_engine_regs(4)
+};
+
+static const struct dce110_aux_registers_shift aux_shift = {
+		DCN_AUX_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce110_aux_registers_mask aux_mask = {
+		DCN_AUX_MASK_SH_LIST(_MASK)
+};
+
+static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+	if (!aux_engine)
+		return NULL;
+
+	dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+			&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
+
+	return &aux_engine->base;
+}
+
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
+
+static const struct dce_i2c_registers i2c_hw_regs[] = {
+		i2c_inst_regs(1),
+		i2c_inst_regs(2),
+		i2c_inst_regs(3),
+		i2c_inst_regs(4),
+		i2c_inst_regs(5)
+};
+
+static const struct dce_i2c_shift i2c_shifts = {
+		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
+};
+
+static const struct dce_i2c_mask i2c_masks = {
+		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
+};
+
+static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
+{
+	struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+
+	if (!dce_i2c_hw)
+		return NULL;
+
+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
+
+	return dce_i2c_hw;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 600000,
+		.hdmi_ycbcr420_supported = true,
+		.dp_ycbcr420_supported = true,
+		.fec_supported = true,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_HBR3_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_TPS4_CAPABLE = true
+};
+
+#define link_regs(id, phyid)\
+		[id] = {\
+				LE_DCN3_REG_LIST(id), \
+				UNIPHY_DCN2_REG_LIST(phyid), \
+				SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
+		}
+
+static const struct dcn10_link_enc_registers link_enc_regs[] = {
+		link_regs(0, A),
+		link_regs(1, B),
+		link_regs(2, C),
+		link_regs(3, D),
+		link_regs(4, E)
+};
+
+static const struct dcn10_link_enc_shift le_shift = {
+		LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
+		DPCS_DCN2_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn10_link_enc_mask le_mask = {
+		LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
+		DPCS_DCN2_MASK_SH_LIST(_MASK)
+};
+
+#define aux_regs(id)\
+		[id] = { DCN2_AUX_REG_LIST(id) }
+
+static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
+		aux_regs(0),
+		aux_regs(1),
+		aux_regs(2),
+		aux_regs(3),
+		aux_regs(4)
+};
+
+#define hpd_regs(id)\
+		[id] = { HPD_REG_LIST(id) }
+
+static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
+		hpd_regs(0),
+		hpd_regs(1),
+		hpd_regs(2),
+		hpd_regs(3),
+		hpd_regs(4)
+};
+
+static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data)
+{
+	struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+
+	if (!enc20)
+		return NULL;
+
+	dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
+			&link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
+			&link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
+
+	return &enc20->enc10.base;
+}
+
+static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
+		{ DCN_PANEL_CNTL_REG_LIST() }
+};
+
+static const struct dce_panel_cntl_shift panel_cntl_shift = {
+		DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_panel_cntl_mask panel_cntl_mask = {
+		DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
+};
+
+static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
+{
+	struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
+
+	if (!panel_cntl)
+		return NULL;
+
+	dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
+			&panel_cntl_shift, &panel_cntl_mask);
+
+	return &panel_cntl->base;
+}
+
+static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
+{
+	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
+			FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
+}
+
+static const struct resource_create_funcs res_create_funcs = {
+		.read_dce_straps = read_dce_straps,
+		.create_audio = dcn302_create_audio,
+		.create_stream_encoder = dcn302_stream_encoder_create,
+		.create_hwseq = dcn302_hwseq_create,
+};
+
+static const struct resource_create_funcs res_create_maximus_funcs = {
+		.read_dce_straps = NULL,
+		.create_audio = NULL,
+		.create_stream_encoder = NULL,
+		.create_hwseq = dcn302_hwseq_create,
+};
+
+static bool is_soc_bounding_box_valid(struct dc *dc)
+{
+	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
+
+	if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
+		return true;
+
+	return false;
+}
+
+static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
+{
+	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
+	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
+
+	DC_LOGGER_INIT(dc->ctx->logger);
+
+	if (!is_soc_bounding_box_valid(dc)) {
+		DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
+		return false;
+	}
+
+	loaded_ip->max_num_otg = pool->pipe_count;
+	loaded_ip->max_num_dpp = pool->pipe_count;
+	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
+	dcn20_patch_bounding_box(dc, loaded_bb);
+	return true;
+}
+
+static void dcn302_resource_destruct(struct resource_pool *pool)
+{
+	unsigned int i;
+
+	for (i = 0; i < pool->stream_enc_count; i++) {
+		if (pool->stream_enc[i] != NULL) {
+			if (pool->stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
+				pool->stream_enc[i]->vpg = NULL;
+			}
+			if (pool->stream_enc[i]->afmt != NULL) {
+				kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
+				pool->stream_enc[i]->afmt = NULL;
+			}
+			kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
+			pool->stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->res_cap->num_dsc; i++) {
+		if (pool->dscs[i] != NULL)
+			dcn20_dsc_destroy(&pool->dscs[i]);
+	}
+
+	if (pool->mpc != NULL) {
+		kfree(TO_DCN20_MPC(pool->mpc));
+		pool->mpc = NULL;
+	}
+
+	if (pool->hubbub != NULL) {
+		kfree(pool->hubbub);
+		pool->hubbub = NULL;
+	}
+
+	for (i = 0; i < pool->pipe_count; i++) {
+		if (pool->dpps[i] != NULL) {
+			kfree(TO_DCN20_DPP(pool->dpps[i]));
+			pool->dpps[i] = NULL;
+		}
+
+		if (pool->hubps[i] != NULL) {
+			kfree(TO_DCN20_HUBP(pool->hubps[i]));
+			pool->hubps[i] = NULL;
+		}
+
+		if (pool->irqs != NULL)
+			dal_irq_service_destroy(&pool->irqs);
+	}
+
+	for (i = 0; i < pool->res_cap->num_ddc; i++) {
+		if (pool->engines[i] != NULL)
+			dce110_engine_destroy(&pool->engines[i]);
+		if (pool->hw_i2cs[i] != NULL) {
+			kfree(pool->hw_i2cs[i]);
+			pool->hw_i2cs[i] = NULL;
+		}
+		if (pool->sw_i2cs[i] != NULL) {
+			kfree(pool->sw_i2cs[i]);
+			pool->sw_i2cs[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->res_cap->num_opp; i++) {
+		if (pool->opps[i] != NULL)
+			pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
+	}
+
+	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
+		if (pool->timing_generators[i] != NULL)	{
+			kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
+			pool->timing_generators[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->res_cap->num_dwb; i++) {
+		if (pool->dwbc[i] != NULL) {
+			kfree(TO_DCN30_DWBC(pool->dwbc[i]));
+			pool->dwbc[i] = NULL;
+		}
+		if (pool->mcif_wb[i] != NULL) {
+			kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
+			pool->mcif_wb[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->audio_count; i++) {
+		if (pool->audios[i])
+			dce_aud_destroy(&pool->audios[i]);
+	}
+
+	for (i = 0; i < pool->clk_src_count; i++) {
+		if (pool->clock_sources[i] != NULL)
+			dcn20_clock_source_destroy(&pool->clock_sources[i]);
+	}
+
+	if (pool->dp_clock_source != NULL)
+		dcn20_clock_source_destroy(&pool->dp_clock_source);
+
+	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
+		if (pool->mpc_lut[i] != NULL) {
+			dc_3dlut_func_release(pool->mpc_lut[i]);
+			pool->mpc_lut[i] = NULL;
+		}
+		if (pool->mpc_shaper[i] != NULL) {
+			dc_transfer_func_release(pool->mpc_shaper[i]);
+			pool->mpc_shaper[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->pipe_count; i++) {
+		if (pool->multiple_abms[i] != NULL)
+			dce_abm_destroy(&pool->multiple_abms[i]);
+	}
+
+	if (pool->dccg != NULL)
+		dcn_dccg_destroy(&pool->dccg);
+}
+
+static void dcn302_destroy_resource_pool(struct resource_pool **pool)
+{
+	dcn302_resource_destruct(*pool);
+	kfree(*pool);
+	*pool = NULL;
+}
+
+static struct resource_funcs dcn302_res_pool_funcs = {
+		.destroy = dcn302_destroy_resource_pool,
+		.link_enc_create = dcn302_link_encoder_create,
+		.panel_cntl_create = dcn302_panel_cntl_create,
+		.validate_bandwidth = dcn30_validate_bandwidth,
+		.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
+		.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
+		.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+		.add_stream_to_ctx = dcn30_add_stream_to_ctx,
+		.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
+		.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+		.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
+		.set_mcif_arb_params = dcn30_set_mcif_arb_params,
+		.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
+		.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
+		.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
+		.update_bw_bounding_box = dcn30_update_bw_bounding_box,
+		.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+};
+
+static struct dc_cap_funcs cap_funcs = {
+		.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+};
+
+static const struct bios_registers bios_regs = {
+		NBIO_SR(BIOS_SCRATCH_3),
+		NBIO_SR(BIOS_SCRATCH_6)
+};
+
+static const struct dccg_registers dccg_regs = {
+		DCCG_REG_LIST_DCN3_02()
+};
+
+static const struct dccg_shift dccg_shift = {
+		DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
+};
+
+static const struct dccg_mask dccg_mask = {
+		DCCG_MASK_SH_LIST_DCN3_02(_MASK)
+};
+
+#define abm_regs(id)\
+		[id] = { ABM_DCN301_REG_LIST(id) }
+
+static const struct dce_abm_registers abm_regs[] = {
+		abm_regs(0),
+		abm_regs(1),
+		abm_regs(2),
+		abm_regs(3),
+		abm_regs(4)
+};
+
+static const struct dce_abm_shift abm_shift = {
+		ABM_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+		ABM_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static bool dcn302_resource_construct(
+		uint8_t num_virtual_links,
+		struct dc *dc,
+		struct resource_pool *pool)
+{
+	int i;
+	struct dc_context *ctx = dc->ctx;
+	struct irq_service_init_data init_data;
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->res_cap = &res_cap_dcn302;
+
+	pool->funcs = &dcn302_res_pool_funcs;
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->pipe_count = pool->res_cap->num_timing_generator;
+	pool->mpcc_count = pool->res_cap->num_timing_generator;
+	dc->caps.max_downscale_ratio = 600;
+	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.max_cursor_size = 256;
+	dc->caps.dmdata_alloc_size = 2048;
+
+	dc->caps.max_slave_planes = 1;
+	dc->caps.post_blend_color_processing = true;
+	dc->caps.force_dp_tps4_for_cp2520 = true;
+	dc->caps.extended_aux_timeout_support = true;
+	dc->caps.dmcub_support = true;
+
+	/* Color pipeline capabilities */
+	dc->caps.color.dpp.dcn_arch = 1;
+	dc->caps.color.dpp.input_lut_shared = 0;
+	dc->caps.color.dpp.icsc = 1;
+	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
+	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
+	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
+	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
+	dc->caps.color.dpp.post_csc = 1;
+	dc->caps.color.dpp.gamma_corr = 1;
+
+	dc->caps.color.dpp.hw_3d_lut = 1;
+	dc->caps.color.dpp.ogam_ram = 1;
+	// no OGAM ROM on DCN3
+	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
+	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
+	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
+	dc->caps.color.dpp.ocsc = 0;
+
+	dc->caps.color.mpc.gamut_remap = 1;
+	dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
+	dc->caps.color.mpc.ogam_ram = 1;
+	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
+	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
+	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
+	dc->caps.color.mpc.ocsc = 1;
+
+	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+		dc->debug = debug_defaults_drv;
+	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)
+		dc->debug = debug_defaults_diags;
+	else
+		dc->debug = debug_defaults_diags;
+
+	// Init the vm_helper
+	if (dc->vm_helper)
+		vm_helper_init(dc->vm_helper, 16);
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	/* Clock Sources for Pixel Clock*/
+	pool->clock_sources[DCN302_CLK_SRC_PLL0] =
+			dcn302_clock_source_create(ctx, ctx->dc_bios,
+					CLOCK_SOURCE_COMBO_PHY_PLL0,
+					&clk_src_regs[0], false);
+	pool->clock_sources[DCN302_CLK_SRC_PLL1] =
+			dcn302_clock_source_create(ctx, ctx->dc_bios,
+					CLOCK_SOURCE_COMBO_PHY_PLL1,
+					&clk_src_regs[1], false);
+	pool->clock_sources[DCN302_CLK_SRC_PLL2] =
+			dcn302_clock_source_create(ctx, ctx->dc_bios,
+					CLOCK_SOURCE_COMBO_PHY_PLL2,
+					&clk_src_regs[2], false);
+	pool->clock_sources[DCN302_CLK_SRC_PLL3] =
+			dcn302_clock_source_create(ctx, ctx->dc_bios,
+					CLOCK_SOURCE_COMBO_PHY_PLL3,
+					&clk_src_regs[3], false);
+	pool->clock_sources[DCN302_CLK_SRC_PLL4] =
+			dcn302_clock_source_create(ctx, ctx->dc_bios,
+					CLOCK_SOURCE_COMBO_PHY_PLL4,
+					&clk_src_regs[4], false);
+
+	pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
+
+	/* todo: not reuse phy_pll registers */
+	pool->dp_clock_source =
+			dcn302_clock_source_create(ctx, ctx->dc_bios,
+					CLOCK_SOURCE_ID_DP_DTO,
+					&clk_src_regs[0], true);
+
+	for (i = 0; i < pool->clk_src_count; i++) {
+		if (pool->clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* DCCG */
+	pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
+	if (pool->dccg == NULL) {
+		dm_error("DC: failed to create dccg!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* PP Lib and SMU interfaces */
+	init_soc_bounding_box(dc, pool);
+
+	/* DML */
+	dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
+
+	/* IRQ */
+	init_data.ctx = dc->ctx;
+	pool->irqs = dal_irq_service_dcn302_create(&init_data);
+	if (!pool->irqs)
+		goto create_fail;
+
+	/* HUBBUB */
+	pool->hubbub = dcn302_hubbub_create(ctx);
+	if (pool->hubbub == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create hubbub!\n");
+		goto create_fail;
+	}
+
+	/* HUBPs, DPPs, OPPs and TGs */
+	for (i = 0; i < pool->pipe_count; i++) {
+		pool->hubps[i] = dcn302_hubp_create(ctx, i);
+		if (pool->hubps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create hubps!\n");
+			goto create_fail;
+		}
+
+		pool->dpps[i] = dcn302_dpp_create(ctx, i);
+		if (pool->dpps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create dpps!\n");
+			goto create_fail;
+		}
+	}
+
+	for (i = 0; i < pool->res_cap->num_opp; i++) {
+		pool->opps[i] = dcn302_opp_create(ctx, i);
+		if (pool->opps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create output pixel processor!\n");
+			goto create_fail;
+		}
+	}
+
+	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
+		pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
+		if (pool->timing_generators[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto create_fail;
+		}
+	}
+	pool->timing_generator_count = i;
+
+	/* ABMs */
+	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
+		pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
+		if (pool->multiple_abms[i] == NULL) {
+			dm_error("DC: failed to create abm for pipe %d!\n", i);
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* MPC and DSC */
+	pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
+	if (pool->mpc == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mpc!\n");
+		goto create_fail;
+	}
+
+	for (i = 0; i < pool->res_cap->num_dsc; i++) {
+		pool->dscs[i] = dcn302_dsc_create(ctx, i);
+		if (pool->dscs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create display stream compressor %d!\n", i);
+			goto create_fail;
+		}
+	}
+
+	/* DWB and MMHUBBUB */
+	if (!dcn302_dwbc_create(ctx, pool)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create dwbc!\n");
+		goto create_fail;
+	}
+
+	if (!dcn302_mmhubbub_create(ctx, pool)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mcif_wb!\n");
+		goto create_fail;
+	}
+
+	/* AUX and I2C */
+	for (i = 0; i < pool->res_cap->num_ddc; i++) {
+		pool->engines[i] = dcn302_aux_engine_create(ctx, i);
+		if (pool->engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC:failed to create aux engine!!\n");
+			goto create_fail;
+		}
+		pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
+		if (pool->hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC:failed to create hw i2c!!\n");
+			goto create_fail;
+		}
+		pool->sw_i2cs[i] = NULL;
+	}
+
+	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
+	if (!resource_construct(num_virtual_links, dc, pool,
+			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
+					&res_create_funcs : &res_create_maximus_funcs)))
+		goto create_fail;
+
+	/* HW Sequencer and Plane caps */
+	dcn302_hw_sequencer_construct(dc);
+
+	dc->caps.max_planes =  pool->pipe_count;
+
+	for (i = 0; i < dc->caps.max_planes; ++i)
+		dc->caps.planes[i] = plane_cap;
+
+	dc->cap_funcs = cap_funcs;
+
+	return true;
+
+create_fail:
+
+	dcn302_resource_destruct(pool);
+
+	return false;
+}
+
+struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
+{
+	struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
+		return pool;
+
+	BREAK_TO_DEBUGGER();
+	kfree(pool);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.h b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.h
new file mode 100644
index 000000000000..71f7deed18e3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN302_RESOURCE_H_
+#define _DCN302_RESOURCE_H_
+
+#include "core_types.h"
+
+struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc);
+
+#endif /* _DCN302_RESOURCE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index b2cc2bf95712..b2cd8491c707 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -35,7 +35,6 @@
 
 struct dp_mst_stream_allocation_table;
 
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 /*
  * Allocate memory accessible by the GPU
  *
@@ -57,7 +56,6 @@ void dm_helpers_free_gpu_mem(
 		enum dc_gpu_mem_alloc_type type,
 		void *pvMem);
 
-#endif
 enum dc_edid_status dm_helpers_parse_edid_caps(
 	struct dc_context *ctx,
 	const struct dc_edid *edid,
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index 3586934df25f..fb41140e8381 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -279,13 +279,35 @@ struct pp_smu_funcs_rn {
 			struct dpm_clocks *clock_table);
 };
 
+struct pp_smu_funcs_vgh {
+	struct pp_smu pp_smu;
+
+	/*
+	 * reader and writer WM's are sent together as part of one table
+	 *
+	 * PPSMC_MSG_SetDriverDramAddrHigh
+	 * PPSMC_MSG_SetDriverDramAddrLow
+	 * PPSMC_MSG_TransferTableDram2Smu
+	 *
+	 */
+	// TODO: Check whether this is moved to DAL, and remove as needed
+	enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
+			struct pp_smu_wm_range_sets *ranges);
+
+	// TODO: Check whether this is moved to DAL, and remove as needed
+	enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
+			struct dpm_clocks *clock_table);
+
+	enum pp_smu_status (*notify_smu_timeout) (struct pp_smu *pp);
+};
+
 struct pp_smu_funcs {
 	struct pp_smu ctx;
 	union {
 		struct pp_smu_funcs_rv rv_funcs;
 		struct pp_smu_funcs_nv nv_funcs;
 		struct pp_smu_funcs_rn rn_funcs;
-
+		struct pp_smu_funcs_vgh vgh_funcs;
 	};
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index fdd1943c828d..9a3f2a44f882 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -31,8 +31,6 @@
 
 #define __DM_SERVICES_H__
 
-#include "amdgpu_dm_trace.h"
-
 /* TODO: remove when DC is complete. */
 #include "dm_services_types.h"
 #include "logger_interface.h"
@@ -49,43 +47,26 @@ irq_handler_idx dm_register_interrupt(
 	interrupt_handler ih,
 	void *handler_args);
 
-
 /*
  *
  * GPU registers access
  *
  */
-uint32_t dm_read_reg_func(
-	const struct dc_context *ctx,
-	uint32_t address,
-	const char *func_name);
+uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
+			  const char *func_name);
+
 /* enable for debugging new code, this adds 50k to the driver size. */
 /* #define DM_CHECK_ADDR_0 */
 
-#define dm_read_reg(ctx, address)	\
-		dm_read_reg_func(ctx, address, __func__)
-
+void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
+		       uint32_t value, const char *func_name);
 
+#define dm_read_reg(ctx, address)	\
+	dm_read_reg_func(ctx, address, __func__)
 
 #define dm_write_reg(ctx, address, value)	\
 	dm_write_reg_func(ctx, address, value, __func__)
 
-static inline void dm_write_reg_func(
-	const struct dc_context *ctx,
-	uint32_t address,
-	uint32_t value,
-	const char *func_name)
-{
-#ifdef DM_CHECK_ADDR_0
-	if (address == 0) {
-		DC_ERR("invalid register write. address = 0");
-		return;
-	}
-#endif
-	cgs_write_register(ctx->cgs_device, address, value);
-	trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
-}
-
 static inline uint32_t dm_read_index_reg(
 	const struct dc_context *ctx,
 	enum cgs_ind_reg addr_space,
@@ -287,13 +268,10 @@ unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
 /*
  * performance tracing
  */
-#define PERF_TRACE()	trace_amdgpu_dc_performance(CTX->perf_trace->read_count,\
-		CTX->perf_trace->write_count, &CTX->perf_trace->last_entry_read,\
-		&CTX->perf_trace->last_entry_write, __func__, __LINE__)
-#define PERF_TRACE_CTX(__CTX)	trace_amdgpu_dc_performance(__CTX->perf_trace->read_count,\
-		__CTX->perf_trace->write_count, &__CTX->perf_trace->last_entry_read,\
-		&__CTX->perf_trace->last_entry_write, __func__, __LINE__)
+void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc_context *ctx);
 
+#define PERF_TRACE()	dm_perf_trace_timestamp(__func__, __LINE__, CTX)
+#define PERF_TRACE_CTX(__CTX)	dm_perf_trace_timestamp(__func__, __LINE__, __CTX)
 
 /*
  * Debug and verification hooks
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index dbc7e2abe379..a02a33dcd70b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -64,6 +64,9 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) -Wframe-larger-than=2048
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
+CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_rcflags)
@@ -71,10 +74,9 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_rcflag
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_rcflags)
-endif
-ifdef CONFIG_DRM_AMD_DC_DCN3_0
-CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) -Wframe-larger-than=2048
-CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)
 endif
 CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_ccflags)
@@ -87,9 +89,6 @@ ifdef CONFIG_DRM_AMD_DC_DCN
 DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
 DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
 DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
-endif
-
-ifdef CONFIG_DRM_AMD_DC_DCN3_0
 DML += dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
 endif
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 9e0ae18e71fa..319dec59bcd1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -23,7 +23,7 @@
  *
  */
 
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+#ifdef CONFIG_DRM_AMD_DC_DCN
 #include "dc.h"
 #include "dc_link.h"
 #include "../display_mode_lib.h"
@@ -3628,7 +3628,7 @@ static double TruncToValidBPP(
 			}
 		}
 	} else {
-		if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0)) ||
+		if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0 || DesiredBPP == 18)) ||
 				(DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) {
 			return BPP_INVALID;
 		} else {
@@ -6870,4 +6870,4 @@ static void UseMinimumDCFCLK(
 	}
 }
 
-#endif /* CONFIG_DRM_AMD_DC_DCN3_0 */
+#endif /* CONFIG_DRM_AMD_DC_DCN */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
index 416bf6fb67bd..5b5916b5bc71 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
@@ -23,7 +23,7 @@
  *
  */
 
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+#ifdef CONFIG_DRM_AMD_DC_DCN
 
 #include "../display_mode_lib.h"
 #include "../display_mode_vba.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
index 950ba04d7503..098d6433f7f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -31,11 +31,9 @@
 #include "dcn20/display_rq_dlg_calc_20v2.h"
 #include "dcn21/display_mode_vba_21.h"
 #include "dcn21/display_rq_dlg_calc_21.h"
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 #include "dcn30/display_mode_vba_30.h"
 #include "dcn30/display_rq_dlg_calc_30.h"
 #include "dml_logger.h"
-#endif
 
 const struct dml_funcs dml20_funcs = {
 	.validate = dml20_ModeSupportAndSystemConfigurationFull,
@@ -58,14 +56,13 @@ const struct dml_funcs dml21_funcs = {
         .rq_dlg_get_rq_reg = dml21_rq_dlg_get_rq_reg
 };
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 const struct dml_funcs dml30_funcs = {
 	.validate = dml30_ModeSupportAndSystemConfigurationFull,
 	.recalculate = dml30_recalculate,
 	.rq_dlg_get_dlg_reg = dml30_rq_dlg_get_dlg_reg,
 	.rq_dlg_get_rq_reg = dml30_rq_dlg_get_rq_reg
 };
-#endif
+
 void dml_init_instance(struct display_mode_lib *lib,
 		const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
 		const struct _vcs_dpi_ip_params_st *ip_params,
@@ -84,11 +81,9 @@ void dml_init_instance(struct display_mode_lib *lib,
         case DML_PROJECT_DCN21:
                 lib->funcs = dml21_funcs;
                 break;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case DML_PROJECT_DCN30:
 		lib->funcs = dml30_funcs;
 		break;
-#endif
 
 	default:
 		break;
@@ -123,7 +118,7 @@ const char *dml_get_status_message(enum dm_validation_status status)
 	default:                                  return "Unknown Status";
 	}
 }
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+
 void dml_log_pipe_params(
 		struct display_mode_lib *mode_lib,
 		display_e2e_pipe_params_st *pipes,
@@ -285,4 +280,3 @@ void dml_log_mode_support_params(struct display_mode_lib *mode_lib)
 		dml_print("DML SUPPORT:     ImmediateFlipSupportedForState      : [%d, %d]\n", mode_lib->vba.ImmediateFlipSupportedForState[i][0], mode_lib->vba.ImmediateFlipSupportedForState[i][1]);
 	}
 }
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index 6adee8a9ee56..6ae5df58a4fc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -37,9 +37,7 @@ enum dml_project {
 	DML_PROJECT_NAVI10,
 	DML_PROJECT_NAVI10v2,
 	DML_PROJECT_DCN21,
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	DML_PROJECT_DCN30,
-#endif
 };
 
 struct display_mode_lib;
@@ -81,12 +79,10 @@ void dml_init_instance(struct display_mode_lib *lib,
 
 const char *dml_get_status_message(enum dm_validation_status status);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 void dml_log_pipe_params(
 		struct display_mode_lib *mode_lib,
 		display_e2e_pipe_params_st *pipes,
 		int pipe_cnt);
 
 void dml_log_mode_support_params(struct display_mode_lib *mode_lib);
-#endif  // CONFIG_DRM_AMD_DC_DCN3_0
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 6ab74640c0da..162464261205 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -126,9 +126,7 @@ struct _vcs_dpi_soc_bounding_box_st {
 
 struct _vcs_dpi_ip_params_st {
 	bool use_min_dcfclk;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	bool clamp_min_dcfclk;
-#endif
 	bool gpuvm_enable;
 	bool hostvm_enable;
 	bool dsc422_native_support;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index b32093136089..62740d4e423d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -288,9 +288,7 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib)
 
 	// IP Parameters
 	mode_lib->vba.UseMinimumRequiredDCFCLK = ip->use_min_dcfclk;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	mode_lib->vba.ClampMinDCFCLK = ip->clamp_min_dcfclk;
-#endif
 	mode_lib->vba.MaxNumDPP = ip->max_num_dpp;
 	mode_lib->vba.MaxNumOTG = ip->max_num_otg;
 	mode_lib->vba.MaxNumHDMIFRLOutputs = ip->max_num_hdmi_frl_outputs;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 21e5111ea7a0..4d4ed1287673 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -919,9 +919,7 @@ struct vba_vars_st {
 	double BPP;
 	enum odm_combine_policy ODMCombinePolicy;
 	bool UseMinimumRequiredDCFCLK;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	bool ClampMinDCFCLK;
-#endif
 	bool AllowDramClockChangeOneDisplayVactive;
 	bool SynchronizeTimingsIfSingleRefreshRate;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 4c844cfaa956..c62d0eddc9c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -545,6 +545,7 @@ static bool setup_dsc_config(
 		int target_bandwidth_kbps,
 		const struct dc_crtc_timing *timing,
 		int min_slice_height_override,
+		int max_dsc_target_bpp_limit_override,
 		struct dc_dsc_config *dsc_cfg)
 {
 	struct dsc_enc_caps dsc_common_caps;
@@ -563,7 +564,7 @@ static bool setup_dsc_config(
 
 	memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));
 
-	dc_dsc_get_policy_for_timing(timing, &policy);
+	dc_dsc_get_policy_for_timing(timing, max_dsc_target_bpp_limit_override, &policy);
 	pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
 	pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
 
@@ -863,9 +864,9 @@ bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, const uint8_t *dpcd_dsc_basic_da
  */
 bool dc_dsc_compute_bandwidth_range(
 		const struct display_stream_compressor *dsc,
-		const uint32_t dsc_min_slice_height_override,
-		const uint32_t min_bpp,
-		const uint32_t max_bpp,
+		uint32_t dsc_min_slice_height_override,
+		uint32_t min_bpp,
+		uint32_t max_bpp,
 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
 		const struct dc_crtc_timing *timing,
 		struct dc_dsc_bw_range *range)
@@ -882,7 +883,7 @@ bool dc_dsc_compute_bandwidth_range(
 
 	if (is_dsc_possible)
 		is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing,
-				dsc_min_slice_height_override, &config);
+				dsc_min_slice_height_override, max_bpp, &config);
 
 	if (is_dsc_possible)
 		get_dsc_bandwidth_range(min_bpp, max_bpp, &dsc_common_caps, timing, range);
@@ -893,7 +894,8 @@ bool dc_dsc_compute_bandwidth_range(
 bool dc_dsc_compute_config(
 		const struct display_stream_compressor *dsc,
 		const struct dsc_dec_dpcd_caps *dsc_sink_caps,
-		const uint32_t dsc_min_slice_height_override,
+		uint32_t dsc_min_slice_height_override,
+		uint32_t max_target_bpp_limit_override,
 		uint32_t target_bandwidth_kbps,
 		const struct dc_crtc_timing *timing,
 		struct dc_dsc_config *dsc_cfg)
@@ -905,11 +907,12 @@ bool dc_dsc_compute_config(
 	is_dsc_possible = setup_dsc_config(dsc_sink_caps,
 			&dsc_enc_caps,
 			target_bandwidth_kbps,
-			timing, dsc_min_slice_height_override, dsc_cfg);
+			timing, dsc_min_slice_height_override,
+			max_target_bpp_limit_override, dsc_cfg);
 	return is_dsc_possible;
 }
 
-void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, struct dc_dsc_policy *policy)
+void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override, struct dc_dsc_policy *policy)
 {
 	uint32_t bpc = 0;
 
@@ -963,10 +966,15 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, struct dc
 	default:
 		return;
 	}
+
 	/* internal upper limit, default 16 bpp */
 	if (policy->max_target_bpp > dsc_policy_max_target_bpp_limit)
 		policy->max_target_bpp = dsc_policy_max_target_bpp_limit;
 
+	/* apply override */
+	if (max_target_bpp_limit_override && policy->max_target_bpp > max_target_bpp_limit_override)
+		policy->max_target_bpp = max_target_bpp_limit_override;
+
 	/* enable DSC when not needed, default false */
 	if (dsc_policy_enable_dsc_when_not_needed)
 		policy->enable_dsc_when_not_needed = dsc_policy_enable_dsc_when_not_needed;
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
index 4da21966ddce..c6a1cd80aeae 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
@@ -51,7 +51,7 @@ static void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc,
 	const struct qp_entry *table = 0L;
 
 	// alias enum
-	enum { min = MM_MIN, max = MM_MAX };
+	enum { min = DAL_MM_MIN, max = DAL_MM_MAX };
 	switch (sel) {
 		TABLE_CASE(444,  8, max);
 		TABLE_CASE(444,  8, min);
@@ -233,8 +233,8 @@ static void _do_calc_rc_params(struct rc_params *rc, enum colour_mode cm,
 	rc->flatness_max_qp     = ((bpc == BPC_8) ? (12) : ((bpc == BPC_10) ? (16) : (20))) - ((minor_version == 1 && cm == CM_444) ? 1 : 0);
 	rc->flatness_det_thresh = 2 << (bpc - 8);
 
-	get_qp_set(rc->qp_min, cm, bpc, MM_MIN, bpp);
-	get_qp_set(rc->qp_max, cm, bpc, MM_MAX, bpp);
+	get_qp_set(rc->qp_min, cm, bpc, DAL_MM_MIN, bpp);
+	get_qp_set(rc->qp_max, cm, bpc, DAL_MM_MAX, bpp);
 	if (cm == CM_444 && minor_version == 1) {
 		for (i = 0; i < QP_SET_SIZE; ++i) {
 			rc->qp_min[i] = rc->qp_min[i] > 0 ? rc->qp_min[i] - 1 : 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
index 21723fa6561e..8123827840c5 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h
@@ -66,8 +66,8 @@ enum bits_per_comp {
 };
 
 enum max_min {
-	MM_MIN = 0,
-	MM_MAX = 1
+	DAL_MM_MIN = 0,
+	DAL_MM_MAX = 1
 };
 
 struct qp_entry {
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 74c0943ed644..c5ddade8b187 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -47,7 +47,7 @@ endif
 ###############################################################################
 # all DCE8.x are derived from DCE8.0
 GPIO_DCE80 = hw_translate_dce80.o hw_factory_dce80.o
-	
+
 AMD_DAL_GPIO_DCE80 = $(addprefix $(AMDDALPATH)/dc/gpio/dce80/,$(GPIO_DCE80))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE80)
@@ -97,11 +97,10 @@ GPIO_DCN21 = hw_translate_dcn21.o hw_factory_dcn21.o
 AMD_DAL_GPIO_DCN21 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn21/,$(GPIO_DCN21))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN21)
-endif
+
 ###############################################################################
 # DCN 3
 ###############################################################################
-ifdef CONFIG_DRM_AMD_DC_DCN3_0
 GPIO_DCN30 = hw_translate_dcn30.o hw_factory_dcn30.o
 
 AMD_DAL_GPIO_DCN30 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn30/,$(GPIO_DCN30))
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
index 21583699f992..5f6ae3edb755 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c
@@ -22,7 +22,7 @@
  * Authors: AMD
  *
  */
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 #include "dm_services.h"
 #include "include/gpio_types.h"
 #include "../hw_factory.h"
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.h
index 7ad15f5aa95f..131e742b050a 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.h
@@ -22,7 +22,7 @@
  * Authors: AMD
  *
  */
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 #ifndef __DAL_HW_FACTORY_DCN30_H__
 #define __DAL_HW_FACTORY_DCN30_H__
 
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
index c2f42e0248b3..0046219a1cc7 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
@@ -26,7 +26,7 @@
 /*
  * Pre-requisites: headers required by header of this unit
  */
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 #include "hw_translate_dcn30.h"
 
 #include "dm_services.h"
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.h
index fe6c3f84aef9..ed55410b7a4e 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.h
@@ -22,7 +22,7 @@
  * Authors: AMD
  *
  */
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 #ifndef __DAL_HW_TRANSLATE_DCN30_H__
 #define __DAL_HW_TRANSLATE_DCN30_H__
 
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 6fc8a6e9dc15..da73bfb3cacd 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -52,8 +52,6 @@
 #include "dcn10/hw_factory_dcn10.h"
 #include "dcn20/hw_factory_dcn20.h"
 #include "dcn21/hw_factory_dcn21.h"
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #include "dcn30/hw_factory_dcn30.h"
 #endif
 
@@ -104,16 +102,15 @@ bool dal_hw_factory_init(
 	case DCN_VERSION_1_01:
 		dal_hw_factory_dcn10_init(factory);
 		return true;
-
 	case DCN_VERSION_2_0:
 		dal_hw_factory_dcn20_init(factory);
 		return true;
 	case DCN_VERSION_2_1:
 		dal_hw_factory_dcn21_init(factory);
 		return true;
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case DCN_VERSION_3_0:
+	case DCN_VERSION_3_01:
+	case DCN_VERSION_3_02:
 		dal_hw_factory_dcn30_init(factory);
 		return true;
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 3a93c945e57d..da9499c09a11 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -50,8 +50,6 @@
 #include "dcn10/hw_translate_dcn10.h"
 #include "dcn20/hw_translate_dcn20.h"
 #include "dcn21/hw_translate_dcn21.h"
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #include "dcn30/hw_translate_dcn30.h"
 #endif
 
@@ -99,16 +97,15 @@ bool dal_hw_translate_init(
 	case DCN_VERSION_1_01:
 		dal_hw_translate_dcn10_init(translate);
 		return true;
-
 	case DCN_VERSION_2_0:
 		dal_hw_translate_dcn20_init(translate);
 		return true;
 	case DCN_VERSION_2_1:
 		dal_hw_translate_dcn21_init(translate);
 		return true;
-#endif
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	case DCN_VERSION_3_0:
+	case DCN_VERSION_3_01:
+	case DCN_VERSION_3_02:
 		dal_hw_translate_dcn30_init(translate);
 		return true;
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index f932801235c6..d34b0b0eea65 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -50,6 +50,9 @@ enum dc_status {
 	DC_FAIL_CLK_BELOW_MIN = 22, /*THIS IS MIN PER IP*/
 	DC_FAIL_CLK_BELOW_CFG_REQUIRED = 23, /*THIS IS hard_min in PPLIB*/
 
+	DC_NOT_SUPPORTED = 24,
+	DC_UNSUPPORTED_VALUE = 25,
+
 	DC_ERROR_UNEXPECTED = -1
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 6e6bc66e49f0..2ce8c39ca6f5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -151,7 +151,7 @@ struct resource_funcs {
 	void (*update_bw_bounding_box)(
 			struct dc *dc,
 			struct clk_bw_params *bw_params);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool (*acquire_post_bldn_3dlut)(
 			struct resource_context *res_ctx,
 			const struct resource_pool *pool,
@@ -209,7 +209,7 @@ struct resource_pool {
 	unsigned int underlay_pipe_index;
 	unsigned int stream_enc_count;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	struct dc_3dlut *mpc_lut[MAX_PIPES];
 	struct dc_transfer_func *mpc_shaper[MAX_PIPES];
 #endif
@@ -241,7 +241,7 @@ struct resource_pool {
 	struct dmcu *dmcu;
 	struct dmub_psr *psr;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	struct abm *multiple_abms[MAX_PIPES];
 #endif
 
@@ -341,7 +341,7 @@ struct resource_context {
 	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
 	uint8_t dp_clock_source_ref_count;
 	bool is_dsc_acquired[MAX_PIPES];
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool is_mpc_3dlut_acquired[MAX_PIPES];
 #endif
 };
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 947d6106f341..3a29f379d0c8 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -43,7 +43,6 @@
 #define DCN_MINIMUM_DISPCLK_Khz 100000
 #define DCN_MINIMUM_DPPCLK_Khz 100000
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 struct dcn3_clk_internal {
 	int dummy;
 	/*TODO:
@@ -61,7 +60,21 @@ struct dcn3_clk_internal {
 	*/
 };
 
-#endif
+struct dcn301_clk_internal {
+	int dummy;
+	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
+	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
+	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
+	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
+	uint32_t CLK1_CLK3_DS_CNTL;	//dcf_deep_sleep_divider
+	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow
+
+	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
+	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
+	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
+	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
+};
+
 /* Will these bw structures be ASIC specific? */
 
 #define MAX_NUM_DPM_LVL		8
@@ -74,12 +87,10 @@ struct clk_limit_table_entry {
 	unsigned int fclk_mhz;
 	unsigned int memclk_mhz;
 	unsigned int socclk_mhz;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	unsigned int dtbclk_mhz;
 	unsigned int dispclk_mhz;
 	unsigned int dppclk_mhz;
 	unsigned int phyclk_mhz;
-#endif
 };
 
 /* This table is contiguous */
@@ -97,8 +108,6 @@ struct wm_range_table_entry {
 	bool valid;
 };
 
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
-
 struct nv_wm_range_entry {
 	bool valid;
 
@@ -116,7 +125,6 @@ struct nv_wm_range_entry {
 		double sr_enter_plus_exit_time_us;
 	} dml_input;
 };
-#endif
 
 struct clk_log_info {
 	bool enabled;
@@ -188,14 +196,10 @@ struct clk_bypass {
  * D occupied, C will be emptry.
  */
 struct wm_table {
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	union {
 		struct nv_wm_range_entry nv_entries[WM_SET_COUNT];
-#endif
-	struct wm_range_table_entry entries[WM_SET_COUNT];
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
+		struct wm_range_table_entry entries[WM_SET_COUNT];
 	};
-#endif
 };
 
 struct dummy_pstate_entry {
@@ -246,7 +250,6 @@ struct clk_mgr_funcs {
 
 	/* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
 	void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link);
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	/*
 	 * Send message to PMFW to set hard min memclk frequency
 	 * When current_mode = false, set DPM0
@@ -259,7 +262,14 @@ struct clk_mgr_funcs {
 
 	/* Get current memclk states from PMFW, update relevant structures */
 	void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr);
-#endif
+};
+
+struct dpm_clocks;
+struct wartermarks;
+
+struct smu_watermark_set {
+	struct watermarks *wm_set;
+	union large_integer mc_address;
 };
 
 struct clk_mgr {
@@ -267,14 +277,13 @@ struct clk_mgr {
 	struct clk_mgr_funcs *funcs;
 	struct dc_clocks clks;
 	bool psr_allow_active_cache;
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	bool force_smu_not_present;
-#endif
 	int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
 	int dentist_vco_freq_khz;
 	struct clk_state_registers_and_bypass boot_snapshot;
 	struct clk_bw_params *bw_params;
 	struct pp_smu_wm_range_sets ranges;
+	struct smu_watermark_set smu_wm_set;
 };
 
 /* forward declarations */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 949b61351ede..ffd37696b6b9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -107,11 +107,9 @@ enum dentist_divider_range {
 	CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
 	CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
 
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 // TODO:
 #define CLK_REG_LIST_DCN3()	  \
 	SR(DENTIST_DISPCLK_CNTL)
-#endif
 
 #define CLK_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -185,10 +183,9 @@ struct clk_mgr_registers {
 	uint32_t CLK3_CLK2_DFS_CNTL;
 	uint32_t CLK3_CLK_PLL_REQ;
 
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	uint32_t CLK0_CLK2_DFS_CNTL;
 	uint32_t CLK0_CLK_PLL_REQ;
-#endif
+
 	uint32_t MP1_SMN_C2PMSG_67;
 	uint32_t MP1_SMN_C2PMSG_83;
 	uint32_t MP1_SMN_C2PMSG_91;
@@ -285,12 +282,10 @@ struct clk_mgr_internal {
 	bool periodic_retraining_disabled;
 
 	unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 
 	bool smu_present;
 	void *wm_range_table;
 	long long wm_range_table_addr;
-#endif
 };
 
 struct clk_mgr_internal_funcs {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index 65f182c8bf14..5425e92efcb8 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -31,9 +31,7 @@ enum dcc_control {
 	dcc_control__256_256_xxx,
 	dcc_control__128_128_xxx,
 	dcc_control__256_64_64,
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	dcc_control__256_128_128,
-#endif
 };
 
 enum segment_order {
@@ -65,9 +63,7 @@ enum dcn_hubbub_page_table_depth {
 enum dcn_hubbub_page_table_block_size {
 	DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0,
 	DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4,
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3
-#endif
 };
 
 struct dcn_hubbub_phys_addr_config {
@@ -152,6 +148,10 @@ struct hubbub_funcs {
 	void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub);
 
 	void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub);
+
+	void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);
+
+	void (*init_watermarks)(struct hubbub *hubbub);
 };
 
 struct hubbub {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 0491720c5fe9..6751186f6f90 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -121,13 +121,11 @@ struct CM_bias_params {
 };
 
 struct dpp_funcs {
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	bool (*dpp_program_gamcor_lut)(
 		struct dpp *dpp_base, const struct pwl_params *params);
 
 	void (*dpp_set_pre_degam)(struct dpp *dpp_base,
 			enum dc_transfer_func_predefined tr);
-#endif
 
 	void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
 		uint32_t enable, uint32_t additive_blending);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
index 3407e5da5534..ec28cb9c3a8e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -72,14 +72,14 @@ enum wbscl_coef_filter_type_sel {
 };
 
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 enum dwb_boundary_mode {
 	DWBSCL_BOUNDARY_MODE_EDGE  = 0,
 	DWBSCL_BOUNDARY_MODE_BLACK = 1
 };
 #endif
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 enum dwb_output_csc_mode {
 	DWB_OUTPUT_CSC_DISABLE = 0,
 	DWB_OUTPUT_CSC_COEF_A = 1,
@@ -209,7 +209,7 @@ struct dwbc_funcs {
 		struct dwb_warmup_params *warmup_params);
 
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 
 	void (*dwb_program_output_csc)(
 		struct dwbc *dwbc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 286cceeb9c24..315e3061c592 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -48,10 +48,8 @@ enum cursor_lines_per_chunk {
 enum hubp_ind_block_size {
 	hubp_ind_block_unconstrained = 0,
 	hubp_ind_block_64b,
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	hubp_ind_block_128b,
 	hubp_ind_block_64b_no_128bcl,
-#endif
 };
 
 struct hubp {
@@ -187,6 +185,9 @@ struct hubp_funcs {
 			struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
 			struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
 			struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr);
+	void (*set_unbounded_requesting)(
+		struct hubp *hubp,
+		bool enable);
 
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index f62ccf242f56..a3a27c16aa2f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -150,14 +150,12 @@ enum ipp_degamma_mode {
 	IPP_DEGAMMA_MODE_USER_PWL
 };
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 enum gamcor_mode {
 	GAMCOR_MODE_BYPASS,
 	GAMCOR_MODE_RESERVED_1,
 	GAMCOR_MODE_USER_PWL,
 	GAMCOR_MODE_RESERVED_3
 };
-#endif
 
 enum ipp_output_format {
 	IPP_OUTPUT_FORMAT_12_BIT_FIX,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index c2b392a533b1..7f5acd8fb918 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -90,7 +90,8 @@ union psr_error_status {
 	struct {
 		unsigned char LINK_CRC_ERROR        :1;
 		unsigned char RFB_STORAGE_ERROR     :1;
-		unsigned char RESERVED              :6;
+		unsigned char VSC_SDP_ERROR         :1;
+		unsigned char RESERVED              :5;
 	} bits;
 	unsigned char raw;
 };
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
index aeab7fd782b8..15cb782f129b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
@@ -43,9 +43,7 @@ struct mcif_arb_params {
 	unsigned int		arbitration_slice;
 	unsigned int		slice_lines;
 	unsigned int		max_scaled_time;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	unsigned int		dram_speed_change_duration;
-#endif
 };
 
 struct mcif_irq_params {
@@ -75,11 +73,9 @@ struct mcif_wb {
 
 struct mcif_wb_funcs {
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	void (*warmup_mcif)(
 		struct mcif_wb *mcif_wb,
 		struct mcif_warmup_params *params);
-#endif
 	void (*enable_mcif)(struct mcif_wb *mcif_wb);
 
 	void (*disable_mcif)(struct mcif_wb *mcif_wb);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index b2892eab5e02..879f502ae530 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -32,11 +32,7 @@
 #define MAX_MPCC 6
 #define MAX_OPP 6
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 #define MAX_DWB		2
-#else
-#define MAX_DWB		1
-#endif
 
 enum mpc_output_csc_mode {
 	MPC_OUTPUT_CSC_DISABLE = 0,
@@ -77,12 +73,11 @@ struct mpcc_blnd_cfg {
 	int bottom_outside_gain;
 };
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 struct mpc_grph_gamut_adjustment {
 	struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
 	enum graphics_gamut_adjust_type gamut_adjust_type;
 };
-#endif
+
 struct mpcc_sm_cfg {
 	bool enable;
 	/* 0-single plane,2-row subsampling,4-column subsampling,6-checkboard subsampling */
@@ -106,13 +101,12 @@ struct mpc_denorm_clamp {
 	int clamp_min_b_cb;
 };
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 struct mpc_dwb_flow_control {
 	int flow_ctrl_mode;
 	int flow_ctrl_cnt0;
 	int flow_ctrl_cnt1;
 };
-#endif
+
 /*
  * MPCC connection and blending configuration for a single MPCC instance.
  * This struct is used as a node in an MPC tree.
@@ -123,9 +117,7 @@ struct mpcc {
 	struct mpcc *mpcc_bot;		/* pointer to bottom layer MPCC.  NULL when not connected */
 	struct mpcc_blnd_cfg blnd_cfg;	/* The blending configuration for this MPCC */
 	struct mpcc_sm_cfg sm_cfg;	/* stereo mix setting for this MPCC */
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	bool shared_bottom;		/* TRUE if MPCC output to both OPP and DWB endpoints, else FALSE */
-#endif
 };
 
 /*
@@ -247,7 +239,6 @@ struct mpc_funcs {
 			int opp_id,
 			bool lock);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	/*
 	 * Add DPP into 'secondary' MPC tree based on specified blending position.
 	 * Only used for planes that are part of blending chain for DWB output
@@ -290,7 +281,6 @@ struct mpc_funcs {
 	struct mpcc* (*get_mpcc_for_dpp_from_secondary)(
 			struct mpc_tree *tree,
 			int dpp_id);
-#endif
 	struct mpcc* (*get_mpcc_for_dpp)(
 			struct mpc_tree *tree,
 			int dpp_id);
@@ -330,7 +320,6 @@ struct mpc_funcs {
 			struct mpc *mpc,
 			int mpcc_id,
 			bool power_on);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	void (*set_dwb_mux)(
 			struct mpc *mpc,
 			int dwb_id,
@@ -350,9 +339,7 @@ struct mpc_funcs {
 		bool enable,
 		bool rate_2x_mode,
 		struct mpc_dwb_flow_control *flow_control);
-#endif
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	void (*set_gamut_remap)(
 			struct mpc *mpc,
 			int mpcc_id,
@@ -372,8 +359,6 @@ struct mpc_funcs {
 
 	int (*release_rmu)(struct mpc *mpc, int mpcc_id);
 
-#endif
-
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 2717352eb697..7617fabbd16e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -313,6 +313,11 @@ struct opp_funcs {
 			int height,
 			int offset);
 
+	void (*opp_program_dpg_dimensions)(
+				struct output_pixel_processor *opp,
+				int width,
+				int height);
+
 	bool (*dpg_is_blanked)(
 			struct output_pixel_processor *opp);
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 0184cefb083b..47c7e4c3a51b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -104,10 +104,8 @@ struct stream_encoder {
 	struct dc_bios *bp;
 	enum engine_id id;
 	uint32_t stream_enc_inst;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	struct vpg *vpg;
 	struct afmt *afmt;
-#endif
 };
 
 struct enc_state {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 084432132b16..12d5718caea8 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -98,19 +98,15 @@ enum crc_selection {
 	INTERSECT_WINDOW_NOT_A_NOT_B,
 };
 
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 enum otg_out_mux_dest {
 	OUT_MUX_DIO = 0,
 };
-#endif
 
 enum h_timing_div_mode {
 	H_TIMING_NO_DIV,
 	H_TIMING_DIV_BY2,
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	H_TIMING_RESERVED,
 	H_TIMING_DIV_BY4,
-#endif
 };
 
 struct crc_params {
@@ -288,7 +284,6 @@ struct timing_generator_funcs {
 	void (*set_gsl_source_select)(struct timing_generator *optc,
 			int group_idx,
 			uint32_t gsl_ready_signal);
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
 	void (*set_vrr_m_const)(struct timing_generator *optc,
 			double vtotal_avg);
@@ -296,7 +291,6 @@ struct timing_generator_funcs {
 			uint32_t window_start, uint32_t window_end);
 	void (*set_vtotal_change_limit)(struct timing_generator *optc,
 			uint32_t limit);
-#endif
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 64c1be818b0e..62804dc7b698 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -50,6 +50,7 @@ struct dpp;
 struct dce_hwseq;
 
 struct hw_sequencer_funcs {
+	void (*hardware_release)(struct dc *dc);
 	/* Embedded Display Related */
 	void (*edp_power_control)(struct dc_link *link, bool enable);
 	void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
@@ -67,8 +68,6 @@ struct hw_sequencer_funcs {
 			int num_planes, struct dc_state *context);
 	void (*program_front_end_for_ctx)(struct dc *dc,
 			struct dc_state *context);
-	bool (*disconnect_pipes)(struct dc *dc,
-			struct dc_state *context);
 	void (*wait_for_pending_cleared)(struct dc *dc,
 			struct dc_state *context);
 	void (*post_unlock_program_front_end)(struct dc *dc,
@@ -215,11 +214,19 @@ struct hw_sequencer_funcs {
 
 	void (*set_pipe)(struct pipe_ctx *pipe_ctx);
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	/* Idle Optimization Related */
 	bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
-#endif
 
+	bool (*is_abm_supported)(struct dc *dc,
+			struct dc_state *context, struct dc_stream_state *stream);
+
+	void (*set_disp_pattern_generator)(const struct dc *dc,
+			struct pipe_ctx *pipe_ctx,
+			enum controller_dp_test_pattern test_pattern,
+			enum controller_dp_color_space color_space,
+			enum dc_color_depth color_depth,
+			const struct tg_color *solid_color,
+			int width, int height, int offset);
 };
 
 void color_space_to_black_color(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index 9af7ee5bc8ee..33590a728fc5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -51,6 +51,7 @@ void dp_enable_link_phy(
 	const struct dc_link_settings *link_settings);
 
 void dp_receiver_power_ctrl(struct dc_link *link, bool on);
+void edp_add_delay_for_T9(struct dc_link *link);
 bool edp_receiver_ready_T9(struct dc_link *link);
 bool edp_receiver_ready_T7(struct dc_link *link);
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h
index dbd74d548de3..d89815a46190 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
@@ -48,9 +48,7 @@ struct resource_caps {
 	int num_ddc;
 	int num_vmid;
 	int num_dsc;
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
 	int num_mpc_3dlut;
-#endif
 };
 
 struct resource_straps {
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 405c25322607..ca8168726324 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -93,14 +93,20 @@ IRQ_DCN21 = irq_service_dcn21.o
 AMD_DAL_IRQ_DCN21= $(addprefix $(AMDDALPATH)/dc/irq/dcn21/,$(IRQ_DCN21))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN21)
-endif
 ###############################################################################
 # DCN 30
 ###############################################################################
-ifdef CONFIG_DRM_AMD_DC_DCN3_0
 IRQ_DCN3 = irq_service_dcn30.o
 
 AMD_DAL_IRQ_DCN3 = $(addprefix $(AMDDALPATH)/dc/irq/dcn30/,$(IRQ_DCN3))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN3)
+###############################################################################
+# DCN 3_02
+###############################################################################
+IRQ_DCN3_02 = irq_service_dcn302.o
+
+AMD_DAL_IRQ_DCN3_02 = $(addprefix $(AMDDALPATH)/dc/irq/dcn302/,$(IRQ_DCN3_02))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN3_02)
 endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
index 49689f71f4f1..a35b76772b9d 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
@@ -22,7 +22,7 @@
  *
  */
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 
 #include "dm_services.h"
 
@@ -306,8 +306,8 @@ irq_source_info_dcn30[DAL_IRQ_SOURCES_NUMBER] = {
 	pflip_int_entry(1),
 	pflip_int_entry(2),
 	pflip_int_entry(3),
-	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
-	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
+	pflip_int_entry(4),
+	pflip_int_entry(5),
 	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
 	gpio_pad_int_entry(0),
 	gpio_pad_int_entry(1),
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.h b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.h
index 5a00acaa1a18..080e21239688 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.h
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.h
@@ -23,7 +23,7 @@
  *
  */
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 
 #ifndef __DAL_IRQ_SERVICE_DCN30_H__
 #define __DAL_IRQ_SERVICE_DCN30_H__
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
new file mode 100644
index 000000000000..927fdc43fb9f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "irq_service_dcn302.h"
+
+#include "../dce110/irq_service_dce110.h"
+
+#include "dimgrey_cavefish_ip_offset.h"
+#include "dcn/dcn_3_0_0_offset.h"
+#include "dcn/dcn_3_0_0_sh_mask.h"
+
+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
+
+static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_service, uint32_t src_id, uint32_t ext_id)
+{
+	switch (src_id) {
+	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK1;
+	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK2;
+	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK3;
+	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK4;
+	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK5;
+	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK6;
+	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP1;
+	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP2;
+	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP3;
+	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP4;
+	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP5;
+	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP6;
+	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE1;
+	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE2;
+	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE3;
+	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE4;
+	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE5;
+	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE6;
+
+	case DCN_1_0__SRCID__DC_HPD1_INT:
+		/* generic src_id for all HPD and HPDRX interrupts */
+		switch (ext_id) {
+		case DCN_1_0__CTXID__DC_HPD1_INT:
+			return DC_IRQ_SOURCE_HPD1;
+		case DCN_1_0__CTXID__DC_HPD2_INT:
+			return DC_IRQ_SOURCE_HPD2;
+		case DCN_1_0__CTXID__DC_HPD3_INT:
+			return DC_IRQ_SOURCE_HPD3;
+		case DCN_1_0__CTXID__DC_HPD4_INT:
+			return DC_IRQ_SOURCE_HPD4;
+		case DCN_1_0__CTXID__DC_HPD5_INT:
+			return DC_IRQ_SOURCE_HPD5;
+		case DCN_1_0__CTXID__DC_HPD6_INT:
+			return DC_IRQ_SOURCE_HPD6;
+		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
+			return DC_IRQ_SOURCE_HPD1RX;
+		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
+			return DC_IRQ_SOURCE_HPD2RX;
+		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
+			return DC_IRQ_SOURCE_HPD3RX;
+		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
+			return DC_IRQ_SOURCE_HPD4RX;
+		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
+			return DC_IRQ_SOURCE_HPD5RX;
+		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
+			return DC_IRQ_SOURCE_HPD6RX;
+		default:
+			return DC_IRQ_SOURCE_INVALID;
+		}
+		break;
+
+	default:
+		return DC_IRQ_SOURCE_INVALID;
+	}
+}
+
+static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info)
+{
+	uint32_t addr = info->status_reg;
+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
+	uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED);
+
+	dal_irq_service_ack_generic(irq_service, info);
+
+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+	set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY);
+
+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+	return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+		.set = NULL,
+		.ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+		.set = NULL,
+		.ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+		.set = NULL,
+		.ack = NULL
+};
+
+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+		.set = NULL,
+		.ack = NULL
+};
+
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+/* compile time expand base address. */
+#define BASE(seg) BASE_INNER(seg)
+
+#define SRI(reg_name, block, id)\
+		BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+		mm ## block ## id ## _ ## reg_name
+
+
+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
+		.enable_reg = SRI(reg1, block, reg_num),\
+		.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+		.enable_value = {\
+				block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+				~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+		},\
+		.ack_reg = SRI(reg2, block, reg_num),\
+		.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
+		.ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
+
+
+
+#define hpd_int_entry(reg_num)\
+		[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
+				IRQ_REG_ENTRY(HPD, reg_num,\
+						DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
+						DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
+						.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+						.funcs = &hpd_irq_info_funcs\
+}
+
+#define hpd_rx_int_entry(reg_num)\
+		[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
+				IRQ_REG_ENTRY(HPD, reg_num,\
+						DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
+						DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
+						.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+						.funcs = &hpd_rx_irq_info_funcs\
+}
+#define pflip_int_entry(reg_num)\
+		[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
+				IRQ_REG_ENTRY(HUBPREQ, reg_num,\
+						DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
+						DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
+						.funcs = &pflip_irq_info_funcs\
+}
+
+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
+ */
+#define vupdate_no_lock_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
+		.funcs = &vupdate_no_lock_irq_info_funcs\
+	}
+
+#define vblank_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
+		.funcs = &vblank_irq_info_funcs\
+	}
+
+#define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }
+
+#define i2c_int_entry(reg_num) \
+		[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
+
+#define dp_sink_int_entry(reg_num) \
+		[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
+
+#define gpio_pad_int_entry(reg_num) \
+		[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
+
+#define dc_underflow_int_entry(reg_num) \
+		[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
+
+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
+		.set = dal_irq_service_dummy_set,
+		.ack = dal_irq_service_dummy_ack
+};
+
+static const struct irq_source_info irq_source_info_dcn302[DAL_IRQ_SOURCES_NUMBER] = {
+		[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
+		hpd_int_entry(0),
+		hpd_int_entry(1),
+		hpd_int_entry(2),
+		hpd_int_entry(3),
+		hpd_int_entry(4),
+		hpd_rx_int_entry(0),
+		hpd_rx_int_entry(1),
+		hpd_rx_int_entry(2),
+		hpd_rx_int_entry(3),
+		hpd_rx_int_entry(4),
+		i2c_int_entry(1),
+		i2c_int_entry(2),
+		i2c_int_entry(3),
+		i2c_int_entry(4),
+		i2c_int_entry(5),
+		dp_sink_int_entry(1),
+		dp_sink_int_entry(2),
+		dp_sink_int_entry(3),
+		dp_sink_int_entry(4),
+		dp_sink_int_entry(5),
+		[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
+		pflip_int_entry(0),
+		pflip_int_entry(1),
+		pflip_int_entry(2),
+		pflip_int_entry(3),
+		pflip_int_entry(4),
+		[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
+		gpio_pad_int_entry(0),
+		gpio_pad_int_entry(1),
+		gpio_pad_int_entry(2),
+		gpio_pad_int_entry(3),
+		gpio_pad_int_entry(4),
+		gpio_pad_int_entry(5),
+		gpio_pad_int_entry(6),
+		gpio_pad_int_entry(7),
+		gpio_pad_int_entry(8),
+		gpio_pad_int_entry(9),
+		gpio_pad_int_entry(10),
+		gpio_pad_int_entry(11),
+		gpio_pad_int_entry(12),
+		gpio_pad_int_entry(13),
+		gpio_pad_int_entry(14),
+		gpio_pad_int_entry(15),
+		gpio_pad_int_entry(16),
+		gpio_pad_int_entry(17),
+		gpio_pad_int_entry(18),
+		gpio_pad_int_entry(19),
+		gpio_pad_int_entry(20),
+		gpio_pad_int_entry(21),
+		gpio_pad_int_entry(22),
+		gpio_pad_int_entry(23),
+		gpio_pad_int_entry(24),
+		gpio_pad_int_entry(25),
+		gpio_pad_int_entry(26),
+		gpio_pad_int_entry(27),
+		gpio_pad_int_entry(28),
+		gpio_pad_int_entry(29),
+		gpio_pad_int_entry(30),
+		dc_underflow_int_entry(1),
+		dc_underflow_int_entry(2),
+		dc_underflow_int_entry(3),
+		dc_underflow_int_entry(4),
+		dc_underflow_int_entry(5),
+		[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
+		[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
+		vupdate_no_lock_int_entry(0),
+		vupdate_no_lock_int_entry(1),
+		vupdate_no_lock_int_entry(2),
+		vupdate_no_lock_int_entry(3),
+		vupdate_no_lock_int_entry(4),
+		vblank_int_entry(0),
+		vblank_int_entry(1),
+		vblank_int_entry(2),
+		vblank_int_entry(3),
+		vblank_int_entry(4),
+};
+
+static const struct irq_service_funcs irq_service_funcs_dcn302 = {
+		.to_dal_irq_source = to_dal_irq_source_dcn302
+};
+
+static void dcn302_irq_construct(struct irq_service *irq_service, struct irq_service_init_data *init_data)
+{
+	dal_irq_service_construct(irq_service, init_data);
+
+	irq_service->info = irq_source_info_dcn302;
+	irq_service->funcs = &irq_service_funcs_dcn302;
+}
+
+struct irq_service *dal_irq_service_dcn302_create(struct irq_service_init_data *init_data)
+{
+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL);
+
+	if (!irq_service)
+		return NULL;
+
+	dcn302_irq_construct(irq_service, init_data);
+	return irq_service;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.h b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.h
new file mode 100644
index 000000000000..c8cd41bc7757
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_IRQ_SERVICE_DCN302_H__
+#define __DAL_IRQ_SERVICE_DCN302_H__
+
+#include "../irq_service.h"
+
+struct irq_service *dal_irq_service_dcn302_create(struct irq_service_init_data *init_data);
+
+#endif /* __DAL_IRQ_SERVICE_DCN302_H__ */
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index c6a8d6c54621..ac41ae2d261b 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -88,9 +88,9 @@ enum dmub_asic {
 	DMUB_ASIC_NONE = 0,
 	DMUB_ASIC_DCN20,
 	DMUB_ASIC_DCN21,
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	DMUB_ASIC_DCN30,
-#endif
+	DMUB_ASIC_DCN301,
+	DMUB_ASIC_DCN302,
 	DMUB_ASIC_MAX,
 };
 
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index d103ec1eaa73..81433c22fb51 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x9cf8f05fe
+#define DMUB_FW_VERSION_GIT_HASH 0x9f0af34af
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 35
+#define DMUB_FW_VERSION_REVISION 40
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
@@ -189,7 +189,9 @@ union dmub_fw_boot_options {
 		uint32_t pemu_env : 1;
 		uint32_t fpga_env : 1;
 		uint32_t optimized_init : 1;
-		uint32_t reserved : 29;
+		uint32_t skip_phy_access : 1;
+		uint32_t disable_clk_gate: 1;
+		uint32_t reserved : 27;
 	} bits;
 	uint32_t all;
 };
@@ -272,6 +274,7 @@ enum dmub_gpint_command {
 	 * ARGS: Stream mask, 1 bit per active stream index.
 	 */
 	DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
+	DMUB_GPINT__PSR_RESIDENCY = 9,
 };
 
 //==============================================================================
@@ -298,6 +301,7 @@ enum dmub_cmd_type {
 	DMUB_CMD__REG_REG_WAIT = 4,
 	DMUB_CMD__PLAT_54186_WA = 5,
 	DMUB_CMD__PSR = 64,
+	DMUB_CMD__MALL = 65,
 	DMUB_CMD__ABM = 66,
 	DMUB_CMD__HW_LOCK = 69,
 	DMUB_CMD__DP_AUX_ACCESS = 70,
@@ -425,6 +429,18 @@ struct dmub_rb_cmd_PLAT_54186_wa {
 	struct dmub_cmd_PLAT_54186_wa flip;
 };
 
+struct dmub_rb_cmd_mall {
+	struct dmub_cmd_header header;
+	union dmub_addr cursor_copy_src;
+	union dmub_addr cursor_copy_dst;
+	uint32_t tmr_delay;
+	uint32_t tmr_scale;
+	uint16_t cursor_width;
+	uint16_t cursor_pitch;
+	uint16_t cursor_height;
+	uint8_t cursor_bpp;
+};
+
 struct dmub_cmd_digx_encoder_control_data {
 	union dig_encoder_control_parameters_v1_5 dig;
 };
@@ -477,6 +493,14 @@ enum dp_aux_request_action {
 	DP_AUX_REQ_ACTION_DPCD_READ		= 0x90
 };
 
+enum aux_return_code_type {
+	AUX_RET_SUCCESS = 0,
+	AUX_RET_ERROR_TIMEOUT,
+	AUX_RET_ERROR_NO_DATA,
+	AUX_RET_ERROR_INVALID_OPERATION,
+	AUX_RET_ERROR_PROTOCOL_ERROR,
+};
+
 /* DP AUX command */
 struct aux_transaction_parameters {
 	uint8_t is_i2c_over_aux;
@@ -526,6 +550,17 @@ struct dmub_rb_cmd_dp_aux_reply {
 	struct aux_reply_data reply_data;
 };
 
+/* DP HPD Notify command - OutBox Cmd */
+enum dp_hpd_type {
+	DP_HPD = 0,
+	DP_IRQ
+};
+
+enum dp_hpd_status {
+	DP_HPD_UNPLUG = 0,
+	DP_HPD_PLUG
+};
+
 struct dp_hpd_data {
 	uint8_t phy_port_index;
 	uint8_t hpd_type;
@@ -549,6 +584,7 @@ enum dmub_cmd_psr_type {
 	DMUB_CMD__PSR_ENABLE			= 2,
 	DMUB_CMD__PSR_DISABLE			= 3,
 	DMUB_CMD__PSR_SET_LEVEL			= 4,
+	DMUB_CMD__PSR_FORCE_STATIC		= 5,
 };
 
 enum psr_version {
@@ -556,6 +592,12 @@ enum psr_version {
 	PSR_VERSION_UNSUPPORTED			= 0xFFFFFFFF,
 };
 
+enum dmub_cmd_mall_type {
+	DMUB_CMD__MALL_ACTION_ALLOW = 0,
+	DMUB_CMD__MALL_ACTION_DISALLOW = 1,
+	DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
+};
+
 struct dmub_cmd_psr_copy_settings_data {
 	union dmub_psr_debug_flags debug;
 	uint16_t psr_level;
@@ -603,6 +645,10 @@ struct dmub_rb_cmd_psr_set_version {
 	struct dmub_cmd_psr_set_version_data psr_set_version_data;
 };
 
+struct dmub_rb_cmd_psr_force_static {
+	struct dmub_cmd_header header;
+};
+
 union dmub_hw_lock_flags {
 	struct {
 		uint8_t lock_pipe   : 1;
@@ -760,7 +806,9 @@ union dmub_rb_cmd {
 	struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
 	struct dmub_rb_cmd_psr_enable psr_enable;
 	struct dmub_rb_cmd_psr_set_level psr_set_level;
+	struct dmub_rb_cmd_psr_force_static psr_force_static;
 	struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
+	struct dmub_rb_cmd_mall mall;
 	struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
 	struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
 	struct dmub_rb_cmd_abm_set_level abm_set_level;
diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
index bb584f39cad0..945287164cf2 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile
+++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
@@ -21,9 +21,8 @@
 #
 
 DMUB = dmub_srv.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
-ifdef CONFIG_DRM_AMD_DC_DCN3_0
-DMUB += dmub_dcn30.o
-endif
+DMUB += dmub_dcn30.o dmub_dcn301.o
+DMUB += dmub_dcn302.o
 
 AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
 
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c
new file mode 100644
index 000000000000..197398257692
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "../dmub_srv.h"
+#include "dmub_reg.h"
+#include "dmub_dcn301.h"
+
+#include "dcn/dcn_3_0_1_offset.h"
+#include "dcn/dcn_3_0_1_sh_mask.h"
+#include "vangogh_ip_offset.h"
+
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
+#define CTX dmub
+#define REGS dmub->regs
+
+/* Registers. */
+
+const struct dmub_srv_common_regs dmub_srv_dcn301_regs = {
+#define DMUB_SR(reg) REG_OFFSET(reg),
+	{ DMUB_COMMON_REGS() },
+#undef DMUB_SR
+
+#define DMUB_SF(reg, field) FD_MASK(reg, field),
+	{ DMUB_COMMON_FIELDS() },
+#undef DMUB_SF
+
+#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
+	{ DMUB_COMMON_FIELDS() },
+#undef DMUB_SF
+};
+
+/* Shared functions. */
+
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.h
new file mode 100644
index 000000000000..faafaf300583
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DMUB_DCN301_H_
+#define _DMUB_DCN301_H_
+
+#include "dmub_dcn20.h"
+
+/* Registers. */
+
+extern const struct dmub_srv_common_regs dmub_srv_dcn301_regs;
+
+/* Hardware functions. */
+
+#endif /* _DMUB_DCN301_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c
new file mode 100644
index 000000000000..f5db4437a882
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "../dmub_srv.h"
+#include "dmub_reg.h"
+#include "dmub_dcn302.h"
+
+#include "dimgrey_cavefish_ip_offset.h"
+#include "dcn/dcn_3_0_0_offset.h"
+#include "dcn/dcn_3_0_0_sh_mask.h"
+
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
+#define CTX dmub
+#define REGS dmub->regs
+
+/* Registers. */
+
+const struct dmub_srv_common_regs dmub_srv_dcn302_regs = {
+#define DMUB_SR(reg) REG_OFFSET(reg),
+	{ DMUB_COMMON_REGS() },
+#undef DMUB_SR
+
+#define DMUB_SF(reg, field) FD_MASK(reg, field),
+	{ DMUB_COMMON_FIELDS() },
+#undef DMUB_SF
+
+#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
+	{ DMUB_COMMON_FIELDS() },
+#undef DMUB_SF
+};
+
+/* Shared functions. */
+
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.h
new file mode 100644
index 000000000000..e2102c865d91
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DMUB_DCN302_H_
+#define _DMUB_DCN302_H_
+
+#include "dmub_dcn20.h"
+
+/* Registers. */
+
+extern const struct dmub_srv_common_regs dmub_srv_dcn302_regs;
+
+/* Hardware functions. */
+
+#endif /* _DMUB_DCN302_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 08da423b24a1..d11b96d132ad 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -27,9 +27,9 @@
 #include "dmub_dcn20.h"
 #include "dmub_dcn21.h"
 #include "dmub_cmd.h"
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 #include "dmub_dcn30.h"
-#endif
+#include "dmub_dcn301.h"
+#include "dmub_dcn302.h"
 #include "os_types.h"
 /*
  * Note: the DMUB service is standalone. No additional headers should be
@@ -136,9 +136,9 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 	switch (asic) {
 	case DMUB_ASIC_DCN20:
 	case DMUB_ASIC_DCN21:
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 	case DMUB_ASIC_DCN30:
-#endif
+	case DMUB_ASIC_DCN301:
+	case DMUB_ASIC_DCN302:
 		dmub->regs = &dmub_srv_dcn20_regs;
 
 		funcs->reset = dmub_dcn20_reset;
@@ -160,7 +160,6 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 			funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
 			funcs->is_phy_init = dmub_dcn21_is_phy_init;
 		}
-#ifdef CONFIG_DRM_AMD_DC_DCN3_0
 		if (asic == DMUB_ASIC_DCN30) {
 			dmub->regs = &dmub_srv_dcn30_regs;
 
@@ -168,7 +167,18 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 			funcs->backdoor_load = dmub_dcn30_backdoor_load;
 			funcs->setup_windows = dmub_dcn30_setup_windows;
 		}
-#endif
+		if (asic == DMUB_ASIC_DCN301) {
+			dmub->regs = &dmub_srv_dcn301_regs;
+
+			funcs->backdoor_load = dmub_dcn30_backdoor_load;
+			funcs->setup_windows = dmub_dcn30_setup_windows;
+		}
+		if (asic == DMUB_ASIC_DCN302) {
+			dmub->regs = &dmub_srv_dcn302_regs;
+
+			funcs->backdoor_load = dmub_dcn30_backdoor_load;
+			funcs->setup_windows = dmub_dcn30_setup_windows;
+		}
 		break;
 
 	default:
@@ -404,15 +414,16 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 		cw1.region.base = DMUB_CW1_BASE;
 		cw1.region.top = cw1.region.base + stack_fb->size - 1;
 
-		/**
-		 * Read back all the instruction memory so we don't hang the
-		 * DMCUB when backdoor loading if the write from x86 hasn't been
-		 * flushed yet. This only occurs in backdoor loading.
-		 */
-		dmub_flush_buffer_mem(inst_fb);
+		if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
+		    /**
+		     * Read back all the instruction memory so we don't hang the
+		     * DMCUB when backdoor loading if the write from x86 hasn't been
+		     * flushed yet. This only occurs in backdoor loading.
+		     */
+		    dmub_flush_buffer_mem(inst_fb);
+		    dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
+		}
 
-		if (params->load_inst_const && dmub->hw_funcs.backdoor_load)
-			dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
 	}
 
 	if (dmub->hw_funcs.reset)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index b267987aed06..24346f1d7dd0 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -195,6 +195,7 @@ enum {
 	NV_NAVI12_P_A0      = 10,
 	NV_NAVI14_M_A0      = 20,
 	NV_SIENNA_CICHLID_P_A0      = 40,
+	NV_DIMGREY_CAVEFISH_P_A0      = 60,
 	NV_UNKNOWN          = 0xFF
 };
 
@@ -202,8 +203,23 @@ enum {
 #define ASICREV_IS_NAVI12_P(eChipRev)        ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
 #define ASICREV_IS_NAVI14_M(eChipRev)        ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
 #define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0))
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev)        ((eChipRev >= NV_SIENNA_CICHLID_P_A0))
+#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev)        ((eChipRev >= NV_SIENNA_CICHLID_P_A0) && (eChipRev < NV_DIMGREY_CAVEFISH_P_A0))
+#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev)        ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN))
+#define GREEN_SARDINE_A0 0xA1
+#ifndef ASICREV_IS_GREEN_SARDINE
+#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
+#endif
+#define FAMILY_VGH 144
+#define DEVICE_ID_VGH_163F 0x163F
+#define VANGOGH_A0 0x01
+#define VANGOGH_UNKNOWN 0xFF
+
+#ifndef ASICREV_IS_VANGOGH
+#define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN))
+#endif
+#define GREEN_SARDINE_A0 0xA1
+#ifndef ASICREV_IS_GREEN_SARDINE
+#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
 #endif
 
 /*
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 8aaa3af69202..0d485802a2d0 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -52,6 +52,8 @@ enum dce_version {
 	DCN_VERSION_2_0,
 	DCN_VERSION_2_1,
 	DCN_VERSION_3_0,
+	DCN_VERSION_3_01,
+	DCN_VERSION_3_02,
 	DCN_VERSION_MAX
 };
 
diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 9ad49da50a17..c9be899cd25c 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -33,6 +33,7 @@
 #define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1
 #define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24
 #define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C
+#define DP_BRANCH_DEVICE_ID_006037 0x006037
 
 enum ddc_result {
 	DDC_RESULT_UNKNOWN = 0,
@@ -122,5 +123,6 @@ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
 /*DP to Dual link DVI converter*/
 static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
+static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
 
 #endif /* __DAL_DDC_SERVICE_TYPES_H__ */
diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
index 3d29646c7cb4..aec7389aff37 100644
--- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h
+++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
@@ -156,5 +156,6 @@ enum dpcd_psr_sink_states {
 #define DP_SOURCE_BACKLIGHT_CURRENT_PEAK    0x326
 #define DP_SOURCE_BACKLIGHT_CONTROL	    0x32E
 #define DP_SOURCE_BACKLIGHT_ENABLE	    0x32F
+#define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED	0x340
 
 #endif /* __DAL_DPCD_DEFS_H__ */
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
index 7a06e3914c00..792652236c61 100644
--- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
@@ -284,6 +284,16 @@ struct ext_hdmi_settings {
 	struct i2c_reg_info      reg_settings_6g[3];
 };
 
+struct edp_info {
+	uint16_t edp_backlight_pwm_hz;
+	uint16_t edp_ss_percentage;
+	uint16_t edp_ss_rate_10hz;
+	uint8_t  edp_pwr_on_off_delay;
+	uint8_t  edp_pwr_on_vary_bl_to_blon;
+	uint8_t  edp_pwr_down_bloff_to_vary_bloff;
+	uint8_t  edp_panel_bpc;
+	uint8_t  edp_bootup_bl_level;
+};
 
 /* V6 */
 struct integrated_info {
@@ -403,6 +413,9 @@ struct integrated_info {
 	struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3];
 	/* V11 */
 	uint32_t dp_ss_control;
+	/* V2.1 */
+	struct edp_info edp1_info;
+	struct edp_info edp2_info;
 };
 
 /**
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index b8695660b480..eced40a2fce4 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -151,7 +151,7 @@ static void compute_de_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
 	div = dc_fixpt_sub(c2, dc_fixpt_mul(c3, l_pow_m1));
 
 	base2 = dc_fixpt_div(base, div);
-	//avoid complex numbers
+	// avoid complex numbers
 	if (dc_fixpt_lt(base2, dc_fixpt_zero))
 		base2 = dc_fixpt_sub(dc_fixpt_zero, base2);
 
@@ -161,7 +161,7 @@ static void compute_de_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
 }
 
 
-/*de gamma, none linear to linear*/
+/* de gamma, non-linear to linear */
 static void compute_hlg_eotf(struct fixed31_32 in_x,
 		struct fixed31_32 *out_y,
 		uint32_t sdr_white_level, uint32_t max_luminance_nits)
@@ -193,7 +193,7 @@ static void compute_hlg_eotf(struct fixed31_32 in_x,
 
 }
 
-/*re gamma, linear to none linear*/
+/* re gamma, linear to non-linear */
 static void compute_hlg_oetf(struct fixed31_32 in_x, struct fixed31_32 *out_y,
 		uint32_t sdr_white_level, uint32_t max_luminance_nits)
 {
@@ -830,7 +830,7 @@ static bool build_regamma(struct pwl_float_data_ex *rgb_regamma,
 
 	i = 0;
 	while (i <= hw_points_num) {
-		/*TODO use y vs r,g,b*/
+		/* TODO use y vs r,g,b */
 		rgb->r = translate_from_linear_space_ex(
 			coord_x->x, coeff, 0, cal_buffer);
 		rgb->g = rgb->r;
@@ -937,6 +937,7 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
 	uint32_t i;
 	struct pwl_float_data_ex *rgb = rgb_regamma;
 	const struct hw_x_point *coord_x = coordinate_x;
+	const struct hw_x_point *prv_coord_x = coord_x;
 	struct fixed31_32 scaledX = dc_fixpt_zero;
 	struct fixed31_32 scaledX1 = dc_fixpt_zero;
 	struct fixed31_32 max_display;
@@ -947,6 +948,9 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
 	bool use_eetf = false;
 	bool is_clipped = false;
 	struct fixed31_32 sdr_white_level;
+	struct fixed31_32 coordX_diff;
+	struct fixed31_32 out_dist_max;
+	struct fixed31_32 bright_norm;
 
 	if (fs_params->max_content == 0 ||
 			fs_params->max_display == 0)
@@ -975,7 +979,7 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
 	for (i = 32; i <= hw_points_num; i++) {
 		if (!is_clipped) {
 			if (use_eetf) {
-				/*max content is equal 1 */
+				/* max content is equal 1 */
 				scaledX1 = dc_fixpt_div(coord_x->x,
 						dc_fixpt_div(max_content, sdr_white_level));
 				hermite_spline_eetf(scaledX1, max_display, min_display,
@@ -990,21 +994,65 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
 				else
 					output = calculate_gamma22(scaledX, use_eetf, cal_buffer);
 
+				// Ensure output respects reasonable boundaries
+				output = dc_fixpt_clamp(output, dc_fixpt_zero, dc_fixpt_one);
+
 				rgb->r = output;
 				rgb->g = output;
 				rgb->b = output;
 			} else {
+				/* Here clipping happens for the first time */
 				is_clipped = true;
-				rgb->r = clip;
-				rgb->g = clip;
-				rgb->b = clip;
+
+				/* The next few lines implement the equation
+				 * output = prev_out +
+				 * (coord_x->x - prev_coord_x->x) *
+				 * (1.0 - prev_out) /
+				 * (maxDisp/sdr_white_level - prevCoordX)
+				 *
+				 * This equation interpolates the first point
+				 * after max_display/80 so that the slope from
+				 * hw_x_before_max and hw_x_after_max is such
+				 * that we hit Y=1.0 at max_display/80.
+				 */
+
+				coordX_diff = dc_fixpt_sub(coord_x->x, prv_coord_x->x);
+				out_dist_max = dc_fixpt_sub(dc_fixpt_one, output);
+				bright_norm = dc_fixpt_div(max_display, sdr_white_level);
+
+				output = dc_fixpt_add(
+					output, dc_fixpt_mul(
+						coordX_diff, dc_fixpt_div(
+							out_dist_max,
+							dc_fixpt_sub(bright_norm, prv_coord_x->x)
+						)
+					)
+				);
+
+				/* Relaxing the maximum boundary to 1.07 (instead of 1.0)
+				 * because the last point in the curve must be such that
+				 * the maximum display pixel brightness interpolates to
+				 * exactly 1.0. The worst case scenario was calculated
+				 * around 1.057, so the limit of 1.07 leaves some safety
+				 * margin.
+				 */
+				output = dc_fixpt_clamp(output, dc_fixpt_zero,
+					dc_fixpt_from_fraction(107, 100));
+
+				rgb->r = output;
+				rgb->g = output;
+				rgb->b = output;
 			}
 		} else {
+			/* Every other clipping after the first
+			 * one is dealt with here
+			 */
 			rgb->r = clip;
 			rgb->g = clip;
 			rgb->b = clip;
 		}
 
+		prv_coord_x = coord_x;
 		++coord_x;
 		++rgb;
 	}
@@ -1073,7 +1121,7 @@ static void build_hlg_degamma(struct pwl_float_data_ex *degamma,
 	const struct hw_x_point *coord_x = coordinate_x;
 
 	i = 0;
-	//check when i == 434
+	// check when i == 434
 	while (i != hw_points_num + 1) {
 		compute_hlg_eotf(coord_x->x, &rgb->r, sdr_white_level, max_luminance_nits);
 		rgb->g = rgb->r;
@@ -1097,7 +1145,7 @@ static void build_hlg_regamma(struct pwl_float_data_ex *regamma,
 
 	i = 0;
 
-	//when i == 471
+	// when i == 471
 	while (i != hw_points_num + 1) {
 		compute_hlg_oetf(coord_x->x, &rgb->r, sdr_white_level, max_luminance_nits);
 		rgb->g = rgb->r;
@@ -1331,6 +1379,8 @@ static void apply_lut_1d(
 	struct fixed31_32 lut1;
 	struct fixed31_32 lut2;
 	const int max_lut_index = 4095;
+	const struct fixed31_32 penult_lut_index_f =
+			dc_fixpt_from_int(max_lut_index-1);
 	const struct fixed31_32 max_lut_index_f =
 			dc_fixpt_from_int(max_lut_index);
 	int32_t index = 0, index_next = 0;
@@ -1355,10 +1405,21 @@ static void apply_lut_1d(
 			index = dc_fixpt_floor(norm_y);
 			index_f = dc_fixpt_from_int(index);
 
-			if (index < 0 || index > max_lut_index)
+			if (index < 0)
 				continue;
 
-			index_next = (index == max_lut_index) ? index : index+1;
+			if (index <= max_lut_index)
+				index_next = (index == max_lut_index) ? index : index+1;
+			else {
+				/* Here we are dealing with the last point in the curve,
+				 * which in some cases might exceed the range given by
+				 * max_lut_index. So we interpolate the value using
+				 * max_lut_index and max_lut_index - 1.
+				 */
+				index = max_lut_index - 1;
+				index_next = max_lut_index;
+				index_f = penult_lut_index_f;
+			}
 
 			if (color == 0) {
 				lut1 = ramp->entries.red[index];
@@ -1586,9 +1647,7 @@ static void build_new_custom_resulted_curve(
 	uint32_t hw_points_num,
 	struct dc_transfer_func_distributed_points *tf_pts)
 {
-	uint32_t i;
-
-	i = 0;
+	uint32_t i = 0;
 
 	while (i != hw_points_num + 1) {
 		tf_pts->red[i] = dc_fixpt_clamp(
@@ -1614,7 +1673,7 @@ static void apply_degamma_for_user_regamma(struct pwl_float_data_ex *rgb_regamma
 	struct pwl_float_data_ex *rgb = rgb_regamma;
 	const struct hw_x_point *coord_x = coordinates_x;
 
-	build_coefficients(&coeff, true);
+	build_coefficients(&coeff, TRANSFER_FUNCTION_SRGB);
 
 	i = 0;
 	while (i != hw_points_num + 1) {
@@ -1637,7 +1696,8 @@ static bool map_regamma_hw_to_x_user(
 	const struct pwl_float_data_ex *rgb_regamma,
 	uint32_t hw_points_num,
 	struct dc_transfer_func_distributed_points *tf_pts,
-	bool mapUserRamp)
+	bool mapUserRamp,
+	bool doClamping)
 {
 	/* setup to spare calculated ideal regamma values */
 
@@ -1665,8 +1725,10 @@ static bool map_regamma_hw_to_x_user(
 		}
 	}
 
-	/* this should be named differently, all it does is clamp to 0-1 */
-	build_new_custom_resulted_curve(hw_points_num, tf_pts);
+	if (doClamping) {
+		/* this should be named differently, all it does is clamp to 0-1 */
+		build_new_custom_resulted_curve(hw_points_num, tf_pts);
+	}
 
 	return true;
 }
@@ -1675,7 +1737,8 @@ static bool map_regamma_hw_to_x_user(
 
 bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,
 		const struct regamma_lut *regamma,
-		struct calculate_buffer *cal_buffer)
+		struct calculate_buffer *cal_buffer,
+		const struct dc_gamma *ramp)
 {
 	struct gamma_coefficients coeff;
 	const struct hw_x_point *coord_x = coordinates_x;
@@ -1716,6 +1779,9 @@ bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,
 		++i;
 	}
 
+	if (ramp && ramp->type == GAMMA_CS_TFM_1D)
+		apply_lut_1d(ramp, MAX_HW_POINTS, &output_tf->tf_pts);
+
 	// this function just clamps output to 0-1
 	build_new_custom_resulted_curve(MAX_HW_POINTS, &output_tf->tf_pts);
 	output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
@@ -1725,7 +1791,8 @@ bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,
 
 bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf,
 		const struct regamma_lut *regamma,
-		struct calculate_buffer *cal_buffer)
+		struct calculate_buffer *cal_buffer,
+		const struct dc_gamma *ramp)
 {
 	struct dc_transfer_func_distributed_points *tf_pts = &output_tf->tf_pts;
 	struct dividers dividers;
@@ -1772,6 +1839,9 @@ bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf,
 	tf_pts->x_point_at_y1_green = 1;
 	tf_pts->x_point_at_y1_blue = 1;
 
+	if (ramp && ramp->type == GAMMA_CS_TFM_1D)
+		apply_lut_1d(ramp, MAX_HW_POINTS, &output_tf->tf_pts);
+
 	// this function just clamps output to 0-1
 	build_new_custom_resulted_curve(MAX_HW_POINTS, tf_pts);
 
@@ -1914,11 +1984,12 @@ bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps,
 			++i;
 		}
 	} else {
-		//clamps to 0-1
+		// clamps to 0-1
 		map_regamma_hw_to_x_user(ramp, coeff, rgb_user,
 				coordinates_x, axis_x, curve,
 				MAX_HW_POINTS, tf_pts,
-				mapUserRamp && ramp && ramp->type == GAMMA_RGB_256);
+				mapUserRamp && ramp && ramp->type == GAMMA_RGB_256,
+				true);
 	}
 
 
@@ -2034,6 +2105,7 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
 	struct gamma_pixel *axis_x = NULL;
 	struct pixel_gamma_point *coeff = NULL;
 	enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
+	bool doClamping = true;
 	bool ret = false;
 
 	if (output_tf->type == TF_TYPE_BYPASS)
@@ -2100,11 +2172,15 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
 			cal_buffer);
 
 	if (ret) {
+		doClamping = !(output_tf->tf == TRANSFER_FUNCTION_GAMMA22 &&
+			fs_params != NULL && fs_params->skip_tm == 0);
+
 		map_regamma_hw_to_x_user(ramp, coeff, rgb_user,
 				coordinates_x, axis_x, rgb_regamma,
 				MAX_HW_POINTS, tf_pts,
 				(mapUserRamp || (ramp && ramp->type != GAMMA_RGB_256)) &&
-				(ramp && ramp->type != GAMMA_CS_TFM_1D));
+				(ramp && ramp->type != GAMMA_CS_TFM_1D),
+				doClamping);
 
 		if (ramp && ramp->type == GAMMA_CS_TFM_1D)
 			apply_lut_1d(ramp, MAX_HW_POINTS, tf_pts);
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
index 37ffbef6602b..7563457e2ff4 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
@@ -120,11 +120,13 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
 
 bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,
 		const struct regamma_lut *regamma,
-		struct calculate_buffer *cal_buffer);
+		struct calculate_buffer *cal_buffer,
+		const struct dc_gamma *ramp);
 
 bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf,
 		const struct regamma_lut *regamma,
-		struct calculate_buffer *cal_buffer);
+		struct calculate_buffer *cal_buffer,
+		const struct dc_gamma *ramp);
 
 
 #endif /* COLOR_MOD_COLOR_GAMMA_H_ */
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index d988533d4af5..52c3cb6b439a 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -41,11 +41,11 @@
 #define BTR_MAX_MARGIN 2500
 /* Threshold to change BTR multiplier (to avoid frequent changes) */
 #define BTR_DRIFT_MARGIN 2000
-/*Threshold to exit fixed refresh rate*/
-#define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 4
-/* Number of consecutive frames to check before entering/exiting fixed refresh*/
+/* Threshold to exit fixed refresh rate */
+#define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 1
+/* Number of consecutive frames to check before entering/exiting fixed refresh */
 #define FIXED_REFRESH_ENTER_FRAME_COUNT 5
-#define FIXED_REFRESH_EXIT_FRAME_COUNT 5
+#define FIXED_REFRESH_EXIT_FRAME_COUNT 10
 
 struct core_freesync {
 	struct mod_freesync public;
@@ -85,7 +85,7 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync)
 	kfree(core_freesync);
 }
 
-#if 0 /* unused currently */
+#if 0 /* Unused currently */
 static unsigned int calc_refresh_in_uhz_from_duration(
 		unsigned int duration_in_ns)
 {
@@ -184,7 +184,7 @@ static void update_v_total_for_static_ramp(
 	bool ramp_direction_is_up = (current_duration_in_us >
 				target_duration_in_us) ? true : false;
 
-	/* Calc ratio between new and current frame duration with 3 digit */
+	/* Calculate ratio between new and current frame duration with 3 digit */
 	unsigned int frame_duration_ratio = div64_u64(1000000,
 		(1000 +  div64_u64(((unsigned long long)(
 		STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) *
@@ -204,10 +204,10 @@ static void update_v_total_for_static_ramp(
 
 	/* Going to a higher refresh rate (lower frame duration) */
 	if (ramp_direction_is_up) {
-		/* reduce frame duration */
+		/* Reduce frame duration */
 		current_duration_in_us -= ramp_rate_interpolated;
 
-		/* adjust for frame duration below min */
+		/* Adjust for frame duration below min */
 		if (current_duration_in_us <= target_duration_in_us) {
 			in_out_vrr->fixed.ramping_active = false;
 			in_out_vrr->fixed.ramping_done = true;
@@ -217,10 +217,10 @@ static void update_v_total_for_static_ramp(
 		}
 	/* Going to a lower refresh rate (larger frame duration) */
 	} else {
-		/* increase frame duration */
+		/* Increase frame duration */
 		current_duration_in_us += ramp_rate_interpolated;
 
-		/* adjust for frame duration above max */
+		/* Adjust for frame duration above max */
 		if (current_duration_in_us >= target_duration_in_us) {
 			in_out_vrr->fixed.ramping_active = false;
 			in_out_vrr->fixed.ramping_done = true;
@@ -289,7 +289,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
 	} else {
 
 		/* Calculate number of midPoint frames that could fit within
-		 * the render time interval- take ceil of this value
+		 * the render time interval - take ceil of this value
 		 */
 		mid_point_frames_ceil = (last_render_time_in_us +
 				in_out_vrr->btr.mid_point_in_us - 1) /
@@ -306,7 +306,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
 		}
 
 		/* Calculate number of midPoint frames that could fit within
-		 * the render time interval- take floor of this value
+		 * the render time interval - take floor of this value
 		 */
 		mid_point_frames_floor = last_render_time_in_us /
 				in_out_vrr->btr.mid_point_in_us;
@@ -420,7 +420,8 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync,
 				in_out_vrr->fixed.target_refresh_in_uhz = 0;
 				update = true;
 			}
-		}
+		} else
+			in_out_vrr->fixed.frame_counter = 0;
 	} else if (last_render_time_in_us > max_render_time_in_us) {
 		/* Enter Fixed Refresh mode */
 		if (!in_out_vrr->fixed.fixed_active) {
@@ -434,7 +435,8 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync,
 						in_out_vrr->max_refresh_in_uhz;
 				update = true;
 			}
-		}
+		} else
+			in_out_vrr->fixed.frame_counter = 0;
 	}
 
 	if (update) {
@@ -559,7 +561,7 @@ static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
 	 */
 	infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
 
-	//FreeSync HDR
+	/* FreeSync HDR */
 	infopacket->sb[9] = 0;
 	infopacket->sb[10] = 0;
 }
@@ -897,15 +899,15 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
 	min_refresh_in_uhz = in_config->min_refresh_in_uhz;
 	max_refresh_in_uhz = in_config->max_refresh_in_uhz;
 
-	// Full range may be larger than current video timing, so cap at nominal
+	/* Full range may be larger than current video timing, so cap at nominal */
 	if (max_refresh_in_uhz > nominal_field_rate_in_uhz)
 		max_refresh_in_uhz = nominal_field_rate_in_uhz;
 
-	// Full range may be larger than current video timing, so cap at nominal
+	/* Full range may be larger than current video timing, so cap at nominal */
 	if (min_refresh_in_uhz > max_refresh_in_uhz)
 		min_refresh_in_uhz = max_refresh_in_uhz;
 
-	// If a monitor reports exactly max refresh of 2x of min, enforce it on nominal
+	/* If a monitor reports exactly max refresh of 2x of min, enforce it on nominal */
 	rounded_nominal_in_uhz =
 			div_u64(nominal_field_rate_in_uhz + 50000, 100000) * 100000;
 	if (in_config->max_refresh_in_uhz == (2 * in_config->min_refresh_in_uhz) &&
@@ -1042,7 +1044,7 @@ void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
 		last_render_time_in_us = curr_time_stamp_in_us -
 				plane->time.prev_update_time_in_us;
 
-		// Sum off all entries except oldest one
+		/* Sum off all entries except oldest one */
 		for (i = 0; i < DC_PLANE_UPDATE_TIMES_MAX; i++) {
 			average_render_time_in_us +=
 					plane->time.time_elapsed_in_us[i];
@@ -1050,7 +1052,7 @@ void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
 		average_render_time_in_us -=
 				plane->time.time_elapsed_in_us[oldest_index];
 
-		// Add render time for current flip
+		/* Add render time for current flip */
 		average_render_time_in_us += last_render_time_in_us;
 		average_render_time_in_us /= DC_PLANE_UPDATE_TIMES_MAX;
 
@@ -1125,8 +1127,9 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
 	if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE)
 		in_out_vrr->fixed.ramping_active = false;
 
-	/* Gradual Static Screen Ramping Logic */
-	/* Execute if ramp is active and user enabled freesync static screen*/
+	/* Gradual Static Screen Ramping Logic
+	 * Execute if ramp is active and user enabled freesync static screen
+	 */
 	if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED &&
 				in_out_vrr->fixed.ramping_active) {
 		update_v_total_for_static_ramp(
@@ -1214,20 +1217,20 @@ bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz,
 	min_refresh_cap_in_uhz /= 1000000;
 	max_refresh_cap_in_uhz /= 1000000;
 
-	// Check nominal is within range
+	/* Check nominal is within range */
 	if (nominal_field_rate_in_uhz > max_refresh_cap_in_uhz ||
 		nominal_field_rate_in_uhz < min_refresh_cap_in_uhz)
 		return false;
 
-	// If nominal is less than max, limit the max allowed refresh rate
+	/* If nominal is less than max, limit the max allowed refresh rate */
 	if (nominal_field_rate_in_uhz < max_refresh_cap_in_uhz)
 		max_refresh_cap_in_uhz = nominal_field_rate_in_uhz;
 
-	// Check min is within range
+	/* Check min is within range */
 	if (min_refresh_cap_in_uhz > max_refresh_cap_in_uhz)
 		return false;
 
-	// For variable range, check for at least 10 Hz range
+	/* For variable range, check for at least 10 Hz range */
 	if (nominal_field_rate_in_uhz - min_refresh_cap_in_uhz < 10)
 		return false;
 
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
index f3711914364e..24ab95b093f7 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_transition.c
@@ -231,7 +231,7 @@ enum mod_hdcp_status mod_hdcp_hdcp1_dp_transition(struct mod_hdcp *hdcp,
 			fail_and_restart_in_ms(0, &status, output);
 			break;
 		} else if (conn->hdcp1_retry_count < conn->link.adjust.hdcp1.min_auth_retries_wa) {
-			fail_and_restart_in_ms(0, &status, output);
+			fail_and_restart_in_ms(200, &status, output);
 			break;
 		}
 		if (conn->is_repeater) {
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
index fb6a19d020f9..ee5230ccf3c4 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
@@ -280,6 +280,6 @@ char *mod_hdcp_state_id_to_str(int32_t id)
 		return "D2_A9_VALIDATE_STREAM_READY";
 	default:
 		return "UNKNOWN_STATE_ID";
-	};
+	}
 }
 
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 61497954e67e..cc983f662157 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -665,7 +665,7 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
 	bool result = false;
 	uint32_t i, j = 0;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#if defined(CONFIG_DRM_AMD_DC_DCN)
 	if (res_pool->abm == NULL && res_pool->multiple_abms[0] == NULL)
 		return false;
 #else
@@ -712,11 +712,11 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
 
 	config.min_abm_backlight = ram_table.min_abm_backlight;
 
-#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
-	if (res_pool->multiple_abms[0]) {
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	if (res_pool->multiple_abms[0])
 		result = res_pool->multiple_abms[0]->funcs->init_abm_config(
 			res_pool->multiple_abms[0], (char *)(&config), sizeof(struct abm_config_table));
-	} else
+	else
 #endif
 		result = res_pool->abm->funcs->init_abm_config(
 			res_pool->abm, (char *)(&config), sizeof(struct abm_config_table));
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 10dc481ecbc4..9676016a37ce 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -45,6 +45,8 @@ enum amd_apu_flags {
 	AMD_APU_IS_RAVEN2 = 0x00000002UL,
 	AMD_APU_IS_PICASSO = 0x00000004UL,
 	AMD_APU_IS_RENOIR = 0x00000008UL,
+	AMD_APU_IS_GREEN_SARDINE = 0x00000010UL,
+	AMD_APU_IS_VANGOGH = 0x00000020UL,
 };
 
 /**
@@ -142,6 +144,7 @@ enum amd_powergating_state {
 #define AMD_CG_SUPPORT_ATHUB_LS			(1 << 28)
 #define AMD_CG_SUPPORT_ATHUB_MGCG		(1 << 29)
 #define AMD_CG_SUPPORT_JPEG_MGCG		(1 << 30)
+#define AMD_CG_SUPPORT_GFX_FGCG			(1 << 31)
 /* PG flags */
 #define AMD_PG_SUPPORT_GFX_PG			(1 << 0)
 #define AMD_PG_SUPPORT_GFX_SMG			(1 << 1)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_offset.h
new file mode 100644
index 000000000000..b99b69b014da
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_offset.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_11_5_0_OFFSET_HEADER
+#define _clk_11_5_0_OFFSET_HEADER
+
+
+// addressBlock: clk_clk1_0_SmuClkDec
+// base address: 0x5c000
+#define mmCLK1_0_CLK1_CLK_PLL_REQ                                                                      0x0410
+#define mmCLK1_0_CLK1_CLK_PLL_REQ_BASE_IDX                                                             0
+#define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL                                                                 0x044a
+#define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL                                                                 0x0454
+#define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL                                                                 0x045e
+#define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK3_DS_CNTL                                                                     0x0461
+#define mmCLK1_0_CLK1_CLK3_DS_CNTL_BASE_IDX                                                            0
+#define mmCLK1_0_CLK1_CLK3_ALLOW_DS                                                                    0x0462
+#define mmCLK1_0_CLK1_CLK3_ALLOW_DS_BASE_IDX                                                           0
+#define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL                                                                 0x0468
+#define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK0_CURRENT_CNT                                                                 0x04a7
+#define mmCLK1_0_CLK1_CLK0_CURRENT_CNT_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK1_CURRENT_CNT                                                                 0x04a8
+#define mmCLK1_0_CLK1_CLK1_CURRENT_CNT_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK2_CURRENT_CNT                                                                 0x04a9
+#define mmCLK1_0_CLK1_CLK2_CURRENT_CNT_BASE_IDX                                                        0
+#define mmCLK1_0_CLK1_CLK3_CURRENT_CNT                                                                 0x04aa
+#define mmCLK1_0_CLK1_CLK3_CURRENT_CNT_BASE_IDX                                                        0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_sh_mask.h
new file mode 100644
index 000000000000..a7c1af165104
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_sh_mask.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_11_5_0_SH_MASK_HEADER
+#define _clk_11_5_0_SH_MASK_HEADER
+
+
+// addressBlock: clk_clk1_0_SmuClkDec
+//CLK1_0_CLK1_CLK_PLL_REQ
+#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                            0x0
+#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                           0x10
+#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                              0x000001FFL
+#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                             0xFFFF0000L
+//CLK1_0_CLK1_CLK0_BYPASS_CNTL
+#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                  0x0
+#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT                                                  0x10
+#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                    0x00000007L
+#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK                                                    0x000F0000L
+//CLK1_0_CLK1_CLK1_BYPASS_CNTL
+#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                  0x0
+#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT                                                  0x10
+#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                    0x00000007L
+#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK                                                    0x000F0000L
+//CLK1_0_CLK1_CLK2_BYPASS_CNTL
+#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                  0x0
+#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT                                                  0x10
+#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                    0x00000007L
+#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK                                                    0x000F0000L
+//CLK1_0_CLK1_CLK3_DS_CNTL
+#define CLK1_0_CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                       0x0
+#define CLK1_0_CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                         0x00000007L
+//CLK1_0_CLK1_CLK3_ALLOW_DS
+#define CLK1_0_CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT                                                       0x0
+#define CLK1_0_CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK                                                         0x00000001L
+//CLK1_0_CLK1_CLK3_BYPASS_CNTL
+#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                  0x0
+#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT                                                  0x10
+#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                    0x00000007L
+#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK                                                    0x000F0000L
+//CLK1_0_CLK1_CLK0_CURRENT_CNT
+#define CLK1_0_CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
+#define CLK1_0_CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
+//CLK1_0_CLK1_CLK1_CURRENT_CNT
+#define CLK1_0_CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
+#define CLK1_0_CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
+//CLK1_0_CLK1_CLK2_CURRENT_CNT
+#define CLK1_0_CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
+#define CLK1_0_CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
+//CLK1_0_CLK1_CLK3_CURRENT_CNT
+#define CLK1_0_CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
+#define CLK1_0_CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h
new file mode 100644
index 000000000000..52caba1b8cb5
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h
@@ -0,0 +1,13271 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_0_1_OFFSET_HEADER
+#define _dcn_3_0_1_OFFSET_HEADER
+
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
+// base address: 0x48
+#define mmVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
+#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
+#define mmVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
+#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
+// base address: 0x3b4
+#define mmCRTC8_IDX                                                                                    0x002d
+#define mmCRTC8_IDX_BASE_IDX                                                                           1
+#define mmCRTC8_DATA                                                                                   0x002d
+#define mmCRTC8_DATA_BASE_IDX                                                                          1
+#define mmGENFC_WT                                                                                     0x002e
+#define mmGENFC_WT_BASE_IDX                                                                            1
+#define mmGENS1                                                                                        0x002e
+#define mmGENS1_BASE_IDX                                                                               1
+#define mmATTRDW                                                                                       0x0030
+#define mmATTRDW_BASE_IDX                                                                              1
+#define mmATTRX                                                                                        0x0030
+#define mmATTRX_BASE_IDX                                                                               1
+#define mmATTRDR                                                                                       0x0030
+#define mmATTRDR_BASE_IDX                                                                              1
+#define mmGENMO_WT                                                                                     0x0030
+#define mmGENMO_WT_BASE_IDX                                                                            1
+#define mmGENS0                                                                                        0x0030
+#define mmGENS0_BASE_IDX                                                                               1
+#define mmGENENB                                                                                       0x0030
+#define mmGENENB_BASE_IDX                                                                              1
+#define mmSEQ8_IDX                                                                                     0x0031
+#define mmSEQ8_IDX_BASE_IDX                                                                            1
+#define mmSEQ8_DATA                                                                                    0x0031
+#define mmSEQ8_DATA_BASE_IDX                                                                           1
+#define mmDAC_MASK                                                                                     0x0031
+#define mmDAC_MASK_BASE_IDX                                                                            1
+#define mmDAC_R_INDEX                                                                                  0x0031
+#define mmDAC_R_INDEX_BASE_IDX                                                                         1
+#define mmDAC_W_INDEX                                                                                  0x0032
+#define mmDAC_W_INDEX_BASE_IDX                                                                         1
+#define mmDAC_DATA                                                                                     0x0032
+#define mmDAC_DATA_BASE_IDX                                                                            1
+#define mmGENFC_RD                                                                                     0x0032
+#define mmGENFC_RD_BASE_IDX                                                                            1
+#define mmGENMO_RD                                                                                     0x0033
+#define mmGENMO_RD_BASE_IDX                                                                            1
+#define mmGRPH8_IDX                                                                                    0x0033
+#define mmGRPH8_IDX_BASE_IDX                                                                           1
+#define mmGRPH8_DATA                                                                                   0x0033
+#define mmGRPH8_DATA_BASE_IDX                                                                          1
+#define mmCRTC8_IDX_1                                                                                  0x0035
+#define mmCRTC8_IDX_1_BASE_IDX                                                                         1
+#define mmCRTC8_DATA_1                                                                                 0x0035
+#define mmCRTC8_DATA_1_BASE_IDX                                                                        1
+#define mmGENFC_WT_1                                                                                   0x0036
+#define mmGENFC_WT_1_BASE_IDX                                                                          1
+#define mmGENS1_1                                                                                      0x0036
+#define mmGENS1_1_BASE_IDX                                                                             1
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+// base address: 0x0
+#define mmCORB_WRITE_POINTER                                                                           0x0000
+#define mmCORB_WRITE_POINTER_BASE_IDX                                                                  0
+#define mmCORB_READ_POINTER                                                                            0x0000
+#define mmCORB_READ_POINTER_BASE_IDX                                                                   0
+#define mmCORB_CONTROL                                                                                 0x0001
+#define mmCORB_CONTROL_BASE_IDX                                                                        0
+#define mmCORB_STATUS                                                                                  0x0001
+#define mmCORB_STATUS_BASE_IDX                                                                         0
+#define mmCORB_SIZE                                                                                    0x0001
+#define mmCORB_SIZE_BASE_IDX                                                                           0
+#define mmRIRB_LOWER_BASE_ADDRESS                                                                      0x0002
+#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX                                                             0
+#define mmRIRB_UPPER_BASE_ADDRESS                                                                      0x0003
+#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX                                                             0
+#define mmRIRB_WRITE_POINTER                                                                           0x0004
+#define mmRIRB_WRITE_POINTER_BASE_IDX                                                                  0
+#define mmRESPONSE_INTERRUPT_COUNT                                                                     0x0004
+#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX                                                            0
+#define mmRIRB_CONTROL                                                                                 0x0005
+#define mmRIRB_CONTROL_BASE_IDX                                                                        0
+#define mmRIRB_STATUS                                                                                  0x0005
+#define mmRIRB_STATUS_BASE_IDX                                                                         0
+#define mmRIRB_SIZE                                                                                    0x0005
+#define mmRIRB_SIZE_BASE_IDX                                                                           0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE                                                           0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                                  0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                                      0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                             0
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                                     0x0006
+#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                            0
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE                                                           0x0007
+#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                                  0
+#define mmIMMEDIATE_COMMAND_STATUS                                                                     0x0008
+#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX                                                            0
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS                                                              0x000a
+#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                                     0
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS                                                              0x000b
+#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                                     0
+#define mmWALL_CLOCK_COUNTER_ALIAS                                                                     0x074c
+#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                                            1
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+// base address: 0x0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                           0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                                  0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                          0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                                 0
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+// base address: 0x0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                                            0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                                   0
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                                           0x0006
+#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                                  0
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+// base address: 0x0
+#define mmVGA_RENDER_CONTROL                                                                           0x0000
+#define mmVGA_RENDER_CONTROL_BASE_IDX                                                                  1
+#define mmVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
+#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
+#define mmVGA_MODE_CONTROL                                                                             0x0002
+#define mmVGA_MODE_CONTROL_BASE_IDX                                                                    1
+#define mmVGA_SURFACE_PITCH_SELECT                                                                     0x0003
+#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
+#define mmVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
+#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
+#define mmVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
+#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
+#define mmVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
+#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
+#define mmVGA_HDP_CONTROL                                                                              0x000a
+#define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1
+#define mmVGA_CACHE_CONTROL                                                                            0x000b
+#define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1
+#define mmD1VGA_CONTROL                                                                                0x000c
+#define mmD1VGA_CONTROL_BASE_IDX                                                                       1
+#define mmD2VGA_CONTROL                                                                                0x000e
+#define mmD2VGA_CONTROL_BASE_IDX                                                                       1
+#define mmVGA_STATUS                                                                                   0x0010
+#define mmVGA_STATUS_BASE_IDX                                                                          1
+#define mmVGA_INTERRUPT_CONTROL                                                                        0x0011
+#define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
+#define mmVGA_STATUS_CLEAR                                                                             0x0012
+#define mmVGA_STATUS_CLEAR_BASE_IDX                                                                    1
+#define mmVGA_INTERRUPT_STATUS                                                                         0x0013
+#define mmVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
+#define mmVGA_MAIN_CONTROL                                                                             0x0014
+#define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1
+#define mmVGA_TEST_CONTROL                                                                             0x0015
+#define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1
+#define mmVGA_QOS_CTRL                                                                                 0x0018
+#define mmVGA_QOS_CTRL_BASE_IDX                                                                        1
+#define mmD3VGA_CONTROL                                                                                0x0038
+#define mmD3VGA_CONTROL_BASE_IDX                                                                       1
+#define mmD4VGA_CONTROL                                                                                0x0039
+#define mmD4VGA_CONTROL_BASE_IDX                                                                       1
+#define mmD5VGA_CONTROL                                                                                0x003a
+#define mmD5VGA_CONTROL_BASE_IDX                                                                       1
+#define mmD6VGA_CONTROL                                                                                0x003b
+#define mmD6VGA_CONTROL_BASE_IDX                                                                       1
+#define mmVGA_SOURCE_SELECT                                                                            0x003c
+#define mmVGA_SOURCE_SELECT_BASE_IDX                                                                   1
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+// base address: 0x0
+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define mmDP_DTO_DBUF_EN                                                                               0x0044
+#define mmDP_DTO_DBUF_EN_BASE_IDX                                                                      1
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
+#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
+#define mmREFCLK_CNTL                                                                                  0x0049
+#define mmREFCLK_CNTL_BASE_IDX                                                                         1
+#define mmREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
+#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define mmDCCG_PERFMON_CNTL2                                                                           0x004e
+#define mmDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1
+#define mmDCCG_DS_DTO_INCR                                                                             0x0053
+#define mmDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
+#define mmDCCG_DS_DTO_MODULO                                                                           0x0054
+#define mmDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
+#define mmDCCG_DS_CNTL                                                                                 0x0055
+#define mmDCCG_DS_CNTL_BASE_IDX                                                                        1
+#define mmDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
+#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
+#define mmDPREFCLK_CNTL                                                                                0x0058
+#define mmDPREFCLK_CNTL_BASE_IDX                                                                       1
+#define mmDCE_VERSION                                                                                  0x005e
+#define mmDCE_VERSION_BASE_IDX                                                                         1
+#define mmDCCG_GTC_CNTL                                                                                0x0060
+#define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1
+#define mmDCCG_GTC_DTO_INCR                                                                            0x0061
+#define mmDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
+#define mmDCCG_GTC_DTO_MODULO                                                                          0x0062
+#define mmDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
+#define mmDCCG_GTC_CURRENT                                                                             0x0063
+#define mmDCCG_GTC_CURRENT_BASE_IDX                                                                    1
+#define mmDSCCLK0_DTO_PARAM                                                                            0x006c
+#define mmDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define mmDSCCLK1_DTO_PARAM                                                                            0x006d
+#define mmDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define mmDSCCLK2_DTO_PARAM                                                                            0x006e
+#define mmDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define mmMILLISECOND_TIME_BASE_DIV                                                                    0x0070
+#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define mmDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
+#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
+#define mmDCCG_PERFMON_CNTL                                                                            0x0073
+#define mmDCCG_PERFMON_CNTL_BASE_IDX                                                                   1
+#define mmDCCG_GATE_DISABLE_CNTL                                                                       0x0074
+#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
+#define mmDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
+#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
+#define mmSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
+#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define mmDCCG_CAC_STATUS                                                                              0x0077
+#define mmDCCG_CAC_STATUS_BASE_IDX                                                                     1
+#define mmMICROSECOND_TIME_BASE_DIV                                                                    0x007b
+#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define mmDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
+#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
+#define mmSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
+#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define mmDCCG_DISP_CNTL_REG                                                                           0x007f
+#define mmDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
+#define mmOTG0_PIXEL_RATE_CNTL                                                                         0x0080
+#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define mmDP_DTO0_PHASE                                                                                0x0081
+#define mmDP_DTO0_PHASE_BASE_IDX                                                                       1
+#define mmDP_DTO0_MODULO                                                                               0x0082
+#define mmDP_DTO0_MODULO_BASE_IDX                                                                      1
+#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
+#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define mmOTG1_PIXEL_RATE_CNTL                                                                         0x0084
+#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define mmDP_DTO1_PHASE                                                                                0x0085
+#define mmDP_DTO1_PHASE_BASE_IDX                                                                       1
+#define mmDP_DTO1_MODULO                                                                               0x0086
+#define mmDP_DTO1_MODULO_BASE_IDX                                                                      1
+#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
+#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define mmOTG2_PIXEL_RATE_CNTL                                                                         0x0088
+#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define mmDP_DTO2_PHASE                                                                                0x0089
+#define mmDP_DTO2_PHASE_BASE_IDX                                                                       1
+#define mmDP_DTO2_MODULO                                                                               0x008a
+#define mmDP_DTO2_MODULO_BASE_IDX                                                                      1
+#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
+#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define mmOTG3_PIXEL_RATE_CNTL                                                                         0x008c
+#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define mmDP_DTO3_PHASE                                                                                0x008d
+#define mmDP_DTO3_PHASE_BASE_IDX                                                                       1
+#define mmDP_DTO3_MODULO                                                                               0x008e
+#define mmDP_DTO3_MODULO_BASE_IDX                                                                      1
+#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
+#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define mmDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
+#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define mmDPPCLK0_DTO_PARAM                                                                            0x0099
+#define mmDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define mmDPPCLK1_DTO_PARAM                                                                            0x009a
+#define mmDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define mmDPPCLK2_DTO_PARAM                                                                            0x009b
+#define mmDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define mmDPPCLK3_DTO_PARAM                                                                            0x009c
+#define mmDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
+#define mmDCCG_CAC_STATUS2                                                                             0x009f
+#define mmDCCG_CAC_STATUS2_BASE_IDX                                                                    1
+#define mmSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
+#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
+#define mmSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
+#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
+#define mmSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
+#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
+#define mmSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
+#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
+#define mmDCCG_SOFT_RESET                                                                              0x00a6
+#define mmDCCG_SOFT_RESET_BASE_IDX                                                                     1
+#define mmDSCCLK_DTO_CTRL                                                                              0x00a7
+#define mmDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define mmDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
+#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
+#define mmDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
+#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
+#define mmDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
+#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
+#define mmDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
+#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
+#define mmDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
+#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
+#define mmDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
+#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
+#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
+#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
+#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
+#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
+#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
+#define mmDPPCLK_DTO_CTRL                                                                              0x00b6
+#define mmDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define mmDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
+#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
+#define mmDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
+#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
+#define mmFORCE_SYMCLK_DISABLE                                                                         0x00ba
+#define mmFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
+#define mmPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
+#define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define mmPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
+#define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define mmPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054
+#define mmPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define mmPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055
+#define mmPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+// base address: 0x0
+#define mmDENTIST_DISPCLK_CNTL                                                                         0x0064
+#define mmDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
+// base address: 0x0
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001
+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002
+#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON0_PERFMON_CNTL                                                                     0x0003
+#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004
+#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005
+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006
+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON0_PERFMON_HI                                                                       0x0007
+#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON0_PERFMON_LOW                                                                      0x0008
+#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
+// base address: 0x30
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x000c
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x000d
+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON1_PERFCOUNTER_STATE                                                                0x000e
+#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON1_PERFMON_CNTL                                                                     0x000f
+#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON1_PERFMON_CNTL2                                                                    0x0010
+#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x0011
+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x0012
+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON1_PERFMON_HI                                                                       0x0013
+#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON1_PERFMON_LOW                                                                      0x0014
+#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_dc_pg_dispdec
+// base address: 0x0
+#define mmDOMAIN0_PG_CONFIG                                                                            0x0080
+#define mmDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
+#define mmDOMAIN0_PG_STATUS                                                                            0x0081
+#define mmDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
+#define mmDOMAIN1_PG_CONFIG                                                                            0x0082
+#define mmDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
+#define mmDOMAIN1_PG_STATUS                                                                            0x0083
+#define mmDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
+#define mmDOMAIN2_PG_CONFIG                                                                            0x0084
+#define mmDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
+#define mmDOMAIN2_PG_STATUS                                                                            0x0085
+#define mmDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
+#define mmDOMAIN3_PG_CONFIG                                                                            0x0086
+#define mmDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
+#define mmDOMAIN3_PG_STATUS                                                                            0x0087
+#define mmDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
+#define mmDOMAIN4_PG_CONFIG                                                                            0x0088
+#define mmDOMAIN4_PG_CONFIG_BASE_IDX                                                                   2
+#define mmDOMAIN4_PG_STATUS                                                                            0x0089
+#define mmDOMAIN4_PG_STATUS_BASE_IDX                                                                   2
+#define mmDOMAIN5_PG_CONFIG                                                                            0x008a
+#define mmDOMAIN5_PG_CONFIG_BASE_IDX                                                                   2
+#define mmDOMAIN5_PG_STATUS                                                                            0x008b
+#define mmDOMAIN5_PG_STATUS_BASE_IDX                                                                   2
+#define mmDOMAIN6_PG_CONFIG                                                                            0x008c
+#define mmDOMAIN6_PG_CONFIG_BASE_IDX                                                                   2
+#define mmDOMAIN6_PG_STATUS                                                                            0x008d
+#define mmDOMAIN6_PG_STATUS_BASE_IDX                                                                   2
+#define mmDOMAIN7_PG_CONFIG                                                                            0x008e
+#define mmDOMAIN7_PG_CONFIG_BASE_IDX                                                                   2
+#define mmDOMAIN7_PG_STATUS                                                                            0x008f
+#define mmDOMAIN7_PG_STATUS_BASE_IDX                                                                   2
+#define mmDOMAIN16_PG_CONFIG                                                                           0x00a1
+#define mmDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
+#define mmDOMAIN16_PG_STATUS                                                                           0x00a2
+#define mmDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
+#define mmDOMAIN17_PG_CONFIG                                                                           0x00a3
+#define mmDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
+#define mmDOMAIN17_PG_STATUS                                                                           0x00a4
+#define mmDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
+#define mmDOMAIN18_PG_CONFIG                                                                           0x00a5
+#define mmDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
+#define mmDOMAIN18_PG_STATUS                                                                           0x00a6
+#define mmDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
+#define mmDCPG_INTERRUPT_STATUS                                                                        0x00ad
+#define mmDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define mmDCPG_INTERRUPT_STATUS_2                                                                      0x00ae
+#define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
+#define mmDCPG_INTERRUPT_CONTROL_1                                                                     0x00af
+#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
+#define mmDCPG_INTERRUPT_CONTROL_2                                                                     0x00b0
+#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX                                                            2
+#define mmDCPG_INTERRUPT_CONTROL_3                                                                     0x00b1
+#define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
+#define mmDC_IP_REQUEST_CNTL                                                                           0x00b2
+#define mmDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
+// base address: 0x2f8
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x00be
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x00bf
+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON2_PERFCOUNTER_STATE                                                                0x00c0
+#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON2_PERFMON_CNTL                                                                     0x00c1
+#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON2_PERFMON_CNTL2                                                                    0x00c2
+#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x00c3
+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x00c4
+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON2_PERFMON_HI                                                                       0x00c5
+#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON2_PERFMON_LOW                                                                      0x00c6
+#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+// base address: 0x0
+#define mmCC_DC_PIPE_DIS                                                                               0x00ca
+#define mmCC_DC_PIPE_DIS_BASE_IDX                                                                      2
+#define mmDMU_CLK_CNTL                                                                                 0x00cb
+#define mmDMU_CLK_CNTL_BASE_IDX                                                                        2
+#define mmDMU_MEM_PWR_CNTL                                                                             0x00cc
+#define mmDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2
+#define mmDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
+#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_dmcu_dispdec
+// base address: 0x0
+#define mmDMCU_CTRL                                                                                    0x00da
+#define mmDMCU_CTRL_BASE_IDX                                                                           2
+#define mmDMCU_STATUS                                                                                  0x00db
+#define mmDMCU_STATUS_BASE_IDX                                                                         2
+#define mmDMCU_PC_START_ADDR                                                                           0x00dc
+#define mmDMCU_PC_START_ADDR_BASE_IDX                                                                  2
+#define mmDMCU_FW_START_ADDR                                                                           0x00dd
+#define mmDMCU_FW_START_ADDR_BASE_IDX                                                                  2
+#define mmDMCU_FW_END_ADDR                                                                             0x00de
+#define mmDMCU_FW_END_ADDR_BASE_IDX                                                                    2
+#define mmDMCU_FW_ISR_START_ADDR                                                                       0x00df
+#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX                                                              2
+#define mmDMCU_FW_CS_HI                                                                                0x00e0
+#define mmDMCU_FW_CS_HI_BASE_IDX                                                                       2
+#define mmDMCU_FW_CS_LO                                                                                0x00e1
+#define mmDMCU_FW_CS_LO_BASE_IDX                                                                       2
+#define mmDMCU_RAM_ACCESS_CTRL                                                                         0x00e2
+#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX                                                                2
+#define mmDMCU_ERAM_WR_CTRL                                                                            0x00e3
+#define mmDMCU_ERAM_WR_CTRL_BASE_IDX                                                                   2
+#define mmDMCU_ERAM_WR_DATA                                                                            0x00e4
+#define mmDMCU_ERAM_WR_DATA_BASE_IDX                                                                   2
+#define mmDMCU_ERAM_RD_CTRL                                                                            0x00e5
+#define mmDMCU_ERAM_RD_CTRL_BASE_IDX                                                                   2
+#define mmDMCU_ERAM_RD_DATA                                                                            0x00e6
+#define mmDMCU_ERAM_RD_DATA_BASE_IDX                                                                   2
+#define mmDMCU_IRAM_WR_CTRL                                                                            0x00e7
+#define mmDMCU_IRAM_WR_CTRL_BASE_IDX                                                                   2
+#define mmDMCU_IRAM_WR_DATA                                                                            0x00e8
+#define mmDMCU_IRAM_WR_DATA_BASE_IDX                                                                   2
+#define mmDMCU_IRAM_RD_CTRL                                                                            0x00e9
+#define mmDMCU_IRAM_RD_CTRL_BASE_IDX                                                                   2
+#define mmDMCU_IRAM_RD_DATA                                                                            0x00ea
+#define mmDMCU_IRAM_RD_DATA_BASE_IDX                                                                   2
+#define mmDMCU_EVENT_TRIGGER                                                                           0x00eb
+#define mmDMCU_EVENT_TRIGGER_BASE_IDX                                                                  2
+#define mmDMCU_UC_INTERNAL_INT_STATUS                                                                  0x00ec
+#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX                                                         2
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                                                0x00ed
+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX                                                       2
+#define mmDMCU_INTERRUPT_STATUS                                                                        0x00ee
+#define mmDMCU_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define mmDMCU_INTERRUPT_STATUS_1                                                                      0x00ef
+#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX                                                             2
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                                               0x00f0
+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX                                                      2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                                                 0x00f1
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1                                                               0x00f2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX                                                      2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                                            0x00f3
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                                          0x00f4
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX                                                 2
+#define mmDC_DMCU_SCRATCH                                                                              0x00f5
+#define mmDC_DMCU_SCRATCH_BASE_IDX                                                                     2
+#define mmDMCU_INT_CNT                                                                                 0x00f6
+#define mmDMCU_INT_CNT_BASE_IDX                                                                        2
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                                               0x00f7
+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX                                                      2
+#define mmDMCU_UC_CLK_GATING_CNTL                                                                      0x00f8
+#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
+#define mmMASTER_COMM_DATA_REG1                                                                        0x00f9
+#define mmMASTER_COMM_DATA_REG1_BASE_IDX                                                               2
+#define mmMASTER_COMM_DATA_REG2                                                                        0x00fa
+#define mmMASTER_COMM_DATA_REG2_BASE_IDX                                                               2
+#define mmMASTER_COMM_DATA_REG3                                                                        0x00fb
+#define mmMASTER_COMM_DATA_REG3_BASE_IDX                                                               2
+#define mmMASTER_COMM_CMD_REG                                                                          0x00fc
+#define mmMASTER_COMM_CMD_REG_BASE_IDX                                                                 2
+#define mmMASTER_COMM_CNTL_REG                                                                         0x00fd
+#define mmMASTER_COMM_CNTL_REG_BASE_IDX                                                                2
+#define mmSLAVE_COMM_DATA_REG1                                                                         0x00fe
+#define mmSLAVE_COMM_DATA_REG1_BASE_IDX                                                                2
+#define mmSLAVE_COMM_DATA_REG2                                                                         0x00ff
+#define mmSLAVE_COMM_DATA_REG2_BASE_IDX                                                                2
+#define mmSLAVE_COMM_DATA_REG3                                                                         0x0100
+#define mmSLAVE_COMM_DATA_REG3_BASE_IDX                                                                2
+#define mmSLAVE_COMM_CMD_REG                                                                           0x0101
+#define mmSLAVE_COMM_CMD_REG_BASE_IDX                                                                  2
+#define mmSLAVE_COMM_CNTL_REG                                                                          0x0102
+#define mmSLAVE_COMM_CNTL_REG_BASE_IDX                                                                 2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1                                                               0x0105
+#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX                                                      2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2                                                               0x0106
+#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX                                                      2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3                                                               0x0107
+#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX                                                      2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4                                                               0x0108
+#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX                                                      2
+#define mmDMCU_PERFMON_INTERRUPT_STATUS5                                                               0x0109
+#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX                                                      2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                                        0x010a
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                               2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                                        0x010b
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX                                               2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                                        0x010c
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX                                               2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                                        0x010d
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX                                               2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                                        0x010e
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX                                               2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                   0x010f
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                          2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                                                   0x0110
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX                                          2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                                                   0x0111
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX                                          2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                                                   0x0112
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX                                          2
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                                                   0x0113
+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX                                          2
+#define mmDMCU_DPRX_INTERRUPT_STATUS1                                                                  0x0114
+#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX                                                         2
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                                           0x0115
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                                  2
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                      0x0116
+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                             2
+#define mmDMCU_INTERRUPT_STATUS_CONTINUE                                                               0x0119
+#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE                                                        0x011a
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX                                               2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE                                                   0x011b
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX                                          2
+#define mmDMCU_INT_CNT_CONTINUE                                                                        0x011c
+#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX                                                               2
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2                                                      0x011d
+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX                                             2
+#define mmDMCU_INTERRUPT_STATUS_2                                                                      0x011e
+#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX                                                             2
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2                                                               0x011f
+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX                                                      2
+#define mmDMCU_INT_CNT_CONT2                                                                           0x0120
+#define mmDMCU_INT_CNT_CONT2_BASE_IDX                                                                  2
+#define mmDMCU_INT_CNT_CONT3                                                                           0x0121
+#define mmDMCU_INT_CNT_CONT3_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+// base address: 0x0
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
+#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
+#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
+#define mmDC_GPU_TIMER_READ                                                                            0x0128
+#define mmDC_GPU_TIMER_READ_BASE_IDX                                                                   2
+#define mmDC_GPU_TIMER_READ_CNTL                                                                       0x0129
+#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
+#define mmDISP_INTERRUPT_STATUS                                                                        0x012a
+#define mmDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
+#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
+#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
+#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
+#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
+#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
+#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
+#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
+#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
+#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
+#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
+#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
+#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
+#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
+#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
+#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
+#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
+#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
+#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
+#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
+#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
+#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
+#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
+#define mmDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
+#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
+#define mmDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
+#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
+#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
+#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
+#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
+#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
+#define mmDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
+#define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
+#define mmDCCG_INTERRUPT_DEST                                                                          0x0148
+#define mmDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmDMU_INTERRUPT_DEST                                                                           0x0149
+#define mmDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmDMU_INTERRUPT_DEST2                                                                          0x014a
+#define mmDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
+#define mmDCPG_INTERRUPT_DEST                                                                          0x014b
+#define mmDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmDCPG_INTERRUPT_DEST2                                                                         0x014c
+#define mmDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
+#define mmMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
+#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
+#define mmWB_INTERRUPT_DEST                                                                            0x014e
+#define mmWB_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define mmDCHUB_INTERRUPT_DEST                                                                         0x014f
+#define mmDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
+#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
+#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
+#define mmDCHUB_INTERRUPT_DEST2                                                                        0x0151
+#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
+#define mmDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
+#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
+#define mmMPC_INTERRUPT_DEST                                                                           0x0153
+#define mmMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmOPP_INTERRUPT_DEST                                                                           0x0154
+#define mmOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmOPTC_INTERRUPT_DEST                                                                          0x0155
+#define mmOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG0_INTERRUPT_DEST                                                                          0x0156
+#define mmOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG1_INTERRUPT_DEST                                                                          0x0157
+#define mmOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG2_INTERRUPT_DEST                                                                          0x0158
+#define mmOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG3_INTERRUPT_DEST                                                                          0x0159
+#define mmOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG4_INTERRUPT_DEST                                                                          0x015a
+#define mmOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmOTG5_INTERRUPT_DEST                                                                          0x015b
+#define mmOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmDIG_INTERRUPT_DEST                                                                           0x015c
+#define mmDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
+#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
+#define mmDIO_INTERRUPT_DEST                                                                           0x015f
+#define mmDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmDCIO_INTERRUPT_DEST                                                                          0x0160
+#define mmDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define mmHPD_INTERRUPT_DEST                                                                           0x0161
+#define mmHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmAZ_INTERRUPT_DEST                                                                            0x0162
+#define mmAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define mmAUX_INTERRUPT_DEST                                                                           0x0163
+#define mmAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define mmDSC_INTERRUPT_DEST                                                                           0x0164
+#define mmDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_fgsec_dispdec
+// base address: 0x0
+#define mmDMCUB_RBBMIF_SEC_CNTL                                                                        0x017a
+#define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+// base address: 0x0
+#define mmRBBMIF_TIMEOUT                                                                               0x017f
+#define mmRBBMIF_TIMEOUT_BASE_IDX                                                                      2
+#define mmRBBMIF_STATUS                                                                                0x0180
+#define mmRBBMIF_STATUS_BASE_IDX                                                                       2
+#define mmRBBMIF_STATUS_2                                                                              0x0181
+#define mmRBBMIF_STATUS_2_BASE_IDX                                                                     2
+#define mmRBBMIF_INT_STATUS                                                                            0x0182
+#define mmRBBMIF_INT_STATUS_BASE_IDX                                                                   2
+#define mmRBBMIF_TIMEOUT_DIS                                                                           0x0183
+#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
+#define mmRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
+#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
+#define mmRBBMIF_STATUS_FLAG                                                                           0x0185
+#define mmRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+// base address: 0x0
+#define mmDMCUB_REGION0_OFFSET                                                                         0x018e
+#define mmDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
+#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION1_OFFSET                                                                         0x0190
+#define mmDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
+#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION2_OFFSET                                                                         0x0192
+#define mmDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
+#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION4_OFFSET                                                                         0x0196
+#define mmDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
+#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION5_OFFSET                                                                         0x0198
+#define mmDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
+#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION6_OFFSET                                                                         0x019a
+#define mmDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
+#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION7_OFFSET                                                                         0x019c
+#define mmDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
+#define mmDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
+#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
+#define mmDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
+#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
+#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
+#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
+#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
+#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
+#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
+#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
+#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
+#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
+#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
+#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
+#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
+#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
+#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
+#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
+#define mmDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
+#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
+#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
+#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
+#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
+#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
+#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
+#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
+#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
+#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
+#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
+#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
+#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
+#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
+#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
+#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
+#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
+#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
+#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
+#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
+#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
+#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
+#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
+#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
+#define mmDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
+#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
+#define mmDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
+#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
+#define mmDMCUB_INTERRUPT_ACK                                                                          0x01c6
+#define mmDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
+#define mmDMCUB_INTERRUPT_STATUS                                                                       0x01c7
+#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
+#define mmDMCUB_INTERRUPT_TYPE                                                                         0x01c8
+#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
+#define mmDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
+#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
+#define mmDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
+#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
+#define mmDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
+#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
+#define mmDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
+#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
+#define mmDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
+#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
+#define mmDMCUB_SEC_CNTL                                                                               0x01ce
+#define mmDMCUB_SEC_CNTL_BASE_IDX                                                                      2
+#define mmDMCUB_MEM_CNTL                                                                               0x01cf
+#define mmDMCUB_MEM_CNTL_BASE_IDX                                                                      2
+#define mmDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
+#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_INBOX0_SIZE                                                                            0x01d1
+#define mmDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
+#define mmDMCUB_INBOX0_WPTR                                                                            0x01d2
+#define mmDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
+#define mmDMCUB_INBOX0_RPTR                                                                            0x01d3
+#define mmDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
+#define mmDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
+#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
+#define mmDMCUB_INBOX1_SIZE                                                                            0x01d5
+#define mmDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
+#define mmDMCUB_INBOX1_WPTR                                                                            0x01d6
+#define mmDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
+#define mmDMCUB_INBOX1_RPTR                                                                            0x01d7
+#define mmDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
+#define mmDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
+#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
+#define mmDMCUB_OUTBOX0_SIZE                                                                           0x01d9
+#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
+#define mmDMCUB_OUTBOX0_WPTR                                                                           0x01da
+#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
+#define mmDMCUB_OUTBOX0_RPTR                                                                           0x01db
+#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
+#define mmDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
+#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
+#define mmDMCUB_OUTBOX1_SIZE                                                                           0x01dd
+#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
+#define mmDMCUB_OUTBOX1_WPTR                                                                           0x01de
+#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
+#define mmDMCUB_OUTBOX1_RPTR                                                                           0x01df
+#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
+#define mmDMCUB_TIMER_TRIGGER0                                                                         0x01e0
+#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
+#define mmDMCUB_TIMER_TRIGGER1                                                                         0x01e1
+#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
+#define mmDMCUB_TIMER_WINDOW                                                                           0x01e2
+#define mmDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
+#define mmDMCUB_SCRATCH0                                                                               0x01e3
+#define mmDMCUB_SCRATCH0_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH1                                                                               0x01e4
+#define mmDMCUB_SCRATCH1_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH2                                                                               0x01e5
+#define mmDMCUB_SCRATCH2_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH3                                                                               0x01e6
+#define mmDMCUB_SCRATCH3_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH4                                                                               0x01e7
+#define mmDMCUB_SCRATCH4_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH5                                                                               0x01e8
+#define mmDMCUB_SCRATCH5_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH6                                                                               0x01e9
+#define mmDMCUB_SCRATCH6_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH7                                                                               0x01ea
+#define mmDMCUB_SCRATCH7_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH8                                                                               0x01eb
+#define mmDMCUB_SCRATCH8_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH9                                                                               0x01ec
+#define mmDMCUB_SCRATCH9_BASE_IDX                                                                      2
+#define mmDMCUB_SCRATCH10                                                                              0x01ed
+#define mmDMCUB_SCRATCH10_BASE_IDX                                                                     2
+#define mmDMCUB_SCRATCH11                                                                              0x01ee
+#define mmDMCUB_SCRATCH11_BASE_IDX                                                                     2
+#define mmDMCUB_SCRATCH12                                                                              0x01ef
+#define mmDMCUB_SCRATCH12_BASE_IDX                                                                     2
+#define mmDMCUB_SCRATCH13                                                                              0x01f0
+#define mmDMCUB_SCRATCH13_BASE_IDX                                                                     2
+#define mmDMCUB_SCRATCH14                                                                              0x01f1
+#define mmDMCUB_SCRATCH14_BASE_IDX                                                                     2
+#define mmDMCUB_SCRATCH15                                                                              0x01f2
+#define mmDMCUB_SCRATCH15_BASE_IDX                                                                     2
+#define mmDMCUB_CNTL                                                                                   0x01f6
+#define mmDMCUB_CNTL_BASE_IDX                                                                          2
+#define mmDMCUB_GPINT_DATAIN0                                                                          0x01f7
+#define mmDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
+#define mmDMCUB_GPINT_DATAIN1                                                                          0x01f8
+#define mmDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
+#define mmDMCUB_GPINT_DATAOUT                                                                          0x01f9
+#define mmDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
+#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
+#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
+#define mmDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
+#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
+#define mmDMCUB_MEM_PWR_CNTL                                                                           0x01fc
+#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
+#define mmDMCUB_TIMER_CURRENT                                                                          0x01fd
+#define mmDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
+#define mmDMCUB_PROC_ID                                                                                0x01ff
+#define mmDMCUB_PROC_ID_BASE_IDX                                                                       2
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+// base address: 0x0
+#define mmMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
+#define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
+#define mmMCIF_WB_BUFMGR_STATUS                                                                        0x0274
+#define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
+#define mmMCIF_WB_BUF_PITCH                                                                            0x0275
+#define mmMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
+#define mmMCIF_WB_BUF_1_STATUS                                                                         0x0276
+#define mmMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_1_STATUS2                                                                        0x0277
+#define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
+#define mmMCIF_WB_BUF_2_STATUS                                                                         0x0278
+#define mmMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_2_STATUS2                                                                        0x0279
+#define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
+#define mmMCIF_WB_BUF_3_STATUS                                                                         0x027a
+#define mmMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_3_STATUS2                                                                        0x027b
+#define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
+#define mmMCIF_WB_BUF_4_STATUS                                                                         0x027c
+#define mmMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_4_STATUS2                                                                        0x027d
+#define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
+#define mmMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
+#define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
+#define mmMCIF_WB_SCLK_CHANGE                                                                          0x027f
+#define mmMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
+#define mmMCIF_WB_TEST_DEBUG_INDEX                                                                     0x0280
+#define mmMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                            2
+#define mmMCIF_WB_TEST_DEBUG_DATA                                                                      0x0281
+#define mmMCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                             2
+#define mmMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
+#define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
+#define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
+#define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
+#define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
+#define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
+#define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
+#define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
+#define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
+#define mmMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
+#define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
+#define mmMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
+#define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
+#define mmMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
+#define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
+#define mmMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
+#define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
+#define mmMULTI_LEVEL_QOS_CTRL                                                                         0x0297
+#define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
+#define mmMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
+#define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
+#define mmMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
+#define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
+#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
+#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
+#define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
+#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
+#define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
+#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
+#define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
+#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
+#define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
+#define mmMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
+#define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
+#define mmMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
+#define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
+#define mmMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
+#define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
+#define mmMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
+#define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
+#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI                                                       0x02a7
+#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX                                              2
+#define mmMCIF_WB_VMID_CONTROL                                                                         0x02a8
+#define mmMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
+#define mmMCIF_WB_MIN_TTO                                                                              0x02a9
+#define mmMCIF_WB_MIN_TTO_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+// base address: 0x0
+#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
+#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
+#define mmMCIF_WB_WATERMARK                                                                            0x02ab
+#define mmMCIF_WB_WATERMARK_BASE_IDX                                                                   2
+#define mmMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
+#define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
+#define mmMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
+#define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
+#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
+#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
+#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
+#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
+#define mmMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
+#define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
+#define mmMMHUBBUB_MIN_TTO                                                                             0x02b1
+#define mmMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
+#define mmWBIF0_MISC_CTRL                                                                              0x0334
+#define mmWBIF0_MISC_CTRL_BASE_IDX                                                                     2
+#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0335
+#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0336
+#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define mmVGA_SRC_SPLIT_CNTL                                                                           0x033d
+#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
+#define mmMMHUBBUB_MEM_PWR_STATUS                                                                      0x033e
+#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define mmMMHUBBUB_MEM_PWR_CNTL                                                                        0x033f
+#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
+#define mmMMHUBBUB_CLOCK_CNTL                                                                          0x0340
+#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define mmMMHUBBUB_SOFT_RESET                                                                          0x0341
+#define mmMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define mmDMU_IF_ERR_STATUS                                                                            0x0345
+#define mmDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
+#define mmMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0346
+#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
+#define mmMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0348
+#define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+// base address: 0x0
+#define mmMCIF_CONTROL                                                                                 0x034a
+#define mmMCIF_CONTROL_BASE_IDX                                                                        2
+#define mmMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
+#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
+// base address: 0xd48
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x0352
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x0353
+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON3_PERFCOUNTER_STATE                                                                0x0354
+#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON3_PERFMON_CNTL                                                                     0x0355
+#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON3_PERFMON_CNTL2                                                                    0x0356
+#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x0357
+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x0358
+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON3_PERFMON_HI                                                                       0x0359
+#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON3_PERFMON_LOW                                                                      0x035a
+#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+// base address: 0x0
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
+#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+// base address: 0x8
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
+#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+// base address: 0x10
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
+#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+// base address: 0x18
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
+#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+// base address: 0x20
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
+#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+// base address: 0x28
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
+#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+// base address: 0x30
+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
+#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+// base address: 0x38
+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
+#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+// base address: 0x0
+#define mmAZ_CLOCK_CNTL                                                                                0x0372
+#define mmAZ_CLOCK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
+// base address: 0xde8
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x037a
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x037b
+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON4_PERFCOUNTER_STATE                                                                0x037c
+#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON4_PERFMON_CNTL                                                                     0x037d
+#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON4_PERFMON_CNTL2                                                                    0x037e
+#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x037f
+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0380
+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON4_PERFMON_HI                                                                       0x0381
+#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON4_PERFMON_LOW                                                                      0x0382
+#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+// base address: 0x0
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+// base address: 0x18
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+// base address: 0x30
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+// base address: 0x48
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+// base address: 0x60
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+// base address: 0x78
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+// base address: 0x90
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+// base address: 0xa8
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+// base address: 0x0
+#define mmAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
+#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
+#define mmAZALIA_AUDIO_DTO                                                                             0x03c3
+#define mmAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
+#define mmAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
+#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
+#define mmAZALIA_SOCCLK_CONTROL                                                                        0x03c5
+#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
+#define mmAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
+#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
+#define mmAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
+#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
+#define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
+#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
+#define mmAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
+#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
+#define mmAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
+#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
+#define mmAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
+#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
+#define mmAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
+#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
+#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
+#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
+#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
+#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
+#define mmAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
+#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
+#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
+#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
+#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
+#define mmAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
+#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
+#define mmAZALIA_CRC0_CONTROL0                                                                         0x03e3
+#define mmAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
+#define mmAZALIA_CRC0_CONTROL1                                                                         0x03e4
+#define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
+#define mmAZALIA_CRC0_CONTROL2                                                                         0x03e5
+#define mmAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
+#define mmAZALIA_CRC0_CONTROL3                                                                         0x03e6
+#define mmAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
+#define mmAZALIA_CRC0_RESULT                                                                           0x03e7
+#define mmAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
+#define mmAZALIA_CRC1_CONTROL0                                                                         0x03e8
+#define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
+#define mmAZALIA_CRC1_CONTROL1                                                                         0x03e9
+#define mmAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
+#define mmAZALIA_CRC1_CONTROL2                                                                         0x03ea
+#define mmAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
+#define mmAZALIA_CRC1_CONTROL3                                                                         0x03eb
+#define mmAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
+#define mmAZALIA_CRC1_RESULT                                                                           0x03ec
+#define mmAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
+#define mmAZALIA_MEM_PWR_CTRL                                                                          0x03ee
+#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define mmAZALIA_MEM_PWR_STATUS                                                                        0x03ef
+#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+// base address: 0x0
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
+#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
+#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
+#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
+#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
+#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
+#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
+#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+// base address: 0x320
+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
+#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+// base address: 0x328
+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define mmAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
+#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+// base address: 0x330
+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
+#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+// base address: 0x338
+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
+#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+// base address: 0x340
+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
+#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+// base address: 0x348
+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
+#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+// base address: 0x350
+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
+#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+// base address: 0x358
+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define mmAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
+#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+// base address: 0x0
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+// base address: 0x10
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+// base address: 0x20
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+// base address: 0x30
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+// base address: 0x40
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+// base address: 0x50
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+// base address: 0x60
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+// base address: 0x70
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
+// base address: 0x0
+#define mmDCHUBBUB_SDPIF_CFG0                                                                          0x048f
+#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
+#define mmVM_REQUEST_PHYSICAL                                                                          0x0490
+#define mmVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
+#define mmDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0491
+#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
+#define mmDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0492
+#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
+#define mmDCN_VM_FB_LOCATION_BASE                                                                      0x0493
+#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
+#define mmDCN_VM_FB_LOCATION_TOP                                                                       0x0494
+#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
+#define mmDCN_VM_FB_OFFSET                                                                             0x0495
+#define mmDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
+#define mmDCN_VM_AGP_BOT                                                                               0x0496
+#define mmDCN_VM_AGP_BOT_BASE_IDX                                                                      2
+#define mmDCN_VM_AGP_TOP                                                                               0x0497
+#define mmDCN_VM_AGP_TOP_BASE_IDX                                                                      2
+#define mmDCN_VM_AGP_BASE                                                                              0x0498
+#define mmDCN_VM_AGP_BASE_BASE_IDX                                                                     2
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x0499
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x049a
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x049b
+#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
+#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x04ba
+#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
+#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x04bb
+#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
+#define mmDCHUBBUB_SDPIF_CFG1                                                                          0x04bf
+#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
+#define mmDCHUBBUB_SDPIF_CFG2                                                                          0x04c0
+#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
+// base address: 0x0
+#define mmDCHUBBUB_RET_PATH_DCC_CFG                                                                    0x04cf
+#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX                                                           2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0                                                                 0x04d0
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1                                                                 0x04d1
+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0                                                                 0x04d2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1                                                                 0x04d3
+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0                                                                 0x04d4
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1                                                                 0x04d5
+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0                                                                 0x04d6
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1                                                                 0x04d7
+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0                                                                 0x04d8
+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1                                                                 0x04d9
+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0                                                                 0x04da
+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1                                                                 0x04db
+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0                                                                 0x04dc
+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1                                                                 0x04dd
+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0                                                                 0x04de
+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1                                                                 0x04df
+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX                                                        2
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04ef
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04f0
+#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
+#define mmDCHUBBUB_CRC_CTRL                                                                            0x04f1
+#define mmDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
+#define mmDCHUBBUB_CRC0_VAL_R_G                                                                        0x04f2
+#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
+#define mmDCHUBBUB_CRC0_VAL_B_A                                                                        0x04f3
+#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
+#define mmDCHUBBUB_CRC1_VAL_R_G                                                                        0x04f4
+#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
+#define mmDCHUBBUB_CRC1_VAL_B_A                                                                        0x04f5
+#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_dispdec
+// base address: 0x0
+#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x0505
+#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
+#define mmDCHUBBUB_ARB_SAT_LEVEL                                                                       0x0506
+#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
+#define mmDCHUBBUB_ARB_QOS_FORCE                                                                       0x0507
+#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
+#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x0508
+#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x0509
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x050a
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x050b
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x050c
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A                                               0x050d
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX                                      2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x050e
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x050f
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x0510
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x0511
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B                                               0x0512
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX                                      2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0513
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0514
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0515
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0516
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C                                               0x0517
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX                                      2
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0518
+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0519
+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051a
+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051b
+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D                                               0x051c
+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX                                      2
+#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x051d
+#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
+#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x051e
+#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
+#define mmDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x051f
+#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
+#define mmSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0520
+#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0521
+#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0522
+#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0523
+#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0524
+#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK2_ADDRESS_MSB                                                                   0x0525
+#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK3_ADDRESS_LSB                                                                   0x0526
+#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
+#define mmSURFACE_CHECK3_ADDRESS_MSB                                                                   0x0527
+#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
+#define mmVTG0_CONTROL                                                                                 0x0528
+#define mmVTG0_CONTROL_BASE_IDX                                                                        2
+#define mmVTG1_CONTROL                                                                                 0x0529
+#define mmVTG1_CONTROL_BASE_IDX                                                                        2
+#define mmVTG2_CONTROL                                                                                 0x052a
+#define mmVTG2_CONTROL_BASE_IDX                                                                        2
+#define mmVTG3_CONTROL                                                                                 0x052b
+#define mmVTG3_CONTROL_BASE_IDX                                                                        2
+#define mmDCHUBBUB_SOFT_RESET                                                                          0x052e
+#define mmDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define mmDCHUBBUB_CLOCK_CNTL                                                                          0x052f
+#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define mmDCFCLK_CNTL                                                                                  0x0530
+#define mmDCFCLK_CNTL_BASE_IDX                                                                         2
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0531
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0532
+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
+#define mmDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0533
+#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
+#define mmDCHUBBUB_CTRL_STATUS                                                                         0x0534
+#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053a
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053b
+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
+#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x053c
+#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
+#define mmDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x053d
+#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
+#define mmDCHUBBUB_TEST_DEBUG_DATA                                                                     0x053e
+#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x053f
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0540
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x0541
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x0542
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0543
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0544
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0545
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0546
+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
+#define mmDCHUBBUB_ARB_HOSTVM_CNTL                                                                     0x0547
+#define mmDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX                                                            2
+#define mmFMON_CTRL                                                                                    0x0548
+#define mmFMON_CTRL_BASE_IDX                                                                           2
+#define mmFMON_CTRL_1                                                                                  0x0548
+#define mmFMON_CTRL_1_BASE_IDX                                                                         2
+
+
+// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1534
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x054d
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x054e
+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON5_PERFCOUNTER_STATE                                                                0x054f
+#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON5_PERFMON_CNTL                                                                     0x0550
+#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON5_PERFMON_CNTL2                                                                    0x0551
+#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x0552
+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0553
+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON5_PERFMON_HI                                                                       0x0554
+#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON5_PERFMON_LOW                                                                      0x0555
+#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
+// base address: 0x0
+#define mmDCN_VM_CONTEXT0_CNTL                                                                         0x0559
+#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT1_CNTL                                                                         0x0560
+#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT2_CNTL                                                                         0x0567
+#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT3_CNTL                                                                         0x056e
+#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT4_CNTL                                                                         0x0575
+#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT5_CNTL                                                                         0x057c
+#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT6_CNTL                                                                         0x0583
+#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT7_CNTL                                                                         0x058a
+#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT8_CNTL                                                                         0x0591
+#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT9_CNTL                                                                         0x0598
+#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define mmDCN_VM_CONTEXT10_CNTL                                                                        0x059f
+#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
+#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
+#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
+#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
+#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
+#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define mmDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
+#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
+#define mmDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
+#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
+#define mmDCN_VM_FAULT_CNTL                                                                            0x05cb
+#define mmDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
+#define mmDCN_VM_FAULT_STATUS                                                                          0x05cc
+#define mmDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
+#define mmDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
+#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
+#define mmDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
+#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+// base address: 0x0
+#define mmHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
+#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define mmHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
+#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define mmHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
+#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define mmHUBP0_DCHUBP_CNTL                                                                            0x05f3
+#define mmHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define mmHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
+#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define mmHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
+#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define mmHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f6
+#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define mmHUBP0_HUBPREQ_DEBUG                                                                          0x05f7
+#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fb
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fc
+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+// base address: 0x0
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define mmHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
+#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
+#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0620
+#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0621
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0622
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0623
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0624
+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0625
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0626
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0627
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0628
+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define mmHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0629
+#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x062a
+#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062b
+#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062c
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062d
+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062e
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062f
+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x0630
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0631
+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0632
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0633
+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0634
+#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0635
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0636
+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0643
+#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define mmHUBPREQ0_BLANK_OFFSET_0                                                                      0x0644
+#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define mmHUBPREQ0_BLANK_OFFSET_1                                                                      0x0645
+#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define mmHUBPREQ0_DST_DIMENSIONS                                                                      0x0646
+#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
+#define mmHUBPREQ0_DST_AFTER_SCALER                                                                    0x0647
+#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define mmHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0648
+#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define mmHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0649
+#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x064a
+#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064b
+#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064c
+#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064d
+#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064e
+#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define mmHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064f
+#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define mmHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x0650
+#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define mmHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0651
+#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define mmHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0652
+#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0653
+#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0654
+#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0655
+#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0656
+#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0657
+#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0658
+#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define mmHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0659
+#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x065a
+#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define mmHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065b
+#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define mmHUBPREQ0_CURSOR_SETTINGS                                                                     0x065c
+#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065d
+#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065e
+#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065f
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x0660
+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0663
+#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define mmHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0664
+#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define mmHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0665
+#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define mmHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0666
+#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define mmHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0667
+#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define mmHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0668
+#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+// base address: 0x0
+#define mmHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
+#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
+#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
+#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define mmHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
+#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define mmHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
+#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define mmHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
+#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
+#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
+#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+// base address: 0x0
+#define mmCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
+#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define mmCURSOR0_0_CURSOR_SIZE                                                                        0x067b
+#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
+#define mmCURSOR0_0_CURSOR_POSITION                                                                    0x067c
+#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
+#define mmCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
+#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define mmCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
+#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define mmCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
+#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
+#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
+#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
+#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define mmCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
+#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define mmCURSOR0_0_DMDATA_CNTL                                                                        0x0684
+#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
+#define mmCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
+#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define mmCURSOR0_0_DMDATA_STATUS                                                                      0x0686
+#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
+#define mmCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
+#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define mmCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
+#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1a74
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x069d
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x069e
+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON6_PERFCOUNTER_STATE                                                                0x069f
+#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON6_PERFMON_CNTL                                                                     0x06a0
+#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON6_PERFMON_CNTL2                                                                    0x06a1
+#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x06a2
+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x06a3
+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON6_PERFMON_HI                                                                       0x06a4
+#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON6_PERFMON_LOW                                                                      0x06a5
+#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+// base address: 0x370
+#define mmHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
+#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define mmHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
+#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define mmHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
+#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define mmHUBP1_DCHUBP_CNTL                                                                            0x06cf
+#define mmHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define mmHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
+#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define mmHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
+#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define mmHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d2
+#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define mmHUBP1_HUBPREQ_DEBUG                                                                          0x06d3
+#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d7
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06d8
+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+// base address: 0x370
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define mmHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
+#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
+#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fc
+#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fd
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fe
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06ff
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0700
+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0701
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0702
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0703
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0704
+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define mmHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0705
+#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0706
+#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0707
+#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0708
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0709
+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x070a
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070b
+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070c
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070d
+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070e
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070f
+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x0710
+#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0711
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0712
+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071f
+#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define mmHUBPREQ1_BLANK_OFFSET_0                                                                      0x0720
+#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define mmHUBPREQ1_BLANK_OFFSET_1                                                                      0x0721
+#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define mmHUBPREQ1_DST_DIMENSIONS                                                                      0x0722
+#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
+#define mmHUBPREQ1_DST_AFTER_SCALER                                                                    0x0723
+#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define mmHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0724
+#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define mmHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0725
+#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0726
+#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0727
+#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0728
+#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0729
+#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x072a
+#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define mmHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072b
+#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define mmHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072c
+#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define mmHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072d
+#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define mmHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072e
+#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072f
+#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_2                                                                    0x0730
+#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0731
+#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0732
+#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0733
+#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0734
+#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define mmHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0735
+#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0736
+#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define mmHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0737
+#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define mmHUBPREQ1_CURSOR_SETTINGS                                                                     0x0738
+#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0739
+#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x073a
+#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073b
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073c
+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073f
+#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define mmHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x0740
+#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define mmHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0741
+#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define mmHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0742
+#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define mmHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0743
+#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define mmHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0744
+#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+// base address: 0x370
+#define mmHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
+#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
+#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
+#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define mmHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
+#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define mmHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
+#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define mmHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
+#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
+#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
+#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+// base address: 0x370
+#define mmCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
+#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define mmCURSOR0_1_CURSOR_SIZE                                                                        0x0757
+#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
+#define mmCURSOR0_1_CURSOR_POSITION                                                                    0x0758
+#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
+#define mmCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
+#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define mmCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
+#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define mmCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
+#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
+#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
+#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
+#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define mmCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
+#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define mmCURSOR0_1_DMDATA_CNTL                                                                        0x0760
+#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
+#define mmCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
+#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define mmCURSOR0_1_DMDATA_STATUS                                                                      0x0762
+#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
+#define mmCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
+#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define mmCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
+#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1de4
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x0779
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x077a
+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON7_PERFCOUNTER_STATE                                                                0x077b
+#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON7_PERFMON_CNTL                                                                     0x077c
+#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON7_PERFMON_CNTL2                                                                    0x077d
+#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x077e
+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x077f
+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON7_PERFMON_HI                                                                       0x0780
+#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON7_PERFMON_LOW                                                                      0x0781
+#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
+// base address: 0x6e0
+#define mmHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
+#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define mmHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
+#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define mmHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
+#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define mmHUBP2_DCHUBP_CNTL                                                                            0x07ab
+#define mmHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define mmHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
+#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define mmHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
+#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define mmHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07ae
+#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define mmHUBP2_HUBPREQ_DEBUG                                                                          0x07af
+#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b3
+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b4
+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
+// base address: 0x6e0
+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define mmHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
+#define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
+#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d8
+#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d9
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07da
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07db
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07dc
+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dd
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07de
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07df
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07e0
+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define mmHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e1
+#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define mmHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e2
+#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e3
+#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e4
+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e5
+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e6
+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e7
+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e8
+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e9
+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07ea
+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07eb
+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07ec
+#define mmHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ed
+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ee
+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fb
+#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define mmHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fc
+#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define mmHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fd
+#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define mmHUBPREQ2_DST_DIMENSIONS                                                                      0x07fe
+#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
+#define mmHUBPREQ2_DST_AFTER_SCALER                                                                    0x07ff
+#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define mmHUBPREQ2_PREFETCH_SETTINGS                                                                   0x0800
+#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define mmHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0801
+#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0802
+#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0803
+#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0804
+#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0805
+#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0806
+#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define mmHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0807
+#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define mmHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0808
+#define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define mmHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0809
+#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define mmHUBPREQ2_NOM_PARAMETERS_0                                                                    0x080a
+#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define mmHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080b
+#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define mmHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080c
+#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define mmHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080d
+#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define mmHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080e
+#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define mmHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080f
+#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define mmHUBPREQ2_NOM_PARAMETERS_6                                                                    0x0810
+#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define mmHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0811
+#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0812
+#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define mmHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0813
+#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define mmHUBPREQ2_CURSOR_SETTINGS                                                                     0x0814
+#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0815
+#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0816
+#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0817
+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0818
+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081b
+#define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define mmHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081c
+#define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define mmHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081d
+#define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define mmHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081e
+#define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define mmHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081f
+#define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define mmHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x0820
+#define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
+// base address: 0x6e0
+#define mmHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
+#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
+#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
+#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define mmHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
+#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define mmHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
+#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define mmHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
+#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
+#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
+#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
+// base address: 0x6e0
+#define mmCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
+#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define mmCURSOR0_2_CURSOR_SIZE                                                                        0x0833
+#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
+#define mmCURSOR0_2_CURSOR_POSITION                                                                    0x0834
+#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
+#define mmCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
+#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define mmCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
+#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define mmCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
+#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
+#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
+#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
+#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define mmCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
+#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define mmCURSOR0_2_DMDATA_CNTL                                                                        0x083c
+#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
+#define mmCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
+#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define mmCURSOR0_2_DMDATA_STATUS                                                                      0x083e
+#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
+#define mmCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
+#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define mmCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
+#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x2154
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0855
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x0856
+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON8_PERFCOUNTER_STATE                                                                0x0857
+#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON8_PERFMON_CNTL                                                                     0x0858
+#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON8_PERFMON_CNTL2                                                                    0x0859
+#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x085a
+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x085b
+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON8_PERFMON_HI                                                                       0x085c
+#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON8_PERFMON_LOW                                                                      0x085d
+#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
+// base address: 0xa50
+#define mmHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
+#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define mmHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
+#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define mmHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
+#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define mmHUBP3_DCHUBP_CNTL                                                                            0x0887
+#define mmHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define mmHUBP3_HUBP_CLK_CNTL                                                                          0x0888
+#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define mmHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
+#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define mmHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088a
+#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define mmHUBP3_HUBPREQ_DEBUG                                                                          0x088b
+#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x088f
+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0890
+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
+// base address: 0xa50
+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define mmHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
+#define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
+#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b4
+#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b5
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b6
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b7
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b8
+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b9
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08ba
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08bb
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bc
+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define mmHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bd
+#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define mmHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08be
+#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08bf
+#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08c0
+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c1
+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c2
+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c3
+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c4
+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c5
+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c6
+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c7
+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define mmHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c8
+#define mmHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c9
+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08ca
+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d7
+#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define mmHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d8
+#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define mmHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d9
+#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define mmHUBPREQ3_DST_DIMENSIONS                                                                      0x08da
+#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
+#define mmHUBPREQ3_DST_AFTER_SCALER                                                                    0x08db
+#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define mmHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08dc
+#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define mmHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dd
+#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08de
+#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08df
+#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08e0
+#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e1
+#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define mmHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e3
+#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define mmHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e4
+#define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define mmHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e5
+#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define mmHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e6
+#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define mmHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e7
+#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define mmHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e8
+#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define mmHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e9
+#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define mmHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08ea
+#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define mmHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08eb
+#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define mmHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08ec
+#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define mmHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ed
+#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ee
+#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define mmHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ef
+#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define mmHUBPREQ3_CURSOR_SETTINGS                                                                     0x08f0
+#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f1
+#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f2
+#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f3
+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f4
+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f7
+#define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define mmHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f8
+#define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define mmHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f9
+#define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define mmHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08fa
+#define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define mmHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fb
+#define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define mmHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fc
+#define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
+// base address: 0xa50
+#define mmHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
+#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
+#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
+#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define mmHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
+#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define mmHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
+#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define mmHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
+#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
+#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
+#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
+// base address: 0xa50
+#define mmCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
+#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define mmCURSOR0_3_CURSOR_SIZE                                                                        0x090f
+#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
+#define mmCURSOR0_3_CURSOR_POSITION                                                                    0x0910
+#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
+#define mmCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
+#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define mmCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
+#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define mmCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
+#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
+#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
+#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
+#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define mmCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
+#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define mmCURSOR0_3_DMDATA_CNTL                                                                        0x0918
+#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
+#define mmCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
+#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define mmCURSOR0_3_DMDATA_STATUS                                                                      0x091a
+#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
+#define mmCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
+#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define mmCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
+#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x24c4
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0931
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0932
+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define mmDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0933
+#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define mmDC_PERFMON9_PERFMON_CNTL                                                                     0x0934
+#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2
+#define mmDC_PERFMON9_PERFMON_CNTL2                                                                    0x0935
+#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x0936
+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x0937
+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define mmDC_PERFMON9_PERFMON_HI                                                                       0x0938
+#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2
+#define mmDC_PERFMON9_PERFMON_LOW                                                                      0x0939
+#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+// base address: 0x0
+#define mmDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
+#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
+#define mmDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
+#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define mmDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
+#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define mmDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
+#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define mmDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
+#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define mmDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
+#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+// base address: 0x0
+#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
+#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define mmCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
+#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
+#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define mmCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
+#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define mmCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
+#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define mmCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
+#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define mmCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
+#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define mmCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
+#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define mmCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
+#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define mmCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
+#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define mmCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
+#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define mmCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
+#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define mmCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
+#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define mmCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
+#define mmCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
+#define mmCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
+#define mmCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
+#define mmCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
+#define mmCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
+#define mmCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
+#define mmCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
+#define mmCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
+#define mmCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
+#define mmCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define mmCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
+#define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define mmCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
+#define mmCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define mmCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
+#define mmCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define mmCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
+#define mmCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define mmCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
+#define mmCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define mmCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
+#define mmCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define mmCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
+#define mmCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define mmCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
+#define mmCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
+#define mmCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
+#define mmCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+// base address: 0x0
+#define mmCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
+#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define mmCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
+#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define mmCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
+#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
+#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+// base address: 0x0
+#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
+#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define mmDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
+#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define mmDSCL0_SCL_MODE                                                                               0x0cfb
+#define mmDSCL0_SCL_MODE_BASE_IDX                                                                      2
+#define mmDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
+#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define mmDSCL0_DSCL_CONTROL                                                                           0x0cfd
+#define mmDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
+#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
+#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
+#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
+#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
+#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define mmDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
+#define mmDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define mmDSCL0_DSCL_UPDATE                                                                            0x0d0b
+#define mmDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
+#define mmDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
+#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
+#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
+#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define mmDSCL0_OTG_H_BLANK                                                                            0x0d0f
+#define mmDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
+#define mmDSCL0_OTG_V_BLANK                                                                            0x0d10
+#define mmDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
+#define mmDSCL0_RECOUT_START                                                                           0x0d11
+#define mmDSCL0_RECOUT_START_BASE_IDX                                                                  2
+#define mmDSCL0_RECOUT_SIZE                                                                            0x0d12
+#define mmDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
+#define mmDSCL0_MPC_SIZE                                                                               0x0d13
+#define mmDSCL0_MPC_SIZE_BASE_IDX                                                                      2
+#define mmDSCL0_LB_DATA_FORMAT                                                                         0x0d14
+#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define mmDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
+#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define mmDSCL0_LB_V_COUNTER                                                                           0x0d16
+#define mmDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
+#define mmDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
+#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define mmDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
+#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define mmDSCL0_OBUF_CONTROL                                                                           0x0d19
+#define mmDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
+#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+// base address: 0x0
+#define mmCM0_CM_CONTROL                                                                               0x0d20
+#define mmCM0_CM_CONTROL_BASE_IDX                                                                      2
+#define mmCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
+#define mmCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
+#define mmCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
+#define mmCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
+#define mmCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
+#define mmCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
+#define mmCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
+#define mmCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define mmCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
+#define mmCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define mmCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
+#define mmCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define mmCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
+#define mmCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define mmCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
+#define mmCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define mmCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
+#define mmCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define mmCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
+#define mmCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define mmCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
+#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
+#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
+#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
+#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
+#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
+#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
+#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define mmCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
+#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define mmCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
+#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define mmCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
+#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define mmCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
+#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define mmCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
+#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define mmCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
+#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define mmCM0_CM_BIAS_CR_R                                                                             0x0d3b
+#define mmCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define mmCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
+#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define mmCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
+#define mmCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define mmCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
+#define mmCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
+#define mmCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define mmCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
+#define mmCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
+#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
+#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
+#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
+#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
+#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
+#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
+#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
+#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
+#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
+#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
+#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
+#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
+#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
+#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
+#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
+#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
+#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
+#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
+#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
+#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
+#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
+#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
+#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
+#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
+#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
+#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
+#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
+#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
+#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
+#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
+#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
+#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
+#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
+#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
+#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
+#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
+#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
+#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
+#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
+#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
+#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
+#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
+#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
+#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_CONTROL                                                                       0x0d87
+#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define mmCM0_CM_BLNDGAM_LUT_INDEX                                                                     0x0d88
+#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define mmCM0_CM_BLNDGAM_LUT_DATA                                                                      0x0d89
+#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define mmCM0_CM_BLNDGAM_LUT_CONTROL                                                                   0x0d8a
+#define mmCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0d8b
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0d8c
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0d8d
+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0d8e
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0d8f
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0d90
+#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0d91
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0d92
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0d93
+#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0d94
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0d95
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0d96
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0d97
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0d98
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0d99
+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0d9a
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0d9b
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0d9c
+#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0d9d
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0d9e
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0d9f
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0da0
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0da1
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0da2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0da3
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0da4
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0da5
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0da6
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0da7
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0da8
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0da9
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0daa
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0dab
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0dac
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0dad
+#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0dae
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0daf
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0db0
+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0db1
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0db2
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0db3
+#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0db4
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0db5
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0db6
+#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0db7
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0db8
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0db9
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0dba
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0dbb
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0dbc
+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0dbd
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0dbe
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0dbf
+#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0dc0
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0dc1
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0dc2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0dc3
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0dc4
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0dc5
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0dc6
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0dc7
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0dc8
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0dc9
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0dca
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0dcb
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0dcc
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0dcd
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0dce
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0dcf
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0dd0
+#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define mmCM0_CM_HDR_MULT_COEF                                                                         0x0dd1
+#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define mmCM0_CM_MEM_PWR_CTRL                                                                          0x0dd2
+#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define mmCM0_CM_MEM_PWR_STATUS                                                                        0x0dd3
+#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define mmCM0_CM_DEALPHA                                                                               0x0dd5
+#define mmCM0_CM_DEALPHA_BASE_IDX                                                                      2
+#define mmCM0_CM_COEF_FORMAT                                                                           0x0dd6
+#define mmCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define mmCM0_CM_SHAPER_CONTROL                                                                        0x0dd7
+#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define mmCM0_CM_SHAPER_OFFSET_R                                                                       0x0dd8
+#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define mmCM0_CM_SHAPER_OFFSET_G                                                                       0x0dd9
+#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define mmCM0_CM_SHAPER_OFFSET_B                                                                       0x0dda
+#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define mmCM0_CM_SHAPER_SCALE_R                                                                        0x0ddb
+#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define mmCM0_CM_SHAPER_SCALE_G_B                                                                      0x0ddc
+#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define mmCM0_CM_SHAPER_LUT_INDEX                                                                      0x0ddd
+#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM0_CM_SHAPER_LUT_DATA                                                                       0x0dde
+#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0ddf
+#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0de0
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0de1
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0de2
+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0de3
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0de4
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0de5
+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_0_1                                                                0x0de6
+#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_2_3                                                                0x0de7
+#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_4_5                                                                0x0de8
+#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_6_7                                                                0x0de9
+#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_8_9                                                                0x0dea
+#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMA_REGION_10_11                                                              0x0deb
+#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_12_13                                                              0x0dec
+#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_14_15                                                              0x0ded
+#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_16_17                                                              0x0dee
+#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_18_19                                                              0x0def
+#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_20_21                                                              0x0df0
+#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_22_23                                                              0x0df1
+#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_24_25                                                              0x0df2
+#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_26_27                                                              0x0df3
+#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_28_29                                                              0x0df4
+#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_30_31                                                              0x0df5
+#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMA_REGION_32_33                                                              0x0df6
+#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0df7
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0df8
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0df9
+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0dfa
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0dfb
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0dfc
+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_0_1                                                                0x0dfd
+#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_2_3                                                                0x0dfe
+#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_4_5                                                                0x0dff
+#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_6_7                                                                0x0e00
+#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_8_9                                                                0x0e01
+#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM0_CM_SHAPER_RAMB_REGION_10_11                                                              0x0e02
+#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_12_13                                                              0x0e03
+#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_14_15                                                              0x0e04
+#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_16_17                                                              0x0e05
+#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_18_19                                                              0x0e06
+#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_20_21                                                              0x0e07
+#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_22_23                                                              0x0e08
+#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_24_25                                                              0x0e09
+#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_26_27                                                              0x0e0a
+#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_28_29                                                              0x0e0b
+#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_30_31                                                              0x0e0c
+#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM0_CM_SHAPER_RAMB_REGION_32_33                                                              0x0e0d
+#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM0_CM_MEM_PWR_CTRL2                                                                         0x0e0e
+#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define mmCM0_CM_MEM_PWR_STATUS2                                                                       0x0e0f
+#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define mmCM0_CM_3DLUT_MODE                                                                            0x0e10
+#define mmCM0_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define mmCM0_CM_3DLUT_INDEX                                                                           0x0e11
+#define mmCM0_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define mmCM0_CM_3DLUT_DATA                                                                            0x0e12
+#define mmCM0_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define mmCM0_CM_3DLUT_DATA_30BIT                                                                      0x0e13
+#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0e14
+#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0e15
+#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define mmCM0_CM_3DLUT_OUT_OFFSET_R                                                                    0x0e16
+#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define mmCM0_CM_3DLUT_OUT_OFFSET_G                                                                    0x0e17
+#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define mmCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0e18
+#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define mmCM0_CM_TEST_DEBUG_INDEX                                                                      0x0e19
+#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define mmCM0_CM_TEST_DEBUG_DATA                                                                       0x0e1a
+#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x3890
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x0e24
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x0e25
+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON10_PERFCOUNTER_STATE                                                               0x0e26
+#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON10_PERFMON_CNTL                                                                    0x0e27
+#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON10_PERFMON_CNTL2                                                                   0x0e28
+#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x0e29
+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x0e2a
+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON10_PERFMON_HI                                                                      0x0e2b
+#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON10_PERFMON_LOW                                                                     0x0e2c
+#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+// base address: 0x5ac
+#define mmDPP_TOP1_DPP_CONTROL                                                                         0x0e30
+#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
+#define mmDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
+#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define mmDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
+#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define mmDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
+#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define mmDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
+#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define mmDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
+#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+// base address: 0x5ac
+#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
+#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define mmCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
+#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
+#define mmCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
+#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define mmCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
+#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define mmCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
+#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define mmCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
+#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define mmCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
+#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define mmCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
+#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define mmCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
+#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define mmCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
+#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define mmCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
+#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define mmCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
+#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define mmCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
+#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define mmCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
+#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define mmCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
+#define mmCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
+#define mmCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
+#define mmCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
+#define mmCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
+#define mmCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
+#define mmCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
+#define mmCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
+#define mmCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
+#define mmCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
+#define mmCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define mmCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
+#define mmCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define mmCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
+#define mmCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define mmCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
+#define mmCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define mmCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
+#define mmCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define mmCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
+#define mmCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define mmCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
+#define mmCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define mmCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
+#define mmCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define mmCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
+#define mmCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
+#define mmCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
+#define mmCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+// base address: 0x5ac
+#define mmCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
+#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define mmCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
+#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define mmCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
+#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
+#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+// base address: 0x5ac
+#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
+#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define mmDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
+#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define mmDSCL1_SCL_MODE                                                                               0x0e66
+#define mmDSCL1_SCL_MODE_BASE_IDX                                                                      2
+#define mmDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
+#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define mmDSCL1_DSCL_CONTROL                                                                           0x0e68
+#define mmDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
+#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
+#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
+#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
+#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
+#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define mmDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
+#define mmDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define mmDSCL1_DSCL_UPDATE                                                                            0x0e76
+#define mmDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
+#define mmDSCL1_DSCL_AUTOCAL                                                                           0x0e77
+#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
+#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
+#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define mmDSCL1_OTG_H_BLANK                                                                            0x0e7a
+#define mmDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
+#define mmDSCL1_OTG_V_BLANK                                                                            0x0e7b
+#define mmDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
+#define mmDSCL1_RECOUT_START                                                                           0x0e7c
+#define mmDSCL1_RECOUT_START_BASE_IDX                                                                  2
+#define mmDSCL1_RECOUT_SIZE                                                                            0x0e7d
+#define mmDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
+#define mmDSCL1_MPC_SIZE                                                                               0x0e7e
+#define mmDSCL1_MPC_SIZE_BASE_IDX                                                                      2
+#define mmDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
+#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define mmDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
+#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define mmDSCL1_LB_V_COUNTER                                                                           0x0e81
+#define mmDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
+#define mmDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
+#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define mmDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
+#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define mmDSCL1_OBUF_CONTROL                                                                           0x0e84
+#define mmDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
+#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+// base address: 0x5ac
+#define mmCM1_CM_CONTROL                                                                               0x0e8b
+#define mmCM1_CM_CONTROL_BASE_IDX                                                                      2
+#define mmCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
+#define mmCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
+#define mmCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
+#define mmCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
+#define mmCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
+#define mmCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
+#define mmCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
+#define mmCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define mmCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
+#define mmCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define mmCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
+#define mmCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define mmCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
+#define mmCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define mmCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
+#define mmCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define mmCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
+#define mmCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define mmCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
+#define mmCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define mmCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
+#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
+#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
+#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
+#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
+#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
+#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
+#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define mmCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
+#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define mmCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
+#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define mmCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
+#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define mmCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
+#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define mmCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
+#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define mmCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
+#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define mmCM1_CM_BIAS_CR_R                                                                             0x0ea6
+#define mmCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define mmCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
+#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define mmCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
+#define mmCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define mmCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
+#define mmCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
+#define mmCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define mmCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
+#define mmCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
+#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
+#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
+#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
+#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
+#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
+#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
+#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
+#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
+#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
+#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
+#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
+#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
+#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
+#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
+#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
+#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
+#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
+#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
+#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
+#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
+#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
+#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
+#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
+#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
+#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
+#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
+#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
+#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
+#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
+#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
+#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
+#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
+#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
+#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
+#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
+#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
+#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
+#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
+#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
+#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
+#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
+#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_CONTROL                                                                       0x0ef2
+#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define mmCM1_CM_BLNDGAM_LUT_INDEX                                                                     0x0ef3
+#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define mmCM1_CM_BLNDGAM_LUT_DATA                                                                      0x0ef4
+#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define mmCM1_CM_BLNDGAM_LUT_CONTROL                                                                   0x0ef5
+#define mmCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0ef6
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0ef7
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0ef8
+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0ef9
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0efa
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0efb
+#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0efc
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0efd
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0efe
+#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0eff
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0f00
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0f01
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0f02
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0f03
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0f04
+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0f05
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0f06
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0f07
+#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0f08
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0f09
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0f0a
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0f0b
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0f0c
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0f0d
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0f0e
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0f0f
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0f10
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0f11
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0f12
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0f13
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0f14
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0f15
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0f16
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0f17
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0f18
+#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0f19
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0f1a
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0f1b
+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0f1c
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0f1d
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0f1e
+#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0f1f
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0f20
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0f21
+#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0f22
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0f23
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0f24
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0f25
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0f26
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0f27
+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0f28
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0f29
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0f2a
+#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0f2b
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0f2c
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0f2d
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0f2e
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0f2f
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0f30
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0f31
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0f32
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0f33
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0f34
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0f35
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0f36
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0f37
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0f38
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0f39
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0f3a
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0f3b
+#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define mmCM1_CM_HDR_MULT_COEF                                                                         0x0f3c
+#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define mmCM1_CM_MEM_PWR_CTRL                                                                          0x0f3d
+#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define mmCM1_CM_MEM_PWR_STATUS                                                                        0x0f3e
+#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define mmCM1_CM_DEALPHA                                                                               0x0f40
+#define mmCM1_CM_DEALPHA_BASE_IDX                                                                      2
+#define mmCM1_CM_COEF_FORMAT                                                                           0x0f41
+#define mmCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define mmCM1_CM_SHAPER_CONTROL                                                                        0x0f42
+#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define mmCM1_CM_SHAPER_OFFSET_R                                                                       0x0f43
+#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define mmCM1_CM_SHAPER_OFFSET_G                                                                       0x0f44
+#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define mmCM1_CM_SHAPER_OFFSET_B                                                                       0x0f45
+#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define mmCM1_CM_SHAPER_SCALE_R                                                                        0x0f46
+#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define mmCM1_CM_SHAPER_SCALE_G_B                                                                      0x0f47
+#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define mmCM1_CM_SHAPER_LUT_INDEX                                                                      0x0f48
+#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM1_CM_SHAPER_LUT_DATA                                                                       0x0f49
+#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0f4a
+#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0f4b
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0f4c
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0f4d
+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0f4e
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0f4f
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0f50
+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_0_1                                                                0x0f51
+#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_2_3                                                                0x0f52
+#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_4_5                                                                0x0f53
+#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_6_7                                                                0x0f54
+#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_8_9                                                                0x0f55
+#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMA_REGION_10_11                                                              0x0f56
+#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_12_13                                                              0x0f57
+#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_14_15                                                              0x0f58
+#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_16_17                                                              0x0f59
+#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_18_19                                                              0x0f5a
+#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_20_21                                                              0x0f5b
+#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_22_23                                                              0x0f5c
+#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_24_25                                                              0x0f5d
+#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_26_27                                                              0x0f5e
+#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_28_29                                                              0x0f5f
+#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_30_31                                                              0x0f60
+#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMA_REGION_32_33                                                              0x0f61
+#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0f62
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0f63
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0f64
+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0f65
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0f66
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0f67
+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_0_1                                                                0x0f68
+#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_2_3                                                                0x0f69
+#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_4_5                                                                0x0f6a
+#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_6_7                                                                0x0f6b
+#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_8_9                                                                0x0f6c
+#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM1_CM_SHAPER_RAMB_REGION_10_11                                                              0x0f6d
+#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_12_13                                                              0x0f6e
+#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_14_15                                                              0x0f6f
+#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_16_17                                                              0x0f70
+#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_18_19                                                              0x0f71
+#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_20_21                                                              0x0f72
+#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_22_23                                                              0x0f73
+#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_24_25                                                              0x0f74
+#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_26_27                                                              0x0f75
+#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_28_29                                                              0x0f76
+#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_30_31                                                              0x0f77
+#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM1_CM_SHAPER_RAMB_REGION_32_33                                                              0x0f78
+#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM1_CM_MEM_PWR_CTRL2                                                                         0x0f79
+#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define mmCM1_CM_MEM_PWR_STATUS2                                                                       0x0f7a
+#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define mmCM1_CM_3DLUT_MODE                                                                            0x0f7b
+#define mmCM1_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define mmCM1_CM_3DLUT_INDEX                                                                           0x0f7c
+#define mmCM1_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define mmCM1_CM_3DLUT_DATA                                                                            0x0f7d
+#define mmCM1_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define mmCM1_CM_3DLUT_DATA_30BIT                                                                      0x0f7e
+#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0f7f
+#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0f80
+#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define mmCM1_CM_3DLUT_OUT_OFFSET_R                                                                    0x0f81
+#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define mmCM1_CM_3DLUT_OUT_OFFSET_G                                                                    0x0f82
+#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define mmCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f83
+#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define mmCM1_CM_TEST_DEBUG_INDEX                                                                      0x0f84
+#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define mmCM1_CM_TEST_DEBUG_DATA                                                                       0x0f85
+#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x3e3c
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x0f8f
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x0f90
+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON11_PERFCOUNTER_STATE                                                               0x0f91
+#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON11_PERFMON_CNTL                                                                    0x0f92
+#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON11_PERFMON_CNTL2                                                                   0x0f93
+#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x0f94
+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x0f95
+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON11_PERFMON_HI                                                                      0x0f96
+#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON11_PERFMON_LOW                                                                     0x0f97
+#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
+// base address: 0xb58
+#define mmDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
+#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
+#define mmDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
+#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define mmDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
+#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define mmDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
+#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define mmDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
+#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define mmDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
+#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
+// base address: 0xb58
+#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
+#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define mmCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
+#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
+#define mmCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
+#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define mmCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
+#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define mmCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
+#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define mmCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
+#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define mmCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
+#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define mmCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
+#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define mmCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
+#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define mmCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
+#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define mmCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
+#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define mmCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
+#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define mmCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
+#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define mmCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
+#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define mmCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4
+#define mmCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2
+#define mmCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5
+#define mmCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2
+#define mmCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6
+#define mmCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define mmCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7
+#define mmCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define mmCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8
+#define mmCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define mmCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9
+#define mmCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define mmCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba
+#define mmCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define mmCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb
+#define mmCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define mmCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc
+#define mmCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define mmCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd
+#define mmCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define mmCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe
+#define mmCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define mmCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf
+#define mmCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define mmCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0
+#define mmCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define mmCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1
+#define mmCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define mmCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2
+#define mmCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define mmCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3
+#define mmCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2
+#define mmCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4
+#define mmCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
+// base address: 0xb58
+#define mmCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7
+#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define mmCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8
+#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define mmCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9
+#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca
+#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
+// base address: 0xb58
+#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf
+#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define mmDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0
+#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define mmDSCL2_SCL_MODE                                                                               0x0fd1
+#define mmDSCL2_SCL_MODE_BASE_IDX                                                                      2
+#define mmDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2
+#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define mmDSCL2_DSCL_CONTROL                                                                           0x0fd3
+#define mmDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4
+#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5
+#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6
+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7
+#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8
+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9
+#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda
+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb
+#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc
+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd
+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde
+#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf
+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define mmDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0
+#define mmDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define mmDSCL2_DSCL_UPDATE                                                                            0x0fe1
+#define mmDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
+#define mmDSCL2_DSCL_AUTOCAL                                                                           0x0fe2
+#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3
+#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4
+#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define mmDSCL2_OTG_H_BLANK                                                                            0x0fe5
+#define mmDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
+#define mmDSCL2_OTG_V_BLANK                                                                            0x0fe6
+#define mmDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
+#define mmDSCL2_RECOUT_START                                                                           0x0fe7
+#define mmDSCL2_RECOUT_START_BASE_IDX                                                                  2
+#define mmDSCL2_RECOUT_SIZE                                                                            0x0fe8
+#define mmDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
+#define mmDSCL2_MPC_SIZE                                                                               0x0fe9
+#define mmDSCL2_MPC_SIZE_BASE_IDX                                                                      2
+#define mmDSCL2_LB_DATA_FORMAT                                                                         0x0fea
+#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define mmDSCL2_LB_MEMORY_CTRL                                                                         0x0feb
+#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define mmDSCL2_LB_V_COUNTER                                                                           0x0fec
+#define mmDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
+#define mmDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed
+#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define mmDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee
+#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define mmDSCL2_OBUF_CONTROL                                                                           0x0fef
+#define mmDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0
+#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
+// base address: 0xb58
+#define mmCM2_CM_CONTROL                                                                               0x0ff6
+#define mmCM2_CM_CONTROL_BASE_IDX                                                                      2
+#define mmCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7
+#define mmCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define mmCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8
+#define mmCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define mmCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9
+#define mmCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define mmCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa
+#define mmCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define mmCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb
+#define mmCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define mmCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc
+#define mmCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define mmCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd
+#define mmCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define mmCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe
+#define mmCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define mmCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff
+#define mmCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define mmCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000
+#define mmCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define mmCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001
+#define mmCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define mmCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002
+#define mmCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define mmCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003
+#define mmCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define mmCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004
+#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define mmCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005
+#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define mmCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006
+#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define mmCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007
+#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define mmCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008
+#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define mmCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009
+#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define mmCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a
+#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define mmCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b
+#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define mmCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c
+#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define mmCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d
+#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define mmCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e
+#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define mmCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f
+#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define mmCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010
+#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define mmCM2_CM_BIAS_CR_R                                                                             0x1011
+#define mmCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define mmCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012
+#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define mmCM2_CM_GAMCOR_CONTROL                                                                        0x1013
+#define mmCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define mmCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014
+#define mmCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015
+#define mmCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define mmCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016
+#define mmCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017
+#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018
+#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019
+#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a
+#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b
+#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c
+#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d
+#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e
+#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f
+#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025
+#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026
+#define mmCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define mmCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027
+#define mmCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define mmCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028
+#define mmCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029
+#define mmCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a
+#define mmCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b
+#define mmCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c
+#define mmCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d
+#define mmCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e
+#define mmCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f
+#define mmCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030
+#define mmCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031
+#define mmCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032
+#define mmCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033
+#define mmCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034
+#define mmCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035
+#define mmCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036
+#define mmCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037
+#define mmCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038
+#define mmCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039
+#define mmCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a
+#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b
+#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c
+#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d
+#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e
+#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f
+#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040
+#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041
+#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042
+#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048
+#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049
+#define mmCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define mmCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a
+#define mmCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define mmCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b
+#define mmCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c
+#define mmCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d
+#define mmCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e
+#define mmCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f
+#define mmCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050
+#define mmCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051
+#define mmCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052
+#define mmCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053
+#define mmCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054
+#define mmCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055
+#define mmCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056
+#define mmCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057
+#define mmCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058
+#define mmCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059
+#define mmCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a
+#define mmCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b
+#define mmCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c
+#define mmCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_CONTROL                                                                       0x105d
+#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define mmCM2_CM_BLNDGAM_LUT_INDEX                                                                     0x105e
+#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define mmCM2_CM_BLNDGAM_LUT_DATA                                                                      0x105f
+#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define mmCM2_CM_BLNDGAM_LUT_CONTROL                                                                   0x1060
+#define mmCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x1061
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x1062
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x1063
+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x1064
+#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x1065
+#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x1066
+#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x1067
+#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x1068
+#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x1069
+#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x106a
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x106b
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x106c
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x106d
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x106e
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x106f
+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x1070
+#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x1071
+#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x1072
+#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x1073
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x1074
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x1075
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x1076
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x1077
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x1078
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x1079
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x107a
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x107b
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x107c
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x107d
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x107e
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x107f
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x1080
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x1081
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x1082
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x1083
+#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x1084
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x1085
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x1086
+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x1087
+#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x1088
+#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x1089
+#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x108a
+#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x108b
+#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x108c
+#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x108d
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x108e
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x108f
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x1090
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x1091
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x1092
+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x1093
+#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x1094
+#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x1095
+#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1096
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1097
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1098
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1099
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x109a
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x109b
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x109c
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x109d
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x109e
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x109f
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x10a0
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x10a1
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x10a2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x10a3
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x10a4
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x10a5
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x10a6
+#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define mmCM2_CM_HDR_MULT_COEF                                                                         0x10a7
+#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define mmCM2_CM_MEM_PWR_CTRL                                                                          0x10a8
+#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define mmCM2_CM_MEM_PWR_STATUS                                                                        0x10a9
+#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define mmCM2_CM_DEALPHA                                                                               0x10ab
+#define mmCM2_CM_DEALPHA_BASE_IDX                                                                      2
+#define mmCM2_CM_COEF_FORMAT                                                                           0x10ac
+#define mmCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define mmCM2_CM_SHAPER_CONTROL                                                                        0x10ad
+#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define mmCM2_CM_SHAPER_OFFSET_R                                                                       0x10ae
+#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define mmCM2_CM_SHAPER_OFFSET_G                                                                       0x10af
+#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define mmCM2_CM_SHAPER_OFFSET_B                                                                       0x10b0
+#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define mmCM2_CM_SHAPER_SCALE_R                                                                        0x10b1
+#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define mmCM2_CM_SHAPER_SCALE_G_B                                                                      0x10b2
+#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define mmCM2_CM_SHAPER_LUT_INDEX                                                                      0x10b3
+#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM2_CM_SHAPER_LUT_DATA                                                                       0x10b4
+#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x10b5
+#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B                                                              0x10b6
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G                                                              0x10b7
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R                                                              0x10b8
+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B                                                                0x10b9
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G                                                                0x10ba
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R                                                                0x10bb
+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMA_REGION_0_1                                                                0x10bc
+#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMA_REGION_2_3                                                                0x10bd
+#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMA_REGION_4_5                                                                0x10be
+#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMA_REGION_6_7                                                                0x10bf
+#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMA_REGION_8_9                                                                0x10c0
+#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMA_REGION_10_11                                                              0x10c1
+#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_REGION_12_13                                                              0x10c2
+#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_REGION_14_15                                                              0x10c3
+#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_REGION_16_17                                                              0x10c4
+#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_REGION_18_19                                                              0x10c5
+#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_REGION_20_21                                                              0x10c6
+#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_REGION_22_23                                                              0x10c7
+#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_REGION_24_25                                                              0x10c8
+#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_REGION_26_27                                                              0x10c9
+#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_REGION_28_29                                                              0x10ca
+#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_REGION_30_31                                                              0x10cb
+#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMA_REGION_32_33                                                              0x10cc
+#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B                                                              0x10cd
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G                                                              0x10ce
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R                                                              0x10cf
+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B                                                                0x10d0
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G                                                                0x10d1
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R                                                                0x10d2
+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMB_REGION_0_1                                                                0x10d3
+#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMB_REGION_2_3                                                                0x10d4
+#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMB_REGION_4_5                                                                0x10d5
+#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMB_REGION_6_7                                                                0x10d6
+#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMB_REGION_8_9                                                                0x10d7
+#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM2_CM_SHAPER_RAMB_REGION_10_11                                                              0x10d8
+#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_REGION_12_13                                                              0x10d9
+#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_REGION_14_15                                                              0x10da
+#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_REGION_16_17                                                              0x10db
+#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_REGION_18_19                                                              0x10dc
+#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_REGION_20_21                                                              0x10dd
+#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_REGION_22_23                                                              0x10de
+#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_REGION_24_25                                                              0x10df
+#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_REGION_26_27                                                              0x10e0
+#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_REGION_28_29                                                              0x10e1
+#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_REGION_30_31                                                              0x10e2
+#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM2_CM_SHAPER_RAMB_REGION_32_33                                                              0x10e3
+#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM2_CM_MEM_PWR_CTRL2                                                                         0x10e4
+#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define mmCM2_CM_MEM_PWR_STATUS2                                                                       0x10e5
+#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define mmCM2_CM_3DLUT_MODE                                                                            0x10e6
+#define mmCM2_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define mmCM2_CM_3DLUT_INDEX                                                                           0x10e7
+#define mmCM2_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define mmCM2_CM_3DLUT_DATA                                                                            0x10e8
+#define mmCM2_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define mmCM2_CM_3DLUT_DATA_30BIT                                                                      0x10e9
+#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL                                                              0x10ea
+#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x10eb
+#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define mmCM2_CM_3DLUT_OUT_OFFSET_R                                                                    0x10ec
+#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define mmCM2_CM_3DLUT_OUT_OFFSET_G                                                                    0x10ed
+#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define mmCM2_CM_3DLUT_OUT_OFFSET_B                                                                    0x10ee
+#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define mmCM2_CM_TEST_DEBUG_INDEX                                                                      0x10ef
+#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define mmCM2_CM_TEST_DEBUG_DATA                                                                       0x10f0
+#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x43e8
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x10fa
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x10fb
+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON12_PERFCOUNTER_STATE                                                               0x10fc
+#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON12_PERFMON_CNTL                                                                    0x10fd
+#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON12_PERFMON_CNTL2                                                                   0x10fe
+#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x10ff
+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x1100
+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON12_PERFMON_HI                                                                      0x1101
+#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON12_PERFMON_LOW                                                                     0x1102
+#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
+// base address: 0x1104
+#define mmDPP_TOP3_DPP_CONTROL                                                                         0x1106
+#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
+#define mmDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
+#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define mmDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
+#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define mmDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
+#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define mmDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
+#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define mmDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
+#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
+// base address: 0x1104
+#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
+#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define mmCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
+#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
+#define mmCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
+#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define mmCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
+#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define mmCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
+#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define mmCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
+#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define mmCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
+#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define mmCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
+#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define mmCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
+#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define mmCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
+#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define mmCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
+#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define mmCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
+#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define mmCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
+#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define mmCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
+#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define mmCNVC_CFG3_PRE_DEALPHA                                                                        0x111f
+#define mmCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2
+#define mmCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120
+#define mmCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2
+#define mmCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121
+#define mmCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define mmCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122
+#define mmCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define mmCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123
+#define mmCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define mmCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124
+#define mmCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define mmCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125
+#define mmCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define mmCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126
+#define mmCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define mmCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127
+#define mmCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define mmCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128
+#define mmCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define mmCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129
+#define mmCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define mmCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a
+#define mmCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define mmCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b
+#define mmCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define mmCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c
+#define mmCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define mmCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d
+#define mmCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define mmCNVC_CFG3_PRE_DEGAM                                                                          0x112e
+#define mmCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2
+#define mmCNVC_CFG3_PRE_REALPHA                                                                        0x112f
+#define mmCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
+// base address: 0x1104
+#define mmCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132
+#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define mmCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133
+#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define mmCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134
+#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135
+#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
+// base address: 0x1104
+#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a
+#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define mmDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b
+#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define mmDSCL3_SCL_MODE                                                                               0x113c
+#define mmDSCL3_SCL_MODE_BASE_IDX                                                                      2
+#define mmDSCL3_SCL_TAP_CONTROL                                                                        0x113d
+#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define mmDSCL3_DSCL_CONTROL                                                                           0x113e
+#define mmDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f
+#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140
+#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141
+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142
+#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143
+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144
+#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145
+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define mmDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146
+#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147
+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148
+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define mmDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149
+#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a
+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define mmDSCL3_SCL_BLACK_COLOR                                                                        0x114b
+#define mmDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define mmDSCL3_DSCL_UPDATE                                                                            0x114c
+#define mmDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
+#define mmDSCL3_DSCL_AUTOCAL                                                                           0x114d
+#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e
+#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f
+#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define mmDSCL3_OTG_H_BLANK                                                                            0x1150
+#define mmDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
+#define mmDSCL3_OTG_V_BLANK                                                                            0x1151
+#define mmDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
+#define mmDSCL3_RECOUT_START                                                                           0x1152
+#define mmDSCL3_RECOUT_START_BASE_IDX                                                                  2
+#define mmDSCL3_RECOUT_SIZE                                                                            0x1153
+#define mmDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
+#define mmDSCL3_MPC_SIZE                                                                               0x1154
+#define mmDSCL3_MPC_SIZE_BASE_IDX                                                                      2
+#define mmDSCL3_LB_DATA_FORMAT                                                                         0x1155
+#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define mmDSCL3_LB_MEMORY_CTRL                                                                         0x1156
+#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define mmDSCL3_LB_V_COUNTER                                                                           0x1157
+#define mmDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
+#define mmDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158
+#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define mmDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159
+#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define mmDSCL3_OBUF_CONTROL                                                                           0x115a
+#define mmDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
+#define mmDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b
+#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
+// base address: 0x1104
+#define mmCM3_CM_CONTROL                                                                               0x1161
+#define mmCM3_CM_CONTROL_BASE_IDX                                                                      2
+#define mmCM3_CM_POST_CSC_CONTROL                                                                      0x1162
+#define mmCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define mmCM3_CM_POST_CSC_C11_C12                                                                      0x1163
+#define mmCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define mmCM3_CM_POST_CSC_C13_C14                                                                      0x1164
+#define mmCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define mmCM3_CM_POST_CSC_C21_C22                                                                      0x1165
+#define mmCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define mmCM3_CM_POST_CSC_C23_C24                                                                      0x1166
+#define mmCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define mmCM3_CM_POST_CSC_C31_C32                                                                      0x1167
+#define mmCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define mmCM3_CM_POST_CSC_C33_C34                                                                      0x1168
+#define mmCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define mmCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169
+#define mmCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define mmCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a
+#define mmCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define mmCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b
+#define mmCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define mmCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c
+#define mmCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define mmCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d
+#define mmCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define mmCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e
+#define mmCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define mmCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f
+#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define mmCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170
+#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define mmCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171
+#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define mmCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172
+#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define mmCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173
+#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define mmCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174
+#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define mmCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175
+#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define mmCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176
+#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define mmCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177
+#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define mmCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178
+#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define mmCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179
+#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define mmCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a
+#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define mmCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b
+#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define mmCM3_CM_BIAS_CR_R                                                                             0x117c
+#define mmCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define mmCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d
+#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define mmCM3_CM_GAMCOR_CONTROL                                                                        0x117e
+#define mmCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define mmCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f
+#define mmCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180
+#define mmCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define mmCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181
+#define mmCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182
+#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183
+#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184
+#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185
+#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186
+#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187
+#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188
+#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189
+#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a
+#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190
+#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191
+#define mmCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define mmCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192
+#define mmCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define mmCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193
+#define mmCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194
+#define mmCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195
+#define mmCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196
+#define mmCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197
+#define mmCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198
+#define mmCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199
+#define mmCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a
+#define mmCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b
+#define mmCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c
+#define mmCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d
+#define mmCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e
+#define mmCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f
+#define mmCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0
+#define mmCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1
+#define mmCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3
+#define mmCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4
+#define mmCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5
+#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6
+#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7
+#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8
+#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9
+#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa
+#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab
+#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac
+#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad
+#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3
+#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define mmCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4
+#define mmCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define mmCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5
+#define mmCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define mmCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6
+#define mmCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7
+#define mmCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8
+#define mmCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9
+#define mmCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba
+#define mmCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb
+#define mmCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc
+#define mmCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd
+#define mmCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be
+#define mmCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf
+#define mmCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0
+#define mmCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1
+#define mmCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3
+#define mmCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4
+#define mmCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5
+#define mmCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6
+#define mmCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7
+#define mmCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_CONTROL                                                                       0x11c8
+#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define mmCM3_CM_BLNDGAM_LUT_INDEX                                                                     0x11c9
+#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define mmCM3_CM_BLNDGAM_LUT_DATA                                                                      0x11ca
+#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define mmCM3_CM_BLNDGAM_LUT_CONTROL                                                                   0x11cb
+#define mmCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x11cc
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x11cd
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x11ce
+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x11cf
+#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x11d0
+#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x11d1
+#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x11d2
+#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x11d3
+#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x11d4
+#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x11d5
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x11d6
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x11d7
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x11d8
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x11d9
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x11da
+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x11db
+#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x11dc
+#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x11dd
+#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x11de
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x11df
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x11e0
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x11e1
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x11e2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x11e3
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x11e4
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x11e5
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x11e6
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x11e7
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x11e8
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x11e9
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x11ea
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x11eb
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x11ec
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x11ed
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x11ee
+#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x11ef
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x11f0
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x11f1
+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x11f2
+#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x11f3
+#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x11f4
+#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x11f5
+#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x11f6
+#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x11f7
+#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x11f8
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x11f9
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x11fa
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x11fb
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x11fc
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x11fd
+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x11fe
+#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x11ff
+#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x1200
+#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1201
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1202
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1203
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1204
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x1205
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x1206
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x1207
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x1208
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x1209
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x120a
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x120b
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x120c
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x120d
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x120e
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x120f
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x1210
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x1211
+#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define mmCM3_CM_HDR_MULT_COEF                                                                         0x1212
+#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define mmCM3_CM_MEM_PWR_CTRL                                                                          0x1213
+#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define mmCM3_CM_MEM_PWR_STATUS                                                                        0x1214
+#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define mmCM3_CM_DEALPHA                                                                               0x1216
+#define mmCM3_CM_DEALPHA_BASE_IDX                                                                      2
+#define mmCM3_CM_COEF_FORMAT                                                                           0x1217
+#define mmCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define mmCM3_CM_SHAPER_CONTROL                                                                        0x1218
+#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define mmCM3_CM_SHAPER_OFFSET_R                                                                       0x1219
+#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define mmCM3_CM_SHAPER_OFFSET_G                                                                       0x121a
+#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define mmCM3_CM_SHAPER_OFFSET_B                                                                       0x121b
+#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define mmCM3_CM_SHAPER_SCALE_R                                                                        0x121c
+#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define mmCM3_CM_SHAPER_SCALE_G_B                                                                      0x121d
+#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define mmCM3_CM_SHAPER_LUT_INDEX                                                                      0x121e
+#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define mmCM3_CM_SHAPER_LUT_DATA                                                                       0x121f
+#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x1220
+#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B                                                              0x1221
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G                                                              0x1222
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R                                                              0x1223
+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B                                                                0x1224
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G                                                                0x1225
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R                                                                0x1226
+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMA_REGION_0_1                                                                0x1227
+#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMA_REGION_2_3                                                                0x1228
+#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMA_REGION_4_5                                                                0x1229
+#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMA_REGION_6_7                                                                0x122a
+#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMA_REGION_8_9                                                                0x122b
+#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMA_REGION_10_11                                                              0x122c
+#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_REGION_12_13                                                              0x122d
+#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_REGION_14_15                                                              0x122e
+#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_REGION_16_17                                                              0x122f
+#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_REGION_18_19                                                              0x1230
+#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_REGION_20_21                                                              0x1231
+#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_REGION_22_23                                                              0x1232
+#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_REGION_24_25                                                              0x1233
+#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_REGION_26_27                                                              0x1234
+#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_REGION_28_29                                                              0x1235
+#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_REGION_30_31                                                              0x1236
+#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMA_REGION_32_33                                                              0x1237
+#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B                                                              0x1238
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G                                                              0x1239
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R                                                              0x123a
+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B                                                                0x123b
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G                                                                0x123c
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R                                                                0x123d
+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMB_REGION_0_1                                                                0x123e
+#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMB_REGION_2_3                                                                0x123f
+#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMB_REGION_4_5                                                                0x1240
+#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMB_REGION_6_7                                                                0x1241
+#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMB_REGION_8_9                                                                0x1242
+#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define mmCM3_CM_SHAPER_RAMB_REGION_10_11                                                              0x1243
+#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_REGION_12_13                                                              0x1244
+#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_REGION_14_15                                                              0x1245
+#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_REGION_16_17                                                              0x1246
+#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_REGION_18_19                                                              0x1247
+#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_REGION_20_21                                                              0x1248
+#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_REGION_22_23                                                              0x1249
+#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_REGION_24_25                                                              0x124a
+#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_REGION_26_27                                                              0x124b
+#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_REGION_28_29                                                              0x124c
+#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_REGION_30_31                                                              0x124d
+#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define mmCM3_CM_SHAPER_RAMB_REGION_32_33                                                              0x124e
+#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define mmCM3_CM_MEM_PWR_CTRL2                                                                         0x124f
+#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define mmCM3_CM_MEM_PWR_STATUS2                                                                       0x1250
+#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define mmCM3_CM_3DLUT_MODE                                                                            0x1251
+#define mmCM3_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define mmCM3_CM_3DLUT_INDEX                                                                           0x1252
+#define mmCM3_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define mmCM3_CM_3DLUT_DATA                                                                            0x1253
+#define mmCM3_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define mmCM3_CM_3DLUT_DATA_30BIT                                                                      0x1254
+#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL                                                              0x1255
+#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x1256
+#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define mmCM3_CM_3DLUT_OUT_OFFSET_R                                                                    0x1257
+#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define mmCM3_CM_3DLUT_OUT_OFFSET_G                                                                    0x1258
+#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define mmCM3_CM_3DLUT_OUT_OFFSET_B                                                                    0x1259
+#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define mmCM3_CM_TEST_DEBUG_INDEX                                                                      0x125a
+#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define mmCM3_CM_TEST_DEBUG_DATA                                                                       0x125b
+#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x4994
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x1265
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x1266
+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON13_PERFCOUNTER_STATE                                                               0x1267
+#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON13_PERFMON_CNTL                                                                    0x1268
+#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON13_PERFMON_CNTL2                                                                   0x1269
+#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x126a
+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x126b
+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON13_PERFMON_HI                                                                      0x126c
+#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON13_PERFMON_LOW                                                                     0x126d
+#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+// base address: 0x0
+#define mmFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
+#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define mmFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
+#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define mmFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
+#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define mmFMT0_FMT_CONTROL                                                                             0x1840
+#define mmFMT0_FMT_CONTROL_BASE_IDX                                                                    2
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
+#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define mmFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
+#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define mmFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
+#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define mmFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
+#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define mmFMT0_FMT_CLAMP_CNTL                                                                          0x1845
+#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define mmFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
+#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define mmFMT0_FMT_422_CONTROL                                                                         0x1849
+#define mmFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+// base address: 0x0
+#define mmDPG0_DPG_CONTROL                                                                             0x1854
+#define mmDPG0_DPG_CONTROL_BASE_IDX                                                                    2
+#define mmDPG0_DPG_RAMP_CONTROL                                                                        0x1855
+#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define mmDPG0_DPG_DIMENSIONS                                                                          0x1856
+#define mmDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define mmDPG0_DPG_COLOUR_R_CR                                                                         0x1857
+#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define mmDPG0_DPG_COLOUR_G_Y                                                                          0x1858
+#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define mmDPG0_DPG_COLOUR_B_CB                                                                         0x1859
+#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define mmDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
+#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define mmDPG0_DPG_STATUS                                                                              0x185b
+#define mmDPG0_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+// base address: 0x0
+#define mmOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
+#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define mmOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
+#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+// base address: 0x0
+#define mmOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
+#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+// base address: 0x0
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+// base address: 0x168
+#define mmFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
+#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define mmFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
+#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define mmFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
+#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define mmFMT1_FMT_CONTROL                                                                             0x189a
+#define mmFMT1_FMT_CONTROL_BASE_IDX                                                                    2
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
+#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define mmFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
+#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define mmFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
+#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define mmFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
+#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define mmFMT1_FMT_CLAMP_CNTL                                                                          0x189f
+#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define mmFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
+#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define mmFMT1_FMT_422_CONTROL                                                                         0x18a3
+#define mmFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+// base address: 0x168
+#define mmDPG1_DPG_CONTROL                                                                             0x18ae
+#define mmDPG1_DPG_CONTROL_BASE_IDX                                                                    2
+#define mmDPG1_DPG_RAMP_CONTROL                                                                        0x18af
+#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define mmDPG1_DPG_DIMENSIONS                                                                          0x18b0
+#define mmDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define mmDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
+#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define mmDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
+#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define mmDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
+#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define mmDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
+#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define mmDPG1_DPG_STATUS                                                                              0x18b5
+#define mmDPG1_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+// base address: 0x168
+#define mmOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
+#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define mmOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
+#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+// base address: 0x168
+#define mmOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
+#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+// base address: 0x168
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_fmt2_dispdec
+// base address: 0x2d0
+#define mmFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
+#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define mmFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
+#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define mmFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
+#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define mmFMT2_FMT_CONTROL                                                                             0x18f4
+#define mmFMT2_FMT_CONTROL_BASE_IDX                                                                    2
+#define mmFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
+#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define mmFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
+#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define mmFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
+#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define mmFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
+#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define mmFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
+#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define mmFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
+#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define mmFMT2_FMT_422_CONTROL                                                                         0x18fd
+#define mmFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_dpg2_dispdec
+// base address: 0x2d0
+#define mmDPG2_DPG_CONTROL                                                                             0x1908
+#define mmDPG2_DPG_CONTROL_BASE_IDX                                                                    2
+#define mmDPG2_DPG_RAMP_CONTROL                                                                        0x1909
+#define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define mmDPG2_DPG_DIMENSIONS                                                                          0x190a
+#define mmDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define mmDPG2_DPG_COLOUR_R_CR                                                                         0x190b
+#define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define mmDPG2_DPG_COLOUR_G_Y                                                                          0x190c
+#define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define mmDPG2_DPG_COLOUR_B_CB                                                                         0x190d
+#define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define mmDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
+#define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define mmDPG2_DPG_STATUS                                                                              0x190f
+#define mmDPG2_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_oppbuf2_dispdec
+// base address: 0x2d0
+#define mmOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
+#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define mmOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
+#define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
+// base address: 0x2d0
+#define mmOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
+#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
+// base address: 0x2d0
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_fmt3_dispdec
+// base address: 0x438
+#define mmFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
+#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define mmFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
+#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define mmFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
+#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define mmFMT3_FMT_CONTROL                                                                             0x194e
+#define mmFMT3_FMT_CONTROL_BASE_IDX                                                                    2
+#define mmFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
+#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define mmFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
+#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define mmFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
+#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define mmFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
+#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define mmFMT3_FMT_CLAMP_CNTL                                                                          0x1953
+#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define mmFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
+#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define mmFMT3_FMT_422_CONTROL                                                                         0x1957
+#define mmFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_dpg3_dispdec
+// base address: 0x438
+#define mmDPG3_DPG_CONTROL                                                                             0x1962
+#define mmDPG3_DPG_CONTROL_BASE_IDX                                                                    2
+#define mmDPG3_DPG_RAMP_CONTROL                                                                        0x1963
+#define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define mmDPG3_DPG_DIMENSIONS                                                                          0x1964
+#define mmDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define mmDPG3_DPG_COLOUR_R_CR                                                                         0x1965
+#define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define mmDPG3_DPG_COLOUR_G_Y                                                                          0x1966
+#define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define mmDPG3_DPG_COLOUR_B_CB                                                                         0x1967
+#define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define mmDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
+#define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define mmDPG3_DPG_STATUS                                                                              0x1969
+#define mmDPG3_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_oppbuf3_dispdec
+// base address: 0x438
+#define mmOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
+#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define mmOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
+#define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
+// base address: 0x438
+#define mmOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
+#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
+// base address: 0x438
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+// base address: 0x0
+#define mmOPP_TOP_CLK_CONTROL                                                                          0x1a5e
+#define mmOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
+#define mmOPP_ABM_CONTROL                                                                              0x1a60
+#define mmOPP_ABM_CONTROL_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+// base address: 0x0
+#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
+#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+// base address: 0x4
+#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
+#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm2_dispdec
+// base address: 0x8
+#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
+#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x6af8
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x1abe
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x1abf
+#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON14_PERFCOUNTER_STATE                                                               0x1ac0
+#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON14_PERFMON_CNTL                                                                    0x1ac1
+#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON14_PERFMON_CNTL2                                                                   0x1ac2
+#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x1ac3
+#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x1ac4
+#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON14_PERFMON_HI                                                                      0x1ac5
+#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON14_PERFMON_LOW                                                                     0x1ac6
+#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+// base address: 0x0
+#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
+#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define mmODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
+#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define mmODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
+#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define mmODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
+#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define mmODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
+#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define mmODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
+#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define mmODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
+#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define mmODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
+#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+// base address: 0x40
+#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
+#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define mmODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
+#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define mmODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
+#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define mmODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
+#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define mmODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
+#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define mmODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
+#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define mmODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
+#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define mmODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
+#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm2_dispdec
+// base address: 0x80
+#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
+#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define mmODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
+#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define mmODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
+#define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define mmODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
+#define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define mmODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
+#define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define mmODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
+#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define mmODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
+#define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define mmODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
+#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm3_dispdec
+// base address: 0xc0
+#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
+#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define mmODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
+#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define mmODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
+#define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define mmODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
+#define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define mmODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
+#define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define mmODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
+#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define mmODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
+#define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define mmODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
+#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+// base address: 0x0
+#define mmOTG0_OTG_H_TOTAL                                                                             0x1b2a
+#define mmOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define mmOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
+#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG0_OTG_H_SYNC_A                                                                            0x1b2c
+#define mmOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
+#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
+#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define mmOTG0_OTG_V_TOTAL                                                                             0x1b2f
+#define mmOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define mmOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
+#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define mmOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
+#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define mmOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
+#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define mmOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
+#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define mmOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
+#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
+#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define mmOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
+#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG0_OTG_V_SYNC_A                                                                            0x1b37
+#define mmOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
+#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
+#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define mmOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
+#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
+#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define mmOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
+#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
+#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define mmOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
+#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
+#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define mmOTG0_OTG_CONTROL                                                                             0x1b41
+#define mmOTG0_OTG_CONTROL_BASE_IDX                                                                    2
+#define mmOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
+#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define mmOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
+#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define mmOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
+#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define mmOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
+#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define mmOTG0_OTG_STATUS                                                                              0x1b49
+#define mmOTG0_OTG_STATUS_BASE_IDX                                                                     2
+#define mmOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
+#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define mmOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
+#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define mmOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
+#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define mmOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
+#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define mmOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
+#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define mmOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
+#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define mmOTG0_OTG_COUNT_RESET                                                                         0x1b50
+#define mmOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
+#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define mmOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
+#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define mmOTG0_OTG_STEREO_STATUS                                                                       0x1b53
+#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define mmOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
+#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define mmOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
+#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define mmOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
+#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define mmOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
+#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define mmOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
+#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define mmOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
+#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define mmOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
+#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
+#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define mmOTG0_OTG_MASTER_EN                                                                           0x1b5c
+#define mmOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define mmOTG0_OTG_BLANK_DATA_COLOR                                                                    0x1b5e
+#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
+#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT                                                                0x1b5f
+#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define mmOTG0_OTG_CRC_CNTL                                                                            0x1b68
+#define mmOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define mmOTG0_OTG_CRC_CNTL2                                                                           0x1b69
+#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b6a
+#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6b
+#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6c
+#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6d
+#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6e
+#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define mmOTG0_OTG_CRC0_DATA_B                                                                         0x1b6f
+#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b70
+#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b71
+#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b72
+#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b73
+#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC1_DATA_RG                                                                        0x1b74
+#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define mmOTG0_OTG_CRC1_DATA_B                                                                         0x1b75
+#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define mmOTG0_OTG_CRC2_DATA_RG                                                                        0x1b76
+#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define mmOTG0_OTG_CRC2_DATA_B                                                                         0x1b77
+#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define mmOTG0_OTG_CRC3_DATA_RG                                                                        0x1b78
+#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define mmOTG0_OTG_CRC3_DATA_B                                                                         0x1b79
+#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b7a
+#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7b
+#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define mmOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b82
+#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define mmOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b83
+#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define mmOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b84
+#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define mmOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b85
+#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define mmOTG0_OTG_CLOCK_CONTROL                                                                       0x1b86
+#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define mmOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b87
+#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define mmOTG0_OTG_VUPDATE_PARAM                                                                       0x1b88
+#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define mmOTG0_OTG_VREADY_PARAM                                                                        0x1b89
+#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define mmOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b8a
+#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define mmOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8b
+#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define mmOTG0_OTG_GSL_CONTROL                                                                         0x1b8c
+#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define mmOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8d
+#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define mmOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8e
+#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define mmOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8f
+#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define mmOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b90
+#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define mmOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b91
+#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define mmOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b92
+#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define mmOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b93
+#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define mmOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b94
+#define mmOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define mmOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b95
+#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define mmOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b96
+#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define mmOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b97
+#define mmOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b98
+#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b99
+#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define mmOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b9a
+#define mmOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define mmOTG0_OTG_DRR_CONTROL                                                                         0x1b9b
+#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define mmOTG0_OTG_M_CONST_DTO0                                                                        0x1b9c
+#define mmOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define mmOTG0_OTG_M_CONST_DTO1                                                                        0x1b9d
+#define mmOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define mmOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9e
+#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define mmOTG0_OTG_DSC_START_POSITION                                                                  0x1b9f
+#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define mmOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1ba0
+#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define mmOTG0_OTG_SPARE_REGISTER                                                                      0x1ba2
+#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+// base address: 0x200
+#define mmOTG1_OTG_H_TOTAL                                                                             0x1baa
+#define mmOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define mmOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
+#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG1_OTG_H_SYNC_A                                                                            0x1bac
+#define mmOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
+#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
+#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define mmOTG1_OTG_V_TOTAL                                                                             0x1baf
+#define mmOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define mmOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
+#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define mmOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
+#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define mmOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
+#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define mmOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
+#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define mmOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
+#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
+#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define mmOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
+#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG1_OTG_V_SYNC_A                                                                            0x1bb7
+#define mmOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
+#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
+#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define mmOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
+#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
+#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define mmOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
+#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
+#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define mmOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
+#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
+#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define mmOTG1_OTG_CONTROL                                                                             0x1bc1
+#define mmOTG1_OTG_CONTROL_BASE_IDX                                                                    2
+#define mmOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
+#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define mmOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
+#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define mmOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
+#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define mmOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
+#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define mmOTG1_OTG_STATUS                                                                              0x1bc9
+#define mmOTG1_OTG_STATUS_BASE_IDX                                                                     2
+#define mmOTG1_OTG_STATUS_POSITION                                                                     0x1bca
+#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define mmOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
+#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define mmOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
+#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define mmOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
+#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define mmOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
+#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define mmOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
+#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define mmOTG1_OTG_COUNT_RESET                                                                         0x1bd0
+#define mmOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
+#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define mmOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
+#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define mmOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
+#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define mmOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
+#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define mmOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
+#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define mmOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
+#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define mmOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
+#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define mmOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
+#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define mmOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
+#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define mmOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
+#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
+#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define mmOTG1_OTG_MASTER_EN                                                                           0x1bdc
+#define mmOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define mmOTG1_OTG_BLANK_DATA_COLOR                                                                    0x1bde
+#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
+#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT                                                                0x1bdf
+#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define mmOTG1_OTG_CRC_CNTL                                                                            0x1be8
+#define mmOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define mmOTG1_OTG_CRC_CNTL2                                                                           0x1be9
+#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1bea
+#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1beb
+#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1bec
+#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bed
+#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC0_DATA_RG                                                                        0x1bee
+#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define mmOTG1_OTG_CRC0_DATA_B                                                                         0x1bef
+#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bf0
+#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf1
+#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf2
+#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf3
+#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf4
+#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define mmOTG1_OTG_CRC1_DATA_B                                                                         0x1bf5
+#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define mmOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf6
+#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define mmOTG1_OTG_CRC2_DATA_B                                                                         0x1bf7
+#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define mmOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf8
+#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define mmOTG1_OTG_CRC3_DATA_B                                                                         0x1bf9
+#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bfa
+#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfb
+#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define mmOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c02
+#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define mmOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c03
+#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define mmOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c04
+#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define mmOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c05
+#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define mmOTG1_OTG_CLOCK_CONTROL                                                                       0x1c06
+#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define mmOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c07
+#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define mmOTG1_OTG_VUPDATE_PARAM                                                                       0x1c08
+#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define mmOTG1_OTG_VREADY_PARAM                                                                        0x1c09
+#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define mmOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c0a
+#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define mmOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0b
+#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define mmOTG1_OTG_GSL_CONTROL                                                                         0x1c0c
+#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define mmOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0d
+#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define mmOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0e
+#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define mmOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0f
+#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define mmOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c10
+#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define mmOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c11
+#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define mmOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c12
+#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define mmOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c13
+#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define mmOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c14
+#define mmOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define mmOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c15
+#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define mmOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c16
+#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define mmOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c17
+#define mmOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c18
+#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c19
+#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define mmOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c1a
+#define mmOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define mmOTG1_OTG_DRR_CONTROL                                                                         0x1c1b
+#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define mmOTG1_OTG_M_CONST_DTO0                                                                        0x1c1c
+#define mmOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define mmOTG1_OTG_M_CONST_DTO1                                                                        0x1c1d
+#define mmOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define mmOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1e
+#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define mmOTG1_OTG_DSC_START_POSITION                                                                  0x1c1f
+#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define mmOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c20
+#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define mmOTG1_OTG_SPARE_REGISTER                                                                      0x1c22
+#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg2_dispdec
+// base address: 0x400
+#define mmOTG2_OTG_H_TOTAL                                                                             0x1c2a
+#define mmOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define mmOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
+#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG2_OTG_H_SYNC_A                                                                            0x1c2c
+#define mmOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
+#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
+#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define mmOTG2_OTG_V_TOTAL                                                                             0x1c2f
+#define mmOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define mmOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
+#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define mmOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
+#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define mmOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
+#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define mmOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
+#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define mmOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
+#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
+#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define mmOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
+#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG2_OTG_V_SYNC_A                                                                            0x1c37
+#define mmOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
+#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
+#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define mmOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
+#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
+#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define mmOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
+#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
+#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define mmOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
+#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
+#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define mmOTG2_OTG_CONTROL                                                                             0x1c41
+#define mmOTG2_OTG_CONTROL_BASE_IDX                                                                    2
+#define mmOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
+#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define mmOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
+#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define mmOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
+#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define mmOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
+#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define mmOTG2_OTG_STATUS                                                                              0x1c49
+#define mmOTG2_OTG_STATUS_BASE_IDX                                                                     2
+#define mmOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
+#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define mmOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
+#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define mmOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
+#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define mmOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
+#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define mmOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
+#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define mmOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
+#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define mmOTG2_OTG_COUNT_RESET                                                                         0x1c50
+#define mmOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
+#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define mmOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
+#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define mmOTG2_OTG_STEREO_STATUS                                                                       0x1c53
+#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define mmOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
+#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define mmOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
+#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define mmOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
+#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define mmOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
+#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define mmOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
+#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define mmOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
+#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define mmOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
+#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
+#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define mmOTG2_OTG_MASTER_EN                                                                           0x1c5c
+#define mmOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define mmOTG2_OTG_BLANK_DATA_COLOR                                                                    0x1c5e
+#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
+#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT                                                                0x1c5f
+#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define mmOTG2_OTG_CRC_CNTL                                                                            0x1c68
+#define mmOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define mmOTG2_OTG_CRC_CNTL2                                                                           0x1c69
+#define mmOTG2_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c6a
+#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6b
+#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6c
+#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6d
+#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6e
+#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define mmOTG2_OTG_CRC0_DATA_B                                                                         0x1c6f
+#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c70
+#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c71
+#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c72
+#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c73
+#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG2_OTG_CRC1_DATA_RG                                                                        0x1c74
+#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define mmOTG2_OTG_CRC1_DATA_B                                                                         0x1c75
+#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define mmOTG2_OTG_CRC2_DATA_RG                                                                        0x1c76
+#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define mmOTG2_OTG_CRC2_DATA_B                                                                         0x1c77
+#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define mmOTG2_OTG_CRC3_DATA_RG                                                                        0x1c78
+#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define mmOTG2_OTG_CRC3_DATA_B                                                                         0x1c79
+#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c7a
+#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7b
+#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define mmOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c82
+#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define mmOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c83
+#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define mmOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c84
+#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define mmOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c85
+#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define mmOTG2_OTG_CLOCK_CONTROL                                                                       0x1c86
+#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define mmOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c87
+#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define mmOTG2_OTG_VUPDATE_PARAM                                                                       0x1c88
+#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define mmOTG2_OTG_VREADY_PARAM                                                                        0x1c89
+#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define mmOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c8a
+#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define mmOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8b
+#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define mmOTG2_OTG_GSL_CONTROL                                                                         0x1c8c
+#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define mmOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8d
+#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define mmOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8e
+#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define mmOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8f
+#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define mmOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c90
+#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define mmOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c91
+#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define mmOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c92
+#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define mmOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c93
+#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define mmOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c94
+#define mmOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define mmOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c95
+#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define mmOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c96
+#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define mmOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c97
+#define mmOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c98
+#define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define mmOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c99
+#define mmOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define mmOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c9a
+#define mmOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define mmOTG2_OTG_DRR_CONTROL                                                                         0x1c9b
+#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define mmOTG2_OTG_M_CONST_DTO0                                                                        0x1c9c
+#define mmOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define mmOTG2_OTG_M_CONST_DTO1                                                                        0x1c9d
+#define mmOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define mmOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9e
+#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define mmOTG2_OTG_DSC_START_POSITION                                                                  0x1c9f
+#define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define mmOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1ca0
+#define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define mmOTG2_OTG_SPARE_REGISTER                                                                      0x1ca2
+#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg3_dispdec
+// base address: 0x600
+#define mmOTG3_OTG_H_TOTAL                                                                             0x1caa
+#define mmOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define mmOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
+#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG3_OTG_H_SYNC_A                                                                            0x1cac
+#define mmOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
+#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
+#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define mmOTG3_OTG_V_TOTAL                                                                             0x1caf
+#define mmOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define mmOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
+#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define mmOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
+#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define mmOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
+#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define mmOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
+#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define mmOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
+#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
+#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define mmOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
+#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define mmOTG3_OTG_V_SYNC_A                                                                            0x1cb7
+#define mmOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define mmOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
+#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define mmOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
+#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define mmOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
+#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
+#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define mmOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
+#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
+#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define mmOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
+#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
+#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define mmOTG3_OTG_CONTROL                                                                             0x1cc1
+#define mmOTG3_OTG_CONTROL_BASE_IDX                                                                    2
+#define mmOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
+#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define mmOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
+#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define mmOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
+#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define mmOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
+#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define mmOTG3_OTG_STATUS                                                                              0x1cc9
+#define mmOTG3_OTG_STATUS_BASE_IDX                                                                     2
+#define mmOTG3_OTG_STATUS_POSITION                                                                     0x1cca
+#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define mmOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
+#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define mmOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
+#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define mmOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
+#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define mmOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
+#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define mmOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
+#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define mmOTG3_OTG_COUNT_RESET                                                                         0x1cd0
+#define mmOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
+#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define mmOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
+#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define mmOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
+#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define mmOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
+#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define mmOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
+#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define mmOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
+#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define mmOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
+#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define mmOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
+#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define mmOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
+#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define mmOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
+#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
+#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define mmOTG3_OTG_MASTER_EN                                                                           0x1cdc
+#define mmOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define mmOTG3_OTG_BLANK_DATA_COLOR                                                                    0x1cde
+#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
+#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT                                                                0x1cdf
+#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define mmOTG3_OTG_CRC_CNTL                                                                            0x1ce8
+#define mmOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define mmOTG3_OTG_CRC_CNTL2                                                                           0x1ce9
+#define mmOTG3_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1cea
+#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ceb
+#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1cec
+#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ced
+#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG3_OTG_CRC0_DATA_RG                                                                        0x1cee
+#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define mmOTG3_OTG_CRC0_DATA_B                                                                         0x1cef
+#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cf0
+#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf1
+#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf2
+#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf3
+#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define mmOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf4
+#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define mmOTG3_OTG_CRC1_DATA_B                                                                         0x1cf5
+#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define mmOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf6
+#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define mmOTG3_OTG_CRC2_DATA_B                                                                         0x1cf7
+#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define mmOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf8
+#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define mmOTG3_OTG_CRC3_DATA_B                                                                         0x1cf9
+#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cfa
+#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfb
+#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define mmOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d02
+#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define mmOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d03
+#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define mmOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d04
+#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define mmOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d05
+#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define mmOTG3_OTG_CLOCK_CONTROL                                                                       0x1d06
+#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define mmOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d07
+#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define mmOTG3_OTG_VUPDATE_PARAM                                                                       0x1d08
+#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define mmOTG3_OTG_VREADY_PARAM                                                                        0x1d09
+#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define mmOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d0a
+#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define mmOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0b
+#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define mmOTG3_OTG_GSL_CONTROL                                                                         0x1d0c
+#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define mmOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0d
+#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define mmOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0e
+#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define mmOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0f
+#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define mmOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d10
+#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define mmOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d11
+#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define mmOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d12
+#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define mmOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d13
+#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define mmOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d14
+#define mmOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define mmOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d15
+#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define mmOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d16
+#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define mmOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d17
+#define mmOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d18
+#define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define mmOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d19
+#define mmOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define mmOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d1a
+#define mmOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define mmOTG3_OTG_DRR_CONTROL                                                                         0x1d1b
+#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define mmOTG3_OTG_M_CONST_DTO0                                                                        0x1d1c
+#define mmOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define mmOTG3_OTG_M_CONST_DTO1                                                                        0x1d1d
+#define mmOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define mmOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1e
+#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define mmOTG3_OTG_DSC_START_POSITION                                                                  0x1d1f
+#define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define mmOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d20
+#define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define mmOTG3_OTG_SPARE_REGISTER                                                                      0x1d22
+#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+// base address: 0x0
+#define mmDWB_SOURCE_SELECT                                                                            0x1e2a
+#define mmDWB_SOURCE_SELECT_BASE_IDX                                                                   2
+#define mmGSL_SOURCE_SELECT                                                                            0x1e2b
+#define mmGSL_SOURCE_SELECT_BASE_IDX                                                                   2
+#define mmOPTC_CLOCK_CONTROL                                                                           0x1e2c
+#define mmOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
+#define mmODM_MEM_PWR_CTRL                                                                             0x1e2d
+#define mmODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define mmODM_MEM_PWR_CTRL2                                                                            0x1e2e
+#define mmODM_MEM_PWR_CTRL2_BASE_IDX                                                                   2
+#define mmODM_MEM_PWR_CTRL3                                                                            0x1e2f
+#define mmODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
+#define mmODM_MEM_PWR_STATUS                                                                           0x1e30
+#define mmODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define mmOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
+#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
+// base address: 0x79a8
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x1e6a
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x1e6b
+#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON15_PERFCOUNTER_STATE                                                               0x1e6c
+#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON15_PERFMON_CNTL                                                                    0x1e6d
+#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON15_PERFMON_CNTL2                                                                   0x1e6e
+#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x1e6f
+#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x1e70
+#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON15_PERFMON_HI                                                                      0x1e71
+#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON15_PERFMON_LOW                                                                     0x1e72
+#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+// base address: 0x0
+#define mmDC_I2C_CONTROL                                                                               0x1e98
+#define mmDC_I2C_CONTROL_BASE_IDX                                                                      2
+#define mmDC_I2C_ARBITRATION                                                                           0x1e99
+#define mmDC_I2C_ARBITRATION_BASE_IDX                                                                  2
+#define mmDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
+#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
+#define mmDC_I2C_SW_STATUS                                                                             0x1e9b
+#define mmDC_I2C_SW_STATUS_BASE_IDX                                                                    2
+#define mmDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
+#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
+#define mmDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
+#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
+#define mmDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
+#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
+#define mmDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
+#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
+#define mmDC_I2C_DDC1_SPEED                                                                            0x1ea2
+#define mmDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
+#define mmDC_I2C_DDC1_SETUP                                                                            0x1ea3
+#define mmDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
+#define mmDC_I2C_DDC2_SPEED                                                                            0x1ea4
+#define mmDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
+#define mmDC_I2C_DDC2_SETUP                                                                            0x1ea5
+#define mmDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
+#define mmDC_I2C_DDC3_SPEED                                                                            0x1ea6
+#define mmDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
+#define mmDC_I2C_DDC3_SETUP                                                                            0x1ea7
+#define mmDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
+#define mmDC_I2C_DDC4_SPEED                                                                            0x1ea8
+#define mmDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
+#define mmDC_I2C_DDC4_SETUP                                                                            0x1ea9
+#define mmDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
+#define mmDC_I2C_TRANSACTION0                                                                          0x1eae
+#define mmDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
+#define mmDC_I2C_TRANSACTION1                                                                          0x1eaf
+#define mmDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
+#define mmDC_I2C_TRANSACTION2                                                                          0x1eb0
+#define mmDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
+#define mmDC_I2C_TRANSACTION3                                                                          0x1eb1
+#define mmDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
+#define mmDC_I2C_DATA                                                                                  0x1eb2
+#define mmDC_I2C_DATA_BASE_IDX                                                                         2
+#define mmDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
+#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
+#define mmDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
+#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+// base address: 0x0
+#define mmDIO_SCRATCH0                                                                                 0x1eca
+#define mmDIO_SCRATCH0_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH1                                                                                 0x1ecb
+#define mmDIO_SCRATCH1_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH2                                                                                 0x1ecc
+#define mmDIO_SCRATCH2_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH3                                                                                 0x1ecd
+#define mmDIO_SCRATCH3_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH4                                                                                 0x1ece
+#define mmDIO_SCRATCH4_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH5                                                                                 0x1ecf
+#define mmDIO_SCRATCH5_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH6                                                                                 0x1ed0
+#define mmDIO_SCRATCH6_BASE_IDX                                                                        2
+#define mmDIO_SCRATCH7                                                                                 0x1ed1
+#define mmDIO_SCRATCH7_BASE_IDX                                                                        2
+#define mmDIO_MEM_PWR_STATUS                                                                           0x1edd
+#define mmDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define mmDIO_MEM_PWR_CTRL                                                                             0x1ede
+#define mmDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define mmDIO_MEM_PWR_CTRL2                                                                            0x1edf
+#define mmDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
+#define mmDIO_CLK_CNTL                                                                                 0x1ee0
+#define mmDIO_CLK_CNTL_BASE_IDX                                                                        2
+#define mmDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
+#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
+#define mmDIG_SOFT_RESET                                                                               0x1eee
+#define mmDIG_SOFT_RESET_BASE_IDX                                                                      2
+#define mmDIO_CLK_CNTL2                                                                                0x1ef2
+#define mmDIO_CLK_CNTL2_BASE_IDX                                                                       2
+#define mmDIO_CLK_CNTL3                                                                                0x1ef3
+#define mmDIO_CLK_CNTL3_BASE_IDX                                                                       2
+#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
+#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
+#define mmDIO_GENERIC_INTERRUPT_MESSAGE                                                                0x1f02
+#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX                                                       2
+#define mmDIO_GENERIC_INTERRUPT_CLEAR                                                                  0x1f03
+#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX                                                         2
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+// base address: 0x0
+#define mmHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
+#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define mmHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
+#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define mmHPD0_DC_HPD_CONTROL                                                                          0x1f16
+#define mmHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+// base address: 0x20
+#define mmHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
+#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define mmHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
+#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define mmHPD1_DC_HPD_CONTROL                                                                          0x1f1e
+#define mmHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd2_dispdec
+// base address: 0x40
+#define mmHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
+#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define mmHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
+#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define mmHPD2_DC_HPD_CONTROL                                                                          0x1f26
+#define mmHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd3_dispdec
+// base address: 0x60
+#define mmHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
+#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define mmHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
+#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define mmHPD3_DC_HPD_CONTROL                                                                          0x1f2e
+#define mmHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
+// base address: 0x7d10
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x1f44
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x1f45
+#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON16_PERFCOUNTER_STATE                                                               0x1f46
+#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON16_PERFMON_CNTL                                                                    0x1f47
+#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON16_PERFMON_CNTL2                                                                   0x1f48
+#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x1f49
+#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x1f4a
+#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON16_PERFMON_HI                                                                      0x1f4b
+#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON16_PERFMON_LOW                                                                     0x1f4c
+#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+// base address: 0x0
+#define mmDP_AUX0_AUX_CONTROL                                                                          0x1f50
+#define mmDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
+#define mmDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
+#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define mmDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
+#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define mmDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
+#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
+#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX0_AUX_SW_DATA                                                                          0x1f56
+#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX0_AUX_LS_DATA                                                                          0x1f57
+#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
+#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
+#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define mmDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
+#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+// base address: 0x70
+#define mmDP_AUX1_AUX_CONTROL                                                                          0x1f6c
+#define mmDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
+#define mmDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
+#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define mmDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
+#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define mmDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
+#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
+#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX1_AUX_SW_DATA                                                                          0x1f72
+#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX1_AUX_LS_DATA                                                                          0x1f73
+#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
+#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
+#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define mmDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
+#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux2_dispdec
+// base address: 0xe0
+#define mmDP_AUX2_AUX_CONTROL                                                                          0x1f88
+#define mmDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
+#define mmDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
+#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define mmDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
+#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define mmDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
+#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
+#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
+#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
+#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define mmDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
+#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
+#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define mmDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
+#define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux3_dispdec
+// base address: 0x150
+#define mmDP_AUX3_AUX_CONTROL                                                                          0x1fa4
+#define mmDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
+#define mmDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
+#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define mmDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
+#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define mmDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
+#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
+#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
+#define mmDP_AUX3_AUX_SW_DATA                                                                          0x1faa
+#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX3_AUX_LS_DATA                                                                          0x1fab
+#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define mmDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
+#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
+#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define mmDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
+#define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
+// base address: 0x154a0
+#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068
+#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define mmVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069
+#define mmVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a
+#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b
+#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define mmVPG0_VPG_GENERIC_STATUS                                                                      0x206c
+#define mmVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define mmVPG0_VPG_MEM_PWR                                                                             0x206d
+#define mmVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e
+#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define mmVPG0_VPG_ISRC1_2_DATA                                                                        0x206f
+#define mmVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define mmVPG0_VPG_MPEG_INFO0                                                                          0x2070
+#define mmVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define mmVPG0_VPG_MPEG_INFO1                                                                          0x2071
+#define mmVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
+// base address: 0x154cc
+#define mmAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074
+#define mmAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075
+#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define mmAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076
+#define mmAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define mmAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077
+#define mmAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define mmAFMT0_AFMT_60958_0                                                                           0x2078
+#define mmAFMT0_AFMT_60958_0_BASE_IDX                                                                  2
+#define mmAFMT0_AFMT_60958_1                                                                           0x2079
+#define mmAFMT0_AFMT_60958_1_BASE_IDX                                                                  2
+#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a
+#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b
+#define mmAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define mmAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c
+#define mmAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define mmAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d
+#define mmAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define mmAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e
+#define mmAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define mmAFMT0_AFMT_60958_2                                                                           0x207f
+#define mmAFMT0_AFMT_60958_2_BASE_IDX                                                                  2
+#define mmAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080
+#define mmAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define mmAFMT0_AFMT_STATUS                                                                            0x2081
+#define mmAFMT0_AFMT_STATUS_BASE_IDX                                                                   2
+#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082
+#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define mmAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083
+#define mmAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define mmAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084
+#define mmAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085
+#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT0_AFMT_MEM_PWR                                                                           0x2087
+#define mmAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
+// base address: 0x15524
+#define mmDME0_DME_CONTROL                                                                             0x2089
+#define mmDME0_DME_CONTROL_BASE_IDX                                                                    2
+#define mmDME0_DME_MEMORY_CONTROL                                                                      0x208a
+#define mmDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+// base address: 0x0
+#define mmDIG0_DIG_FE_CNTL                                                                             0x208b
+#define mmDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x208c
+#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x208d
+#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define mmDIG0_DIG_CLOCK_PATTERN                                                                       0x208e
+#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define mmDIG0_DIG_TEST_PATTERN                                                                        0x208f
+#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x2090
+#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define mmDIG0_DIG_FIFO_STATUS                                                                         0x2091
+#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define mmDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x2092
+#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define mmDIG0_HDMI_CONTROL                                                                            0x2093
+#define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
+#define mmDIG0_HDMI_STATUS                                                                             0x2094
+#define mmDIG0_HDMI_STATUS_BASE_IDX                                                                    2
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2095
+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2096
+#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2097
+#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2098
+#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x2099
+#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x209a
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x209b
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x209c
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GC                                                                                 0x209d
+#define mmDIG0_HDMI_GC_BASE_IDX                                                                        2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x209e
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x209f
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20a0
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20a1
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20a2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20a3
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20a4
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20a5
+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define mmDIG0_HDMI_DB_CONTROL                                                                         0x20a6
+#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define mmDIG0_HDMI_ACR_32_0                                                                           0x20a7
+#define mmDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_32_1                                                                           0x20a8
+#define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_44_0                                                                           0x20a9
+#define mmDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_44_1                                                                           0x20aa
+#define mmDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_48_0                                                                           0x20ab
+#define mmDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_48_1                                                                           0x20ac
+#define mmDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define mmDIG0_HDMI_ACR_STATUS_0                                                                       0x20ad
+#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define mmDIG0_HDMI_ACR_STATUS_1                                                                       0x20ae
+#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define mmDIG0_AFMT_CNTL                                                                               0x20af
+#define mmDIG0_AFMT_CNTL_BASE_IDX                                                                      2
+#define mmDIG0_DIG_BE_CNTL                                                                             0x20b0
+#define mmDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define mmDIG0_DIG_BE_EN_CNTL                                                                          0x20b1
+#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define mmDIG0_TMDS_CNTL                                                                               0x20d7
+#define mmDIG0_TMDS_CNTL_BASE_IDX                                                                      2
+#define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x20d8
+#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20d9
+#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20da
+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20db
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20dc
+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define mmDIG0_TMDS_CTL_BITS                                                                           0x20de
+#define mmDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define mmDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20df
+#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20e0
+#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define mmDIG0_DIG_VERSION                                                                             0x20e4
+#define mmDIG0_DIG_VERSION_BASE_IDX                                                                    2
+#define mmDIG0_DIG_LANE_ENABLE                                                                         0x20e5
+#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX                                                                2
+#define mmDIG0_FORCE_DIG_DISABLE                                                                       0x20e6
+#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+// base address: 0x0
+#define mmDP0_DP_LINK_CNTL                                                                             0x2108
+#define mmDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define mmDP0_DP_PIXEL_FORMAT                                                                          0x2109
+#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define mmDP0_DP_MSA_COLORIMETRY                                                                       0x210a
+#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define mmDP0_DP_CONFIG                                                                                0x210b
+#define mmDP0_DP_CONFIG_BASE_IDX                                                                       2
+#define mmDP0_DP_VID_STREAM_CNTL                                                                       0x210c
+#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define mmDP0_DP_STEER_FIFO                                                                            0x210d
+#define mmDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define mmDP0_DP_MSA_MISC                                                                              0x210e
+#define mmDP0_DP_MSA_MISC_BASE_IDX                                                                     2
+#define mmDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x210f
+#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define mmDP0_DP_VID_TIMING                                                                            0x2110
+#define mmDP0_DP_VID_TIMING_BASE_IDX                                                                   2
+#define mmDP0_DP_VID_N                                                                                 0x2111
+#define mmDP0_DP_VID_N_BASE_IDX                                                                        2
+#define mmDP0_DP_VID_M                                                                                 0x2112
+#define mmDP0_DP_VID_M_BASE_IDX                                                                        2
+#define mmDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
+#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define mmDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
+#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define mmDP0_DP_VID_MSA_VBID                                                                          0x2115
+#define mmDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define mmDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
+#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define mmDP0_DP_DPHY_CNTL                                                                             0x2117
+#define mmDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define mmDP0_DP_DPHY_SYM0                                                                             0x2119
+#define mmDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define mmDP0_DP_DPHY_SYM1                                                                             0x211a
+#define mmDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define mmDP0_DP_DPHY_SYM2                                                                             0x211b
+#define mmDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define mmDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
+#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define mmDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
+#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define mmDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
+#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define mmDP0_DP_DPHY_CRC_EN                                                                           0x211f
+#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define mmDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
+#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define mmDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
+#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define mmDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
+#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define mmDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
+#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define mmDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
+#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define mmDP0_DP_SEC_CNTL                                                                              0x212b
+#define mmDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define mmDP0_DP_SEC_CNTL1                                                                             0x212c
+#define mmDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_FRAMING1                                                                          0x212d
+#define mmDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define mmDP0_DP_SEC_FRAMING2                                                                          0x212e
+#define mmDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define mmDP0_DP_SEC_FRAMING3                                                                          0x212f
+#define mmDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define mmDP0_DP_SEC_FRAMING4                                                                          0x2130
+#define mmDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define mmDP0_DP_SEC_AUD_N                                                                             0x2131
+#define mmDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
+#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define mmDP0_DP_SEC_AUD_M                                                                             0x2133
+#define mmDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
+#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define mmDP0_DP_SEC_TIMESTAMP                                                                         0x2135
+#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define mmDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
+#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define mmDP0_DP_MSE_RATE_CNTL                                                                         0x2137
+#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define mmDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
+#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define mmDP0_DP_MSE_SAT0                                                                              0x213a
+#define mmDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define mmDP0_DP_MSE_SAT1                                                                              0x213b
+#define mmDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define mmDP0_DP_MSE_SAT2                                                                              0x213c
+#define mmDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define mmDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
+#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define mmDP0_DP_MSE_LINK_TIMING                                                                       0x213e
+#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define mmDP0_DP_MSE_MISC_CNTL                                                                         0x213f
+#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define mmDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
+#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define mmDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
+#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define mmDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
+#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define mmDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
+#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define mmDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
+#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define mmDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
+#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define mmDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
+#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define mmDP0_DP_MSO_CNTL                                                                              0x2150
+#define mmDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define mmDP0_DP_MSO_CNTL1                                                                             0x2151
+#define mmDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define mmDP0_DP_DSC_CNTL                                                                              0x2152
+#define mmDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define mmDP0_DP_SEC_CNTL2                                                                             0x2153
+#define mmDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_CNTL3                                                                             0x2154
+#define mmDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_CNTL4                                                                             0x2155
+#define mmDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_CNTL5                                                                             0x2156
+#define mmDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_CNTL6                                                                             0x2157
+#define mmDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define mmDP0_DP_SEC_CNTL7                                                                             0x2158
+#define mmDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define mmDP0_DP_DB_CNTL                                                                               0x2159
+#define mmDP0_DP_DB_CNTL_BASE_IDX                                                                      2
+#define mmDP0_DP_MSA_VBID_MISC                                                                         0x215a
+#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define mmDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
+#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define mmDP0_DP_DSC_BYTES_PER_PIXEL                                                                   0x215c
+#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define mmDP0_DP_ALPM_CNTL                                                                             0x215d
+#define mmDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define mmDP0_DP_GSP8_CNTL                                                                             0x215e
+#define mmDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define mmDP0_DP_GSP9_CNTL                                                                             0x215f
+#define mmDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define mmDP0_DP_GSP10_CNTL                                                                            0x2160
+#define mmDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define mmDP0_DP_GSP11_CNTL                                                                            0x2161
+#define mmDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define mmDP0_DP_GSP_EN_DB_STATUS                                                                      0x2162
+#define mmDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
+// base address: 0x158a0
+#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2168
+#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define mmVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x2169
+#define mmVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x216a
+#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x216b
+#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define mmVPG1_VPG_GENERIC_STATUS                                                                      0x216c
+#define mmVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define mmVPG1_VPG_MEM_PWR                                                                             0x216d
+#define mmVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x216e
+#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define mmVPG1_VPG_ISRC1_2_DATA                                                                        0x216f
+#define mmVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define mmVPG1_VPG_MPEG_INFO0                                                                          0x2170
+#define mmVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define mmVPG1_VPG_MPEG_INFO1                                                                          0x2171
+#define mmVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
+// base address: 0x158cc
+#define mmAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2174
+#define mmAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2175
+#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define mmAFMT1_AFMT_AUDIO_INFO0                                                                       0x2176
+#define mmAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define mmAFMT1_AFMT_AUDIO_INFO1                                                                       0x2177
+#define mmAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define mmAFMT1_AFMT_60958_0                                                                           0x2178
+#define mmAFMT1_AFMT_60958_0_BASE_IDX                                                                  2
+#define mmAFMT1_AFMT_60958_1                                                                           0x2179
+#define mmAFMT1_AFMT_60958_1_BASE_IDX                                                                  2
+#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x217a
+#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT1_AFMT_RAMP_CONTROL0                                                                     0x217b
+#define mmAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define mmAFMT1_AFMT_RAMP_CONTROL1                                                                     0x217c
+#define mmAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define mmAFMT1_AFMT_RAMP_CONTROL2                                                                     0x217d
+#define mmAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define mmAFMT1_AFMT_RAMP_CONTROL3                                                                     0x217e
+#define mmAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define mmAFMT1_AFMT_60958_2                                                                           0x217f
+#define mmAFMT1_AFMT_60958_2_BASE_IDX                                                                  2
+#define mmAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x2180
+#define mmAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define mmAFMT1_AFMT_STATUS                                                                            0x2181
+#define mmAFMT1_AFMT_STATUS_BASE_IDX                                                                   2
+#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x2182
+#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define mmAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x2183
+#define mmAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define mmAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x2184
+#define mmAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x2185
+#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT1_AFMT_MEM_PWR                                                                           0x2187
+#define mmAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
+// base address: 0x15924
+#define mmDME1_DME_CONTROL                                                                             0x2189
+#define mmDME1_DME_CONTROL_BASE_IDX                                                                    2
+#define mmDME1_DME_MEMORY_CONTROL                                                                      0x218a
+#define mmDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+// base address: 0x400
+#define mmDIG1_DIG_FE_CNTL                                                                             0x218b
+#define mmDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x218c
+#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x218d
+#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define mmDIG1_DIG_CLOCK_PATTERN                                                                       0x218e
+#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define mmDIG1_DIG_TEST_PATTERN                                                                        0x218f
+#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x2190
+#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define mmDIG1_DIG_FIFO_STATUS                                                                         0x2191
+#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define mmDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x2192
+#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define mmDIG1_HDMI_CONTROL                                                                            0x2193
+#define mmDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
+#define mmDIG1_HDMI_STATUS                                                                             0x2194
+#define mmDIG1_HDMI_STATUS_BASE_IDX                                                                    2
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2195
+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2196
+#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2197
+#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2198
+#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x2199
+#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x219a
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x219b
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x219c
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GC                                                                                 0x219d
+#define mmDIG1_HDMI_GC_BASE_IDX                                                                        2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x219e
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x219f
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21a0
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21a1
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21a2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21a3
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21a4
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21a5
+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define mmDIG1_HDMI_DB_CONTROL                                                                         0x21a6
+#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define mmDIG1_HDMI_ACR_32_0                                                                           0x21a7
+#define mmDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_32_1                                                                           0x21a8
+#define mmDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_44_0                                                                           0x21a9
+#define mmDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_44_1                                                                           0x21aa
+#define mmDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_48_0                                                                           0x21ab
+#define mmDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_48_1                                                                           0x21ac
+#define mmDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define mmDIG1_HDMI_ACR_STATUS_0                                                                       0x21ad
+#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define mmDIG1_HDMI_ACR_STATUS_1                                                                       0x21ae
+#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define mmDIG1_AFMT_CNTL                                                                               0x21af
+#define mmDIG1_AFMT_CNTL_BASE_IDX                                                                      2
+#define mmDIG1_DIG_BE_CNTL                                                                             0x21b0
+#define mmDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define mmDIG1_DIG_BE_EN_CNTL                                                                          0x21b1
+#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define mmDIG1_TMDS_CNTL                                                                               0x21d7
+#define mmDIG1_TMDS_CNTL_BASE_IDX                                                                      2
+#define mmDIG1_TMDS_CONTROL_CHAR                                                                       0x21d8
+#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21d9
+#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21da
+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21db
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21dc
+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define mmDIG1_TMDS_CTL_BITS                                                                           0x21de
+#define mmDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define mmDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21df
+#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21e0
+#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define mmDIG1_DIG_VERSION                                                                             0x21e4
+#define mmDIG1_DIG_VERSION_BASE_IDX                                                                    2
+#define mmDIG1_DIG_LANE_ENABLE                                                                         0x21e5
+#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX                                                                2
+#define mmDIG1_FORCE_DIG_DISABLE                                                                       0x21e6
+#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+// base address: 0x400
+#define mmDP1_DP_LINK_CNTL                                                                             0x2208
+#define mmDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define mmDP1_DP_PIXEL_FORMAT                                                                          0x2209
+#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define mmDP1_DP_MSA_COLORIMETRY                                                                       0x220a
+#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define mmDP1_DP_CONFIG                                                                                0x220b
+#define mmDP1_DP_CONFIG_BASE_IDX                                                                       2
+#define mmDP1_DP_VID_STREAM_CNTL                                                                       0x220c
+#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define mmDP1_DP_STEER_FIFO                                                                            0x220d
+#define mmDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define mmDP1_DP_MSA_MISC                                                                              0x220e
+#define mmDP1_DP_MSA_MISC_BASE_IDX                                                                     2
+#define mmDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x220f
+#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define mmDP1_DP_VID_TIMING                                                                            0x2210
+#define mmDP1_DP_VID_TIMING_BASE_IDX                                                                   2
+#define mmDP1_DP_VID_N                                                                                 0x2211
+#define mmDP1_DP_VID_N_BASE_IDX                                                                        2
+#define mmDP1_DP_VID_M                                                                                 0x2212
+#define mmDP1_DP_VID_M_BASE_IDX                                                                        2
+#define mmDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
+#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define mmDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
+#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define mmDP1_DP_VID_MSA_VBID                                                                          0x2215
+#define mmDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define mmDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
+#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define mmDP1_DP_DPHY_CNTL                                                                             0x2217
+#define mmDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define mmDP1_DP_DPHY_SYM0                                                                             0x2219
+#define mmDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define mmDP1_DP_DPHY_SYM1                                                                             0x221a
+#define mmDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define mmDP1_DP_DPHY_SYM2                                                                             0x221b
+#define mmDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define mmDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
+#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
+#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define mmDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
+#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define mmDP1_DP_DPHY_CRC_EN                                                                           0x221f
+#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define mmDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
+#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define mmDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
+#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define mmDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
+#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define mmDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
+#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define mmDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
+#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define mmDP1_DP_SEC_CNTL                                                                              0x222b
+#define mmDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define mmDP1_DP_SEC_CNTL1                                                                             0x222c
+#define mmDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_FRAMING1                                                                          0x222d
+#define mmDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define mmDP1_DP_SEC_FRAMING2                                                                          0x222e
+#define mmDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define mmDP1_DP_SEC_FRAMING3                                                                          0x222f
+#define mmDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define mmDP1_DP_SEC_FRAMING4                                                                          0x2230
+#define mmDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define mmDP1_DP_SEC_AUD_N                                                                             0x2231
+#define mmDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
+#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define mmDP1_DP_SEC_AUD_M                                                                             0x2233
+#define mmDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
+#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define mmDP1_DP_SEC_TIMESTAMP                                                                         0x2235
+#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define mmDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
+#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define mmDP1_DP_MSE_RATE_CNTL                                                                         0x2237
+#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define mmDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
+#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define mmDP1_DP_MSE_SAT0                                                                              0x223a
+#define mmDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define mmDP1_DP_MSE_SAT1                                                                              0x223b
+#define mmDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define mmDP1_DP_MSE_SAT2                                                                              0x223c
+#define mmDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define mmDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
+#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define mmDP1_DP_MSE_LINK_TIMING                                                                       0x223e
+#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define mmDP1_DP_MSE_MISC_CNTL                                                                         0x223f
+#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define mmDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
+#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define mmDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
+#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define mmDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
+#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define mmDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
+#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define mmDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
+#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define mmDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
+#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define mmDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
+#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define mmDP1_DP_MSO_CNTL                                                                              0x2250
+#define mmDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define mmDP1_DP_MSO_CNTL1                                                                             0x2251
+#define mmDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define mmDP1_DP_DSC_CNTL                                                                              0x2252
+#define mmDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define mmDP1_DP_SEC_CNTL2                                                                             0x2253
+#define mmDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_CNTL3                                                                             0x2254
+#define mmDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_CNTL4                                                                             0x2255
+#define mmDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_CNTL5                                                                             0x2256
+#define mmDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_CNTL6                                                                             0x2257
+#define mmDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define mmDP1_DP_SEC_CNTL7                                                                             0x2258
+#define mmDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define mmDP1_DP_DB_CNTL                                                                               0x2259
+#define mmDP1_DP_DB_CNTL_BASE_IDX                                                                      2
+#define mmDP1_DP_MSA_VBID_MISC                                                                         0x225a
+#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define mmDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
+#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define mmDP1_DP_DSC_BYTES_PER_PIXEL                                                                   0x225c
+#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define mmDP1_DP_ALPM_CNTL                                                                             0x225d
+#define mmDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define mmDP1_DP_GSP8_CNTL                                                                             0x225e
+#define mmDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define mmDP1_DP_GSP9_CNTL                                                                             0x225f
+#define mmDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define mmDP1_DP_GSP10_CNTL                                                                            0x2260
+#define mmDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define mmDP1_DP_GSP11_CNTL                                                                            0x2261
+#define mmDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define mmDP1_DP_GSP_EN_DB_STATUS                                                                      0x2262
+#define mmDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
+// base address: 0x15ca0
+#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2268
+#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define mmVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x2269
+#define mmVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x226a
+#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x226b
+#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define mmVPG2_VPG_GENERIC_STATUS                                                                      0x226c
+#define mmVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define mmVPG2_VPG_MEM_PWR                                                                             0x226d
+#define mmVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x226e
+#define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define mmVPG2_VPG_ISRC1_2_DATA                                                                        0x226f
+#define mmVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define mmVPG2_VPG_MPEG_INFO0                                                                          0x2270
+#define mmVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define mmVPG2_VPG_MPEG_INFO1                                                                          0x2271
+#define mmVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
+// base address: 0x15ccc
+#define mmAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x2274
+#define mmAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2275
+#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define mmAFMT2_AFMT_AUDIO_INFO0                                                                       0x2276
+#define mmAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define mmAFMT2_AFMT_AUDIO_INFO1                                                                       0x2277
+#define mmAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define mmAFMT2_AFMT_60958_0                                                                           0x2278
+#define mmAFMT2_AFMT_60958_0_BASE_IDX                                                                  2
+#define mmAFMT2_AFMT_60958_1                                                                           0x2279
+#define mmAFMT2_AFMT_60958_1_BASE_IDX                                                                  2
+#define mmAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x227a
+#define mmAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT2_AFMT_RAMP_CONTROL0                                                                     0x227b
+#define mmAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define mmAFMT2_AFMT_RAMP_CONTROL1                                                                     0x227c
+#define mmAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define mmAFMT2_AFMT_RAMP_CONTROL2                                                                     0x227d
+#define mmAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define mmAFMT2_AFMT_RAMP_CONTROL3                                                                     0x227e
+#define mmAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define mmAFMT2_AFMT_60958_2                                                                           0x227f
+#define mmAFMT2_AFMT_60958_2_BASE_IDX                                                                  2
+#define mmAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x2280
+#define mmAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define mmAFMT2_AFMT_STATUS                                                                            0x2281
+#define mmAFMT2_AFMT_STATUS_BASE_IDX                                                                   2
+#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x2282
+#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define mmAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x2283
+#define mmAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define mmAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x2284
+#define mmAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x2285
+#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT2_AFMT_MEM_PWR                                                                           0x2287
+#define mmAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
+// base address: 0x15d24
+#define mmDME2_DME_CONTROL                                                                             0x2289
+#define mmDME2_DME_CONTROL_BASE_IDX                                                                    2
+#define mmDME2_DME_MEMORY_CONTROL                                                                      0x228a
+#define mmDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig2_dispdec
+// base address: 0x800
+#define mmDIG2_DIG_FE_CNTL                                                                             0x228b
+#define mmDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define mmDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x228c
+#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define mmDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x228d
+#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define mmDIG2_DIG_CLOCK_PATTERN                                                                       0x228e
+#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define mmDIG2_DIG_TEST_PATTERN                                                                        0x228f
+#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define mmDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x2290
+#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define mmDIG2_DIG_FIFO_STATUS                                                                         0x2291
+#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define mmDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x2292
+#define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define mmDIG2_HDMI_CONTROL                                                                            0x2293
+#define mmDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
+#define mmDIG2_HDMI_STATUS                                                                             0x2294
+#define mmDIG2_HDMI_STATUS_BASE_IDX                                                                    2
+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2295
+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define mmDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2296
+#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2297
+#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2298
+#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define mmDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x2299
+#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x229a
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x229b
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x229c
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define mmDIG2_HDMI_GC                                                                                 0x229d
+#define mmDIG2_HDMI_GC_BASE_IDX                                                                        2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x229e
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x229f
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22a0
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22a1
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22a2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22a3
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22a4
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22a5
+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define mmDIG2_HDMI_DB_CONTROL                                                                         0x22a6
+#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define mmDIG2_HDMI_ACR_32_0                                                                           0x22a7
+#define mmDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define mmDIG2_HDMI_ACR_32_1                                                                           0x22a8
+#define mmDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define mmDIG2_HDMI_ACR_44_0                                                                           0x22a9
+#define mmDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define mmDIG2_HDMI_ACR_44_1                                                                           0x22aa
+#define mmDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define mmDIG2_HDMI_ACR_48_0                                                                           0x22ab
+#define mmDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define mmDIG2_HDMI_ACR_48_1                                                                           0x22ac
+#define mmDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define mmDIG2_HDMI_ACR_STATUS_0                                                                       0x22ad
+#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define mmDIG2_HDMI_ACR_STATUS_1                                                                       0x22ae
+#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define mmDIG2_AFMT_CNTL                                                                               0x22af
+#define mmDIG2_AFMT_CNTL_BASE_IDX                                                                      2
+#define mmDIG2_DIG_BE_CNTL                                                                             0x22b0
+#define mmDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define mmDIG2_DIG_BE_EN_CNTL                                                                          0x22b1
+#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define mmDIG2_TMDS_CNTL                                                                               0x22d7
+#define mmDIG2_TMDS_CNTL_BASE_IDX                                                                      2
+#define mmDIG2_TMDS_CONTROL_CHAR                                                                       0x22d8
+#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define mmDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22d9
+#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22da
+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22db
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22dc
+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define mmDIG2_TMDS_CTL_BITS                                                                           0x22de
+#define mmDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define mmDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22df
+#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22e0
+#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define mmDIG2_DIG_VERSION                                                                             0x22e4
+#define mmDIG2_DIG_VERSION_BASE_IDX                                                                    2
+#define mmDIG2_DIG_LANE_ENABLE                                                                         0x22e5
+#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX                                                                2
+#define mmDIG2_FORCE_DIG_DISABLE                                                                       0x22e6
+#define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp2_dispdec
+// base address: 0x800
+#define mmDP2_DP_LINK_CNTL                                                                             0x2308
+#define mmDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define mmDP2_DP_PIXEL_FORMAT                                                                          0x2309
+#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define mmDP2_DP_MSA_COLORIMETRY                                                                       0x230a
+#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define mmDP2_DP_CONFIG                                                                                0x230b
+#define mmDP2_DP_CONFIG_BASE_IDX                                                                       2
+#define mmDP2_DP_VID_STREAM_CNTL                                                                       0x230c
+#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define mmDP2_DP_STEER_FIFO                                                                            0x230d
+#define mmDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define mmDP2_DP_MSA_MISC                                                                              0x230e
+#define mmDP2_DP_MSA_MISC_BASE_IDX                                                                     2
+#define mmDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x230f
+#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define mmDP2_DP_VID_TIMING                                                                            0x2310
+#define mmDP2_DP_VID_TIMING_BASE_IDX                                                                   2
+#define mmDP2_DP_VID_N                                                                                 0x2311
+#define mmDP2_DP_VID_N_BASE_IDX                                                                        2
+#define mmDP2_DP_VID_M                                                                                 0x2312
+#define mmDP2_DP_VID_M_BASE_IDX                                                                        2
+#define mmDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
+#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define mmDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
+#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define mmDP2_DP_VID_MSA_VBID                                                                          0x2315
+#define mmDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define mmDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
+#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define mmDP2_DP_DPHY_CNTL                                                                             0x2317
+#define mmDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define mmDP2_DP_DPHY_SYM0                                                                             0x2319
+#define mmDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define mmDP2_DP_DPHY_SYM1                                                                             0x231a
+#define mmDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define mmDP2_DP_DPHY_SYM2                                                                             0x231b
+#define mmDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define mmDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
+#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define mmDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
+#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define mmDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
+#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define mmDP2_DP_DPHY_CRC_EN                                                                           0x231f
+#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define mmDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
+#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define mmDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
+#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define mmDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
+#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define mmDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
+#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define mmDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
+#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define mmDP2_DP_SEC_CNTL                                                                              0x232b
+#define mmDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define mmDP2_DP_SEC_CNTL1                                                                             0x232c
+#define mmDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define mmDP2_DP_SEC_FRAMING1                                                                          0x232d
+#define mmDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define mmDP2_DP_SEC_FRAMING2                                                                          0x232e
+#define mmDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define mmDP2_DP_SEC_FRAMING3                                                                          0x232f
+#define mmDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define mmDP2_DP_SEC_FRAMING4                                                                          0x2330
+#define mmDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define mmDP2_DP_SEC_AUD_N                                                                             0x2331
+#define mmDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define mmDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
+#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define mmDP2_DP_SEC_AUD_M                                                                             0x2333
+#define mmDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define mmDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
+#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define mmDP2_DP_SEC_TIMESTAMP                                                                         0x2335
+#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define mmDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
+#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define mmDP2_DP_MSE_RATE_CNTL                                                                         0x2337
+#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define mmDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
+#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define mmDP2_DP_MSE_SAT0                                                                              0x233a
+#define mmDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define mmDP2_DP_MSE_SAT1                                                                              0x233b
+#define mmDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define mmDP2_DP_MSE_SAT2                                                                              0x233c
+#define mmDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define mmDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
+#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define mmDP2_DP_MSE_LINK_TIMING                                                                       0x233e
+#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define mmDP2_DP_MSE_MISC_CNTL                                                                         0x233f
+#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define mmDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
+#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define mmDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
+#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define mmDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
+#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define mmDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
+#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define mmDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
+#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define mmDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
+#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define mmDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
+#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define mmDP2_DP_MSO_CNTL                                                                              0x2350
+#define mmDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define mmDP2_DP_MSO_CNTL1                                                                             0x2351
+#define mmDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define mmDP2_DP_DSC_CNTL                                                                              0x2352
+#define mmDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define mmDP2_DP_SEC_CNTL2                                                                             0x2353
+#define mmDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define mmDP2_DP_SEC_CNTL3                                                                             0x2354
+#define mmDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define mmDP2_DP_SEC_CNTL4                                                                             0x2355
+#define mmDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define mmDP2_DP_SEC_CNTL5                                                                             0x2356
+#define mmDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define mmDP2_DP_SEC_CNTL6                                                                             0x2357
+#define mmDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define mmDP2_DP_SEC_CNTL7                                                                             0x2358
+#define mmDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define mmDP2_DP_DB_CNTL                                                                               0x2359
+#define mmDP2_DP_DB_CNTL_BASE_IDX                                                                      2
+#define mmDP2_DP_MSA_VBID_MISC                                                                         0x235a
+#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define mmDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
+#define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define mmDP2_DP_DSC_BYTES_PER_PIXEL                                                                   0x235c
+#define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define mmDP2_DP_ALPM_CNTL                                                                             0x235d
+#define mmDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define mmDP2_DP_GSP8_CNTL                                                                             0x235e
+#define mmDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define mmDP2_DP_GSP9_CNTL                                                                             0x235f
+#define mmDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define mmDP2_DP_GSP10_CNTL                                                                            0x2360
+#define mmDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define mmDP2_DP_GSP11_CNTL                                                                            0x2361
+#define mmDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define mmDP2_DP_GSP_EN_DB_STATUS                                                                      0x2362
+#define mmDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
+// base address: 0x160a0
+#define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2368
+#define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define mmVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x2369
+#define mmVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x236a
+#define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x236b
+#define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define mmVPG3_VPG_GENERIC_STATUS                                                                      0x236c
+#define mmVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define mmVPG3_VPG_MEM_PWR                                                                             0x236d
+#define mmVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x236e
+#define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define mmVPG3_VPG_ISRC1_2_DATA                                                                        0x236f
+#define mmVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define mmVPG3_VPG_MPEG_INFO0                                                                          0x2370
+#define mmVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define mmVPG3_VPG_MPEG_INFO1                                                                          0x2371
+#define mmVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
+// base address: 0x160cc
+#define mmAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x2374
+#define mmAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2375
+#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define mmAFMT3_AFMT_AUDIO_INFO0                                                                       0x2376
+#define mmAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define mmAFMT3_AFMT_AUDIO_INFO1                                                                       0x2377
+#define mmAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define mmAFMT3_AFMT_60958_0                                                                           0x2378
+#define mmAFMT3_AFMT_60958_0_BASE_IDX                                                                  2
+#define mmAFMT3_AFMT_60958_1                                                                           0x2379
+#define mmAFMT3_AFMT_60958_1_BASE_IDX                                                                  2
+#define mmAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x237a
+#define mmAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT3_AFMT_RAMP_CONTROL0                                                                     0x237b
+#define mmAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define mmAFMT3_AFMT_RAMP_CONTROL1                                                                     0x237c
+#define mmAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define mmAFMT3_AFMT_RAMP_CONTROL2                                                                     0x237d
+#define mmAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define mmAFMT3_AFMT_RAMP_CONTROL3                                                                     0x237e
+#define mmAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define mmAFMT3_AFMT_60958_2                                                                           0x237f
+#define mmAFMT3_AFMT_60958_2_BASE_IDX                                                                  2
+#define mmAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x2380
+#define mmAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define mmAFMT3_AFMT_STATUS                                                                            0x2381
+#define mmAFMT3_AFMT_STATUS_BASE_IDX                                                                   2
+#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x2382
+#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define mmAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x2383
+#define mmAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define mmAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x2384
+#define mmAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define mmAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x2385
+#define mmAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define mmAFMT3_AFMT_MEM_PWR                                                                           0x2387
+#define mmAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
+// base address: 0x16124
+#define mmDME3_DME_CONTROL                                                                             0x2389
+#define mmDME3_DME_CONTROL_BASE_IDX                                                                    2
+#define mmDME3_DME_MEMORY_CONTROL                                                                      0x238a
+#define mmDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig3_dispdec
+// base address: 0xc00
+#define mmDIG3_DIG_FE_CNTL                                                                             0x238b
+#define mmDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define mmDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x238c
+#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define mmDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x238d
+#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define mmDIG3_DIG_CLOCK_PATTERN                                                                       0x238e
+#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define mmDIG3_DIG_TEST_PATTERN                                                                        0x238f
+#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define mmDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2390
+#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define mmDIG3_DIG_FIFO_STATUS                                                                         0x2391
+#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define mmDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2392
+#define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define mmDIG3_HDMI_CONTROL                                                                            0x2393
+#define mmDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
+#define mmDIG3_HDMI_STATUS                                                                             0x2394
+#define mmDIG3_HDMI_STATUS_BASE_IDX                                                                    2
+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2395
+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define mmDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2396
+#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2397
+#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define mmDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2398
+#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define mmDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2399
+#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x239a
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x239b
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x239c
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define mmDIG3_HDMI_GC                                                                                 0x239d
+#define mmDIG3_HDMI_GC_BASE_IDX                                                                        2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x239e
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x239f
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x23a0
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x23a1
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x23a2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x23a3
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x23a4
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x23a5
+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define mmDIG3_HDMI_DB_CONTROL                                                                         0x23a6
+#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define mmDIG3_HDMI_ACR_32_0                                                                           0x23a7
+#define mmDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define mmDIG3_HDMI_ACR_32_1                                                                           0x23a8
+#define mmDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define mmDIG3_HDMI_ACR_44_0                                                                           0x23a9
+#define mmDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define mmDIG3_HDMI_ACR_44_1                                                                           0x23aa
+#define mmDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define mmDIG3_HDMI_ACR_48_0                                                                           0x23ab
+#define mmDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define mmDIG3_HDMI_ACR_48_1                                                                           0x23ac
+#define mmDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define mmDIG3_HDMI_ACR_STATUS_0                                                                       0x23ad
+#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define mmDIG3_HDMI_ACR_STATUS_1                                                                       0x23ae
+#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define mmDIG3_AFMT_CNTL                                                                               0x23af
+#define mmDIG3_AFMT_CNTL_BASE_IDX                                                                      2
+#define mmDIG3_DIG_BE_CNTL                                                                             0x23b0
+#define mmDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define mmDIG3_DIG_BE_EN_CNTL                                                                          0x23b1
+#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define mmDIG3_TMDS_CNTL                                                                               0x23d7
+#define mmDIG3_TMDS_CNTL_BASE_IDX                                                                      2
+#define mmDIG3_TMDS_CONTROL_CHAR                                                                       0x23d8
+#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define mmDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23d9
+#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23da
+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23db
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23dc
+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define mmDIG3_TMDS_CTL_BITS                                                                           0x23de
+#define mmDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define mmDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23df
+#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23e0
+#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define mmDIG3_DIG_VERSION                                                                             0x23e4
+#define mmDIG3_DIG_VERSION_BASE_IDX                                                                    2
+#define mmDIG3_DIG_LANE_ENABLE                                                                         0x23e5
+#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX                                                                2
+#define mmDIG3_FORCE_DIG_DISABLE                                                                       0x23e6
+#define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp3_dispdec
+// base address: 0xc00
+#define mmDP3_DP_LINK_CNTL                                                                             0x2408
+#define mmDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define mmDP3_DP_PIXEL_FORMAT                                                                          0x2409
+#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define mmDP3_DP_MSA_COLORIMETRY                                                                       0x240a
+#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define mmDP3_DP_CONFIG                                                                                0x240b
+#define mmDP3_DP_CONFIG_BASE_IDX                                                                       2
+#define mmDP3_DP_VID_STREAM_CNTL                                                                       0x240c
+#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define mmDP3_DP_STEER_FIFO                                                                            0x240d
+#define mmDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define mmDP3_DP_MSA_MISC                                                                              0x240e
+#define mmDP3_DP_MSA_MISC_BASE_IDX                                                                     2
+#define mmDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x240f
+#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define mmDP3_DP_VID_TIMING                                                                            0x2410
+#define mmDP3_DP_VID_TIMING_BASE_IDX                                                                   2
+#define mmDP3_DP_VID_N                                                                                 0x2411
+#define mmDP3_DP_VID_N_BASE_IDX                                                                        2
+#define mmDP3_DP_VID_M                                                                                 0x2412
+#define mmDP3_DP_VID_M_BASE_IDX                                                                        2
+#define mmDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
+#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define mmDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
+#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define mmDP3_DP_VID_MSA_VBID                                                                          0x2415
+#define mmDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define mmDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
+#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define mmDP3_DP_DPHY_CNTL                                                                             0x2417
+#define mmDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define mmDP3_DP_DPHY_SYM0                                                                             0x2419
+#define mmDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define mmDP3_DP_DPHY_SYM1                                                                             0x241a
+#define mmDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define mmDP3_DP_DPHY_SYM2                                                                             0x241b
+#define mmDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define mmDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
+#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define mmDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
+#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define mmDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
+#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define mmDP3_DP_DPHY_CRC_EN                                                                           0x241f
+#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define mmDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
+#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define mmDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
+#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define mmDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
+#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define mmDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
+#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define mmDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
+#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define mmDP3_DP_SEC_CNTL                                                                              0x242b
+#define mmDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define mmDP3_DP_SEC_CNTL1                                                                             0x242c
+#define mmDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define mmDP3_DP_SEC_FRAMING1                                                                          0x242d
+#define mmDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define mmDP3_DP_SEC_FRAMING2                                                                          0x242e
+#define mmDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define mmDP3_DP_SEC_FRAMING3                                                                          0x242f
+#define mmDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define mmDP3_DP_SEC_FRAMING4                                                                          0x2430
+#define mmDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define mmDP3_DP_SEC_AUD_N                                                                             0x2431
+#define mmDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define mmDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
+#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define mmDP3_DP_SEC_AUD_M                                                                             0x2433
+#define mmDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define mmDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
+#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define mmDP3_DP_SEC_TIMESTAMP                                                                         0x2435
+#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define mmDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
+#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define mmDP3_DP_MSE_RATE_CNTL                                                                         0x2437
+#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define mmDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
+#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define mmDP3_DP_MSE_SAT0                                                                              0x243a
+#define mmDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define mmDP3_DP_MSE_SAT1                                                                              0x243b
+#define mmDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define mmDP3_DP_MSE_SAT2                                                                              0x243c
+#define mmDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define mmDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
+#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define mmDP3_DP_MSE_LINK_TIMING                                                                       0x243e
+#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define mmDP3_DP_MSE_MISC_CNTL                                                                         0x243f
+#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define mmDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
+#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define mmDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
+#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define mmDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
+#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define mmDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
+#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define mmDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
+#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define mmDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
+#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define mmDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
+#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define mmDP3_DP_MSO_CNTL                                                                              0x2450
+#define mmDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define mmDP3_DP_MSO_CNTL1                                                                             0x2451
+#define mmDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define mmDP3_DP_DSC_CNTL                                                                              0x2452
+#define mmDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define mmDP3_DP_SEC_CNTL2                                                                             0x2453
+#define mmDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define mmDP3_DP_SEC_CNTL3                                                                             0x2454
+#define mmDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define mmDP3_DP_SEC_CNTL4                                                                             0x2455
+#define mmDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define mmDP3_DP_SEC_CNTL5                                                                             0x2456
+#define mmDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define mmDP3_DP_SEC_CNTL6                                                                             0x2457
+#define mmDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define mmDP3_DP_SEC_CNTL7                                                                             0x2458
+#define mmDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define mmDP3_DP_DB_CNTL                                                                               0x2459
+#define mmDP3_DP_DB_CNTL_BASE_IDX                                                                      2
+#define mmDP3_DP_MSA_VBID_MISC                                                                         0x245a
+#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define mmDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
+#define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define mmDP3_DP_DSC_BYTES_PER_PIXEL                                                                   0x245c
+#define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define mmDP3_DP_ALPM_CNTL                                                                             0x245d
+#define mmDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define mmDP3_DP_GSP8_CNTL                                                                             0x245e
+#define mmDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define mmDP3_DP_GSP9_CNTL                                                                             0x245f
+#define mmDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define mmDP3_DP_GSP10_CNTL                                                                            0x2460
+#define mmDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define mmDP3_DP_GSP11_CNTL                                                                            0x2461
+#define mmDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define mmDP3_DP_GSP_EN_DB_STATUS                                                                      0x2462
+#define mmDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+// base address: 0x0
+#define mmDC_GENERICA                                                                                  0x2868
+#define mmDC_GENERICA_BASE_IDX                                                                         2
+#define mmDC_GENERICB                                                                                  0x2869
+#define mmDC_GENERICB_BASE_IDX                                                                         2
+#define mmDCIO_CLOCK_CNTL                                                                              0x286a
+#define mmDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
+#define mmDC_REF_CLK_CNTL                                                                              0x286b
+#define mmDC_REF_CLK_CNTL_BASE_IDX                                                                     2
+#define mmUNIPHYA_LINK_CNTL                                                                            0x286d
+#define mmUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
+#define mmUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
+#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define mmUNIPHYB_LINK_CNTL                                                                            0x286f
+#define mmUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
+#define mmUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
+#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define mmUNIPHYC_LINK_CNTL                                                                            0x2871
+#define mmUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
+#define mmUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
+#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define mmUNIPHYD_LINK_CNTL                                                                            0x2873
+#define mmUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
+#define mmUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
+#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define mmDCIO_WRCMD_DELAY                                                                             0x287e
+#define mmDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
+#define mmDC_PINSTRAPS                                                                                 0x2880
+#define mmDC_PINSTRAPS_BASE_IDX                                                                        2
+#define mmPANEL_PWRSEQ0_CNTL                                                                           0x2883
+#define mmPANEL_PWRSEQ0_CNTL_BASE_IDX                                                                  2
+#define mmPANEL_PWRSEQ0_STATE                                                                          0x2884
+#define mmPANEL_PWRSEQ0_STATE_BASE_IDX                                                                 2
+#define mmPANEL_PWRSEQ0_REF_DIV                                                                        0x2885
+#define mmPANEL_PWRSEQ0_REF_DIV_BASE_IDX                                                               2
+#define mmPANEL_PWRSEQ0_DELAY1                                                                         0x2886
+#define mmPANEL_PWRSEQ0_DELAY1_BASE_IDX                                                                2
+#define mmPANEL_PWRSEQ0_DELAY2                                                                         0x2887
+#define mmPANEL_PWRSEQ0_DELAY2_BASE_IDX                                                                2
+#define mmBL_PWM0_CNTL                                                                                 0x2888
+#define mmBL_PWM0_CNTL_BASE_IDX                                                                        2
+#define mmBL_PWM0_CNTL2                                                                                0x2889
+#define mmBL_PWM0_CNTL2_BASE_IDX                                                                       2
+#define mmBL_PWM0_PERIOD_CNTL                                                                          0x288a
+#define mmBL_PWM0_PERIOD_CNTL_BASE_IDX                                                                 2
+#define mmBL_PWM0_GRP1_REG_LOCK                                                                        0x288b
+#define mmBL_PWM0_GRP1_REG_LOCK_BASE_IDX                                                               2
+#define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
+#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
+#define mmDCIO_SOFT_RESET                                                                              0x289e
+#define mmDCIO_SOFT_RESET_BASE_IDX                                                                     2
+#define mmPANEL_PWRSEQ1_CNTL                                                                           0x28a6
+#define mmPANEL_PWRSEQ1_CNTL_BASE_IDX                                                                  2
+#define mmPANEL_PWRSEQ1_STATE                                                                          0x28a7
+#define mmPANEL_PWRSEQ1_STATE_BASE_IDX                                                                 2
+#define mmPANEL_PWRSEQ1_REF_DIV                                                                        0x28a8
+#define mmPANEL_PWRSEQ1_REF_DIV_BASE_IDX                                                               2
+#define mmPANEL_PWRSEQ1_DELAY1                                                                         0x28a9
+#define mmPANEL_PWRSEQ1_DELAY1_BASE_IDX                                                                2
+#define mmPANEL_PWRSEQ1_DELAY2                                                                         0x28aa
+#define mmPANEL_PWRSEQ1_DELAY2_BASE_IDX                                                                2
+#define mmBL_PWM1_CNTL                                                                                 0x28ab
+#define mmBL_PWM1_CNTL_BASE_IDX                                                                        2
+#define mmBL_PWM1_CNTL2                                                                                0x28ac
+#define mmBL_PWM1_CNTL2_BASE_IDX                                                                       2
+#define mmBL_PWM1_PERIOD_CNTL                                                                          0x28ad
+#define mmBL_PWM1_PERIOD_CNTL_BASE_IDX                                                                 2
+#define mmBL_PWM1_GRP1_REG_LOCK                                                                        0x28ae
+#define mmBL_PWM1_GRP1_REG_LOCK_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+// base address: 0x0
+#define mmDC_GPIO_GENERIC_MASK                                                                         0x28c8
+#define mmDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
+#define mmDC_GPIO_GENERIC_A                                                                            0x28c9
+#define mmDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
+#define mmDC_GPIO_GENERIC_EN                                                                           0x28ca
+#define mmDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
+#define mmDC_GPIO_GENERIC_Y                                                                            0x28cb
+#define mmDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
+#define mmDC_GPIO_DDC1_MASK                                                                            0x28d0
+#define mmDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
+#define mmDC_GPIO_DDC1_A                                                                               0x28d1
+#define mmDC_GPIO_DDC1_A_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDC1_EN                                                                              0x28d2
+#define mmDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
+#define mmDC_GPIO_DDC1_Y                                                                               0x28d3
+#define mmDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDC2_MASK                                                                            0x28d4
+#define mmDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
+#define mmDC_GPIO_DDC2_A                                                                               0x28d5
+#define mmDC_GPIO_DDC2_A_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDC2_EN                                                                              0x28d6
+#define mmDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
+#define mmDC_GPIO_DDC2_Y                                                                               0x28d7
+#define mmDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDC3_MASK                                                                            0x28d8
+#define mmDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
+#define mmDC_GPIO_DDC3_A                                                                               0x28d9
+#define mmDC_GPIO_DDC3_A_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDC3_EN                                                                              0x28da
+#define mmDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
+#define mmDC_GPIO_DDC3_Y                                                                               0x28db
+#define mmDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDC4_MASK                                                                            0x28dc
+#define mmDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
+#define mmDC_GPIO_DDC4_A                                                                               0x28dd
+#define mmDC_GPIO_DDC4_A_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDC4_EN                                                                              0x28de
+#define mmDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
+#define mmDC_GPIO_DDC4_Y                                                                               0x28df
+#define mmDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
+#define mmDC_GPIO_DDCVGA_MASK                                                                          0x28e8
+#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
+#define mmDC_GPIO_DDCVGA_A                                                                             0x28e9
+#define mmDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
+#define mmDC_GPIO_DDCVGA_EN                                                                            0x28ea
+#define mmDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
+#define mmDC_GPIO_DDCVGA_Y                                                                             0x28eb
+#define mmDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
+#define mmDC_GPIO_GENLK_MASK                                                                           0x28f0
+#define mmDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
+#define mmDC_GPIO_GENLK_A                                                                              0x28f1
+#define mmDC_GPIO_GENLK_A_BASE_IDX                                                                     2
+#define mmDC_GPIO_GENLK_EN                                                                             0x28f2
+#define mmDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
+#define mmDC_GPIO_GENLK_Y                                                                              0x28f3
+#define mmDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
+#define mmDC_GPIO_HPD_MASK                                                                             0x28f4
+#define mmDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
+#define mmDC_GPIO_HPD_A                                                                                0x28f5
+#define mmDC_GPIO_HPD_A_BASE_IDX                                                                       2
+#define mmDC_GPIO_HPD_EN                                                                               0x28f6
+#define mmDC_GPIO_HPD_EN_BASE_IDX                                                                      2
+#define mmDC_GPIO_HPD_Y                                                                                0x28f7
+#define mmDC_GPIO_HPD_Y_BASE_IDX                                                                       2
+#define mmDC_GPIO_PWRSEQ0_MASK                                                                         0x28f8
+#define mmDC_GPIO_PWRSEQ0_MASK_BASE_IDX                                                                2
+#define mmDC_GPIO_PWRSEQ0_A                                                                            0x28f9
+#define mmDC_GPIO_PWRSEQ0_A_BASE_IDX                                                                   2
+#define mmDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
+#define mmDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
+#define mmDC_GPIO_PWRSEQ0_Y                                                                            0x28fb
+#define mmDC_GPIO_PWRSEQ0_Y_BASE_IDX                                                                   2
+#define mmDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
+#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
+#define mmDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
+#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
+#define mmPHY_AUX_CNTL                                                                                 0x28ff
+#define mmPHY_AUX_CNTL_BASE_IDX                                                                        2
+#define mmDC_GPIO_PWRSEQ1_MASK                                                                         0x2900
+#define mmDC_GPIO_PWRSEQ1_MASK_BASE_IDX                                                                2
+#define mmDC_GPIO_PWRSEQ1_A                                                                            0x2901
+#define mmDC_GPIO_PWRSEQ1_A_BASE_IDX                                                                   2
+#define mmDC_GPIO_PWRSEQ1_EN                                                                           0x2902
+#define mmDC_GPIO_PWRSEQ1_EN_BASE_IDX                                                                  2
+#define mmDC_GPIO_PWRSEQ1_Y                                                                            0x2903
+#define mmDC_GPIO_PWRSEQ1_Y_BASE_IDX                                                                   2
+#define mmDC_GPIO_TX12_EN                                                                              0x2915
+#define mmDC_GPIO_TX12_EN_BASE_IDX                                                                     2
+#define mmDC_GPIO_AUX_CTRL_0                                                                           0x2916
+#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
+#define mmDC_GPIO_AUX_CTRL_1                                                                           0x2917
+#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
+#define mmDC_GPIO_AUX_CTRL_2                                                                           0x2918
+#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
+#define mmDC_GPIO_RXEN                                                                                 0x2919
+#define mmDC_GPIO_RXEN_BASE_IDX                                                                        2
+#define mmDC_GPIO_PULLUPEN                                                                             0x291a
+#define mmDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
+#define mmDC_GPIO_AUX_CTRL_3                                                                           0x291b
+#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
+#define mmDC_GPIO_AUX_CTRL_4                                                                           0x291c
+#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
+#define mmDC_GPIO_AUX_CTRL_5                                                                           0x291d
+#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
+#define mmAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
+#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
+// base address: 0x360
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
+#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
+// base address: 0x6c0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
+#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
+// base address: 0xa20
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
+#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+// base address: 0x0
+#define mmDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
+#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define mmDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
+#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+// base address: 0x0
+#define mmDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
+#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define mmDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
+#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+// base address: 0x0
+#define mmDSCC0_DSCC_CONFIG0                                                                           0x300a
+#define mmDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define mmDSCC0_DSCC_CONFIG1                                                                           0x300b
+#define mmDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define mmDSCC0_DSCC_STATUS                                                                            0x300c
+#define mmDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
+#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
+#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define mmDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
+#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
+#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
+#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
+#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
+#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
+#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
+#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
+#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
+#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
+#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define mmDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
+#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
+#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
+#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
+#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
+#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
+#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
+#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
+#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
+#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
+#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
+#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
+#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
+#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define mmDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
+#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define mmDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
+#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define mmDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
+#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
+#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
+#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
+#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
+#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a
+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc140
+#define mmDC_PERFMON17_PERFCOUNTER_CNTL                                                                0x3050
+#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON17_PERFCOUNTER_CNTL2                                                               0x3051
+#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON17_PERFCOUNTER_STATE                                                               0x3052
+#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON17_PERFMON_CNTL                                                                    0x3053
+#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON17_PERFMON_CNTL2                                                                   0x3054
+#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC                                                         0x3055
+#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON17_PERFMON_CVALUE_LOW                                                              0x3056
+#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON17_PERFMON_HI                                                                      0x3057
+#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON17_PERFMON_LOW                                                                     0x3058
+#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+// base address: 0x170
+#define mmDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
+#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define mmDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
+#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+// base address: 0x170
+#define mmDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
+#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define mmDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
+#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+// base address: 0x170
+#define mmDSCC1_DSCC_CONFIG0                                                                           0x3066
+#define mmDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define mmDSCC1_DSCC_CONFIG1                                                                           0x3067
+#define mmDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define mmDSCC1_DSCC_STATUS                                                                            0x3068
+#define mmDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
+#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
+#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define mmDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
+#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
+#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
+#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
+#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
+#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
+#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
+#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
+#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
+#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
+#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define mmDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
+#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
+#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
+#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
+#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
+#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
+#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
+#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
+#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
+#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
+#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
+#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
+#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
+#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define mmDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
+#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define mmDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
+#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define mmDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
+#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
+#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
+#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
+#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
+#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096
+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc2b0
+#define mmDC_PERFMON18_PERFCOUNTER_CNTL                                                                0x30ac
+#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON18_PERFCOUNTER_CNTL2                                                               0x30ad
+#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON18_PERFCOUNTER_STATE                                                               0x30ae
+#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON18_PERFMON_CNTL                                                                    0x30af
+#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON18_PERFMON_CNTL2                                                                   0x30b0
+#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC                                                         0x30b1
+#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON18_PERFMON_CVALUE_LOW                                                              0x30b2
+#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON18_PERFMON_HI                                                                      0x30b3
+#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON18_PERFMON_LOW                                                                     0x30b4
+#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
+// base address: 0x2e0
+#define mmDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
+#define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define mmDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
+#define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
+// base address: 0x2e0
+#define mmDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
+#define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define mmDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
+#define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
+// base address: 0x2e0
+#define mmDSCC2_DSCC_CONFIG0                                                                           0x30c2
+#define mmDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define mmDSCC2_DSCC_CONFIG1                                                                           0x30c3
+#define mmDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define mmDSCC2_DSCC_STATUS                                                                            0x30c4
+#define mmDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
+#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
+#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define mmDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
+#define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define mmDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
+#define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define mmDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
+#define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define mmDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
+#define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define mmDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
+#define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define mmDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
+#define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define mmDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
+#define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define mmDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
+#define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define mmDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
+#define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define mmDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
+#define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define mmDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
+#define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
+#define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
+#define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
+#define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
+#define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
+#define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
+#define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
+#define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
+#define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
+#define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
+#define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
+#define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
+#define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define mmDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
+#define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define mmDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
+#define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define mmDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
+#define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
+#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
+#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
+#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
+#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2
+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc420
+#define mmDC_PERFMON19_PERFCOUNTER_CNTL                                                                0x3108
+#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON19_PERFCOUNTER_CNTL2                                                               0x3109
+#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON19_PERFCOUNTER_STATE                                                               0x310a
+#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON19_PERFMON_CNTL                                                                    0x310b
+#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON19_PERFMON_CNTL2                                                                   0x310c
+#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC                                                         0x310d
+#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON19_PERFMON_CVALUE_LOW                                                              0x310e
+#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON19_PERFMON_HI                                                                      0x310f
+#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON19_PERFMON_LOW                                                                     0x3110
+#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
+// base address: 0x0
+#define mmDWB_ENABLE_CLK_CTRL                                                                          0x3228
+#define mmDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
+#define mmDWB_MEM_PWR_CTRL                                                                             0x3229
+#define mmDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define mmFC_MODE_CTRL                                                                                 0x322a
+#define mmFC_MODE_CTRL_BASE_IDX                                                                        2
+#define mmFC_FLOW_CTRL                                                                                 0x322b
+#define mmFC_FLOW_CTRL_BASE_IDX                                                                        2
+#define mmFC_WINDOW_START                                                                              0x322c
+#define mmFC_WINDOW_START_BASE_IDX                                                                     2
+#define mmFC_WINDOW_SIZE                                                                               0x322d
+#define mmFC_WINDOW_SIZE_BASE_IDX                                                                      2
+#define mmFC_SOURCE_SIZE                                                                               0x322e
+#define mmFC_SOURCE_SIZE_BASE_IDX                                                                      2
+#define mmDWB_UPDATE_CTRL                                                                              0x322f
+#define mmDWB_UPDATE_CTRL_BASE_IDX                                                                     2
+#define mmDWB_CRC_CTRL                                                                                 0x3230
+#define mmDWB_CRC_CTRL_BASE_IDX                                                                        2
+#define mmDWB_CRC_MASK_R_G                                                                             0x3231
+#define mmDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
+#define mmDWB_CRC_MASK_B_A                                                                             0x3232
+#define mmDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
+#define mmDWB_CRC_VAL_R_G                                                                              0x3233
+#define mmDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
+#define mmDWB_CRC_VAL_B_A                                                                              0x3234
+#define mmDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
+#define mmDWB_OUT_CTRL                                                                                 0x3235
+#define mmDWB_OUT_CTRL_BASE_IDX                                                                        2
+#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
+#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
+#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
+#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
+#define mmDWB_HOST_READ_CONTROL                                                                        0x3238
+#define mmDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
+#define mmDWB_OVERFLOW_STATUS                                                                          0x3239
+#define mmDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
+#define mmDWB_OVERFLOW_COUNTER                                                                         0x323a
+#define mmDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
+#define mmDWB_SOFT_RESET                                                                               0x323b
+#define mmDWB_SOFT_RESET_BASE_IDX                                                                      2
+#define mmDWB_DEBUG_CTRL                                                                               0x323c
+#define mmDWB_DEBUG_CTRL_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
+// base address: 0xca20
+#define mmDC_PERFMON20_PERFCOUNTER_CNTL                                                                0x3288
+#define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define mmDC_PERFMON20_PERFCOUNTER_CNTL2                                                               0x3289
+#define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define mmDC_PERFMON20_PERFCOUNTER_STATE                                                               0x328a
+#define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define mmDC_PERFMON20_PERFMON_CNTL                                                                    0x328b
+#define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX                                                           2
+#define mmDC_PERFMON20_PERFMON_CNTL2                                                                   0x328c
+#define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX                                                          2
+#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC                                                         0x328d
+#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define mmDC_PERFMON20_PERFMON_CVALUE_LOW                                                              0x328e
+#define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define mmDC_PERFMON20_PERFMON_HI                                                                      0x328f
+#define mmDC_PERFMON20_PERFMON_HI_BASE_IDX                                                             2
+#define mmDC_PERFMON20_PERFMON_LOW                                                                     0x3290
+#define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
+// base address: 0x0
+#define mmDWB_HDR_MULT_COEF                                                                            0x3294
+#define mmDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
+#define mmDWB_GAMUT_REMAP_MODE                                                                         0x3295
+#define mmDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
+#define mmDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
+#define mmDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
+#define mmDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
+#define mmDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
+#define mmDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
+#define mmDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
+#define mmDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
+#define mmDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
+#define mmDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
+#define mmDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
+#define mmDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
+#define mmDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
+#define mmDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
+#define mmDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
+#define mmDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
+#define mmDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
+#define mmDWB_OGAM_CONTROL                                                                             0x32a3
+#define mmDWB_OGAM_CONTROL_BASE_IDX                                                                    2
+#define mmDWB_OGAM_LUT_INDEX                                                                           0x32a4
+#define mmDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
+#define mmDWB_OGAM_LUT_DATA                                                                            0x32a5
+#define mmDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
+#define mmDWB_OGAM_LUT_CONTROL                                                                         0x32a6
+#define mmDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
+#define mmDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
+#define mmDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
+#define mmDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
+#define mmDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
+#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
+#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
+#define mmDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
+#define mmDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
+#define mmDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
+#define mmDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
+#define mmDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
+#define mmDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
+#define mmDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
+#define mmDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
+#define mmDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
+#define mmDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
+#define mmDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
+#define mmDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
+#define mmDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
+#define mmDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
+#define mmDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
+#define mmDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
+#define mmDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
+#define mmDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
+#define mmDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
+#define mmDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
+#define mmDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
+#define mmDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
+#define mmDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
+#define mmDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
+#define mmDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
+#define mmDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
+#define mmDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
+#define mmDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
+#define mmDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
+#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
+#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define mmDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
+#define mmDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
+#define mmDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
+#define mmDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
+#define mmDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
+#define mmDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
+#define mmDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
+#define mmDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
+#define mmDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
+#define mmDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
+#define mmDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
+#define mmDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
+#define mmDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
+#define mmDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
+#define mmDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
+#define mmDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
+#define mmDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
+#define mmDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
+#define mmDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
+#define mmDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
+#define mmDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
+#define mmDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
+#define mmDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
+#define mmDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
+#define mmDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
+#define mmDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
+#define mmDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
+#define mmDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
+#define mmDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
+#define mmDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
+#define mmDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dchvm_hvm_dispdec
+// base address: 0x0
+#define mmDCHVM_CTRL0                                                                                  0x3603
+#define mmDCHVM_CTRL0_BASE_IDX                                                                         2
+#define mmDCHVM_CTRL1                                                                                  0x3604
+#define mmDCHVM_CTRL1_BASE_IDX                                                                         2
+#define mmDCHVM_CLK_CTRL                                                                               0x3605
+#define mmDCHVM_CLK_CTRL_BASE_IDX                                                                      2
+#define mmDCHVM_MEM_CTRL                                                                               0x3606
+#define mmDCHVM_MEM_CTRL_BASE_IDX                                                                      2
+#define mmDCHVM_RIOMMU_CTRL0                                                                           0x3607
+#define mmDCHVM_RIOMMU_CTRL0_BASE_IDX                                                                  2
+#define mmDCHVM_RIOMMU_STAT0                                                                           0x3608
+#define mmDCHVM_RIOMMU_STAT0_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+// base address: 0x0
+#define mmMPCC0_MPCC_TOP_SEL                                                                           0x0000
+#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define mmMPCC0_MPCC_BOT_SEL                                                                           0x0001
+#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define mmMPCC0_MPCC_OPP_ID                                                                            0x0002
+#define mmMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define mmMPCC0_MPCC_CONTROL                                                                           0x0003
+#define mmMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
+#define mmMPCC0_MPCC_SM_CONTROL                                                                        0x0004
+#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define mmMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
+#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define mmMPCC0_MPCC_TOP_GAIN                                                                          0x0006
+#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define mmMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
+#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
+#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define mmMPCC0_MPCC_BG_R_CR                                                                           0x0009
+#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define mmMPCC0_MPCC_BG_G_Y                                                                            0x000a
+#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define mmMPCC0_MPCC_BG_B_CB                                                                           0x000b
+#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define mmMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000c
+#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define mmMPCC0_MPCC_STATUS                                                                            0x000d
+#define mmMPCC0_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+// base address: 0x80
+#define mmMPCC1_MPCC_TOP_SEL                                                                           0x0020
+#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define mmMPCC1_MPCC_BOT_SEL                                                                           0x0021
+#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define mmMPCC1_MPCC_OPP_ID                                                                            0x0022
+#define mmMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define mmMPCC1_MPCC_CONTROL                                                                           0x0023
+#define mmMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
+#define mmMPCC1_MPCC_SM_CONTROL                                                                        0x0024
+#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define mmMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x0025
+#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define mmMPCC1_MPCC_TOP_GAIN                                                                          0x0026
+#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define mmMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x0027
+#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0028
+#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define mmMPCC1_MPCC_BG_R_CR                                                                           0x0029
+#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define mmMPCC1_MPCC_BG_G_Y                                                                            0x002a
+#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define mmMPCC1_MPCC_BG_B_CB                                                                           0x002b
+#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define mmMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x002c
+#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define mmMPCC1_MPCC_STATUS                                                                            0x002d
+#define mmMPCC1_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc2_dispdec
+// base address: 0x100
+#define mmMPCC2_MPCC_TOP_SEL                                                                           0x0040
+#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define mmMPCC2_MPCC_BOT_SEL                                                                           0x0041
+#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define mmMPCC2_MPCC_OPP_ID                                                                            0x0042
+#define mmMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define mmMPCC2_MPCC_CONTROL                                                                           0x0043
+#define mmMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3
+#define mmMPCC2_MPCC_SM_CONTROL                                                                        0x0044
+#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define mmMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x0045
+#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define mmMPCC2_MPCC_TOP_GAIN                                                                          0x0046
+#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define mmMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0047
+#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0048
+#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define mmMPCC2_MPCC_BG_R_CR                                                                           0x0049
+#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define mmMPCC2_MPCC_BG_G_Y                                                                            0x004a
+#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define mmMPCC2_MPCC_BG_B_CB                                                                           0x004b
+#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define mmMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x004c
+#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define mmMPCC2_MPCC_STATUS                                                                            0x004d
+#define mmMPCC2_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc3_dispdec
+// base address: 0x180
+#define mmMPCC3_MPCC_TOP_SEL                                                                           0x0060
+#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define mmMPCC3_MPCC_BOT_SEL                                                                           0x0061
+#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define mmMPCC3_MPCC_OPP_ID                                                                            0x0062
+#define mmMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define mmMPCC3_MPCC_CONTROL                                                                           0x0063
+#define mmMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3
+#define mmMPCC3_MPCC_SM_CONTROL                                                                        0x0064
+#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define mmMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0065
+#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define mmMPCC3_MPCC_TOP_GAIN                                                                          0x0066
+#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define mmMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0067
+#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0068
+#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define mmMPCC3_MPCC_BG_R_CR                                                                           0x0069
+#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define mmMPCC3_MPCC_BG_G_Y                                                                            0x006a
+#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define mmMPCC3_MPCC_BG_B_CB                                                                           0x006b
+#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define mmMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x006c
+#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define mmMPCC3_MPCC_STATUS                                                                            0x006d
+#define mmMPCC3_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+// base address: 0x0
+#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x0100
+#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x0101
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x0102
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x0103
+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0104
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0105
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0106
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0107
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0108
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0109
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x010a
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x010b
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x010c
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x010d
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x010e
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x010f
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0110
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0111
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0112
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0113
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0114
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0115
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0116
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0117
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0118
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0119
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x011a
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x011b
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x011c
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x011d
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x011e
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x011f
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0120
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0121
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0122
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0123
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0124
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0125
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0126
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0127
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0128
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0129
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x012a
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x012b
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x012c
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x012d
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x012e
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x012f
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0130
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0131
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0132
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0133
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0134
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0135
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0136
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0137
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0138
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0139
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x013a
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x013b
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x013c
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x013d
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x013e
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x013f
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0140
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0141
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0142
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0143
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0144
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0145
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0146
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0147
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0148
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0149
+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x014a
+#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x014b
+#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x014c
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x014d
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x014e
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x014f
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0150
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0151
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0152
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0153
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0154
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0155
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0156
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0157
+#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+// base address: 0x200
+#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0180
+#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0181
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0182
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0183
+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0184
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0185
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0186
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0187
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0188
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0189
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x018a
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x018b
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x018c
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x018d
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x018e
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x018f
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0190
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0191
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0192
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0193
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0194
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0195
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0196
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0197
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0198
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0199
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x019a
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x019b
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x019c
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x019d
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x019e
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x019f
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01a0
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01a1
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01a2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01a3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01a4
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01a5
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01a6
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01a7
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01a8
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01a9
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01aa
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ab
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ac
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ad
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01ae
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01af
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01b0
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01b1
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01b2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01b3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01b4
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01b5
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01b6
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01b7
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01b8
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01b9
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01ba
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01bb
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01bc
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01bd
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01be
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01bf
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01c0
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01c1
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01c2
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01c3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01c4
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01c5
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01c6
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01c7
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01c8
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01c9
+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ca
+#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x01cb
+#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01cc
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01cd
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01ce
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01cf
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01d0
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01d1
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01d2
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01d3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01d4
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01d5
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01d6
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01d7
+#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
+// base address: 0x400
+#define mmMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0200
+#define mmMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0201
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0202
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0203
+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0204
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0205
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0206
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0207
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0208
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0209
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x020a
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x020b
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x020c
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x020d
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x020e
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x020f
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0210
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0211
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0212
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0213
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0214
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0215
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0216
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0217
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0218
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0219
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x021a
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x021b
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x021c
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x021d
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x021e
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x021f
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0220
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0221
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0222
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0223
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0224
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0225
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0226
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0227
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0228
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0229
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x022a
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x022b
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x022c
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x022d
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x022e
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x022f
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0230
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0231
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0232
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0233
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0234
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0235
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0236
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0237
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0238
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0239
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x023a
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x023b
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x023c
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x023d
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x023e
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x023f
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0240
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0241
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0242
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0243
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0244
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0245
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0246
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0247
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0248
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0249
+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x024a
+#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x024b
+#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x024c
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x024d
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x024e
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x024f
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0250
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0251
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0252
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0253
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0254
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0255
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0256
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0257
+#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
+// base address: 0x600
+#define mmMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x0280
+#define mmMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x0281
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x0282
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x0283
+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0284
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0285
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0286
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0287
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0288
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0289
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x028a
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x028b
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x028c
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x028d
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x028e
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x028f
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0290
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0291
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0292
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0293
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0294
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0295
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0296
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0297
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0298
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0299
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x029a
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x029b
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x029c
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x029d
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x029e
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x029f
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x02a0
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x02a1
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x02a2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x02a3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x02a4
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x02a5
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x02a6
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x02a7
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x02a8
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x02a9
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x02aa
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x02ab
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x02ac
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x02ad
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x02ae
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x02af
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x02b0
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x02b1
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x02b2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x02b3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x02b4
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x02b5
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x02b6
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x02b7
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x02b8
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x02b9
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x02ba
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x02bb
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x02bc
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x02bd
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x02be
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x02bf
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x02c0
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x02c1
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x02c2
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x02c3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x02c4
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x02c5
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x02c6
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x02c7
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x02c8
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x02c9
+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x02ca
+#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x02cb
+#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x02cc
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x02cd
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x02ce
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x02cf
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x02d0
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x02d1
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x02d2
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x02d3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x02d4
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x02d5
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x02d6
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x02d7
+#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+// base address: 0x0
+#define mmMPC_CLOCK_CONTROL                                                                            0x0500
+#define mmMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
+#define mmMPC_SOFT_RESET                                                                               0x0501
+#define mmMPC_SOFT_RESET_BASE_IDX                                                                      3
+#define mmMPC_CRC_CTRL                                                                                 0x0502
+#define mmMPC_CRC_CTRL_BASE_IDX                                                                        3
+#define mmMPC_CRC_SEL_CONTROL                                                                          0x0503
+#define mmMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
+#define mmMPC_CRC_RESULT_AR                                                                            0x0504
+#define mmMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
+#define mmMPC_CRC_RESULT_GB                                                                            0x0505
+#define mmMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
+#define mmMPC_CRC_RESULT_C                                                                             0x0506
+#define mmMPC_CRC_RESULT_C_BASE_IDX                                                                    3
+#define mmMPC_PERFMON_EVENT_CTRL                                                                       0x0509
+#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              3
+#define mmMPC_BYPASS_BG_AR                                                                             0x050a
+#define mmMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
+#define mmMPC_BYPASS_BG_GB                                                                             0x050b
+#define mmMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
+#define mmMPC_HOST_READ_CONTROL                                                                        0x050c
+#define mmMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
+#define mmMPC_DPP_PENDING_STATUS                                                                       0x050d
+#define mmMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
+#define mmMPC_PENDING_STATUS_MISC                                                                      0x050e
+#define mmMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x050f
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
+#define mmADR_CFG_VUPDATE_LOCK_SET0                                                                    0x0510
+#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
+#define mmADR_VUPDATE_LOCK_SET0                                                                        0x0511
+#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define mmCFG_VUPDATE_LOCK_SET0                                                                        0x0512
+#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define mmCUR_VUPDATE_LOCK_SET0                                                                        0x0513
+#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x0514
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
+#define mmADR_CFG_VUPDATE_LOCK_SET1                                                                    0x0515
+#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
+#define mmADR_VUPDATE_LOCK_SET1                                                                        0x0516
+#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define mmCFG_VUPDATE_LOCK_SET1                                                                        0x0517
+#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define mmCUR_VUPDATE_LOCK_SET1                                                                        0x0518
+#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x0519
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3
+#define mmADR_CFG_VUPDATE_LOCK_SET2                                                                    0x051a
+#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3
+#define mmADR_VUPDATE_LOCK_SET2                                                                        0x051b
+#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define mmCFG_VUPDATE_LOCK_SET2                                                                        0x051c
+#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define mmCUR_VUPDATE_LOCK_SET2                                                                        0x051d
+#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x051e
+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3
+#define mmADR_CFG_VUPDATE_LOCK_SET3                                                                    0x051f
+#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3
+#define mmADR_VUPDATE_LOCK_SET3                                                                        0x0520
+#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define mmCFG_VUPDATE_LOCK_SET3                                                                        0x0521
+#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define mmCUR_VUPDATE_LOCK_SET3                                                                        0x0522
+#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define mmMPC_DWB0_MUX                                                                                 0x055c
+#define mmMPC_DWB0_MUX_BASE_IDX                                                                        3
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+// base address: 0x0
+#define mmMPC_OUT0_MUX                                                                                 0x0580
+#define mmMPC_OUT0_MUX_BASE_IDX                                                                        3
+#define mmMPC_OUT0_DENORM_CONTROL                                                                      0x0581
+#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3
+#define mmMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x0582
+#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define mmMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x0583
+#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define mmMPC_OUT1_MUX                                                                                 0x0584
+#define mmMPC_OUT1_MUX_BASE_IDX                                                                        3
+#define mmMPC_OUT1_DENORM_CONTROL                                                                      0x0585
+#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3
+#define mmMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x0586
+#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define mmMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x0587
+#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define mmMPC_OUT2_MUX                                                                                 0x0588
+#define mmMPC_OUT2_MUX_BASE_IDX                                                                        3
+#define mmMPC_OUT2_DENORM_CONTROL                                                                      0x0589
+#define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3
+#define mmMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x058a
+#define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define mmMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x058b
+#define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define mmMPC_OUT3_MUX                                                                                 0x058c
+#define mmMPC_OUT3_MUX_BASE_IDX                                                                        3
+#define mmMPC_OUT3_DENORM_CONTROL                                                                      0x058d
+#define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3
+#define mmMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x058e
+#define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define mmMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x058f
+#define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define mmMPC_OUT_CSC_COEF_FORMAT                                                                      0x0590
+#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3
+#define mmMPC_OUT0_CSC_MODE                                                                            0x0591
+#define mmMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3
+#define mmMPC_OUT0_CSC_C11_C12_A                                                                       0x0592
+#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C13_C14_A                                                                       0x0593
+#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C21_C22_A                                                                       0x0594
+#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C23_C24_A                                                                       0x0595
+#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C31_C32_A                                                                       0x0596
+#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C33_C34_A                                                                       0x0597
+#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C11_C12_B                                                                       0x0598
+#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C13_C14_B                                                                       0x0599
+#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C21_C22_B                                                                       0x059a
+#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C23_C24_B                                                                       0x059b
+#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C31_C32_B                                                                       0x059c
+#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3
+#define mmMPC_OUT0_CSC_C33_C34_B                                                                       0x059d
+#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_MODE                                                                            0x059e
+#define mmMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3
+#define mmMPC_OUT1_CSC_C11_C12_A                                                                       0x059f
+#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C13_C14_A                                                                       0x05a0
+#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C21_C22_A                                                                       0x05a1
+#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C23_C24_A                                                                       0x05a2
+#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C31_C32_A                                                                       0x05a3
+#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C33_C34_A                                                                       0x05a4
+#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C11_C12_B                                                                       0x05a5
+#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C13_C14_B                                                                       0x05a6
+#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C21_C22_B                                                                       0x05a7
+#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C23_C24_B                                                                       0x05a8
+#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C31_C32_B                                                                       0x05a9
+#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3
+#define mmMPC_OUT1_CSC_C33_C34_B                                                                       0x05aa
+#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_MODE                                                                            0x05ab
+#define mmMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3
+#define mmMPC_OUT2_CSC_C11_C12_A                                                                       0x05ac
+#define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_C13_C14_A                                                                       0x05ad
+#define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_C21_C22_A                                                                       0x05ae
+#define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_C23_C24_A                                                                       0x05af
+#define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_C31_C32_A                                                                       0x05b0
+#define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_C33_C34_A                                                                       0x05b1
+#define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_C11_C12_B                                                                       0x05b2
+#define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_C13_C14_B                                                                       0x05b3
+#define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_C21_C22_B                                                                       0x05b4
+#define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_C23_C24_B                                                                       0x05b5
+#define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_C31_C32_B                                                                       0x05b6
+#define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3
+#define mmMPC_OUT2_CSC_C33_C34_B                                                                       0x05b7
+#define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_MODE                                                                            0x05b8
+#define mmMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3
+#define mmMPC_OUT3_CSC_C11_C12_A                                                                       0x05b9
+#define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_C13_C14_A                                                                       0x05ba
+#define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_C21_C22_A                                                                       0x05bb
+#define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_C23_C24_A                                                                       0x05bc
+#define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_C31_C32_A                                                                       0x05bd
+#define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_C33_C34_A                                                                       0x05be
+#define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_C11_C12_B                                                                       0x05bf
+#define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_C13_C14_B                                                                       0x05c0
+#define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_C21_C22_B                                                                       0x05c1
+#define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_C23_C24_B                                                                       0x05c2
+#define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_C31_C32_B                                                                       0x05c3
+#define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3
+#define mmMPC_OUT3_CSC_C33_C34_B                                                                       0x05c4
+#define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3
+
+
+// addressBlock: dce_dc_mpc_mpc_rmu_dispdec
+// base address: 0x0
+#define mmMPC_RMU_CONTROL                                                                              0x0680
+#define mmMPC_RMU_CONTROL_BASE_IDX                                                                     3
+#define mmMPC_RMU_MEM_PWR_CTRL                                                                         0x0681
+#define mmMPC_RMU_MEM_PWR_CTRL_BASE_IDX                                                                3
+#define mmMPC_RMU0_SHAPER_CONTROL                                                                      0x0682
+#define mmMPC_RMU0_SHAPER_CONTROL_BASE_IDX                                                             3
+#define mmMPC_RMU0_SHAPER_OFFSET_R                                                                     0x0683
+#define mmMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX                                                            3
+#define mmMPC_RMU0_SHAPER_OFFSET_G                                                                     0x0684
+#define mmMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX                                                            3
+#define mmMPC_RMU0_SHAPER_OFFSET_B                                                                     0x0685
+#define mmMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX                                                            3
+#define mmMPC_RMU0_SHAPER_SCALE_R                                                                      0x0686
+#define mmMPC_RMU0_SHAPER_SCALE_R_BASE_IDX                                                             3
+#define mmMPC_RMU0_SHAPER_SCALE_G_B                                                                    0x0687
+#define mmMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX                                                           3
+#define mmMPC_RMU0_SHAPER_LUT_INDEX                                                                    0x0688
+#define mmMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX                                                           3
+#define mmMPC_RMU0_SHAPER_LUT_DATA                                                                     0x0689
+#define mmMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX                                                            3
+#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK                                                            0x068a
+#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B                                                            0x068b
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G                                                            0x068c
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R                                                            0x068d
+#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B                                                              0x068e
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G                                                              0x068f
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R                                                              0x0690
+#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1                                                              0x0691
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3                                                              0x0692
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5                                                              0x0693
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7                                                              0x0694
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9                                                              0x0695
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11                                                            0x0696
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13                                                            0x0697
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15                                                            0x0698
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17                                                            0x0699
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19                                                            0x069a
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21                                                            0x069b
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23                                                            0x069c
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25                                                            0x069d
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27                                                            0x069e
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29                                                            0x069f
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31                                                            0x06a0
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33                                                            0x06a1
+#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B                                                            0x06a2
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G                                                            0x06a3
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R                                                            0x06a4
+#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B                                                              0x06a5
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G                                                              0x06a6
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R                                                              0x06a7
+#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1                                                              0x06a8
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3                                                              0x06a9
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5                                                              0x06aa
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7                                                              0x06ab
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9                                                              0x06ac
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11                                                            0x06ad
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13                                                            0x06ae
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15                                                            0x06af
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17                                                            0x06b0
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19                                                            0x06b1
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21                                                            0x06b2
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23                                                            0x06b3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25                                                            0x06b4
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27                                                            0x06b5
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29                                                            0x06b6
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31                                                            0x06b7
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33                                                            0x06b8
+#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
+#define mmMPC_RMU0_3DLUT_MODE                                                                          0x06b9
+#define mmMPC_RMU0_3DLUT_MODE_BASE_IDX                                                                 3
+#define mmMPC_RMU0_3DLUT_INDEX                                                                         0x06ba
+#define mmMPC_RMU0_3DLUT_INDEX_BASE_IDX                                                                3
+#define mmMPC_RMU0_3DLUT_DATA                                                                          0x06bb
+#define mmMPC_RMU0_3DLUT_DATA_BASE_IDX                                                                 3
+#define mmMPC_RMU0_3DLUT_DATA_30BIT                                                                    0x06bc
+#define mmMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX                                                           3
+#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL                                                            0x06bd
+#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
+#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR                                                               0x06be
+#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R                                                                  0x06bf
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G                                                                  0x06c0
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B                                                                  0x06c1
+#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
+#define mmMPC_RMU1_SHAPER_CONTROL                                                                      0x06c2
+#define mmMPC_RMU1_SHAPER_CONTROL_BASE_IDX                                                             3
+#define mmMPC_RMU1_SHAPER_OFFSET_R                                                                     0x06c3
+#define mmMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX                                                            3
+#define mmMPC_RMU1_SHAPER_OFFSET_G                                                                     0x06c4
+#define mmMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX                                                            3
+#define mmMPC_RMU1_SHAPER_OFFSET_B                                                                     0x06c5
+#define mmMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX                                                            3
+#define mmMPC_RMU1_SHAPER_SCALE_R                                                                      0x06c6
+#define mmMPC_RMU1_SHAPER_SCALE_R_BASE_IDX                                                             3
+#define mmMPC_RMU1_SHAPER_SCALE_G_B                                                                    0x06c7
+#define mmMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX                                                           3
+#define mmMPC_RMU1_SHAPER_LUT_INDEX                                                                    0x06c8
+#define mmMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX                                                           3
+#define mmMPC_RMU1_SHAPER_LUT_DATA                                                                     0x06c9
+#define mmMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX                                                            3
+#define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK                                                            0x06ca
+#define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B                                                            0x06cb
+#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G                                                            0x06cc
+#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R                                                            0x06cd
+#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B                                                              0x06ce
+#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G                                                              0x06cf
+#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R                                                              0x06d0
+#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1                                                              0x06d1
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3                                                              0x06d2
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5                                                              0x06d3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7                                                              0x06d4
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9                                                              0x06d5
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11                                                            0x06d6
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13                                                            0x06d7
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15                                                            0x06d8
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17                                                            0x06d9
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19                                                            0x06da
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21                                                            0x06db
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23                                                            0x06dc
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25                                                            0x06dd
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27                                                            0x06de
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29                                                            0x06df
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31                                                            0x06e0
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33                                                            0x06e1
+#define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B                                                            0x06e2
+#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G                                                            0x06e3
+#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R                                                            0x06e4
+#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B                                                              0x06e5
+#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G                                                              0x06e6
+#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R                                                              0x06e7
+#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1                                                              0x06e8
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3                                                              0x06e9
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5                                                              0x06ea
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7                                                              0x06eb
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9                                                              0x06ec
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11                                                            0x06ed
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13                                                            0x06ee
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15                                                            0x06ef
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17                                                            0x06f0
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19                                                            0x06f1
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21                                                            0x06f2
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23                                                            0x06f3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25                                                            0x06f4
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27                                                            0x06f5
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29                                                            0x06f6
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31                                                            0x06f7
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33                                                            0x06f8
+#define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
+#define mmMPC_RMU1_3DLUT_MODE                                                                          0x06f9
+#define mmMPC_RMU1_3DLUT_MODE_BASE_IDX                                                                 3
+#define mmMPC_RMU1_3DLUT_INDEX                                                                         0x06fa
+#define mmMPC_RMU1_3DLUT_INDEX_BASE_IDX                                                                3
+#define mmMPC_RMU1_3DLUT_DATA                                                                          0x06fb
+#define mmMPC_RMU1_3DLUT_DATA_BASE_IDX                                                                 3
+#define mmMPC_RMU1_3DLUT_DATA_30BIT                                                                    0x06fc
+#define mmMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX                                                           3
+#define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL                                                            0x06fd
+#define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
+#define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR                                                               0x06fe
+#define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
+#define mmMPC_RMU1_3DLUT_OUT_OFFSET_R                                                                  0x06ff
+#define mmMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
+#define mmMPC_RMU1_3DLUT_OUT_OFFSET_G                                                                  0x0700
+#define mmMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
+#define mmMPC_RMU1_3DLUT_OUT_OFFSET_B                                                                  0x0701
+#define mmMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1901c
+#define mmDC_PERFMON21_PERFCOUNTER_CNTL                                                                0x08c7
+#define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX                                                       3
+#define mmDC_PERFMON21_PERFCOUNTER_CNTL2                                                               0x08c8
+#define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
+#define mmDC_PERFMON21_PERFCOUNTER_STATE                                                               0x08c9
+#define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX                                                      3
+#define mmDC_PERFMON21_PERFMON_CNTL                                                                    0x08ca
+#define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX                                                           3
+#define mmDC_PERFMON21_PERFMON_CNTL2                                                                   0x08cb
+#define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX                                                          3
+#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC                                                         0x08cc
+#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
+#define mmDC_PERFMON21_PERFMON_CVALUE_LOW                                                              0x08cd
+#define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
+#define mmDC_PERFMON21_PERFMON_HI                                                                      0x08ce
+#define mmDC_PERFMON21_PERFMON_HI_BASE_IDX                                                             3
+#define mmDC_PERFMON21_PERFMON_LOW                                                                     0x08cf
+#define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX                                                            3
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+// base address: 0x0
+#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a
+#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define mmABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b
+#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c
+#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d
+#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e
+#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f
+#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define mmABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80
+#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81
+#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define mmABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82
+#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define mmABM0_DC_ABM1_CNTL                                                                            0x0e83
+#define mmABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84
+#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e
+#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define mmABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f
+#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90
+#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91
+#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92
+#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define mmABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93
+#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94
+#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95
+#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96
+#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97
+#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98
+#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99
+#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a
+#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b
+#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c
+#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d
+#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e
+#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f
+#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0
+#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1
+#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2
+#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3
+#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4
+#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5
+#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6
+#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define mmABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7
+#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8
+#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9
+#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa
+#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab
+#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac
+#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead
+#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae
+#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf
+#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0
+#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1
+#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2
+#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3
+#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4
+#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5
+#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define mmABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6
+#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm1_dispdec
+// base address: 0x104
+#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb
+#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define mmABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc
+#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd
+#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe
+#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf
+#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0
+#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define mmABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1
+#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2
+#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define mmABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3
+#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define mmABM1_DC_ABM1_CNTL                                                                            0x0ec4
+#define mmABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5
+#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf
+#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define mmABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0
+#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1
+#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2
+#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3
+#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define mmABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4
+#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5
+#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6
+#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7
+#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8
+#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9
+#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda
+#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb
+#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc
+#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd
+#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede
+#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf
+#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0
+#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1
+#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2
+#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3
+#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4
+#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5
+#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6
+#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7
+#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define mmABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8
+#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9
+#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea
+#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb
+#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec
+#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed
+#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee
+#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef
+#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0
+#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1
+#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2
+#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3
+#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4
+#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5
+#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6
+#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define mmABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7
+#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm2_dispdec
+// base address: 0x208
+#define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc
+#define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define mmABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd
+#define mmABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define mmABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe
+#define mmABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff
+#define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00
+#define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01
+#define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define mmABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02
+#define mmABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03
+#define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define mmABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04
+#define mmABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define mmABM2_DC_ABM1_CNTL                                                                            0x0f05
+#define mmABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define mmABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06
+#define mmABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10
+#define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define mmABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11
+#define mmABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12
+#define mmABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13
+#define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14
+#define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define mmABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15
+#define mmABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16
+#define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17
+#define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18
+#define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19
+#define mmABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a
+#define mmABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b
+#define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c
+#define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d
+#define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e
+#define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f
+#define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20
+#define mmABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define mmABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21
+#define mmABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define mmABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22
+#define mmABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define mmABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23
+#define mmABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define mmABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24
+#define mmABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define mmABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25
+#define mmABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define mmABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26
+#define mmABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define mmABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27
+#define mmABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define mmABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28
+#define mmABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define mmABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29
+#define mmABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a
+#define mmABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b
+#define mmABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c
+#define mmABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d
+#define mmABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e
+#define mmABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f
+#define mmABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30
+#define mmABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31
+#define mmABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32
+#define mmABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33
+#define mmABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34
+#define mmABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35
+#define mmABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36
+#define mmABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37
+#define mmABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define mmABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38
+#define mmABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm3_dispdec
+// base address: 0x30c
+#define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d
+#define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define mmABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e
+#define mmABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define mmABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f
+#define mmABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40
+#define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41
+#define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42
+#define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define mmABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43
+#define mmABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44
+#define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define mmABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45
+#define mmABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define mmABM3_DC_ABM1_CNTL                                                                            0x0f46
+#define mmABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define mmABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47
+#define mmABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51
+#define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define mmABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52
+#define mmABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53
+#define mmABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54
+#define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55
+#define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define mmABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56
+#define mmABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57
+#define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58
+#define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59
+#define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define mmABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a
+#define mmABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b
+#define mmABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c
+#define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d
+#define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e
+#define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f
+#define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60
+#define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define mmABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61
+#define mmABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define mmABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62
+#define mmABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define mmABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63
+#define mmABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define mmABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64
+#define mmABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define mmABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65
+#define mmABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define mmABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66
+#define mmABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define mmABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67
+#define mmABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define mmABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68
+#define mmABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define mmABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69
+#define mmABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define mmABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a
+#define mmABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b
+#define mmABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c
+#define mmABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d
+#define mmABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e
+#define mmABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f
+#define mmABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70
+#define mmABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71
+#define mmABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72
+#define mmABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73
+#define mmABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74
+#define mmABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75
+#define mmABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76
+#define mmABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77
+#define mmABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78
+#define mmABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define mmABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79
+#define mmABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: vga_vgaseqind
+// base address: 0x0
+#define ixSEQ00                                                                                        0x0000
+#define ixSEQ01                                                                                        0x0001
+#define ixSEQ02                                                                                        0x0002
+#define ixSEQ03                                                                                        0x0003
+#define ixSEQ04                                                                                        0x0004
+
+
+// addressBlock: vga_vgacrtind
+// base address: 0x0
+#define ixCRT00                                                                                        0x0000
+#define ixCRT01                                                                                        0x0001
+#define ixCRT02                                                                                        0x0002
+#define ixCRT03                                                                                        0x0003
+#define ixCRT04                                                                                        0x0004
+#define ixCRT05                                                                                        0x0005
+#define ixCRT06                                                                                        0x0006
+#define ixCRT07                                                                                        0x0007
+#define ixCRT08                                                                                        0x0008
+#define ixCRT09                                                                                        0x0009
+#define ixCRT0A                                                                                        0x000a
+#define ixCRT0B                                                                                        0x000b
+#define ixCRT0C                                                                                        0x000c
+#define ixCRT0D                                                                                        0x000d
+#define ixCRT0E                                                                                        0x000e
+#define ixCRT0F                                                                                        0x000f
+#define ixCRT10                                                                                        0x0010
+#define ixCRT11                                                                                        0x0011
+#define ixCRT12                                                                                        0x0012
+#define ixCRT13                                                                                        0x0013
+#define ixCRT14                                                                                        0x0014
+#define ixCRT15                                                                                        0x0015
+#define ixCRT16                                                                                        0x0016
+#define ixCRT17                                                                                        0x0017
+#define ixCRT18                                                                                        0x0018
+#define ixCRT1E                                                                                        0x001e
+#define ixCRT1F                                                                                        0x001f
+#define ixCRT22                                                                                        0x0022
+
+
+// addressBlock: vga_vgagrphind
+// base address: 0x0
+#define ixGRA00                                                                                        0x0000
+#define ixGRA01                                                                                        0x0001
+#define ixGRA02                                                                                        0x0002
+#define ixGRA03                                                                                        0x0003
+#define ixGRA04                                                                                        0x0004
+#define ixGRA05                                                                                        0x0005
+#define ixGRA06                                                                                        0x0006
+#define ixGRA07                                                                                        0x0007
+#define ixGRA08                                                                                        0x0008
+
+
+// addressBlock: vga_vgaattrind
+// base address: 0x0
+#define ixATTR00                                                                                       0x0000
+#define ixATTR01                                                                                       0x0001
+#define ixATTR02                                                                                       0x0002
+#define ixATTR03                                                                                       0x0003
+#define ixATTR04                                                                                       0x0004
+#define ixATTR05                                                                                       0x0005
+#define ixATTR06                                                                                       0x0006
+#define ixATTR07                                                                                       0x0007
+#define ixATTR08                                                                                       0x0008
+#define ixATTR09                                                                                       0x0009
+#define ixATTR0A                                                                                       0x000a
+#define ixATTR0B                                                                                       0x000b
+#define ixATTR0C                                                                                       0x000c
+#define ixATTR0D                                                                                       0x000d
+#define ixATTR0E                                                                                       0x000e
+#define ixATTR0F                                                                                       0x000f
+#define ixATTR10                                                                                       0x0010
+#define ixATTR11                                                                                       0x0011
+#define ixATTR12                                                                                       0x0012
+#define ixATTR13                                                                                       0x0013
+#define ixATTR14                                                                                       0x0014
+
+
+// addressBlock: azendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
+
+
+// addressBlock: azendpoint_descriptorind
+// base address: 0x0
+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001
+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002
+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003
+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004
+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005
+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006
+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007
+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008
+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009
+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a
+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b
+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c
+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d
+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e
+
+
+// addressBlock: azendpoint_sinkinfoind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
+#define ixSINK_DESCRIPTION0                                                                            0x0005
+#define ixSINK_DESCRIPTION1                                                                            0x0006
+#define ixSINK_DESCRIPTION2                                                                            0x0007
+#define ixSINK_DESCRIPTION3                                                                            0x0008
+#define ixSINK_DESCRIPTION4                                                                            0x0009
+#define ixSINK_DESCRIPTION5                                                                            0x000a
+#define ixSINK_DESCRIPTION6                                                                            0x000b
+#define ixSINK_DESCRIPTION7                                                                            0x000c
+#define ixSINK_DESCRIPTION8                                                                            0x000d
+#define ixSINK_DESCRIPTION9                                                                            0x000e
+#define ixSINK_DESCRIPTION10                                                                           0x000f
+#define ixSINK_DESCRIPTION11                                                                           0x0010
+#define ixSINK_DESCRIPTION12                                                                           0x0011
+#define ixSINK_DESCRIPTION13                                                                           0x0012
+#define ixSINK_DESCRIPTION14                                                                           0x0013
+#define ixSINK_DESCRIPTION15                                                                           0x0014
+#define ixSINK_DESCRIPTION16                                                                           0x0015
+#define ixSINK_DESCRIPTION17                                                                           0x0016
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azcrc0resultind
+// base address: 0x0
+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azf0controller_azcrc1resultind
+// base address: 0x0
+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azinputendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
+
+
+// addressBlock: azroot_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
+
+
+// addressBlock: azf0stream0_streamind
+// base address: 0x0
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream1_streamind
+// base address: 0x0
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream2_streamind
+// base address: 0x0
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream3_streamind
+// base address: 0x0
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream4_streamind
+// base address: 0x0
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream5_streamind
+// base address: 0x0
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream6_streamind
+// base address: 0x0
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream7_streamind
+// base address: 0x0
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream8_streamind
+// base address: 0x0
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream9_streamind
+// base address: 0x0
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream10_streamind
+// base address: 0x0
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream11_streamind
+// base address: 0x0
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream12_streamind
+// base address: 0x0
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream13_streamind
+// base address: 0x0
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream14_streamind
+// base address: 0x0
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream15_streamind
+// base address: 0x0
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0endpoint0_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint1_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint2_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint3_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint4_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint5_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint6_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint7_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h
new file mode 100644
index 000000000000..2a622c13817b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h
@@ -0,0 +1,53357 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_0_1_SH_MASK_HEADER
+#define _dcn_3_0_1_SH_MASK_HEADER
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+//GLOBAL_CAPABILITIES
+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT                                          0x0
+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                                      0x1
+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT                                 0x3
+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT                                         0x8
+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT                                        0xc
+#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK                                            0x0001L
+#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                        0x0006L
+#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK                                   0x00F8L
+#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK                                           0x0F00L
+#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK                                          0xF000L
+//MINOR_VERSION
+#define MINOR_VERSION__MINOR_VERSION__SHIFT                                                                   0x0
+#define MINOR_VERSION__MINOR_VERSION_MASK                                                                     0xFFL
+//MAJOR_VERSION
+#define MAJOR_VERSION__MAJOR_VERSION__SHIFT                                                                   0x0
+#define MAJOR_VERSION__MAJOR_VERSION_MASK                                                                     0xFFL
+//OUTPUT_PAYLOAD_CAPABILITY
+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                           0x0
+#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                             0xFFFFL
+//INPUT_PAYLOAD_CAPABILITY
+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                             0x0
+#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                               0xFFFFL
+//GLOBAL_CONTROL
+#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT                                                               0x0
+#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT                                                                  0x1
+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT                                             0x8
+#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK                                                                 0x00000001L
+#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK                                                                    0x00000002L
+#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK                                               0x00000100L
+//WAKE_ENABLE
+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT                                                             0x0
+#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK                                                               0x0001L
+//STATE_CHANGE_STATUS
+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT                                                       0x0
+#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK                                                         0x0001L
+//GLOBAL_STATUS
+#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT                                                                    0x1
+#define GLOBAL_STATUS__FLUSH_STATUS_MASK                                                                      0x00000002L
+//OUTPUT_STREAM_PAYLOAD_CAPABILITY
+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x0
+#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFFL
+//INPUT_STREAM_PAYLOAD_CAPABILITY
+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x0
+#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFFL
+//INTERRUPT_CONTROL
+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT                                                   0x0
+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT                                                   0x1
+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT                                                   0x2
+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT                                                   0x3
+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT                                                   0x4
+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT                                                   0x5
+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT                                                   0x6
+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT                                                   0x7
+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT                                                   0x8
+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT                                                   0x9
+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT                                                  0xa
+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT                                                  0xb
+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT                                                  0xc
+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT                                                  0xd
+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT                                                  0xe
+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT                                                  0xf
+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT                                                 0x1e
+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT                                                     0x1f
+#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK                                                     0x00000001L
+#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK                                                     0x00000002L
+#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK                                                     0x00000004L
+#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK                                                     0x00000008L
+#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK                                                     0x00000010L
+#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK                                                     0x00000020L
+#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK                                                     0x00000040L
+#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK                                                     0x00000080L
+#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK                                                     0x00000100L
+#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK                                                     0x00000200L
+#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK                                                    0x00000400L
+#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK                                                    0x00000800L
+#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK                                                    0x00001000L
+#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK                                                    0x00002000L
+#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK                                                    0x00004000L
+#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK                                                    0x00008000L
+#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK                                                   0x40000000L
+#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK                                                       0x80000000L
+//INTERRUPT_STATUS
+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT                                                    0x0
+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT                                                    0x1
+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT                                                    0x2
+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT                                                    0x3
+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT                                                    0x4
+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT                                                    0x5
+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT                                                    0x6
+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT                                                    0x7
+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT                                                    0x8
+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT                                                    0x9
+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT                                                   0xa
+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT                                                   0xb
+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT                                                   0xc
+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT                                                   0xd
+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT                                                   0xe
+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT                                                   0xf
+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT                                                  0x1e
+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT                                                      0x1f
+#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK                                                      0x00000001L
+#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK                                                      0x00000002L
+#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK                                                      0x00000004L
+#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK                                                      0x00000008L
+#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK                                                      0x00000010L
+#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK                                                      0x00000020L
+#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK                                                      0x00000040L
+#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK                                                      0x00000080L
+#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK                                                      0x00000100L
+#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK                                                      0x00000200L
+#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK                                                     0x00000400L
+#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK                                                     0x00000800L
+#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK                                                     0x00001000L
+#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK                                                     0x00002000L
+#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK                                                     0x00004000L
+#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK                                                     0x00008000L
+#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK                                                    0x40000000L
+#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK                                                        0x80000000L
+//WALL_CLOCK_COUNTER
+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT                                                         0x0
+#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK                                                           0xFFFFFFFFL
+//STREAM_SYNCHRONIZATION
+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT                                               0x0
+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT                                               0x1
+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT                                               0x2
+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT                                               0x3
+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT                                               0x4
+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT                                               0x5
+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT                                               0x6
+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT                                               0x7
+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT                                               0x8
+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT                                               0x9
+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT                                              0xa
+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT                                              0xb
+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT                                              0xc
+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT                                              0xd
+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT                                              0xe
+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT                                              0xf
+#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK                                                 0x00000001L
+#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK                                                 0x00000002L
+#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK                                                 0x00000004L
+#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK                                                 0x00000008L
+#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK                                                 0x00000010L
+#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK                                                 0x00000020L
+#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK                                                 0x00000040L
+#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK                                                 0x00000080L
+#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK                                                 0x00000100L
+#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK                                                 0x00000200L
+#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK                                                0x00000400L
+#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK                                                0x00000800L
+#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK                                                0x00001000L
+#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK                                                0x00002000L
+#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK                                                0x00004000L
+#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK                                                0x00008000L
+//CORB_LOWER_BASE_ADDRESS
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                                    0x0
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT                                               0x7
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                                      0x0000007FL
+#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK                                                 0xFFFFFF80L
+//CORB_UPPER_BASE_ADDRESS
+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT                                               0x0
+#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//CORB_WRITE_POINTER
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                                         0x0
+#define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                                           0x00FFL
+//CORB_READ_POINTER
+#define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                                           0x0
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                                     0xf
+#define CORB_READ_POINTER__CORB_READ_POINTER_MASK                                                             0x00FFL
+#define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                                       0x8000L
+//CORB_CONTROL
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x0
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                                           0x1
+#define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                                 0x01L
+#define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                                             0x02L
+//CORB_STATUS
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                                      0x0
+#define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                                        0x01L
+//CORB_SIZE
+#define CORB_SIZE__CORB_SIZE__SHIFT                                                                           0x0
+#define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                                0x4
+#define CORB_SIZE__CORB_SIZE_MASK                                                                             0x0003L
+#define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
+//RIRB_LOWER_BASE_ADDRESS
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                                    0x0
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                               0x7
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                                      0x0000007FL
+#define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                                 0xFFFFFF80L
+//RIRB_UPPER_BASE_ADDRESS
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                               0x0
+#define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//RIRB_WRITE_POINTER
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                                         0x0
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                                   0xf
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                                           0x00FFL
+#define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                                     0x8000L
+//RESPONSE_INTERRUPT_COUNT
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                                           0x0
+#define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                                             0x00FFL
+//RIRB_CONTROL
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                                       0x0
+#define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                                  0x1
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                               0x2
+#define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                                         0x01L
+#define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                                    0x02L
+#define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                                 0x04L
+//RIRB_STATUS
+#define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                                0x0
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                                 0x2
+#define RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                                  0x01L
+#define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                                   0x04L
+//RIRB_SIZE
+#define RIRB_SIZE__RIRB_SIZE__SHIFT                                                                           0x0
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                                0x4
+#define RIRB_SIZE__RIRB_SIZE_MASK                                                                             0x0003L
+#define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT                   0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT                      0x1c
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK                     0x0FFFFFFFL
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK                        0xF0000000L
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                               0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                                 0xFFFFFFFFL
+//IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                              0x0
+#define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                                0x0000FFFFL
+//IMMEDIATE_RESPONSE_INPUT_INTERFACE
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                                    0x0
+#define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                                      0xFFFFFFFFL
+//IMMEDIATE_COMMAND_STATUS
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                               0x0
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                               0x1
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                                 0x00000001L
+#define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                                 0x00000002L
+//DMA_POSITION_LOWER_BASE_ADDRESS
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                                    0x0
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                    0x1
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                               0x7
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                                      0x00000001L
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                      0x0000007EL
+#define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                                 0xFFFFFF80L
+//DMA_POSITION_UPPER_BASE_ADDRESS
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                               0x0
+#define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                                 0xFFFFFFFFL
+//WALL_CLOCK_COUNTER_ALIAS
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                                             0x0
+#define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                               0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                    0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                      0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                   0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                     0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                     0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                       0xFFFFFFFFL
+//AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                    0x0
+#define AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                      0x0001FFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
+//VGA_MEM_WRITE_PAGE_ADDR
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT                                              0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT                                              0x10
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK                                                0x000003FFL
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK                                                0x03FF0000L
+//VGA_MEM_READ_PAGE_ADDR
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT                                                0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT                                                0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK                                                  0x000003FFL
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK                                                  0x03FF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
+//CRTC8_IDX
+#define CRTC8_IDX__VCRTC_IDX__SHIFT                                                                           0x0
+#define CRTC8_IDX__VCRTC_IDX_MASK                                                                             0x3FL
+//CRTC8_DATA
+#define CRTC8_DATA__VCRTC_DATA__SHIFT                                                                         0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK                                                                           0xFFL
+//GENFC_WT
+#define GENFC_WT__VSYNC_SEL_W__SHIFT                                                                          0x3
+#define GENFC_WT__VSYNC_SEL_W_MASK                                                                            0x08L
+//GENS1
+#define GENS1__NO_DISPLAY__SHIFT                                                                              0x0
+#define GENS1__VGA_VSTATUS__SHIFT                                                                             0x3
+#define GENS1__PIXEL_READ_BACK__SHIFT                                                                         0x4
+#define GENS1__NO_DISPLAY_MASK                                                                                0x01L
+#define GENS1__VGA_VSTATUS_MASK                                                                               0x08L
+#define GENS1__PIXEL_READ_BACK_MASK                                                                           0x30L
+//ATTRDW
+#define ATTRDW__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDW__ATTR_DATA_MASK                                                                                0xFFL
+//ATTRX
+#define ATTRX__ATTR_IDX__SHIFT                                                                                0x0
+#define ATTRX__ATTR_IDX_MASK                                                                                  0x1FL
+//ATTRDR
+#define ATTRDR__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDR__ATTR_DATA_MASK                                                                                0xFFL
+//GENMO_WT
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_WT__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_WT__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_WT__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_WT__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_WT__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_WT__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GENS0
+#define GENS0__SENSE_SWITCH__SHIFT                                                                            0x4
+#define GENS0__CRT_INTR__SHIFT                                                                                0x7
+#define GENS0__SENSE_SWITCH_MASK                                                                              0x10L
+#define GENS0__CRT_INTR_MASK                                                                                  0x80L
+//GENENB
+//SEQ8_IDX
+#define SEQ8_IDX__SEQ_IDX__SHIFT                                                                              0x0
+#define SEQ8_IDX__SEQ_IDX_MASK                                                                                0x07L
+//SEQ8_DATA
+#define SEQ8_DATA__SEQ_DATA__SHIFT                                                                            0x0
+#define SEQ8_DATA__SEQ_DATA_MASK                                                                              0xFFL
+//DAC_MASK
+#define DAC_MASK__DAC_MASK__SHIFT                                                                             0x0
+#define DAC_MASK__DAC_MASK_MASK                                                                               0xFFL
+//DAC_R_INDEX
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT                                                                       0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK                                                                         0xFFL
+//DAC_W_INDEX
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT                                                                       0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK                                                                         0xFFL
+//DAC_DATA
+#define DAC_DATA__DAC_DATA__SHIFT                                                                             0x0
+#define DAC_DATA__DAC_DATA_MASK                                                                               0x3FL
+//GENFC_RD
+#define GENFC_RD__VSYNC_SEL_R__SHIFT                                                                          0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK                                                                            0x08L
+//GENMO_RD
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_RD__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_RD__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_RD__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_RD__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_RD__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_RD__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GRPH8_IDX
+#define GRPH8_IDX__GRPH_IDX__SHIFT                                                                            0x0
+#define GRPH8_IDX__GRPH_IDX_MASK                                                                              0x0FL
+//GRPH8_DATA
+#define GRPH8_DATA__GRPH_DATA__SHIFT                                                                          0x0
+#define GRPH8_DATA__GRPH_DATA_MASK                                                                            0xFFL
+//CRTC8_IDX_1
+#define CRTC8_IDX_1__VCRTC_IDX__SHIFT                                                                         0x0
+#define CRTC8_IDX_1__VCRTC_IDX_MASK                                                                           0x3FL
+//CRTC8_DATA_1
+#define CRTC8_DATA_1__VCRTC_DATA__SHIFT                                                                       0x0
+#define CRTC8_DATA_1__VCRTC_DATA_MASK                                                                         0xFFL
+//GENFC_WT_1
+#define GENFC_WT_1__VSYNC_SEL_W__SHIFT                                                                        0x3
+#define GENFC_WT_1__VSYNC_SEL_W_MASK                                                                          0x08L
+//GENS1_1
+#define GENS1_1__NO_DISPLAY__SHIFT                                                                            0x0
+#define GENS1_1__VGA_VSTATUS__SHIFT                                                                           0x3
+#define GENS1_1__PIXEL_READ_BACK__SHIFT                                                                       0x4
+#define GENS1_1__NO_DISPLAY_MASK                                                                              0x01L
+#define GENS1_1__VGA_VSTATUS_MASK                                                                             0x08L
+#define GENS1_1__PIXEL_READ_BACK_MASK                                                                         0x30L
+
+
+// addressBlock: dce_dc_hda_azstream0_azdec
+
+
+// addressBlock: dce_dc_hda_azstream1_azdec
+
+
+// addressBlock: dce_dc_hda_azstream2_azdec
+
+
+// addressBlock: dce_dc_hda_azstream3_azdec
+
+
+// addressBlock: dce_dc_hda_azstream4_azdec
+
+
+// addressBlock: dce_dc_hda_azstream5_azdec
+
+
+// addressBlock: dce_dc_hda_azstream6_azdec
+
+
+// addressBlock: dce_dc_hda_azstream7_azdec
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+//VGA_RENDER_CONTROL
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT                                                             0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT                                                             0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT                                                    0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT                                                 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT                                                           0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT                                                              0x18
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK                                                               0x0000001FL
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK                                                               0x00000060L
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK                                                      0x00000080L
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK                                                   0x00000100L
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK                                                             0x00030000L
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK                                                                0x01000000L
+//VGA_SEQUENCER_RESET_CONTROL
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT                                      0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT                             0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT                                0x12
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000001L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000002L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000004L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000008L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000010L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000020L
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000100L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000200L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000400L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000800L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00001000L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00002000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK                                        0x00010000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK                               0x00020000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK                                  0x00FC0000L
+//VGA_MODE_CONTROL
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT                                                               0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT                                                  0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT                                                     0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT                                                      0x10
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT                                                    0x18
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK                                                                 0x00000001L
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK                                                    0x00000030L
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK                                                       0x00000100L
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK                                                        0x00010000L
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK                                                      0x01000000L
+//VGA_SURFACE_PITCH_SELECT
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT                                             0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT                                            0x8
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK                                               0x00000003L
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK                                              0x00000300L
+//VGA_MEMORY_BASE_ADDRESS
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT                                               0x0
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//VGA_DISPBUF1_SURFACE_ADDR
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_DISPBUF2_SURFACE_ADDR
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_MEMORY_BASE_ADDRESS_HIGH
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT                                     0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK                                       0x0000FFFFL
+//VGA_HDP_CONTROL
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT                                                        0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT                                                            0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT                                                         0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT                                                                0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK                                                          0x00000001L
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK                                                              0x00000010L
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK                                                           0x00000100L
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK                                                                  0x00010000L
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK                                                          0x01000000L
+//VGA_CACHE_CONTROL
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT                                                 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT                                                      0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT                                                  0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT                                                          0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT                                                        0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK                                                   0x00000001L
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK                                                        0x00000100L
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK                                                    0x00010000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK                                                            0x00100000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK                                                          0x3F000000L
+//D1VGA_CONTROL
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT                                                                    0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK                                                                      0x03000000L
+//D2VGA_CONTROL
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT                                                                    0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_STATUS
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT                                                              0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT                                                              0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT                                                          0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT                                                       0x3
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK                                                                0x00000001L
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK                                                                0x00000002L
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK                                                            0x00000004L
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK                                                         0x00000008L
+//VGA_INTERRUPT_CONTROL
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT                                                 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT                                                 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT                                             0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT                                          0x18
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK                                                   0x00000001L
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK                                                   0x00000100L
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK                                               0x00010000L
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK                                            0x01000000L
+//VGA_STATUS_CLEAR
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT                                                     0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT                                                     0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT                                                 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT                                              0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK                                                       0x00000001L
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK                                                       0x00000100L
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK                                                   0x00010000L
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK                                                0x01000000L
+//VGA_INTERRUPT_STATUS
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT                                                0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT                                                0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT                                            0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT                                         0x3
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK                                                  0x00000001L
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK                                                  0x00000002L
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK                                              0x00000004L
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK                                           0x00000008L
+//VGA_MAIN_CONTROL
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT                                                             0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT                                                     0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT                                        0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT                                       0x8
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT                                                0xc
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT                                        0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT                                          0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT                                             0x1a
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT                                                       0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT                                0x1f
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK                                                               0x00000003L
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK                                                       0x00000018L
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK                                          0x000000E0L
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK                                         0x00000300L
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK                                                  0x0000F000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK                                          0x00030000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK                                            0x03000000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK                                               0x04000000L
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK                                                         0x20000000L
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK                                  0x80000000L
+//VGA_TEST_CONTROL
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT                                                              0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT                                                        0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT                                                         0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT                                               0x18
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK                                                                0x00000001L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK                                                          0x00000100L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK                                                           0x00010000L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK                                                 0x01000000L
+//VGA_QOS_CTRL
+#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT                                                                     0x0
+#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT                                                                    0x4
+#define VGA_QOS_CTRL__VGA_READ_QOS_MASK                                                                       0x0000000FL
+#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK                                                                      0x000000F0L
+//D3VGA_CONTROL
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT                                                                    0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK                                                                      0x03000000L
+//D4VGA_CONTROL
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT                                                                    0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK                                                                      0x03000000L
+//D5VGA_CONTROL
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT                                                                    0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK                                                                      0x03000000L
+//D6VGA_CONTROL
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT                                                                    0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_SOURCE_SELECT
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT                                                            0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT                                                            0x8
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK                                                              0x00000007L
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK                                                              0x00000700L
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+//PHYPLLA_PIXCLK_RESYNC_CNTL
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//PHYPLLB_PIXCLK_RESYNC_CNTL
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//PHYPLLC_PIXCLK_RESYNC_CNTL
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//PHYPLLD_PIXCLK_RESYNC_CNTL
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//DP_DTO_DBUF_EN
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L
+//DPREFCLK_CGTT_BLK_CTRL_REG
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L
+//REFCLK_CNTL
+#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT                                                                   0x0
+#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT                                                                    0x1
+#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK                                                                     0x00000001L
+#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK                                                                      0x00000002L
+//REFCLK_CGTT_BLK_CTRL_REG
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_PERFMON_CNTL2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT                                                    0x0
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT                                                    0x1
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT                                                   0x2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT                                                   0x3
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT                                            0x4
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT                                            0x5
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT                                            0x6
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT                                            0x7
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT                                            0x8
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK                                                      0x00000001L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK                                                      0x00000002L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK                                                     0x00000004L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK                                                     0x00000008L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK                                              0x00000010L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK                                              0x00000020L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK                                              0x00000040L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK                                              0x00000080L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK                                              0x00000100L
+//DCCG_DS_DTO_INCR
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL
+//DCCG_DS_DTO_MODULO
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT                                                         0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK                                                           0xFFFFFFFFL
+//DCCG_DS_CNTL
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT                                                                   0x0
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT                                                                  0x4
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT                                                            0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT                                                           0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT                                                        0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT                                                           0x19
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK                                                                     0x00000001L
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK                                                                    0x00000030L
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK                                                              0x00000100L
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK                                                             0x00000200L
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK                                                            0x00030000L
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK                                                          0x01000000L
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK                                                             0x02000000L
+//DCCG_DS_HW_CAL_INTERVAL
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT                                               0x0
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK                                                 0xFFFFFFFFL
+//DPREFCLK_CNTL
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L
+//DCE_VERSION
+#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0
+#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8
+#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL
+#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L
+//DCCG_GTC_CNTL
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT                                                                 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK                                                                   0x00000001L
+//DCCG_GTC_DTO_INCR
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT                                                           0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK                                                             0xFFFFFFFFL
+//DCCG_GTC_DTO_MODULO
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT                                                       0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK                                                         0xFFFFFFFFL
+//DCCG_GTC_CURRENT
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT                                                             0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK                                                               0xFFFFFFFFL
+//DSCCLK0_DTO_PARAM
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK1_DTO_PARAM
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK2_DTO_PARAM
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//MILLISECOND_TIME_BASE_DIV
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DISPCLK_FREQ_CHANGE_CNTL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L
+//DC_MEM_GLOBAL_PWR_REQ_CNTL
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L
+//DCCG_PERFMON_CNTL
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT                                                    0x0
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT                                                   0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT                                             0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT                                             0x3
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT                                                    0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT                                                               0x5
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT                                                        0x6
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT                                                        0x7
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT                                                           0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT                                                  0xb
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK                                                      0x00000001L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK                                                     0x00000002L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK                                               0x00000004L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK                                               0x00000008L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK                                                      0x00000010L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK                                                                 0x00000020L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK                                                          0x00000040L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK                                                          0x00000080L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK                                                             0x00000700L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK                                                    0xFFFFF800L
+//DCCG_GATE_DISABLE_CNTL
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT                                                  0xc
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT                                              0x16
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK                                                    0x00001000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK                                                0x00400000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L
+//DISPCLK_CGTT_BLK_CTRL_REG
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L
+//SOCCLK_CGTT_BLK_CTRL_REG
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_CAC_STATUS
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL
+//MICROSECOND_TIME_BASE_DIV
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DCCG_GATE_DISABLE_CNTL2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT                                             0x8
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT                                             0xc
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE__SHIFT                                               0x18
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE__SHIFT                                               0x19
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE__SHIFT                                               0x1a
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE__SHIFT                                               0x1b
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE__SHIFT                                               0x1c
+#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE__SHIFT                                               0x1d
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK                                               0x00000100L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK                                               0x00001000L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK                                               0x00002000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE_MASK                                                 0x01000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE_MASK                                                 0x02000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE_MASK                                                 0x04000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE_MASK                                                 0x08000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE_MASK                                                 0x10000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE_MASK                                                 0x20000000L
+//SYMCLK_CGTT_BLK_CTRL_REG
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_DISP_CNTL_REG
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L
+//OTG0_PIXEL_RATE_CNTL
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO0_PHASE
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO0_MODULO
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG0_PHYPLL_PIXEL_RATE_CNTL
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG1_PIXEL_RATE_CNTL
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO1_PHASE
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO1_MODULO
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG1_PHYPLL_PIXEL_RATE_CNTL
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG2_PIXEL_RATE_CNTL
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT                                                           0x4
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT                                                       0x5
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK                                                             0x00000010L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO2_PHASE
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT                                                                   0x0
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO2_MODULO
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT                                                                 0x0
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG2_PHYPLL_PIXEL_RATE_CNTL
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG3_PIXEL_RATE_CNTL
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT                                                           0x4
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT                                                       0x5
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK                                                             0x00000010L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+//DP_DTO3_PHASE
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT                                                                   0x0
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO3_MODULO
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT                                                                 0x0
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG3_PHYPLL_PIXEL_RATE_CNTL
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//DPPCLK_CGTT_BLK_CTRL_REG
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DPPCLK0_DTO_PARAM
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK1_DTO_PARAM
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK2_DTO_PARAM
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK3_DTO_PARAM
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK                                                            0x00FF0000L
+//DCCG_CAC_STATUS2
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x00001FFFL
+//SYMCLKA_CLOCK_ENABLE
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKB_CLOCK_ENABLE
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKC_CLOCK_ENABLE
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKD_CLOCK_ENABLE
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK                                                       0x00000700L
+//DCCG_SOFT_RESET
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT                                                        0x1
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L
+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK                                                          0x00000002L
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L
+//DSCCLK_DTO_CTRL
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT                                                            0x1
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT                                                            0x2
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT                                                            0x3
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT                                                            0x4
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT                                                            0x5
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK                                                              0x00000002L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK                                                              0x00000004L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK                                                              0x00000008L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK                                                              0x00000010L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK                                                              0x00000020L
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L
+//DCCG_AUDIO_DTO_SOURCE
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000030L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L
+//DCCG_AUDIO_DTO0_PHASE
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO0_MODULE
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_PHASE
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_MODULE
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_VSYNC_OTG0_LATCH_VALUE
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG1_LATCH_VALUE
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG2_LATCH_VALUE
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG3_LATCH_VALUE
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG4_LATCH_VALUE
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG5_LATCH_VALUE
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DPPCLK_DTO_CTRL
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT                                                            0x4
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT                                                            0x8
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT                                                            0xc
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT                                                            0x10
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT                                                            0x14
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK                                                              0x00000010L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK                                                              0x00000100L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK                                                              0x00001000L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK                                                              0x00010000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK                                                              0x00100000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L
+//DCCG_VSYNC_CNT_CTRL
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL__SHIFT                                                 0x1
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL_MASK                                                   0x00000002L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L
+//DCCG_VSYNC_CNT_INT_CTRL
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L
+//FORCE_SYMCLK_DISABLE
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L
+//PHYASYMCLK_CLOCK_CNTL
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000010L
+//PHYBSYMCLK_CLOCK_CNTL
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000010L
+//PHYCSYMCLK_CLOCK_CNTL
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000010L
+//PHYDSYMCLK_CLOCK_CNTL
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000010L
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+//DENTIST_DISPCLK_CNTL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
+//DC_PERFMON0_PERFCOUNTER_CNTL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_CNTL2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_STATE
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON0_PERFMON_CNTL
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON0_PERFMON_CNTL2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON0_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON0_PERFMON_CVALUE_LOW
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON0_PERFMON_HI
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON0_PERFMON_LOW
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
+//DC_PERFMON1_PERFCOUNTER_CNTL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_CNTL2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_STATE
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON1_PERFMON_CNTL
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON1_PERFMON_CNTL2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON1_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON1_PERFMON_CVALUE_LOW
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON1_PERFMON_HI
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON1_PERFMON_LOW
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmu_dc_pg_dispdec
+//DOMAIN0_PG_CONFIG
+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN0_PG_STATUS
+#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN1_PG_CONFIG
+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN1_PG_STATUS
+#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN2_PG_CONFIG
+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN2_PG_STATUS
+#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN3_PG_CONFIG
+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN3_PG_STATUS
+#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN4_PG_CONFIG
+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN4_PG_STATUS
+#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN5_PG_CONFIG
+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN5_PG_STATUS
+#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN6_PG_CONFIG
+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN6_PG_STATUS
+#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN7_PG_CONFIG
+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN7_PG_STATUS
+#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN16_PG_CONFIG
+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON__SHIFT                                                     0x0
+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE__SHIFT                                                        0x8
+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON_MASK                                                       0x00000001L
+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE_MASK                                                          0x00000100L
+//DOMAIN16_PG_STATUS
+#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE__SHIFT                                                 0x1c
+#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS__SHIFT                                                  0x1e
+#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE_MASK                                                   0x10000000L
+#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS_MASK                                                    0xC0000000L
+//DOMAIN17_PG_CONFIG
+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON__SHIFT                                                     0x0
+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE__SHIFT                                                        0x8
+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON_MASK                                                       0x00000001L
+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE_MASK                                                          0x00000100L
+//DOMAIN17_PG_STATUS
+#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE__SHIFT                                                 0x1c
+#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS__SHIFT                                                  0x1e
+#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE_MASK                                                   0x10000000L
+#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS_MASK                                                    0xC0000000L
+//DOMAIN18_PG_CONFIG
+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON__SHIFT                                                     0x0
+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE__SHIFT                                                        0x8
+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON_MASK                                                       0x00000001L
+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE_MASK                                                          0x00000100L
+//DOMAIN18_PG_STATUS
+#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE__SHIFT                                                 0x1c
+#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS__SHIFT                                                  0x1e
+#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE_MASK                                                   0x10000000L
+#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS_MASK                                                    0xC0000000L
+//DCPG_INTERRUPT_STATUS
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                           0x0
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x1
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                           0x2
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x3
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                           0x4
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x5
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                           0x6
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x7
+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT                                           0x8
+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x9
+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT                                           0xa
+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT                                         0xb
+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT                                           0xc
+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT                                         0xd
+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT                                           0xe
+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT                                         0xf
+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT                                           0x10
+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x11
+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT                                           0x12
+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x13
+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT                                          0x14
+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x15
+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT                                          0x16
+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x17
+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT                                          0x18
+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x19
+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT                                          0x1a
+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x1b
+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT                                          0x1c
+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x1d
+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT                                          0x1e
+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x1f
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000002L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                             0x00000004L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000020L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                             0x00000040L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000080L
+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED_MASK                                             0x00000100L
+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000200L
+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED_MASK                                             0x00000400L
+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000800L
+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED_MASK                                             0x00001000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK                                           0x00002000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED_MASK                                             0x00004000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK                                           0x00008000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED_MASK                                             0x00010000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK                                           0x00020000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED_MASK                                             0x00040000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK                                           0x00080000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED_MASK                                            0x00100000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK                                          0x00200000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED_MASK                                            0x00400000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK                                          0x00800000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED_MASK                                            0x01000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK                                          0x02000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED_MASK                                            0x04000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK                                          0x08000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED_MASK                                            0x10000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK                                          0x20000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED_MASK                                            0x40000000L
+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK                                          0x80000000L
+//DCPG_INTERRUPT_STATUS_2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                                        0x0
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                                        0x2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                                        0x4
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                                        0x6
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT                                        0x8
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x9
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT                                        0xa
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT                                      0xb
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED_MASK                                          0x00000100L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000200L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED_MASK                                          0x00000400L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000800L
+//DCPG_INTERRUPT_CONTROL_1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT                                            0x0
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                           0x1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT                                          0x2
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT                                            0x4
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                           0x5
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT                                          0x6
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT                                            0x8
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                           0x9
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT                                          0xa
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                         0xb
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT                                            0xc
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                           0xd
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT                                          0xe
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                         0xf
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK__SHIFT                                            0x10
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR__SHIFT                                           0x11
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK__SHIFT                                          0x12
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT                                         0x13
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK__SHIFT                                            0x14
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR__SHIFT                                           0x15
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK__SHIFT                                          0x16
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT                                         0x17
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK__SHIFT                                            0x18
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR__SHIFT                                           0x19
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK__SHIFT                                          0x1a
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT                                         0x1b
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK__SHIFT                                            0x1c
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR__SHIFT                                           0x1d
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK__SHIFT                                          0x1e
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT                                         0x1f
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK                                              0x00000001L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK                                             0x00000002L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK                                            0x00000004L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK                                              0x00000010L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK                                             0x00000020L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK                                            0x00000040L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK                                              0x00000100L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK                                             0x00000200L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK                                            0x00000400L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                           0x00000800L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK                                              0x00001000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK                                             0x00002000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK                                            0x00004000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                           0x00008000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK_MASK                                              0x00010000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR_MASK                                             0x00020000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK_MASK                                            0x00040000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR_MASK                                           0x00080000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK_MASK                                              0x00100000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR_MASK                                             0x00200000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK_MASK                                            0x00400000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR_MASK                                           0x00800000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK_MASK                                              0x01000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR_MASK                                             0x02000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK_MASK                                            0x04000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR_MASK                                           0x08000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK_MASK                                              0x10000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR_MASK                                             0x20000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK_MASK                                            0x40000000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR_MASK                                           0x80000000L
+//DCPG_INTERRUPT_CONTROL_2
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK__SHIFT                                            0x0
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR__SHIFT                                           0x1
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK__SHIFT                                          0x2
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK__SHIFT                                            0x4
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR__SHIFT                                           0x5
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK__SHIFT                                          0x6
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK__SHIFT                                           0x8
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR__SHIFT                                          0x9
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK__SHIFT                                         0xa
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK__SHIFT                                           0xc
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR__SHIFT                                          0xd
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK__SHIFT                                         0xe
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK__SHIFT                                           0x10
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR__SHIFT                                          0x11
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK__SHIFT                                         0x12
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT                                        0x13
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK__SHIFT                                           0x14
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR__SHIFT                                          0x15
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK__SHIFT                                         0x16
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT                                        0x17
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK__SHIFT                                           0x18
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR__SHIFT                                          0x19
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK__SHIFT                                         0x1a
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT                                        0x1b
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK__SHIFT                                           0x1c
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR__SHIFT                                          0x1d
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK__SHIFT                                         0x1e
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT                                        0x1f
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK_MASK                                              0x00000001L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR_MASK                                             0x00000002L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK_MASK                                            0x00000004L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK_MASK                                              0x00000010L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR_MASK                                             0x00000020L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK_MASK                                            0x00000040L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK_MASK                                             0x00000100L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR_MASK                                            0x00000200L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK_MASK                                           0x00000400L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK_MASK                                             0x00001000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR_MASK                                            0x00002000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK_MASK                                           0x00004000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK_MASK                                             0x00010000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR_MASK                                            0x00020000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK_MASK                                           0x00040000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR_MASK                                          0x00080000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK_MASK                                             0x00100000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR_MASK                                            0x00200000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK_MASK                                           0x00400000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR_MASK                                          0x00800000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK_MASK                                             0x01000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR_MASK                                            0x02000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK_MASK                                           0x04000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR_MASK                                          0x08000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK_MASK                                             0x10000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR_MASK                                            0x20000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK_MASK                                           0x40000000L
+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR_MASK                                          0x80000000L
+//DCPG_INTERRUPT_CONTROL_3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT                                           0x0
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                          0x1
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT                                         0x2
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT                                           0x4
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                          0x5
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT                                         0x6
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT                                           0x8
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                          0x9
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT                                         0xa
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT                                           0xc
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                          0xd
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT                                         0xe
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK__SHIFT                                           0x10
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR__SHIFT                                          0x11
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK__SHIFT                                         0x12
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT                                        0x13
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK__SHIFT                                           0x14
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR__SHIFT                                          0x15
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK__SHIFT                                         0x16
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT                                        0x17
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK                                            0x00000002L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK                                           0x00000004L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK                                            0x00000020L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK                                           0x00000040L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK                                             0x00000100L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK                                            0x00000200L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK                                           0x00000400L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK                                             0x00001000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK                                            0x00002000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK                                           0x00004000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK_MASK                                             0x00010000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR_MASK                                            0x00020000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK_MASK                                           0x00040000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR_MASK                                          0x00080000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK_MASK                                             0x00100000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR_MASK                                            0x00200000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK_MASK                                           0x00400000L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR_MASK                                          0x00800000L
+//DC_IP_REQUEST_CNTL
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT                                                              0x0
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK                                                                0x00000001L
+
+
+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON2_PERFCOUNTER_CNTL
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON2_PERFCOUNTER_CNTL2
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON2_PERFCOUNTER_STATE
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON2_PERFMON_CNTL
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON2_PERFMON_CNTL2
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON2_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON2_PERFMON_CVALUE_LOW
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON2_PERFMON_HI
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON2_PERFMON_LOW
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+//CC_DC_PIPE_DIS
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L
+//DMU_CLK_CNTL
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT                                                          0x5
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x6
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x8
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT                                                          0x9
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0xa
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK                                                            0x00000020L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000040L
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000100L
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK                                                            0x00000200L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000400L
+//DMU_MEM_PWR_CNTL
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT                                                   0x0
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT                                                      0x1
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT                                                        0x3
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT                                                      0x4
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT                                                      0x8
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT                                                        0x9
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT                                                      0xa
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK                                                     0x00000001L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK                                                        0x00000006L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK                                                          0x00000008L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK                                                        0x00000030L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK                                                        0x00000100L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK                                                          0x00000200L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK                                                        0x00000400L
+//DMU_MISC_ALLOW_DS_FORCE
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_dmu_dmcu_dispdec
+//DMCU_CTRL
+#define DMCU_CTRL__RESET_UC__SHIFT                                                                            0x0
+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT                                                                       0x1
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT                                                                   0x2
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT                                                                  0x3
+#define DMCU_CTRL__DMCU_ENABLE__SHIFT                                                                         0x4
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT                                                              0x8
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT                                                                   0x10
+#define DMCU_CTRL__RESET_UC_MASK                                                                              0x00000001L
+#define DMCU_CTRL__IGNORE_PWRMGT_MASK                                                                         0x00000002L
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK                                                                     0x00000004L
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK                                                                    0x00000008L
+#define DMCU_CTRL__DMCU_ENABLE_MASK                                                                           0x00000010L
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK                                                                0x00000100L
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK                                                                     0xFFFF0000L
+//DMCU_STATUS
+#define DMCU_STATUS__UC_IN_RESET__SHIFT                                                                       0x0
+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT                                                                   0x1
+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT                                                                   0x2
+#define DMCU_STATUS__UC_IN_RESET_MASK                                                                         0x00000001L
+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK                                                                     0x00000002L
+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK                                                                     0x00000004L
+//DMCU_PC_START_ADDR
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT                                                          0x0
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT                                                          0x8
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK                                                            0x000000FFL
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK                                                            0x0000FF00L
+//DMCU_FW_START_ADDR
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT                                                          0x0
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT                                                          0x8
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK                                                            0x000000FFL
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK                                                            0x0000FF00L
+//DMCU_FW_END_ADDR
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT                                                              0x0
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT                                                              0x8
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK                                                                0x000000FFL
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK                                                                0x0000FF00L
+//DMCU_FW_ISR_START_ADDR
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT                                                  0x0
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT                                                  0x8
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK                                                    0x000000FFL
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK                                                    0x0000FF00L
+//DMCU_FW_CS_HI
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT                                                                  0x0
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK                                                                    0xFFFFFFFFL
+//DMCU_FW_CS_LO
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT                                                                  0x0
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK                                                                    0xFFFFFFFFL
+//DMCU_RAM_ACCESS_CTRL
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x1
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x2
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x3
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT                                                      0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT                                                      0x5
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000001L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000002L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000004L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000008L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK                                                        0x00000010L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK                                                        0x00000020L
+//DMCU_ERAM_WR_CTRL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT                                                                0x0
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT                                                                  0x10
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT                                                           0x14
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK                                                                  0x0000FFFFL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK                                                                    0x000F0000L
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK                                                             0x00100000L
+//DMCU_ERAM_WR_DATA
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT                                                                0x0
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK                                                                  0xFFFFFFFFL
+//DMCU_ERAM_RD_CTRL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT                                                                0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT                                                                  0x10
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT                                                           0x14
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK                                                                  0x0000FFFFL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK                                                                    0x000F0000L
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK                                                             0x00100000L
+//DMCU_ERAM_RD_DATA
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT                                                                0x0
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK                                                                  0xFFFFFFFFL
+//DMCU_IRAM_WR_CTRL
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT                                                                0x0
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK                                                                  0x000003FFL
+//DMCU_IRAM_WR_DATA
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT                                                                0x0
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK                                                                  0x000000FFL
+//DMCU_IRAM_RD_CTRL
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT                                                                0x0
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK                                                                  0x000003FFL
+//DMCU_IRAM_RD_DATA
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT                                                                0x0
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK                                                                  0x000000FFL
+//DMCU_EVENT_TRIGGER
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT                                                       0x10
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK                                                         0x007F0000L
+//DMCU_UC_INTERNAL_INT_STATUS
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT                                                  0x0
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT                                                 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT                                         0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT                                        0x3
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT                                     0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT                                     0x5
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT                                     0x6
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT                                     0x7
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT                                             0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT                                        0x9
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT                     0xa
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT                                      0xb
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT                                      0xc
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT                                      0xd
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT                               0xe
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT                                 0xf
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK                                                    0x00000001L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK                                                   0x00000002L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK                                           0x00000004L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK                                          0x00000008L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK                                       0x00000010L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK                                       0x00000020L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK                                       0x00000040L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK                                       0x00000080L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK                                               0x00000100L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK                                          0x00000200L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK                       0x00000400L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK                                        0x00000800L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK                                        0x00001000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK                                        0x00002000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK                                 0x00004000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK                                   0x00008000L
+//DMCU_SS_INTERRUPT_CNTL_STATUS
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT                                       0xd
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT                                     0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT                                        0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT                                       0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT                                     0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT                                        0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT                                       0x11
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT                                     0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT                                        0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT                                       0x13
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT                                     0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT                                        0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT                                       0x15
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT                                     0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT                                        0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT                                       0x17
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT                                     0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT                                        0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK                                         0x00002000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK                                       0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK                                          0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK                                         0x00008000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK                                       0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK                                          0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK                                         0x00020000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK                                       0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK                                          0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK                                         0x00080000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK                                       0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK                                          0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK                                         0x00200000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK                                       0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK                                          0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK                                         0x00800000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK                                       0x01000000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK                                          0x01000000L
+//DMCU_INTERRUPT_STATUS
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT                                              0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT                                                 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT                                              0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT                                                 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT                                             0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT                                                0x2
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT                                                        0x3
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT                                                0x8
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT                                                   0x8
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT                                                        0x9
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT                                                0xa
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT                                                   0xa
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT                                          0xb
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT                                             0xb
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                  0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                     0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                  0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                     0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                  0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                     0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                  0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                     0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT                                  0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT                                     0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT                                  0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT                                     0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                   0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                   0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                   0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                   0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT                                0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT                                   0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT                                0x17
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT                                   0x17
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT                                                    0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT                                                       0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT                                                    0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT                                                       0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT                                                    0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT                                                       0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT                                                    0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT                                                       0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT                                                    0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT                                                       0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT                                                    0x1d
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT                                                       0x1d
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK                                                0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK                                                   0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK                                                0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK                                                   0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK                                               0x00000004L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK                                                  0x00000004L
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK                                                          0x00000008L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK                                                  0x00000100L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK                                                     0x00000100L
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK                                                          0x00000200L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK                                                  0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK                                                     0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK                                            0x00000800L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK                                               0x00000800L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                    0x00001000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK                                       0x00001000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                    0x00002000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK                                       0x00002000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                    0x00004000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK                                       0x00004000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                    0x00008000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK                                       0x00008000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK                                    0x00010000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK                                       0x00010000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK                                    0x00020000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK                                       0x00020000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                  0x00040000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                     0x00040000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                  0x00080000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                     0x00080000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                  0x00100000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                     0x00100000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                  0x00200000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                     0x00200000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK                                  0x00400000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK                                     0x00400000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK                                  0x00800000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK                                     0x00800000L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK                                                      0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK                                                         0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK                                                      0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK                                                         0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK                                                      0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK                                                         0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK                                                      0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK                                                         0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK                                                      0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK                                                         0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK                                                      0x20000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK                                                         0x20000000L
+//DMCU_INTERRUPT_STATUS_1
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x6
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x6
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x7
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x7
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x8
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x8
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x9
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x9
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xa
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xa
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xb
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xb
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT                                       0xd
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT                                          0xd
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_OCCURRED__SHIFT                                            0xe
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_CLEAR__SHIFT                                               0xe
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_OCCURRED__SHIFT                                            0xf
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_CLEAR__SHIFT                                               0xf
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_OCCURRED__SHIFT                                           0x10
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_CLEAR__SHIFT                                              0x10
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_OCCURRED__SHIFT                                            0x11
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_CLEAR__SHIFT                                               0x11
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_OCCURRED__SHIFT                                            0x12
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_CLEAR__SHIFT                                               0x12
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_OCCURRED__SHIFT                                           0x13
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_CLEAR__SHIFT                                              0x13
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK                                         0x00002000L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK                                            0x00002000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_OCCURRED_MASK                                              0x00004000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_CLEAR_MASK                                                 0x00004000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_OCCURRED_MASK                                              0x00008000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_CLEAR_MASK                                                 0x00008000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_OCCURRED_MASK                                             0x00010000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_CLEAR_MASK                                                0x00010000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_OCCURRED_MASK                                              0x00020000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_CLEAR_MASK                                                 0x00020000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_OCCURRED_MASK                                              0x00040000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_CLEAR_MASK                                                 0x00040000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_OCCURRED_MASK                                             0x00080000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_CLEAR_MASK                                                0x00080000L
+//DMCU_INTERRUPT_TO_HOST_EN_MASK
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT                                         0x0
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT                                         0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT                                        0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT                                         0x3
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT                                         0x4
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT                                        0x5
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT                                                   0x9
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT                                           0xa
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT                                     0xb
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_HG_READY_INT_MASK__SHIFT                                         0xc
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_LS_READY_INT_MASK__SHIFT                                         0xd
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_BL_UPDATE_INT_MASK__SHIFT                                        0xe
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_HG_READY_INT_MASK__SHIFT                                         0xf
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_LS_READY_INT_MASK__SHIFT                                         0x10
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_BL_UPDATE_INT_MASK__SHIFT                                        0x11
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK                                           0x00000001L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK                                           0x00000002L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK                                          0x00000004L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK                                           0x00000008L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK                                           0x00000010L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK                                          0x00000020L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK                                                     0x00000200L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK                                             0x00000400L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK                                       0x00000800L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_HG_READY_INT_MASK_MASK                                           0x00001000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_LS_READY_INT_MASK_MASK                                           0x00002000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_BL_UPDATE_INT_MASK_MASK                                          0x00004000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_HG_READY_INT_MASK_MASK                                           0x00008000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_LS_READY_INT_MASK_MASK                                           0x00010000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_BL_UPDATE_INT_MASK_MASK                                          0x00020000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT                                       0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT                                       0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT                                      0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT                                                 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT                                      0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT                                      0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT                                         0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT                                      0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT                                      0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT                                      0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT                           0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT                           0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT                           0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT                           0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT                           0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT                           0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT                                             0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT                                             0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT                                             0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT                                             0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT                                             0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT                                             0x1d
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT                                      0x1e
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK                                         0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK                                         0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK                                        0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK                                                   0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK                                        0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK                                        0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK                                           0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK                                        0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK                                        0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK                                        0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK                             0x00001000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK                             0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK                             0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK                             0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK                             0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK                             0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00400000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00800000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK                                               0x01000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK                                               0x02000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK                                               0x04000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK                                               0x08000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK                                               0x10000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK                                               0x20000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK                                        0x40000000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT                                      0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_HG_READY_INT_TO_UC_EN__SHIFT                                     0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_LS_READY_INT_TO_UC_EN__SHIFT                                     0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_BL_UPDATE_INT_TO_UC_EN__SHIFT                                    0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_HG_READY_INT_TO_UC_EN__SHIFT                                     0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_LS_READY_INT_TO_UC_EN__SHIFT                                     0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_BL_UPDATE_INT_TO_UC_EN__SHIFT                                    0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK                                        0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_HG_READY_INT_TO_UC_EN_MASK                                       0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_LS_READY_INT_TO_UC_EN_MASK                                       0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_BL_UPDATE_INT_TO_UC_EN_MASK                                      0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_HG_READY_INT_TO_UC_EN_MASK                                       0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_LS_READY_INT_TO_UC_EN_MASK                                       0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_BL_UPDATE_INT_TO_UC_EN_MASK                                      0x00080000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                             0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT                                        0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT                             0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT                             0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT                                0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT                             0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT                             0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT                             0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT                                    0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT                                    0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1d
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT                             0x1e
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                               0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK                                          0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK                               0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK                               0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK                                  0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK                               0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK                               0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK                               0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00001000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00400000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00800000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK                                      0x01000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK                                      0x02000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK                                      0x04000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK                                      0x08000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK                                      0x10000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK                                      0x20000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK                               0x40000000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT                             0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                           0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                           0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK                               0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_HG_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_LS_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                             0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_HG_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_LS_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                             0x00080000L
+//DC_DMCU_SCRATCH
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT                                                                  0x0
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK                                                                    0xFFFFFFFFL
+//DMCU_INT_CNT
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT                                                       0x0
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT                                                       0x8
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT                                                      0x10
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK                                                         0x000000FFL
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK                                                         0x0000FF00L
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK                                                        0x00FF0000L
+//DMCU_FW_CHECKSUM_SMPL_BYTE_POS
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT                              0x0
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT                              0x2
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK                                0x00000003L
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK                                0x0000000CL
+//DMCU_UC_CLK_GATING_CNTL
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT                                                      0x0
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT                                                      0x8
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT                                              0x10
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK                                                        0x00000007L
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK                                                        0x00000700L
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK                                                0x00010000L
+//MASTER_COMM_DATA_REG1
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_DATA_REG2
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_DATA_REG3
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_CMD_REG
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT                                                 0x0
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT                                                 0x8
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT                                                 0x10
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT                                                 0x18
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK                                                   0x000000FFL
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK                                                   0x0000FF00L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK                                                   0x00FF0000L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK                                                   0xFF000000L
+//MASTER_COMM_CNTL_REG
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT                                                    0x0
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK                                                      0x00000001L
+//SLAVE_COMM_DATA_REG1
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_DATA_REG2
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_DATA_REG3
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_CMD_REG
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT                                                   0x0
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT                                                   0x8
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT                                                   0x10
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT                                                   0x18
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK                                                     0x000000FFL
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK                                                     0x0000FF00L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK                                                     0x00FF0000L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK                                                     0xFF000000L
+//SLAVE_COMM_CNTL_REG
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT                                                      0x0
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT                                         0x8
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK                                                        0x00000001L
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK                                           0x00000100L
+//DMCU_PERFMON_INTERRUPT_STATUS1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+//DMCU_PERFMON_INTERRUPT_STATUS2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                            0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                               0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                              0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                                 0x00000100L
+//DMCU_PERFMON_INTERRUPT_STATUS3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
+//DMCU_PERFMON_INTERRUPT_STATUS4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT                             0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT                                0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                          0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                             0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK                               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK                                  0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                            0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000010L
+//DMCU_PERFMON_INTERRUPT_STATUS5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000200L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                     0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                       0x00000100L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                   0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                     0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000010L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000200L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT            0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK              0x00000100L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT          0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK            0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000010L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
+//DMCU_DPRX_INTERRUPT_STATUS1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT            0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT               0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT         0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT            0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT          0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT             0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT      0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT         0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT               0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT                  0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT                          0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT                             0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT                           0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT                              0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT                          0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT                             0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT                         0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT                            0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT                    0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT                       0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT                                      0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT                                         0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT                                      0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT                                         0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT                                      0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT                                         0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT                             0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT                                0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT                             0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT                                0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT                             0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT                                0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT                             0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT                                0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK              0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                 0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK           0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK              0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK            0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK               0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK        0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK           0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK                 0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                    0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK                            0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK                               0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK                             0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK                                0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK                            0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK                               0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK                           0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK                              0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK                      0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK                         0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK                                        0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK                                           0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK                                        0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK                                           0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK                                        0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK                                           0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK                               0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK                                  0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK                               0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK                                  0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK                               0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK                                  0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK                               0x10000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK                                  0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT     0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT   0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT        0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT                   0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT                    0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT                   0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT                  0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT             0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT                               0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT                               0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT                               0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK       0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK    0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK     0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK          0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK                     0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK                      0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK                     0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK                    0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK               0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK                                 0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK                                 0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK                                 0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK                        0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK                        0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK                        0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK                        0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT          0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT           0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT          0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT         0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT    0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT                      0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT                      0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT                      0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK            0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK             0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK            0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK           0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK      0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK                        0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK                        0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK                        0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x10000000L
+//DMCU_INTERRUPT_STATUS_CONTINUE
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT                         0x0
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT                            0x0
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT                         0x1
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT                            0x1
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT                         0x2
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT                            0x2
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT                         0x3
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT                            0x3
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT                        0x4
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT                           0x4
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT                        0x5
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT                           0x5
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT                        0x6
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT                           0x6
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT                        0x7
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT                           0x7
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT                        0x8
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT                           0x8
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT                        0x9
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT                           0x9
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT                       0xa
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT                          0xa
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT                       0xb
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT                          0xb
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT                       0xc
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT                          0xc
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT                       0xd
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT                          0xd
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT                      0xe
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT                         0xe
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT                      0xf
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT                         0xf
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT                      0x10
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT                         0x10
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT                      0x11
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT                         0x11
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT                      0x12
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT                         0x12
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT                      0x13
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT                         0x13
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT                          0x14
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT                             0x14
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT                          0x15
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT                             0x15
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT                          0x16
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT                             0x16
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT                          0x17
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT                             0x17
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT                          0x18
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT                             0x18
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT                          0x19
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT                             0x19
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT                                     0x1a
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT                                        0x1a
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT                                     0x1b
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT                                        0x1b
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT                                    0x1c
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT                                       0x1c
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK                           0x00000001L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK                              0x00000001L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK                           0x00000002L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK                              0x00000002L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK                           0x00000004L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK                              0x00000004L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK                           0x00000008L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK                              0x00000008L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK                          0x00000010L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK                             0x00000010L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK                          0x00000020L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK                             0x00000020L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK                          0x00000040L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK                             0x00000040L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK                          0x00000080L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK                             0x00000080L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK                          0x00000100L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK                             0x00000100L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK                          0x00000200L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK                             0x00000200L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK                         0x00000400L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK                            0x00000400L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK                         0x00000800L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK                            0x00000800L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK                         0x00001000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK                            0x00001000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK                         0x00002000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK                            0x00002000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK                        0x00004000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK                           0x00004000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK                        0x00008000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK                           0x00008000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK                        0x00010000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK                           0x00010000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK                        0x00020000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK                           0x00020000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK                        0x00040000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK                           0x00040000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK                        0x00080000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK                           0x00080000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK                            0x00100000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK                               0x00100000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK                            0x00200000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK                               0x00200000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK                            0x00400000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK                               0x00400000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK                            0x00800000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK                               0x00800000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK                            0x01000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK                               0x01000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK                            0x02000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK                               0x02000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK                                       0x04000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK                                          0x04000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK                                       0x08000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK                                          0x08000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK                                      0x10000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK                                         0x10000000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT                  0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT                  0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT                  0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT                  0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT                 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT                 0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT                 0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT                 0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT                 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT                 0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT               0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT               0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT                   0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT                   0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT                   0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT                   0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT                   0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT                   0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT                              0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT                              0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT                             0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK                    0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK                    0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK                    0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK                    0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK                   0x00000010L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK                   0x00000020L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK                   0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK                   0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK                   0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK                   0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00001000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK                     0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK                     0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK                     0x00400000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK                     0x00800000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK                     0x01000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK                     0x02000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK                                0x04000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK                                0x08000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK                               0x10000000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT          0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT          0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT          0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT          0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT          0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT          0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                    0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000010L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000020L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00001000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK            0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK            0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK            0x00400000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK            0x00800000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK            0x01000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK            0x02000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK                       0x04000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK                       0x08000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                      0x10000000L
+//DMCU_INT_CNT_CONTINUE
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT                                              0x0
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT                                              0x8
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT                                             0x10
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK                                                0x000000FFL
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK                                                0x0000FF00L
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK                                               0x00FF0000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT                        0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT                        0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT                        0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT                        0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT                        0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT                        0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT                        0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000010L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000020L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK                          0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK                          0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK                          0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK                          0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK                          0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK                          0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK                          0x00400000L
+//DMCU_INTERRUPT_STATUS_2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                               0x2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                  0x2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                               0x3
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                  0x3
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT                               0x4
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR__SHIFT                                  0x4
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT                               0x5
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR__SHIFT                                  0x5
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                             0x6
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                0x6
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                             0x7
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                0x7
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                             0x8
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                0x8
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                             0x9
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                0x9
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT                             0xa
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT                                0xa
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT                             0xb
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT                                0xb
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT                                            0x10
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT                                               0x10
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT                                            0x11
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT                                               0x11
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT                                            0x12
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT                                               0x12
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT                                            0x13
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT                                               0x13
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT                                            0x14
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT                                               0x14
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT                                            0x15
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT                                               0x15
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT                                            0x16
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT                                               0x16
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                 0x00000004L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR_MASK                                    0x00000004L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                 0x00000008L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR_MASK                                    0x00000008L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED_MASK                                 0x00000010L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR_MASK                                    0x00000010L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED_MASK                                 0x00000020L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR_MASK                                    0x00000020L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                               0x00000040L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                  0x00000040L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                               0x00000080L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                  0x00000080L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                               0x00000100L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                  0x00000100L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                               0x00000200L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                  0x00000200L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK                               0x00000400L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR_MASK                                  0x00000400L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK                               0x00000800L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR_MASK                                  0x00000800L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK                                              0x00010000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK                                                 0x00010000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK                                              0x00020000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK                                                 0x00020000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK                                              0x00040000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK                                                 0x00040000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK                                              0x00080000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK                                                 0x00080000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK                                              0x00100000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK                                                 0x00100000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK                                              0x00200000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK                                                 0x00200000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK                                              0x00400000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK                                                 0x00400000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN__SHIFT                        0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN__SHIFT                        0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN__SHIFT                        0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN__SHIFT                        0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT                                     0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT                                     0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT                                     0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT                                     0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT                                     0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT                                     0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT                                     0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN_MASK                          0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN_MASK                          0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN_MASK                          0x00000010L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN_MASK                          0x00000020L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK                                       0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK                                       0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK                                       0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK                                       0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK                                       0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK                                       0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK                                       0x00400000L
+//DMCU_INT_CNT_CONT2
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_HG_READY_INT_CNT__SHIFT                                                 0x0
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_LS_READY_INT_CNT__SHIFT                                                 0x8
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_BL_UPDATE_INT_CNT__SHIFT                                                0x10
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_HG_READY_INT_CNT_MASK                                                   0x000000FFL
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_LS_READY_INT_CNT_MASK                                                   0x0000FF00L
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_BL_UPDATE_INT_CNT_MASK                                                  0x00FF0000L
+//DMCU_INT_CNT_CONT3
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_HG_READY_INT_CNT__SHIFT                                                 0x0
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_LS_READY_INT_CNT__SHIFT                                                 0x8
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_BL_UPDATE_INT_CNT__SHIFT                                                0x10
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_HG_READY_INT_CNT_MASK                                                   0x000000FFL
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_LS_READY_INT_CNT_MASK                                                   0x0000FF00L
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_BL_UPDATE_INT_CNT_MASK                                                  0x00FF0000L
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+//DC_GPU_TIMER_START_POSITION_V_UPDATE
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L
+//DC_GPU_TIMER_START_POSITION_VSTARTUP
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L
+//DC_GPU_TIMER_READ
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL
+//DC_GPU_TIMER_READ_CNTL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L
+//DISP_INTERRUPT_STATUS
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT                                                    0x1a
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT                                                            0x1b
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT                                                       0x1c
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT                                                       0x1d
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT                                                      0x1e
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK                                                      0x04000000L
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK                                                              0x08000000L
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK                                                         0x10000000L
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK                                                         0x20000000L
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK                                                        0x40000000L
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE10
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT                             0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT                             0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK                               0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK                               0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK                                     0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK                                     0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK                                     0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK                                     0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT                                    0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK                                      0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                            0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                            0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                              0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                              0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE14
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE15
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE19
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE20
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE21
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT__SHIFT                        0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT_MASK                          0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE22
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT__SHIFT                          0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT__SHIFT                          0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT__SHIFT                         0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT__SHIFT                         0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT__SHIFT                         0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT__SHIFT                         0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT__SHIFT                         0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT__SHIFT                         0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT__SHIFT                        0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT__SHIFT                        0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT__SHIFT                       0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT__SHIFT                       0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT__SHIFT                       0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT__SHIFT                       0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT__SHIFT                       0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT__SHIFT                       0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT                                            0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT                                            0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT                                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_MASK                            0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_MASK                            0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_MASK                           0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_MASK                           0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_MASK                           0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_MASK                           0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_MASK                           0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_MASK                           0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_MASK                          0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_MASK                          0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_MASK                         0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_MASK                         0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_MASK                         0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_MASK                         0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK                                              0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK                                              0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK                                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L
+//DC_GPU_TIMER_START_POSITION_VREADY
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L
+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L
+//DISP_INTERRUPT_STATUS_CONTINUE23
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE24
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT__SHIFT                                    0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT_MASK                                      0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE25
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT__SHIFT                                            0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT__SHIFT                                            0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT__SHIFT                                           0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT__SHIFT                                            0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT__SHIFT                                            0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT__SHIFT                                           0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT__SHIFT                                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT__SHIFT                                            0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT__SHIFT                                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT__SHIFT                                            0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT__SHIFT                                            0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT__SHIFT                                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT_MASK                                              0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT_MASK                                              0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT_MASK                                             0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT_MASK                                              0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT_MASK                                              0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT_MASK                                             0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT_MASK                                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT_MASK                                              0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT_MASK                                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT_MASK                                              0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT_MASK                                              0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT_MASK                                             0x00000800L
+//DCCG_INTERRUPT_DEST
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT                                 0xe
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT                                 0xf
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK                                   0x00004000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK                                   0x00008000L
+//DMU_INTERRUPT_DEST
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0x4
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0x5
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0x6
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0x7
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0x8
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0x9
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0xa
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0xb
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT                                      0xe
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT                                      0xf
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x10
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT                                      0x11
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT                                      0x12
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x13
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x18
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x19
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1a
+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT                                      0x1b
+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT                                                0x1c
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000010L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000020L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00000040L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00000080L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00000100L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00000200L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00000400L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00000800L
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK                                        0x00004000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK                                        0x00008000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00010000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK                                        0x00020000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK                                        0x00040000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00080000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x01000000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x02000000L
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x04000000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK                                        0x08000000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK                                                  0x10000000L
+//DMU_INTERRUPT_DEST2
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST__SHIFT                                     0x0
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST__SHIFT                                     0x1
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x2
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST__SHIFT                                     0x3
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST__SHIFT                                     0x4
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x5
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST__SHIFT                                     0x6
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST__SHIFT                                     0x7
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x8
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST__SHIFT                                     0x9
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST__SHIFT                                     0xa
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0xb
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST_MASK                                       0x00000001L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST_MASK                                       0x00000002L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000004L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST_MASK                                       0x00000008L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST_MASK                                       0x00000010L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000020L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST_MASK                                       0x00000040L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST_MASK                                       0x00000080L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000100L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST_MASK                                       0x00000200L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST_MASK                                       0x00000400L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000800L
+//DCPG_INTERRUPT_DEST
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x8
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x9
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xa
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xb
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xc
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xd
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xe
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xf
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x18
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x19
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1a
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1b
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1c
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1d
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1e
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1f
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000100L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000200L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST_MASK                                   0x00000400L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST_MASK                                   0x00000800L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST_MASK                                   0x00001000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST_MASK                                   0x00002000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST_MASK                                   0x00004000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST_MASK                                   0x00008000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x01000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x02000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x04000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x08000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x10000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x20000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x40000000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x80000000L
+//DCPG_INTERRUPT_DEST2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x6
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x7
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x8
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x9
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000040L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000080L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000100L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000200L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L
+//MMHUBBUB_INTERRUPT_DEST
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT                                        0x0
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT                                    0x8
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                          0xc
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                          0xd
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK                                          0x00000001L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK                                      0x00000100L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                            0x00001000L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                            0x00002000L
+//WB_INTERRUPT_DEST
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xc
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xd
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xe
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xf
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0x10
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0x11
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00001000L
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00002000L
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00004000L
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00008000L
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00010000L
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00020000L
+//DCHUB_INTERRUPT_DEST
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L
+//DCHUB_PERFCOUNTER_INTERRUPT_DEST
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                   0xc
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                   0xd
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0xe
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0xf
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x10
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x11
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x12
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x13
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x14
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x15
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x16
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x17
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x18
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x19
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1a
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1b
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1c
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1d
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                     0x00001000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                     0x00002000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00004000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00008000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00010000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00020000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00040000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00080000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00100000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00200000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00400000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00800000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x01000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x02000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x04000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x08000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x10000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x20000000L
+//DCHUB_INTERRUPT_DEST2
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L
+//DPP_PERFCOUNTER_INTERRUPT_DEST
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xc
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xd
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xe
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xf
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x10
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x11
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x12
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x13
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x14
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x15
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x16
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x17
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x18
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x19
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x1a
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x1b
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00001000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00002000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00004000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00008000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00010000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00020000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00040000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00080000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00100000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00200000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00400000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00800000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x01000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x02000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x04000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x08000000L
+//MPC_INTERRUPT_DEST
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//OPP_INTERRUPT_DEST
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//OPTC_INTERRUPT_DEST
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L
+//OTG0_INTERRUPT_DEST
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG1_INTERRUPT_DEST
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG2_INTERRUPT_DEST
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG3_INTERRUPT_DEST
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG4_INTERRUPT_DEST
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG5_INTERRUPT_DEST
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//DIG_INTERRUPT_DEST
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L
+//I2C_DDC_HPD_INTERRUPT_DEST
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16
+#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST__SHIFT                        0x17
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST_MASK                          0x00800000L
+//DIO_INTERRUPT_DEST
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//DCIO_INTERRUPT_DEST
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L
+//HPD_INTERRUPT_DEST
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L
+//AZ_INTERRUPT_DEST
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                      0x1e
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                      0x1f
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                        0x40000000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                        0x80000000L
+//AUX_INTERRUPT_DEST
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x10
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x11
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x12
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x13
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x14
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x15
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x16
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x17
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x18
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x19
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x1a
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x1b
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00010000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00020000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00040000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00080000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00100000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00200000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00400000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00800000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x01000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x02000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x04000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x08000000L
+//DSC_INTERRUPT_DEST
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x0
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x2
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x3
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x4
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x6
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x7
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x8
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xa
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xb
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0xc
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xe
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xf
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x10
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x12
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x13
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x14
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x16
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x17
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000004L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000008L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000040L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000080L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000100L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000400L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000800L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00004000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00008000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00010000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00040000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00080000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00100000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00400000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00800000L
+
+
+// addressBlock: dce_dc_dmu_fgsec_dispdec
+//DMCUB_RBBMIF_SEC_CNTL
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL__SHIFT                                                  0x4
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID__SHIFT                                                  0x8
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL_MASK                                                    0x00000070L
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID_MASK                                                    0x01FFFF00L
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+//RBBMIF_TIMEOUT
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT                                                           0x0
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT                                                     0x14
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK                                                             0x000FFFFFL
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK                                                       0xFFF00000L
+//RBBMIF_STATUS
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT                                                      0x0
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK                                                        0xFFFFFFFFL
+//RBBMIF_STATUS_2
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT                                                  0x0
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK                                                    0x0000007FL
+//RBBMIF_INT_STATUS
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT                                                         0x2
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT                                                           0x1c
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT                                                  0x1d
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT                                                          0x1e
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT                                                         0x1f
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK                                                           0x0003FFFCL
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK                                                             0x10000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK                                                    0x20000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK                                                            0x40000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK                                                           0x80000000L
+//RBBMIF_TIMEOUT_DIS
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT                                                        0x0
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT                                                        0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT                                                        0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT                                                        0x3
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT                                                        0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT                                                        0x5
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT                                                        0x6
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT                                                        0x7
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT                                                        0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT                                                        0x9
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT                                                       0xa
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT                                                       0xb
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT                                                       0xc
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT                                                       0xd
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT                                                       0xe
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT                                                       0xf
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT                                                       0x10
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT                                                       0x11
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT                                                       0x12
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT                                                       0x13
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT                                                       0x14
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT                                                       0x15
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT                                                       0x16
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT                                                       0x17
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT                                                       0x18
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT                                                       0x19
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT                                                       0x1a
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT                                                       0x1b
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT                                                       0x1c
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT                                                       0x1d
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT                                                       0x1e
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT                                                       0x1f
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK                                                          0x00000001L
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK                                                          0x00000002L
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK                                                          0x00000004L
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK                                                          0x00000008L
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK                                                          0x00000010L
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK                                                          0x00000020L
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK                                                          0x00000040L
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK                                                          0x00000080L
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK                                                          0x00000100L
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK                                                          0x00000200L
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK                                                         0x00000400L
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK                                                         0x00000800L
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK                                                         0x00001000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK                                                         0x00002000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK                                                         0x00004000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK                                                         0x00008000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK                                                         0x00010000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK                                                         0x00020000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK                                                         0x00040000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK                                                         0x00080000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK                                                         0x00100000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK                                                         0x00200000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK                                                         0x00400000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK                                                         0x00800000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK                                                         0x01000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK                                                         0x02000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK                                                         0x04000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK                                                         0x08000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK                                                         0x10000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK                                                         0x20000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK                                                         0x40000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK                                                         0x80000000L
+//RBBMIF_TIMEOUT_DIS_2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT                                                     0x0
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT                                                     0x1
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT                                                     0x2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT                                                     0x3
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT                                                     0x4
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT                                                     0x5
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT                                                     0x6
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK                                                       0x00000001L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK                                                       0x00000002L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK                                                       0x00000004L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK                                                       0x00000008L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK                                                       0x00000010L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK                                                       0x00000020L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK                                                       0x00000040L
+//RBBMIF_STATUS_FLAG
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT                                                               0x0
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT                                                        0x4
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT                                                          0x5
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT                                                           0x6
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                                 0x8
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                                 0x9
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                                 0x10
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK                                                                 0x00000003L
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK                                                          0x00000010L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK                                                            0x00000020L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK                                                             0x00000040L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                   0x00000100L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                   0x00000E00L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                   0xFFFF0000L
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+//DMCUB_REGION0_OFFSET
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION0_OFFSET_HIGH
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION1_OFFSET
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION1_OFFSET_HIGH
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION2_OFFSET
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION2_OFFSET_HIGH
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION4_OFFSET
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION4_OFFSET_HIGH
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION5_OFFSET
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION5_OFFSET_HIGH
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION6_OFFSET
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION6_OFFSET_HIGH
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION7_OFFSET
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION7_OFFSET_HIGH
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION0_TOP_ADDRESS
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION1_TOP_ADDRESS
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION2_TOP_ADDRESS
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION4_TOP_ADDRESS
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION5_TOP_ADDRESS
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION6_TOP_ADDRESS
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION7_TOP_ADDRESS
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION3_CW0_BASE_ADDRESS
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW1_BASE_ADDRESS
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW2_BASE_ADDRESS
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW3_BASE_ADDRESS
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW4_BASE_ADDRESS
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW5_BASE_ADDRESS
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW6_BASE_ADDRESS
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW7_BASE_ADDRESS
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW0_TOP_ADDRESS
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW1_TOP_ADDRESS
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW2_TOP_ADDRESS
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW3_TOP_ADDRESS
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW4_TOP_ADDRESS
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW5_TOP_ADDRESS
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW6_TOP_ADDRESS
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW7_TOP_ADDRESS
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW0_OFFSET
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW0_OFFSET_HIGH
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW1_OFFSET
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW1_OFFSET_HIGH
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW2_OFFSET
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW2_OFFSET_HIGH
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW3_OFFSET
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW3_OFFSET_HIGH
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW4_OFFSET
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW4_OFFSET_HIGH
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW5_OFFSET
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW5_OFFSET_HIGH
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW6_OFFSET
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW6_OFFSET_HIGH
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW7_OFFSET
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW7_OFFSET_HIGH
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_INTERRUPT_ENABLE
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0xd
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00002000L
+//DMCUB_INTERRUPT_ACK
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0xd
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00002000L
+//DMCUB_INTERRUPT_STATUS
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0xd
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0xe
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0xf
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00002000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00004000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00008000L
+//DMCUB_INTERRUPT_TYPE
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0xd
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00002000L
+//DMCUB_EXT_INTERRUPT_STATUS
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L
+//DMCUB_EXT_INTERRUPT_CTXID
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL
+//DMCUB_EXT_INTERRUPT_ACK
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L
+//DMCUB_INST_FETCH_FAULT_ADDR
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_DATA_WRITE_FAULT_ADDR
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_SEC_CNTL
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L
+//DMCUB_MEM_CNTL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE__SHIFT                                                          0x8
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE__SHIFT                                                           0xc
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE_MASK                                                            0x00000700L
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE_MASK                                                             0x00007000L
+//DMCUB_INBOX0_BASE_ADDRESS
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX0_SIZE
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_WPTR
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_RPTR
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_BASE_ADDRESS
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX1_SIZE
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_WPTR
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_RPTR
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_OUTBOX0_BASE_ADDRESS
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_SIZE
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_WPTR
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_RPTR
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_BASE_ADDRESS
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_SIZE
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_WPTR
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_RPTR
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER1
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_WINDOW
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L
+//DMCUB_SCRATCH0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH1
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH2
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH3
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH4
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH5
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH6
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH7
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH8
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH9
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH10
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH11
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH12
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH13
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH14
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH15
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL
+//DMCUB_CNTL
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8
+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10
+#define DMCUB_CNTL__DMCUB_SOFT_RESET__SHIFT                                                                   0x11
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L
+#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L
+#define DMCUB_CNTL__DMCUB_SOFT_RESET_MASK                                                                     0x00020000L
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L
+//DMCUB_GPINT_DATAIN0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN1
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAOUT
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL
+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL
+//DMCUB_LS_WAKE_INT_ENABLE
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL
+//DMCUB_MEM_PWR_CNTL
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L
+//DMCUB_TIMER_CURRENT
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL
+//DMCUB_PROC_ID
+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0
+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+//MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                               0x0
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT                                            0x1
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                            0x4
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                           0x5
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                                      0x6
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                                    0x7
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                              0x8
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                           0x18
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                                 0x00000001L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK                                              0x00000002L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                              0x00000010L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                             0x00000020L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                                        0x00000040L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                                      0x00000080L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                                0x00000F00L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                             0x01000000L
+//MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                           0x0
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                            0x1
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                                    0x2
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                                  0x4
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                             0x7
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                                   0x8
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                               0xc
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                                 0x1c
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                             0x00000001L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                              0x00000002L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                                      0x00000004L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                                    0x00000070L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                               0x00000080L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                                     0x00000F00L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                                 0x01FFF000L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                                   0x70000000L
+//MCIF_WB_BUF_PITCH
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                                      0x8
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                                    0x18
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                                        0x0000FF00L
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                                      0xFF000000L
+//MCIF_WB_BUF_1_STATUS
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_2_STATUS
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_3_STATUS
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_4_STATUS
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                                  0x0
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                            0x14
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                                    0x00000003L
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                              0xFFF00000L
+//MCIF_WB_SCLK_CHANGE
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                                    0x0
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                                      0x00000001L
+//MCIF_WB_TEST_DEBUG_INDEX
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                             0x0
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                          0x8
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                               0x000000FFL
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                            0x00000100L
+//MCIF_WB_TEST_DEBUG_DATA
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                               0x0
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                                 0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                                     0x0
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                          0x4
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                         0x5
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                                    0x6
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                            0x8
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                          0x10
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                                       0x00000001L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                            0x00000010L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                           0x00000020L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                                      0x00000040L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                              0x00000F00L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                            0x1FFF0000L
+//MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT                              0x0
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                           0x1
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT                                          0x2
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK                                0x00000001L
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                             0x00000002L
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK                                            0x00000004L
+//MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                                  0x0
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                                    0x00000001L
+//MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT                                         0x0
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                            0x1
+#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK                                           0x00000001L
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                              0x00000002L
+//MULTI_LEVEL_QOS_CTRL
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                                0x0
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                                  0x003FFFFFL
+//MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                                   0x0
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                                     0x000FFFFFL
+//MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                               0x0
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                                 0x000FFFFFL
+//MCIF_WB_BUF_1_ADDR_Y_HIGH
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_ADDR_C_HIGH
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_Y_HIGH
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_C_HIGH
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_Y_HIGH
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_C_HIGH
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_Y_HIGH
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_C_HIGH
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_RESOLUTION
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_2_RESOLUTION
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_3_RESOLUTION
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_4_RESOLUTION
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI
+#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__SHIFT                 0x0
+#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_MASK                   0x0000FFFFL
+//MCIF_WB_VMID_CONTROL
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT                                                           0x0
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK                                                             0x0000000FL
+//MCIF_WB_MIN_TTO
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT                                                               0x0
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK                                                                 0x0007FFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT                        0x0
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                           0x18
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                          0x001FFFFFL
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                             0x07000000L
+//MCIF_WB_WATERMARK
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                                       0x0
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                         0x001FFFFFL
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK                                                    0x07000000L
+//MMHUBBUB_WARMUP_CONFIG
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT                                                    0x10
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT                                                   0x14
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK                                                      0x000F0000L
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK                                                     0x00F00000L
+//MMHUBBUB_WARMUP_CONTROL_STATUS
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT                                             0x0
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT                                      0x4
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT                                  0x5
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT                                     0x6
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT                                       0x8
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK                                               0x00000001L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK                                        0x00000010L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK                                    0x00000020L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK                                       0x00000040L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK                                         0x03FFFF00L
+//MMHUBBUB_WARMUP_BASE_ADDR_LOW
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT                                   0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK                                     0xFFFFFFFFL
+//MMHUBBUB_WARMUP_BASE_ADDR_HIGH
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT                                 0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK                                   0x000007FFL
+//MMHUBBUB_WARMUP_ADDR_REGION
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT                                       0x0
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK                                         0x07FFFFFFL
+//MMHUBBUB_MIN_TTO
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT                                                             0x0
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK                                                               0x0007FFFFL
+//WBIF0_MISC_CTRL
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                                   0x18
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                                0x19
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                     0x01000000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                                  0x02000000L
+//WBIF0_PHASE0_OUTSTANDING_COUNTER
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//WBIF0_PHASE1_OUTSTANDING_COUNTER
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//VGA_SRC_SPLIT_CNTL
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT                                                              0x0
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK                                                                0x00000003L
+//MMHUBBUB_MEM_PWR_STATUS
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT                                                     0x1f
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK                                                       0x80000000L
+//MMHUBBUB_MEM_PWR_CNTL
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT                                                       0x0
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT                                                         0x1
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK                                                         0x00000001L
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK                                                           0x00000002L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L
+//MMHUBBUB_CLOCK_CNTL
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT                                                  0x6
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT                                                   0x7
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT                                                    0x8
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK                                                    0x00000040L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK                                                     0x00000080L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK                                                      0x00000100L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L
+//MMHUBBUB_SOFT_RESET
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT                                                            0x0
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT                                                          0x1
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK                                                              0x00000001L
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK                                                            0x00000002L
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L
+//DMU_IF_ERR_STATUS
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L
+//MMHUBBUB_CLIENT_UNIT_ID
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT                                                           0x0
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK                                                             0x0000003FL
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L
+//MMHUBBUB_WARMUP_VMID_CONTROL
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT                                           0x0
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK                                             0x0000000FL
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+//MCIF_CONTROL
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT                                                   0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT                                              0x1f
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK                                                     0x40000000L
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK                                                0x80000000L
+//MCIF_WRITE_COMBINE_CONTROL
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT                                         0x0
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK                                           0x000003FFL
+//MCIF_PHASE0_OUTSTANDING_COUNTER
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE1_OUTSTANDING_COUNTER
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE2_OUTSTANDING_COUNTER
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON3_PERFCOUNTER_CNTL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_CNTL2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_STATE
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON3_PERFMON_CNTL
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON3_PERFMON_CNTL2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON3_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON3_PERFMON_CVALUE_LOW
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON3_PERFMON_HI
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON3_PERFMON_LOW
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+//AZF0STREAM0_AZALIA_STREAM_INDEX
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM0_AZALIA_STREAM_DATA
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+//AZF0STREAM1_AZALIA_STREAM_INDEX
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM1_AZALIA_STREAM_DATA
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+//AZF0STREAM2_AZALIA_STREAM_INDEX
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM2_AZALIA_STREAM_DATA
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+//AZF0STREAM3_AZALIA_STREAM_INDEX
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM3_AZALIA_STREAM_DATA
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+//AZF0STREAM4_AZALIA_STREAM_INDEX
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM4_AZALIA_STREAM_DATA
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+//AZF0STREAM5_AZALIA_STREAM_INDEX
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM5_AZALIA_STREAM_DATA
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+//AZF0STREAM6_AZALIA_STREAM_INDEX
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM6_AZALIA_STREAM_DATA
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+//AZF0STREAM7_AZALIA_STREAM_INDEX
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM7_AZALIA_STREAM_DATA
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+//AZ_CLOCK_CNTL
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT                                                       0x0
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT                                                              0x8
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT                                                         0x10
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT                                                              0x18
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK                                                         0x00000001L
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK                                                                0x00000100L
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK                                                           0x00010000L
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK                                                                0x1F000000L
+
+
+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON4_PERFCOUNTER_CNTL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_CNTL2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_STATE
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON4_PERFMON_CNTL
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON4_PERFMON_CNTL2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON4_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON4_PERFMON_CVALUE_LOW
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON4_PERFMON_HI
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON4_PERFMON_LOW
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+//AZALIA_CONTROLLER_CLOCK_GATING
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L
+//AZALIA_AUDIO_DTO
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L
+//AZALIA_AUDIO_DTO_CONTROL
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L
+//AZALIA_SOCCLK_CONTROL
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L
+//AZALIA_UNDERFLOW_FILLER_SAMPLE
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL
+//AZALIA_DATA_DMA_CONTROL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L
+//AZALIA_BDL_DMA_CONTROL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L
+//AZALIA_RIRB_AND_DP_CONTROL
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L
+//AZALIA_CORB_DMA_CONTROL
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L
+//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT            0x0
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK              0xFFFFFFFFL
+//AZALIA_CYCLIC_BUFFER_SYNC
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT                                           0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK                                             0x00000001L
+//AZALIA_GLOBAL_CAPABILITIES
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L
+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L
+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L
+//AZALIA_INPUT_PAYLOAD_CAPABILITY
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L
+//AZALIA_INPUT_CRC0_CONTROL0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC0_CONTROL1
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CONTROL2
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC0_CONTROL3
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC0_RESULT
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC1_CONTROL1
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL2
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC1_CONTROL3
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC1_RESULT
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL0
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC0_CONTROL1
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL2
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC0_CONTROL3
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC0_RESULT
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL0
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC1_CONTROL1
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL2
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC1_CONTROL3
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC1_RESULT
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_MEM_PWR_CTRL
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L
+//AZALIA_MEM_PWR_STATUS
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L
+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L
+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L
+//AZALIA_F0_GTC_GROUP_OFFSET0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET1
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET2
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET3
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET4
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET5
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET6
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK                                                   0xFFFFFFFFL
+//REG_DC_AUDIO_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L
+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+//AZF0STREAM8_AZALIA_STREAM_INDEX
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM8_AZALIA_STREAM_DATA
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+//AZF0STREAM9_AZALIA_STREAM_INDEX
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM9_AZALIA_STREAM_DATA
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+//AZF0STREAM10_AZALIA_STREAM_INDEX
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM10_AZALIA_STREAM_DATA
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+//AZF0STREAM11_AZALIA_STREAM_INDEX
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM11_AZALIA_STREAM_DATA
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+//AZF0STREAM12_AZALIA_STREAM_INDEX
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM12_AZALIA_STREAM_DATA
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+//AZF0STREAM13_AZALIA_STREAM_INDEX
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM13_AZALIA_STREAM_DATA
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+//AZF0STREAM14_AZALIA_STREAM_INDEX
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM14_AZALIA_STREAM_DATA
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+//AZF0STREAM15_AZALIA_STREAM_INDEX
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM15_AZALIA_STREAM_DATA
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
+//DCHUBBUB_SDPIF_CFG0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L
+//VM_REQUEST_PHYSICAL
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L
+//DCHUBBUB_FORCE_IO_STATUS_0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L
+//DCHUBBUB_FORCE_IO_STATUS_1
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL
+//DCN_VM_FB_LOCATION_BASE
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL
+//DCN_VM_FB_LOCATION_TOP
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL
+//DCN_VM_FB_OFFSET
+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0
+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL
+//DCN_VM_AGP_BOT
+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0
+#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_TOP
+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0
+#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_BASE
+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0
+#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_START
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_END
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L
+//DCHUBBUB_SDPIF_MEM_PWR_CTRL
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L
+//DCHUBBUB_SDPIF_MEM_PWR_STATUS
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L
+//DCHUBBUB_SDPIF_CFG1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L
+//DCHUBBUB_SDPIF_CFG2
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
+//DCHUBBUB_RET_PATH_DCC_CFG
+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT                                                 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK                                                   0x00000001L
+//DCHUBBUB_RET_PATH_DCC_CFG0_0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG0_1
+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG1_0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG1_1
+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG2_0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG2_1
+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG3_0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG3_1
+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG4_0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG4_1
+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG5_0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG5_1
+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG6_0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG6_1
+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG7_0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG7_1
+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L
+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L
+//DCHUBBUB_CRC_CTRL
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00001000L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L
+//DCHUBBUB_CRC0_VAL_R_G
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC0_VAL_B_A
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_R_G
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_B_A
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK                                                       0xFFFF0000L
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_dispdec
+//DCHUBBUB_ARB_DF_REQ_OUTSTAND
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xc
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT                   0x17
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000001FFL
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x001FF000L
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK                     0xFF800000L
+//DCHUBBUB_ARB_SAT_LEVEL
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL
+//DCHUBBUB_ARB_QOS_FORCE
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS__SHIFT                                          0xc
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS_MASK                                            0x0000F000L
+//DCHUBBUB_ARB_DRAM_STATE_CNTL
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT  0x8
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT  0x9
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK  0x00000100L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK  0x00000200L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A__SHIFT                 0x10
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A_MASK                   0x3FFF0000L
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A__SHIFT        0x10
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A_MASK          0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A__SHIFT          0x10
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A_MASK            0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT  0x10
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK  0xFFFF0000L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B__SHIFT                 0x10
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B_MASK                   0x3FFF0000L
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B__SHIFT        0x10
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B_MASK          0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B__SHIFT          0x10
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B_MASK            0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT  0x10
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK  0xFFFF0000L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C__SHIFT                 0x10
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK                     0x00003FFFL
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C_MASK                   0x3FFF0000L
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C__SHIFT        0x10
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK                 0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C_MASK          0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C__SHIFT          0x10
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK                   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C_MASK            0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT  0x10
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK  0xFFFF0000L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D__SHIFT                 0x10
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK                     0x00003FFFL
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D_MASK                   0x3FFF0000L
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D__SHIFT        0x10
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK                 0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D_MASK          0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D__SHIFT          0x10
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK                   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D_MASK            0xFFFF0000L
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT  0x10
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK   0x0000FFFFL
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK  0xFFFF0000L
+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000003L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L
+//DCHUBBUB_ARB_TIMEOUT_ENABLE
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L
+//DCHUBBUB_GLOBAL_TIMER_CNTL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L
+//SURFACE_CHECK0_ADDRESS_LSB
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK0_ADDRESS_MSB
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK1_ADDRESS_LSB
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK1_ADDRESS_MSB
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK2_ADDRESS_LSB
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK2_ADDRESS_MSB
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK3_ADDRESS_LSB
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK3_ADDRESS_MSB
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L
+//VTG0_CONTROL
+#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f
+#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L
+//VTG1_CONTROL
+#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f
+#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L
+//VTG2_CONTROL
+#define VTG2_CONTROL__VTG2_FP2__SHIFT                                                                         0x0
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT                                                                      0x1f
+#define VTG2_CONTROL__VTG2_FP2_MASK                                                                           0x00007FFFL
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG2_CONTROL__VTG2_ENABLE_MASK                                                                        0x80000000L
+//VTG3_CONTROL
+#define VTG3_CONTROL__VTG3_FP2__SHIFT                                                                         0x0
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT                                                                      0x1f
+#define VTG3_CONTROL__VTG3_FP2_MASK                                                                           0x00007FFFL
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG3_CONTROL__VTG3_ENABLE_MASK                                                                        0x80000000L
+//DCHUBBUB_SOFT_RESET
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L
+//DCHUBBUB_CLOCK_CNTL
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L
+//DCFCLK_CNTL
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x007FF800L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x13
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x7FF80000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L
+//DCHUBBUB_VLINE_SNAPSHOT
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L
+//DCHUBBUB_CTRL_STATUS
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT                                                  0x0
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK                                                    0x00000001L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L
+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L
+//DCHUBBUB_TEST_DEBUG_INDEX
+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT                                           0x0
+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK                                             0x000000FFL
+//DCHUBBUB_TEST_DEBUG_DATA
+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT                                             0x0
+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK                                               0xFFFFFFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_HOSTVM_CNTL
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT                                          0x0
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT                                    0x1
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT                                                       0x2
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT                                                  0x3
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT                                                  0x4
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT                                           0x5
+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT                                         0x6
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT                                          0x8
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT                                           0x10
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT                                                           0x18
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT                                0x1c
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK                                            0x00000001L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK                                      0x00000002L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK                                                         0x00000004L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK                                                    0x00000008L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK                                                    0x00000010L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK                                             0x00000020L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK                                           0x00000040L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK                                            0x00003F00L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK                                             0x00FF0000L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK                                                             0x0F000000L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK                                  0xF0000000L
+//FMON_CTRL
+#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0
+#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1
+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4
+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5
+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6
+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7
+#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9
+#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc
+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd
+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11
+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16
+#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b
+#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L
+#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L
+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L
+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L
+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L
+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L
+#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L
+#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L
+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L
+#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L
+#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L
+#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L
+//FMON_CTRL_1
+#define FMON_CTRL_1__FMON_START__SHIFT                                                                        0x0
+#define FMON_CTRL_1__FMON_MODE__SHIFT                                                                         0x1
+#define FMON_CTRL_1__FMON_PSTATE_IGNORE__SHIFT                                                                0x4
+#define FMON_CTRL_1__FMON_STATUS_IGNORE__SHIFT                                                                0x5
+#define FMON_CTRL_1__FMON_URG_MODE_GREATER__SHIFT                                                             0x6
+#define FMON_CTRL_1__FMON_FILTER_UID_EN__SHIFT                                                                0x7
+#define FMON_CTRL_1__FMON_STATE__SHIFT                                                                        0x9
+#define FMON_CTRL_1__FMON_URG_FILTER__SHIFT                                                                   0xc
+#define FMON_CTRL_1__FMON_URG_THRESHOLD__SHIFT                                                                0xd
+#define FMON_CTRL_1__FMON_FILTER_UID_1__SHIFT                                                                 0x11
+#define FMON_CTRL_1__FMON_FILTER_UID_2__SHIFT                                                                 0x16
+#define FMON_CTRL_1__FMON_SOF_SEL__SHIFT                                                                      0x1b
+#define FMON_CTRL_1__FMON_START_MASK                                                                          0x00000001L
+#define FMON_CTRL_1__FMON_MODE_MASK                                                                           0x00000006L
+#define FMON_CTRL_1__FMON_PSTATE_IGNORE_MASK                                                                  0x00000010L
+#define FMON_CTRL_1__FMON_STATUS_IGNORE_MASK                                                                  0x00000020L
+#define FMON_CTRL_1__FMON_URG_MODE_GREATER_MASK                                                               0x00000040L
+#define FMON_CTRL_1__FMON_FILTER_UID_EN_MASK                                                                  0x00000180L
+#define FMON_CTRL_1__FMON_STATE_MASK                                                                          0x00000600L
+#define FMON_CTRL_1__FMON_URG_FILTER_MASK                                                                     0x00001000L
+#define FMON_CTRL_1__FMON_URG_THRESHOLD_MASK                                                                  0x0001E000L
+#define FMON_CTRL_1__FMON_FILTER_UID_1_MASK                                                                   0x003E0000L
+#define FMON_CTRL_1__FMON_FILTER_UID_2_MASK                                                                   0x07C00000L
+#define FMON_CTRL_1__FMON_SOF_SEL_MASK                                                                        0x38000000L
+
+
+// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON5_PERFCOUNTER_CNTL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_CNTL2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_STATE
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON5_PERFMON_CNTL
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON5_PERFMON_CNTL2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON5_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON5_PERFMON_CVALUE_LOW
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON5_PERFMON_HI
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON5_PERFMON_LOW
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
+//DCN_VM_CONTEXT0_CNTL
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT1_CNTL
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT2_CNTL
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT3_CNTL
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT4_CNTL
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT5_CNTL
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT6_CNTL
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT7_CNTL
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT8_CNTL
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT9_CNTL
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_CNTL
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT11_CNTL
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT12_CNTL
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT13_CNTL
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT14_CNTL
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT15_CNTL
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_DEFAULT_ADDR_MSB
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L
+//DCN_VM_DEFAULT_ADDR_LSB
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL
+//DCN_VM_FAULT_CNTL
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L
+//DCN_VM_FAULT_STATUS
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT                                                 0x14
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x18
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x1a
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK                                                   0x00F00000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x03000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x3C000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L
+//DCN_VM_FAULT_ADDR_MSB
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL
+//DCN_VM_FAULT_ADDR_LSB
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+//HUBP0_DCSURF_SURFACE_CONFIG
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP0_DCSURF_ADDR_CONFIG
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP0_DCSURF_TILING_CONFIG
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP0_DCSURF_PRI_VIEWPORT_START
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP0_DCHUBP_CNTL
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP0_HUBP_CLK_CNTL
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP0_DCHUBP_VMPG_CONFIG
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP0_HUBPREQ_DEBUG_DB
+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP0_HUBPREQ_DEBUG
+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+//HUBPREQ0_DCSURF_SURFACE_PITCH
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ0_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ0_VMID_SETTINGS_0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ0_DCSURF_SURFACE_CONTROL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL2
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ0_DCN_EXPANSION_MODE
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ0_DCN_TTU_QOS_WM
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_DMDATA_VM_CNTL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ0_BLANK_OFFSET_0
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ0_BLANK_OFFSET_1
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ0_DST_DIMENSIONS
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ0_DST_AFTER_SCALER
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ0_PREFETCH_SETTINGS
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ0_PREFETCH_SETTINGS_C
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ0_VBLANK_PARAMETERS_1
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_2
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_3
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_4
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ0_FLIP_PARAMETERS_1
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_2
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_1
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_2
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_3
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_4
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_5
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_6
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_7
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ0_PER_LINE_DELIVERY_PRE
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ0_PER_LINE_DELIVERY
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ0_CURSOR_SETTINGS
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ0_VBLANK_PARAMETERS_5
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_6
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_3
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_4
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_5
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_6
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+//HUBPRET0_HUBPRET_CONTROL
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET0_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET0_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET0_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET0_HUBPRET_READ_LINE0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE1
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_INTERRUPT
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET0_HUBPRET_READ_LINE_VALUE
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_STATUS
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+//CURSOR0_0_CURSOR_CONTROL
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_0_CURSOR_SIZE
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_0_CURSOR_POSITION
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_0_CURSOR_HOT_SPOT
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_0_CURSOR_STEREO_CONTROL
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_0_CURSOR_DST_OFFSET
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_0_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_0_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_0_DMDATA_ADDRESS_HIGH
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_0_DMDATA_ADDRESS_LOW
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_0_DMDATA_CNTL
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_0_DMDATA_QOS_CNTL
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_0_DMDATA_STATUS
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_0_DMDATA_SW_CNTL
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_0_DMDATA_SW_DATA
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON6_PERFCOUNTER_CNTL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_CNTL2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_STATE
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON6_PERFMON_CNTL
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON6_PERFMON_CNTL2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON6_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON6_PERFMON_CVALUE_LOW
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON6_PERFMON_HI
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON6_PERFMON_LOW
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+//HUBP1_DCSURF_SURFACE_CONFIG
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP1_DCSURF_ADDR_CONFIG
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP1_DCSURF_TILING_CONFIG
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP1_DCSURF_PRI_VIEWPORT_START
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP1_DCHUBP_CNTL
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP1_HUBP_CLK_CNTL
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP1_DCHUBP_VMPG_CONFIG
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP1_HUBPREQ_DEBUG_DB
+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP1_HUBPREQ_DEBUG
+#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+//HUBPREQ1_DCSURF_SURFACE_PITCH
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ1_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ1_VMID_SETTINGS_0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ1_DCSURF_SURFACE_CONTROL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL2
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ1_DCN_EXPANSION_MODE
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ1_DCN_TTU_QOS_WM
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_DMDATA_VM_CNTL
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ1_BLANK_OFFSET_0
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ1_BLANK_OFFSET_1
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ1_DST_DIMENSIONS
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ1_DST_AFTER_SCALER
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ1_PREFETCH_SETTINGS
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ1_PREFETCH_SETTINGS_C
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ1_VBLANK_PARAMETERS_1
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_2
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_3
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_4
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ1_FLIP_PARAMETERS_1
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_2
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_1
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_2
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_3
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_4
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_5
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_6
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_7
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ1_PER_LINE_DELIVERY_PRE
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ1_PER_LINE_DELIVERY
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ1_CURSOR_SETTINGS
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ1_VBLANK_PARAMETERS_5
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_6
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_3
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_4
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_5
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_6
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+//HUBPRET1_HUBPRET_CONTROL
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET1_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET1_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET1_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET1_HUBPRET_READ_LINE0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE1
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_INTERRUPT
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET1_HUBPRET_READ_LINE_VALUE
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_STATUS
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+//CURSOR0_1_CURSOR_CONTROL
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_1_CURSOR_SIZE
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_1_CURSOR_POSITION
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_1_CURSOR_HOT_SPOT
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_1_CURSOR_STEREO_CONTROL
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_1_CURSOR_DST_OFFSET
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_1_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_1_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_1_DMDATA_ADDRESS_HIGH
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_1_DMDATA_ADDRESS_LOW
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_1_DMDATA_CNTL
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_1_DMDATA_QOS_CNTL
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_1_DMDATA_STATUS
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_1_DMDATA_SW_CNTL
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_1_DMDATA_SW_DATA
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON7_PERFCOUNTER_CNTL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_CNTL2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_STATE
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON7_PERFMON_CNTL
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON7_PERFMON_CNTL2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON7_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON7_PERFMON_CVALUE_LOW
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON7_PERFMON_HI
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON7_PERFMON_LOW
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
+//HUBP2_DCSURF_SURFACE_CONFIG
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP2_DCSURF_ADDR_CONFIG
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP2_DCSURF_TILING_CONFIG
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP2_DCSURF_PRI_VIEWPORT_START
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP2_DCHUBP_CNTL
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP2_HUBP_CLK_CNTL
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP2_DCHUBP_VMPG_CONFIG
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP2_HUBPREQ_DEBUG_DB
+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP2_HUBPREQ_DEBUG
+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
+//HUBPREQ2_DCSURF_SURFACE_PITCH
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ2_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ2_VMID_SETTINGS_0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ2_DCSURF_SURFACE_CONTROL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL2
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ2_DCN_EXPANSION_MODE
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ2_DCN_TTU_QOS_WM
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ2_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_DMDATA_VM_CNTL
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ2_BLANK_OFFSET_0
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ2_BLANK_OFFSET_1
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ2_DST_DIMENSIONS
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ2_DST_AFTER_SCALER
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ2_PREFETCH_SETTINGS
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ2_PREFETCH_SETTINGS_C
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ2_VBLANK_PARAMETERS_1
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_2
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_3
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_4
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ2_FLIP_PARAMETERS_1
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_2
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_1
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_2
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_3
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_4
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_5
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_6
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_7
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ2_PER_LINE_DELIVERY_PRE
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ2_PER_LINE_DELIVERY
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ2_CURSOR_SETTINGS
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ2_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ2_VBLANK_PARAMETERS_5
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_6
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_3
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_4
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_5
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_6
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
+//HUBPRET2_HUBPRET_CONTROL
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET2_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET2_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET2_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET2_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET2_HUBPRET_READ_LINE0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE1
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_INTERRUPT
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET2_HUBPRET_READ_LINE_VALUE
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE_STATUS
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
+//CURSOR0_2_CURSOR_CONTROL
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_2_CURSOR_SIZE
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_2_CURSOR_POSITION
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_2_CURSOR_HOT_SPOT
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_2_CURSOR_STEREO_CONTROL
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_2_CURSOR_DST_OFFSET
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_2_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_2_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_2_DMDATA_ADDRESS_HIGH
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_2_DMDATA_ADDRESS_LOW
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_2_DMDATA_CNTL
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_2_DMDATA_QOS_CNTL
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_2_DMDATA_STATUS
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_2_DMDATA_SW_CNTL
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_2_DMDATA_SW_DATA
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON8_PERFCOUNTER_CNTL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_CNTL2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_STATE
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON8_PERFMON_CNTL
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON8_PERFMON_CNTL2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON8_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON8_PERFMON_CVALUE_LOW
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON8_PERFMON_HI
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON8_PERFMON_LOW
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
+//HUBP3_DCSURF_SURFACE_CONFIG
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP3_DCSURF_ADDR_CONFIG
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP3_DCSURF_TILING_CONFIG
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP3_DCSURF_PRI_VIEWPORT_START
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP3_DCHUBP_CNTL
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP3_HUBP_CLK_CNTL
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP3_DCHUBP_VMPG_CONFIG
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP3_HUBPREQ_DEBUG_DB
+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP3_HUBPREQ_DEBUG
+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
+//HUBPREQ3_DCSURF_SURFACE_PITCH
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ3_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ3_VMID_SETTINGS_0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ3_DCSURF_SURFACE_CONTROL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL2
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ3_DCN_EXPANSION_MODE
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ3_DCN_TTU_QOS_WM
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ3_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_DMDATA_VM_CNTL
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ3_BLANK_OFFSET_0
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ3_BLANK_OFFSET_1
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ3_DST_DIMENSIONS
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ3_DST_AFTER_SCALER
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ3_PREFETCH_SETTINGS
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ3_PREFETCH_SETTINGS_C
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ3_VBLANK_PARAMETERS_1
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_2
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_3
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_4
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ3_FLIP_PARAMETERS_1
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_2
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_1
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_2
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_3
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_4
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_5
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_6
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_7
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ3_PER_LINE_DELIVERY_PRE
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ3_PER_LINE_DELIVERY
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ3_CURSOR_SETTINGS
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ3_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ3_VBLANK_PARAMETERS_5
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_6
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_3
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_4
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_5
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_6
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
+//HUBPRET3_HUBPRET_CONTROL
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET3_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET3_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET3_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET3_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET3_HUBPRET_READ_LINE0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE1
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_INTERRUPT
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET3_HUBPRET_READ_LINE_VALUE
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE_STATUS
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
+//CURSOR0_3_CURSOR_CONTROL
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_3_CURSOR_SIZE
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_3_CURSOR_POSITION
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_3_CURSOR_HOT_SPOT
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_3_CURSOR_STEREO_CONTROL
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_3_CURSOR_DST_OFFSET
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_3_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_3_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_3_DMDATA_ADDRESS_HIGH
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_3_DMDATA_ADDRESS_LOW
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_3_DMDATA_CNTL
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_3_DMDATA_QOS_CNTL
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_3_DMDATA_STATUS
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_3_DMDATA_SW_CNTL
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_3_DMDATA_SW_DATA
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON9_PERFCOUNTER_CNTL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_CNTL2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_STATE
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON9_PERFMON_CNTL
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON9_PERFMON_CNTL2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON9_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON9_PERFMON_CVALUE_LOW
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON9_PERFMON_HI
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON9_PERFMON_LOW
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+//DPP_TOP0_DPP_CONTROL
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP0_DPP_SOFT_RESET
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP0_DPP_CRC_VAL_R_G
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP0_DPP_CRC_VAL_B_A
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP0_DPP_CRC_CTRL
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP0_HOST_READ_CONTROL
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG0_FORMAT_CONTROL
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG0_FCNV_FP_BIAS_R
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_G
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_B
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_R
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_G
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_B
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_COLOR_KEYER_CONTROL
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG0_COLOR_KEYER_ALPHA
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_RED
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_GREEN
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_BLUE
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG0_ALPHA_2BIT_LUT
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG0_PRE_DEALPHA
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG0_PRE_CSC_MODE
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG0_PRE_CSC_C11_C12
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C13_C14
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C21_C22
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C23_C24
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C31_C32
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C33_C34
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C11_C12
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C13_C14
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C21_C22
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C23_C24
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C31_C32
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C33_C34
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_CNVC_COEF_FORMAT
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG0_PRE_DEGAM
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG0_PRE_REALPHA
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+//CNVC_CUR0_CURSOR0_CONTROL
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR0_CURSOR0_COLOR0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_COLOR1
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+//DSCL0_SCL_COEF_RAM_TAP_SELECT
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL0_SCL_COEF_RAM_TAP_DATA
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL0_SCL_MODE
+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL0_SCL_TAP_CONTROL
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL0_DSCL_CONTROL
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL0_DSCL_2TAP_CONTROL
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT_C
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL0_SCL_BLACK_COLOR
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL0_DSCL_UPDATE
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL0_DSCL_AUTOCAL
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL0_OTG_H_BLANK
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_OTG_V_BLANK
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_RECOUT_START
+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL0_RECOUT_SIZE
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL0_MPC_SIZE
+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL0_LB_DATA_FORMAT
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL0_LB_MEMORY_CTRL
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL0_LB_V_COUNTER
+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL0_DSCL_MEM_PWR_CTRL
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL0_DSCL_MEM_PWR_STATUS
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL0_OBUF_CONTROL
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL0_OBUF_MEM_PWR_CTRL
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+//CM0_CM_CONTROL
+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM0_CM_POST_CSC_CONTROL
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM0_CM_POST_CSC_C11_C12
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C13_C14
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C21_C22
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C23_C24
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C31_C32
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C33_C34
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_B_C11_C12
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C13_C14
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C21_C22
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C23_C24
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C31_C32
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C33_C34
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_CONTROL
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM0_CM_GAMUT_REMAP_C11_C12
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C13_C14
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C21_C22
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C23_C24
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C31_C32
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C33_C34
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C11_C12
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C13_C14
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C21_C22
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C23_C24
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C31_C32
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C33_C34
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM0_CM_BIAS_CR_R
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM0_CM_BIAS_Y_G_CB_B
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM0_CM_GAMCOR_CONTROL
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM0_CM_GAMCOR_LUT_INDEX
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM0_CM_GAMCOR_LUT_DATA
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM0_CM_GAMCOR_LUT_CONTROL
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_OFFSET_B
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_G
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_R
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_REGION_0_1
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_2_3
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_4_5
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_6_7
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_8_9
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_10_11
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_12_13
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_14_15
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_16_17
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_18_19
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_20_21
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_22_23
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_24_25
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_26_27
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_28_29
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_30_31
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_32_33
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_OFFSET_B
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_G
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_R
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_REGION_0_1
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_2_3
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_4_5
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_6_7
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_8_9
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_10_11
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_12_13
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_14_15
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_16_17
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_18_19
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_20_21
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_22_23
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_24_25
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_26_27
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_28_29
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_30_31
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_32_33
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_BLNDGAM_CONTROL
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM0_CM_BLNDGAM_LUT_INDEX
+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM0_CM_BLNDGAM_LUT_DATA
+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM0_CM_BLNDGAM_LUT_CONTROL
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_HDR_MULT_COEF
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM0_CM_MEM_PWR_CTRL
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM0_CM_MEM_PWR_STATUS
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM0_CM_DEALPHA
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM0_CM_COEF_FORMAT
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM0_CM_SHAPER_CONTROL
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM0_CM_SHAPER_OFFSET_R
+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_OFFSET_G
+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_OFFSET_B
+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_SCALE_R
+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM0_CM_SHAPER_SCALE_G_B
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM0_CM_SHAPER_LUT_INDEX
+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM0_CM_SHAPER_LUT_DATA
+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM0_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM0_CM_SHAPER_RAMA_START_CNTL_B
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_START_CNTL_G
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_START_CNTL_R
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_B
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_G
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_R
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_REGION_0_1
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_2_3
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_4_5
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_6_7
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_8_9
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_10_11
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_12_13
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_14_15
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_16_17
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_18_19
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_20_21
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_22_23
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_24_25
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_26_27
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_28_29
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_30_31
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_32_33
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_B
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_G
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_R
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_B
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_G
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_R
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_REGION_0_1
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_2_3
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_4_5
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_6_7
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_8_9
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_10_11
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_12_13
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_14_15
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_16_17
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_18_19
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_20_21
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_22_23
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_24_25
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_26_27
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_28_29
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_30_31
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_32_33
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_MEM_PWR_CTRL2
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM0_CM_MEM_PWR_STATUS2
+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM0_CM_3DLUT_MODE
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM0_CM_3DLUT_INDEX
+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM0_CM_3DLUT_DATA
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM0_CM_3DLUT_DATA_30BIT
+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM0_CM_3DLUT_READ_WRITE_CONTROL
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM0_CM_3DLUT_OUT_NORM_FACTOR
+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM0_CM_3DLUT_OUT_OFFSET_R
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM0_CM_3DLUT_OUT_OFFSET_G
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM0_CM_3DLUT_OUT_OFFSET_B
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM0_CM_TEST_DEBUG_INDEX
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM0_CM_TEST_DEBUG_DATA
+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON10_PERFCOUNTER_CNTL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_CNTL2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_STATE
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON10_PERFMON_CNTL
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON10_PERFMON_CNTL2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON10_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON10_PERFMON_CVALUE_LOW
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON10_PERFMON_HI
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON10_PERFMON_LOW
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+//DPP_TOP1_DPP_CONTROL
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP1_DPP_SOFT_RESET
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP1_DPP_CRC_VAL_R_G
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP1_DPP_CRC_VAL_B_A
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP1_DPP_CRC_CTRL
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP1_HOST_READ_CONTROL
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG1_FORMAT_CONTROL
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG1_FCNV_FP_BIAS_R
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_G
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_B
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_R
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_G
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_B
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_COLOR_KEYER_CONTROL
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG1_COLOR_KEYER_ALPHA
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_RED
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_GREEN
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_BLUE
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG1_ALPHA_2BIT_LUT
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG1_PRE_DEALPHA
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG1_PRE_CSC_MODE
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG1_PRE_CSC_C11_C12
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C13_C14
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C21_C22
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C23_C24
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C31_C32
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C33_C34
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C11_C12
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C13_C14
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C21_C22
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C23_C24
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C31_C32
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C33_C34
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_CNVC_COEF_FORMAT
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG1_PRE_DEGAM
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG1_PRE_REALPHA
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+//CNVC_CUR1_CURSOR0_CONTROL
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR1_CURSOR0_COLOR0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_COLOR1
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+//DSCL1_SCL_COEF_RAM_TAP_SELECT
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL1_SCL_COEF_RAM_TAP_DATA
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL1_SCL_MODE
+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL1_SCL_TAP_CONTROL
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL1_DSCL_CONTROL
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL1_DSCL_2TAP_CONTROL
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT_C
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL1_SCL_BLACK_COLOR
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL1_DSCL_UPDATE
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL1_DSCL_AUTOCAL
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL1_OTG_H_BLANK
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_OTG_V_BLANK
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_RECOUT_START
+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL1_RECOUT_SIZE
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL1_MPC_SIZE
+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL1_LB_DATA_FORMAT
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL1_LB_MEMORY_CTRL
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL1_LB_V_COUNTER
+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL1_DSCL_MEM_PWR_CTRL
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL1_DSCL_MEM_PWR_STATUS
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL1_OBUF_CONTROL
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL1_OBUF_MEM_PWR_CTRL
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+//CM1_CM_CONTROL
+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM1_CM_POST_CSC_CONTROL
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM1_CM_POST_CSC_C11_C12
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C13_C14
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C21_C22
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C23_C24
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C31_C32
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C33_C34
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_B_C11_C12
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C13_C14
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C21_C22
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C23_C24
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C31_C32
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C33_C34
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_CONTROL
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM1_CM_GAMUT_REMAP_C11_C12
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C13_C14
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C21_C22
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C23_C24
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C31_C32
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C33_C34
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C11_C12
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C13_C14
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C21_C22
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C23_C24
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C31_C32
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C33_C34
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM1_CM_BIAS_CR_R
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM1_CM_BIAS_Y_G_CB_B
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM1_CM_GAMCOR_CONTROL
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM1_CM_GAMCOR_LUT_INDEX
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM1_CM_GAMCOR_LUT_DATA
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM1_CM_GAMCOR_LUT_CONTROL
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_OFFSET_B
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_G
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_R
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_REGION_0_1
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_2_3
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_4_5
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_6_7
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_8_9
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_10_11
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_12_13
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_14_15
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_16_17
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_18_19
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_20_21
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_22_23
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_24_25
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_26_27
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_28_29
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_30_31
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_32_33
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_OFFSET_B
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_G
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_R
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_REGION_0_1
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_2_3
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_4_5
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_6_7
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_8_9
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_10_11
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_12_13
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_14_15
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_16_17
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_18_19
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_20_21
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_22_23
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_24_25
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_26_27
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_28_29
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_30_31
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_32_33
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_BLNDGAM_CONTROL
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM1_CM_BLNDGAM_LUT_INDEX
+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM1_CM_BLNDGAM_LUT_DATA
+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM1_CM_BLNDGAM_LUT_CONTROL
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_HDR_MULT_COEF
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM1_CM_MEM_PWR_CTRL
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM1_CM_MEM_PWR_STATUS
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM1_CM_DEALPHA
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM1_CM_COEF_FORMAT
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM1_CM_SHAPER_CONTROL
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM1_CM_SHAPER_OFFSET_R
+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_OFFSET_G
+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_OFFSET_B
+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_SCALE_R
+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM1_CM_SHAPER_SCALE_G_B
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM1_CM_SHAPER_LUT_INDEX
+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM1_CM_SHAPER_LUT_DATA
+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM1_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM1_CM_SHAPER_RAMA_START_CNTL_B
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_START_CNTL_G
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_START_CNTL_R
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_B
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_G
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_R
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_REGION_0_1
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_2_3
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_4_5
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_6_7
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_8_9
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_10_11
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_12_13
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_14_15
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_16_17
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_18_19
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_20_21
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_22_23
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_24_25
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_26_27
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_28_29
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_30_31
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_32_33
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_B
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_G
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_R
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_B
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_G
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_R
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_REGION_0_1
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_2_3
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_4_5
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_6_7
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_8_9
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_10_11
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_12_13
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_14_15
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_16_17
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_18_19
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_20_21
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_22_23
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_24_25
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_26_27
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_28_29
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_30_31
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_32_33
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_MEM_PWR_CTRL2
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM1_CM_MEM_PWR_STATUS2
+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM1_CM_3DLUT_MODE
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM1_CM_3DLUT_INDEX
+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM1_CM_3DLUT_DATA
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM1_CM_3DLUT_DATA_30BIT
+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM1_CM_3DLUT_READ_WRITE_CONTROL
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM1_CM_3DLUT_OUT_NORM_FACTOR
+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM1_CM_3DLUT_OUT_OFFSET_R
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM1_CM_3DLUT_OUT_OFFSET_G
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM1_CM_3DLUT_OUT_OFFSET_B
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM1_CM_TEST_DEBUG_INDEX
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM1_CM_TEST_DEBUG_DATA
+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON11_PERFCOUNTER_CNTL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_CNTL2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_STATE
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON11_PERFMON_CNTL
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON11_PERFMON_CNTL2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON11_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON11_PERFMON_CVALUE_LOW
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON11_PERFMON_HI
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON11_PERFMON_LOW
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
+//DPP_TOP2_DPP_CONTROL
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP2_DPP_SOFT_RESET
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP2_DPP_CRC_VAL_R_G
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP2_DPP_CRC_VAL_B_A
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP2_DPP_CRC_CTRL
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP2_HOST_READ_CONTROL
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG2_FORMAT_CONTROL
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG2_FCNV_FP_BIAS_R
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_G
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_B
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_R
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_G
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_B
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_COLOR_KEYER_CONTROL
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG2_COLOR_KEYER_ALPHA
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_RED
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_GREEN
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_BLUE
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG2_ALPHA_2BIT_LUT
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG2_PRE_DEALPHA
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG2_PRE_CSC_MODE
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG2_PRE_CSC_C11_C12
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C13_C14
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C21_C22
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C23_C24
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C31_C32
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C33_C34
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C11_C12
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C13_C14
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C21_C22
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C23_C24
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C31_C32
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C33_C34
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_CNVC_COEF_FORMAT
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG2_PRE_DEGAM
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG2_PRE_REALPHA
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
+//CNVC_CUR2_CURSOR0_CONTROL
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR2_CURSOR0_COLOR0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_COLOR1
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
+//DSCL2_SCL_COEF_RAM_TAP_SELECT
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL2_SCL_COEF_RAM_TAP_DATA
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL2_SCL_MODE
+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL2_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL2_SCL_TAP_CONTROL
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL2_DSCL_CONTROL
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL2_DSCL_2TAP_CONTROL
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL2_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT_C
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL2_SCL_BLACK_COLOR
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL2_DSCL_UPDATE
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL2_DSCL_AUTOCAL
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL2_OTG_H_BLANK
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_OTG_V_BLANK
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_RECOUT_START
+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL2_RECOUT_SIZE
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL2_MPC_SIZE
+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL2_LB_DATA_FORMAT
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL2_LB_MEMORY_CTRL
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL2_LB_V_COUNTER
+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL2_DSCL_MEM_PWR_CTRL
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL2_DSCL_MEM_PWR_STATUS
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL2_OBUF_CONTROL
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL2_OBUF_MEM_PWR_CTRL
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
+//CM2_CM_CONTROL
+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM2_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM2_CM_POST_CSC_CONTROL
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM2_CM_POST_CSC_C11_C12
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C13_C14
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C21_C22
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C23_C24
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C31_C32
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C33_C34
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_B_C11_C12
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C13_C14
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C21_C22
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C23_C24
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C31_C32
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C33_C34
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_CONTROL
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM2_CM_GAMUT_REMAP_C11_C12
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C13_C14
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C21_C22
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C23_C24
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C31_C32
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C33_C34
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C11_C12
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C13_C14
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C21_C22
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C23_C24
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C31_C32
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C33_C34
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM2_CM_BIAS_CR_R
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM2_CM_BIAS_Y_G_CB_B
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM2_CM_GAMCOR_CONTROL
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM2_CM_GAMCOR_LUT_INDEX
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM2_CM_GAMCOR_LUT_DATA
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM2_CM_GAMCOR_LUT_CONTROL
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_OFFSET_B
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_G
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_R
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_REGION_0_1
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_2_3
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_4_5
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_6_7
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_8_9
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_10_11
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_12_13
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_14_15
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_16_17
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_18_19
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_20_21
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_22_23
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_24_25
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_26_27
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_28_29
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_30_31
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_32_33
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_OFFSET_B
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_G
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_R
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_REGION_0_1
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_2_3
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_4_5
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_6_7
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_8_9
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_10_11
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_12_13
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_14_15
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_16_17
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_18_19
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_20_21
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_22_23
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_24_25
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_26_27
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_28_29
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_30_31
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_32_33
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_BLNDGAM_CONTROL
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM2_CM_BLNDGAM_LUT_INDEX
+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM2_CM_BLNDGAM_LUT_DATA
+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM2_CM_BLNDGAM_LUT_CONTROL
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_HDR_MULT_COEF
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM2_CM_MEM_PWR_CTRL
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM2_CM_MEM_PWR_STATUS
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM2_CM_DEALPHA
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM2_CM_COEF_FORMAT
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM2_CM_SHAPER_CONTROL
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM2_CM_SHAPER_OFFSET_R
+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM2_CM_SHAPER_OFFSET_G
+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM2_CM_SHAPER_OFFSET_B
+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM2_CM_SHAPER_SCALE_R
+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM2_CM_SHAPER_SCALE_G_B
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM2_CM_SHAPER_LUT_INDEX
+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM2_CM_SHAPER_LUT_DATA
+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM2_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM2_CM_SHAPER_RAMA_START_CNTL_B
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMA_START_CNTL_G
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMA_START_CNTL_R
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_B
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_G
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_R
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_REGION_0_1
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_2_3
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_4_5
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_6_7
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_8_9
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_10_11
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_12_13
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_14_15
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_16_17
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_18_19
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_20_21
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_22_23
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_24_25
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_26_27
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_28_29
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_30_31
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_32_33
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_B
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_G
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_R
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_B
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_G
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_R
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_REGION_0_1
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_2_3
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_4_5
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_6_7
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_8_9
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_10_11
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_12_13
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_14_15
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_16_17
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_18_19
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_20_21
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_22_23
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_24_25
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_26_27
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_28_29
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_30_31
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_32_33
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_MEM_PWR_CTRL2
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM2_CM_MEM_PWR_STATUS2
+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM2_CM_3DLUT_MODE
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM2_CM_3DLUT_INDEX
+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM2_CM_3DLUT_DATA
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM2_CM_3DLUT_DATA_30BIT
+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM2_CM_3DLUT_READ_WRITE_CONTROL
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM2_CM_3DLUT_OUT_NORM_FACTOR
+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM2_CM_3DLUT_OUT_OFFSET_R
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM2_CM_3DLUT_OUT_OFFSET_G
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM2_CM_3DLUT_OUT_OFFSET_B
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM2_CM_TEST_DEBUG_INDEX
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM2_CM_TEST_DEBUG_DATA
+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON12_PERFCOUNTER_CNTL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_CNTL2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_STATE
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON12_PERFMON_CNTL
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON12_PERFMON_CNTL2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON12_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON12_PERFMON_CVALUE_LOW
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON12_PERFMON_HI
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON12_PERFMON_LOW
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
+//DPP_TOP3_DPP_CONTROL
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP3_DPP_SOFT_RESET
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP3_DPP_CRC_VAL_R_G
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP3_DPP_CRC_VAL_B_A
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP3_DPP_CRC_CTRL
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP3_HOST_READ_CONTROL
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG3_FORMAT_CONTROL
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG3_FCNV_FP_BIAS_R
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_G
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_B
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_R
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_G
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_B
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_COLOR_KEYER_CONTROL
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG3_COLOR_KEYER_ALPHA
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_RED
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_GREEN
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_BLUE
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG3_ALPHA_2BIT_LUT
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG3_PRE_DEALPHA
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG3_PRE_CSC_MODE
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG3_PRE_CSC_C11_C12
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C13_C14
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C21_C22
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C23_C24
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C31_C32
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C33_C34
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C11_C12
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C13_C14
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C21_C22
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C23_C24
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C31_C32
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C33_C34
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_CNVC_COEF_FORMAT
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG3_PRE_DEGAM
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG3_PRE_REALPHA
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
+//CNVC_CUR3_CURSOR0_CONTROL
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR3_CURSOR0_COLOR0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_COLOR1
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
+//DSCL3_SCL_COEF_RAM_TAP_SELECT
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL3_SCL_COEF_RAM_TAP_DATA
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL3_SCL_MODE
+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL3_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL3_SCL_TAP_CONTROL
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL3_DSCL_CONTROL
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL3_DSCL_2TAP_CONTROL
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL3_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT_C
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL3_SCL_BLACK_COLOR
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL3_DSCL_UPDATE
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL3_DSCL_AUTOCAL
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL3_OTG_H_BLANK
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_OTG_V_BLANK
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_RECOUT_START
+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL3_RECOUT_SIZE
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL3_MPC_SIZE
+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL3_LB_DATA_FORMAT
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL3_LB_MEMORY_CTRL
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL3_LB_V_COUNTER
+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL3_DSCL_MEM_PWR_CTRL
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL3_DSCL_MEM_PWR_STATUS
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL3_OBUF_CONTROL
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL3_OBUF_MEM_PWR_CTRL
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
+//CM3_CM_CONTROL
+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM3_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM3_CM_POST_CSC_CONTROL
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM3_CM_POST_CSC_C11_C12
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C13_C14
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C21_C22
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C23_C24
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C31_C32
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C33_C34
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_B_C11_C12
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C13_C14
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C21_C22
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C23_C24
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C31_C32
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C33_C34
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_CONTROL
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM3_CM_GAMUT_REMAP_C11_C12
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C13_C14
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C21_C22
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C23_C24
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C31_C32
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C33_C34
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C11_C12
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C13_C14
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C21_C22
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C23_C24
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C31_C32
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C33_C34
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM3_CM_BIAS_CR_R
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM3_CM_BIAS_Y_G_CB_B
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM3_CM_GAMCOR_CONTROL
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM3_CM_GAMCOR_LUT_INDEX
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM3_CM_GAMCOR_LUT_DATA
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM3_CM_GAMCOR_LUT_CONTROL
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_OFFSET_B
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_G
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_R
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_REGION_0_1
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_2_3
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_4_5
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_6_7
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_8_9
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_10_11
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_12_13
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_14_15
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_16_17
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_18_19
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_20_21
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_22_23
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_24_25
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_26_27
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_28_29
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_30_31
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_32_33
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_OFFSET_B
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_G
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_R
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_REGION_0_1
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_2_3
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_4_5
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_6_7
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_8_9
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_10_11
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_12_13
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_14_15
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_16_17
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_18_19
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_20_21
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_22_23
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_24_25
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_26_27
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_28_29
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_30_31
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_32_33
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_BLNDGAM_CONTROL
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM3_CM_BLNDGAM_LUT_INDEX
+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM3_CM_BLNDGAM_LUT_DATA
+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM3_CM_BLNDGAM_LUT_CONTROL
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_HDR_MULT_COEF
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM3_CM_MEM_PWR_CTRL
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM3_CM_MEM_PWR_STATUS
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM3_CM_DEALPHA
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM3_CM_COEF_FORMAT
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM3_CM_SHAPER_CONTROL
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM3_CM_SHAPER_OFFSET_R
+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM3_CM_SHAPER_OFFSET_G
+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM3_CM_SHAPER_OFFSET_B
+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM3_CM_SHAPER_SCALE_R
+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM3_CM_SHAPER_SCALE_G_B
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM3_CM_SHAPER_LUT_INDEX
+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM3_CM_SHAPER_LUT_DATA
+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM3_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM3_CM_SHAPER_RAMA_START_CNTL_B
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMA_START_CNTL_G
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMA_START_CNTL_R
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_B
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_G
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_R
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_REGION_0_1
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_2_3
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_4_5
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_6_7
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_8_9
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_10_11
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_12_13
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_14_15
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_16_17
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_18_19
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_20_21
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_22_23
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_24_25
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_26_27
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_28_29
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_30_31
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_32_33
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_B
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_G
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_R
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_B
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_G
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_R
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_REGION_0_1
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_2_3
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_4_5
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_6_7
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_8_9
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_10_11
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_12_13
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_14_15
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_16_17
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_18_19
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_20_21
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_22_23
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_24_25
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_26_27
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_28_29
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_30_31
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_32_33
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_MEM_PWR_CTRL2
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM3_CM_MEM_PWR_STATUS2
+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM3_CM_3DLUT_MODE
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM3_CM_3DLUT_INDEX
+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM3_CM_3DLUT_DATA
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM3_CM_3DLUT_DATA_30BIT
+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM3_CM_3DLUT_READ_WRITE_CONTROL
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM3_CM_3DLUT_OUT_NORM_FACTOR
+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM3_CM_3DLUT_OUT_OFFSET_R
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM3_CM_3DLUT_OUT_OFFSET_G
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM3_CM_3DLUT_OUT_OFFSET_B
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM3_CM_TEST_DEBUG_INDEX
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM3_CM_TEST_DEBUG_DATA
+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON13_PERFCOUNTER_CNTL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_CNTL2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_STATE
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON13_PERFMON_CNTL
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON13_PERFMON_CNTL2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON13_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON13_PERFMON_CVALUE_LOW
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON13_PERFMON_HI
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON13_PERFMON_LOW
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+//FMT0_FMT_CLAMP_COMPONENT_R
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_G
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_B
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT0_FMT_DYNAMIC_EXP_CNTL
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT0_FMT_CONTROL
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT0_FMT_BIT_DEPTH_CONTROL
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT0_FMT_DITHER_RAND_R_SEED
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_G_SEED
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_B_SEED
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT0_FMT_CLAMP_CNTL
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT0_FMT_MAP420_MEMORY_CONTROL
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT0_FMT_422_CONTROL
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+//DPG0_DPG_CONTROL
+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG0_DPG_RAMP_CONTROL
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG0_DPG_DIMENSIONS
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG0_DPG_COLOUR_R_CR
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG0_DPG_COLOUR_G_Y
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG0_DPG_COLOUR_B_CB
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG0_DPG_OFFSET_SEGMENT
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG0_DPG_STATUS
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+//OPPBUF0_OPPBUF_CONTROL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF0_OPPBUF_CONTROL1
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+//OPP_PIPE0_OPP_PIPE_CONTROL
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+//FMT1_FMT_CLAMP_COMPONENT_R
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_G
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_B
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT1_FMT_DYNAMIC_EXP_CNTL
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT1_FMT_CONTROL
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT1_FMT_BIT_DEPTH_CONTROL
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT1_FMT_DITHER_RAND_R_SEED
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_G_SEED
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_B_SEED
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT1_FMT_CLAMP_CNTL
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT1_FMT_MAP420_MEMORY_CONTROL
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT1_FMT_422_CONTROL
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+//DPG1_DPG_CONTROL
+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG1_DPG_RAMP_CONTROL
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG1_DPG_DIMENSIONS
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG1_DPG_COLOUR_R_CR
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG1_DPG_COLOUR_G_Y
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG1_DPG_COLOUR_B_CB
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG1_DPG_OFFSET_SEGMENT
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG1_DPG_STATUS
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+//OPPBUF1_OPPBUF_CONTROL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF1_OPPBUF_CONTROL1
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+//OPP_PIPE1_OPP_PIPE_CONTROL
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_fmt2_dispdec
+//FMT2_FMT_CLAMP_COMPONENT_R
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_G
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_B
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT2_FMT_DYNAMIC_EXP_CNTL
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT2_FMT_CONTROL
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT2_FMT_BIT_DEPTH_CONTROL
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT2_FMT_DITHER_RAND_R_SEED
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_G_SEED
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_B_SEED
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT2_FMT_CLAMP_CNTL
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT2_FMT_MAP420_MEMORY_CONTROL
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT2_FMT_422_CONTROL
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg2_dispdec
+//DPG2_DPG_CONTROL
+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG2_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG2_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG2_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG2_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG2_DPG_RAMP_CONTROL
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG2_DPG_DIMENSIONS
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG2_DPG_COLOUR_R_CR
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG2_DPG_COLOUR_G_Y
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG2_DPG_COLOUR_B_CB
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG2_DPG_OFFSET_SEGMENT
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG2_DPG_STATUS
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf2_dispdec
+//OPPBUF2_OPPBUF_CONTROL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF2_OPPBUF_CONTROL1
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
+//OPP_PIPE2_OPP_PIPE_CONTROL
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_fmt3_dispdec
+//FMT3_FMT_CLAMP_COMPONENT_R
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_G
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_B
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT3_FMT_DYNAMIC_EXP_CNTL
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT3_FMT_CONTROL
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT3_FMT_BIT_DEPTH_CONTROL
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT3_FMT_DITHER_RAND_R_SEED
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_G_SEED
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_B_SEED
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT3_FMT_CLAMP_CNTL
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT3_FMT_MAP420_MEMORY_CONTROL
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT3_FMT_422_CONTROL
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_dpg3_dispdec
+//DPG3_DPG_CONTROL
+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG3_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG3_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG3_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG3_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG3_DPG_RAMP_CONTROL
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG3_DPG_DIMENSIONS
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG3_DPG_COLOUR_R_CR
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG3_DPG_COLOUR_G_Y
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG3_DPG_COLOUR_B_CB
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG3_DPG_OFFSET_SEGMENT
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG3_DPG_STATUS
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf3_dispdec
+//OPPBUF3_OPPBUF_CONTROL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF3_OPPBUF_CONTROL1
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
+//OPP_PIPE3_OPP_PIPE_CONTROL
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+//OPP_TOP_CLK_CONTROL
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT                                                         0xe
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT                                                         0xf
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK                                                           0x00004000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK                                                           0x00008000L
+//OPP_ABM_CONTROL
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT                                                             0x0
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK                                                               0x00000007L
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm2_dispdec
+//DSCRM2_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON14_PERFCOUNTER_CNTL
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON14_PERFCOUNTER_CNTL2
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON14_PERFCOUNTER_STATE
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON14_PERFMON_CNTL
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON14_PERFMON_CNTL2
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON14_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON14_PERFMON_CVALUE_LOW
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON14_PERFMON_HI
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON14_PERFMON_LOW
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+//ODM0_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM0_OPTC_DATA_SOURCE_SELECT
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x10
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x14
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0x00F00000L
+//ODM0_OPTC_DATA_FORMAT_CONTROL
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM0_OPTC_BYTES_PER_PIXEL
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM0_OPTC_WIDTH_CONTROL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM0_OPTC_INPUT_CLOCK_CONTROL
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM0_OPTC_MEMORY_CONFIG
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+//ODM0_OPTC_INPUT_SPARE_REGISTER
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+//ODM1_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM1_OPTC_DATA_SOURCE_SELECT
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x10
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x14
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0x00F00000L
+//ODM1_OPTC_DATA_FORMAT_CONTROL
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM1_OPTC_BYTES_PER_PIXEL
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM1_OPTC_WIDTH_CONTROL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM1_OPTC_INPUT_CLOCK_CONTROL
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM1_OPTC_MEMORY_CONFIG
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+//ODM1_OPTC_INPUT_SPARE_REGISTER
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm2_dispdec
+//ODM2_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM2_OPTC_DATA_SOURCE_SELECT
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x10
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x14
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0x00F00000L
+//ODM2_OPTC_DATA_FORMAT_CONTROL
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM2_OPTC_BYTES_PER_PIXEL
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM2_OPTC_WIDTH_CONTROL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM2_OPTC_INPUT_CLOCK_CONTROL
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM2_OPTC_MEMORY_CONFIG
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+//ODM2_OPTC_INPUT_SPARE_REGISTER
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm3_dispdec
+//ODM3_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM3_OPTC_DATA_SOURCE_SELECT
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x10
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x14
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0x00F00000L
+//ODM3_OPTC_DATA_FORMAT_CONTROL
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM3_OPTC_BYTES_PER_PIXEL
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM3_OPTC_WIDTH_CONTROL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM3_OPTC_INPUT_CLOCK_CONTROL
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM3_OPTC_MEMORY_CONFIG
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+//ODM3_OPTC_INPUT_SPARE_REGISTER
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+//OTG0_OTG_H_TOTAL
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_H_BLANK_START_END
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_H_SYNC_A
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_H_SYNC_A_CNTL
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG0_OTG_H_TIMING_CNTL
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG0_OTG_V_TOTAL
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_V_TOTAL_MIN
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MAX
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MID
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_CONTROL
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG0_OTG_V_TOTAL_INT_STATUS
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG0_OTG_VSYNC_NOM_INT_STATUS
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG0_OTG_V_BLANK_START_END
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_V_SYNC_A
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_V_SYNC_A_CNTL
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG0_OTG_TRIGA_CNTL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGA_MANUAL_TRIG
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_TRIGB_CNTL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGB_MANUAL_TRIG
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG0_OTG_FLOW_CONTROL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG0_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG0_OTG_CONTROL
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00100000L
+//OTG0_OTG_INTERLACE_CONTROL
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG0_OTG_INTERLACE_STATUS
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG0_OTG_PIXEL_DATA_READBACK0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG0_OTG_PIXEL_DATA_READBACK1
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG0_OTG_STATUS
+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG0_OTG_STATUS_POSITION
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG0_OTG_NOM_VERT_POSITION
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG0_OTG_STATUS_FRAME_COUNT
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG0_OTG_STATUS_VF_COUNT
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_STATUS_HV_COUNT
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_COUNT_CONTROL
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG0_OTG_COUNT_RESET
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG0_OTG_VERT_SYNC_CONTROL
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG0_OTG_STEREO_STATUS
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG0_OTG_STEREO_CONTROL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG0_OTG_SNAPSHOT_STATUS
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG0_OTG_SNAPSHOT_CONTROL
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG0_OTG_SNAPSHOT_POSITION
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG0_OTG_SNAPSHOT_FRAME
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG0_OTG_INTERRUPT_CONTROL
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG0_OTG_UPDATE_LOCK
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG0_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG0_OTG_MASTER_EN
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG0_OTG_BLANK_DATA_COLOR
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
+//OTG0_OTG_BLANK_DATA_COLOR_EXT
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_CRC_CNTL
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG0_OTG_CRC_CNTL2
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_DATA_RG
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC0_DATA_B
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_DATA_RG
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC1_DATA_B
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_RG
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_B
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_RG
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_B
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG0_OTG_STATIC_SCREEN_CONTROL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG0_OTG_3D_STRUCTURE_CONTROL
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG0_OTG_GSL_VSYNC_GAP
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG0_OTG_MASTER_UPDATE_MODE
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG0_OTG_CLOCK_CONTROL
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG0_OTG_VSTARTUP_PARAM
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG0_OTG_VUPDATE_PARAM
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG0_OTG_VREADY_PARAM
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG0_OTG_GLOBAL_SYNC_STATUS
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG0_OTG_MASTER_UPDATE_LOCK
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG0_OTG_GSL_CONTROL
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG0_OTG_GSL_WINDOW_X
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG0_OTG_GSL_WINDOW_Y
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG0_OTG_VUPDATE_KEEPOUT
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL1
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL2
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL3
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG0_OTG_GLOBAL_CONTROL4
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG0_OTG_TRIG_MANUAL_CONTROL
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_MANUAL_FLOW_CONTROL
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_DRR_TIMING_INT_STATUS
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG0_OTG_DRR_V_TOTAL_CHANGE
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG0_OTG_DRR_TRIGGER_WINDOW
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG0_OTG_DRR_CONTROL
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG0_OTG_M_CONST_DTO0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG0_OTG_M_CONST_DTO1
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG0_OTG_REQUEST_CONTROL
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG0_OTG_DSC_START_POSITION
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG0_OTG_PIPE_UPDATE_STATUS
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG0_OTG_SPARE_REGISTER
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+//OTG1_OTG_H_TOTAL
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_H_BLANK_START_END
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_H_SYNC_A
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_H_SYNC_A_CNTL
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG1_OTG_H_TIMING_CNTL
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG1_OTG_V_TOTAL
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_V_TOTAL_MIN
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MAX
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MID
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_CONTROL
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG1_OTG_V_TOTAL_INT_STATUS
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG1_OTG_VSYNC_NOM_INT_STATUS
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG1_OTG_V_BLANK_START_END
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_V_SYNC_A
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_V_SYNC_A_CNTL
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG1_OTG_TRIGA_CNTL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGA_MANUAL_TRIG
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_TRIGB_CNTL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGB_MANUAL_TRIG
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG1_OTG_FLOW_CONTROL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG1_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG1_OTG_CONTROL
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00100000L
+//OTG1_OTG_INTERLACE_CONTROL
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG1_OTG_INTERLACE_STATUS
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG1_OTG_PIXEL_DATA_READBACK0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG1_OTG_PIXEL_DATA_READBACK1
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG1_OTG_STATUS
+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG1_OTG_STATUS_POSITION
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG1_OTG_NOM_VERT_POSITION
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG1_OTG_STATUS_FRAME_COUNT
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG1_OTG_STATUS_VF_COUNT
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_STATUS_HV_COUNT
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_COUNT_CONTROL
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG1_OTG_COUNT_RESET
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG1_OTG_VERT_SYNC_CONTROL
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG1_OTG_STEREO_STATUS
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG1_OTG_STEREO_CONTROL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG1_OTG_SNAPSHOT_STATUS
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG1_OTG_SNAPSHOT_CONTROL
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG1_OTG_SNAPSHOT_POSITION
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG1_OTG_SNAPSHOT_FRAME
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG1_OTG_INTERRUPT_CONTROL
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG1_OTG_UPDATE_LOCK
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG1_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG1_OTG_MASTER_EN
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG1_OTG_BLANK_DATA_COLOR
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
+//OTG1_OTG_BLANK_DATA_COLOR_EXT
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_CRC_CNTL
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG1_OTG_CRC_CNTL2
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_DATA_RG
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC0_DATA_B
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_DATA_RG
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC1_DATA_B
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_RG
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_B
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_RG
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_B
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG1_OTG_STATIC_SCREEN_CONTROL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG1_OTG_3D_STRUCTURE_CONTROL
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG1_OTG_GSL_VSYNC_GAP
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG1_OTG_MASTER_UPDATE_MODE
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG1_OTG_CLOCK_CONTROL
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG1_OTG_VSTARTUP_PARAM
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG1_OTG_VUPDATE_PARAM
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG1_OTG_VREADY_PARAM
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG1_OTG_GLOBAL_SYNC_STATUS
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG1_OTG_MASTER_UPDATE_LOCK
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG1_OTG_GSL_CONTROL
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG1_OTG_GSL_WINDOW_X
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG1_OTG_GSL_WINDOW_Y
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG1_OTG_VUPDATE_KEEPOUT
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL1
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL2
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL3
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG1_OTG_GLOBAL_CONTROL4
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG1_OTG_TRIG_MANUAL_CONTROL
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_MANUAL_FLOW_CONTROL
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_DRR_TIMING_INT_STATUS
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG1_OTG_DRR_V_TOTAL_CHANGE
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG1_OTG_DRR_TRIGGER_WINDOW
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG1_OTG_DRR_CONTROL
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG1_OTG_M_CONST_DTO0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG1_OTG_M_CONST_DTO1
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG1_OTG_REQUEST_CONTROL
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG1_OTG_DSC_START_POSITION
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG1_OTG_PIPE_UPDATE_STATUS
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG1_OTG_SPARE_REGISTER
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg2_dispdec
+//OTG2_OTG_H_TOTAL
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_H_BLANK_START_END
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_H_SYNC_A
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_H_SYNC_A_CNTL
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG2_OTG_H_TIMING_CNTL
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG2_OTG_V_TOTAL
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_V_TOTAL_MIN
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MAX
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MID
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_CONTROL
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG2_OTG_V_TOTAL_INT_STATUS
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG2_OTG_VSYNC_NOM_INT_STATUS
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG2_OTG_V_BLANK_START_END
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_V_SYNC_A
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_V_SYNC_A_CNTL
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG2_OTG_TRIGA_CNTL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGA_MANUAL_TRIG
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_TRIGB_CNTL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGB_MANUAL_TRIG
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG2_OTG_FLOW_CONTROL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG2_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG2_OTG_CONTROL
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00100000L
+//OTG2_OTG_INTERLACE_CONTROL
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG2_OTG_INTERLACE_STATUS
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG2_OTG_PIXEL_DATA_READBACK0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG2_OTG_PIXEL_DATA_READBACK1
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG2_OTG_STATUS
+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG2_OTG_STATUS_POSITION
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG2_OTG_NOM_VERT_POSITION
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG2_OTG_STATUS_FRAME_COUNT
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG2_OTG_STATUS_VF_COUNT
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_STATUS_HV_COUNT
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_COUNT_CONTROL
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG2_OTG_COUNT_RESET
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG2_OTG_VERT_SYNC_CONTROL
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG2_OTG_STEREO_STATUS
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG2_OTG_STEREO_CONTROL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG2_OTG_SNAPSHOT_STATUS
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG2_OTG_SNAPSHOT_CONTROL
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG2_OTG_SNAPSHOT_POSITION
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG2_OTG_SNAPSHOT_FRAME
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG2_OTG_INTERRUPT_CONTROL
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG2_OTG_UPDATE_LOCK
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG2_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG2_OTG_MASTER_EN
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG2_OTG_BLANK_DATA_COLOR
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
+//OTG2_OTG_BLANK_DATA_COLOR_EXT
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
+//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_CRC_CNTL
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG2_OTG_CRC_CNTL2
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_DATA_RG
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC0_DATA_B
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_DATA_RG
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC1_DATA_B
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_RG
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_B
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_RG
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_B
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG2_OTG_STATIC_SCREEN_CONTROL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG2_OTG_3D_STRUCTURE_CONTROL
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG2_OTG_GSL_VSYNC_GAP
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG2_OTG_MASTER_UPDATE_MODE
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG2_OTG_CLOCK_CONTROL
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG2_OTG_VSTARTUP_PARAM
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG2_OTG_VUPDATE_PARAM
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG2_OTG_VREADY_PARAM
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG2_OTG_GLOBAL_SYNC_STATUS
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG2_OTG_MASTER_UPDATE_LOCK
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG2_OTG_GSL_CONTROL
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG2_OTG_GSL_WINDOW_X
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG2_OTG_GSL_WINDOW_Y
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG2_OTG_VUPDATE_KEEPOUT
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL1
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL2
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL3
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG2_OTG_GLOBAL_CONTROL4
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG2_OTG_TRIG_MANUAL_CONTROL
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_MANUAL_FLOW_CONTROL
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_DRR_TIMING_INT_STATUS
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG2_OTG_DRR_V_TOTAL_CHANGE
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG2_OTG_DRR_TRIGGER_WINDOW
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG2_OTG_DRR_CONTROL
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG2_OTG_M_CONST_DTO0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG2_OTG_M_CONST_DTO1
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG2_OTG_REQUEST_CONTROL
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG2_OTG_DSC_START_POSITION
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG2_OTG_PIPE_UPDATE_STATUS
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG2_OTG_SPARE_REGISTER
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg3_dispdec
+//OTG3_OTG_H_TOTAL
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_H_BLANK_START_END
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_H_SYNC_A
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_H_SYNC_A_CNTL
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG3_OTG_H_TIMING_CNTL
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG3_OTG_V_TOTAL
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_V_TOTAL_MIN
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MAX
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MID
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_CONTROL
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG3_OTG_V_TOTAL_INT_STATUS
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG3_OTG_VSYNC_NOM_INT_STATUS
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG3_OTG_V_BLANK_START_END
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_V_SYNC_A
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_V_SYNC_A_CNTL
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG3_OTG_TRIGA_CNTL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGA_MANUAL_TRIG
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_TRIGB_CNTL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGB_MANUAL_TRIG
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG3_OTG_FLOW_CONTROL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG3_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG3_OTG_CONTROL
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00100000L
+//OTG3_OTG_INTERLACE_CONTROL
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG3_OTG_INTERLACE_STATUS
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG3_OTG_PIXEL_DATA_READBACK0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG3_OTG_PIXEL_DATA_READBACK1
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG3_OTG_STATUS
+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG3_OTG_STATUS_POSITION
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG3_OTG_NOM_VERT_POSITION
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG3_OTG_STATUS_FRAME_COUNT
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG3_OTG_STATUS_VF_COUNT
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_STATUS_HV_COUNT
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_COUNT_CONTROL
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG3_OTG_COUNT_RESET
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG3_OTG_VERT_SYNC_CONTROL
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG3_OTG_STEREO_STATUS
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG3_OTG_STEREO_CONTROL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG3_OTG_SNAPSHOT_STATUS
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG3_OTG_SNAPSHOT_CONTROL
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG3_OTG_SNAPSHOT_POSITION
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG3_OTG_SNAPSHOT_FRAME
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG3_OTG_INTERRUPT_CONTROL
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG3_OTG_UPDATE_LOCK
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG3_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG3_OTG_MASTER_EN
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG3_OTG_BLANK_DATA_COLOR
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
+//OTG3_OTG_BLANK_DATA_COLOR_EXT
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
+//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_CRC_CNTL
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG3_OTG_CRC_CNTL2
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_DATA_RG
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC0_DATA_B
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_DATA_RG
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC1_DATA_B
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_RG
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_B
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_RG
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_B
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG3_OTG_STATIC_SCREEN_CONTROL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG3_OTG_3D_STRUCTURE_CONTROL
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG3_OTG_GSL_VSYNC_GAP
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG3_OTG_MASTER_UPDATE_MODE
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG3_OTG_CLOCK_CONTROL
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG3_OTG_VSTARTUP_PARAM
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG3_OTG_VUPDATE_PARAM
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG3_OTG_VREADY_PARAM
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG3_OTG_GLOBAL_SYNC_STATUS
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG3_OTG_MASTER_UPDATE_LOCK
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG3_OTG_GSL_CONTROL
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG3_OTG_GSL_WINDOW_X
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG3_OTG_GSL_WINDOW_Y
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG3_OTG_VUPDATE_KEEPOUT
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL1
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL2
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL3
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG3_OTG_GLOBAL_CONTROL4
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG3_OTG_TRIG_MANUAL_CONTROL
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_MANUAL_FLOW_CONTROL
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_DRR_TIMING_INT_STATUS
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG3_OTG_DRR_V_TOTAL_CHANGE
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG3_OTG_DRR_TRIGGER_WINDOW
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG3_OTG_DRR_CONTROL
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG3_OTG_M_CONST_DTO0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG3_OTG_M_CONST_DTO1
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG3_OTG_REQUEST_CONTROL
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG3_OTG_DSC_START_POSITION
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG3_OTG_PIPE_UPDATE_STATUS
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG3_OTG_SPARE_REGISTER
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+//DWB_SOURCE_SELECT
+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT                                                     0x0
+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT                                                     0x3
+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT                                                     0x6
+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK                                                       0x00000007L
+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK                                                       0x00000038L
+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK                                                       0x000001C0L
+//GSL_SOURCE_SELECT
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L
+//OPTC_CLOCK_CONTROL
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L
+//ODM_MEM_PWR_CTRL
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT                                                           0x10
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT                                                             0x12
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT                                                           0x14
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT                                                             0x16
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT                                                           0x18
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT                                                             0x1a
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT                                                           0x1c
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT                                                             0x1e
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK                                                             0x00030000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK                                                               0x00040000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK                                                             0x00300000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK                                                               0x00400000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK                                                             0x03000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK                                                               0x04000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK                                                             0x30000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK                                                               0x40000000L
+//ODM_MEM_PWR_CTRL2
+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE__SHIFT                                                          0x0
+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS__SHIFT                                                            0x2
+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE__SHIFT                                                          0x4
+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS__SHIFT                                                            0x6
+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE__SHIFT                                                         0x8
+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS__SHIFT                                                           0xa
+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE__SHIFT                                                         0xc
+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS__SHIFT                                                           0xe
+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE_MASK                                                            0x00000003L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS_MASK                                                              0x00000004L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE_MASK                                                            0x00000030L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS_MASK                                                              0x00000040L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE_MASK                                                           0x00000300L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS_MASK                                                             0x00000400L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE_MASK                                                           0x00003000L
+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS_MASK                                                             0x00004000L
+//ODM_MEM_PWR_CTRL3
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL
+//ODM_MEM_PWR_STATUS
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT                                                         0x8
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT                                                         0xa
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT                                                         0xc
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT                                                         0xe
+#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE__SHIFT                                                         0x10
+#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE__SHIFT                                                         0x12
+#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE__SHIFT                                                        0x14
+#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE__SHIFT                                                        0x16
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK                                                           0x00000300L
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK                                                           0x00000C00L
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK                                                           0x00003000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK                                                           0x0000C000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE_MASK                                                           0x00030000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE_MASK                                                           0x000C0000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE_MASK                                                          0x00300000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE_MASK                                                          0x00C00000L
+//OPTC_MISC_SPARE_REGISTER
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL
+
+
+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON15_PERFCOUNTER_CNTL
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON15_PERFCOUNTER_CNTL2
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON15_PERFCOUNTER_STATE
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON15_PERFMON_CNTL
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON15_PERFMON_CNTL2
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON15_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON15_PERFMON_CVALUE_LOW
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON15_PERFMON_HI
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON15_PERFMON_LOW
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+//DC_I2C_CONTROL
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L
+//DC_I2C_ARBITRATION
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L
+//DC_I2C_INTERRUPT_CONTROL
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L
+//DC_I2C_SW_STATUS
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L
+//DC_I2C_DDC1_HW_STATUS
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC2_HW_STATUS
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC3_HW_STATUS
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC4_HW_STATUS
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC1_SPEED
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC1_SETUP
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC2_SPEED
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC2_SETUP
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC3_SPEED
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC3_SETUP
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC4_SPEED
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC4_SETUP
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_TRANSACTION0
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION2
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION3
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L
+//DC_I2C_DATA
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L
+#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L
+//DC_I2C_EDID_DETECT_CTRL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L
+//DC_I2C_READ_REQUEST_INTERRUPT
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+//DIO_SCRATCH0
+#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT                                                                     0x0
+#define DIO_SCRATCH0__DIO_SCRATCH0_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH1
+#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT                                                                     0x0
+#define DIO_SCRATCH1__DIO_SCRATCH1_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH2
+#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT                                                                     0x0
+#define DIO_SCRATCH2__DIO_SCRATCH2_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH3
+#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT                                                                     0x0
+#define DIO_SCRATCH3__DIO_SCRATCH3_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH4
+#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT                                                                     0x0
+#define DIO_SCRATCH4__DIO_SCRATCH4_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH5
+#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT                                                                     0x0
+#define DIO_SCRATCH5__DIO_SCRATCH5_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH6
+#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT                                                                     0x0
+#define DIO_SCRATCH6__DIO_SCRATCH6_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH7
+#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT                                                                     0x0
+#define DIO_SCRATCH7__DIO_SCRATCH7_MASK                                                                       0xFFFFFFFFL
+//DIO_MEM_PWR_STATUS
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT                                                          0x0
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT                                                          0x3
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT                                                          0x4
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT                                                          0x5
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT                                                          0x6
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT                                                          0x7
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT                                                          0x8
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT                                                          0x9
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK                                                            0x00000001L
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK                                                            0x00000008L
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK                                                            0x00000200L
+//DIO_MEM_PWR_CTRL
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT                                                        0x0
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT                                                          0x1
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT                                                          0x4
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT                                                          0x5
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT                                                          0x6
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT                                                          0x7
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT                                                          0x8
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT                                                          0x9
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT                                                          0xa
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK                                                          0x00000001L
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK                                                            0x00000002L
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK                                                            0x00000200L
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK                                                            0x00000400L
+//DIO_MEM_PWR_CTRL2
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT                                                       0x18
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT                                                       0x19
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1a
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1b
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1c
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1d
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1e
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK                                                         0x01000000L
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK                                                         0x02000000L
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK                                                         0x04000000L
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK                                                         0x08000000L
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK                                                         0x10000000L
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK                                                         0x20000000L
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK                                                         0x40000000L
+//DIO_CLK_CNTL
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT                                                           0x5
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT                                                            0xa
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT                                                          0x18
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT                                                          0x19
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT                                                          0x1a
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT                                                          0x1b
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT                                                          0x1c
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT                                                          0x1d
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT                                                          0x1e
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK                                                             0x00000020L
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK                                                              0x00000400L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK                                                            0x01000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK                                                            0x02000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK                                                            0x04000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK                                                            0x08000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK                                                            0x10000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK                                                            0x20000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK                                                            0x40000000L
+//DIO_POWER_MANAGEMENT_CNTL
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT                                                     0x0
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT                                                     0x8
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK                                                       0x00000001L
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK                                                       0x00000100L
+//DIG_SOFT_RESET
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT                                                             0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT                                                             0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT                                                             0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT                                                             0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT                                                             0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT                                                             0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT                                                             0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT                                                             0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT                                                             0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT                                                             0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT                                                             0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT                                                             0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT                                                             0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT                                                             0x19
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK                                                               0x00000001L
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK                                                               0x00000002L
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK                                                               0x00000010L
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK                                                               0x00000020L
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK                                                               0x00000100L
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK                                                               0x00000200L
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK                                                               0x00001000L
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK                                                               0x00002000L
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK                                                               0x00010000L
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK                                                               0x00020000L
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK                                                               0x00100000L
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK                                                               0x00200000L
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK                                                               0x01000000L
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK                                                               0x02000000L
+//DIO_CLK_CNTL2
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT                                                                0x0
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT                                                         0x7
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT                                                         0x8
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT                                                         0x9
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x11
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x12
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x13
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x14
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x15
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x16
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x17
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS__SHIFT                                                           0x18
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS__SHIFT                                                           0x19
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS__SHIFT                                                           0x1a
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS__SHIFT                                                           0x1b
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS__SHIFT                                                           0x1c
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS__SHIFT                                                           0x1d
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS__SHIFT                                                           0x1e
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK                                                                  0x0000007FL
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK                                                           0x00000080L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK                                                           0x00000100L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK                                                           0x00000200L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK                                                        0x00020000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK                                                        0x00040000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK                                                        0x00080000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK                                                        0x00100000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK                                                        0x00200000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK                                                        0x00400000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK                                                        0x00800000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS_MASK                                                             0x01000000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS_MASK                                                             0x02000000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS_MASK                                                             0x04000000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS_MASK                                                             0x08000000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS_MASK                                                             0x10000000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS_MASK                                                             0x20000000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS_MASK                                                             0x40000000L
+//DIO_CLK_CNTL3
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x0
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x1
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x2
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x3
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x4
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x5
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x6
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT                                                         0xe
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT                                                         0xf
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT                                                         0x10
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000001L
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000002L
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000004L
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000008L
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000010L
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000020L
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000040L
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK                                                           0x00004000L
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK                                                           0x00008000L
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK                                                           0x00010000L
+//DIO_HDMI_RXSTATUS_TIMER_CONTROL
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L
+//DIO_GENERIC_INTERRUPT_MESSAGE
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT                                    0x0
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT                                   0x1
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK                                      0x00000001L
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK                                     0xFFFFFFFEL
+//DIO_GENERIC_INTERRUPT_CLEAR
+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT                                       0x0
+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK                                         0x00000001L
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+//HPD0_DC_HPD_INT_STATUS
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD0_DC_HPD_INT_CONTROL
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD0_DC_HPD_CONTROL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD0_DC_HPD_FAST_TRAIN_CNTL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD0_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+//HPD1_DC_HPD_INT_STATUS
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD1_DC_HPD_INT_CONTROL
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD1_DC_HPD_CONTROL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD1_DC_HPD_FAST_TRAIN_CNTL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD1_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd2_dispdec
+//HPD2_DC_HPD_INT_STATUS
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD2_DC_HPD_INT_CONTROL
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD2_DC_HPD_CONTROL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD2_DC_HPD_FAST_TRAIN_CNTL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD2_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd3_dispdec
+//HPD3_DC_HPD_INT_STATUS
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD3_DC_HPD_INT_CONTROL
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD3_DC_HPD_CONTROL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD3_DC_HPD_FAST_TRAIN_CNTL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD3_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON16_PERFCOUNTER_CNTL
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON16_PERFCOUNTER_CNTL2
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON16_PERFCOUNTER_STATE
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON16_PERFMON_CNTL
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON16_PERFMON_CNTL2
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON16_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON16_PERFMON_CVALUE_LOW
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON16_PERFMON_HI
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON16_PERFMON_LOW
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+//DP_AUX0_AUX_CONTROL
+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX0_AUX_SW_CONTROL
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX0_AUX_ARB_CONTROL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX0_AUX_INTERRUPT_CONTROL
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX0_AUX_SW_STATUS
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX0_AUX_LS_STATUS
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX0_AUX_SW_DATA
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX0_AUX_LS_DATA
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX0_AUX_DPHY_TX_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL1
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX0_AUX_DPHY_TX_STATUS
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX0_AUX_DPHY_RX_STATUS
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX0_AUX_PHY_WAKE_CNTL
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+//DP_AUX1_AUX_CONTROL
+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX1_AUX_SW_CONTROL
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX1_AUX_ARB_CONTROL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX1_AUX_INTERRUPT_CONTROL
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX1_AUX_SW_STATUS
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX1_AUX_LS_STATUS
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX1_AUX_SW_DATA
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX1_AUX_LS_DATA
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX1_AUX_DPHY_TX_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL1
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX1_AUX_DPHY_TX_STATUS
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX1_AUX_DPHY_RX_STATUS
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX1_AUX_PHY_WAKE_CNTL
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux2_dispdec
+//DP_AUX2_AUX_CONTROL
+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX2_AUX_SW_CONTROL
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX2_AUX_ARB_CONTROL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX2_AUX_INTERRUPT_CONTROL
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX2_AUX_SW_STATUS
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX2_AUX_LS_STATUS
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX2_AUX_SW_DATA
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX2_AUX_LS_DATA
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX2_AUX_DPHY_TX_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL1
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX2_AUX_DPHY_TX_STATUS
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX2_AUX_DPHY_RX_STATUS
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX2_AUX_PHY_WAKE_CNTL
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux3_dispdec
+//DP_AUX3_AUX_CONTROL
+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX3_AUX_SW_CONTROL
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX3_AUX_ARB_CONTROL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX3_AUX_INTERRUPT_CONTROL
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX3_AUX_SW_STATUS
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX3_AUX_LS_STATUS
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX3_AUX_SW_DATA
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX3_AUX_LS_DATA
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX3_AUX_DPHY_TX_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL1
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX3_AUX_DPHY_TX_STATUS
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX3_AUX_DPHY_RX_STATUS
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX3_AUX_PHY_WAKE_CNTL
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
+//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG0_VPG_GENERIC_PACKET_DATA
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG0_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG0_VPG_GENERIC_STATUS
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG0_VPG_MEM_PWR
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG0_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG0_VPG_ISRC1_2_DATA
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG0_VPG_MPEG_INFO0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG0_VPG_MPEG_INFO1
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
+//AFMT0_AFMT_VBI_PACKET_CONTROL
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT0_AFMT_AUDIO_INFO0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT0_AFMT_AUDIO_INFO1
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT0_AFMT_60958_0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT0_AFMT_60958_1
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_CONTROL
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT0_AFMT_RAMP_CONTROL0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT0_AFMT_RAMP_CONTROL1
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT0_AFMT_RAMP_CONTROL2
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_RAMP_CONTROL3
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_60958_2
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_RESULT
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT0_AFMT_STATUS
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT0_AFMT_INFOFRAME_CONTROL0
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT0_AFMT_INTERRUPT_STATUS
+//AFMT0_AFMT_AUDIO_SRC_CONTROL
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT0_AFMT_MEM_PWR
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
+//DME0_DME_CONTROL
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+//DME0_DME_MEMORY_CONTROL
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+//DIG0_DIG_FE_CNTL
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG0_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG0_DIG_OUTPUT_CRC_CNTL
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG0_DIG_OUTPUT_CRC_RESULT
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG0_DIG_CLOCK_PATTERN
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG0_DIG_TEST_PATTERN
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG0_DIG_RANDOM_PATTERN_SEED
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG0_DIG_FIFO_STATUS
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG0_HDMI_METADATA_PACKET_CONTROL
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG0_HDMI_CONTROL
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG0_HDMI_STATUS
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG0_HDMI_AUDIO_PACKET_CONTROL
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG0_HDMI_ACR_PACKET_CONTROL
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG0_HDMI_VBI_PACKET_CONTROL
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG0_HDMI_INFOFRAME_CONTROL0
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG0_HDMI_INFOFRAME_CONTROL1
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG0_HDMI_GC
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG0_HDMI_DB_CONTROL
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG0_HDMI_ACR_32_0
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_32_1
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_44_0
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_44_1
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_48_0
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_48_1
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_STATUS_0
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG0_HDMI_ACR_STATUS_1
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG0_AFMT_CNTL
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG0_DIG_BE_CNTL
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG0_DIG_BE_EN_CNTL
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG0_TMDS_CNTL
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG0_TMDS_CONTROL_CHAR
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG0_TMDS_CONTROL0_FEEDBACK
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG0_TMDS_STEREOSYNC_CTL_SEL
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG0_TMDS_CTL_BITS
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG0_TMDS_DCBALANCER_CONTROL
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG0_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG0_DIG_VERSION
+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG0_DIG_LANE_ENABLE
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
+//DIG0_FORCE_DIG_DISABLE
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+//DP0_DP_LINK_CNTL
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP0_DP_PIXEL_FORMAT
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP0_DP_MSA_COLORIMETRY
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP0_DP_CONFIG
+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP0_DP_VID_STREAM_CNTL
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP0_DP_STEER_FIFO
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP0_DP_MSA_MISC
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP0_DP_DPHY_INTERNAL_CTRL
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP0_DP_VID_TIMING
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP0_DP_VID_N
+#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP0_DP_VID_M
+#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP0_DP_LINK_FRAMING_CNTL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP0_DP_HBR2_EYE_PATTERN
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP0_DP_VID_MSA_VBID
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP0_DP_VID_INTERRUPT_CNTL
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP0_DP_DPHY_CNTL
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP0_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP0_DP_DPHY_SYM0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM1
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM2
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP0_DP_DPHY_8B10B_CNTL
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP0_DP_DPHY_PRBS_CNTL
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP0_DP_DPHY_SCRAM_CNTL
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP0_DP_DPHY_CRC_EN
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP0_DP_DPHY_CRC_CNTL
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP0_DP_DPHY_CRC_RESULT
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP0_DP_DPHY_CRC_MST_CNTL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP0_DP_DPHY_CRC_MST_STATUS
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP0_DP_DPHY_FAST_TRAINING
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP0_DP_DPHY_FAST_TRAINING_STATUS
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP0_DP_SEC_CNTL
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL1
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_FRAMING1
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING2
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING3
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP0_DP_SEC_FRAMING4
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP0_DP_SEC_AUD_N
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_N_READBACK
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_AUD_M
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_M_READBACK
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_TIMESTAMP
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP0_DP_SEC_PACKET_CNTL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP0_DP_MSE_RATE_CNTL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP0_DP_MSE_RATE_UPDATE
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP0_DP_MSE_SAT0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT1
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT2
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT_UPDATE
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP0_DP_MSE_LINK_TIMING
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP0_DP_MSE_MISC_CNTL
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP0_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP0_DP_MSE_SAT0_STATUS
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT1_STATUS
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT2_STATUS
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSA_TIMING_PARAM1
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM2
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM3
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP0_DP_MSA_TIMING_PARAM4
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP0_DP_MSO_CNTL
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP0_DP_MSO_CNTL1
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP0_DP_DSC_CNTL
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP0_DP_SEC_CNTL2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL3
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL4
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL5
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL6
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP0_DP_SEC_CNTL7
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP0_DP_DB_CNTL
+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP0_DP_MSA_VBID_MISC
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP0_DP_SEC_METADATA_TRANSMISSION
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP0_DP_DSC_BYTES_PER_PIXEL
+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP0_DP_ALPM_CNTL
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP0_DP_GSP8_CNTL
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP9_CNTL
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP10_CNTL
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP11_CNTL
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP_EN_DB_STATUS
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
+//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG1_VPG_GENERIC_PACKET_DATA
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG1_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG1_VPG_GENERIC_STATUS
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG1_VPG_MEM_PWR
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG1_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG1_VPG_ISRC1_2_DATA
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG1_VPG_MPEG_INFO0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG1_VPG_MPEG_INFO1
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
+//AFMT1_AFMT_VBI_PACKET_CONTROL
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT1_AFMT_AUDIO_INFO0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT1_AFMT_AUDIO_INFO1
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT1_AFMT_60958_0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT1_AFMT_60958_1
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_CONTROL
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT1_AFMT_RAMP_CONTROL0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT1_AFMT_RAMP_CONTROL1
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT1_AFMT_RAMP_CONTROL2
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_RAMP_CONTROL3
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_60958_2
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_RESULT
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT1_AFMT_STATUS
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT1_AFMT_INFOFRAME_CONTROL0
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT1_AFMT_INTERRUPT_STATUS
+//AFMT1_AFMT_AUDIO_SRC_CONTROL
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT1_AFMT_MEM_PWR
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
+//DME1_DME_CONTROL
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+//DME1_DME_MEMORY_CONTROL
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+//DIG1_DIG_FE_CNTL
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG1_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG1_DIG_OUTPUT_CRC_CNTL
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG1_DIG_OUTPUT_CRC_RESULT
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG1_DIG_CLOCK_PATTERN
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG1_DIG_TEST_PATTERN
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG1_DIG_RANDOM_PATTERN_SEED
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG1_DIG_FIFO_STATUS
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG1_HDMI_METADATA_PACKET_CONTROL
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG1_HDMI_CONTROL
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG1_HDMI_STATUS
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG1_HDMI_AUDIO_PACKET_CONTROL
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG1_HDMI_ACR_PACKET_CONTROL
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG1_HDMI_VBI_PACKET_CONTROL
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG1_HDMI_INFOFRAME_CONTROL0
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG1_HDMI_INFOFRAME_CONTROL1
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG1_HDMI_GC
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG1_HDMI_DB_CONTROL
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG1_HDMI_ACR_32_0
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_32_1
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_44_0
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_44_1
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_48_0
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_48_1
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_STATUS_0
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG1_HDMI_ACR_STATUS_1
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG1_AFMT_CNTL
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG1_DIG_BE_CNTL
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG1_DIG_BE_EN_CNTL
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG1_TMDS_CNTL
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG1_TMDS_CONTROL_CHAR
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG1_TMDS_CONTROL0_FEEDBACK
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG1_TMDS_STEREOSYNC_CTL_SEL
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG1_TMDS_CTL_BITS
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG1_TMDS_DCBALANCER_CONTROL
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG1_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG1_DIG_VERSION
+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG1_DIG_LANE_ENABLE
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
+//DIG1_FORCE_DIG_DISABLE
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+//DP1_DP_LINK_CNTL
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP1_DP_PIXEL_FORMAT
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP1_DP_MSA_COLORIMETRY
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP1_DP_CONFIG
+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP1_DP_VID_STREAM_CNTL
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP1_DP_STEER_FIFO
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP1_DP_MSA_MISC
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP1_DP_DPHY_INTERNAL_CTRL
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP1_DP_VID_TIMING
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP1_DP_VID_N
+#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP1_DP_VID_M
+#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP1_DP_LINK_FRAMING_CNTL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP1_DP_HBR2_EYE_PATTERN
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP1_DP_VID_MSA_VBID
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP1_DP_VID_INTERRUPT_CNTL
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP1_DP_DPHY_CNTL
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP1_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP1_DP_DPHY_SYM0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM1
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM2
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP1_DP_DPHY_8B10B_CNTL
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP1_DP_DPHY_PRBS_CNTL
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP1_DP_DPHY_SCRAM_CNTL
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP1_DP_DPHY_CRC_EN
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP1_DP_DPHY_CRC_CNTL
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP1_DP_DPHY_CRC_RESULT
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP1_DP_DPHY_CRC_MST_CNTL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP1_DP_DPHY_CRC_MST_STATUS
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP1_DP_DPHY_FAST_TRAINING
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP1_DP_DPHY_FAST_TRAINING_STATUS
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP1_DP_SEC_CNTL
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL1
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_FRAMING1
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING2
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING3
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP1_DP_SEC_FRAMING4
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP1_DP_SEC_AUD_N
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_N_READBACK
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_AUD_M
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_M_READBACK
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_TIMESTAMP
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP1_DP_SEC_PACKET_CNTL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP1_DP_MSE_RATE_CNTL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP1_DP_MSE_RATE_UPDATE
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP1_DP_MSE_SAT0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT1
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT2
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT_UPDATE
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP1_DP_MSE_LINK_TIMING
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP1_DP_MSE_MISC_CNTL
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP1_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP1_DP_MSE_SAT0_STATUS
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT1_STATUS
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT2_STATUS
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSA_TIMING_PARAM1
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM2
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM3
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP1_DP_MSA_TIMING_PARAM4
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP1_DP_MSO_CNTL
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP1_DP_MSO_CNTL1
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP1_DP_DSC_CNTL
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP1_DP_SEC_CNTL2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL3
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL4
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL5
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL6
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP1_DP_SEC_CNTL7
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP1_DP_DB_CNTL
+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP1_DP_MSA_VBID_MISC
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP1_DP_SEC_METADATA_TRANSMISSION
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP1_DP_DSC_BYTES_PER_PIXEL
+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP1_DP_ALPM_CNTL
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP1_DP_GSP8_CNTL
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP9_CNTL
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP10_CNTL
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP11_CNTL
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP_EN_DB_STATUS
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
+//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG2_VPG_GENERIC_PACKET_DATA
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG2_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG2_VPG_GENERIC_STATUS
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG2_VPG_MEM_PWR
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG2_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG2_VPG_ISRC1_2_DATA
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG2_VPG_MPEG_INFO0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG2_VPG_MPEG_INFO1
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
+//AFMT2_AFMT_VBI_PACKET_CONTROL
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT2_AFMT_AUDIO_INFO0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT2_AFMT_AUDIO_INFO1
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT2_AFMT_60958_0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT2_AFMT_60958_1
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_CONTROL
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT2_AFMT_RAMP_CONTROL0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT2_AFMT_RAMP_CONTROL1
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT2_AFMT_RAMP_CONTROL2
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_RAMP_CONTROL3
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_60958_2
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_RESULT
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT2_AFMT_STATUS
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT2_AFMT_INFOFRAME_CONTROL0
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT2_AFMT_INTERRUPT_STATUS
+//AFMT2_AFMT_AUDIO_SRC_CONTROL
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT2_AFMT_MEM_PWR
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
+//DME2_DME_CONTROL
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+//DME2_DME_MEMORY_CONTROL
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig2_dispdec
+//DIG2_DIG_FE_CNTL
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG2_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG2_DIG_OUTPUT_CRC_CNTL
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG2_DIG_OUTPUT_CRC_RESULT
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG2_DIG_CLOCK_PATTERN
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG2_DIG_TEST_PATTERN
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG2_DIG_RANDOM_PATTERN_SEED
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG2_DIG_FIFO_STATUS
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG2_HDMI_METADATA_PACKET_CONTROL
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG2_HDMI_CONTROL
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG2_HDMI_STATUS
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG2_HDMI_AUDIO_PACKET_CONTROL
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG2_HDMI_ACR_PACKET_CONTROL
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG2_HDMI_VBI_PACKET_CONTROL
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG2_HDMI_INFOFRAME_CONTROL0
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG2_HDMI_INFOFRAME_CONTROL1
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG2_HDMI_GC
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG2_HDMI_DB_CONTROL
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG2_HDMI_ACR_32_0
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_32_1
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_44_0
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_44_1
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_48_0
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_48_1
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_STATUS_0
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG2_HDMI_ACR_STATUS_1
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG2_AFMT_CNTL
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG2_DIG_BE_CNTL
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG2_DIG_BE_EN_CNTL
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG2_TMDS_CNTL
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG2_TMDS_CONTROL_CHAR
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG2_TMDS_CONTROL0_FEEDBACK
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG2_TMDS_STEREOSYNC_CTL_SEL
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG2_TMDS_CTL_BITS
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG2_TMDS_DCBALANCER_CONTROL
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG2_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG2_DIG_VERSION
+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG2_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG2_DIG_LANE_ENABLE
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
+#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
+#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
+#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
+//DIG2_FORCE_DIG_DISABLE
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp2_dispdec
+//DP2_DP_LINK_CNTL
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP2_DP_PIXEL_FORMAT
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP2_DP_MSA_COLORIMETRY
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP2_DP_CONFIG
+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP2_DP_VID_STREAM_CNTL
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP2_DP_STEER_FIFO
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP2_DP_MSA_MISC
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP2_DP_DPHY_INTERNAL_CTRL
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP2_DP_VID_TIMING
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP2_DP_VID_N
+#define DP2_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP2_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP2_DP_VID_M
+#define DP2_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP2_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP2_DP_LINK_FRAMING_CNTL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP2_DP_HBR2_EYE_PATTERN
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP2_DP_VID_MSA_VBID
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP2_DP_VID_INTERRUPT_CNTL
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP2_DP_DPHY_CNTL
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP2_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP2_DP_DPHY_SYM0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM1
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM2
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP2_DP_DPHY_8B10B_CNTL
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP2_DP_DPHY_PRBS_CNTL
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP2_DP_DPHY_SCRAM_CNTL
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP2_DP_DPHY_CRC_EN
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP2_DP_DPHY_CRC_CNTL
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP2_DP_DPHY_CRC_RESULT
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP2_DP_DPHY_CRC_MST_CNTL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP2_DP_DPHY_CRC_MST_STATUS
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP2_DP_DPHY_FAST_TRAINING
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP2_DP_DPHY_FAST_TRAINING_STATUS
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP2_DP_SEC_CNTL
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL1
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_FRAMING1
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING2
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING3
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP2_DP_SEC_FRAMING4
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP2_DP_SEC_AUD_N
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_N_READBACK
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_AUD_M
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_M_READBACK
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_TIMESTAMP
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP2_DP_SEC_PACKET_CNTL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP2_DP_MSE_RATE_CNTL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP2_DP_MSE_RATE_UPDATE
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP2_DP_MSE_SAT0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT1
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT2
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT_UPDATE
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP2_DP_MSE_LINK_TIMING
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP2_DP_MSE_MISC_CNTL
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP2_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP2_DP_MSE_SAT0_STATUS
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT1_STATUS
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT2_STATUS
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSA_TIMING_PARAM1
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM2
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM3
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP2_DP_MSA_TIMING_PARAM4
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP2_DP_MSO_CNTL
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP2_DP_MSO_CNTL1
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP2_DP_DSC_CNTL
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP2_DP_SEC_CNTL2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL3
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL4
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL5
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL6
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP2_DP_SEC_CNTL7
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP2_DP_DB_CNTL
+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP2_DP_MSA_VBID_MISC
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP2_DP_SEC_METADATA_TRANSMISSION
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP2_DP_DSC_BYTES_PER_PIXEL
+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP2_DP_ALPM_CNTL
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP2_DP_GSP8_CNTL
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP9_CNTL
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP10_CNTL
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP11_CNTL
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP_EN_DB_STATUS
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
+//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG3_VPG_GENERIC_PACKET_DATA
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG3_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG3_VPG_GENERIC_STATUS
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG3_VPG_MEM_PWR
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG3_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG3_VPG_ISRC1_2_DATA
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG3_VPG_MPEG_INFO0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG3_VPG_MPEG_INFO1
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
+//AFMT3_AFMT_VBI_PACKET_CONTROL
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT3_AFMT_AUDIO_INFO0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT3_AFMT_AUDIO_INFO1
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT3_AFMT_60958_0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT3_AFMT_60958_1
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_CONTROL
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT3_AFMT_RAMP_CONTROL0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT3_AFMT_RAMP_CONTROL1
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT3_AFMT_RAMP_CONTROL2
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_RAMP_CONTROL3
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_60958_2
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_RESULT
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT3_AFMT_STATUS
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT3_AFMT_INFOFRAME_CONTROL0
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT3_AFMT_INTERRUPT_STATUS
+//AFMT3_AFMT_AUDIO_SRC_CONTROL
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT3_AFMT_MEM_PWR
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
+//DME3_DME_CONTROL
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+//DME3_DME_MEMORY_CONTROL
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig3_dispdec
+//DIG3_DIG_FE_CNTL
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG3_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG3_DIG_OUTPUT_CRC_CNTL
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG3_DIG_OUTPUT_CRC_RESULT
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG3_DIG_CLOCK_PATTERN
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG3_DIG_TEST_PATTERN
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG3_DIG_RANDOM_PATTERN_SEED
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG3_DIG_FIFO_STATUS
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG3_HDMI_METADATA_PACKET_CONTROL
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG3_HDMI_CONTROL
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG3_HDMI_STATUS
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG3_HDMI_AUDIO_PACKET_CONTROL
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG3_HDMI_ACR_PACKET_CONTROL
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG3_HDMI_VBI_PACKET_CONTROL
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG3_HDMI_INFOFRAME_CONTROL0
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG3_HDMI_INFOFRAME_CONTROL1
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG3_HDMI_GC
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG3_HDMI_DB_CONTROL
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG3_HDMI_ACR_32_0
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_32_1
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_44_0
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_44_1
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_48_0
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_48_1
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_STATUS_0
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG3_HDMI_ACR_STATUS_1
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG3_AFMT_CNTL
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG3_DIG_BE_CNTL
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG3_DIG_BE_EN_CNTL
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG3_TMDS_CNTL
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG3_TMDS_CONTROL_CHAR
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG3_TMDS_CONTROL0_FEEDBACK
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG3_TMDS_STEREOSYNC_CTL_SEL
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG3_TMDS_CTL_BITS
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG3_TMDS_DCBALANCER_CONTROL
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG3_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG3_DIG_VERSION
+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG3_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG3_DIG_LANE_ENABLE
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
+#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
+#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
+#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
+//DIG3_FORCE_DIG_DISABLE
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp3_dispdec
+//DP3_DP_LINK_CNTL
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP3_DP_PIXEL_FORMAT
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP3_DP_MSA_COLORIMETRY
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP3_DP_CONFIG
+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP3_DP_VID_STREAM_CNTL
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP3_DP_STEER_FIFO
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP3_DP_MSA_MISC
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP3_DP_DPHY_INTERNAL_CTRL
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP3_DP_VID_TIMING
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP3_DP_VID_N
+#define DP3_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP3_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP3_DP_VID_M
+#define DP3_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP3_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP3_DP_LINK_FRAMING_CNTL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP3_DP_HBR2_EYE_PATTERN
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP3_DP_VID_MSA_VBID
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP3_DP_VID_INTERRUPT_CNTL
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP3_DP_DPHY_CNTL
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP3_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP3_DP_DPHY_SYM0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM1
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM2
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP3_DP_DPHY_8B10B_CNTL
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP3_DP_DPHY_PRBS_CNTL
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP3_DP_DPHY_SCRAM_CNTL
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP3_DP_DPHY_CRC_EN
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP3_DP_DPHY_CRC_CNTL
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP3_DP_DPHY_CRC_RESULT
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP3_DP_DPHY_CRC_MST_CNTL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP3_DP_DPHY_CRC_MST_STATUS
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP3_DP_DPHY_FAST_TRAINING
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP3_DP_DPHY_FAST_TRAINING_STATUS
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP3_DP_SEC_CNTL
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL1
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_FRAMING1
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING2
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING3
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP3_DP_SEC_FRAMING4
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP3_DP_SEC_AUD_N
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_N_READBACK
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_AUD_M
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_M_READBACK
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_TIMESTAMP
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP3_DP_SEC_PACKET_CNTL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP3_DP_MSE_RATE_CNTL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP3_DP_MSE_RATE_UPDATE
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP3_DP_MSE_SAT0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT1
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT2
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT_UPDATE
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP3_DP_MSE_LINK_TIMING
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP3_DP_MSE_MISC_CNTL
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP3_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP3_DP_MSE_SAT0_STATUS
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT1_STATUS
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT2_STATUS
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSA_TIMING_PARAM1
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM2
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM3
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP3_DP_MSA_TIMING_PARAM4
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP3_DP_MSO_CNTL
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP3_DP_MSO_CNTL1
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP3_DP_DSC_CNTL
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP3_DP_SEC_CNTL2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL3
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL4
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL5
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL6
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP3_DP_SEC_CNTL7
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP3_DP_DB_CNTL
+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP3_DP_MSA_VBID_MISC
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP3_DP_SEC_METADATA_TRANSMISSION
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP3_DP_DSC_BYTES_PER_PIXEL
+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP3_DP_ALPM_CNTL
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP3_DP_GSP8_CNTL
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP9_CNTL
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP10_CNTL
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP11_CNTL
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP_EN_DB_STATUS
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+//DC_GENERICA
+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DC_GENERICB
+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DCIO_CLOCK_CNTL
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
+//DC_REF_CLK_CNTL
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
+//UNIPHYA_LINK_CNTL
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_BYPASS_PWRSEQ__SHIFT                                                   0x1a
+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_BYPASS_PWRSEQ_MASK                                                     0x04000000L
+//UNIPHYA_CHANNEL_XBAR_CNTL
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
+//UNIPHYB_LINK_CNTL
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_BYPASS_PWRSEQ__SHIFT                                                   0x1a
+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_BYPASS_PWRSEQ_MASK                                                     0x04000000L
+//UNIPHYB_CHANNEL_XBAR_CNTL
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
+//UNIPHYC_LINK_CNTL
+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_BYPASS_PWRSEQ__SHIFT                                                   0x1a
+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_BYPASS_PWRSEQ_MASK                                                     0x04000000L
+//UNIPHYC_CHANNEL_XBAR_CNTL
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
+//UNIPHYD_LINK_CNTL
+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_BYPASS_PWRSEQ__SHIFT                                                   0x1a
+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_BYPASS_PWRSEQ_MASK                                                     0x04000000L
+//UNIPHYD_CHANNEL_XBAR_CNTL
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
+//DCIO_WRCMD_DELAY
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT                                                                0xc
+#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT                                                                   0x10
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK                                                                  0x0000F000L
+#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK                                                                     0x000F0000L
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
+//DC_PINSTRAPS
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
+//PANEL_PWRSEQ0_CNTL
+#define PANEL_PWRSEQ0_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                            0x0
+#define PANEL_PWRSEQ0_CNTL__PANEL_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT                               0x1
+#define PANEL_PWRSEQ0_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                                  0x4
+#define PANEL_PWRSEQ0_CNTL__PANEL_SYNCEN__SHIFT                                                               0x8
+#define PANEL_PWRSEQ0_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                          0x9
+#define PANEL_PWRSEQ0_CNTL__PANEL_SYNCEN_POL__SHIFT                                                           0xa
+#define PANEL_PWRSEQ0_CNTL__PANEL_DIGON__SHIFT                                                                0x10
+#define PANEL_PWRSEQ0_CNTL__PANEL_DIGON_OVRD__SHIFT                                                           0x11
+#define PANEL_PWRSEQ0_CNTL__PANEL_DIGON_POL__SHIFT                                                            0x12
+#define PANEL_PWRSEQ0_CNTL__PANEL_BLON__SHIFT                                                                 0x18
+#define PANEL_PWRSEQ0_CNTL__PANEL_BLON_OVRD__SHIFT                                                            0x19
+#define PANEL_PWRSEQ0_CNTL__PANEL_BLON_POL__SHIFT                                                             0x1a
+#define PANEL_PWRSEQ0_CNTL__PANEL_PWRSEQ_EN_MASK                                                              0x00000001L
+#define PANEL_PWRSEQ0_CNTL__PANEL_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK                                 0x00000002L
+#define PANEL_PWRSEQ0_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                                    0x00000010L
+#define PANEL_PWRSEQ0_CNTL__PANEL_SYNCEN_MASK                                                                 0x00000100L
+#define PANEL_PWRSEQ0_CNTL__PANEL_SYNCEN_OVRD_MASK                                                            0x00000200L
+#define PANEL_PWRSEQ0_CNTL__PANEL_SYNCEN_POL_MASK                                                             0x00000400L
+#define PANEL_PWRSEQ0_CNTL__PANEL_DIGON_MASK                                                                  0x00010000L
+#define PANEL_PWRSEQ0_CNTL__PANEL_DIGON_OVRD_MASK                                                             0x00020000L
+#define PANEL_PWRSEQ0_CNTL__PANEL_DIGON_POL_MASK                                                              0x00040000L
+#define PANEL_PWRSEQ0_CNTL__PANEL_BLON_MASK                                                                   0x01000000L
+#define PANEL_PWRSEQ0_CNTL__PANEL_BLON_OVRD_MASK                                                              0x02000000L
+#define PANEL_PWRSEQ0_CNTL__PANEL_BLON_POL_MASK                                                               0x04000000L
+//PANEL_PWRSEQ0_STATE
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                               0x0
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                        0x1
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                       0x2
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                         0x3
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                         0x4
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                        0x8
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                                 0x00000001L
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_DIGON_MASK                                                          0x00000002L
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                         0x00000004L
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_BLON_MASK                                                           0x00000008L
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_DONE_MASK                                                           0x00000010L
+#define PANEL_PWRSEQ0_STATE__PANEL_PWRSEQ_STATE_MASK                                                          0x00000F00L
+//PANEL_PWRSEQ0_REF_DIV
+#define PANEL_PWRSEQ0_REF_DIV__PANEL_PWRSEQ_REF_DIV__SHIFT                                                    0x0
+#define PANEL_PWRSEQ0_REF_DIV__BL_PWM_REF_DIV__SHIFT                                                          0x10
+#define PANEL_PWRSEQ0_REF_DIV__PANEL_PWRSEQ_REF_DIV_MASK                                                      0x00000FFFL
+#define PANEL_PWRSEQ0_REF_DIV__BL_PWM_REF_DIV_MASK                                                            0xFFFF0000L
+//PANEL_PWRSEQ0_DELAY1
+#define PANEL_PWRSEQ0_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                       0x0
+#define PANEL_PWRSEQ0_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                       0x8
+#define PANEL_PWRSEQ0_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                       0x10
+#define PANEL_PWRSEQ0_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                       0x18
+#define PANEL_PWRSEQ0_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                         0x000000FFL
+#define PANEL_PWRSEQ0_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                         0x0000FF00L
+#define PANEL_PWRSEQ0_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                         0x00FF0000L
+#define PANEL_PWRSEQ0_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                         0xFF000000L
+//PANEL_PWRSEQ0_DELAY2
+#define PANEL_PWRSEQ0_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                                   0x0
+#define PANEL_PWRSEQ0_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                       0x8
+#define PANEL_PWRSEQ0_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                       0x10
+#define PANEL_PWRSEQ0_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                                0x18
+#define PANEL_PWRSEQ0_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                                     0x000000FFL
+#define PANEL_PWRSEQ0_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                         0x0000FF00L
+#define PANEL_PWRSEQ0_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                         0x00FF0000L
+#define PANEL_PWRSEQ0_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                                  0x01000000L
+//BL_PWM0_CNTL
+#define BL_PWM0_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                           0x0
+#define BL_PWM0_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                             0x1e
+#define BL_PWM0_CNTL__BL_PWM_EN__SHIFT                                                                        0x1f
+#define BL_PWM0_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                             0x0000FFFFL
+#define BL_PWM0_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                               0x40000000L
+#define BL_PWM0_CNTL__BL_PWM_EN_MASK                                                                          0x80000000L
+//BL_PWM0_CNTL2
+#define BL_PWM0_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                     0x0
+#define BL_PWM0_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                                   0x1e
+#define BL_PWM0_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                                 0x1f
+#define BL_PWM0_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                       0x0000FFFFL
+#define BL_PWM0_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                                     0x40000000L
+#define BL_PWM0_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                                   0x80000000L
+//BL_PWM0_PERIOD_CNTL
+#define BL_PWM0_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                             0x0
+#define BL_PWM0_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                                      0x10
+#define BL_PWM0_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                               0x0000FFFFL
+#define BL_PWM0_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                        0x000F0000L
+//BL_PWM0_GRP1_REG_LOCK
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                                    0x0
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                          0x8
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                       0x10
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT                                        0x11
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                                    0x18
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                       0x1f
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                                      0x00000001L
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                            0x00000100L
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                         0x00010000L
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK                                          0x000E0000L
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                                      0x01000000L
+#define BL_PWM0_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                         0x80000000L
+//DCIO_GSL_GENLK_PAD_CNTL
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
+//DCIO_GSL_SWAPLOCK_PAD_CNTL
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
+//DCIO_SOFT_RESET
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x1
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x2
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x3
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x4
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0x5
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x6
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0x7
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x8
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0x9
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0xa
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xb
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0xc
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xd
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT                                                            0x14
+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT                                                               0x1a
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000002L
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000004L
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000008L
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000010L
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000020L
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000040L
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000080L
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000100L
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00000200L
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000400L
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00000800L
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00001000L
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00002000L
+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK                                                              0x00100000L
+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK                                                                 0x04000000L
+//PANEL_PWRSEQ1_CNTL
+#define PANEL_PWRSEQ1_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                            0x0
+#define PANEL_PWRSEQ1_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                                  0x4
+#define PANEL_PWRSEQ1_CNTL__PANEL_SYNCEN__SHIFT                                                               0x8
+#define PANEL_PWRSEQ1_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                          0x9
+#define PANEL_PWRSEQ1_CNTL__PANEL_SYNCEN_POL__SHIFT                                                           0xa
+#define PANEL_PWRSEQ1_CNTL__PANEL_DIGON__SHIFT                                                                0x10
+#define PANEL_PWRSEQ1_CNTL__PANEL_DIGON_OVRD__SHIFT                                                           0x11
+#define PANEL_PWRSEQ1_CNTL__PANEL_DIGON_POL__SHIFT                                                            0x12
+#define PANEL_PWRSEQ1_CNTL__PANEL_BLON__SHIFT                                                                 0x18
+#define PANEL_PWRSEQ1_CNTL__PANEL_BLON_OVRD__SHIFT                                                            0x19
+#define PANEL_PWRSEQ1_CNTL__PANEL_BLON_POL__SHIFT                                                             0x1a
+#define PANEL_PWRSEQ1_CNTL__PANEL_PWRSEQ_EN_MASK                                                              0x00000001L
+#define PANEL_PWRSEQ1_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                                    0x00000010L
+#define PANEL_PWRSEQ1_CNTL__PANEL_SYNCEN_MASK                                                                 0x00000100L
+#define PANEL_PWRSEQ1_CNTL__PANEL_SYNCEN_OVRD_MASK                                                            0x00000200L
+#define PANEL_PWRSEQ1_CNTL__PANEL_SYNCEN_POL_MASK                                                             0x00000400L
+#define PANEL_PWRSEQ1_CNTL__PANEL_DIGON_MASK                                                                  0x00010000L
+#define PANEL_PWRSEQ1_CNTL__PANEL_DIGON_OVRD_MASK                                                             0x00020000L
+#define PANEL_PWRSEQ1_CNTL__PANEL_DIGON_POL_MASK                                                              0x00040000L
+#define PANEL_PWRSEQ1_CNTL__PANEL_BLON_MASK                                                                   0x01000000L
+#define PANEL_PWRSEQ1_CNTL__PANEL_BLON_OVRD_MASK                                                              0x02000000L
+#define PANEL_PWRSEQ1_CNTL__PANEL_BLON_POL_MASK                                                               0x04000000L
+//PANEL_PWRSEQ1_STATE
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                               0x0
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                        0x1
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                       0x2
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                         0x3
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                         0x4
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                        0x8
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                                 0x00000001L
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_DIGON_MASK                                                          0x00000002L
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                         0x00000004L
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_BLON_MASK                                                           0x00000008L
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_DONE_MASK                                                           0x00000010L
+#define PANEL_PWRSEQ1_STATE__PANEL_PWRSEQ_STATE_MASK                                                          0x00000F00L
+//PANEL_PWRSEQ1_REF_DIV
+#define PANEL_PWRSEQ1_REF_DIV__PANEL_PWRSEQ_REF_DIV__SHIFT                                                    0x0
+#define PANEL_PWRSEQ1_REF_DIV__BL_PWM_REF_DIV__SHIFT                                                          0x10
+#define PANEL_PWRSEQ1_REF_DIV__PANEL_PWRSEQ_REF_DIV_MASK                                                      0x00000FFFL
+#define PANEL_PWRSEQ1_REF_DIV__BL_PWM_REF_DIV_MASK                                                            0xFFFF0000L
+//PANEL_PWRSEQ1_DELAY1
+#define PANEL_PWRSEQ1_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                       0x0
+#define PANEL_PWRSEQ1_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                       0x8
+#define PANEL_PWRSEQ1_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                       0x10
+#define PANEL_PWRSEQ1_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                       0x18
+#define PANEL_PWRSEQ1_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                         0x000000FFL
+#define PANEL_PWRSEQ1_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                         0x0000FF00L
+#define PANEL_PWRSEQ1_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                         0x00FF0000L
+#define PANEL_PWRSEQ1_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                         0xFF000000L
+//PANEL_PWRSEQ1_DELAY2
+#define PANEL_PWRSEQ1_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                                   0x0
+#define PANEL_PWRSEQ1_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                       0x8
+#define PANEL_PWRSEQ1_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                       0x10
+#define PANEL_PWRSEQ1_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                                0x18
+#define PANEL_PWRSEQ1_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                                     0x000000FFL
+#define PANEL_PWRSEQ1_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                         0x0000FF00L
+#define PANEL_PWRSEQ1_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                         0x00FF0000L
+#define PANEL_PWRSEQ1_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                                  0x01000000L
+//BL_PWM1_CNTL
+#define BL_PWM1_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                           0x0
+#define BL_PWM1_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                             0x1e
+#define BL_PWM1_CNTL__BL_PWM_EN__SHIFT                                                                        0x1f
+#define BL_PWM1_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                             0x0000FFFFL
+#define BL_PWM1_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                               0x40000000L
+#define BL_PWM1_CNTL__BL_PWM_EN_MASK                                                                          0x80000000L
+//BL_PWM1_CNTL2
+#define BL_PWM1_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                     0x0
+#define BL_PWM1_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                                   0x1e
+#define BL_PWM1_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                                 0x1f
+#define BL_PWM1_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                       0x0000FFFFL
+#define BL_PWM1_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                                     0x40000000L
+#define BL_PWM1_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                                   0x80000000L
+//BL_PWM1_PERIOD_CNTL
+#define BL_PWM1_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                             0x0
+#define BL_PWM1_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                                      0x10
+#define BL_PWM1_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                               0x0000FFFFL
+#define BL_PWM1_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                        0x000F0000L
+//BL_PWM1_GRP1_REG_LOCK
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                                    0x0
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                          0x8
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                       0x10
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT                                        0x11
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                                    0x18
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                       0x1f
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                                      0x00000001L
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                            0x00000100L
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                         0x00010000L
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK                                          0x000E0000L
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                                      0x01000000L
+#define BL_PWM1_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                         0x80000000L
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+//DC_GPIO_GENERIC_MASK
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
+//DC_GPIO_GENERIC_A
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
+//DC_GPIO_GENERIC_EN
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
+//DC_GPIO_GENERIC_Y
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
+//DC_GPIO_DDC1_MASK
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC1_A
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC1_EN
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC1_Y
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_MASK
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC2_A
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_EN
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC2_Y
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_MASK
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC3_A
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_EN
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC3_Y
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_MASK
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC4_A
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_EN
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC4_Y
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDCVGA_MASK
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
+//DC_GPIO_DDCVGA_A
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
+//DC_GPIO_DDCVGA_EN
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
+//DC_GPIO_DDCVGA_Y
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
+//DC_GPIO_GENLK_MASK
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
+//DC_GPIO_GENLK_A
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
+//DC_GPIO_GENLK_EN
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
+//DC_GPIO_GENLK_Y
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
+//DC_GPIO_HPD_MASK
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT                                                          0x1
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT                                                        0x2
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT                                                        0x3
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK                                                            0x00000002L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK                                                          0x00000004L
+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK                                                          0x00000008L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
+//DC_GPIO_HPD_A
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
+//DC_GPIO_HPD_EN
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT                                                               0x3
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT                                                               0x4
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT                                                                    0x7
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK                                                                 0x00000008L
+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK                                                                 0x00000010L
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
+#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK                                                                      0x00000080L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
+//DC_GPIO_HPD_Y
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
+//DC_GPIO_PWRSEQ0_MASK
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_BLON_MASK__SHIFT                                                        0x0
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                                      0x4
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_BLON_RECV__SHIFT                                                        0x6
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                       0x8
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                                     0xc
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                       0xe
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_ENA_BL_MASK__SHIFT                                                      0x10
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT                                                    0x14
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_ENA_BL_RECV__SHIFT                                                      0x16
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT                                                    0x18
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT                                                    0x1a
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT                                                    0x1c
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT                                                  0x1d
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT                                                    0x1e
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_BLON_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                        0x00000010L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_BLON_RECV_MASK                                                          0x000000C0L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_DIGON_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                       0x00001000L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_DIGON_RECV_MASK                                                         0x0000C000L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_ENA_BL_MASK_MASK                                                        0x00010000L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK                                                      0x00100000L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_ENA_BL_RECV_MASK                                                        0x00C00000L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_VSYNC_IN_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_VSYNC_IN_RECV_MASK                                                      0x04000000L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_HSYNC_IN_MASK_MASK                                                      0x10000000L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK                                                    0x20000000L
+#define DC_GPIO_PWRSEQ0_MASK__DC_GPIO_HSYNC_IN_RECV_MASK                                                      0x40000000L
+//DC_GPIO_PWRSEQ0_A
+#define DC_GPIO_PWRSEQ0_A__DC_GPIO_BLON_A__SHIFT                                                              0x0
+#define DC_GPIO_PWRSEQ0_A__DC_GPIO_DIGON_A__SHIFT                                                             0x8
+#define DC_GPIO_PWRSEQ0_A__DC_GPIO_ENA_BL_A__SHIFT                                                            0x10
+#define DC_GPIO_PWRSEQ0_A__DC_GPIO_VSYNC_IN_A__SHIFT                                                          0x18
+#define DC_GPIO_PWRSEQ0_A__DC_GPIO_HSYNC_IN_A__SHIFT                                                          0x1f
+#define DC_GPIO_PWRSEQ0_A__DC_GPIO_BLON_A_MASK                                                                0x00000001L
+#define DC_GPIO_PWRSEQ0_A__DC_GPIO_DIGON_A_MASK                                                               0x00000100L
+#define DC_GPIO_PWRSEQ0_A__DC_GPIO_ENA_BL_A_MASK                                                              0x00010000L
+#define DC_GPIO_PWRSEQ0_A__DC_GPIO_VSYNC_IN_A_MASK                                                            0x01000000L
+#define DC_GPIO_PWRSEQ0_A__DC_GPIO_HSYNC_IN_A_MASK                                                            0x80000000L
+//DC_GPIO_PWRSEQ0_EN
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_EN__SHIFT                                                            0x0
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_DIGON_EN__SHIFT                                                           0x8
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_ENA_BL_EN__SHIFT                                                          0x10
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VSYNC_IN_EN__SHIFT                                                        0x18
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_ENA_BL_OTG_VSYNC_EN__SHIFT                                                0x19
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_ENA_BL_OTG_VSYNC_SEL__SHIFT                                               0x1a
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_HSYNC_IN_EN__SHIFT                                                        0x1f
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_EN_MASK                                                              0x00000001L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x00000002L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_DIGON_EN_MASK                                                             0x00000100L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_ENA_BL_EN_MASK                                                            0x00010000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VSYNC_IN_EN_MASK                                                          0x01000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_ENA_BL_OTG_VSYNC_EN_MASK                                                  0x02000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_ENA_BL_OTG_VSYNC_SEL_MASK                                                 0x1C000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_HSYNC_IN_EN_MASK                                                          0x80000000L
+//DC_GPIO_PWRSEQ0_Y
+#define DC_GPIO_PWRSEQ0_Y__DC_GPIO_BLON_Y__SHIFT                                                              0x0
+#define DC_GPIO_PWRSEQ0_Y__DC_GPIO_DIGON_Y__SHIFT                                                             0x8
+#define DC_GPIO_PWRSEQ0_Y__DC_GPIO_ENA_BL_Y__SHIFT                                                            0x10
+#define DC_GPIO_PWRSEQ0_Y__DC_GPIO_VSYNC_IN__SHIFT                                                            0x18
+#define DC_GPIO_PWRSEQ0_Y__DC_GPIO_HSYNC_IN__SHIFT                                                            0x1f
+#define DC_GPIO_PWRSEQ0_Y__DC_GPIO_BLON_Y_MASK                                                                0x00000001L
+#define DC_GPIO_PWRSEQ0_Y__DC_GPIO_DIGON_Y_MASK                                                               0x00000100L
+#define DC_GPIO_PWRSEQ0_Y__DC_GPIO_ENA_BL_Y_MASK                                                              0x00010000L
+#define DC_GPIO_PWRSEQ0_Y__DC_GPIO_VSYNC_IN_MASK                                                              0x01000000L
+#define DC_GPIO_PWRSEQ0_Y__DC_GPIO_HSYNC_IN_MASK                                                              0x80000000L
+//DC_GPIO_PAD_STRENGTH_1
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT                                                     0x8
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT                                                     0xc
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK                                                       0x00000F00L
+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK                                                       0x0000F000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
+//DC_GPIO_PAD_STRENGTH_2
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT                                                     0x10
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT                                                     0x14
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK                                                       0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK                                                       0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
+//PHY_AUX_CNTL
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT                                                               0x0
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT                                                                0x1
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT                                                               0x2
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT                                                                0x3
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT                                                              0x4
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT                                                                 0x5
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT                                                               0x6
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT                                                                  0x7
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT                                                               0x8
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT                                                                0x17
+#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT                                                                    0x18
+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT                                                                0x1c
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK                                                                 0x00000001L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK                                                                  0x00000002L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK                                                                 0x00000004L
+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK                                                                  0x00000008L
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK                                                                0x00000010L
+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK                                                                   0x00000020L
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK                                                                 0x00000040L
+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK                                                                    0x00000080L
+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK                                                                 0x00000100L
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK                                                                  0x00800000L
+#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK                                                                      0x03000000L
+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK                                                                  0x70000000L
+//DC_GPIO_PWRSEQ1_MASK
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_BLON_MASK__SHIFT                                                        0x0
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                                      0x4
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_BLON_RECV__SHIFT                                                        0x6
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                       0x8
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                                     0xc
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                       0xe
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_ENA_BL_MASK__SHIFT                                                      0x10
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT                                                    0x14
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_ENA_BL_RECV__SHIFT                                                      0x16
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_BLON_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                        0x00000010L
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_BLON_RECV_MASK                                                          0x000000C0L
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_DIGON_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                       0x00001000L
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_DIGON_RECV_MASK                                                         0x0000C000L
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_ENA_BL_MASK_MASK                                                        0x00010000L
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK                                                      0x00100000L
+#define DC_GPIO_PWRSEQ1_MASK__DC_GPIO_ENA_BL_RECV_MASK                                                        0x00C00000L
+//DC_GPIO_PWRSEQ1_A
+#define DC_GPIO_PWRSEQ1_A__DC_GPIO_BLON_A__SHIFT                                                              0x0
+#define DC_GPIO_PWRSEQ1_A__DC_GPIO_DIGON_A__SHIFT                                                             0x8
+#define DC_GPIO_PWRSEQ1_A__DC_GPIO_ENA_BL_A__SHIFT                                                            0x10
+#define DC_GPIO_PWRSEQ1_A__DC_GPIO_BLON_A_MASK                                                                0x00000001L
+#define DC_GPIO_PWRSEQ1_A__DC_GPIO_DIGON_A_MASK                                                               0x00000100L
+#define DC_GPIO_PWRSEQ1_A__DC_GPIO_ENA_BL_A_MASK                                                              0x00010000L
+//DC_GPIO_PWRSEQ1_EN
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_EN__SHIFT                                                            0x0
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_DIGON_EN__SHIFT                                                           0x8
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_ENA_BL_EN__SHIFT                                                          0x10
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_ENA_BL_OTG_VSYNC_EN__SHIFT                                                0x19
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_ENA_BL_OTG_VSYNC_SEL__SHIFT                                               0x1a
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_EN_MASK                                                              0x00000001L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_DIGON_EN_MASK                                                             0x00000100L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_ENA_BL_EN_MASK                                                            0x00010000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_ENA_BL_OTG_VSYNC_EN_MASK                                                  0x02000000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_ENA_BL_OTG_VSYNC_SEL_MASK                                                 0x1C000000L
+//DC_GPIO_PWRSEQ1_Y
+#define DC_GPIO_PWRSEQ1_Y__DC_GPIO_BLON_Y__SHIFT                                                              0x0
+#define DC_GPIO_PWRSEQ1_Y__DC_GPIO_DIGON_Y__SHIFT                                                             0x8
+#define DC_GPIO_PWRSEQ1_Y__DC_GPIO_ENA_BL_Y__SHIFT                                                            0x10
+#define DC_GPIO_PWRSEQ1_Y__DC_GPIO_BLON_Y_MASK                                                                0x00000001L
+#define DC_GPIO_PWRSEQ1_Y__DC_GPIO_DIGON_Y_MASK                                                               0x00000100L
+#define DC_GPIO_PWRSEQ1_Y__DC_GPIO_ENA_BL_Y_MASK                                                              0x00010000L
+//DC_GPIO_TX12_EN
+#define DC_GPIO_TX12_EN__DC_GPIO_BLON0_TX12_EN__SHIFT                                                         0x0
+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON0_TX12_EN__SHIFT                                                        0x1
+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL0_TX12_EN__SHIFT                                                       0x2
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
+#define DC_GPIO_TX12_EN__DC_GPIO_BLON1_TX12_EN__SHIFT                                                         0xa
+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON1_TX12_EN__SHIFT                                                        0xb
+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL1_TX12_EN__SHIFT                                                       0xc
+#define DC_GPIO_TX12_EN__DC_GPIO_BLON0_TX12_EN_MASK                                                           0x00000001L
+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON0_TX12_EN_MASK                                                          0x00000002L
+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL0_TX12_EN_MASK                                                         0x00000004L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
+#define DC_GPIO_TX12_EN__DC_GPIO_BLON1_TX12_EN_MASK                                                           0x00000400L
+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON1_TX12_EN_MASK                                                          0x00000800L
+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL1_TX12_EN_MASK                                                         0x00001000L
+//DC_GPIO_AUX_CTRL_0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00400000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0x40000000L
+//DC_GPIO_AUX_CTRL_1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x9
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xc
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00000200L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00000800L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00001000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0x40000000L
+//DC_GPIO_AUX_CTRL_2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
+//DC_GPIO_RXEN
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
+#define DC_GPIO_RXEN__DC_GPIO_BLON0_RXEN__SHIFT                                                               0x14
+#define DC_GPIO_RXEN__DC_GPIO_DIGON0_RXEN__SHIFT                                                              0x15
+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL0_RXEN__SHIFT                                                             0x16
+#define DC_GPIO_RXEN__DC_GPIO_BLON1_RXEN__SHIFT                                                               0x17
+#define DC_GPIO_RXEN__DC_GPIO_DIGON1_RXEN__SHIFT                                                              0x18
+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL1_RXEN__SHIFT                                                             0x19
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
+#define DC_GPIO_RXEN__DC_GPIO_BLON0_RXEN_MASK                                                                 0x00100000L
+#define DC_GPIO_RXEN__DC_GPIO_DIGON0_RXEN_MASK                                                                0x00200000L
+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL0_RXEN_MASK                                                               0x00400000L
+#define DC_GPIO_RXEN__DC_GPIO_BLON1_RXEN_MASK                                                                 0x00800000L
+#define DC_GPIO_RXEN__DC_GPIO_DIGON1_RXEN_MASK                                                                0x01000000L
+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL1_RXEN_MASK                                                               0x02000000L
+//DC_GPIO_PULLUPEN
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON0_PU_EN__SHIFT                                                          0x14
+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON0_PU_EN__SHIFT                                                         0x15
+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL0_PU_EN__SHIFT                                                        0x16
+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON1_PU_EN__SHIFT                                                          0x17
+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON1_PU_EN__SHIFT                                                         0x18
+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL1_PU_EN__SHIFT                                                        0x19
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON0_PU_EN_MASK                                                            0x00100000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON0_PU_EN_MASK                                                           0x00200000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL0_PU_EN_MASK                                                          0x00400000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON1_PU_EN_MASK                                                            0x00800000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON1_PU_EN_MASK                                                           0x01000000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL1_PU_EN_MASK                                                          0x02000000L
+//DC_GPIO_AUX_CTRL_3
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
+//DC_GPIO_AUX_CTRL_4
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
+//DC_GPIO_AUX_CTRL_5
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
+//AUXI2C_PAD_ALL_PWR_OK
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+//DSC_TOP0_DSC_TOP_CONTROL
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP0_DSC_DEBUG_CONTROL
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+//DSCCIF0_DSCCIF_CONFIG0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF0_DSCCIF_CONFIG1
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+//DSCC0_DSCC_CONFIG0
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC0_DSCC_CONFIG1
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+//DSCC0_DSCC_STATUS
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+//DSCC0_DSCC_PPS_CONFIG0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG1
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG2
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG3
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG4
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG5
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG6
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC0_DSCC_PPS_CONFIG7
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG8
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG9
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG11
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG12
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG13
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG14
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG15
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG16
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG17
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG18
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG19
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG20
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG21
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG22
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC0_DSCC_MEM_POWER_CONTROL
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_MAX_ABS_ERROR0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC0_DSCC_MAX_ABS_ERROR1
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON17_PERFCOUNTER_CNTL
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON17_PERFCOUNTER_CNTL2
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON17_PERFCOUNTER_STATE
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON17_PERFMON_CNTL
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON17_PERFMON_CNTL2
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON17_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON17_PERFMON_CVALUE_LOW
+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON17_PERFMON_HI
+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON17_PERFMON_LOW
+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+//DSC_TOP1_DSC_TOP_CONTROL
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP1_DSC_DEBUG_CONTROL
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+//DSCCIF1_DSCCIF_CONFIG0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF1_DSCCIF_CONFIG1
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+//DSCC1_DSCC_CONFIG0
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC1_DSCC_CONFIG1
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+//DSCC1_DSCC_STATUS
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+//DSCC1_DSCC_PPS_CONFIG0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG1
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG2
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG3
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG4
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG5
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG6
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC1_DSCC_PPS_CONFIG7
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG8
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG9
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG11
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG12
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG13
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG14
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG15
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG16
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG17
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG18
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG19
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG20
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG21
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG22
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC1_DSCC_MEM_POWER_CONTROL
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_MAX_ABS_ERROR0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC1_DSCC_MAX_ABS_ERROR1
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON18_PERFCOUNTER_CNTL
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON18_PERFCOUNTER_CNTL2
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON18_PERFCOUNTER_STATE
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON18_PERFMON_CNTL
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON18_PERFMON_CNTL2
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON18_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON18_PERFMON_CVALUE_LOW
+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON18_PERFMON_HI
+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON18_PERFMON_LOW
+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
+//DSC_TOP2_DSC_TOP_CONTROL
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP2_DSC_DEBUG_CONTROL
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
+//DSCCIF2_DSCCIF_CONFIG0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF2_DSCCIF_CONFIG1
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
+//DSCC2_DSCC_CONFIG0
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC2_DSCC_CONFIG1
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+//DSCC2_DSCC_STATUS
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+//DSCC2_DSCC_PPS_CONFIG0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG1
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG2
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG3
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG4
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG5
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG6
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC2_DSCC_PPS_CONFIG7
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG8
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG9
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG11
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG12
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG13
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG14
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG15
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG16
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG17
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG18
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG19
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG20
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG21
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG22
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC2_DSCC_MEM_POWER_CONTROL
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_MAX_ABS_ERROR0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC2_DSCC_MAX_ABS_ERROR1
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON19_PERFCOUNTER_CNTL
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON19_PERFCOUNTER_CNTL2
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON19_PERFCOUNTER_STATE
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON19_PERFMON_CNTL
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON19_PERFMON_CNTL2
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON19_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON19_PERFMON_CVALUE_LOW
+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON19_PERFMON_HI
+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON19_PERFMON_LOW
+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
+//DWB_ENABLE_CLK_CTRL
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT                                                                0x0
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT                                                    0x4
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT                                                    0x8
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT                                                          0xc
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK                                                                  0x00000001L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK                                                      0x00000010L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK                                                      0x00000100L
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK                                                            0x00003000L
+//DWB_MEM_PWR_CTRL
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT                                                   0xc
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT                                                   0x14
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK                                                     0x00003000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK                                                     0x00300000L
+//FC_MODE_CTRL
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT                                                              0x0
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT                                                            0x4
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT                                                                0x8
+#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT                                                                 0xc
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT                                                           0x10
+#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT                                                                   0x14
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                      0x1f
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK                                                                0x00000001L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK                                                              0x00000030L
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK                                                                  0x00000100L
+#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK                                                                   0x00003000L
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK                                                             0x00010000L
+#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK                                                                     0x00100000L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK                                                        0x80000000L
+//FC_FLOW_CTRL
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT                                                       0x0
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK                                                         0x00000FFFL
+//FC_WINDOW_START
+#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT                                                             0x0
+#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT                                                             0x10
+#define FC_WINDOW_START__FC_WINDOW_START_X_MASK                                                               0x00001FFFL
+#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK                                                               0x1FFF0000L
+//FC_WINDOW_SIZE
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT                                                                0x0
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT                                                               0x10
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK                                                                  0x00000FFFL
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK                                                                 0x0FFF0000L
+//FC_SOURCE_SIZE
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT                                                                0x0
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT                                                               0x10
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK                                                                  0x00007FFFL
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK                                                                 0x7FFF0000L
+//DWB_UPDATE_CTRL
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT                                                               0x0
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT                                                            0x4
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK                                                                 0x00000001L
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK                                                              0x00000010L
+//DWB_CRC_CTRL
+#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT                                                                       0x0
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT                                                                  0x4
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT                                                                  0x8
+#define DWB_CRC_CTRL__DWB_CRC_EN_MASK                                                                         0x00000001L
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK                                                                    0x00000300L
+//DWB_CRC_MASK_R_G
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT                                                             0x0
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT                                                           0x10
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK                                                               0x0000FFFFL
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK                                                             0xFFFF0000L
+//DWB_CRC_MASK_B_A
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT                                                            0x0
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT                                                               0x10
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK                                                              0x0000FFFFL
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK                                                                 0xFFFF0000L
+//DWB_CRC_VAL_R_G
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT                                                               0x0
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT                                                             0x10
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK                                                                 0x0000FFFFL
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK                                                               0xFFFF0000L
+//DWB_CRC_VAL_B_A
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT                                                              0x0
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT                                                                 0x10
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK                                                                0x0000FFFFL
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK                                                                   0xFFFF0000L
+//DWB_OUT_CTRL
+#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT                                                                       0x0
+#define DWB_OUT_CTRL__OUT_DENORM__SHIFT                                                                       0x4
+#define DWB_OUT_CTRL__OUT_MAX__SHIFT                                                                          0x8
+#define DWB_OUT_CTRL__OUT_MIN__SHIFT                                                                          0x14
+#define DWB_OUT_CTRL__OUT_FORMAT_MASK                                                                         0x00000003L
+#define DWB_OUT_CTRL__OUT_DENORM_MASK                                                                         0x00000030L
+#define DWB_OUT_CTRL__OUT_MAX_MASK                                                                            0x0003FF00L
+#define DWB_OUT_CTRL__OUT_MIN_MASK                                                                            0x3FF00000L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT                             0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK                               0x00000001L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT                                   0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK                                     0x0000FFFFL
+//DWB_HOST_READ_CONTROL
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT                                              0x0
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK                                                0x000000FFL
+//DWB_OVERFLOW_STATUS
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT                                                    0x0
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT                                                     0x8
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT                                                    0xc
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT                                              0x10
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT                                                0x14
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK                                                      0x00000001L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK                                                       0x00000100L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK                                                      0x00001000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK                                                0x00010000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK                                                  0x00100000L
+//DWB_OVERFLOW_COUNTER
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT                                                   0x0
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT                                              0x4
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT                                              0x10
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK                                                     0x00000003L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK                                                0x0000FFF0L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK                                                0x0FFF0000L
+//DWB_SOFT_RESET
+#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT                                                                 0x0
+#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK                                                                   0x00000001L
+//DWB_DEBUG_CTRL
+#define DWB_DEBUG_CTRL__DWB_DEBUG_EN__SHIFT                                                                   0x0
+#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL__SHIFT                                                                  0x6
+#define DWB_DEBUG_CTRL__DWB_DEBUG_EN_MASK                                                                     0x00000001L
+#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL_MASK                                                                    0x000000C0L
+
+
+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON20_PERFCOUNTER_CNTL
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON20_PERFCOUNTER_CNTL2
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON20_PERFCOUNTER_STATE
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON20_PERFMON_CNTL
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON20_PERFMON_CNTL2
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON20_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON20_PERFMON_CVALUE_LOW
+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON20_PERFMON_HI
+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON20_PERFMON_LOW
+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
+//DWB_HDR_MULT_COEF
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT                                                           0x0
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK                                                             0x0007FFFFL
+//DWB_GAMUT_REMAP_MODE
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT                                                     0x0
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT                                             0x18
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK                                                       0x00000003L
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK                                               0x03000000L
+//DWB_GAMUT_REMAP_COEF_FORMAT
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT                                       0x0
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK                                         0x00000001L
+//DWB_GAMUT_REMAPA_C11_C12
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C13_C14
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C21_C22
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C23_C24
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C31_C32
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C33_C34
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C11_C12
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C13_C14
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C21_C22
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C23_C24
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C31_C32
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C33_C34
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK                                                   0xFFFF0000L
+//DWB_OGAM_CONTROL
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT                                                                0x0
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT                                                              0x4
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT                                                         0x8
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT                                                        0x18
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT                                                      0x1c
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK                                                                  0x00000003L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK                                                                0x00000010L
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK                                                           0x00000100L
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK                                                          0x03000000L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK                                                        0x10000000L
+//DWB_OGAM_LUT_INDEX
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT                                                         0x0
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK                                                           0x000001FFL
+//DWB_OGAM_LUT_DATA
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT                                                           0x0
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK                                                             0x0003FFFFL
+//DWB_OGAM_LUT_CONTROL
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                                            0x0
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT                                              0x4
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT                                                    0x8
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT                                                    0xc
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT                                                 0x10
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK                                              0x00000007L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK                                                0x00000030L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK                                                      0x00000100L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK                                                      0x00001000L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK                                                   0x00010000L
+//DWB_OGAM_RAMA_START_CNTL_B
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_G
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_R
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_BASE_CNTL_B
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_G
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_R
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL1_B
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_B
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_G
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_G
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_R
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_R
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_OFFSET_B
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_G
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_R
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_REGION_0_1
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_2_3
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_4_5
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_6_7
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_8_9
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_10_11
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_12_13
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_14_15
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_16_17
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_18_19
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_20_21
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_22_23
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_24_25
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_26_27
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_28_29
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_30_31
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_32_33
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_START_CNTL_B
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_G
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_R
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_BASE_CNTL_B
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_G
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_R
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL1_B
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_B
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_G
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_G
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_R
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_R
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_OFFSET_B
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_G
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_R
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_REGION_0_1
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_2_3
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_4_5
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_6_7
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_8_9
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_10_11
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_12_13
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_14_15
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_16_17
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_18_19
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_20_21
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_22_23
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_24_25
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_26_27
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_28_29
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_30_31
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_32_33
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+
+
+// addressBlock: dce_dc_dchvm_hvm_dispdec
+//DCHVM_CTRL0
+#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT                                                                   0x0
+#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK                                                                     0x00000001L
+//DCHVM_CTRL1
+#define DCHVM_CTRL1__DUMMY1__SHIFT                                                                            0x0
+#define DCHVM_CTRL1__DUMMY1_MASK                                                                              0xFFFFFFFFL
+//DCHVM_CLK_CTRL
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT                                                         0x0
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT                                                         0x1
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT                                                          0x4
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT                                                          0x5
+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT                                                          0x8
+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT                                                         0xa
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK                                                           0x00000001L
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK                                                           0x00000002L
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK                                                            0x00000010L
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK                                                            0x00000020L
+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK                                                            0x00000300L
+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK                                                           0x00000C00L
+//DCHVM_MEM_CTRL
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT                                                       0x0
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT                                                         0x2
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT                                                      0x4
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK                                                         0x00000001L
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK                                                           0x0000000CL
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK                                                        0x00000030L
+//DCHVM_RIOMMU_CTRL0
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT                                                        0x0
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT                                                         0x1
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK                                                          0x00000001L
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK                                                           0x00000002L
+//DCHVM_RIOMMU_STAT0
+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT                                                              0x0
+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT                                                       0x1
+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK                                                                0x00000001L
+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK                                                         0x00000002L
+//DCHVM_DEBUG_CTRL0
+#define DCHVM_DEBUG_CTRL0__DCHVM_DBG_EN__SHIFT                                                                0x0
+#define DCHVM_DEBUG_CTRL0__DCHVM_DCFCLK_DBG_DIRECT_OUT_SEL__SHIFT                                             0x4
+#define DCHVM_DEBUG_CTRL0__DCHVM_DBG_EN_MASK                                                                  0x00000001L
+#define DCHVM_DEBUG_CTRL0__DCHVM_DCFCLK_DBG_DIRECT_OUT_SEL_MASK                                               0x000000F0L
+//DCHVM_TEST_DEBUG_INDEX
+#define DCHVM_TEST_DEBUG_INDEX__DCHVM_TEST_DEBUG_INDEX__SHIFT                                                 0x0
+#define DCHVM_TEST_DEBUG_INDEX__DCHVM_TEST_DEBUG_INDEX_MASK                                                   0x000000FFL
+//DCHVM_TEST_DEBUG_DATA
+#define DCHVM_TEST_DEBUG_DATA__DCHVM_TEST_DEBUG_DATA__SHIFT                                                   0x0
+#define DCHVM_TEST_DEBUG_DATA__DCHVM_TEST_DEBUG_DATA_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+//MPCC0_MPCC_TOP_SEL
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_BOT_SEL
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_OPP_ID
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC0_MPCC_CONTROL
+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC0_MPCC_SM_CONTROL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC0_MPCC_UPDATE_LOCK_SEL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC0_MPCC_TOP_GAIN
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_INSIDE
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC0_MPCC_BG_R_CR
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_BG_G_Y
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC0_MPCC_BG_B_CB
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_MEM_PWR_CTRL
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC0_MPCC_STATUS
+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+//MPCC1_MPCC_TOP_SEL
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_BOT_SEL
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_OPP_ID
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC1_MPCC_CONTROL
+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC1_MPCC_SM_CONTROL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC1_MPCC_UPDATE_LOCK_SEL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC1_MPCC_TOP_GAIN
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_INSIDE
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC1_MPCC_BG_R_CR
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_BG_G_Y
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC1_MPCC_BG_B_CB
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_MEM_PWR_CTRL
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC1_MPCC_STATUS
+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc2_dispdec
+//MPCC2_MPCC_TOP_SEL
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_BOT_SEL
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_OPP_ID
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC2_MPCC_CONTROL
+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC2_MPCC_SM_CONTROL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC2_MPCC_UPDATE_LOCK_SEL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC2_MPCC_TOP_GAIN
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_INSIDE
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC2_MPCC_BG_R_CR
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_BG_G_Y
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC2_MPCC_BG_B_CB
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_MEM_PWR_CTRL
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC2_MPCC_STATUS
+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc3_dispdec
+//MPCC3_MPCC_TOP_SEL
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_BOT_SEL
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_OPP_ID
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC3_MPCC_CONTROL
+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC3_MPCC_SM_CONTROL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC3_MPCC_UPDATE_LOCK_SEL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC3_MPCC_TOP_GAIN
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_INSIDE
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC3_MPCC_BG_R_CR
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_BG_G_Y
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC3_MPCC_BG_B_CB
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_MEM_PWR_CTRL
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC3_MPCC_STATUS
+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+//MPCC_OGAM0_MPCC_OGAM_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+//MPCC_OGAM1_MPCC_OGAM_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
+//MPCC_OGAM2_MPCC_OGAM_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
+//MPCC_OGAM3_MPCC_OGAM_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+//MPC_CLOCK_CONTROL
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L
+//MPC_SOFT_RESET
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT                                                               0x2
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT                                                               0x3
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT                                                            0xc
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT                                                            0xd
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT                                                            0x16
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT                                                            0x17
+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK                                                                 0x00000004L
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK                                                                 0x00000008L
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK                                                              0x00001000L
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK                                                              0x00002000L
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK                                                              0x00400000L
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK                                                              0x00800000L
+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L
+//MPC_CRC_CTRL
+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f
+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L
+//MPC_CRC_SEL_CONTROL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT                                                           0x8
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK                                                             0x00000300L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L
+//MPC_CRC_RESULT_AR
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_GB
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_C
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT                                                             0x0
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK                                                               0x0000FFFFL
+//MPC_PERFMON_EVENT_CTRL
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT                                                   0x0
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK                                                     0x00000001L
+//MPC_BYPASS_BG_AR
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L
+//MPC_BYPASS_BG_GB
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L
+//MPC_HOST_READ_CONTROL
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL
+//MPC_DPP_PENDING_STATUS
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                         0x0
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                          0x1
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                          0x2
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                         0x4
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                          0x5
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                          0x6
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT                                         0x8
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT                                          0x9
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT                                          0xa
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT                                         0xc
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT                                          0xd
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT                                          0xe
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                           0x00000001L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                            0x00000002L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                            0x00000004L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                           0x00000010L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                            0x00000020L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                            0x00000040L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK                                           0x00000100L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK                                            0x00000200L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK                                            0x00000400L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK                                           0x00001000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK                                            0x00002000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK                                            0x00004000L
+//MPC_PENDING_STATUS_MISC
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                        0x0
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                        0x1
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT                                        0x2
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT                                        0x3
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                           0x8
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                           0x9
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT                                           0xa
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT                                           0xb
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT                                         0x10
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                          0x00000001L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                          0x00000002L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK                                          0x00000004L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK                                          0x00000008L
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK                                             0x00000100L
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK                                             0x00000200L
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK                                             0x00000400L
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK                                             0x00000800L
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK                                           0x00010000L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET1
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET1
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET1
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET1
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET1
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET2
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET2
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET2
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET2
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET2
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET3
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET3
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET3
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET3
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET3
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//MPC_DWB0_MUX
+#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT                                                                     0x0
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT                                                              0x4
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK                                                                       0x0000000FL
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK                                                                0x000000F0L
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+//MPC_OUT0_MUX
+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT0_DENORM_CONTROL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT0_DENORM_CLAMP_G_Y
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT0_DENORM_CLAMP_B_CB
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT1_MUX
+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT1_DENORM_CONTROL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT1_DENORM_CLAMP_G_Y
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT1_DENORM_CLAMP_B_CB
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT2_MUX
+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT2_DENORM_CONTROL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT2_DENORM_CLAMP_G_Y
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT2_DENORM_CLAMP_B_CB
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT3_MUX
+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT3_DENORM_CONTROL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT3_DENORM_CLAMP_G_Y
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT3_DENORM_CLAMP_B_CB
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT_CSC_COEF_FORMAT
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT                                                 0x2
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT                                                 0x3
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK                                                   0x00000004L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK                                                   0x00000008L
+//MPC_OUT0_CSC_MODE
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT0_CSC_C11_C12_A
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_A
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_A
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_A
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_A
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_A
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C11_C12_B
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_B
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_B
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_B
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_B
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_B
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_MODE
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT1_CSC_C11_C12_A
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_A
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_A
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_A
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_A
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_A
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C11_C12_B
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_B
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_B
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_B
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_B
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_B
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_MODE
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT2_CSC_C11_C12_A
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_A
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_A
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_A
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_A
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_A
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C11_C12_B
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_B
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_B
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_B
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_B
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_B
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_MODE
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT3_CSC_C11_C12_A
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_A
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_A
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_A
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_A
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_A
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C11_C12_B
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_B
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_B
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_B
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_B
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_B
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpc_rmu_dispdec
+//MPC_RMU_CONTROL
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX__SHIFT                                                                  0x0
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS__SHIFT                                                           0x4
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX__SHIFT                                                                  0x8
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX_STATUS__SHIFT                                                           0xc
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_MASK                                                                    0x0000000FL
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS_MASK                                                             0x000000F0L
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX_MASK                                                                    0x00000F00L
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX_STATUS_MASK                                                             0x0000F000L
+//MPC_RMU_MEM_PWR_CTRL
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE__SHIFT                                                   0x0
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS__SHIFT                                                     0x2
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE__SHIFT                                            0x4
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE__SHIFT                                             0x6
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE__SHIFT                                                0x8
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_FORCE__SHIFT                                                   0xa
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_DIS__SHIFT                                                     0xc
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_SHAPER_MEM_PWR_STATE__SHIFT                                            0xe
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_3DLUT_MEM_PWR_STATE__SHIFT                                             0x10
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_LOW_PWR_MODE__SHIFT                                                0x12
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE_MASK                                                     0x00000003L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS_MASK                                                       0x00000004L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE_MASK                                              0x00000030L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE_MASK                                               0x000000C0L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE_MASK                                                  0x00000300L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_FORCE_MASK                                                     0x00000C00L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_DIS_MASK                                                       0x00001000L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_SHAPER_MEM_PWR_STATE_MASK                                              0x0000C000L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_3DLUT_MEM_PWR_STATE_MASK                                               0x00030000L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_LOW_PWR_MODE_MASK                                                  0x000C0000L
+//MPC_RMU0_SHAPER_CONTROL
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE__SHIFT                                               0x0
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT__SHIFT                                           0x8
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE_MASK                                                 0x00000003L
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT_MASK                                             0x00000300L
+//MPC_RMU0_SHAPER_OFFSET_R
+#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_OFFSET_G
+#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_OFFSET_B
+#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_SCALE_R
+#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R__SHIFT                                                0x0
+#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R_MASK                                                  0x0000FFFFL
+//MPC_RMU0_SHAPER_SCALE_G_B
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B__SHIFT                                              0x10
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G_MASK                                                0x0000FFFFL
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B_MASK                                                0xFFFF0000L
+//MPC_RMU0_SHAPER_LUT_INDEX
+#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX__SHIFT                                            0x0
+#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX_MASK                                              0x000000FFL
+//MPC_RMU0_SHAPER_LUT_DATA
+#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA_MASK                                                0x00FFFFFFL
+//MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK__SHIFT                            0x0
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL__SHIFT                                0x4
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK_MASK                              0x00000007L
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL_MASK                                  0x00000010L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_B
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_G
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_R
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_B
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_G
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_R
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_REGION_0_1
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_2_3
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_4_5
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_6_7
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_8_9
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_10_11
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_12_13
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_14_15
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_16_17
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_18_19
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_20_21
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_22_23
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_24_25
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_26_27
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_28_29
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_30_31
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_32_33
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_B
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_G
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_R
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_B
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_G
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_R
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_REGION_0_1
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_2_3
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_4_5
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_6_7
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_8_9
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_10_11
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_12_13
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_14_15
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_16_17
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_18_19
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_20_21
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_22_23
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_24_25
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_26_27
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_28_29
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_30_31
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_32_33
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_3DLUT_MODE
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE__SHIFT                                                        0x0
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE__SHIFT                                                        0x4
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT__SHIFT                                                0x8
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_MASK                                                          0x00000003L
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE_MASK                                                          0x00000010L
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT_MASK                                                  0x00000300L
+//MPC_RMU0_3DLUT_INDEX
+#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX__SHIFT                                                      0x0
+#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX_MASK                                                        0x000007FFL
+//MPC_RMU0_3DLUT_DATA
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0__SHIFT                                                       0x0
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1__SHIFT                                                       0x10
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0_MASK                                                         0x0000FFFFL
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1_MASK                                                         0xFFFF0000L
+//MPC_RMU0_3DLUT_DATA_30BIT
+#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT__SHIFT                                            0x2
+#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT_MASK                                              0xFFFFFFFCL
+//MPC_RMU0_3DLUT_READ_WRITE_CONTROL
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK__SHIFT                                 0x0
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL__SHIFT                                       0x4
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN__SHIFT                                      0x8
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL__SHIFT                                      0x10
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK_MASK                                   0x0000000FL
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL_MASK                                         0x00000010L
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN_MASK                                        0x00000100L
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL_MASK                                        0x00030000L
+//MPC_RMU0_3DLUT_OUT_NORM_FACTOR
+#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR__SHIFT                                  0x0
+#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR_MASK                                    0x0000FFFFL
+//MPC_RMU0_3DLUT_OUT_OFFSET_R
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R_MASK                                           0xFFFF0000L
+//MPC_RMU0_3DLUT_OUT_OFFSET_G
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G_MASK                                           0xFFFF0000L
+//MPC_RMU0_3DLUT_OUT_OFFSET_B
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B_MASK                                           0xFFFF0000L
+//MPC_RMU1_SHAPER_CONTROL
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE__SHIFT                                               0x0
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT__SHIFT                                           0x8
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE_MASK                                                 0x00000003L
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT_MASK                                             0x00000300L
+//MPC_RMU1_SHAPER_OFFSET_R
+#define MPC_RMU1_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R_MASK                                                0x0007FFFFL
+//MPC_RMU1_SHAPER_OFFSET_G
+#define MPC_RMU1_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G_MASK                                                0x0007FFFFL
+//MPC_RMU1_SHAPER_OFFSET_B
+#define MPC_RMU1_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B_MASK                                                0x0007FFFFL
+//MPC_RMU1_SHAPER_SCALE_R
+#define MPC_RMU1_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R__SHIFT                                                0x0
+#define MPC_RMU1_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R_MASK                                                  0x0000FFFFL
+//MPC_RMU1_SHAPER_SCALE_G_B
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B__SHIFT                                              0x10
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G_MASK                                                0x0000FFFFL
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B_MASK                                                0xFFFF0000L
+//MPC_RMU1_SHAPER_LUT_INDEX
+#define MPC_RMU1_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX__SHIFT                                            0x0
+#define MPC_RMU1_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX_MASK                                              0x000000FFL
+//MPC_RMU1_SHAPER_LUT_DATA
+#define MPC_RMU1_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA_MASK                                                0x00FFFFFFL
+//MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK__SHIFT                            0x0
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL__SHIFT                                0x4
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK_MASK                              0x00000007L
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL_MASK                                  0x00000010L
+//MPC_RMU1_SHAPER_RAMA_START_CNTL_B
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMA_START_CNTL_G
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMA_START_CNTL_R
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMA_END_CNTL_B
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMA_END_CNTL_G
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMA_END_CNTL_R
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMA_REGION_0_1
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_2_3
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_4_5
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_6_7
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_8_9
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_10_11
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_12_13
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_14_15
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_16_17
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_18_19
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_20_21
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_22_23
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_24_25
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_26_27
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_28_29
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_30_31
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_32_33
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_START_CNTL_B
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMB_START_CNTL_G
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMB_START_CNTL_R
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMB_END_CNTL_B
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMB_END_CNTL_G
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMB_END_CNTL_R
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMB_REGION_0_1
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_2_3
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_4_5
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_6_7
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_8_9
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_10_11
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_12_13
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_14_15
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_16_17
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_18_19
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_20_21
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_22_23
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_24_25
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_26_27
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_28_29
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_30_31
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_32_33
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_3DLUT_MODE
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE__SHIFT                                                        0x0
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_SIZE__SHIFT                                                        0x4
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT__SHIFT                                                0x8
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_MASK                                                          0x00000003L
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_SIZE_MASK                                                          0x00000010L
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT_MASK                                                  0x00000300L
+//MPC_RMU1_3DLUT_INDEX
+#define MPC_RMU1_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX__SHIFT                                                      0x0
+#define MPC_RMU1_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX_MASK                                                        0x000007FFL
+//MPC_RMU1_3DLUT_DATA
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA0__SHIFT                                                       0x0
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA1__SHIFT                                                       0x10
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA0_MASK                                                         0x0000FFFFL
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA1_MASK                                                         0xFFFF0000L
+//MPC_RMU1_3DLUT_DATA_30BIT
+#define MPC_RMU1_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT__SHIFT                                            0x2
+#define MPC_RMU1_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT_MASK                                              0xFFFFFFFCL
+//MPC_RMU1_3DLUT_READ_WRITE_CONTROL
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK__SHIFT                                 0x0
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL__SHIFT                                       0x4
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN__SHIFT                                      0x8
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL__SHIFT                                      0x10
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK_MASK                                   0x0000000FL
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL_MASK                                         0x00000010L
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN_MASK                                        0x00000100L
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL_MASK                                        0x00030000L
+//MPC_RMU1_3DLUT_OUT_NORM_FACTOR
+#define MPC_RMU1_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR__SHIFT                                  0x0
+#define MPC_RMU1_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR_MASK                                    0x0000FFFFL
+//MPC_RMU1_3DLUT_OUT_OFFSET_R
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R__SHIFT                                        0x0
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R__SHIFT                                         0x10
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R_MASK                                          0x0000FFFFL
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R_MASK                                           0xFFFF0000L
+//MPC_RMU1_3DLUT_OUT_OFFSET_G
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G__SHIFT                                        0x0
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G__SHIFT                                         0x10
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G_MASK                                          0x0000FFFFL
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G_MASK                                           0xFFFF0000L
+//MPC_RMU1_3DLUT_OUT_OFFSET_B
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B__SHIFT                                        0x0
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B__SHIFT                                         0x10
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B_MASK                                          0x0000FFFFL
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B_MASK                                           0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON21_PERFCOUNTER_CNTL
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON21_PERFCOUNTER_CNTL2
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON21_PERFCOUNTER_STATE
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON21_PERFMON_CNTL
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON21_PERFMON_CNTL2
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON21_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON21_PERFMON_CVALUE_LOW
+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON21_PERFMON_HI
+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON21_PERFMON_LOW
+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM0_BL1_PWM_USER_LEVEL
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM0_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM0_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM0_BL1_PWM_ABM_CNTL
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM0_BL1_PWM_GRP2_REG_LOCK
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM0_DC_ABM1_CNTL
+#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM0_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM0_DC_ABM1_HG_MISC_CTRL
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM0_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM0_DC_ABM1_LS_PIXEL_COUNT
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_HG_SAMPLE_RATE
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_LS_SAMPLE_RATE
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_1
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_2
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_3
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_4
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_5
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_6
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_7
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_8
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_9
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_10
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_11
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_12
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_13
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_14
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_15
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_16
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_17
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_18
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_19
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_20
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_21
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_22
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_23
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_24
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_BL_MASTER_LOCK
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm1_dispdec
+//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM1_BL1_PWM_USER_LEVEL
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM1_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM1_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM1_BL1_PWM_ABM_CNTL
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM1_BL1_PWM_GRP2_REG_LOCK
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM1_DC_ABM1_CNTL
+#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM1_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM1_DC_ABM1_HG_MISC_CTRL
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM1_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM1_DC_ABM1_LS_PIXEL_COUNT
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_HG_SAMPLE_RATE
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_LS_SAMPLE_RATE
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_1
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_2
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_3
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_4
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_5
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_6
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_7
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_8
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_9
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_10
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_11
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_12
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_13
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_14
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_15
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_16
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_17
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_18
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_19
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_20
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_21
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_22
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_23
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_24
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_BL_MASTER_LOCK
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm2_dispdec
+//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM2_BL1_PWM_USER_LEVEL
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM2_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM2_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM2_BL1_PWM_ABM_CNTL
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM2_BL1_PWM_GRP2_REG_LOCK
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM2_DC_ABM1_CNTL
+#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM2_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM2_DC_ABM1_HG_MISC_CTRL
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM2_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM2_DC_ABM1_LS_PIXEL_COUNT
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_HG_SAMPLE_RATE
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_LS_SAMPLE_RATE
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_1
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_2
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_3
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_4
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_5
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_6
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_7
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_8
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_9
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_10
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_11
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_12
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_13
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_14
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_15
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_16
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_17
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_18
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_19
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_20
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_21
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_22
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_23
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_24
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_BL_MASTER_LOCK
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm3_dispdec
+//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM3_BL1_PWM_USER_LEVEL
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM3_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM3_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM3_BL1_PWM_ABM_CNTL
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM3_BL1_PWM_GRP2_REG_LOCK
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM3_DC_ABM1_CNTL
+#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM3_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM3_DC_ABM1_HG_MISC_CTRL
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM3_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM3_DC_ABM1_LS_PIXEL_COUNT
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_HG_SAMPLE_RATE
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_LS_SAMPLE_RATE
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_1
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_2
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_3
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_4
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_5
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_6
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_7
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_8
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_9
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_10
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_11
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_12
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_13
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_14
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_15
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_16
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_17
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_18
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_19
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_20
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_21
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_22
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_23
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_24
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_BL_MASTER_LOCK
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: vga_vgaseqind
+//SEQ00
+#define SEQ00__SEQ_RST0B__SHIFT                                                                               0x0
+#define SEQ00__SEQ_RST1B__SHIFT                                                                               0x1
+#define SEQ00__SEQ_RST0B_MASK                                                                                 0x01L
+#define SEQ00__SEQ_RST1B_MASK                                                                                 0x02L
+//SEQ01
+#define SEQ01__SEQ_DOT8__SHIFT                                                                                0x0
+#define SEQ01__SEQ_SHIFT2__SHIFT                                                                              0x2
+#define SEQ01__SEQ_PCLKBY2__SHIFT                                                                             0x3
+#define SEQ01__SEQ_SHIFT4__SHIFT                                                                              0x4
+#define SEQ01__SEQ_MAXBW__SHIFT                                                                               0x5
+#define SEQ01__SEQ_DOT8_MASK                                                                                  0x01L
+#define SEQ01__SEQ_SHIFT2_MASK                                                                                0x04L
+#define SEQ01__SEQ_PCLKBY2_MASK                                                                               0x08L
+#define SEQ01__SEQ_SHIFT4_MASK                                                                                0x10L
+#define SEQ01__SEQ_MAXBW_MASK                                                                                 0x20L
+//SEQ02
+#define SEQ02__SEQ_MAP0_EN__SHIFT                                                                             0x0
+#define SEQ02__SEQ_MAP1_EN__SHIFT                                                                             0x1
+#define SEQ02__SEQ_MAP2_EN__SHIFT                                                                             0x2
+#define SEQ02__SEQ_MAP3_EN__SHIFT                                                                             0x3
+#define SEQ02__SEQ_MAP0_EN_MASK                                                                               0x01L
+#define SEQ02__SEQ_MAP1_EN_MASK                                                                               0x02L
+#define SEQ02__SEQ_MAP2_EN_MASK                                                                               0x04L
+#define SEQ02__SEQ_MAP3_EN_MASK                                                                               0x08L
+//SEQ03
+#define SEQ03__SEQ_FONT_B1__SHIFT                                                                             0x0
+#define SEQ03__SEQ_FONT_B2__SHIFT                                                                             0x1
+#define SEQ03__SEQ_FONT_A1__SHIFT                                                                             0x2
+#define SEQ03__SEQ_FONT_A2__SHIFT                                                                             0x3
+#define SEQ03__SEQ_FONT_B0__SHIFT                                                                             0x4
+#define SEQ03__SEQ_FONT_A0__SHIFT                                                                             0x5
+#define SEQ03__SEQ_FONT_B1_MASK                                                                               0x01L
+#define SEQ03__SEQ_FONT_B2_MASK                                                                               0x02L
+#define SEQ03__SEQ_FONT_A1_MASK                                                                               0x04L
+#define SEQ03__SEQ_FONT_A2_MASK                                                                               0x08L
+#define SEQ03__SEQ_FONT_B0_MASK                                                                               0x10L
+#define SEQ03__SEQ_FONT_A0_MASK                                                                               0x20L
+//SEQ04
+#define SEQ04__SEQ_256K__SHIFT                                                                                0x1
+#define SEQ04__SEQ_ODDEVEN__SHIFT                                                                             0x2
+#define SEQ04__SEQ_CHAIN__SHIFT                                                                               0x3
+#define SEQ04__SEQ_256K_MASK                                                                                  0x02L
+#define SEQ04__SEQ_ODDEVEN_MASK                                                                               0x04L
+#define SEQ04__SEQ_CHAIN_MASK                                                                                 0x08L
+
+
+// addressBlock: vga_vgacrtind
+//CRT00
+#define CRT00__H_TOTAL__SHIFT                                                                                 0x0
+#define CRT00__H_TOTAL_MASK                                                                                   0xFFL
+//CRT01
+#define CRT01__H_DISP_END__SHIFT                                                                              0x0
+#define CRT01__H_DISP_END_MASK                                                                                0xFFL
+//CRT02
+#define CRT02__H_BLANK_START__SHIFT                                                                           0x0
+#define CRT02__H_BLANK_START_MASK                                                                             0xFFL
+//CRT03
+#define CRT03__H_BLANK_END__SHIFT                                                                             0x0
+#define CRT03__H_DE_SKEW__SHIFT                                                                               0x5
+#define CRT03__CR10CR11_R_DIS_B__SHIFT                                                                        0x7
+#define CRT03__H_BLANK_END_MASK                                                                               0x1FL
+#define CRT03__H_DE_SKEW_MASK                                                                                 0x60L
+#define CRT03__CR10CR11_R_DIS_B_MASK                                                                          0x80L
+//CRT04
+#define CRT04__H_SYNC_START__SHIFT                                                                            0x0
+#define CRT04__H_SYNC_START_MASK                                                                              0xFFL
+//CRT05
+#define CRT05__H_SYNC_END__SHIFT                                                                              0x0
+#define CRT05__H_SYNC_SKEW__SHIFT                                                                             0x5
+#define CRT05__H_BLANK_END_B5__SHIFT                                                                          0x7
+#define CRT05__H_SYNC_END_MASK                                                                                0x1FL
+#define CRT05__H_SYNC_SKEW_MASK                                                                               0x60L
+#define CRT05__H_BLANK_END_B5_MASK                                                                            0x80L
+//CRT06
+#define CRT06__V_TOTAL__SHIFT                                                                                 0x0
+#define CRT06__V_TOTAL_MASK                                                                                   0xFFL
+//CRT07
+#define CRT07__V_TOTAL_B8__SHIFT                                                                              0x0
+#define CRT07__V_DISP_END_B8__SHIFT                                                                           0x1
+#define CRT07__V_SYNC_START_B8__SHIFT                                                                         0x2
+#define CRT07__V_BLANK_START_B8__SHIFT                                                                        0x3
+#define CRT07__LINE_CMP_B8__SHIFT                                                                             0x4
+#define CRT07__V_TOTAL_B9__SHIFT                                                                              0x5
+#define CRT07__V_DISP_END_B9__SHIFT                                                                           0x6
+#define CRT07__V_SYNC_START_B9__SHIFT                                                                         0x7
+#define CRT07__V_TOTAL_B8_MASK                                                                                0x01L
+#define CRT07__V_DISP_END_B8_MASK                                                                             0x02L
+#define CRT07__V_SYNC_START_B8_MASK                                                                           0x04L
+#define CRT07__V_BLANK_START_B8_MASK                                                                          0x08L
+#define CRT07__LINE_CMP_B8_MASK                                                                               0x10L
+#define CRT07__V_TOTAL_B9_MASK                                                                                0x20L
+#define CRT07__V_DISP_END_B9_MASK                                                                             0x40L
+#define CRT07__V_SYNC_START_B9_MASK                                                                           0x80L
+//CRT08
+#define CRT08__ROW_SCAN_START__SHIFT                                                                          0x0
+#define CRT08__BYTE_PAN__SHIFT                                                                                0x5
+#define CRT08__ROW_SCAN_START_MASK                                                                            0x1FL
+#define CRT08__BYTE_PAN_MASK                                                                                  0x60L
+//CRT09
+#define CRT09__MAX_ROW_SCAN__SHIFT                                                                            0x0
+#define CRT09__V_BLANK_START_B9__SHIFT                                                                        0x5
+#define CRT09__LINE_CMP_B9__SHIFT                                                                             0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT                                                                      0x7
+#define CRT09__MAX_ROW_SCAN_MASK                                                                              0x1FL
+#define CRT09__V_BLANK_START_B9_MASK                                                                          0x20L
+#define CRT09__LINE_CMP_B9_MASK                                                                               0x40L
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK                                                                        0x80L
+//CRT0A
+#define CRT0A__CURSOR_START__SHIFT                                                                            0x0
+#define CRT0A__CURSOR_DISABLE__SHIFT                                                                          0x5
+#define CRT0A__CURSOR_START_MASK                                                                              0x1FL
+#define CRT0A__CURSOR_DISABLE_MASK                                                                            0x20L
+//CRT0B
+#define CRT0B__CURSOR_END__SHIFT                                                                              0x0
+#define CRT0B__CURSOR_SKEW__SHIFT                                                                             0x5
+#define CRT0B__CURSOR_END_MASK                                                                                0x1FL
+#define CRT0B__CURSOR_SKEW_MASK                                                                               0x60L
+//CRT0C
+#define CRT0C__DISP_START__SHIFT                                                                              0x0
+#define CRT0C__DISP_START_MASK                                                                                0xFFL
+//CRT0D
+#define CRT0D__DISP_START__SHIFT                                                                              0x0
+#define CRT0D__DISP_START_MASK                                                                                0xFFL
+//CRT0E
+#define CRT0E__CURSOR_LOC_HI__SHIFT                                                                           0x0
+#define CRT0E__CURSOR_LOC_HI_MASK                                                                             0xFFL
+//CRT0F
+#define CRT0F__CURSOR_LOC_LO__SHIFT                                                                           0x0
+#define CRT0F__CURSOR_LOC_LO_MASK                                                                             0xFFL
+//CRT10
+#define CRT10__V_SYNC_START__SHIFT                                                                            0x0
+#define CRT10__V_SYNC_START_MASK                                                                              0xFFL
+//CRT11
+#define CRT11__V_SYNC_END__SHIFT                                                                              0x0
+#define CRT11__V_INTR_CLR__SHIFT                                                                              0x4
+#define CRT11__V_INTR_EN__SHIFT                                                                               0x5
+#define CRT11__SEL5_REFRESH_CYC__SHIFT                                                                        0x6
+#define CRT11__C0T7_WR_ONLY__SHIFT                                                                            0x7
+#define CRT11__V_SYNC_END_MASK                                                                                0x0FL
+#define CRT11__V_INTR_CLR_MASK                                                                                0x10L
+#define CRT11__V_INTR_EN_MASK                                                                                 0x20L
+#define CRT11__SEL5_REFRESH_CYC_MASK                                                                          0x40L
+#define CRT11__C0T7_WR_ONLY_MASK                                                                              0x80L
+//CRT12
+#define CRT12__V_DISP_END__SHIFT                                                                              0x0
+#define CRT12__V_DISP_END_MASK                                                                                0xFFL
+//CRT13
+#define CRT13__DISP_PITCH__SHIFT                                                                              0x0
+#define CRT13__DISP_PITCH_MASK                                                                                0xFFL
+//CRT14
+#define CRT14__UNDRLN_LOC__SHIFT                                                                              0x0
+#define CRT14__ADDR_CNT_BY4__SHIFT                                                                            0x5
+#define CRT14__DOUBLE_WORD__SHIFT                                                                             0x6
+#define CRT14__UNDRLN_LOC_MASK                                                                                0x1FL
+#define CRT14__ADDR_CNT_BY4_MASK                                                                              0x20L
+#define CRT14__DOUBLE_WORD_MASK                                                                               0x40L
+//CRT15
+#define CRT15__V_BLANK_START__SHIFT                                                                           0x0
+#define CRT15__V_BLANK_START_MASK                                                                             0xFFL
+//CRT16
+#define CRT16__V_BLANK_END__SHIFT                                                                             0x0
+#define CRT16__V_BLANK_END_MASK                                                                               0xFFL
+//CRT17
+#define CRT17__RA0_AS_A13B__SHIFT                                                                             0x0
+#define CRT17__RA1_AS_A14B__SHIFT                                                                             0x1
+#define CRT17__VCOUNT_BY2__SHIFT                                                                              0x2
+#define CRT17__ADDR_CNT_BY2__SHIFT                                                                            0x3
+#define CRT17__WRAP_A15TOA0__SHIFT                                                                            0x5
+#define CRT17__BYTE_MODE__SHIFT                                                                               0x6
+#define CRT17__CRTC_SYNC_EN__SHIFT                                                                            0x7
+#define CRT17__RA0_AS_A13B_MASK                                                                               0x01L
+#define CRT17__RA1_AS_A14B_MASK                                                                               0x02L
+#define CRT17__VCOUNT_BY2_MASK                                                                                0x04L
+#define CRT17__ADDR_CNT_BY2_MASK                                                                              0x08L
+#define CRT17__WRAP_A15TOA0_MASK                                                                              0x20L
+#define CRT17__BYTE_MODE_MASK                                                                                 0x40L
+#define CRT17__CRTC_SYNC_EN_MASK                                                                              0x80L
+//CRT18
+#define CRT18__LINE_CMP__SHIFT                                                                                0x0
+#define CRT18__LINE_CMP_MASK                                                                                  0xFFL
+//CRT1E
+#define CRT1E__GRPH_DEC_RD1__SHIFT                                                                            0x1
+#define CRT1E__GRPH_DEC_RD1_MASK                                                                              0x02L
+//CRT1F
+#define CRT1F__GRPH_DEC_RD0__SHIFT                                                                            0x0
+#define CRT1F__GRPH_DEC_RD0_MASK                                                                              0xFFL
+//CRT22
+#define CRT22__GRPH_LATCH_DATA__SHIFT                                                                         0x0
+#define CRT22__GRPH_LATCH_DATA_MASK                                                                           0xFFL
+
+
+// addressBlock: vga_vgagrphind
+//GRA00
+#define GRA00__GRPH_SET_RESET0__SHIFT                                                                         0x0
+#define GRA00__GRPH_SET_RESET1__SHIFT                                                                         0x1
+#define GRA00__GRPH_SET_RESET2__SHIFT                                                                         0x2
+#define GRA00__GRPH_SET_RESET3__SHIFT                                                                         0x3
+#define GRA00__GRPH_SET_RESET0_MASK                                                                           0x01L
+#define GRA00__GRPH_SET_RESET1_MASK                                                                           0x02L
+#define GRA00__GRPH_SET_RESET2_MASK                                                                           0x04L
+#define GRA00__GRPH_SET_RESET3_MASK                                                                           0x08L
+//GRA01
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT                                                                     0x0
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT                                                                     0x1
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT                                                                     0x2
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT                                                                     0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK                                                                       0x01L
+#define GRA01__GRPH_SET_RESET_ENA1_MASK                                                                       0x02L
+#define GRA01__GRPH_SET_RESET_ENA2_MASK                                                                       0x04L
+#define GRA01__GRPH_SET_RESET_ENA3_MASK                                                                       0x08L
+//GRA02
+#define GRA02__GRPH_CCOMP__SHIFT                                                                              0x0
+#define GRA02__GRPH_CCOMP_MASK                                                                                0x0FL
+//GRA03
+#define GRA03__GRPH_ROTATE__SHIFT                                                                             0x0
+#define GRA03__GRPH_FN_SEL__SHIFT                                                                             0x3
+#define GRA03__GRPH_ROTATE_MASK                                                                               0x07L
+#define GRA03__GRPH_FN_SEL_MASK                                                                               0x18L
+//GRA04
+#define GRA04__GRPH_RMAP__SHIFT                                                                               0x0
+#define GRA04__GRPH_RMAP_MASK                                                                                 0x03L
+//GRA05
+#define GRA05__GRPH_WRITE_MODE__SHIFT                                                                         0x0
+#define GRA05__GRPH_READ1__SHIFT                                                                              0x3
+#define GRA05__CGA_ODDEVEN__SHIFT                                                                             0x4
+#define GRA05__GRPH_OES__SHIFT                                                                                0x5
+#define GRA05__GRPH_PACK__SHIFT                                                                               0x6
+#define GRA05__GRPH_WRITE_MODE_MASK                                                                           0x03L
+#define GRA05__GRPH_READ1_MASK                                                                                0x08L
+#define GRA05__CGA_ODDEVEN_MASK                                                                               0x10L
+#define GRA05__GRPH_OES_MASK                                                                                  0x20L
+#define GRA05__GRPH_PACK_MASK                                                                                 0x40L
+//GRA06
+#define GRA06__GRPH_GRAPHICS__SHIFT                                                                           0x0
+#define GRA06__GRPH_ODDEVEN__SHIFT                                                                            0x1
+#define GRA06__GRPH_ADRSEL__SHIFT                                                                             0x2
+#define GRA06__GRPH_GRAPHICS_MASK                                                                             0x01L
+#define GRA06__GRPH_ODDEVEN_MASK                                                                              0x02L
+#define GRA06__GRPH_ADRSEL_MASK                                                                               0x0CL
+//GRA07
+#define GRA07__GRPH_XCARE0__SHIFT                                                                             0x0
+#define GRA07__GRPH_XCARE1__SHIFT                                                                             0x1
+#define GRA07__GRPH_XCARE2__SHIFT                                                                             0x2
+#define GRA07__GRPH_XCARE3__SHIFT                                                                             0x3
+#define GRA07__GRPH_XCARE0_MASK                                                                               0x01L
+#define GRA07__GRPH_XCARE1_MASK                                                                               0x02L
+#define GRA07__GRPH_XCARE2_MASK                                                                               0x04L
+#define GRA07__GRPH_XCARE3_MASK                                                                               0x08L
+//GRA08
+#define GRA08__GRPH_BMSK__SHIFT                                                                               0x0
+#define GRA08__GRPH_BMSK_MASK                                                                                 0xFFL
+
+
+// addressBlock: vga_vgaattrind
+//ATTR00
+#define ATTR00__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR00__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR01
+#define ATTR01__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR01__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR02
+#define ATTR02__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR02__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR03
+#define ATTR03__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR03__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR04
+#define ATTR04__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR04__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR05
+#define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR05__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR06
+#define ATTR06__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR06__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR07
+#define ATTR07__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR07__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR08
+#define ATTR08__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR08__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR09
+#define ATTR09__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR09__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0A
+#define ATTR0A__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0A__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0B
+#define ATTR0B__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0B__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0C
+#define ATTR0C__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0C__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0D
+#define ATTR0D__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0D__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0E
+#define ATTR0E__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0E__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0F
+#define ATTR0F__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0F__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR10
+#define ATTR10__ATTR_GRPH_MODE__SHIFT                                                                         0x0
+#define ATTR10__ATTR_MONO_EN__SHIFT                                                                           0x1
+#define ATTR10__ATTR_LGRPH_EN__SHIFT                                                                          0x2
+#define ATTR10__ATTR_BLINK_EN__SHIFT                                                                          0x3
+#define ATTR10__ATTR_PANTOPONLY__SHIFT                                                                        0x5
+#define ATTR10__ATTR_PCLKBY2__SHIFT                                                                           0x6
+#define ATTR10__ATTR_CSEL_EN__SHIFT                                                                           0x7
+#define ATTR10__ATTR_GRPH_MODE_MASK                                                                           0x01L
+#define ATTR10__ATTR_MONO_EN_MASK                                                                             0x02L
+#define ATTR10__ATTR_LGRPH_EN_MASK                                                                            0x04L
+#define ATTR10__ATTR_BLINK_EN_MASK                                                                            0x08L
+#define ATTR10__ATTR_PANTOPONLY_MASK                                                                          0x20L
+#define ATTR10__ATTR_PCLKBY2_MASK                                                                             0x40L
+#define ATTR10__ATTR_CSEL_EN_MASK                                                                             0x80L
+//ATTR11
+#define ATTR11__ATTR_OVSC__SHIFT                                                                              0x0
+#define ATTR11__ATTR_OVSC_MASK                                                                                0xFFL
+//ATTR12
+#define ATTR12__ATTR_MAP_EN__SHIFT                                                                            0x0
+#define ATTR12__ATTR_MAP_EN_MASK                                                                              0x0FL
+//ATTR13
+#define ATTR13__ATTR_PPAN__SHIFT                                                                              0x0
+#define ATTR13__ATTR_PPAN_MASK                                                                                0x0FL
+//ATTR14
+#define ATTR14__ATTR_CSEL1__SHIFT                                                                             0x0
+#define ATTR14__ATTR_CSEL2__SHIFT                                                                             0x2
+#define ATTR14__ATTR_CSEL1_MASK                                                                               0x03L
+#define ATTR14__ATTR_CSEL2_MASK                                                                               0x0CL
+
+
+// addressBlock: azendpoint_f2codecind
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL
+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT            0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT              0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT             0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK              0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK                0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK               0x00000070L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L
+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L
+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L
+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L
+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L
+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L
+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azendpoint_descriptorind
+//AUDIO_DESCRIPTOR0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR1
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR2
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR3
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR4
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR5
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR6
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR8
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR9
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR10
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR11
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR12
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR13
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+
+
+// addressBlock: azendpoint_sinkinfoind
+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL
+//SINK_DESCRIPTION0
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION1
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION2
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION3
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION4
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION5
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION6
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION7
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION8
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION9
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION10
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION11
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION12
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION13
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION14
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION15
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION16
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION17
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+//AZALIA_INPUT_CRC0_CHANNEL0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL1
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL2
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL3
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL4
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL5
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL6
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL7
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+//AZALIA_INPUT_CRC1_CHANNEL0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL1
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL2
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL3
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL4
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL5
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL6
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL7
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc0resultind
+//AZALIA_CRC0_CHANNEL0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL1
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL2
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL3
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL4
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL5
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL6
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL7
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc1resultind
+//AZALIA_CRC1_CHANNEL0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL1
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL2
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL3
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL4
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL5
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL6
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL7
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azinputendpoint_f2codecind
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L
+
+
+// addressBlock: azroot_f2codecind
+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+
+
+// addressBlock: azf0stream0_streamind
+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream1_streamind
+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream2_streamind
+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream3_streamind
+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream4_streamind
+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream5_streamind
+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream6_streamind
+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream7_streamind
+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream8_streamind
+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream9_streamind
+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream10_streamind
+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream11_streamind
+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream12_streamind
+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream13_streamind
+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream14_streamind
+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream15_streamind
+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0endpoint0_endpointind
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint1_endpointind
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint2_endpointind
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint3_endpointind
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint4_endpointind
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint5_endpointind
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint6_endpointind
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint7_endpointind
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h
index e245e912535e..21d2f7d1debc 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h
@@ -1859,6 +1859,7 @@
 #define mmGCMC_SHARED_VIRT_RESET_REQ2_DEFAULT                                    0x00000000
 #define mmGCMC_VM_XGMI_LFB_CNTL_DEFAULT                                          0x00000000
 #define mmGCMC_VM_XGMI_LFB_SIZE_DEFAULT                                          0x00000000
+#define mmGCMC_VM_FB_NOALLOC_CNTL_DEFAULT                                        0x00000000
 #define mmGCUTCL2_HARVEST_BYPASS_GROUPS_DEFAULT                                  0x00000000
 
 
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 66a4151fa676..0102487a2c5f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -3661,6 +3661,8 @@
 #define mmGCMC_VM_XGMI_LFB_CNTL_BASE_IDX                                                               0
 #define mmGCMC_VM_XGMI_LFB_SIZE                                                                        0x16f8
 #define mmGCMC_VM_XGMI_LFB_SIZE_BASE_IDX                                                               0
+#define mmGCMC_VM_FB_NOALLOC_CNTL                                                                      0x16f9
+#define mmGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX                                                             0
 #define mmGCUTCL2_HARVEST_BYPASS_GROUPS                                                                0x16fa
 #define mmGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX                                                       0
 
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
index aed799d9a0e8..4d2a1432c121 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
@@ -612,6 +612,7 @@
 #define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT                                                                0x10
 #define SDMA0_UTCL1_PAGE__USE_BC__SHIFT                                                                       0x16
 #define SDMA0_UTCL1_PAGE__ADDR_IS_PA__SHIFT                                                                   0x17
+#define SDMA0_UTCL1_PAGE__LLC_NOALLOC__SHIFT                                                                  0x18
 #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
 #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
 #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000003C0L
@@ -622,6 +623,7 @@
 #define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE_MASK                                                                  0x003F0000L
 #define SDMA0_UTCL1_PAGE__USE_BC_MASK                                                                         0x00400000L
 #define SDMA0_UTCL1_PAGE__ADDR_IS_PA_MASK                                                                     0x00800000L
+#define SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK                                                                    0x01000000L
 //SDMA0_RELAX_ORDERING_LUT
 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
 #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
@@ -3484,6 +3486,7 @@
 #define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT                                                                0x10
 #define SDMA1_UTCL1_PAGE__USE_BC__SHIFT                                                                       0x16
 #define SDMA1_UTCL1_PAGE__ADDR_IS_PA__SHIFT                                                                   0x17
+#define SDMA1_UTCL1_PAGE__LLC_NOALLOC__SHIFT                                                                  0x18
 #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
 #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
 #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000003C0L
@@ -3494,6 +3497,7 @@
 #define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE_MASK                                                                  0x003F0000L
 #define SDMA1_UTCL1_PAGE__USE_BC_MASK                                                                         0x00400000L
 #define SDMA1_UTCL1_PAGE__ADDR_IS_PA_MASK                                                                     0x00800000L
+#define SDMA1_UTCL1_PAGE__LLC_NOALLOC_MASK                                                                    0x01000000L
 //SDMA1_RELAX_ORDERING_LUT
 #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
 #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
@@ -7284,6 +7288,7 @@
 #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
 #define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
 #define WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT                                                                  0x1d
+#define WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT                                                            0x1e
 #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
 #define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
 #define WD_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
@@ -7292,6 +7297,7 @@
 #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
 #define WD_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
 #define WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK                                                                    0x20000000L
+#define WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK                                                              0x40000000L
 //WD_UTCL1_STATUS
 #define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
 #define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
@@ -7321,6 +7327,7 @@
 #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
 #define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
 #define IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT                                                                  0x1d
+#define IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT                                                            0x1e
 #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
 #define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
 #define IA_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
@@ -7329,6 +7336,7 @@
 #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
 #define IA_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
 #define IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK                                                                    0x20000000L
+#define IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK                                                              0x40000000L
 //IA_UTCL1_STATUS
 #define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
 #define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
@@ -13584,6 +13592,13 @@
 //GCMC_VM_XGMI_LFB_SIZE
 #define GCMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT                                                             0x0
 #define GCMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK                                                               0x0001FFFFL
+//GCMC_VM_FB_NOALLOC_CNTL
+#define GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT                                                0x0
+#define GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT                                               0x1
+#define GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH__SHIFT                                               0x2
+#define GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK                                                  0x00000001L
+#define GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK                                                 0x00000002L
+#define GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH_MASK                                                 0x00000004L
 //GCUTCL2_HARVEST_BYPASS_GROUPS
 #define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT                                                   0x0
 #define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK                                                     0xFFFFFFFFL
@@ -20063,6 +20078,10 @@
 #define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT                                                       0x14
 #define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE__SHIFT                                                            0x18
 #define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE__SHIFT                                                            0x19
+#define DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC__SHIFT                                                             0x1a
+#define DB_RMI_L2_CACHE_CONTROL__S_NOALLOC__SHIFT                                                             0x1b
+#define DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC__SHIFT                                                         0x1c
+#define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC__SHIFT                                                        0x1d
 #define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY_MASK                                                             0x00000003L
 #define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY_MASK                                                             0x0000000CL
 #define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY_MASK                                                         0x00000030L
@@ -20072,6 +20091,10 @@
 #define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY_MASK                                                         0x00300000L
 #define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE_MASK                                                              0x01000000L
 #define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE_MASK                                                              0x02000000L
+#define DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC_MASK                                                               0x04000000L
+#define DB_RMI_L2_CACHE_CONTROL__S_NOALLOC_MASK                                                               0x08000000L
+#define DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC_MASK                                                           0x10000000L
+#define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC_MASK                                                          0x20000000L
 //TA_BC_BASE_ADDR
 #define TA_BC_BASE_ADDR__ADDRESS__SHIFT                                                                       0x0
 #define TA_BC_BASE_ADDR__ADDRESS_MASK                                                                         0xFFFFFFFFL
@@ -32705,6 +32728,8 @@
 #define RLC_SPM_MC_CNTL__RLC_SPM_VOL__SHIFT                                                                   0xe
 #define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT                                                                0xf
 #define RLC_SPM_MC_CNTL__RESERVED_3__SHIFT                                                                    0x10
+#define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC__SHIFT                                                           0x12
+#define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER__SHIFT                                                      0x13
 #define RLC_SPM_MC_CNTL__RESERVED__SHIFT                                                                      0x14
 #define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK                                                                    0x0000000FL
 #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK                                                                  0x00000030L
@@ -32717,6 +32742,8 @@
 #define RLC_SPM_MC_CNTL__RLC_SPM_VOL_MASK                                                                     0x00004000L
 #define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK                                                                  0x00008000L
 #define RLC_SPM_MC_CNTL__RESERVED_3_MASK                                                                      0x00030000L
+#define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_MASK                                                             0x00040000L
+#define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER_MASK                                                        0x00080000L
 #define RLC_SPM_MC_CNTL__RESERVED_MASK                                                                        0xFFF00000L
 //RLC_SPM_INT_CNTL
 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT                                                             0x0
@@ -37158,6 +37185,7 @@
 #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT                                         0x12
 #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT                                        0x15
 #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT                                          0x16
+#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT                                   0x18
 #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT                                           0x1f
 #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK                                            0x0000000FL
 #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK                                           0x00000070L
@@ -37169,6 +37197,7 @@
 #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK                                           0x001C0000L
 #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK                                          0x00200000L
 #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK                                            0x00C00000L
+#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK                                     0x01000000L
 #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK                                             0x80000000L
 
 
@@ -37761,6 +37790,7 @@
 #define SDMA2_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT                                                                0x10
 #define SDMA2_UTCL1_PAGE__USE_BC__SHIFT                                                                       0x16
 #define SDMA2_UTCL1_PAGE__ADDR_IS_PA__SHIFT                                                                   0x17
+#define SDMA2_UTCL1_PAGE__LLC_NOALLOC__SHIFT                                                                  0x18
 #define SDMA2_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
 #define SDMA2_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
 #define SDMA2_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000003C0L
@@ -37771,6 +37801,7 @@
 #define SDMA2_UTCL1_PAGE__DMA_PAGE_SIZE_MASK                                                                  0x003F0000L
 #define SDMA2_UTCL1_PAGE__USE_BC_MASK                                                                         0x00400000L
 #define SDMA2_UTCL1_PAGE__ADDR_IS_PA_MASK                                                                     0x00800000L
+#define SDMA2_UTCL1_PAGE__LLC_NOALLOC_MASK                                                                    0x01000000L
 //SDMA2_RELAX_ORDERING_LUT
 #define SDMA2_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
 #define SDMA2_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
@@ -40633,6 +40664,7 @@
 #define SDMA3_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT                                                                0x10
 #define SDMA3_UTCL1_PAGE__USE_BC__SHIFT                                                                       0x16
 #define SDMA3_UTCL1_PAGE__ADDR_IS_PA__SHIFT                                                                   0x17
+#define SDMA3_UTCL1_PAGE__LLC_NOALLOC__SHIFT                                                                  0x18
 #define SDMA3_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
 #define SDMA3_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
 #define SDMA3_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000003C0L
@@ -40643,6 +40675,7 @@
 #define SDMA3_UTCL1_PAGE__DMA_PAGE_SIZE_MASK                                                                  0x003F0000L
 #define SDMA3_UTCL1_PAGE__USE_BC_MASK                                                                         0x00400000L
 #define SDMA3_UTCL1_PAGE__ADDR_IS_PA_MASK                                                                     0x00800000L
+#define SDMA3_UTCL1_PAGE__LLC_NOALLOC_MASK                                                                    0x01000000L
 //SDMA3_RELAX_ORDERING_LUT
 #define SDMA3_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
 #define SDMA3_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h
index f26246a600c6..4089cfa081f5 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h
@@ -745,4 +745,4 @@
 #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT_MASK                                                  0x30000000L
 #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT_MASK                                                  0xC0000000L
 
-#endif
\ No newline at end of file
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_default.h
new file mode 100644
index 000000000000..7d2a1be4e722
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_default.h
@@ -0,0 +1,1253 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mmhub_2_3_0_DEFAULT_HEADER
+#define _mmhub_2_3_0_DEFAULT_HEADER
+
+
+// addressBlock: mmhub_dagbdec
+#define mmDAGB0_RDCLI0_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_RDCLI1_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_RDCLI2_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_RDCLI3_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_RDCLI4_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_RDCLI5_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_RDCLI6_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_RDCLI7_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_RDCLI8_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_RDCLI9_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_RDCLI10_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI11_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI12_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI13_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI14_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI15_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI16_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI17_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI18_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI19_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI20_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI21_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI22_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI23_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI24_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI25_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI26_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI27_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI28_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI29_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RDCLI30_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_RD_CNTL_DEFAULT                                                  0x03527df8
+#define mmDAGB0_RD_GMI_CNTL_DEFAULT                                              0x00003046
+#define mmDAGB0_RD_ADDR_DAGB_DEFAULT                                             0x00002039
+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
+#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT                                         0x08000100
+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT                                   0x08000100
+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT                                   0x08000100
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_DEFAULT                                  0x88888888
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_DEFAULT                                 0x11111111
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3_DEFAULT                                  0x88888888
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_DEFAULT                                 0x11111111
+#define mmDAGB0_RD_VC0_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_RD_VC1_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_RD_VC2_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_RD_VC3_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_RD_VC4_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_RD_VC5_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_RD_VC6_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_RD_VC7_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_RD_CNTL_MISC_DEFAULT                                             0x01a0e408
+#define mmDAGB0_RD_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
+#define mmDAGB0_RD_RDRET_CREDIT_CNTL_DEFAULT                                     0xc1041041
+#define mmDAGB0_RD_RDRET_CREDIT_CNTL2_DEFAULT                                    0x0000001a
+#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT                                        0x00000000
+#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT                                         0x00000000
+#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
+#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT                                        0x00000000
+#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT                                       0x00000000
+#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT                                        0x00000000
+#define mmDAGB0_WRCLI0_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_WRCLI1_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_WRCLI2_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_WRCLI3_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_WRCLI4_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_WRCLI5_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_WRCLI6_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_WRCLI7_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_WRCLI8_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_WRCLI9_DEFAULT                                                   0xfe5fe0f9
+#define mmDAGB0_WRCLI10_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI11_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI12_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI13_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI14_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI15_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI16_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI17_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI18_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI19_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI20_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI21_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI22_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI23_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI24_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI25_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI26_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI27_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI28_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI29_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WRCLI30_DEFAULT                                                  0xfe5fe0f9
+#define mmDAGB0_WR_CNTL_DEFAULT                                                  0x03527df8
+#define mmDAGB0_WR_GMI_CNTL_DEFAULT                                              0x00003046
+#define mmDAGB0_WR_ADDR_DAGB_DEFAULT                                             0x00002039
+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
+#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT                                         0x08000100
+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT                                   0x08000100
+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT                                   0x08000100
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_DEFAULT                                  0x88888888
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_DEFAULT                                 0x11111111
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3_DEFAULT                                  0x88888888
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_DEFAULT                                 0x11111111
+#define mmDAGB0_WR_DATA_DAGB_DEFAULT                                             0x00000039
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT                                  0x11111111
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT                                 0x00000000
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT                                  0x11111111
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT                                 0x00000000
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_DEFAULT                                  0x11111111
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_DEFAULT                                 0x00000000
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST3_DEFAULT                                  0x11111111
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3_DEFAULT                                 0x00000000
+#define mmDAGB0_WR_VC0_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_WR_VC1_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_WR_VC2_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_WR_VC3_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_WR_VC4_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_WR_VC5_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_WR_VC6_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_WR_VC7_CNTL_DEFAULT                                              0xff2ff082
+#define mmDAGB0_WR_CNTL_MISC_DEFAULT                                             0x01a0e408
+#define mmDAGB0_WR_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
+#define mmDAGB0_WR_DATA_CREDIT_DEFAULT                                           0x60606070
+#define mmDAGB0_WR_MISC_CREDIT_DEFAULT                                           0x0078dc87
+#define mmDAGB0_WR_OSD_CREDIT_CNTL1_DEFAULT                                      0x10024424
+#define mmDAGB0_WR_OSD_CREDIT_CNTL2_DEFAULT                                      0x00000004
+#define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_DEFAULT                                0x3ef21084
+#define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL2_DEFAULT                                0x00088888
+#define mmDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_DEFAULT                              0x3fe00800
+#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT                                        0x00000000
+#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT                                         0x00000000
+#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
+#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT                                        0x00000000
+#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT                                       0x00000000
+#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT                                        0x00000000
+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT                                   0x00000000
+#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT                                    0x00000000
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_DEFAULT                                 0x00000000
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_DEFAULT                           0x00000000
+#define mmDAGB0_DAGB_DLY_DEFAULT                                                 0x00000000
+#define mmDAGB0_CNTL_MISC_DEFAULT                                                0xcf7c1ffa
+#define mmDAGB0_CNTL_MISC2_DEFAULT                                               0x00fbd000
+#define mmDAGB0_FIFO_EMPTY_DEFAULT                                               0x00ffffff
+#define mmDAGB0_FIFO_FULL_DEFAULT                                                0x00000000
+#define mmDAGB0_WR_CREDITS_FULL_DEFAULT                                          0x1fffffff
+#define mmDAGB0_RD_CREDITS_FULL_DEFAULT                                          0x0003ffff
+#define mmDAGB0_PERFCOUNTER_LO_DEFAULT                                           0x00000000
+#define mmDAGB0_PERFCOUNTER_HI_DEFAULT                                           0x00000000
+#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
+#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
+#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT                                         0x00000000
+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
+#define mmDAGB0_RESERVE0_DEFAULT                                                 0xffffffff
+#define mmDAGB0_RESERVE1_DEFAULT                                                 0xffffffff
+#define mmDAGB0_RESERVE2_DEFAULT                                                 0xffffffff
+#define mmDAGB0_RESERVE3_DEFAULT                                                 0xffffffff
+#define mmDAGB0_RESERVE4_DEFAULT                                                 0xffffffff
+#define mmDAGB0_RESERVE5_DEFAULT                                                 0xffffffff
+#define mmDAGB0_RESERVE6_DEFAULT                                                 0xffffffff
+#define mmDAGB0_RESERVE7_DEFAULT                                                 0xffffffff
+#define mmDAGB0_RESERVE8_DEFAULT                                                 0xffffffff
+#define mmDAGB0_RESERVE9_DEFAULT                                                 0xffffffff
+
+
+// addressBlock: mmhub_mmea_mmeadec0
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT                                     0x55555555
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT                                     0x55555555
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT                                     0x55555555
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT                                     0x55555555
+#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT                                       0x00000e25
+#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT                                       0x00000e25
+#define mmMMEA0_DRAM_RD_LAZY_DEFAULT                                             0x78000924
+#define mmMMEA0_DRAM_WR_LAZY_DEFAULT                                             0x78000924
+#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT                                         0x16db4444
+#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT                                         0x16db4444
+#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT                                          0x20002000
+#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT                                          0x00db6249
+#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT                                          0x00db6249
+#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT                                      0x00000db6
+#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT                                      0x00000db6
+#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT                                        0x00000924
+#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT                                        0x00000924
+#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT                                      0x0000fdb6
+#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT                                      0x0000fdb6
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
+#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT                                      0x00000000
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT                                     0x00000000
+#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT                                      0x00000000
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT                                     0x00000000
+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT                                    0x00000000
+#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_DEFAULT                                   0x00000000
+#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT                             0x00000000
+#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT                                         0x000003cf
+#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT                                         0xfffff000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT                              0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT                              0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT                              0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT                              0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT                              0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT                              0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT                                 0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT                                0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT                                0x00000000
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT                                0x00000000
+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT                               0x00000000
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_DEFAULT                           0x00000000
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_DEFAULT                             0x00000000
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_DEFAULT                           0x00000000
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_DEFAULT                             0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT                                   0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT                                   0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT                                   0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT                                   0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT                                   0x00050408
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT                                   0x00050408
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT                                   0x04076543
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT                                   0x04076543
+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT                                     0x00000000
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT                                     0x00000000
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS1_DEFAULT                                      0x00000000
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS3_DEFAULT                                      0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT                                   0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT                                   0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT                                   0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT                                   0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT                                   0x00050408
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT                                   0x00050408
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT                                   0x04076543
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT                                   0x04076543
+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT                                     0x00000000
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT                                     0x00000000
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS1_DEFAULT                                      0x00000000
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS3_DEFAULT                                      0x00000000
+#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT                                 0x00600000
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ0_DEFAULT                               0x00000000
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ1_DEFAULT                               0x00000000
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ2_DEFAULT                               0x00000000
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ3_DEFAULT                               0x00000000
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ4_DEFAULT                               0x00000000
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ5_DEFAULT                               0x00000000
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS1_DEFAULT                                   0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS3_DEFAULT                                   0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS1_DEFAULT                                0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS3_DEFAULT                                0xfffffffe
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS1_DEFAULT                                    0x00050408
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS3_DEFAULT                                    0x00050408
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS1_DEFAULT                                    0x04076543
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS3_DEFAULT                                    0x04076543
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS1_DEFAULT                                  0x87654321
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS3_DEFAULT                                  0x87654321
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS1_DEFAULT                                  0xa9876543
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS3_DEFAULT                                  0xa9876543
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS1_DEFAULT                                   0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS3_DEFAULT                                   0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS1_DEFAULT                                0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS3_DEFAULT                                0xfffffffe
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS1_DEFAULT                                    0x00050408
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS3_DEFAULT                                    0x00050408
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS1_DEFAULT                                    0x04076543
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS3_DEFAULT                                    0x04076543
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS1_DEFAULT                                  0x87654321
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS3_DEFAULT                                  0x87654321
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS1_DEFAULT                                  0xa9876543
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS3_DEFAULT                                  0xa9876543
+#define mmMMEA0_ADDRNORMDRAM_MASKING_DEFAULT                                     0x00000fff
+#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
+#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
+#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
+#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
+#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT                                      0x00007777
+#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT                                      0x00017777
+#define mmMMEA0_IO_GROUP_BURST_DEFAULT                                           0x1f031f03
+#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT                                            0x00db6249
+#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT                                            0x00db6249
+#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT                                        0x00000db6
+#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT                                        0x00000db6
+#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT                                          0x00000924
+#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT                                          0x00000924
+#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT                                        0x00000492
+#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT                                        0x00000492
+#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
+#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
+#define mmMMEA0_SDP_ARB_DRAM_DEFAULT                                             0x00101e40
+#define mmMMEA0_SDP_ARB_FINAL_DEFAULT                                            0x00007fff
+#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT                                        0x00000000
+#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT                                          0x00000000
+#define mmMMEA0_SDP_CREDITS_DEFAULT                                              0x000101bf
+#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT                                         0x00000000
+#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT                                         0x00000000
+#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT                                         0x00000000
+#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT                                         0x00000000
+#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT                                         0x00000000
+#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT                                         0x00000000
+#define mmMMEA0_SDP_REQ_CNTL_DEFAULT                                             0x0000001f
+#define mmMMEA0_MISC_DEFAULT                                                     0x0c00a070
+#define mmMMEA0_LATENCY_SAMPLING_DEFAULT                                         0x00000000
+#define mmMMEA0_PERFCOUNTER_LO_DEFAULT                                           0x00000000
+#define mmMMEA0_PERFCOUNTER_HI_DEFAULT                                           0x00000000
+#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
+#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
+#define mmMMEA0_EDC_CNT_DEFAULT                                                  0x00000000
+#define mmMMEA0_EDC_CNT2_DEFAULT                                                 0x00000000
+#define mmMMEA0_DSM_CNTL_DEFAULT                                                 0x00000000
+#define mmMMEA0_DSM_CNTLA_DEFAULT                                                0x00000000
+#define mmMMEA0_DSM_CNTLB_DEFAULT                                                0x00000000
+#define mmMMEA0_DSM_CNTL2_DEFAULT                                                0x00000000
+#define mmMMEA0_DSM_CNTL2A_DEFAULT                                               0x00000000
+#define mmMMEA0_DSM_CNTL2B_DEFAULT                                               0x00000000
+#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT                                            0x08000100
+#define mmMMEA0_EDC_MODE_DEFAULT                                                 0x00000000
+#define mmMMEA0_ERR_STATUS_DEFAULT                                               0x00010300
+#define mmMMEA0_MISC2_DEFAULT                                                    0x00000000
+#define mmMMEA0_ADDRDEC_SELECT_DEFAULT                                           0x00000000
+#define mmMMEA0_EDC_CNT3_DEFAULT                                                 0x00000000
+#define mmMMEA0_SDP_PRIORITY_OVERRIDE_DEFAULT                                    0x00000000
+#define mmMMEA0_MISC_AON_DEFAULT                                                 0x00000001
+
+
+// addressBlock: mmhub_pctldec
+#define mmPCTL_CTRL_DEFAULT                                                      0x00088270
+#define mmPCTL_MMHUB_DEEPSLEEP_IB_DEFAULT                                        0x00000000
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT                                  0x00000000
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_DEFAULT                               0x00000000
+#define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT                                       0x00000000
+#define mmPCTL_PG_IGNORE_DEEPSLEEP_IB_DEFAULT                                    0x00000000
+#define mmPCTL_SLICE0_CFG_DAGB_WRBUSY_DEFAULT                                    0x00000000
+#define mmPCTL_SLICE0_CFG_DAGB_RDBUSY_DEFAULT                                    0x00000000
+#define mmPCTL_SLICE0_CFG_DS_ALLOW_DEFAULT                                       0x00000000
+#define mmPCTL_SLICE0_CFG_DS_ALLOW_IB_DEFAULT                                    0x00000000
+#define mmPCTL_SLICE1_CFG_DAGB_WRBUSY_DEFAULT                                    0x00000000
+#define mmPCTL_SLICE1_CFG_DAGB_RDBUSY_DEFAULT                                    0x00000000
+#define mmPCTL_SLICE1_CFG_DS_ALLOW_DEFAULT                                       0x00000000
+#define mmPCTL_SLICE1_CFG_DS_ALLOW_IB_DEFAULT                                    0x00000000
+#define mmPCTL_UTCL2_MISC_DEFAULT                                                0x00051000
+#define mmPCTL_SLICE0_MISC_DEFAULT                                               0x00040800
+#define mmPCTL_SLICE1_MISC_DEFAULT                                               0x00040800
+#define mmPCTL_RENG_CTRL_DEFAULT                                                 0x00000000
+#define mmPCTL_UTCL2_RENG_EXECUTE_DEFAULT                                        0x00000000
+#define mmPCTL_SLICE0_RENG_EXECUTE_DEFAULT                                       0x00000000
+#define mmPCTL_SLICE1_RENG_EXECUTE_DEFAULT                                       0x00000000
+#define mmPCTL_UTCL2_RENG_RAM_INDEX_DEFAULT                                      0x00000000
+#define mmPCTL_UTCL2_RENG_RAM_DATA_DEFAULT                                       0x00000000
+#define mmPCTL_SLICE0_RENG_RAM_INDEX_DEFAULT                                     0x00000000
+#define mmPCTL_SLICE0_RENG_RAM_DATA_DEFAULT                                      0x00000000
+#define mmPCTL_SLICE1_RENG_RAM_INDEX_DEFAULT                                     0x00000000
+#define mmPCTL_SLICE1_RENG_RAM_DATA_DEFAULT                                      0x00000000
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                         0x00000000
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                         0x00000000
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                         0x00000000
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                         0x00000000
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                         0x00000000
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                      0xffffffff
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                      0xffffffff
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                        0x00000000
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                        0x00000000
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                        0x00000000
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                        0x00000000
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                        0x00000000
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                     0xffffffff
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                     0xffffffff
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                        0x00000000
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                        0x00000000
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                        0x00000000
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                        0x00000000
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                        0x00000000
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                     0xffffffff
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                     0xffffffff
+#define mmPCTL_STATUS_DEFAULT                                                    0x00000000
+#define mmPCTL_PERFCOUNTER_LO_DEFAULT                                            0x00000000
+#define mmPCTL_PERFCOUNTER_HI_DEFAULT                                            0x00000000
+#define mmPCTL_PERFCOUNTER0_CFG_DEFAULT                                          0x00000000
+#define mmPCTL_PERFCOUNTER1_CFG_DEFAULT                                          0x00000000
+#define mmPCTL_PERFCOUNTER_RSLT_CNTL_DEFAULT                                     0x04000000
+#define mmPCTL_RESERVED_0_DEFAULT                                                0x00000000
+#define mmPCTL_RESERVED_1_DEFAULT                                                0x00000000
+#define mmPCTL_RESERVED_2_DEFAULT                                                0x00000000
+#define mmPCTL_RESERVED_3_DEFAULT                                                0x00000000
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pfdec
+#define mmMMMC_VM_MX_L1_TLB0_STATUS_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLB1_STATUS_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLB2_STATUS_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLB3_STATUS_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLB4_STATUS_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLB5_STATUS_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLB6_STATUS_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLB7_STATUS_DEFAULT                                      0x00000000
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pldec
+#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT                                 0x00000000
+#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT                                 0x00000000
+#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT                                 0x00000000
+#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT                                 0x00000000
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT                            0x04000000
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1prdec
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT                                   0x00000000
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT                                   0x00000000
+
+
+// addressBlock: mmhub_l1tlb_mmvmtlspfdec
+#define mmMMMC_VM_MX_L1_TLS0_CNTL_DEFAULT                                        0xa5a50004
+#define mmMMMC_VM_MX_L1_TLS0_CNTL0_DEFAULT                                       0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL1_DEFAULT                                       0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL2_DEFAULT                                       0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL3_DEFAULT                                       0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL4_DEFAULT                                       0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL5_DEFAULT                                       0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL6_DEFAULT                                       0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL7_DEFAULT                                       0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL8_DEFAULT                                       0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL9_DEFAULT                                       0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL10_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL11_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL12_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL13_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL14_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL15_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL16_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL17_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL18_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL19_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL20_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL21_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL22_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL23_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL24_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL25_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL26_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL27_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL28_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL29_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL30_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL31_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL32_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL33_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL34_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL35_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL36_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_CNTL37_DEFAULT                                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32_DEFAULT                            0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32_DEFAULT                           0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32_DEFAULT                             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32_DEFAULT                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32_DEFAULT                      0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32_DEFAULT             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32_DEFAULT             0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_DEFAULT                     0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_DEFAULT                  0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_DEFAULT                  0x00000000
+#define mmMMVM_L2_SAW_CNTL_DEFAULT                                               0x0c0b8602
+#define mmMMVM_L2_SAW_CNTL2_DEFAULT                                              0x00000000
+#define mmMMVM_L2_SAW_CNTL3_DEFAULT                                              0x80100004
+#define mmMMVM_L2_SAW_CNTL4_DEFAULT                                              0x00000001
+#define mmMMVM_L2_SAW_CONTEXT0_CNTL_DEFAULT                                      0x00fffed8
+#define mmMMVM_L2_SAW_CONTEXT0_CNTL2_DEFAULT                                     0x00000000
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
+#define mmMMVM_L2_SAW_CONTEXTS_DISABLE_DEFAULT                                   0x00000000
+#define mmMMVM_L2_SAW_PIPES_BUSY_LO32_DEFAULT                                    0x00000000
+#define mmMMVM_L2_SAW_PIPES_BUSY_HI32_DEFAULT                                    0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS_DEFAULT                          0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32_DEFAULT                     0x00000000
+#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32_DEFAULT                     0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2dec
+#define mmMM_ATC_L2_CNTL_DEFAULT                                                 0x05311b00
+#define mmMM_ATC_L2_CNTL2_DEFAULT                                                0x00000100
+#define mmMM_ATC_L2_CACHE_DATA0_DEFAULT                                          0x00000000
+#define mmMM_ATC_L2_CACHE_DATA1_DEFAULT                                          0x00000000
+#define mmMM_ATC_L2_CACHE_DATA2_DEFAULT                                          0x00000000
+#define mmMM_ATC_L2_CNTL3_DEFAULT                                                0x07e090c0
+#define mmMM_ATC_L2_CNTL4_DEFAULT                                                0x000090c0
+#define mmMM_ATC_L2_CNTL5_DEFAULT                                                0x00000000
+#define mmMM_ATC_L2_MM_GROUP_RT_CLASSES_DEFAULT                                  0x00000005
+#define mmMM_ATC_L2_STATUS_DEFAULT                                               0x00000000
+#define mmMM_ATC_L2_STATUS2_DEFAULT                                              0x00000000
+#define mmMM_ATC_L2_MISC_CG_DEFAULT                                              0x00000200
+#define mmMM_ATC_L2_MEM_POWER_LS_DEFAULT                                         0x00000208
+#define mmMM_ATC_L2_CGTT_CLK_CTRL_DEFAULT                                        0x00008080
+#define mmMM_ATC_L2_SDPPORT_CTRL_DEFAULT                                         0x000003ff
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pfdec
+#define mmMMVM_L2_CNTL_DEFAULT                                                   0x00080602
+#define mmMMVM_L2_CNTL2_DEFAULT                                                  0x00000000
+#define mmMMVM_L2_CNTL3_DEFAULT                                                  0x80100007
+#define mmMMVM_L2_STATUS_DEFAULT                                                 0x00000000
+#define mmMMVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT                                     0x00000090
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT                                0x00000000
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT                                0x00000000
+#define mmMMVM_INVALIDATE_CNTL_DEFAULT                                           0x0000010f
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL_DEFAULT                                  0x3ffffffc
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT                                 0x000a0000
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT                              0xffffffff
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT                              0xffffffff
+#define mmMMVM_L2_PROTECTION_FAULT_STATUS_DEFAULT                                0x00000000
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT                             0x00000000
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT                             0x00000000
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT                     0x00000000
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT                     0x00000000
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT               0x00000000
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT               0x00000000
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT              0x00000000
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT              0x00000000
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT                  0x00000000
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT                  0x00000000
+#define mmMMVM_L2_CNTL4_DEFAULT                                                  0x000000c1
+#define mmMMVM_L2_MM_GROUP_RT_CLASSES_DEFAULT                                    0x00000000
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT                               0x00000000
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT                              0x00000000
+#define mmMMVM_L2_CACHE_PARITY_CNTL_DEFAULT                                      0x00000000
+#define mmMMVM_L2_IH_LOG_CNTL_DEFAULT                                            0x00000002
+#define mmMMVM_L2_IH_LOG_BUSY_DEFAULT                                            0x00000000
+#define mmMMVM_L2_CGTT_CLK_CTRL_DEFAULT                                          0x00008080
+#define mmMMVM_L2_CNTL5_DEFAULT                                                  0x00003fe0
+#define mmMMVM_L2_GCR_CNTL_DEFAULT                                               0x00000000
+#define mmMMVM_L2_CGTT_BUSY_CTRL_DEFAULT                                         0x00000004
+#define mmMMVM_L2_PTE_CACHE_DUMP_CNTL_DEFAULT                                    0x00000000
+#define mmMMVM_L2_PTE_CACHE_DUMP_READ_DEFAULT                                    0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2vcdec
+#define mmMMVM_CONTEXT0_CNTL_DEFAULT                                             0x007ffe80
+#define mmMMVM_CONTEXT1_CNTL_DEFAULT                                             0x007ffe80
+#define mmMMVM_CONTEXT2_CNTL_DEFAULT                                             0x007ffe80
+#define mmMMVM_CONTEXT3_CNTL_DEFAULT                                             0x007ffe80
+#define mmMMVM_CONTEXT4_CNTL_DEFAULT                                             0x007ffe80
+#define mmMMVM_CONTEXT5_CNTL_DEFAULT                                             0x007ffe80
+#define mmMMVM_CONTEXT6_CNTL_DEFAULT                                             0x007ffe80
+#define mmMMVM_CONTEXT7_CNTL_DEFAULT                                             0x007ffe80
+#define mmMMVM_CONTEXT8_CNTL_DEFAULT                                             0x007ffe80
+#define mmMMVM_CONTEXT9_CNTL_DEFAULT                                             0x007ffe80
+#define mmMMVM_CONTEXT10_CNTL_DEFAULT                                            0x007ffe80
+#define mmMMVM_CONTEXT11_CNTL_DEFAULT                                            0x007ffe80
+#define mmMMVM_CONTEXT12_CNTL_DEFAULT                                            0x007ffe80
+#define mmMMVM_CONTEXT13_CNTL_DEFAULT                                            0x007ffe80
+#define mmMMVM_CONTEXT14_CNTL_DEFAULT                                            0x007ffe80
+#define mmMMVM_CONTEXT15_CNTL_DEFAULT                                            0x007ffe80
+#define mmMMVM_CONTEXTS_DISABLE_DEFAULT                                          0x00000000
+#define mmMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT                      0x00001c00
+#define mmMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c00
+#define mmMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c00
+#define mmMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c00
+#define mmMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c00
+#define mmMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c00
+#define mmMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c00
+#define mmMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c00
+#define mmMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c00
+#define mmMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c00
+#define mmMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT             0x00001c00
+#define mmMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c00
+#define mmMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c00
+#define mmMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c00
+#define mmMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c00
+#define mmMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c00
+#define mmMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_DEFAULT            0x00001c00
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pldec
+#define mmMMMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT                                    0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT                                    0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT                                    0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT                                    0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT                                    0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT                                    0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT                                    0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT                                    0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT                               0x04000000
+#define mmMMUTCL2_PERFCOUNTER0_CFG_DEFAULT                                       0x00000000
+#define mmMMUTCL2_PERFCOUNTER1_CFG_DEFAULT                                       0x00000000
+#define mmMMUTCL2_PERFCOUNTER2_CFG_DEFAULT                                       0x00000000
+#define mmMMUTCL2_PERFCOUNTER3_CFG_DEFAULT                                       0x00000000
+#define mmMMUTCL2_PERFCOUNTER_RSLT_CNTL_DEFAULT                                  0x04000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2prdec
+#define mmMMMC_VM_L2_PERFCOUNTER_LO_DEFAULT                                      0x00000000
+#define mmMMMC_VM_L2_PERFCOUNTER_HI_DEFAULT                                      0x00000000
+#define mmMMUTCL2_PERFCOUNTER_LO_DEFAULT                                         0x00000000
+#define mmMMUTCL2_PERFCOUNTER_HI_DEFAULT                                         0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT                                     0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT                                     0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT                                     0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT                                     0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT                                     0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT                                     0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT                                     0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT                                     0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT                                     0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT                                     0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF16_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF17_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF18_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF19_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF20_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF21_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF22_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF23_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF24_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF25_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF26_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF27_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF28_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF29_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF30_DEFAULT                                    0x00000000
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF31_DEFAULT                                    0x00000000
+#define mmMMVM_IOMMU_MMIO_CNTRL_1_DEFAULT                                        0x00000100
+#define mmMMMC_VM_MARC_BASE_LO_0_DEFAULT                                         0x00000000
+#define mmMMMC_VM_MARC_BASE_LO_1_DEFAULT                                         0x00000000
+#define mmMMMC_VM_MARC_BASE_LO_2_DEFAULT                                         0x00000000
+#define mmMMMC_VM_MARC_BASE_LO_3_DEFAULT                                         0x00000000
+#define mmMMMC_VM_MARC_BASE_HI_0_DEFAULT                                         0x00000000
+#define mmMMMC_VM_MARC_BASE_HI_1_DEFAULT                                         0x00000000
+#define mmMMMC_VM_MARC_BASE_HI_2_DEFAULT                                         0x00000000
+#define mmMMMC_VM_MARC_BASE_HI_3_DEFAULT                                         0x00000000
+#define mmMMMC_VM_MARC_RELOC_LO_0_DEFAULT                                        0x00000000
+#define mmMMMC_VM_MARC_RELOC_LO_1_DEFAULT                                        0x00000000
+#define mmMMMC_VM_MARC_RELOC_LO_2_DEFAULT                                        0x00000000
+#define mmMMMC_VM_MARC_RELOC_LO_3_DEFAULT                                        0x00000000
+#define mmMMMC_VM_MARC_RELOC_HI_0_DEFAULT                                        0x00000000
+#define mmMMMC_VM_MARC_RELOC_HI_1_DEFAULT                                        0x00000000
+#define mmMMMC_VM_MARC_RELOC_HI_2_DEFAULT                                        0x00000000
+#define mmMMMC_VM_MARC_RELOC_HI_3_DEFAULT                                        0x00000000
+#define mmMMMC_VM_MARC_LEN_LO_0_DEFAULT                                          0x00000000
+#define mmMMMC_VM_MARC_LEN_LO_1_DEFAULT                                          0x00000000
+#define mmMMMC_VM_MARC_LEN_LO_2_DEFAULT                                          0x00000000
+#define mmMMMC_VM_MARC_LEN_LO_3_DEFAULT                                          0x00000000
+#define mmMMMC_VM_MARC_LEN_HI_0_DEFAULT                                          0x00000000
+#define mmMMMC_VM_MARC_LEN_HI_1_DEFAULT                                          0x00000000
+#define mmMMMC_VM_MARC_LEN_HI_2_DEFAULT                                          0x00000000
+#define mmMMMC_VM_MARC_LEN_HI_3_DEFAULT                                          0x00000000
+#define mmMMVM_IOMMU_CONTROL_REGISTER_DEFAULT                                    0x00000000
+#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT           0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_DEFAULT                                             0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_0_DEFAULT                                        0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_1_DEFAULT                                        0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_2_DEFAULT                                        0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_3_DEFAULT                                        0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_4_DEFAULT                                        0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_5_DEFAULT                                        0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_6_DEFAULT                                        0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_7_DEFAULT                                        0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_8_DEFAULT                                        0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_9_DEFAULT                                        0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_10_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_11_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_12_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_13_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_14_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_15_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_16_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_17_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_18_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_19_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_20_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_21_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_22_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_23_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_24_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_25_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_26_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_27_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_28_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_29_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_30_DEFAULT                                       0x00000000
+#define mmMMVM_PCIE_ATS_CNTL_VF_31_DEFAULT                                       0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
+#define mmMMMC_VM_NB_MMIOBASE_DEFAULT                                            0x00000000
+#define mmMMMC_VM_NB_MMIOLIMIT_DEFAULT                                           0x00000000
+#define mmMMMC_VM_NB_PCI_CTRL_DEFAULT                                            0x00000000
+#define mmMMMC_VM_NB_PCI_ARB_DEFAULT                                             0x00000008
+#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT                                   0x00000000
+#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT                                  0x00000000
+#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT                                  0x00000000
+#define mmMMMC_VM_FB_OFFSET_DEFAULT                                              0x00000000
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT                       0x00000000
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT                       0x00000000
+#define mmMMMC_VM_STEERING_DEFAULT                                               0x00000001
+#define mmMMMC_SHARED_VIRT_RESET_REQ_DEFAULT                                     0x00000000
+#define mmMMMC_MEM_POWER_LS_DEFAULT                                              0x00000208
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT                           0x00000000
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT                             0x000fffff
+#define mmMMMC_VM_APT_CNTL_DEFAULT                                               0x0000000c
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT                            0x00000000
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT                                0x00000000
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT                                  0x000fffff
+#define mmMMUTCL2_CGTT_CLK_CTRL_DEFAULT                                          0x00008080
+#define mmMMMC_SHARED_ACTIVE_FCN_ID_DEFAULT                                      0x00000000
+#define mmMMMC_SHARED_VIRT_RESET_REQ2_DEFAULT                                    0x00000000
+#define mmMMUTCL2_CGTT_BUSY_CTRL_DEFAULT                                         0x00000008
+#define mmMMUTCL2_HARVEST_BYPASS_GROUPS_DEFAULT                                  0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
+#define mmMMMC_VM_FB_LOCATION_BASE_DEFAULT                                       0x00000000
+#define mmMMMC_VM_FB_LOCATION_TOP_DEFAULT                                        0x00000000
+#define mmMMMC_VM_AGP_TOP_DEFAULT                                                0x00000000
+#define mmMMMC_VM_AGP_BOT_DEFAULT                                                0x00000000
+#define mmMMMC_VM_AGP_BASE_DEFAULT                                               0x00000000
+#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT                               0x00000000
+#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT                              0x00000000
+#define mmMMMC_VM_MX_L1_TLB_CNTL_DEFAULT                                         0x00000501
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
+#define mmMM_ATC_L2_PERFCOUNTER_LO_DEFAULT                                       0x00000000
+#define mmMM_ATC_L2_PERFCOUNTER_HI_DEFAULT                                       0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
+#define mmMM_ATC_L2_PERFCOUNTER0_CFG_DEFAULT                                     0x00000000
+#define mmMM_ATC_L2_PERFCOUNTER1_CFG_DEFAULT                                     0x00000000
+#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT                                0x04000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2ptdec
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE0_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE1_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE0_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE1_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE0_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE1_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE0_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE1_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE0_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE1_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE0_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE1_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE0_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE1_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE0_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE1_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE0_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE1_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT                         0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE0_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE1_DEFAULT                              0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE0_DEFAULT                             0x00000000
+#define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE1_DEFAULT                             0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE0_DEFAULT                             0x00000000
+#define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE1_DEFAULT                             0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE0_DEFAULT                             0x00000000
+#define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE1_DEFAULT                             0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE0_DEFAULT                             0x00000000
+#define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE1_DEFAULT                             0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE0_DEFAULT                             0x00000000
+#define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE1_DEFAULT                             0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                       0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT                      0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT                        0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE0_DEFAULT                             0x00000000
+#define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE1_DEFAULT                             0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2indec
+#define mmMMVM_INVALIDATE_ENG0_SEM_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG0_REQ_DEFAULT                                       0x02f80000
+#define mmMMVM_INVALIDATE_ENG0_ACK_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG0_RESERVE0_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG0_RESERVE1_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG0_RESERVE2_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG1_SEM_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG1_REQ_DEFAULT                                       0x02f80000
+#define mmMMVM_INVALIDATE_ENG1_ACK_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG1_RESERVE0_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG1_RESERVE1_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG1_RESERVE2_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG2_SEM_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG2_REQ_DEFAULT                                       0x02f80000
+#define mmMMVM_INVALIDATE_ENG2_ACK_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG2_RESERVE0_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG2_RESERVE1_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG2_RESERVE2_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG3_SEM_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG3_REQ_DEFAULT                                       0x02f80000
+#define mmMMVM_INVALIDATE_ENG3_ACK_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG3_RESERVE0_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG3_RESERVE1_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG3_RESERVE2_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG4_SEM_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG4_REQ_DEFAULT                                       0x02f80000
+#define mmMMVM_INVALIDATE_ENG4_ACK_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG4_RESERVE0_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG4_RESERVE1_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG4_RESERVE2_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG5_SEM_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG5_REQ_DEFAULT                                       0x02f80000
+#define mmMMVM_INVALIDATE_ENG5_ACK_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG5_RESERVE0_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG5_RESERVE1_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG5_RESERVE2_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG6_SEM_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG6_REQ_DEFAULT                                       0x02f80000
+#define mmMMVM_INVALIDATE_ENG6_ACK_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG6_RESERVE0_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG6_RESERVE1_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG6_RESERVE2_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG7_SEM_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG7_REQ_DEFAULT                                       0x02f80000
+#define mmMMVM_INVALIDATE_ENG7_ACK_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG7_RESERVE0_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG7_RESERVE1_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG7_RESERVE2_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG8_SEM_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG8_REQ_DEFAULT                                       0x02f80000
+#define mmMMVM_INVALIDATE_ENG8_ACK_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG8_RESERVE0_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG8_RESERVE1_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG8_RESERVE2_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG9_SEM_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG9_REQ_DEFAULT                                       0x02f80000
+#define mmMMVM_INVALIDATE_ENG9_ACK_DEFAULT                                       0x00000000
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT                           0x00000000
+#define mmMMVM_INVALIDATE_ENG9_RESERVE0_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG9_RESERVE1_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG9_RESERVE2_DEFAULT                                  0x00000000
+#define mmMMVM_INVALIDATE_ENG10_SEM_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG10_REQ_DEFAULT                                      0x02f80000
+#define mmMMVM_INVALIDATE_ENG10_ACK_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG10_RESERVE0_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG10_RESERVE1_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG10_RESERVE2_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG11_SEM_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG11_REQ_DEFAULT                                      0x02f80000
+#define mmMMVM_INVALIDATE_ENG11_ACK_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG11_RESERVE0_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG11_RESERVE1_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG11_RESERVE2_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG12_SEM_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG12_REQ_DEFAULT                                      0x02f80000
+#define mmMMVM_INVALIDATE_ENG12_ACK_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG12_RESERVE0_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG12_RESERVE1_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG12_RESERVE2_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG13_SEM_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG13_REQ_DEFAULT                                      0x02f80000
+#define mmMMVM_INVALIDATE_ENG13_ACK_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG13_RESERVE0_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG13_RESERVE1_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG13_RESERVE2_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG14_SEM_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG14_REQ_DEFAULT                                      0x02f80000
+#define mmMMVM_INVALIDATE_ENG14_ACK_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG14_RESERVE0_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG14_RESERVE1_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG14_RESERVE2_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG15_SEM_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG15_REQ_DEFAULT                                      0x02f80000
+#define mmMMVM_INVALIDATE_ENG15_ACK_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG15_RESERVE0_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG15_RESERVE1_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG15_RESERVE2_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG16_SEM_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG16_REQ_DEFAULT                                      0x02f80000
+#define mmMMVM_INVALIDATE_ENG16_ACK_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG16_RESERVE0_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG16_RESERVE1_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG16_RESERVE2_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG17_SEM_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG17_REQ_DEFAULT                                      0x02f80000
+#define mmMMVM_INVALIDATE_ENG17_ACK_DEFAULT                                      0x00000000
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT                          0x00000000
+#define mmMMVM_INVALIDATE_ENG17_RESERVE0_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG17_RESERVE1_DEFAULT                                 0x00000000
+#define mmMMVM_INVALIDATE_ENG17_RESERVE2_DEFAULT                                 0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpfdec
+#define mmMML2TLB_TLB0_STATUS_DEFAULT                                            0x00000000
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpldec
+#define mmMML2TLB_PERFCOUNTER0_CFG_DEFAULT                                       0x00000000
+#define mmMML2TLB_PERFCOUNTER1_CFG_DEFAULT                                       0x00000000
+#define mmMML2TLB_PERFCOUNTER2_CFG_DEFAULT                                       0x00000000
+#define mmMML2TLB_PERFCOUNTER3_CFG_DEFAULT                                       0x00000000
+#define mmMML2TLB_PERFCOUNTER_RSLT_CNTL_DEFAULT                                  0x04000000
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbprdec
+#define mmMML2TLB_PERFCOUNTER_LO_DEFAULT                                         0x00000000
+#define mmMML2TLB_PERFCOUNTER_HI_DEFAULT                                         0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_offset.h
new file mode 100644
index 000000000000..c4536de17eb4
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_offset.h
@@ -0,0 +1,2439 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mmhub_2_3_0_OFFSET_HEADER
+#define _mmhub_2_3_0_OFFSET_HEADER
+
+
+
+// addressBlock: mmhub_dagbdec
+// base address: 0x68000
+#define mmDAGB0_RDCLI0                                                                                 0x0000
+#define mmDAGB0_RDCLI0_BASE_IDX                                                                        1
+#define mmDAGB0_RDCLI1                                                                                 0x0001
+#define mmDAGB0_RDCLI1_BASE_IDX                                                                        1
+#define mmDAGB0_RDCLI2                                                                                 0x0002
+#define mmDAGB0_RDCLI2_BASE_IDX                                                                        1
+#define mmDAGB0_RDCLI3                                                                                 0x0003
+#define mmDAGB0_RDCLI3_BASE_IDX                                                                        1
+#define mmDAGB0_RDCLI4                                                                                 0x0004
+#define mmDAGB0_RDCLI4_BASE_IDX                                                                        1
+#define mmDAGB0_RDCLI5                                                                                 0x0005
+#define mmDAGB0_RDCLI5_BASE_IDX                                                                        1
+#define mmDAGB0_RDCLI6                                                                                 0x0006
+#define mmDAGB0_RDCLI6_BASE_IDX                                                                        1
+#define mmDAGB0_RDCLI7                                                                                 0x0007
+#define mmDAGB0_RDCLI7_BASE_IDX                                                                        1
+#define mmDAGB0_RDCLI8                                                                                 0x0008
+#define mmDAGB0_RDCLI8_BASE_IDX                                                                        1
+#define mmDAGB0_RDCLI9                                                                                 0x0009
+#define mmDAGB0_RDCLI9_BASE_IDX                                                                        1
+#define mmDAGB0_RDCLI10                                                                                0x000a
+#define mmDAGB0_RDCLI10_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI11                                                                                0x000b
+#define mmDAGB0_RDCLI11_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI12                                                                                0x000c
+#define mmDAGB0_RDCLI12_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI13                                                                                0x000d
+#define mmDAGB0_RDCLI13_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI14                                                                                0x000e
+#define mmDAGB0_RDCLI14_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI15                                                                                0x000f
+#define mmDAGB0_RDCLI15_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI16                                                                                0x0010
+#define mmDAGB0_RDCLI16_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI17                                                                                0x0011
+#define mmDAGB0_RDCLI17_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI18                                                                                0x0012
+#define mmDAGB0_RDCLI18_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI19                                                                                0x0013
+#define mmDAGB0_RDCLI19_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI20                                                                                0x0014
+#define mmDAGB0_RDCLI20_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI21                                                                                0x0015
+#define mmDAGB0_RDCLI21_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI22                                                                                0x0016
+#define mmDAGB0_RDCLI22_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI23                                                                                0x0017
+#define mmDAGB0_RDCLI23_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI24                                                                                0x0018
+#define mmDAGB0_RDCLI24_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI25                                                                                0x0019
+#define mmDAGB0_RDCLI25_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI26                                                                                0x001a
+#define mmDAGB0_RDCLI26_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI27                                                                                0x001b
+#define mmDAGB0_RDCLI27_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI28                                                                                0x001c
+#define mmDAGB0_RDCLI28_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI29                                                                                0x001d
+#define mmDAGB0_RDCLI29_BASE_IDX                                                                       1
+#define mmDAGB0_RDCLI30                                                                                0x001e
+#define mmDAGB0_RDCLI30_BASE_IDX                                                                       1
+#define mmDAGB0_RD_CNTL                                                                                0x001f
+#define mmDAGB0_RD_CNTL_BASE_IDX                                                                       1
+#define mmDAGB0_RD_GMI_CNTL                                                                            0x0020
+#define mmDAGB0_RD_GMI_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_RD_ADDR_DAGB                                                                           0x0021
+#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX                                                                  1
+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST                                                               0x0022
+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER                                                              0x0023
+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
+#define mmDAGB0_RD_CGTT_CLK_CTRL                                                                       0x0024
+#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX                                                              1
+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL                                                                 0x0025
+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL                                                                 0x0026
+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0                                                                0x0027
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0                                                               0x0028
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1                                                                0x0029
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1                                                               0x002a
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2                                                                0x002b
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX                                                       1
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2                                                               0x002c
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX                                                      1
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3                                                                0x002d
+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX                                                       1
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3                                                               0x002e
+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX                                                      1
+#define mmDAGB0_RD_VC0_CNTL                                                                            0x002f
+#define mmDAGB0_RD_VC0_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_RD_VC1_CNTL                                                                            0x0030
+#define mmDAGB0_RD_VC1_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_RD_VC2_CNTL                                                                            0x0031
+#define mmDAGB0_RD_VC2_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_RD_VC3_CNTL                                                                            0x0032
+#define mmDAGB0_RD_VC3_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_RD_VC4_CNTL                                                                            0x0033
+#define mmDAGB0_RD_VC4_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_RD_VC5_CNTL                                                                            0x0034
+#define mmDAGB0_RD_VC5_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_RD_VC6_CNTL                                                                            0x0035
+#define mmDAGB0_RD_VC6_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_RD_VC7_CNTL                                                                            0x0036
+#define mmDAGB0_RD_VC7_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_RD_CNTL_MISC                                                                           0x0037
+#define mmDAGB0_RD_CNTL_MISC_BASE_IDX                                                                  1
+#define mmDAGB0_RD_TLB_CREDIT                                                                          0x0038
+#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX                                                                 1
+#define mmDAGB0_RD_RDRET_CREDIT_CNTL                                                                   0x0039
+#define mmDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX                                                          1
+#define mmDAGB0_RD_RDRET_CREDIT_CNTL2                                                                  0x003a
+#define mmDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX                                                         1
+#define mmDAGB0_RDCLI_ASK_PENDING                                                                      0x003b
+#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX                                                             1
+#define mmDAGB0_RDCLI_GO_PENDING                                                                       0x003c
+#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX                                                              1
+#define mmDAGB0_RDCLI_GBLSEND_PENDING                                                                  0x003d
+#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX                                                         1
+#define mmDAGB0_RDCLI_TLB_PENDING                                                                      0x003e
+#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX                                                             1
+#define mmDAGB0_RDCLI_OARB_PENDING                                                                     0x003f
+#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX                                                            1
+#define mmDAGB0_RDCLI_OSD_PENDING                                                                      0x0040
+#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX                                                             1
+#define mmDAGB0_WRCLI0                                                                                 0x0041
+#define mmDAGB0_WRCLI0_BASE_IDX                                                                        1
+#define mmDAGB0_WRCLI1                                                                                 0x0042
+#define mmDAGB0_WRCLI1_BASE_IDX                                                                        1
+#define mmDAGB0_WRCLI2                                                                                 0x0043
+#define mmDAGB0_WRCLI2_BASE_IDX                                                                        1
+#define mmDAGB0_WRCLI3                                                                                 0x0044
+#define mmDAGB0_WRCLI3_BASE_IDX                                                                        1
+#define mmDAGB0_WRCLI4                                                                                 0x0045
+#define mmDAGB0_WRCLI4_BASE_IDX                                                                        1
+#define mmDAGB0_WRCLI5                                                                                 0x0046
+#define mmDAGB0_WRCLI5_BASE_IDX                                                                        1
+#define mmDAGB0_WRCLI6                                                                                 0x0047
+#define mmDAGB0_WRCLI6_BASE_IDX                                                                        1
+#define mmDAGB0_WRCLI7                                                                                 0x0048
+#define mmDAGB0_WRCLI7_BASE_IDX                                                                        1
+#define mmDAGB0_WRCLI8                                                                                 0x0049
+#define mmDAGB0_WRCLI8_BASE_IDX                                                                        1
+#define mmDAGB0_WRCLI9                                                                                 0x004a
+#define mmDAGB0_WRCLI9_BASE_IDX                                                                        1
+#define mmDAGB0_WRCLI10                                                                                0x004b
+#define mmDAGB0_WRCLI10_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI11                                                                                0x004c
+#define mmDAGB0_WRCLI11_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI12                                                                                0x004d
+#define mmDAGB0_WRCLI12_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI13                                                                                0x004e
+#define mmDAGB0_WRCLI13_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI14                                                                                0x004f
+#define mmDAGB0_WRCLI14_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI15                                                                                0x0050
+#define mmDAGB0_WRCLI15_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI16                                                                                0x0051
+#define mmDAGB0_WRCLI16_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI17                                                                                0x0052
+#define mmDAGB0_WRCLI17_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI18                                                                                0x0053
+#define mmDAGB0_WRCLI18_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI19                                                                                0x0054
+#define mmDAGB0_WRCLI19_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI20                                                                                0x0055
+#define mmDAGB0_WRCLI20_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI21                                                                                0x0056
+#define mmDAGB0_WRCLI21_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI22                                                                                0x0057
+#define mmDAGB0_WRCLI22_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI23                                                                                0x0058
+#define mmDAGB0_WRCLI23_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI24                                                                                0x0059
+#define mmDAGB0_WRCLI24_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI25                                                                                0x005a
+#define mmDAGB0_WRCLI25_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI26                                                                                0x005b
+#define mmDAGB0_WRCLI26_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI27                                                                                0x005c
+#define mmDAGB0_WRCLI27_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI28                                                                                0x005d
+#define mmDAGB0_WRCLI28_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI29                                                                                0x005e
+#define mmDAGB0_WRCLI29_BASE_IDX                                                                       1
+#define mmDAGB0_WRCLI30                                                                                0x005f
+#define mmDAGB0_WRCLI30_BASE_IDX                                                                       1
+#define mmDAGB0_WR_CNTL                                                                                0x0060
+#define mmDAGB0_WR_CNTL_BASE_IDX                                                                       1
+#define mmDAGB0_WR_GMI_CNTL                                                                            0x0061
+#define mmDAGB0_WR_GMI_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_WR_ADDR_DAGB                                                                           0x0062
+#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX                                                                  1
+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST                                                               0x0063
+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER                                                              0x0064
+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
+#define mmDAGB0_WR_CGTT_CLK_CTRL                                                                       0x0065
+#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX                                                              1
+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL                                                                 0x0066
+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL                                                                 0x0067
+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0                                                                0x0068
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0                                                               0x0069
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1                                                                0x006a
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1                                                               0x006b
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2                                                                0x006c
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX                                                       1
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2                                                               0x006d
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX                                                      1
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3                                                                0x006e
+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX                                                       1
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3                                                               0x006f
+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX                                                      1
+#define mmDAGB0_WR_DATA_DAGB                                                                           0x0070
+#define mmDAGB0_WR_DATA_DAGB_BASE_IDX                                                                  1
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0                                                                0x0071
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX                                                       1
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0                                                               0x0072
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1                                                                0x0073
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX                                                       1
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1                                                               0x0074
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2                                                                0x0075
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX                                                       1
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2                                                               0x0076
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX                                                      1
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST3                                                                0x0077
+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX                                                       1
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3                                                               0x0078
+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX                                                      1
+#define mmDAGB0_WR_VC0_CNTL                                                                            0x0079
+#define mmDAGB0_WR_VC0_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_WR_VC1_CNTL                                                                            0x007a
+#define mmDAGB0_WR_VC1_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_WR_VC2_CNTL                                                                            0x007b
+#define mmDAGB0_WR_VC2_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_WR_VC3_CNTL                                                                            0x007c
+#define mmDAGB0_WR_VC3_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_WR_VC4_CNTL                                                                            0x007d
+#define mmDAGB0_WR_VC4_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_WR_VC5_CNTL                                                                            0x007e
+#define mmDAGB0_WR_VC5_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_WR_VC6_CNTL                                                                            0x007f
+#define mmDAGB0_WR_VC6_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_WR_VC7_CNTL                                                                            0x0080
+#define mmDAGB0_WR_VC7_CNTL_BASE_IDX                                                                   1
+#define mmDAGB0_WR_CNTL_MISC                                                                           0x0081
+#define mmDAGB0_WR_CNTL_MISC_BASE_IDX                                                                  1
+#define mmDAGB0_WR_TLB_CREDIT                                                                          0x0082
+#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX                                                                 1
+#define mmDAGB0_WR_DATA_CREDIT                                                                         0x0083
+#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX                                                                1
+#define mmDAGB0_WR_MISC_CREDIT                                                                         0x0084
+#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX                                                                1
+#define mmDAGB0_WR_OSD_CREDIT_CNTL1                                                                    0x0085
+#define mmDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX                                                           1
+#define mmDAGB0_WR_OSD_CREDIT_CNTL2                                                                    0x0086
+#define mmDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX                                                           1
+#define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL1                                                              0x0087
+#define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX                                                     1
+#define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL2                                                              0x0088
+#define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL2_BASE_IDX                                                     1
+#define mmDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1                                                            0x0089
+#define mmDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX                                                   1
+#define mmDAGB0_WRCLI_ASK_PENDING                                                                      0x008a
+#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX                                                             1
+#define mmDAGB0_WRCLI_GO_PENDING                                                                       0x008b
+#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX                                                              1
+#define mmDAGB0_WRCLI_GBLSEND_PENDING                                                                  0x008c
+#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX                                                         1
+#define mmDAGB0_WRCLI_TLB_PENDING                                                                      0x008d
+#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX                                                             1
+#define mmDAGB0_WRCLI_OARB_PENDING                                                                     0x008e
+#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX                                                            1
+#define mmDAGB0_WRCLI_OSD_PENDING                                                                      0x008f
+#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX                                                             1
+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING                                                                 0x0090
+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX                                                        1
+#define mmDAGB0_WRCLI_DBUS_GO_PENDING                                                                  0x0091
+#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX                                                         1
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE                                                               0x0092
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX                                                      1
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE                                                         0x0093
+#define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX                                                1
+#define mmDAGB0_DAGB_DLY                                                                               0x0094
+#define mmDAGB0_DAGB_DLY_BASE_IDX                                                                      1
+#define mmDAGB0_CNTL_MISC                                                                              0x0095
+#define mmDAGB0_CNTL_MISC_BASE_IDX                                                                     1
+#define mmDAGB0_CNTL_MISC2                                                                             0x0096
+#define mmDAGB0_CNTL_MISC2_BASE_IDX                                                                    1
+#define mmDAGB0_FIFO_EMPTY                                                                             0x0097
+#define mmDAGB0_FIFO_EMPTY_BASE_IDX                                                                    1
+#define mmDAGB0_FIFO_FULL                                                                              0x0098
+#define mmDAGB0_FIFO_FULL_BASE_IDX                                                                     1
+#define mmDAGB0_WR_CREDITS_FULL                                                                        0x0099
+#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX                                                               1
+#define mmDAGB0_RD_CREDITS_FULL                                                                        0x009a
+#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX                                                               1
+#define mmDAGB0_PERFCOUNTER_LO                                                                         0x009b
+#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX                                                                1
+#define mmDAGB0_PERFCOUNTER_HI                                                                         0x009c
+#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX                                                                1
+#define mmDAGB0_PERFCOUNTER0_CFG                                                                       0x009d
+#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX                                                              1
+#define mmDAGB0_PERFCOUNTER1_CFG                                                                       0x009e
+#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX                                                              1
+#define mmDAGB0_PERFCOUNTER2_CFG                                                                       0x009f
+#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX                                                              1
+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL                                                                  0x00a0
+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
+#define mmDAGB0_RESERVE0                                                                               0x00a1
+#define mmDAGB0_RESERVE0_BASE_IDX                                                                      1
+#define mmDAGB0_RESERVE1                                                                               0x00a2
+#define mmDAGB0_RESERVE1_BASE_IDX                                                                      1
+#define mmDAGB0_RESERVE2                                                                               0x00a3
+#define mmDAGB0_RESERVE2_BASE_IDX                                                                      1
+#define mmDAGB0_RESERVE3                                                                               0x00a4
+#define mmDAGB0_RESERVE3_BASE_IDX                                                                      1
+#define mmDAGB0_RESERVE4                                                                               0x00a5
+#define mmDAGB0_RESERVE4_BASE_IDX                                                                      1
+#define mmDAGB0_RESERVE5                                                                               0x00a6
+#define mmDAGB0_RESERVE5_BASE_IDX                                                                      1
+#define mmDAGB0_RESERVE6                                                                               0x00a7
+#define mmDAGB0_RESERVE6_BASE_IDX                                                                      1
+#define mmDAGB0_RESERVE7                                                                               0x00a8
+#define mmDAGB0_RESERVE7_BASE_IDX                                                                      1
+#define mmDAGB0_RESERVE8                                                                               0x00a9
+#define mmDAGB0_RESERVE8_BASE_IDX                                                                      1
+#define mmDAGB0_RESERVE9                                                                               0x00aa
+#define mmDAGB0_RESERVE9_BASE_IDX                                                                      1
+
+
+// addressBlock: mmhub_mmea_mmeadec0
+// base address: 0x68400
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0                                                                   0x0100
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                          1
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1                                                                   0x0101
+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                          1
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0                                                                   0x0102
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                          1
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1                                                                   0x0103
+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                          1
+#define mmMMEA0_DRAM_RD_GRP2VC_MAP                                                                     0x0104
+#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                            1
+#define mmMMEA0_DRAM_WR_GRP2VC_MAP                                                                     0x0105
+#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                            1
+#define mmMMEA0_DRAM_RD_LAZY                                                                           0x0106
+#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX                                                                  1
+#define mmMMEA0_DRAM_WR_LAZY                                                                           0x0107
+#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX                                                                  1
+#define mmMMEA0_DRAM_RD_CAM_CNTL                                                                       0x0108
+#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX                                                              1
+#define mmMMEA0_DRAM_WR_CAM_CNTL                                                                       0x0109
+#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX                                                              1
+#define mmMMEA0_DRAM_PAGE_BURST                                                                        0x010a
+#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX                                                               1
+#define mmMMEA0_DRAM_RD_PRI_AGE                                                                        0x010b
+#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX                                                               1
+#define mmMMEA0_DRAM_WR_PRI_AGE                                                                        0x010c
+#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX                                                               1
+#define mmMMEA0_DRAM_RD_PRI_QUEUING                                                                    0x010d
+#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX                                                           1
+#define mmMMEA0_DRAM_WR_PRI_QUEUING                                                                    0x010e
+#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX                                                           1
+#define mmMMEA0_DRAM_RD_PRI_FIXED                                                                      0x010f
+#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX                                                             1
+#define mmMMEA0_DRAM_WR_PRI_FIXED                                                                      0x0110
+#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX                                                             1
+#define mmMMEA0_DRAM_RD_PRI_URGENCY                                                                    0x0111
+#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX                                                           1
+#define mmMMEA0_DRAM_WR_PRI_URGENCY                                                                    0x0112
+#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX                                                           1
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1                                                                 0x0113
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                        1
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2                                                                 0x0114
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                        1
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3                                                                 0x0115
+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                        1
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1                                                                 0x0116
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                        1
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2                                                                 0x0117
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        1
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3                                                                 0x0118
+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                        1
+#define mmMMEA0_ADDRNORM_BASE_ADDR0                                                                    0x0134
+#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX                                                           1
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0                                                                   0x0135
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX                                                          1
+#define mmMMEA0_ADDRNORM_BASE_ADDR1                                                                    0x0136
+#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX                                                           1
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1                                                                   0x0137
+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX                                                          1
+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1                                                                  0x0138
+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX                                                         1
+#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL                                                                 0x0143
+#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX                                                        1
+#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG                                                           0x0145
+#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX                                                  1
+#define mmMMEA0_ADDRDEC_BANK_CFG                                                                       0x0147
+#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX                                                              1
+#define mmMMEA0_ADDRDEC_MISC_CFG                                                                       0x0148
+#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX                                                              1
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0                                                            0x0149
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX                                                   1
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1                                                            0x014a
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX                                                   1
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2                                                            0x014b
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX                                                   1
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3                                                            0x014c
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX                                                   1
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4                                                            0x014d
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX                                                   1
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5                                                            0x014e
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX                                                   1
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC                                                               0x014f
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX                                                      1
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2                                                              0x0150
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0                                                              0x0151
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1                                                              0x0152
+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE                                                             0x0153
+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX                                                    1
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0                                                         0x0154
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_BASE_IDX                                                1
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0                                                           0x0155
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_BASE_IDX                                                  1
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1                                                         0x0156
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_BASE_IDX                                                1
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1                                                           0x0157
+#define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_BASE_IDX                                                  1
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0                                                                 0x0167
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1                                                                 0x0168
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2                                                                 0x0169
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3                                                                 0x016a
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0                                                              0x016b
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1                                                              0x016c
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2                                                              0x016d
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3                                                              0x016e
+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01                                                                0x016f
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23                                                                0x0170
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01                                                             0x0171
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX                                                    1
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23                                                             0x0172
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX                                                    1
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01                                                                 0x0173
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23                                                                 0x0174
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01                                                                 0x0175
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23                                                                 0x0176
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01                                                                0x0177
+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23                                                                0x0178
+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01                                                               0x0179
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX                                                      1
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23                                                               0x017a
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX                                                      1
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01                                                               0x017b
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX                                                      1
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23                                                               0x017c
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX                                                      1
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01                                                                   0x017d
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX                                                          1
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23                                                                   0x017e
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX                                                          1
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS1                                                                    0x017f
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS1_BASE_IDX                                                           1
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS3                                                                    0x0180
+#define mmMMEA0_ADDRDEC0_RM_SEL_CS3_BASE_IDX                                                           1
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0                                                                 0x0181
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1                                                                 0x0182
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2                                                                 0x0183
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3                                                                 0x0184
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0                                                              0x0185
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1                                                              0x0186
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2                                                              0x0187
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3                                                              0x0188
+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01                                                                0x0189
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23                                                                0x018a
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01                                                             0x018b
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX                                                    1
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23                                                             0x018c
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX                                                    1
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01                                                                 0x018d
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23                                                                 0x018e
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01                                                                 0x018f
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23                                                                 0x0190
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01                                                                0x0191
+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23                                                                0x0192
+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01                                                               0x0193
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX                                                      1
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23                                                               0x0194
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX                                                      1
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01                                                               0x0195
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX                                                      1
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23                                                               0x0196
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX                                                      1
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01                                                                   0x0197
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX                                                          1
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23                                                                   0x0198
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX                                                          1
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS1                                                                    0x0199
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS1_BASE_IDX                                                           1
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS3                                                                    0x019a
+#define mmMMEA0_ADDRDEC1_RM_SEL_CS3_BASE_IDX                                                           1
+#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL                                                               0x01b5
+#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX                                                      1
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ0                                                             0x01b7
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ0_BASE_IDX                                                    1
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ1                                                             0x01b8
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ1_BASE_IDX                                                    1
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ2                                                             0x01b9
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ2_BASE_IDX                                                    1
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ3                                                             0x01ba
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ3_BASE_IDX                                                    1
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ4                                                             0x01bb
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ4_BASE_IDX                                                    1
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ5                                                             0x01bc
+#define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ5_BASE_IDX                                                    1
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS1                                                                 0x01c3
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS1_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS3                                                                 0x01c4
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS3_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS1                                                              0x01c5
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS1_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS3                                                              0x01c6
+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS3_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS1                                                                  0x01c7
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS1_BASE_IDX                                                         1
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS3                                                                  0x01c8
+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS3_BASE_IDX                                                         1
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS1                                                                  0x01c9
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS1_BASE_IDX                                                         1
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS3                                                                  0x01ca
+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS3_BASE_IDX                                                         1
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS1                                                                0x01cb
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS1_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS3                                                                0x01cc
+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS3_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS1                                                                0x01cd
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS1_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS3                                                                0x01ce
+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS3_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS1                                                                 0x01cf
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS1_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS3                                                                 0x01d0
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS3_BASE_IDX                                                        1
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS1                                                              0x01d1
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS1_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS3                                                              0x01d2
+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS3_BASE_IDX                                                     1
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS1                                                                  0x01d3
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS1_BASE_IDX                                                         1
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS3                                                                  0x01d4
+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS3_BASE_IDX                                                         1
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS1                                                                  0x01d5
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS1_BASE_IDX                                                         1
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS3                                                                  0x01d6
+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS3_BASE_IDX                                                         1
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS1                                                                0x01d7
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS1_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS3                                                                0x01d8
+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS3_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS1                                                                0x01d9
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS1_BASE_IDX                                                       1
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS3                                                                0x01da
+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS3_BASE_IDX                                                       1
+#define mmMMEA0_ADDRNORMDRAM_MASKING                                                                   0x01db
+#define mmMMEA0_ADDRNORMDRAM_MASKING_BASE_IDX                                                          1
+#define mmMMEA0_IO_RD_CLI2GRP_MAP0                                                                     0x01dd
+#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                            1
+#define mmMMEA0_IO_RD_CLI2GRP_MAP1                                                                     0x01de
+#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                            1
+#define mmMMEA0_IO_WR_CLI2GRP_MAP0                                                                     0x01df
+#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                            1
+#define mmMMEA0_IO_WR_CLI2GRP_MAP1                                                                     0x01e0
+#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                            1
+#define mmMMEA0_IO_RD_COMBINE_FLUSH                                                                    0x01e1
+#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX                                                           1
+#define mmMMEA0_IO_WR_COMBINE_FLUSH                                                                    0x01e2
+#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX                                                           1
+#define mmMMEA0_IO_GROUP_BURST                                                                         0x01e3
+#define mmMMEA0_IO_GROUP_BURST_BASE_IDX                                                                1
+#define mmMMEA0_IO_RD_PRI_AGE                                                                          0x01e4
+#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX                                                                 1
+#define mmMMEA0_IO_WR_PRI_AGE                                                                          0x01e5
+#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX                                                                 1
+#define mmMMEA0_IO_RD_PRI_QUEUING                                                                      0x01e6
+#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX                                                             1
+#define mmMMEA0_IO_WR_PRI_QUEUING                                                                      0x01e7
+#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX                                                             1
+#define mmMMEA0_IO_RD_PRI_FIXED                                                                        0x01e8
+#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX                                                               1
+#define mmMMEA0_IO_WR_PRI_FIXED                                                                        0x01e9
+#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX                                                               1
+#define mmMMEA0_IO_RD_PRI_URGENCY                                                                      0x01ea
+#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX                                                             1
+#define mmMMEA0_IO_WR_PRI_URGENCY                                                                      0x01eb
+#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX                                                             1
+#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING                                                              0x01ec
+#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                     1
+#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING                                                              0x01ed
+#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                     1
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1                                                                   0x01ee
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                          1
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2                                                                   0x01ef
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                          1
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3                                                                   0x01f0
+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                          1
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1                                                                   0x01f1
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                          1
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2                                                                   0x01f2
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                          1
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3                                                                   0x01f3
+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                          1
+#define mmMMEA0_SDP_ARB_DRAM                                                                           0x01f4
+#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX                                                                  1
+#define mmMMEA0_SDP_ARB_FINAL                                                                          0x01f6
+#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX                                                                 1
+#define mmMMEA0_SDP_DRAM_PRIORITY                                                                      0x01f7
+#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX                                                             1
+#define mmMMEA0_SDP_IO_PRIORITY                                                                        0x01f9
+#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX                                                               1
+#define mmMMEA0_SDP_CREDITS                                                                            0x01fa
+#define mmMMEA0_SDP_CREDITS_BASE_IDX                                                                   1
+#define mmMMEA0_SDP_TAG_RESERVE0                                                                       0x01fb
+#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX                                                              1
+#define mmMMEA0_SDP_TAG_RESERVE1                                                                       0x01fc
+#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX                                                              1
+#define mmMMEA0_SDP_VCC_RESERVE0                                                                       0x01fd
+#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX                                                              1
+#define mmMMEA0_SDP_VCC_RESERVE1                                                                       0x01fe
+#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX                                                              1
+#define mmMMEA0_SDP_VCD_RESERVE0                                                                       0x01ff
+#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX                                                              1
+#define mmMMEA0_SDP_VCD_RESERVE1                                                                       0x0200
+#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX                                                              1
+#define mmMMEA0_SDP_REQ_CNTL                                                                           0x0201
+#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX                                                                  1
+#define mmMMEA0_MISC                                                                                   0x0202
+#define mmMMEA0_MISC_BASE_IDX                                                                          1
+#define mmMMEA0_LATENCY_SAMPLING                                                                       0x0203
+#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX                                                              1
+#define mmMMEA0_PERFCOUNTER_LO                                                                         0x0204
+#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX                                                                1
+#define mmMMEA0_PERFCOUNTER_HI                                                                         0x0205
+#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX                                                                1
+#define mmMMEA0_PERFCOUNTER0_CFG                                                                       0x0206
+#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX                                                              1
+#define mmMMEA0_PERFCOUNTER1_CFG                                                                       0x0207
+#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX                                                              1
+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL                                                                  0x0208
+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
+#define mmMMEA0_EDC_CNT                                                                                0x020f
+#define mmMMEA0_EDC_CNT_BASE_IDX                                                                       1
+#define mmMMEA0_EDC_CNT2                                                                               0x0210
+#define mmMMEA0_EDC_CNT2_BASE_IDX                                                                      1
+#define mmMMEA0_DSM_CNTL                                                                               0x0211
+#define mmMMEA0_DSM_CNTL_BASE_IDX                                                                      1
+#define mmMMEA0_DSM_CNTLA                                                                              0x0212
+#define mmMMEA0_DSM_CNTLA_BASE_IDX                                                                     1
+#define mmMMEA0_DSM_CNTLB                                                                              0x0213
+#define mmMMEA0_DSM_CNTLB_BASE_IDX                                                                     1
+#define mmMMEA0_DSM_CNTL2                                                                              0x0214
+#define mmMMEA0_DSM_CNTL2_BASE_IDX                                                                     1
+#define mmMMEA0_DSM_CNTL2A                                                                             0x0215
+#define mmMMEA0_DSM_CNTL2A_BASE_IDX                                                                    1
+#define mmMMEA0_DSM_CNTL2B                                                                             0x0216
+#define mmMMEA0_DSM_CNTL2B_BASE_IDX                                                                    1
+#define mmMMEA0_CGTT_CLK_CTRL                                                                          0x0218
+#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX                                                                 1
+#define mmMMEA0_EDC_MODE                                                                               0x0219
+#define mmMMEA0_EDC_MODE_BASE_IDX                                                                      1
+#define mmMMEA0_ERR_STATUS                                                                             0x021a
+#define mmMMEA0_ERR_STATUS_BASE_IDX                                                                    1
+#define mmMMEA0_MISC2                                                                                  0x021b
+#define mmMMEA0_MISC2_BASE_IDX                                                                         1
+#define mmMMEA0_ADDRDEC_SELECT                                                                         0x021c
+#define mmMMEA0_ADDRDEC_SELECT_BASE_IDX                                                                1
+#define mmMMEA0_EDC_CNT3                                                                               0x021d
+#define mmMMEA0_EDC_CNT3_BASE_IDX                                                                      1
+#define mmMMEA0_SDP_PRIORITY_OVERRIDE                                                                  0x021e
+#define mmMMEA0_SDP_PRIORITY_OVERRIDE_BASE_IDX                                                         1
+#define mmMMEA0_MISC_AON                                                                               0x021f
+#define mmMMEA0_MISC_AON_BASE_IDX                                                                      1
+
+
+// addressBlock: mmhub_pctldec
+// base address: 0x68e00
+#define mmPCTL_CTRL                                                                                    0x0380
+#define mmPCTL_CTRL_BASE_IDX                                                                           1
+#define mmPCTL_MMHUB_DEEPSLEEP_IB                                                                      0x0381
+#define mmPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX                                                             1
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE                                                                0x0382
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX                                                       1
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB                                                             0x0383
+#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX                                                    1
+#define mmPCTL_PG_IGNORE_DEEPSLEEP                                                                     0x0384
+#define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX                                                            1
+#define mmPCTL_PG_IGNORE_DEEPSLEEP_IB                                                                  0x0385
+#define mmPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX                                                         1
+#define mmPCTL_SLICE0_CFG_DAGB_WRBUSY                                                                  0x0386
+#define mmPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX                                                         1
+#define mmPCTL_SLICE0_CFG_DAGB_RDBUSY                                                                  0x0387
+#define mmPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX                                                         1
+#define mmPCTL_SLICE0_CFG_DS_ALLOW                                                                     0x0388
+#define mmPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX                                                            1
+#define mmPCTL_SLICE0_CFG_DS_ALLOW_IB                                                                  0x0389
+#define mmPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX                                                         1
+#define mmPCTL_SLICE1_CFG_DAGB_WRBUSY                                                                  0x038a
+#define mmPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX                                                         1
+#define mmPCTL_SLICE1_CFG_DAGB_RDBUSY                                                                  0x038b
+#define mmPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX                                                         1
+#define mmPCTL_SLICE1_CFG_DS_ALLOW                                                                     0x038c
+#define mmPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX                                                            1
+#define mmPCTL_SLICE1_CFG_DS_ALLOW_IB                                                                  0x038d
+#define mmPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX                                                         1
+#define mmPCTL_UTCL2_MISC                                                                              0x038e
+#define mmPCTL_UTCL2_MISC_BASE_IDX                                                                     1
+#define mmPCTL_SLICE0_MISC                                                                             0x038f
+#define mmPCTL_SLICE0_MISC_BASE_IDX                                                                    1
+#define mmPCTL_SLICE1_MISC                                                                             0x0390
+#define mmPCTL_SLICE1_MISC_BASE_IDX                                                                    1
+#define mmPCTL_RENG_CTRL                                                                               0x0391
+#define mmPCTL_RENG_CTRL_BASE_IDX                                                                      1
+#define mmPCTL_UTCL2_RENG_EXECUTE                                                                      0x0392
+#define mmPCTL_UTCL2_RENG_EXECUTE_BASE_IDX                                                             1
+#define mmPCTL_SLICE0_RENG_EXECUTE                                                                     0x0393
+#define mmPCTL_SLICE0_RENG_EXECUTE_BASE_IDX                                                            1
+#define mmPCTL_SLICE1_RENG_EXECUTE                                                                     0x0394
+#define mmPCTL_SLICE1_RENG_EXECUTE_BASE_IDX                                                            1
+#define mmPCTL_UTCL2_RENG_RAM_INDEX                                                                    0x0395
+#define mmPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX                                                           1
+#define mmPCTL_UTCL2_RENG_RAM_DATA                                                                     0x0396
+#define mmPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX                                                            1
+#define mmPCTL_SLICE0_RENG_RAM_INDEX                                                                   0x0397
+#define mmPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX                                                          1
+#define mmPCTL_SLICE0_RENG_RAM_DATA                                                                    0x0398
+#define mmPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX                                                           1
+#define mmPCTL_SLICE1_RENG_RAM_INDEX                                                                   0x0399
+#define mmPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX                                                          1
+#define mmPCTL_SLICE1_RENG_RAM_DATA                                                                    0x039a
+#define mmPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX                                                           1
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0                                                       0x039b
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                              1
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1                                                       0x039c
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                              1
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2                                                       0x039d
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                              1
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3                                                       0x039e
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                              1
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4                                                       0x039f
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                              1
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0                                                    0x03a0
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                           1
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1                                                    0x03a1
+#define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                           1
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0                                                      0x03a2
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                             1
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1                                                      0x03a3
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                             1
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2                                                      0x03a4
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                             1
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3                                                      0x03a5
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                             1
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4                                                      0x03a6
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                             1
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0                                                   0x03a7
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                          1
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1                                                   0x03a8
+#define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                          1
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0                                                      0x03a9
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                             1
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1                                                      0x03aa
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                             1
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2                                                      0x03ab
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                             1
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3                                                      0x03ac
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                             1
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4                                                      0x03ad
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                             1
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0                                                   0x03ae
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                          1
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1                                                   0x03af
+#define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                          1
+#define mmPCTL_STATUS                                                                                  0x03b0
+#define mmPCTL_STATUS_BASE_IDX                                                                         1
+#define mmPCTL_PERFCOUNTER_LO                                                                          0x03b1
+#define mmPCTL_PERFCOUNTER_LO_BASE_IDX                                                                 1
+#define mmPCTL_PERFCOUNTER_HI                                                                          0x03b2
+#define mmPCTL_PERFCOUNTER_HI_BASE_IDX                                                                 1
+#define mmPCTL_PERFCOUNTER0_CFG                                                                        0x03b3
+#define mmPCTL_PERFCOUNTER0_CFG_BASE_IDX                                                               1
+#define mmPCTL_PERFCOUNTER1_CFG                                                                        0x03b4
+#define mmPCTL_PERFCOUNTER1_CFG_BASE_IDX                                                               1
+#define mmPCTL_PERFCOUNTER_RSLT_CNTL                                                                   0x03b5
+#define mmPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                          1
+#define mmPCTL_RESERVED_0                                                                              0x03b6
+#define mmPCTL_RESERVED_0_BASE_IDX                                                                     1
+#define mmPCTL_RESERVED_1                                                                              0x03b7
+#define mmPCTL_RESERVED_1_BASE_IDX                                                                     1
+#define mmPCTL_RESERVED_2                                                                              0x03b8
+#define mmPCTL_RESERVED_2_BASE_IDX                                                                     1
+#define mmPCTL_RESERVED_3                                                                              0x03b9
+#define mmPCTL_RESERVED_3_BASE_IDX                                                                     1
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pfdec
+// base address: 0x69600
+#define mmMMMC_VM_MX_L1_TLB0_STATUS                                                                    0x0588
+#define mmMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLB1_STATUS                                                                    0x0589
+#define mmMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLB2_STATUS                                                                    0x058a
+#define mmMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLB3_STATUS                                                                    0x058b
+#define mmMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLB4_STATUS                                                                    0x058c
+#define mmMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLB5_STATUS                                                                    0x058d
+#define mmMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLB6_STATUS                                                                    0x058e
+#define mmMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLB7_STATUS                                                                    0x058f
+#define mmMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX                                                           1
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pldec
+// base address: 0x69670
+#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG                                                               0x059c
+#define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX                                                      1
+#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG                                                               0x059d
+#define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX                                                      1
+#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG                                                               0x059e
+#define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX                                                      1
+#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG                                                               0x059f
+#define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX                                                      1
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL                                                          0x05a0
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                 1
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1prdec
+// base address: 0x69690
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO                                                                 0x05a4
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX                                                        1
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI                                                                 0x05a5
+#define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX                                                        1
+
+
+// addressBlock: mmhub_l1tlb_mmvmtlspfdec
+// base address: 0x696c0
+#define mmMMMC_VM_MX_L1_TLS0_CNTL                                                                      0x05b0
+#define mmMMMC_VM_MX_L1_TLS0_CNTL_BASE_IDX                                                             1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL0                                                                     0x05b1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL0_BASE_IDX                                                            1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL1                                                                     0x05b2
+#define mmMMMC_VM_MX_L1_TLS0_CNTL1_BASE_IDX                                                            1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL2                                                                     0x05b3
+#define mmMMMC_VM_MX_L1_TLS0_CNTL2_BASE_IDX                                                            1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL3                                                                     0x05b4
+#define mmMMMC_VM_MX_L1_TLS0_CNTL3_BASE_IDX                                                            1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL4                                                                     0x05b5
+#define mmMMMC_VM_MX_L1_TLS0_CNTL4_BASE_IDX                                                            1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL5                                                                     0x05b6
+#define mmMMMC_VM_MX_L1_TLS0_CNTL5_BASE_IDX                                                            1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL6                                                                     0x05b7
+#define mmMMMC_VM_MX_L1_TLS0_CNTL6_BASE_IDX                                                            1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL7                                                                     0x05b8
+#define mmMMMC_VM_MX_L1_TLS0_CNTL7_BASE_IDX                                                            1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL8                                                                     0x05b9
+#define mmMMMC_VM_MX_L1_TLS0_CNTL8_BASE_IDX                                                            1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL9                                                                     0x05ba
+#define mmMMMC_VM_MX_L1_TLS0_CNTL9_BASE_IDX                                                            1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL10                                                                    0x05bb
+#define mmMMMC_VM_MX_L1_TLS0_CNTL10_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL11                                                                    0x05bc
+#define mmMMMC_VM_MX_L1_TLS0_CNTL11_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL12                                                                    0x05bd
+#define mmMMMC_VM_MX_L1_TLS0_CNTL12_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL13                                                                    0x05be
+#define mmMMMC_VM_MX_L1_TLS0_CNTL13_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL14                                                                    0x05bf
+#define mmMMMC_VM_MX_L1_TLS0_CNTL14_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL15                                                                    0x05c0
+#define mmMMMC_VM_MX_L1_TLS0_CNTL15_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL16                                                                    0x05c1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL16_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL17                                                                    0x05c2
+#define mmMMMC_VM_MX_L1_TLS0_CNTL17_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL18                                                                    0x05c3
+#define mmMMMC_VM_MX_L1_TLS0_CNTL18_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL19                                                                    0x05c4
+#define mmMMMC_VM_MX_L1_TLS0_CNTL19_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL20                                                                    0x05c5
+#define mmMMMC_VM_MX_L1_TLS0_CNTL20_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL21                                                                    0x05c6
+#define mmMMMC_VM_MX_L1_TLS0_CNTL21_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL22                                                                    0x05c7
+#define mmMMMC_VM_MX_L1_TLS0_CNTL22_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL23                                                                    0x05c8
+#define mmMMMC_VM_MX_L1_TLS0_CNTL23_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL24                                                                    0x05c9
+#define mmMMMC_VM_MX_L1_TLS0_CNTL24_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL25                                                                    0x05ca
+#define mmMMMC_VM_MX_L1_TLS0_CNTL25_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL26                                                                    0x05cb
+#define mmMMMC_VM_MX_L1_TLS0_CNTL26_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL27                                                                    0x05cc
+#define mmMMMC_VM_MX_L1_TLS0_CNTL27_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL28                                                                    0x05cd
+#define mmMMMC_VM_MX_L1_TLS0_CNTL28_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL29                                                                    0x05ce
+#define mmMMMC_VM_MX_L1_TLS0_CNTL29_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL30                                                                    0x05cf
+#define mmMMMC_VM_MX_L1_TLS0_CNTL30_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL31                                                                    0x05d0
+#define mmMMMC_VM_MX_L1_TLS0_CNTL31_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL32                                                                    0x05d1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL32_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL33                                                                    0x05d2
+#define mmMMMC_VM_MX_L1_TLS0_CNTL33_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL34                                                                    0x05d3
+#define mmMMMC_VM_MX_L1_TLS0_CNTL34_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL35                                                                    0x05d4
+#define mmMMMC_VM_MX_L1_TLS0_CNTL35_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL36                                                                    0x05d5
+#define mmMMMC_VM_MX_L1_TLS0_CNTL36_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_CNTL37                                                                    0x05d6
+#define mmMMMC_VM_MX_L1_TLS0_CNTL37_BASE_IDX                                                           1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32                                                          0x05d7
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32                                                          0x05d8
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32                                                          0x05d9
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32                                                          0x05da
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32                                                          0x05db
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32                                                          0x05dc
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32                                                          0x05dd
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32                                                          0x05de
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32                                                          0x05df
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32                                                          0x05e0
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32                                                          0x05e1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32                                                          0x05e2
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32                                                          0x05e3
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32                                                          0x05e4
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32                                                          0x05e5
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32                                                          0x05e6
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32                                                          0x05e7
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32                                                          0x05e8
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32                                                          0x05e9
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32                                                          0x05ea
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32_BASE_IDX                                                 1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32                                                         0x05eb
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32                                                         0x05ec
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32                                                         0x05ed
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32                                                         0x05ee
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32                                                         0x05ef
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32                                                         0x05f0
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32                                                         0x05f1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32                                                         0x05f2
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32                                                         0x05f3
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32                                                         0x05f4
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32                                                         0x05f5
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32                                                         0x05f6
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32                                                         0x05f7
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32                                                         0x05f8
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32                                                         0x05f9
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32                                                         0x05fa
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32                                                         0x05fb
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32                                                         0x05fc
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32                                                         0x05fd
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32                                                         0x05fe
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32                                                         0x05ff
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32                                                         0x0600
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32                                                         0x0601
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32                                                         0x0602
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32                                                         0x0603
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32                                                         0x0604
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32                                                         0x0605
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32                                                         0x0606
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32                                                         0x0607
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32                                                         0x0608
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32                                                         0x0609
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32                                                         0x060a
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32                                                         0x060b
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32                                                         0x060c
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32                                                         0x060d
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32                                                         0x060e
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32                                                         0x060f
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32                                                         0x0610
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32                                                         0x0611
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32                                                         0x0612
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32                                                         0x0613
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32                                                         0x0614
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32                                                         0x0615
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32                                                         0x0616
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32                                                         0x0617
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32                                                         0x0618
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32                                                         0x0619
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32                                                         0x061a
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32                                                         0x061b
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32                                                         0x061c
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32                                                         0x061d
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32                                                         0x061e
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32                                                         0x061f
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32                                                         0x0620
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32                                                         0x0621
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32                                                         0x0622
+#define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32_BASE_IDX                                                1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32                                                            0x0623
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32                                                            0x0624
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32                                                            0x0625
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32                                                            0x0626
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32                                                            0x0627
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32                                                            0x0628
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32                                                            0x0629
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32                                                            0x062a
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32                                                            0x062b
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32                                                            0x062c
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32                                                            0x062d
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32                                                            0x062e
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32                                                            0x062f
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32                                                            0x0630
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32                                                            0x0631
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32                                                            0x0632
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32                                                            0x0633
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32                                                            0x0634
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32                                                            0x0635
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32                                                            0x0636
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32                                                           0x0637
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32                                                           0x0638
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32                                                           0x0639
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32                                                           0x063a
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32                                                           0x063b
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32                                                           0x063c
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32                                                           0x063d
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32                                                           0x063e
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32                                                           0x063f
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32                                                           0x0640
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32                                                           0x0641
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32                                                           0x0642
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32                                                           0x0643
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32                                                           0x0644
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32                                                           0x0645
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32                                                           0x0646
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32                                                           0x0647
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32                                                           0x0648
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32                                                           0x0649
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32                                                           0x064a
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32                                                           0x064b
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32                                                           0x064c
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32                                                           0x064d
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32                                                           0x064e
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32                                                           0x064f
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32                                                           0x0650
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32                                                           0x0651
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32                                                           0x0652
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32                                                           0x0653
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32                                                           0x0654
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32                                                           0x0655
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32                                                           0x0656
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32                                                           0x0657
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32                                                           0x0658
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32                                                           0x0659
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32                                                           0x065a
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32                                                           0x065b
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32                                                           0x065c
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32                                                           0x065d
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32                                                           0x065e
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32                                                           0x065f
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32                                                           0x0660
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32                                                           0x0661
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32                                                           0x0662
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32                                                           0x0663
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32                                                           0x0664
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32                                                           0x0665
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32                                                           0x0666
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32                                                           0x0667
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32                                                           0x0668
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32                                                           0x0669
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32                                                           0x066a
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32                                                           0x066b
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32                                                           0x066c
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32                                                           0x066d
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32                                                           0x066e
+#define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32_BASE_IDX                                                  1
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32                                                    0x066f
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32_BASE_IDX                                           1
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32                                                    0x0670
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32_BASE_IDX                                           1
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32                                           0x0671
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32_BASE_IDX                                  1
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32                                           0x0672
+#define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32_BASE_IDX                                  1
+#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS                                                   0x0673
+#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_BASE_IDX                                          1
+#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32                                                0x0674
+#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_BASE_IDX                                       1
+#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32                                                0x0675
+#define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_BASE_IDX                                       1
+#define mmMMVM_L2_SAW_CNTL                                                                             0x0676
+#define mmMMVM_L2_SAW_CNTL_BASE_IDX                                                                    1
+#define mmMMVM_L2_SAW_CNTL2                                                                            0x0677
+#define mmMMVM_L2_SAW_CNTL2_BASE_IDX                                                                   1
+#define mmMMVM_L2_SAW_CNTL3                                                                            0x0678
+#define mmMMVM_L2_SAW_CNTL3_BASE_IDX                                                                   1
+#define mmMMVM_L2_SAW_CNTL4                                                                            0x0679
+#define mmMMVM_L2_SAW_CNTL4_BASE_IDX                                                                   1
+#define mmMMVM_L2_SAW_CONTEXT0_CNTL                                                                    0x067a
+#define mmMMVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX                                                           1
+#define mmMMVM_L2_SAW_CONTEXT0_CNTL2                                                                   0x067b
+#define mmMMVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX                                                          1
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                               0x067c
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                               0x067d
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                              0x067e
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                              0x067f
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                0x0680
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                0x0681
+#define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
+#define mmMMVM_L2_SAW_CONTEXTS_DISABLE                                                                 0x0682
+#define mmMMVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX                                                        1
+#define mmMMVM_L2_SAW_PIPES_BUSY_LO32                                                                  0x0683
+#define mmMMVM_L2_SAW_PIPES_BUSY_LO32_BASE_IDX                                                         1
+#define mmMMVM_L2_SAW_PIPES_BUSY_HI32                                                                  0x0684
+#define mmMMVM_L2_SAW_PIPES_BUSY_HI32_BASE_IDX                                                         1
+#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS                                                        0x0685
+#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS_BASE_IDX                                               1
+#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32                                                   0x0686
+#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32_BASE_IDX                                          1
+#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32                                                   0x0687
+#define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32_BASE_IDX                                          1
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2dec
+// base address: 0x69b00
+#define mmMM_ATC_L2_CNTL                                                                               0x06c0
+#define mmMM_ATC_L2_CNTL_BASE_IDX                                                                      1
+#define mmMM_ATC_L2_CNTL2                                                                              0x06c1
+#define mmMM_ATC_L2_CNTL2_BASE_IDX                                                                     1
+#define mmMM_ATC_L2_CACHE_DATA0                                                                        0x06c4
+#define mmMM_ATC_L2_CACHE_DATA0_BASE_IDX                                                               1
+#define mmMM_ATC_L2_CACHE_DATA1                                                                        0x06c5
+#define mmMM_ATC_L2_CACHE_DATA1_BASE_IDX                                                               1
+#define mmMM_ATC_L2_CACHE_DATA2                                                                        0x06c6
+#define mmMM_ATC_L2_CACHE_DATA2_BASE_IDX                                                               1
+#define mmMM_ATC_L2_CNTL3                                                                              0x06c7
+#define mmMM_ATC_L2_CNTL3_BASE_IDX                                                                     1
+#define mmMM_ATC_L2_CNTL4                                                                              0x06c8
+#define mmMM_ATC_L2_CNTL4_BASE_IDX                                                                     1
+#define mmMM_ATC_L2_CNTL5                                                                              0x06c9
+#define mmMM_ATC_L2_CNTL5_BASE_IDX                                                                     1
+#define mmMM_ATC_L2_MM_GROUP_RT_CLASSES                                                                0x06ca
+#define mmMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                       1
+#define mmMM_ATC_L2_STATUS                                                                             0x06cb
+#define mmMM_ATC_L2_STATUS_BASE_IDX                                                                    1
+#define mmMM_ATC_L2_STATUS2                                                                            0x06cc
+#define mmMM_ATC_L2_STATUS2_BASE_IDX                                                                   1
+#define mmMM_ATC_L2_MISC_CG                                                                            0x06cd
+#define mmMM_ATC_L2_MISC_CG_BASE_IDX                                                                   1
+#define mmMM_ATC_L2_MEM_POWER_LS                                                                       0x06ce
+#define mmMM_ATC_L2_MEM_POWER_LS_BASE_IDX                                                              1
+#define mmMM_ATC_L2_CGTT_CLK_CTRL                                                                      0x06cf
+#define mmMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX                                                             1
+#define mmMM_ATC_L2_SDPPORT_CTRL                                                                       0x06d2
+#define mmMM_ATC_L2_SDPPORT_CTRL_BASE_IDX                                                              1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pfdec
+// base address: 0x69c00
+#define mmMMVM_L2_CNTL                                                                                 0x0700
+#define mmMMVM_L2_CNTL_BASE_IDX                                                                        1
+#define mmMMVM_L2_CNTL2                                                                                0x0701
+#define mmMMVM_L2_CNTL2_BASE_IDX                                                                       1
+#define mmMMVM_L2_CNTL3                                                                                0x0702
+#define mmMMVM_L2_CNTL3_BASE_IDX                                                                       1
+#define mmMMVM_L2_STATUS                                                                               0x0703
+#define mmMMVM_L2_STATUS_BASE_IDX                                                                      1
+#define mmMMVM_DUMMY_PAGE_FAULT_CNTL                                                                   0x0704
+#define mmMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX                                                          1
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32                                                              0x0705
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX                                                     1
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32                                                              0x0706
+#define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX                                                     1
+#define mmMMVM_INVALIDATE_CNTL                                                                         0x0707
+#define mmMMVM_INVALIDATE_CNTL_BASE_IDX                                                                1
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL                                                                0x0708
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX                                                       1
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL2                                                               0x0709
+#define mmMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX                                                      1
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3                                                            0x070a
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX                                                   1
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4                                                            0x070b
+#define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX                                                   1
+#define mmMMVM_L2_PROTECTION_FAULT_STATUS                                                              0x070c
+#define mmMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX                                                     1
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32                                                           0x070d
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX                                                  1
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32                                                           0x070e
+#define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX                                                  1
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32                                                   0x070f
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX                                          1
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32                                                   0x0710
+#define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX                                          1
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32                                             0x0712
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX                                    1
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32                                             0x0713
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX                                    1
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32                                            0x0714
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX                                   1
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32                                            0x0715
+#define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX                                   1
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32                                                0x0716
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX                                       1
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32                                                0x0717
+#define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX                                       1
+#define mmMMVM_L2_CNTL4                                                                                0x0718
+#define mmMMVM_L2_CNTL4_BASE_IDX                                                                       1
+#define mmMMVM_L2_MM_GROUP_RT_CLASSES                                                                  0x0719
+#define mmMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                         1
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID                                                             0x071a
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX                                                    1
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2                                                            0x071b
+#define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX                                                   1
+#define mmMMVM_L2_CACHE_PARITY_CNTL                                                                    0x071c
+#define mmMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX                                                           1
+#define mmMMVM_L2_IH_LOG_CNTL                                                                          0x071d
+#define mmMMVM_L2_IH_LOG_CNTL_BASE_IDX                                                                 1
+#define mmMMVM_L2_IH_LOG_BUSY                                                                          0x071e
+#define mmMMVM_L2_IH_LOG_BUSY_BASE_IDX                                                                 1
+#define mmMMVM_L2_CGTT_CLK_CTRL                                                                        0x071f
+#define mmMMVM_L2_CGTT_CLK_CTRL_BASE_IDX                                                               1
+#define mmMMVM_L2_CNTL5                                                                                0x0720
+#define mmMMVM_L2_CNTL5_BASE_IDX                                                                       1
+#define mmMMVM_L2_GCR_CNTL                                                                             0x0721
+#define mmMMVM_L2_GCR_CNTL_BASE_IDX                                                                    1
+#define mmMMVM_L2_CGTT_BUSY_CTRL                                                                       0x0722
+#define mmMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX                                                              1
+#define mmMMVM_L2_PTE_CACHE_DUMP_CNTL                                                                  0x0723
+#define mmMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX                                                         1
+#define mmMMVM_L2_PTE_CACHE_DUMP_READ                                                                  0x0724
+#define mmMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX                                                         1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2vcdec
+// base address: 0x69d00
+#define mmMMVM_CONTEXT0_CNTL                                                                           0x0740
+#define mmMMVM_CONTEXT0_CNTL_BASE_IDX                                                                  1
+#define mmMMVM_CONTEXT1_CNTL                                                                           0x0741
+#define mmMMVM_CONTEXT1_CNTL_BASE_IDX                                                                  1
+#define mmMMVM_CONTEXT2_CNTL                                                                           0x0742
+#define mmMMVM_CONTEXT2_CNTL_BASE_IDX                                                                  1
+#define mmMMVM_CONTEXT3_CNTL                                                                           0x0743
+#define mmMMVM_CONTEXT3_CNTL_BASE_IDX                                                                  1
+#define mmMMVM_CONTEXT4_CNTL                                                                           0x0744
+#define mmMMVM_CONTEXT4_CNTL_BASE_IDX                                                                  1
+#define mmMMVM_CONTEXT5_CNTL                                                                           0x0745
+#define mmMMVM_CONTEXT5_CNTL_BASE_IDX                                                                  1
+#define mmMMVM_CONTEXT6_CNTL                                                                           0x0746
+#define mmMMVM_CONTEXT6_CNTL_BASE_IDX                                                                  1
+#define mmMMVM_CONTEXT7_CNTL                                                                           0x0747
+#define mmMMVM_CONTEXT7_CNTL_BASE_IDX                                                                  1
+#define mmMMVM_CONTEXT8_CNTL                                                                           0x0748
+#define mmMMVM_CONTEXT8_CNTL_BASE_IDX                                                                  1
+#define mmMMVM_CONTEXT9_CNTL                                                                           0x0749
+#define mmMMVM_CONTEXT9_CNTL_BASE_IDX                                                                  1
+#define mmMMVM_CONTEXT10_CNTL                                                                          0x074a
+#define mmMMVM_CONTEXT10_CNTL_BASE_IDX                                                                 1
+#define mmMMVM_CONTEXT11_CNTL                                                                          0x074b
+#define mmMMVM_CONTEXT11_CNTL_BASE_IDX                                                                 1
+#define mmMMVM_CONTEXT12_CNTL                                                                          0x074c
+#define mmMMVM_CONTEXT12_CNTL_BASE_IDX                                                                 1
+#define mmMMVM_CONTEXT13_CNTL                                                                          0x074d
+#define mmMMVM_CONTEXT13_CNTL_BASE_IDX                                                                 1
+#define mmMMVM_CONTEXT14_CNTL                                                                          0x074e
+#define mmMMVM_CONTEXT14_CNTL_BASE_IDX                                                                 1
+#define mmMMVM_CONTEXT15_CNTL                                                                          0x074f
+#define mmMMVM_CONTEXT15_CNTL_BASE_IDX                                                                 1
+#define mmMMVM_CONTEXTS_DISABLE                                                                        0x0750
+#define mmMMVM_CONTEXTS_DISABLE_BASE_IDX                                                               1
+#define mmMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                                    0x0751
+#define mmMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                           1
+#define mmMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0752
+#define mmMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define mmMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0753
+#define mmMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define mmMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0754
+#define mmMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define mmMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0755
+#define mmMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define mmMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0756
+#define mmMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define mmMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0757
+#define mmMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define mmMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0758
+#define mmMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define mmMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x0759
+#define mmMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define mmMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x075a
+#define mmMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define mmMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x075b
+#define mmMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  1
+#define mmMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x075c
+#define mmMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+#define mmMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x075d
+#define mmMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+#define mmMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x075e
+#define mmMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+#define mmMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x075f
+#define mmMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+#define mmMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x0760
+#define mmMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+#define mmMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x0761
+#define mmMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pldec
+// base address: 0x6a090
+#define mmMMMC_VM_L2_PERFCOUNTER0_CFG                                                                  0x0824
+#define mmMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX                                                         1
+#define mmMMMC_VM_L2_PERFCOUNTER1_CFG                                                                  0x0825
+#define mmMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX                                                         1
+#define mmMMMC_VM_L2_PERFCOUNTER2_CFG                                                                  0x0826
+#define mmMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX                                                         1
+#define mmMMMC_VM_L2_PERFCOUNTER3_CFG                                                                  0x0827
+#define mmMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX                                                         1
+#define mmMMMC_VM_L2_PERFCOUNTER4_CFG                                                                  0x0828
+#define mmMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX                                                         1
+#define mmMMMC_VM_L2_PERFCOUNTER5_CFG                                                                  0x0829
+#define mmMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX                                                         1
+#define mmMMMC_VM_L2_PERFCOUNTER6_CFG                                                                  0x082a
+#define mmMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX                                                         1
+#define mmMMMC_VM_L2_PERFCOUNTER7_CFG                                                                  0x082b
+#define mmMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX                                                         1
+#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL                                                             0x082c
+#define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                    1
+#define mmMMUTCL2_PERFCOUNTER0_CFG                                                                     0x082d
+#define mmMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX                                                            1
+#define mmMMUTCL2_PERFCOUNTER1_CFG                                                                     0x082e
+#define mmMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX                                                            1
+#define mmMMUTCL2_PERFCOUNTER2_CFG                                                                     0x082f
+#define mmMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX                                                            1
+#define mmMMUTCL2_PERFCOUNTER3_CFG                                                                     0x0830
+#define mmMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX                                                            1
+#define mmMMUTCL2_PERFCOUNTER_RSLT_CNTL                                                                0x0831
+#define mmMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                       1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2prdec
+// base address: 0x6a0e0
+#define mmMMMC_VM_L2_PERFCOUNTER_LO                                                                    0x0838
+#define mmMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX                                                           1
+#define mmMMMC_VM_L2_PERFCOUNTER_HI                                                                    0x0839
+#define mmMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX                                                           1
+#define mmMMUTCL2_PERFCOUNTER_LO                                                                       0x083a
+#define mmMMUTCL2_PERFCOUNTER_LO_BASE_IDX                                                              1
+#define mmMMUTCL2_PERFCOUNTER_HI                                                                       0x083b
+#define mmMMUTCL2_PERFCOUNTER_HI_BASE_IDX                                                              1
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
+// base address: 0x6a130
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF0                                                                   0x084c
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX                                                          1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF1                                                                   0x084d
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX                                                          1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF2                                                                   0x084e
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX                                                          1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF3                                                                   0x084f
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX                                                          1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF4                                                                   0x0850
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX                                                          1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF5                                                                   0x0851
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX                                                          1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF6                                                                   0x0852
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX                                                          1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF7                                                                   0x0853
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX                                                          1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF8                                                                   0x0854
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX                                                          1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF9                                                                   0x0855
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX                                                          1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF10                                                                  0x0856
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF11                                                                  0x0857
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF12                                                                  0x0858
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF13                                                                  0x0859
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF14                                                                  0x085a
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF15                                                                  0x085b
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF16                                                                  0x085c
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF17                                                                  0x085d
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF18                                                                  0x085e
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF19                                                                  0x085f
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF20                                                                  0x0860
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF21                                                                  0x0861
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF22                                                                  0x0862
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF23                                                                  0x0863
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF24                                                                  0x0864
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF25                                                                  0x0865
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF26                                                                  0x0866
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF27                                                                  0x0867
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF28                                                                  0x0868
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF29                                                                  0x0869
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF30                                                                  0x086a
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX                                                         1
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF31                                                                  0x086b
+#define mmMMMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX                                                         1
+#define mmMMVM_IOMMU_MMIO_CNTRL_1                                                                      0x086c
+#define mmMMVM_IOMMU_MMIO_CNTRL_1_BASE_IDX                                                             1
+#define mmMMMC_VM_MARC_BASE_LO_0                                                                       0x086d
+#define mmMMMC_VM_MARC_BASE_LO_0_BASE_IDX                                                              1
+#define mmMMMC_VM_MARC_BASE_LO_1                                                                       0x086e
+#define mmMMMC_VM_MARC_BASE_LO_1_BASE_IDX                                                              1
+#define mmMMMC_VM_MARC_BASE_LO_2                                                                       0x086f
+#define mmMMMC_VM_MARC_BASE_LO_2_BASE_IDX                                                              1
+#define mmMMMC_VM_MARC_BASE_LO_3                                                                       0x0870
+#define mmMMMC_VM_MARC_BASE_LO_3_BASE_IDX                                                              1
+#define mmMMMC_VM_MARC_BASE_HI_0                                                                       0x0871
+#define mmMMMC_VM_MARC_BASE_HI_0_BASE_IDX                                                              1
+#define mmMMMC_VM_MARC_BASE_HI_1                                                                       0x0872
+#define mmMMMC_VM_MARC_BASE_HI_1_BASE_IDX                                                              1
+#define mmMMMC_VM_MARC_BASE_HI_2                                                                       0x0873
+#define mmMMMC_VM_MARC_BASE_HI_2_BASE_IDX                                                              1
+#define mmMMMC_VM_MARC_BASE_HI_3                                                                       0x0874
+#define mmMMMC_VM_MARC_BASE_HI_3_BASE_IDX                                                              1
+#define mmMMMC_VM_MARC_RELOC_LO_0                                                                      0x0875
+#define mmMMMC_VM_MARC_RELOC_LO_0_BASE_IDX                                                             1
+#define mmMMMC_VM_MARC_RELOC_LO_1                                                                      0x0876
+#define mmMMMC_VM_MARC_RELOC_LO_1_BASE_IDX                                                             1
+#define mmMMMC_VM_MARC_RELOC_LO_2                                                                      0x0877
+#define mmMMMC_VM_MARC_RELOC_LO_2_BASE_IDX                                                             1
+#define mmMMMC_VM_MARC_RELOC_LO_3                                                                      0x0878
+#define mmMMMC_VM_MARC_RELOC_LO_3_BASE_IDX                                                             1
+#define mmMMMC_VM_MARC_RELOC_HI_0                                                                      0x0879
+#define mmMMMC_VM_MARC_RELOC_HI_0_BASE_IDX                                                             1
+#define mmMMMC_VM_MARC_RELOC_HI_1                                                                      0x087a
+#define mmMMMC_VM_MARC_RELOC_HI_1_BASE_IDX                                                             1
+#define mmMMMC_VM_MARC_RELOC_HI_2                                                                      0x087b
+#define mmMMMC_VM_MARC_RELOC_HI_2_BASE_IDX                                                             1
+#define mmMMMC_VM_MARC_RELOC_HI_3                                                                      0x087c
+#define mmMMMC_VM_MARC_RELOC_HI_3_BASE_IDX                                                             1
+#define mmMMMC_VM_MARC_LEN_LO_0                                                                        0x087d
+#define mmMMMC_VM_MARC_LEN_LO_0_BASE_IDX                                                               1
+#define mmMMMC_VM_MARC_LEN_LO_1                                                                        0x087e
+#define mmMMMC_VM_MARC_LEN_LO_1_BASE_IDX                                                               1
+#define mmMMMC_VM_MARC_LEN_LO_2                                                                        0x087f
+#define mmMMMC_VM_MARC_LEN_LO_2_BASE_IDX                                                               1
+#define mmMMMC_VM_MARC_LEN_LO_3                                                                        0x0880
+#define mmMMMC_VM_MARC_LEN_LO_3_BASE_IDX                                                               1
+#define mmMMMC_VM_MARC_LEN_HI_0                                                                        0x0881
+#define mmMMMC_VM_MARC_LEN_HI_0_BASE_IDX                                                               1
+#define mmMMMC_VM_MARC_LEN_HI_1                                                                        0x0882
+#define mmMMMC_VM_MARC_LEN_HI_1_BASE_IDX                                                               1
+#define mmMMMC_VM_MARC_LEN_HI_2                                                                        0x0883
+#define mmMMMC_VM_MARC_LEN_HI_2_BASE_IDX                                                               1
+#define mmMMMC_VM_MARC_LEN_HI_3                                                                        0x0884
+#define mmMMMC_VM_MARC_LEN_HI_3_BASE_IDX                                                               1
+#define mmMMVM_IOMMU_CONTROL_REGISTER                                                                  0x0885
+#define mmMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX                                                         1
+#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER                                         0x0886
+#define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX                                1
+#define mmMMVM_PCIE_ATS_CNTL                                                                           0x0887
+#define mmMMVM_PCIE_ATS_CNTL_BASE_IDX                                                                  1
+#define mmMMVM_PCIE_ATS_CNTL_VF_0                                                                      0x0888
+#define mmMMVM_PCIE_ATS_CNTL_VF_0_BASE_IDX                                                             1
+#define mmMMVM_PCIE_ATS_CNTL_VF_1                                                                      0x0889
+#define mmMMVM_PCIE_ATS_CNTL_VF_1_BASE_IDX                                                             1
+#define mmMMVM_PCIE_ATS_CNTL_VF_2                                                                      0x088a
+#define mmMMVM_PCIE_ATS_CNTL_VF_2_BASE_IDX                                                             1
+#define mmMMVM_PCIE_ATS_CNTL_VF_3                                                                      0x088b
+#define mmMMVM_PCIE_ATS_CNTL_VF_3_BASE_IDX                                                             1
+#define mmMMVM_PCIE_ATS_CNTL_VF_4                                                                      0x088c
+#define mmMMVM_PCIE_ATS_CNTL_VF_4_BASE_IDX                                                             1
+#define mmMMVM_PCIE_ATS_CNTL_VF_5                                                                      0x088d
+#define mmMMVM_PCIE_ATS_CNTL_VF_5_BASE_IDX                                                             1
+#define mmMMVM_PCIE_ATS_CNTL_VF_6                                                                      0x088e
+#define mmMMVM_PCIE_ATS_CNTL_VF_6_BASE_IDX                                                             1
+#define mmMMVM_PCIE_ATS_CNTL_VF_7                                                                      0x088f
+#define mmMMVM_PCIE_ATS_CNTL_VF_7_BASE_IDX                                                             1
+#define mmMMVM_PCIE_ATS_CNTL_VF_8                                                                      0x0890
+#define mmMMVM_PCIE_ATS_CNTL_VF_8_BASE_IDX                                                             1
+#define mmMMVM_PCIE_ATS_CNTL_VF_9                                                                      0x0891
+#define mmMMVM_PCIE_ATS_CNTL_VF_9_BASE_IDX                                                             1
+#define mmMMVM_PCIE_ATS_CNTL_VF_10                                                                     0x0892
+#define mmMMVM_PCIE_ATS_CNTL_VF_10_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_11                                                                     0x0893
+#define mmMMVM_PCIE_ATS_CNTL_VF_11_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_12                                                                     0x0894
+#define mmMMVM_PCIE_ATS_CNTL_VF_12_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_13                                                                     0x0895
+#define mmMMVM_PCIE_ATS_CNTL_VF_13_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_14                                                                     0x0896
+#define mmMMVM_PCIE_ATS_CNTL_VF_14_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_15                                                                     0x0897
+#define mmMMVM_PCIE_ATS_CNTL_VF_15_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_16                                                                     0x0898
+#define mmMMVM_PCIE_ATS_CNTL_VF_16_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_17                                                                     0x0899
+#define mmMMVM_PCIE_ATS_CNTL_VF_17_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_18                                                                     0x089a
+#define mmMMVM_PCIE_ATS_CNTL_VF_18_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_19                                                                     0x089b
+#define mmMMVM_PCIE_ATS_CNTL_VF_19_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_20                                                                     0x089c
+#define mmMMVM_PCIE_ATS_CNTL_VF_20_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_21                                                                     0x089d
+#define mmMMVM_PCIE_ATS_CNTL_VF_21_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_22                                                                     0x089e
+#define mmMMVM_PCIE_ATS_CNTL_VF_22_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_23                                                                     0x089f
+#define mmMMVM_PCIE_ATS_CNTL_VF_23_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_24                                                                     0x08a0
+#define mmMMVM_PCIE_ATS_CNTL_VF_24_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_25                                                                     0x08a1
+#define mmMMVM_PCIE_ATS_CNTL_VF_25_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_26                                                                     0x08a2
+#define mmMMVM_PCIE_ATS_CNTL_VF_26_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_27                                                                     0x08a3
+#define mmMMVM_PCIE_ATS_CNTL_VF_27_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_28                                                                     0x08a4
+#define mmMMVM_PCIE_ATS_CNTL_VF_28_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_29                                                                     0x08a5
+#define mmMMVM_PCIE_ATS_CNTL_VF_29_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_30                                                                     0x08a6
+#define mmMMVM_PCIE_ATS_CNTL_VF_30_BASE_IDX                                                            1
+#define mmMMVM_PCIE_ATS_CNTL_VF_31                                                                     0x08a7
+#define mmMMVM_PCIE_ATS_CNTL_VF_31_BASE_IDX                                                            1
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
+// base address: 0x6a340
+#define mmMMMC_VM_NB_MMIOBASE                                                                          0x08d0
+#define mmMMMC_VM_NB_MMIOBASE_BASE_IDX                                                                 1
+#define mmMMMC_VM_NB_MMIOLIMIT                                                                         0x08d1
+#define mmMMMC_VM_NB_MMIOLIMIT_BASE_IDX                                                                1
+#define mmMMMC_VM_NB_PCI_CTRL                                                                          0x08d2
+#define mmMMMC_VM_NB_PCI_CTRL_BASE_IDX                                                                 1
+#define mmMMMC_VM_NB_PCI_ARB                                                                           0x08d3
+#define mmMMMC_VM_NB_PCI_ARB_BASE_IDX                                                                  1
+#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1                                                                 0x08d4
+#define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX                                                        1
+#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2                                                                0x08d5
+#define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX                                                       1
+#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2                                                                0x08d6
+#define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX                                                       1
+#define mmMMMC_VM_FB_OFFSET                                                                            0x08d7
+#define mmMMMC_VM_FB_OFFSET_BASE_IDX                                                                   1
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB                                                     0x08d8
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX                                            1
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB                                                     0x08d9
+#define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX                                            1
+#define mmMMMC_VM_STEERING                                                                             0x08da
+#define mmMMMC_VM_STEERING_BASE_IDX                                                                    1
+#define mmMMMC_SHARED_VIRT_RESET_REQ                                                                   0x08db
+#define mmMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX                                                          1
+#define mmMMMC_MEM_POWER_LS                                                                            0x08dc
+#define mmMMMC_MEM_POWER_LS_BASE_IDX                                                                   1
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START                                                         0x08dd
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX                                                1
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END                                                           0x08de
+#define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX                                                  1
+#define mmMMMC_VM_APT_CNTL                                                                             0x08df
+#define mmMMMC_VM_APT_CNTL_BASE_IDX                                                                    1
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                          0x08e0
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                 1
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START                                                              0x08e1
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                     1
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END                                                                0x08e2
+#define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                       1
+#define mmMMUTCL2_CGTT_CLK_CTRL                                                                        0x08e3
+#define mmMMUTCL2_CGTT_CLK_CTRL_BASE_IDX                                                               1
+#define mmMMMC_SHARED_ACTIVE_FCN_ID                                                                    0x08e4
+#define mmMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX                                                           1
+#define mmMMMC_SHARED_VIRT_RESET_REQ2                                                                  0x08e5
+#define mmMMMC_SHARED_VIRT_RESET_REQ2_BASE_IDX                                                         1
+#define mmMMUTCL2_CGTT_BUSY_CTRL                                                                       0x08e6
+#define mmMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX                                                              1
+#define mmMMUTCL2_HARVEST_BYPASS_GROUPS                                                                0x08e7
+#define mmMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX                                                       1
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
+// base address: 0x6a3b0
+#define mmMMMC_VM_FB_LOCATION_BASE                                                                     0x08ec
+#define mmMMMC_VM_FB_LOCATION_BASE_BASE_IDX                                                            1
+#define mmMMMC_VM_FB_LOCATION_TOP                                                                      0x08ed
+#define mmMMMC_VM_FB_LOCATION_TOP_BASE_IDX                                                             1
+#define mmMMMC_VM_AGP_TOP                                                                              0x08ee
+#define mmMMMC_VM_AGP_TOP_BASE_IDX                                                                     1
+#define mmMMMC_VM_AGP_BOT                                                                              0x08ef
+#define mmMMMC_VM_AGP_BOT_BASE_IDX                                                                     1
+#define mmMMMC_VM_AGP_BASE                                                                             0x08f0
+#define mmMMMC_VM_AGP_BASE_BASE_IDX                                                                    1
+#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR                                                             0x08f1
+#define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                                    1
+#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR                                                            0x08f2
+#define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                                   1
+#define mmMMMC_VM_MX_L1_TLB_CNTL                                                                       0x08f3
+#define mmMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX                                                              1
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
+// base address: 0x6a400
+#define mmMM_ATC_L2_PERFCOUNTER_LO                                                                     0x0900
+#define mmMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX                                                            1
+#define mmMM_ATC_L2_PERFCOUNTER_HI                                                                     0x0901
+#define mmMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX                                                            1
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
+// base address: 0x6a420
+#define mmMM_ATC_L2_PERFCOUNTER0_CFG                                                                   0x0908
+#define mmMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX                                                          1
+#define mmMM_ATC_L2_PERFCOUNTER1_CFG                                                                   0x0909
+#define mmMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX                                                          1
+#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL                                                              0x090a
+#define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                     1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2ptdec
+// base address: 0x6a500
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0940
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0941
+#define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                     0x0942
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                     0x0943
+#define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                       0x0944
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                       0x0945
+#define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE0                                                            0x0946
+#define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE0_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE1                                                            0x0947
+#define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE1_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0948
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0949
+#define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                     0x094a
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                     0x094b
+#define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                       0x094c
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                       0x094d
+#define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE0                                                            0x094e
+#define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE0_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE1                                                            0x094f
+#define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE1_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0950
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0951
+#define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                     0x0952
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                     0x0953
+#define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                       0x0954
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                       0x0955
+#define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE0                                                            0x0956
+#define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE0_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE1                                                            0x0957
+#define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE1_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0958
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0959
+#define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                     0x095a
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                     0x095b
+#define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                       0x095c
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                       0x095d
+#define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE0                                                            0x095e
+#define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE0_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE1                                                            0x095f
+#define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE1_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0960
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0961
+#define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                     0x0962
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                     0x0963
+#define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                       0x0964
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                       0x0965
+#define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE0                                                            0x0966
+#define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE0_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE1                                                            0x0967
+#define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE1_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0968
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0969
+#define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                     0x096a
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                     0x096b
+#define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                       0x096c
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                       0x096d
+#define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE0                                                            0x096e
+#define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE0_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE1                                                            0x096f
+#define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE1_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0970
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0971
+#define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                     0x0972
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                     0x0973
+#define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                       0x0974
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                       0x0975
+#define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE0                                                            0x0976
+#define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE0_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE1                                                            0x0977
+#define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE1_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0978
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0979
+#define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                     0x097a
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                     0x097b
+#define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                       0x097c
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                       0x097d
+#define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE0                                                            0x097e
+#define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE0_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE1                                                            0x097f
+#define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE1_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0980
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0981
+#define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                     0x0982
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                     0x0983
+#define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                       0x0984
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                       0x0985
+#define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE0                                                            0x0986
+#define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE0_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE1                                                            0x0987
+#define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE1_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                      0x0988
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                      0x0989
+#define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                     0x098a
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                     0x098b
+#define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                       0x098c
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                       0x098d
+#define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              1
+#define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE0                                                            0x098e
+#define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE0_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE1                                                            0x098f
+#define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE1_BASE_IDX                                                   1
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                     0x0990
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                     0x0991
+#define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                    0x0992
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                    0x0993
+#define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                      0x0994
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                      0x0995
+#define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE0                                                           0x0996
+#define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE0_BASE_IDX                                                  1
+#define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE1                                                           0x0997
+#define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE1_BASE_IDX                                                  1
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                     0x0998
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                     0x0999
+#define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                    0x099a
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                    0x099b
+#define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                      0x099c
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                      0x099d
+#define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE0                                                           0x099e
+#define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE0_BASE_IDX                                                  1
+#define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE1                                                           0x099f
+#define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE1_BASE_IDX                                                  1
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                     0x09a0
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                     0x09a1
+#define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                    0x09a2
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                    0x09a3
+#define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                      0x09a4
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                      0x09a5
+#define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE0                                                           0x09a6
+#define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE0_BASE_IDX                                                  1
+#define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE1                                                           0x09a7
+#define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE1_BASE_IDX                                                  1
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                     0x09a8
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                     0x09a9
+#define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                    0x09aa
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                    0x09ab
+#define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                      0x09ac
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                      0x09ad
+#define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE0                                                           0x09ae
+#define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE0_BASE_IDX                                                  1
+#define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE1                                                           0x09af
+#define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE1_BASE_IDX                                                  1
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                     0x09b0
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                     0x09b1
+#define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                    0x09b2
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                    0x09b3
+#define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                      0x09b4
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                      0x09b5
+#define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE0                                                           0x09b6
+#define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE0_BASE_IDX                                                  1
+#define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE1                                                           0x09b7
+#define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE1_BASE_IDX                                                  1
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                     0x09b8
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                     0x09b9
+#define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            1
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                    0x09ba
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                    0x09bb
+#define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           1
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                      0x09bc
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                      0x09bd
+#define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             1
+#define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE0                                                           0x09be
+#define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE0_BASE_IDX                                                  1
+#define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE1                                                           0x09bf
+#define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE1_BASE_IDX                                                  1
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2indec
+// base address: 0x6a800
+#define mmMMVM_INVALIDATE_ENG0_SEM                                                                     0x0a00
+#define mmMMVM_INVALIDATE_ENG0_SEM_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG0_REQ                                                                     0x0a01
+#define mmMMVM_INVALIDATE_ENG0_REQ_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG0_ACK                                                                     0x0a02
+#define mmMMVM_INVALIDATE_ENG0_ACK_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32                                                         0x0a03
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32                                                         0x0a04
+#define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG0_RESERVE0                                                                0x0a05
+#define mmMMVM_INVALIDATE_ENG0_RESERVE0_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG0_RESERVE1                                                                0x0a06
+#define mmMMVM_INVALIDATE_ENG0_RESERVE1_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG0_RESERVE2                                                                0x0a07
+#define mmMMVM_INVALIDATE_ENG0_RESERVE2_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG1_SEM                                                                     0x0a08
+#define mmMMVM_INVALIDATE_ENG1_SEM_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG1_REQ                                                                     0x0a09
+#define mmMMVM_INVALIDATE_ENG1_REQ_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG1_ACK                                                                     0x0a0a
+#define mmMMVM_INVALIDATE_ENG1_ACK_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32                                                         0x0a0b
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32                                                         0x0a0c
+#define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG1_RESERVE0                                                                0x0a0d
+#define mmMMVM_INVALIDATE_ENG1_RESERVE0_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG1_RESERVE1                                                                0x0a0e
+#define mmMMVM_INVALIDATE_ENG1_RESERVE1_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG1_RESERVE2                                                                0x0a0f
+#define mmMMVM_INVALIDATE_ENG1_RESERVE2_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG2_SEM                                                                     0x0a10
+#define mmMMVM_INVALIDATE_ENG2_SEM_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG2_REQ                                                                     0x0a11
+#define mmMMVM_INVALIDATE_ENG2_REQ_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG2_ACK                                                                     0x0a12
+#define mmMMVM_INVALIDATE_ENG2_ACK_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32                                                         0x0a13
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32                                                         0x0a14
+#define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG2_RESERVE0                                                                0x0a15
+#define mmMMVM_INVALIDATE_ENG2_RESERVE0_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG2_RESERVE1                                                                0x0a16
+#define mmMMVM_INVALIDATE_ENG2_RESERVE1_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG2_RESERVE2                                                                0x0a17
+#define mmMMVM_INVALIDATE_ENG2_RESERVE2_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG3_SEM                                                                     0x0a18
+#define mmMMVM_INVALIDATE_ENG3_SEM_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG3_REQ                                                                     0x0a19
+#define mmMMVM_INVALIDATE_ENG3_REQ_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG3_ACK                                                                     0x0a1a
+#define mmMMVM_INVALIDATE_ENG3_ACK_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32                                                         0x0a1b
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32                                                         0x0a1c
+#define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG3_RESERVE0                                                                0x0a1d
+#define mmMMVM_INVALIDATE_ENG3_RESERVE0_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG3_RESERVE1                                                                0x0a1e
+#define mmMMVM_INVALIDATE_ENG3_RESERVE1_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG3_RESERVE2                                                                0x0a1f
+#define mmMMVM_INVALIDATE_ENG3_RESERVE2_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG4_SEM                                                                     0x0a20
+#define mmMMVM_INVALIDATE_ENG4_SEM_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG4_REQ                                                                     0x0a21
+#define mmMMVM_INVALIDATE_ENG4_REQ_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG4_ACK                                                                     0x0a22
+#define mmMMVM_INVALIDATE_ENG4_ACK_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32                                                         0x0a23
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32                                                         0x0a24
+#define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG4_RESERVE0                                                                0x0a25
+#define mmMMVM_INVALIDATE_ENG4_RESERVE0_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG4_RESERVE1                                                                0x0a26
+#define mmMMVM_INVALIDATE_ENG4_RESERVE1_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG4_RESERVE2                                                                0x0a27
+#define mmMMVM_INVALIDATE_ENG4_RESERVE2_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG5_SEM                                                                     0x0a28
+#define mmMMVM_INVALIDATE_ENG5_SEM_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG5_REQ                                                                     0x0a29
+#define mmMMVM_INVALIDATE_ENG5_REQ_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG5_ACK                                                                     0x0a2a
+#define mmMMVM_INVALIDATE_ENG5_ACK_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32                                                         0x0a2b
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32                                                         0x0a2c
+#define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG5_RESERVE0                                                                0x0a2d
+#define mmMMVM_INVALIDATE_ENG5_RESERVE0_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG5_RESERVE1                                                                0x0a2e
+#define mmMMVM_INVALIDATE_ENG5_RESERVE1_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG5_RESERVE2                                                                0x0a2f
+#define mmMMVM_INVALIDATE_ENG5_RESERVE2_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG6_SEM                                                                     0x0a30
+#define mmMMVM_INVALIDATE_ENG6_SEM_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG6_REQ                                                                     0x0a31
+#define mmMMVM_INVALIDATE_ENG6_REQ_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG6_ACK                                                                     0x0a32
+#define mmMMVM_INVALIDATE_ENG6_ACK_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32                                                         0x0a33
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32                                                         0x0a34
+#define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG6_RESERVE0                                                                0x0a35
+#define mmMMVM_INVALIDATE_ENG6_RESERVE0_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG6_RESERVE1                                                                0x0a36
+#define mmMMVM_INVALIDATE_ENG6_RESERVE1_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG6_RESERVE2                                                                0x0a37
+#define mmMMVM_INVALIDATE_ENG6_RESERVE2_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG7_SEM                                                                     0x0a38
+#define mmMMVM_INVALIDATE_ENG7_SEM_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG7_REQ                                                                     0x0a39
+#define mmMMVM_INVALIDATE_ENG7_REQ_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG7_ACK                                                                     0x0a3a
+#define mmMMVM_INVALIDATE_ENG7_ACK_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32                                                         0x0a3b
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32                                                         0x0a3c
+#define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG7_RESERVE0                                                                0x0a3d
+#define mmMMVM_INVALIDATE_ENG7_RESERVE0_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG7_RESERVE1                                                                0x0a3e
+#define mmMMVM_INVALIDATE_ENG7_RESERVE1_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG7_RESERVE2                                                                0x0a3f
+#define mmMMVM_INVALIDATE_ENG7_RESERVE2_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG8_SEM                                                                     0x0a40
+#define mmMMVM_INVALIDATE_ENG8_SEM_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG8_REQ                                                                     0x0a41
+#define mmMMVM_INVALIDATE_ENG8_REQ_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG8_ACK                                                                     0x0a42
+#define mmMMVM_INVALIDATE_ENG8_ACK_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32                                                         0x0a43
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32                                                         0x0a44
+#define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG8_RESERVE0                                                                0x0a45
+#define mmMMVM_INVALIDATE_ENG8_RESERVE0_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG8_RESERVE1                                                                0x0a46
+#define mmMMVM_INVALIDATE_ENG8_RESERVE1_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG8_RESERVE2                                                                0x0a47
+#define mmMMVM_INVALIDATE_ENG8_RESERVE2_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG9_SEM                                                                     0x0a48
+#define mmMMVM_INVALIDATE_ENG9_SEM_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG9_REQ                                                                     0x0a49
+#define mmMMVM_INVALIDATE_ENG9_REQ_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG9_ACK                                                                     0x0a4a
+#define mmMMVM_INVALIDATE_ENG9_ACK_BASE_IDX                                                            1
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32                                                         0x0a4b
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32                                                         0x0a4c
+#define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX                                                1
+#define mmMMVM_INVALIDATE_ENG9_RESERVE0                                                                0x0a4d
+#define mmMMVM_INVALIDATE_ENG9_RESERVE0_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG9_RESERVE1                                                                0x0a4e
+#define mmMMVM_INVALIDATE_ENG9_RESERVE1_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG9_RESERVE2                                                                0x0a4f
+#define mmMMVM_INVALIDATE_ENG9_RESERVE2_BASE_IDX                                                       1
+#define mmMMVM_INVALIDATE_ENG10_SEM                                                                    0x0a50
+#define mmMMVM_INVALIDATE_ENG10_SEM_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG10_REQ                                                                    0x0a51
+#define mmMMVM_INVALIDATE_ENG10_REQ_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG10_ACK                                                                    0x0a52
+#define mmMMVM_INVALIDATE_ENG10_ACK_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32                                                        0x0a53
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32                                                        0x0a54
+#define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG10_RESERVE0                                                               0x0a55
+#define mmMMVM_INVALIDATE_ENG10_RESERVE0_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG10_RESERVE1                                                               0x0a56
+#define mmMMVM_INVALIDATE_ENG10_RESERVE1_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG10_RESERVE2                                                               0x0a57
+#define mmMMVM_INVALIDATE_ENG10_RESERVE2_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG11_SEM                                                                    0x0a58
+#define mmMMVM_INVALIDATE_ENG11_SEM_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG11_REQ                                                                    0x0a59
+#define mmMMVM_INVALIDATE_ENG11_REQ_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG11_ACK                                                                    0x0a5a
+#define mmMMVM_INVALIDATE_ENG11_ACK_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32                                                        0x0a5b
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32                                                        0x0a5c
+#define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG11_RESERVE0                                                               0x0a5d
+#define mmMMVM_INVALIDATE_ENG11_RESERVE0_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG11_RESERVE1                                                               0x0a5e
+#define mmMMVM_INVALIDATE_ENG11_RESERVE1_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG11_RESERVE2                                                               0x0a5f
+#define mmMMVM_INVALIDATE_ENG11_RESERVE2_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG12_SEM                                                                    0x0a60
+#define mmMMVM_INVALIDATE_ENG12_SEM_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG12_REQ                                                                    0x0a61
+#define mmMMVM_INVALIDATE_ENG12_REQ_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG12_ACK                                                                    0x0a62
+#define mmMMVM_INVALIDATE_ENG12_ACK_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32                                                        0x0a63
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32                                                        0x0a64
+#define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG12_RESERVE0                                                               0x0a65
+#define mmMMVM_INVALIDATE_ENG12_RESERVE0_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG12_RESERVE1                                                               0x0a66
+#define mmMMVM_INVALIDATE_ENG12_RESERVE1_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG12_RESERVE2                                                               0x0a67
+#define mmMMVM_INVALIDATE_ENG12_RESERVE2_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG13_SEM                                                                    0x0a68
+#define mmMMVM_INVALIDATE_ENG13_SEM_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG13_REQ                                                                    0x0a69
+#define mmMMVM_INVALIDATE_ENG13_REQ_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG13_ACK                                                                    0x0a6a
+#define mmMMVM_INVALIDATE_ENG13_ACK_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32                                                        0x0a6b
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32                                                        0x0a6c
+#define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG13_RESERVE0                                                               0x0a6d
+#define mmMMVM_INVALIDATE_ENG13_RESERVE0_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG13_RESERVE1                                                               0x0a6e
+#define mmMMVM_INVALIDATE_ENG13_RESERVE1_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG13_RESERVE2                                                               0x0a6f
+#define mmMMVM_INVALIDATE_ENG13_RESERVE2_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG14_SEM                                                                    0x0a70
+#define mmMMVM_INVALIDATE_ENG14_SEM_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG14_REQ                                                                    0x0a71
+#define mmMMVM_INVALIDATE_ENG14_REQ_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG14_ACK                                                                    0x0a72
+#define mmMMVM_INVALIDATE_ENG14_ACK_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32                                                        0x0a73
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32                                                        0x0a74
+#define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG14_RESERVE0                                                               0x0a75
+#define mmMMVM_INVALIDATE_ENG14_RESERVE0_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG14_RESERVE1                                                               0x0a76
+#define mmMMVM_INVALIDATE_ENG14_RESERVE1_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG14_RESERVE2                                                               0x0a77
+#define mmMMVM_INVALIDATE_ENG14_RESERVE2_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG15_SEM                                                                    0x0a78
+#define mmMMVM_INVALIDATE_ENG15_SEM_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG15_REQ                                                                    0x0a79
+#define mmMMVM_INVALIDATE_ENG15_REQ_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG15_ACK                                                                    0x0a7a
+#define mmMMVM_INVALIDATE_ENG15_ACK_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32                                                        0x0a7b
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32                                                        0x0a7c
+#define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG15_RESERVE0                                                               0x0a7d
+#define mmMMVM_INVALIDATE_ENG15_RESERVE0_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG15_RESERVE1                                                               0x0a7e
+#define mmMMVM_INVALIDATE_ENG15_RESERVE1_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG15_RESERVE2                                                               0x0a7f
+#define mmMMVM_INVALIDATE_ENG15_RESERVE2_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG16_SEM                                                                    0x0a80
+#define mmMMVM_INVALIDATE_ENG16_SEM_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG16_REQ                                                                    0x0a81
+#define mmMMVM_INVALIDATE_ENG16_REQ_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG16_ACK                                                                    0x0a82
+#define mmMMVM_INVALIDATE_ENG16_ACK_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32                                                        0x0a83
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32                                                        0x0a84
+#define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG16_RESERVE0                                                               0x0a85
+#define mmMMVM_INVALIDATE_ENG16_RESERVE0_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG16_RESERVE1                                                               0x0a86
+#define mmMMVM_INVALIDATE_ENG16_RESERVE1_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG16_RESERVE2                                                               0x0a87
+#define mmMMVM_INVALIDATE_ENG16_RESERVE2_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG17_SEM                                                                    0x0a88
+#define mmMMVM_INVALIDATE_ENG17_SEM_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG17_REQ                                                                    0x0a89
+#define mmMMVM_INVALIDATE_ENG17_REQ_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG17_ACK                                                                    0x0a8a
+#define mmMMVM_INVALIDATE_ENG17_ACK_BASE_IDX                                                           1
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32                                                        0x0a8b
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32                                                        0x0a8c
+#define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX                                               1
+#define mmMMVM_INVALIDATE_ENG17_RESERVE0                                                               0x0a8d
+#define mmMMVM_INVALIDATE_ENG17_RESERVE0_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG17_RESERVE1                                                               0x0a8e
+#define mmMMVM_INVALIDATE_ENG17_RESERVE1_BASE_IDX                                                      1
+#define mmMMVM_INVALIDATE_ENG17_RESERVE2                                                               0x0a8f
+#define mmMMVM_INVALIDATE_ENG17_RESERVE2_BASE_IDX                                                      1
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpfdec
+// base address: 0x6aa90
+#define mmMML2TLB_TLB0_STATUS                                                                          0x0aa5
+#define mmMML2TLB_TLB0_STATUS_BASE_IDX                                                                 1
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpldec
+// base address: 0x6ab00
+#define mmMML2TLB_PERFCOUNTER0_CFG                                                                     0x0ac0
+#define mmMML2TLB_PERFCOUNTER0_CFG_BASE_IDX                                                            1
+#define mmMML2TLB_PERFCOUNTER1_CFG                                                                     0x0ac1
+#define mmMML2TLB_PERFCOUNTER1_CFG_BASE_IDX                                                            1
+#define mmMML2TLB_PERFCOUNTER2_CFG                                                                     0x0ac2
+#define mmMML2TLB_PERFCOUNTER2_CFG_BASE_IDX                                                            1
+#define mmMML2TLB_PERFCOUNTER3_CFG                                                                     0x0ac3
+#define mmMML2TLB_PERFCOUNTER3_CFG_BASE_IDX                                                            1
+#define mmMML2TLB_PERFCOUNTER_RSLT_CNTL                                                                0x0ac4
+#define mmMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                       1
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbprdec
+// base address: 0x6ab20
+#define mmMML2TLB_PERFCOUNTER_LO                                                                       0x0ac8
+#define mmMML2TLB_PERFCOUNTER_LO_BASE_IDX                                                              1
+#define mmMML2TLB_PERFCOUNTER_HI                                                                       0x0ac9
+#define mmMML2TLB_PERFCOUNTER_HI_BASE_IDX                                                              1
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_sh_mask.h
new file mode 100644
index 000000000000..1c120658fe91
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_3_0_sh_mask.h
@@ -0,0 +1,10331 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mmhub_2_3_0_SH_MASK_HEADER
+#define _mmhub_2_3_0_SH_MASK_HEADER
+
+
+// addressBlock: mmhub_dagbdec
+//DAGB0_RDCLI0
+#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI0__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI0__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI0__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI1
+#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI1__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI1__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI1__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI2
+#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI2__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI2__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI2__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI3
+#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI3__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI3__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI3__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI4
+#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI4__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI4__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI4__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI5
+#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI5__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI5__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI5__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI6
+#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI6__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI6__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI6__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI7
+#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI7__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI7__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI7__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI8
+#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI8__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI8__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI8__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI9
+#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_RDCLI9__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_RDCLI9__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_RDCLI9__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_RDCLI10
+#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI10__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI10__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI10__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI11
+#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI11__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI11__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI11__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI12
+#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI12__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI12__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI12__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI13
+#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI13__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI13__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI13__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI14
+#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI14__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI14__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI14__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI15
+#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI15__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI15__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI15__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI16
+#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI16__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI16__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI16__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI16__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI16__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI16__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI16__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI16__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI16__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI16__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI16__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI17
+#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI17__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI17__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI17__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI17__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI17__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI17__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI17__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI17__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI17__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI17__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI17__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI18
+#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI18__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI18__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI18__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI18__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI18__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI18__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI18__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI18__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI18__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI18__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI18__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI19
+#define DAGB0_RDCLI19__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI19__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI19__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI19__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI19__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI19__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI19__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI19__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI19__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI19__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI19__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI19__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI20
+#define DAGB0_RDCLI20__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI20__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI20__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI20__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI20__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI20__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI20__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI20__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI20__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI20__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI20__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI20__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI21
+#define DAGB0_RDCLI21__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI21__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI21__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI21__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI21__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI21__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI21__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI21__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI21__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI21__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI21__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI21__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI22
+#define DAGB0_RDCLI22__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI22__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI22__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI22__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI22__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI22__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI22__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI22__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI22__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI22__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI22__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI22__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI23
+#define DAGB0_RDCLI23__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI23__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI23__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI23__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI23__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI23__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI23__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI23__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI23__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI23__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI23__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI23__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI24
+#define DAGB0_RDCLI24__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI24__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI24__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI24__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI24__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI24__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI24__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI24__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI24__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI24__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI24__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI24__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI25
+#define DAGB0_RDCLI25__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI25__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI25__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI25__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI25__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI25__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI25__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI25__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI25__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI25__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI25__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI25__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI26
+#define DAGB0_RDCLI26__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI26__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI26__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI26__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI26__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI26__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI26__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI26__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI26__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI26__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI26__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI26__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI27
+#define DAGB0_RDCLI27__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI27__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI27__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI27__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI27__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI27__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI27__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI27__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI27__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI27__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI27__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI27__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI28
+#define DAGB0_RDCLI28__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI28__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI28__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI28__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI28__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI28__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI28__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI28__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI28__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI28__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI28__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI28__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI29
+#define DAGB0_RDCLI29__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI29__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI29__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI29__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI29__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI29__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI29__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI29__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI29__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI29__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI29__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI29__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RDCLI30
+#define DAGB0_RDCLI30__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_RDCLI30__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_RDCLI30__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_RDCLI30__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_RDCLI30__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_RDCLI30__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_RDCLI30__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_RDCLI30__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_RDCLI30__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_RDCLI30__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_RDCLI30__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_RDCLI30__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_RDCLI30__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_RDCLI30__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_RDCLI30__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_RDCLI30__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_RDCLI30__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_RDCLI30__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_RDCLI30__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_RDCLI30__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_RD_CNTL
+#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
+#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
+#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
+#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
+#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
+#define DAGB0_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
+#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
+#define DAGB0_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
+#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
+#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
+//DAGB0_RD_GMI_CNTL
+#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
+#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
+#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
+#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
+#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
+#define DAGB0_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
+#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
+#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
+//DAGB0_RD_ADDR_DAGB
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
+#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
+#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
+#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
+#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
+//DAGB0_RD_OUTPUT_DAGB_MAX_BURST
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
+//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
+//DAGB0_RD_CGTT_CLK_CTRL
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
+#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
+#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
+//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
+//DAGB0_ATCVM_RD_CGTT_CLK_CTRL
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST1
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST2
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT                                                        0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT                                                        0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT                                                        0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT                                                        0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT                                                        0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT                                                        0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT                                                        0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT                                                        0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK                                                          0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK                                                          0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK                                                          0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK                                                          0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK                                                          0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK                                                          0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK                                                          0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK                                                          0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT                                                       0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT                                                       0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT                                                       0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT                                                       0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT                                                       0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT                                                       0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT                                                       0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT                                                       0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK                                                         0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK                                                         0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK                                                         0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK                                                         0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK                                                         0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK                                                         0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK                                                         0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK                                                         0xF0000000L
+//DAGB0_RD_ADDR_DAGB_MAX_BURST3
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT                                                        0x0
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT                                                        0x4
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT                                                        0x8
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT                                                        0xc
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT                                                        0x10
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT                                                        0x14
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT                                                        0x18
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT                                                        0x1c
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK                                                          0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK                                                          0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK                                                          0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK                                                          0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK                                                          0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK                                                          0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK                                                          0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK                                                          0xF0000000L
+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER3
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT                                                       0x0
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT                                                       0x4
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT                                                       0x8
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT                                                       0xc
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT                                                       0x10
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT                                                       0x14
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT                                                       0x18
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT                                                       0x1c
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK                                                         0x0000000FL
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK                                                         0x000000F0L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK                                                         0x00000F00L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK                                                         0x0000F000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK                                                         0x000F0000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK                                                         0x00F00000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK                                                         0x0F000000L
+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK                                                         0xF0000000L
+//DAGB0_RD_VC0_CNTL
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC1_CNTL
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC2_CNTL
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC3_CNTL
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC4_CNTL
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC5_CNTL
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC6_CNTL
+#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_VC7_CNTL
+#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_RD_CNTL_MISC
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
+#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
+#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
+#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
+#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
+#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
+#define DAGB0_RD_CNTL_MISC__HDP_CID__SHIFT                                                                    0x1a
+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
+#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
+#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
+#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
+#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
+#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
+#define DAGB0_RD_CNTL_MISC__HDP_CID_MASK                                                                      0x7C000000L
+//DAGB0_RD_TLB_CREDIT
+#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
+#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
+#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
+#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
+#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
+#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
+#define DAGB0_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
+#define DAGB0_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
+#define DAGB0_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
+#define DAGB0_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
+#define DAGB0_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
+#define DAGB0_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
+//DAGB0_RD_RDRET_CREDIT_CNTL
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT                                                         0x0
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT                                                         0x6
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT                                                         0xc
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT                                                         0x12
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT                                                         0x18
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT                                                            0x1e
+#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT                                                             0x1f
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK                                                           0x0000003FL
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK                                                           0x00000FC0L
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK                                                           0x0003F000L
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK                                                           0x00FC0000L
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK                                                           0x3F000000L
+#define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK                                                              0x40000000L
+#define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK                                                               0x80000000L
+//DAGB0_RD_RDRET_CREDIT_CNTL2
+#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT                                                       0x0
+#define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK                                                         0x0000007FL
+//DAGB0_RDCLI_ASK_PENDING
+#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_RDCLI_GO_PENDING
+#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
+#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
+//DAGB0_RDCLI_GBLSEND_PENDING
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
+//DAGB0_RDCLI_TLB_PENDING
+#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_RDCLI_OARB_PENDING
+#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
+#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
+//DAGB0_RDCLI_OSD_PENDING
+#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_WRCLI0
+#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI0__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI0__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI0__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI1
+#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI1__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI1__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI1__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI2
+#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI2__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI2__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI2__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI3
+#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI3__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI3__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI3__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI4
+#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI4__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI4__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI4__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI5
+#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI5__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI5__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI5__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI6
+#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI6__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI6__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI6__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI7
+#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI7__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI7__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI7__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI8
+#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI8__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI8__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI8__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI9
+#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
+#define DAGB0_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
+#define DAGB0_WRCLI9__URG_LOW__SHIFT                                                                          0x8
+#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
+#define DAGB0_WRCLI9__MAX_BW__SHIFT                                                                           0xd
+#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
+#define DAGB0_WRCLI9__MIN_BW__SHIFT                                                                           0x16
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
+#define DAGB0_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
+#define DAGB0_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
+#define DAGB0_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
+#define DAGB0_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
+#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
+#define DAGB0_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
+#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
+#define DAGB0_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
+#define DAGB0_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
+//DAGB0_WRCLI10
+#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI10__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI10__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI10__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI11
+#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI11__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI11__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI11__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI12
+#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI12__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI12__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI12__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI13
+#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI13__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI13__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI13__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI14
+#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI14__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI14__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI14__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI15
+#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI15__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI15__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI15__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI16
+#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI16__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI16__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI16__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI16__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI16__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI16__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI16__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI16__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI16__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI16__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI16__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI17
+#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI17__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI17__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI17__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI17__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI17__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI17__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI17__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI17__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI17__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI17__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI17__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI18
+#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI18__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI18__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI18__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI18__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI18__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI18__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI18__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI18__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI18__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI18__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI18__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI19
+#define DAGB0_WRCLI19__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI19__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI19__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI19__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI19__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI19__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI19__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI19__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI19__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI19__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI19__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI19__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI20
+#define DAGB0_WRCLI20__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI20__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI20__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI20__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI20__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI20__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI20__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI20__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI20__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI20__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI20__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI20__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI21
+#define DAGB0_WRCLI21__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI21__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI21__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI21__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI21__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI21__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI21__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI21__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI21__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI21__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI21__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI21__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI22
+#define DAGB0_WRCLI22__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI22__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI22__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI22__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI22__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI22__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI22__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI22__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI22__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI22__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI22__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI22__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI23
+#define DAGB0_WRCLI23__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI23__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI23__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI23__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI23__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI23__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI23__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI23__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI23__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI23__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI23__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI23__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI24
+#define DAGB0_WRCLI24__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI24__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI24__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI24__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI24__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI24__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI24__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI24__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI24__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI24__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI24__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI24__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI25
+#define DAGB0_WRCLI25__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI25__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI25__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI25__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI25__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI25__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI25__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI25__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI25__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI25__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI25__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI25__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI26
+#define DAGB0_WRCLI26__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI26__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI26__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI26__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI26__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI26__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI26__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI26__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI26__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI26__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI26__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI26__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI27
+#define DAGB0_WRCLI27__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI27__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI27__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI27__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI27__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI27__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI27__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI27__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI27__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI27__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI27__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI27__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI28
+#define DAGB0_WRCLI28__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI28__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI28__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI28__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI28__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI28__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI28__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI28__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI28__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI28__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI28__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI28__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI29
+#define DAGB0_WRCLI29__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI29__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI29__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI29__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI29__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI29__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI29__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI29__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI29__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI29__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI29__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI29__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WRCLI30
+#define DAGB0_WRCLI30__VIRT_CHAN__SHIFT                                                                       0x0
+#define DAGB0_WRCLI30__CHECK_TLB_CREDIT__SHIFT                                                                0x3
+#define DAGB0_WRCLI30__URG_HIGH__SHIFT                                                                        0x4
+#define DAGB0_WRCLI30__URG_LOW__SHIFT                                                                         0x8
+#define DAGB0_WRCLI30__MAX_BW_ENABLE__SHIFT                                                                   0xc
+#define DAGB0_WRCLI30__MAX_BW__SHIFT                                                                          0xd
+#define DAGB0_WRCLI30__MIN_BW_ENABLE__SHIFT                                                                   0x15
+#define DAGB0_WRCLI30__MIN_BW__SHIFT                                                                          0x16
+#define DAGB0_WRCLI30__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
+#define DAGB0_WRCLI30__MAX_OSD__SHIFT                                                                         0x1a
+#define DAGB0_WRCLI30__VIRT_CHAN_MASK                                                                         0x00000007L
+#define DAGB0_WRCLI30__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
+#define DAGB0_WRCLI30__URG_HIGH_MASK                                                                          0x000000F0L
+#define DAGB0_WRCLI30__URG_LOW_MASK                                                                           0x00000F00L
+#define DAGB0_WRCLI30__MAX_BW_ENABLE_MASK                                                                     0x00001000L
+#define DAGB0_WRCLI30__MAX_BW_MASK                                                                            0x001FE000L
+#define DAGB0_WRCLI30__MIN_BW_ENABLE_MASK                                                                     0x00200000L
+#define DAGB0_WRCLI30__MIN_BW_MASK                                                                            0x01C00000L
+#define DAGB0_WRCLI30__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
+#define DAGB0_WRCLI30__MAX_OSD_MASK                                                                           0xFC000000L
+//DAGB0_WR_CNTL
+#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
+#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
+#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
+#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
+#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
+#define DAGB0_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
+#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
+#define DAGB0_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
+#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
+#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
+//DAGB0_WR_GMI_CNTL
+#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
+#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
+#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
+#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
+#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
+#define DAGB0_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
+#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
+#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
+//DAGB0_WR_ADDR_DAGB
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
+#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
+#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
+#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
+#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
+//DAGB0_WR_OUTPUT_DAGB_MAX_BURST
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
+//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
+//DAGB0_WR_CGTT_CLK_CTRL
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
+#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
+#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
+//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
+//DAGB0_ATCVM_WR_CGTT_CLK_CTRL
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST1
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST2
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT                                                        0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT                                                        0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT                                                        0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT                                                        0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT                                                        0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT                                                        0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT                                                        0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT                                                        0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK                                                          0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK                                                          0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK                                                          0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK                                                          0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK                                                          0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK                                                          0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK                                                          0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK                                                          0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT                                                       0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT                                                       0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT                                                       0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT                                                       0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT                                                       0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT                                                       0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT                                                       0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT                                                       0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK                                                         0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK                                                         0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK                                                         0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK                                                         0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK                                                         0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK                                                         0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK                                                         0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK                                                         0xF0000000L
+//DAGB0_WR_ADDR_DAGB_MAX_BURST3
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT                                                        0x0
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT                                                        0x4
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT                                                        0x8
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT                                                        0xc
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT                                                        0x10
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT                                                        0x14
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT                                                        0x18
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT                                                        0x1c
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK                                                          0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK                                                          0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK                                                          0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK                                                          0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK                                                          0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK                                                          0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK                                                          0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK                                                          0xF0000000L
+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER3
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT                                                       0x0
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT                                                       0x4
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT                                                       0x8
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT                                                       0xc
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT                                                       0x10
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT                                                       0x14
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT                                                       0x18
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT                                                       0x1c
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK                                                         0x0000000FL
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK                                                         0x000000F0L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK                                                         0x00000F00L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK                                                         0x0000F000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK                                                         0x000F0000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK                                                         0x00F00000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK                                                         0x0F000000L
+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK                                                         0xF0000000L
+//DAGB0_WR_DATA_DAGB
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
+#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
+#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
+//DAGB0_WR_DATA_DAGB_MAX_BURST0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST1
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST2
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT                                                        0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT                                                        0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT                                                        0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT                                                        0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT                                                        0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT                                                        0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT                                                        0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT                                                        0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK                                                          0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK                                                          0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK                                                          0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK                                                          0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK                                                          0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK                                                          0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK                                                          0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK                                                          0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER2
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT                                                       0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT                                                       0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT                                                       0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT                                                       0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT                                                       0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT                                                       0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT                                                       0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT                                                       0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK                                                         0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK                                                         0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK                                                         0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK                                                         0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK                                                         0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK                                                         0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK                                                         0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK                                                         0xF0000000L
+//DAGB0_WR_DATA_DAGB_MAX_BURST3
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT                                                        0x0
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT                                                        0x4
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT                                                        0x8
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT                                                        0xc
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT                                                        0x10
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT                                                        0x14
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT                                                        0x18
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT                                                        0x1c
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK                                                          0x0000000FL
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK                                                          0x000000F0L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK                                                          0x00000F00L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK                                                          0x0000F000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK                                                          0x000F0000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK                                                          0x00F00000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK                                                          0x0F000000L
+#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK                                                          0xF0000000L
+//DAGB0_WR_DATA_DAGB_LAZY_TIMER3
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT                                                       0x0
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT                                                       0x4
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT                                                       0x8
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT                                                       0xc
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT                                                       0x10
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT                                                       0x14
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT                                                       0x18
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT                                                       0x1c
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK                                                         0x0000000FL
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK                                                         0x000000F0L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK                                                         0x00000F00L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK                                                         0x0000F000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK                                                         0x000F0000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK                                                         0x00F00000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK                                                         0x0F000000L
+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK                                                         0xF0000000L
+//DAGB0_WR_VC0_CNTL
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC1_CNTL
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC2_CNTL
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC3_CNTL
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC4_CNTL
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC5_CNTL
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC6_CNTL
+#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_VC7_CNTL
+#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
+#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
+#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
+#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
+#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
+#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
+#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
+#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
+#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
+#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
+#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
+#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
+#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
+#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
+#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
+#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
+//DAGB0_WR_CNTL_MISC
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
+#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
+#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
+#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
+#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
+#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
+#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT                                                                    0x1a
+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
+#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
+#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
+#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
+#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
+#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
+#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK                                                                      0x7C000000L
+//DAGB0_WR_TLB_CREDIT
+#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
+#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
+#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
+#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
+#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
+#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
+#define DAGB0_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
+#define DAGB0_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
+#define DAGB0_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
+#define DAGB0_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
+#define DAGB0_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
+#define DAGB0_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
+//DAGB0_WR_DATA_CREDIT
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
+//DAGB0_WR_MISC_CREDIT
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
+#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
+#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
+#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
+#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
+//DAGB0_WR_OSD_CREDIT_CNTL1
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                          0x0
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                          0x4
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                          0x8
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                          0xc
+#define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT                                                           0x10
+#define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT                                                          0x14
+#define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                         0x18
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK                                                            0x0000000FL
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK                                                            0x000000F0L
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK                                                            0x00000F00L
+#define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK                                                            0x0000F000L
+#define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK                                                             0x000F0000L
+#define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK                                                            0x00F00000L
+#define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK                                                           0x3F000000L
+//DAGB0_WR_OSD_CREDIT_CNTL2
+#define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT                                                       0x0
+#define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT                                                       0x4
+#define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK                                                         0x0000000FL
+#define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK                                                         0x00000010L
+//DAGB0_WR_DATA_FIFO_CREDIT_CNTL1
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                    0x0
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                    0x5
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                    0xa
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                    0xf
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                   0x14
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                       0x19
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                        0x1a
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                          0x1b
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX1__SHIFT                                                          0x1c
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX2__SHIFT                                                          0x1d
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                      0x0000001FL
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                      0x000003E0L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                      0x00007C00L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                      0x000F8000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                     0x01F00000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                         0x02000000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                          0x04000000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK                                                            0x08000000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX1_MASK                                                            0x10000000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX2_MASK                                                            0x20000000L
+//DAGB0_WR_DATA_FIFO_CREDIT_CNTL2
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC0_MAX_LENGTH__SHIFT                                                0x0
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC1_MAX_LENGTH__SHIFT                                                0x4
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC2_MAX_LENGTH__SHIFT                                                0x8
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC3_MAX_LENGTH__SHIFT                                                0xc
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC4_MAX_LENGTH__SHIFT                                                0x10
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC0_MAX_LENGTH_MASK                                                  0x0000000FL
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC1_MAX_LENGTH_MASK                                                  0x000000F0L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC2_MAX_LENGTH_MASK                                                  0x00000F00L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC3_MAX_LENGTH_MASK                                                  0x0000F000L
+#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL2__VC4_MAX_LENGTH_MASK                                                  0x000F0000L
+//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                  0x0
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                  0x5
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                  0xa
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                  0xf
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                 0x14
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                     0x19
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                      0x1a
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                        0x1b
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT                                                        0x1c
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT                                                        0x1d
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                    0x0000001FL
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                    0x000003E0L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                    0x00007C00L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                    0x000F8000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                   0x01F00000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                       0x02000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                        0x04000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK                                                          0x08000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK                                                          0x10000000L
+#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK                                                          0x20000000L
+//DAGB0_WRCLI_ASK_PENDING
+#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_WRCLI_GO_PENDING
+#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
+#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
+//DAGB0_WRCLI_GBLSEND_PENDING
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
+//DAGB0_WRCLI_TLB_PENDING
+#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_WRCLI_OARB_PENDING
+#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
+#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
+//DAGB0_WRCLI_OSD_PENDING
+#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
+#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_ASK_PENDING
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
+//DAGB0_WRCLI_DBUS_GO_PENDING
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
+//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT                                                         0x0
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK                                                           0xFFFFFFFFL
+//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT                                                   0x0
+#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK                                                     0xFFFFFFFFL
+//DAGB0_DAGB_DLY
+#define DAGB0_DAGB_DLY__DLY__SHIFT                                                                            0x0
+#define DAGB0_DAGB_DLY__CLI__SHIFT                                                                            0x8
+#define DAGB0_DAGB_DLY__POS__SHIFT                                                                            0x10
+#define DAGB0_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
+#define DAGB0_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
+#define DAGB0_DAGB_DLY__POS_MASK                                                                              0x000F0000L
+//DAGB0_CNTL_MISC
+#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
+#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
+#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
+#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
+#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
+#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
+#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
+#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
+#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
+#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
+#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
+#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
+#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
+#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
+#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
+#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
+#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
+#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
+//DAGB0_CNTL_MISC2
+#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
+#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
+#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
+#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
+#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
+#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
+#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
+#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
+#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
+#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT                                                          0xb
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xc
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_CREDITS__SHIFT                                                           0xd
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x13
+#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
+#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
+#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
+#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
+#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
+#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
+#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
+#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
+#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
+#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK                                                            0x00000800L
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00001000L
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_CREDITS_MASK                                                             0x0007E000L
+#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x01F80000L
+//DAGB0_FIFO_EMPTY
+#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
+#define DAGB0_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
+//DAGB0_FIFO_FULL
+#define DAGB0_FIFO_FULL__FULL__SHIFT                                                                          0x0
+#define DAGB0_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
+//DAGB0_WR_CREDITS_FULL
+#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
+#define DAGB0_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
+//DAGB0_RD_CREDITS_FULL
+#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
+#define DAGB0_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
+//DAGB0_PERFCOUNTER_LO
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
+//DAGB0_PERFCOUNTER_HI
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
+//DAGB0_PERFCOUNTER0_CFG
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
+#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
+#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
+//DAGB0_PERFCOUNTER1_CFG
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
+#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
+#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
+//DAGB0_PERFCOUNTER2_CFG
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
+#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
+#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
+//DAGB0_PERFCOUNTER_RSLT_CNTL
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
+//DAGB0_RESERVE0
+#define DAGB0_RESERVE0__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE1
+#define DAGB0_RESERVE1__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE2
+#define DAGB0_RESERVE2__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE3
+#define DAGB0_RESERVE3__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE4
+#define DAGB0_RESERVE4__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE5
+#define DAGB0_RESERVE5__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE6
+#define DAGB0_RESERVE6__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE7
+#define DAGB0_RESERVE7__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE8
+#define DAGB0_RESERVE8__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
+//DAGB0_RESERVE9
+#define DAGB0_RESERVE9__RESERVE__SHIFT                                                                        0x0
+#define DAGB0_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
+
+
+// addressBlock: mmhub_mmea_mmeadec0
+//MMEA0_DRAM_RD_CLI2GRP_MAP0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
+//MMEA0_DRAM_RD_CLI2GRP_MAP1
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
+//MMEA0_DRAM_WR_CLI2GRP_MAP0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
+//MMEA0_DRAM_WR_CLI2GRP_MAP1
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
+//MMEA0_DRAM_RD_GRP2VC_MAP
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
+//MMEA0_DRAM_WR_GRP2VC_MAP
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
+//MMEA0_DRAM_RD_LAZY
+#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
+#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
+#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
+#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
+#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
+#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
+#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
+#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
+//MMEA0_DRAM_WR_LAZY
+#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
+#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
+#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
+#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
+#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
+#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
+#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
+#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
+//MMEA0_DRAM_RD_CAM_CNTL
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
+#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
+#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
+//MMEA0_DRAM_WR_CAM_CNTL
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
+#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
+#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
+//MMEA0_DRAM_PAGE_BURST
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
+//MMEA0_DRAM_RD_PRI_AGE
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
+//MMEA0_DRAM_WR_PRI_AGE
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
+//MMEA0_DRAM_RD_PRI_QUEUING
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
+//MMEA0_DRAM_WR_PRI_QUEUING
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
+//MMEA0_DRAM_RD_PRI_FIXED
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
+//MMEA0_DRAM_WR_PRI_FIXED
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
+//MMEA0_DRAM_RD_PRI_URGENCY
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
+//MMEA0_DRAM_WR_PRI_URGENCY
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI1
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI2
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
+//MMEA0_DRAM_RD_PRI_QUANT_PRI3
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI1
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI2
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
+//MMEA0_DRAM_WR_PRI_QUANT_PRI3
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
+//MMEA0_ADDRNORM_BASE_ADDR0
+#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
+#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
+#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
+#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
+#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
+#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
+//MMEA0_ADDRNORM_LIMIT_ADDR0
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
+#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
+//MMEA0_ADDRNORM_BASE_ADDR1
+#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
+#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
+#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
+#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
+#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
+#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
+//MMEA0_ADDRNORM_LIMIT_ADDR1
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
+#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
+//MMEA0_ADDRNORM_OFFSET_ADDR1
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
+//MMEA0_ADDRNORMDRAM_HOLE_CNTL
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
+//MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
+//MMEA0_ADDRDEC_BANK_CFG
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
+//MMEA0_ADDRDEC_MISC_CFG
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_PC
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
+//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
+//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDECDRAM_HARVEST_ENABLE
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
+//MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START__SHIFT                                                    0x0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR__SHIFT                                                 0x1c
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START_MASK                                                      0x000FFFFFL
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR_MASK                                                   0xF0000000L
+//MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END__SHIFT                                                        0x0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END_MASK                                                          0x000FFFFFL
+//MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START__SHIFT                                                    0x0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR__SHIFT                                                 0x1c
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START_MASK                                                      0x000FFFFFL
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR_MASK                                                   0xF0000000L
+//MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END__SHIFT                                                        0x0
+#define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END_MASK                                                          0x000FFFFFL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS2
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_CS3
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_CS01
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_CS23
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_CFG_CS01
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
+//MMEA0_ADDRDEC0_ADDR_CFG_CS23
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
+//MMEA0_ADDRDEC0_ADDR_SEL_CS01
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
+//MMEA0_ADDRDEC0_ADDR_SEL_CS23
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
+//MMEA0_ADDRDEC0_ADDR_SEL2_CS01
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
+//MMEA0_ADDRDEC0_ADDR_SEL2_CS23
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
+//MMEA0_ADDRDEC0_COL_SEL_LO_CS01
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_LO_CS23
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_HI_CS01
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_HI_CS23
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
+//MMEA0_ADDRDEC0_RM_SEL_CS01
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS__SHIFT                                                    0x1c
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_SEC__SHIFT                                                0x1e
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_MASK                                                      0x30000000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_SEC_MASK                                                  0xC0000000L
+//MMEA0_ADDRDEC0_RM_SEL_CS23
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS__SHIFT                                                    0x1c
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_SEC__SHIFT                                                0x1e
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_MASK                                                      0x30000000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_SEC_MASK                                                  0xC0000000L
+//MMEA0_ADDRDEC0_RM_SEL_CS1
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__RM0__SHIFT                                                                 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__RM1__SHIFT                                                                 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__RM2__SHIFT                                                                 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__CHAN_BIT__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__INVERT_ROW_MSBS__SHIFT                                                     0x1c
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__INVERT_ROW_MSBS_SEC__SHIFT                                                 0x1e
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__RM0_MASK                                                                   0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__RM1_MASK                                                                   0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__RM2_MASK                                                                   0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__CHAN_BIT_MASK                                                              0x000F0000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__INVERT_ROW_MSBS_MASK                                                       0x30000000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS1__INVERT_ROW_MSBS_SEC_MASK                                                   0xC0000000L
+//MMEA0_ADDRDEC0_RM_SEL_CS3
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__RM0__SHIFT                                                                 0x0
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__RM1__SHIFT                                                                 0x4
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__RM2__SHIFT                                                                 0x8
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__CHAN_BIT__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__INVERT_ROW_MSBS__SHIFT                                                     0x1c
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__INVERT_ROW_MSBS_SEC__SHIFT                                                 0x1e
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__RM0_MASK                                                                   0x0000000FL
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__RM1_MASK                                                                   0x000000F0L
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__RM2_MASK                                                                   0x00000F00L
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__CHAN_BIT_MASK                                                              0x000F0000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__INVERT_ROW_MSBS_MASK                                                       0x30000000L
+#define MMEA0_ADDRDEC0_RM_SEL_CS3__INVERT_ROW_MSBS_SEC_MASK                                                   0xC0000000L
+//MMEA0_ADDRDEC1_BASE_ADDR_CS0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS2
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_CS3
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_CS01
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_CS23
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_CFG_CS01
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
+//MMEA0_ADDRDEC1_ADDR_CFG_CS23
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
+//MMEA0_ADDRDEC1_ADDR_SEL_CS01
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
+//MMEA0_ADDRDEC1_ADDR_SEL_CS23
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
+//MMEA0_ADDRDEC1_ADDR_SEL2_CS01
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT                                                        0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK                                                          0x0000F000L
+//MMEA0_ADDRDEC1_ADDR_SEL2_CS23
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT                                                        0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK                                                          0x0000F000L
+//MMEA0_ADDRDEC1_COL_SEL_LO_CS01
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_LO_CS23
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_HI_CS01
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_HI_CS23
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
+//MMEA0_ADDRDEC1_RM_SEL_CS01
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS__SHIFT                                                    0x1c
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_SEC__SHIFT                                                0x1e
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_MASK                                                      0x30000000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_SEC_MASK                                                  0xC0000000L
+//MMEA0_ADDRDEC1_RM_SEL_CS23
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS__SHIFT                                                    0x1c
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_SEC__SHIFT                                                0x1e
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_MASK                                                      0x30000000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_SEC_MASK                                                  0xC0000000L
+//MMEA0_ADDRDEC1_RM_SEL_CS1
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__RM0__SHIFT                                                                 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__RM1__SHIFT                                                                 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__RM2__SHIFT                                                                 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__CHAN_BIT__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__INVERT_ROW_MSBS__SHIFT                                                     0x1c
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__INVERT_ROW_MSBS_SEC__SHIFT                                                 0x1e
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__RM0_MASK                                                                   0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__RM1_MASK                                                                   0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__RM2_MASK                                                                   0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__CHAN_BIT_MASK                                                              0x000F0000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__INVERT_ROW_MSBS_MASK                                                       0x30000000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS1__INVERT_ROW_MSBS_SEC_MASK                                                   0xC0000000L
+//MMEA0_ADDRDEC1_RM_SEL_CS3
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__RM0__SHIFT                                                                 0x0
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__RM1__SHIFT                                                                 0x4
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__RM2__SHIFT                                                                 0x8
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__CHAN_BIT__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__INVERT_ROW_MSBS__SHIFT                                                     0x1c
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__INVERT_ROW_MSBS_SEC__SHIFT                                                 0x1e
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__RM0_MASK                                                                   0x0000000FL
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__RM1_MASK                                                                   0x000000F0L
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__RM2_MASK                                                                   0x00000F00L
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__CHAN_BIT_MASK                                                              0x000F0000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__INVERT_ROW_MSBS_MASK                                                       0x30000000L
+#define MMEA0_ADDRDEC1_RM_SEL_CS3__INVERT_ROW_MSBS_SEC_MASK                                                   0xC0000000L
+//MMEA0_ADDRNORMDRAM_GLOBAL_CNTL
+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
+//MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__START__SHIFT                                                        0x0
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__END__SHIFT                                                          0xa
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__SUB__SHIFT                                                          0x14
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__START_MASK                                                          0x000003FFL
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__END_MASK                                                            0x000FFC00L
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ0__SUB_MASK                                                            0x3FF00000L
+//MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__START__SHIFT                                                        0x0
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__END__SHIFT                                                          0xa
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__SUB__SHIFT                                                          0x14
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__START_MASK                                                          0x000003FFL
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__END_MASK                                                            0x000FFC00L
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ1__SUB_MASK                                                            0x3FF00000L
+//MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__START__SHIFT                                                        0x0
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__END__SHIFT                                                          0xa
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__SUB__SHIFT                                                          0x14
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__START_MASK                                                          0x000003FFL
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__END_MASK                                                            0x000FFC00L
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ2__SUB_MASK                                                            0x3FF00000L
+//MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__START__SHIFT                                                        0x0
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__END__SHIFT                                                          0xa
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__SUB__SHIFT                                                          0x14
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__START_MASK                                                          0x000003FFL
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__END_MASK                                                            0x000FFC00L
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ3__SUB_MASK                                                            0x3FF00000L
+//MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__START__SHIFT                                                        0x0
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__END__SHIFT                                                          0xa
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__SUB__SHIFT                                                          0x14
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__START_MASK                                                          0x000003FFL
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__END_MASK                                                            0x000FFC00L
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ4__SUB_MASK                                                            0x3FF00000L
+//MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__START__SHIFT                                                        0x0
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__END__SHIFT                                                          0xa
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__SUB__SHIFT                                                          0x14
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__START_MASK                                                          0x000003FFL
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__END_MASK                                                            0x000FFC00L
+#define MMEA0_ADDRDECDRAM_GECC_HARV_ADJ5__SUB_MASK                                                            0x3FF00000L
+//MMEA0_ADDRDEC0_ADDR_MASK_CS1
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS1__ADDR_MASK__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS1__ADDR_MASK_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_CS3
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS3__ADDR_MASK__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_CS3__ADDR_MASK_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS1
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS1__ADDR_MASK__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS1__ADDR_MASK_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS3
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS3__ADDR_MASK__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS3__ADDR_MASK_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC0_ADDR_CFG_CS1
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_BANK_GROUPS__SHIFT                                                   0x1
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_RM__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_ROW_LO__SHIFT                                                        0x8
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_ROW_HI__SHIFT                                                        0xc
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_COL__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_BANKS__SHIFT                                                         0x14
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__HI_COL_EN__SHIFT                                                         0x1f
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_BANK_GROUPS_MASK                                                     0x0000000EL
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_RM_MASK                                                              0x00000030L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_ROW_LO_MASK                                                          0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_ROW_HI_MASK                                                          0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_COL_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__NUM_BANKS_MASK                                                           0x00300000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS1__HI_COL_EN_MASK                                                           0x80000000L
+//MMEA0_ADDRDEC0_ADDR_CFG_CS3
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_BANK_GROUPS__SHIFT                                                   0x1
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_RM__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_ROW_LO__SHIFT                                                        0x8
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_ROW_HI__SHIFT                                                        0xc
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_COL__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_BANKS__SHIFT                                                         0x14
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__HI_COL_EN__SHIFT                                                         0x1f
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_BANK_GROUPS_MASK                                                     0x0000000EL
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_RM_MASK                                                              0x00000030L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_ROW_LO_MASK                                                          0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_ROW_HI_MASK                                                          0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_COL_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__NUM_BANKS_MASK                                                           0x00300000L
+#define MMEA0_ADDRDEC0_ADDR_CFG_CS3__HI_COL_EN_MASK                                                           0x80000000L
+//MMEA0_ADDRDEC0_ADDR_SEL_CS1
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK0__SHIFT                                                             0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK1__SHIFT                                                             0x4
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK2__SHIFT                                                             0x8
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK3__SHIFT                                                             0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK4__SHIFT                                                             0x10
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__ROW_LO__SHIFT                                                            0x18
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__ROW_HI__SHIFT                                                            0x1c
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK0_MASK                                                               0x0000000FL
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK1_MASK                                                               0x000000F0L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK2_MASK                                                               0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK3_MASK                                                               0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__BANK4_MASK                                                               0x001F0000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__ROW_LO_MASK                                                              0x0F000000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS1__ROW_HI_MASK                                                              0xF0000000L
+//MMEA0_ADDRDEC0_ADDR_SEL_CS3
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK0__SHIFT                                                             0x0
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK1__SHIFT                                                             0x4
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK2__SHIFT                                                             0x8
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK3__SHIFT                                                             0xc
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK4__SHIFT                                                             0x10
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__ROW_LO__SHIFT                                                            0x18
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__ROW_HI__SHIFT                                                            0x1c
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK0_MASK                                                               0x0000000FL
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK1_MASK                                                               0x000000F0L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK2_MASK                                                               0x00000F00L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK3_MASK                                                               0x0000F000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__BANK4_MASK                                                               0x001F0000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__ROW_LO_MASK                                                              0x0F000000L
+#define MMEA0_ADDRDEC0_ADDR_SEL_CS3__ROW_HI_MASK                                                              0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_LO_CS1
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL0__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL1__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL2__SHIFT                                                            0x8
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL3__SHIFT                                                            0xc
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL4__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL5__SHIFT                                                            0x14
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL6__SHIFT                                                            0x18
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL7__SHIFT                                                            0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL0_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL1_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL2_MASK                                                              0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL3_MASK                                                              0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL4_MASK                                                              0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL5_MASK                                                              0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL6_MASK                                                              0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS1__COL7_MASK                                                              0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_LO_CS3
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL0__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL1__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL2__SHIFT                                                            0x8
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL3__SHIFT                                                            0xc
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL4__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL5__SHIFT                                                            0x14
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL6__SHIFT                                                            0x18
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL7__SHIFT                                                            0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL0_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL1_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL2_MASK                                                              0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL3_MASK                                                              0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL4_MASK                                                              0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL5_MASK                                                              0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL6_MASK                                                              0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS3__COL7_MASK                                                              0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_HI_CS1
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL8__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL9__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL10__SHIFT                                                           0x8
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL11__SHIFT                                                           0xc
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL12__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL13__SHIFT                                                           0x14
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL14__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL15__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL8_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL9_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL10_MASK                                                             0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL11_MASK                                                             0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL12_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL13_MASK                                                             0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL14_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS1__COL15_MASK                                                             0xF0000000L
+//MMEA0_ADDRDEC0_COL_SEL_HI_CS3
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL8__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL9__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL10__SHIFT                                                           0x8
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL11__SHIFT                                                           0xc
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL12__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL13__SHIFT                                                           0x14
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL14__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL15__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL8_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL9_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL10_MASK                                                             0x00000F00L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL11_MASK                                                             0x0000F000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL12_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL13_MASK                                                             0x00F00000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL14_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS3__COL15_MASK                                                             0xF0000000L
+//MMEA0_ADDRDEC1_ADDR_MASK_CS1
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS1__ADDR_MASK__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS1__ADDR_MASK_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_CS3
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS3__ADDR_MASK__SHIFT                                                        0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_CS3__ADDR_MASK_MASK                                                          0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS1
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS1__ADDR_MASK__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS1__ADDR_MASK_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS3
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS3__ADDR_MASK__SHIFT                                                     0x1
+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS3__ADDR_MASK_MASK                                                       0xFFFFFFFEL
+//MMEA0_ADDRDEC1_ADDR_CFG_CS1
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_BANK_GROUPS__SHIFT                                                   0x1
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_RM__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_ROW_LO__SHIFT                                                        0x8
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_ROW_HI__SHIFT                                                        0xc
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_COL__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_BANKS__SHIFT                                                         0x14
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__HI_COL_EN__SHIFT                                                         0x1f
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_BANK_GROUPS_MASK                                                     0x0000000EL
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_RM_MASK                                                              0x00000030L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_ROW_LO_MASK                                                          0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_ROW_HI_MASK                                                          0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_COL_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__NUM_BANKS_MASK                                                           0x00300000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS1__HI_COL_EN_MASK                                                           0x80000000L
+//MMEA0_ADDRDEC1_ADDR_CFG_CS3
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_BANK_GROUPS__SHIFT                                                   0x1
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_RM__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_ROW_LO__SHIFT                                                        0x8
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_ROW_HI__SHIFT                                                        0xc
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_COL__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_BANKS__SHIFT                                                         0x14
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__HI_COL_EN__SHIFT                                                         0x1f
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_BANK_GROUPS_MASK                                                     0x0000000EL
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_RM_MASK                                                              0x00000030L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_ROW_LO_MASK                                                          0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_ROW_HI_MASK                                                          0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_COL_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__NUM_BANKS_MASK                                                           0x00300000L
+#define MMEA0_ADDRDEC1_ADDR_CFG_CS3__HI_COL_EN_MASK                                                           0x80000000L
+//MMEA0_ADDRDEC1_ADDR_SEL_CS1
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK0__SHIFT                                                             0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK1__SHIFT                                                             0x4
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK2__SHIFT                                                             0x8
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK3__SHIFT                                                             0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK4__SHIFT                                                             0x10
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__ROW_LO__SHIFT                                                            0x18
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__ROW_HI__SHIFT                                                            0x1c
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK0_MASK                                                               0x0000000FL
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK1_MASK                                                               0x000000F0L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK2_MASK                                                               0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK3_MASK                                                               0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__BANK4_MASK                                                               0x001F0000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__ROW_LO_MASK                                                              0x0F000000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS1__ROW_HI_MASK                                                              0xF0000000L
+//MMEA0_ADDRDEC1_ADDR_SEL_CS3
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK0__SHIFT                                                             0x0
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK1__SHIFT                                                             0x4
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK2__SHIFT                                                             0x8
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK3__SHIFT                                                             0xc
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK4__SHIFT                                                             0x10
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__ROW_LO__SHIFT                                                            0x18
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__ROW_HI__SHIFT                                                            0x1c
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK0_MASK                                                               0x0000000FL
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK1_MASK                                                               0x000000F0L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK2_MASK                                                               0x00000F00L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK3_MASK                                                               0x0000F000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__BANK4_MASK                                                               0x001F0000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__ROW_LO_MASK                                                              0x0F000000L
+#define MMEA0_ADDRDEC1_ADDR_SEL_CS3__ROW_HI_MASK                                                              0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_LO_CS1
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL0__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL1__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL2__SHIFT                                                            0x8
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL3__SHIFT                                                            0xc
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL4__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL5__SHIFT                                                            0x14
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL6__SHIFT                                                            0x18
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL7__SHIFT                                                            0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL0_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL1_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL2_MASK                                                              0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL3_MASK                                                              0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL4_MASK                                                              0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL5_MASK                                                              0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL6_MASK                                                              0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS1__COL7_MASK                                                              0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_LO_CS3
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL0__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL1__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL2__SHIFT                                                            0x8
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL3__SHIFT                                                            0xc
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL4__SHIFT                                                            0x10
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL5__SHIFT                                                            0x14
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL6__SHIFT                                                            0x18
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL7__SHIFT                                                            0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL0_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL1_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL2_MASK                                                              0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL3_MASK                                                              0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL4_MASK                                                              0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL5_MASK                                                              0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL6_MASK                                                              0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS3__COL7_MASK                                                              0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_HI_CS1
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL8__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL9__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL10__SHIFT                                                           0x8
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL11__SHIFT                                                           0xc
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL12__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL13__SHIFT                                                           0x14
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL14__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL15__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL8_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL9_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL10_MASK                                                             0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL11_MASK                                                             0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL12_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL13_MASK                                                             0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL14_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS1__COL15_MASK                                                             0xF0000000L
+//MMEA0_ADDRDEC1_COL_SEL_HI_CS3
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL8__SHIFT                                                            0x0
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL9__SHIFT                                                            0x4
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL10__SHIFT                                                           0x8
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL11__SHIFT                                                           0xc
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL12__SHIFT                                                           0x10
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL13__SHIFT                                                           0x14
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL14__SHIFT                                                           0x18
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL15__SHIFT                                                           0x1c
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL8_MASK                                                              0x0000000FL
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL9_MASK                                                              0x000000F0L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL10_MASK                                                             0x00000F00L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL11_MASK                                                             0x0000F000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL12_MASK                                                             0x000F0000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL13_MASK                                                             0x00F00000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL14_MASK                                                             0x0F000000L
+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS3__COL15_MASK                                                             0xF0000000L
+//MMEA0_ADDRNORMDRAM_MASKING
+#define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT                                                        0x0
+#define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK                                                          0x00000FFFL
+//MMEA0_IO_RD_CLI2GRP_MAP0
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
+//MMEA0_IO_RD_CLI2GRP_MAP1
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
+//MMEA0_IO_WR_CLI2GRP_MAP0
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
+//MMEA0_IO_WR_CLI2GRP_MAP1
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
+//MMEA0_IO_RD_COMBINE_FLUSH
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
+#define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
+#define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
+//MMEA0_IO_WR_COMBINE_FLUSH
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
+#define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT                                                           0x10
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
+#define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK                                                             0x00030000L
+//MMEA0_IO_GROUP_BURST
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
+//MMEA0_IO_RD_PRI_AGE
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
+//MMEA0_IO_WR_PRI_AGE
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
+//MMEA0_IO_RD_PRI_QUEUING
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
+#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
+//MMEA0_IO_WR_PRI_QUEUING
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
+#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
+//MMEA0_IO_RD_PRI_FIXED
+#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
+#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
+#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
+#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
+#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
+#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
+//MMEA0_IO_WR_PRI_FIXED
+#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
+#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
+#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
+#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
+#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
+#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
+//MMEA0_IO_RD_PRI_URGENCY
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
+//MMEA0_IO_WR_PRI_URGENCY
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
+//MMEA0_IO_RD_PRI_URGENCY_MASKING
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
+//MMEA0_IO_WR_PRI_URGENCY_MASKING
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI1
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI2
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
+//MMEA0_IO_RD_PRI_QUANT_PRI3
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI1
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI2
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
+//MMEA0_IO_WR_PRI_QUANT_PRI3
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
+//MMEA0_SDP_ARB_DRAM
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
+#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
+#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
+#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
+#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
+//MMEA0_SDP_ARB_FINAL
+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
+#define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT                                                          0x1c
+#define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT                                                          0x1d
+#define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT                                                           0x1e
+#define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT                                                           0x1f
+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
+#define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK                                                            0x10000000L
+#define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK                                                            0x20000000L
+#define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK                                                             0x40000000L
+#define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK                                                             0x80000000L
+//MMEA0_SDP_DRAM_PRIORITY
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
+//MMEA0_SDP_IO_PRIORITY
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
+//MMEA0_SDP_CREDITS
+#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
+#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
+#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
+#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
+#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
+#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
+//MMEA0_SDP_TAG_RESERVE0
+#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
+#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
+#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
+#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
+#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
+#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
+#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
+#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
+//MMEA0_SDP_TAG_RESERVE1
+#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
+#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
+#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
+#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
+#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
+#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
+#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
+#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
+//MMEA0_SDP_VCC_RESERVE0
+#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
+#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
+#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
+#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
+#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
+#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
+#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
+#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
+#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
+#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
+//MMEA0_SDP_VCC_RESERVE1
+#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
+#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
+#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
+#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
+#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
+#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
+#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
+#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
+//MMEA0_SDP_VCD_RESERVE0
+#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
+#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
+#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
+#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
+#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
+#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
+#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
+#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
+#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
+#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
+//MMEA0_SDP_VCD_RESERVE1
+#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
+#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
+#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
+#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
+#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
+#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
+#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
+#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
+//MMEA0_SDP_REQ_CNTL
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
+#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT                                                       0x6
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT                                                      0x8
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT                                                     0xa
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
+#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK                                                         0x000000C0L
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK                                                        0x00000300L
+#define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK                                                       0x00000C00L
+//MMEA0_MISC
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
+#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
+#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
+#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
+#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
+#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
+#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
+#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
+#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
+#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
+#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
+//MMEA0_LATENCY_SAMPLING
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
+//MMEA0_PERFCOUNTER_LO
+#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
+#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
+//MMEA0_PERFCOUNTER_HI
+#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
+#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
+#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
+#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
+//MMEA0_PERFCOUNTER0_CFG
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
+#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
+#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
+#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
+#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
+#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
+#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
+//MMEA0_PERFCOUNTER1_CFG
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
+#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
+#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
+#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
+#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
+#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
+#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
+//MMEA0_PERFCOUNTER_RSLT_CNTL
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
+//MMEA0_EDC_CNT
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT                                                          0x14
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT                                                          0x16
+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x18
+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x1a
+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x1c
+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1e
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK                                                            0x00300000L
+#define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK                                                            0x00C00000L
+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x03000000L
+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x0C000000L
+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x30000000L
+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0xC0000000L
+//MMEA0_EDC_CNT2
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
+#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
+#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
+#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
+#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
+#define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT                                                            0x18
+#define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT                                                            0x1a
+#define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT                                                            0x1c
+#define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT                                                            0x1e
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
+#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
+#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
+#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
+#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
+#define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK                                                              0x03000000L
+#define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK                                                              0x0C000000L
+#define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK                                                              0x30000000L
+#define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK                                                              0xC0000000L
+//MMEA0_DSM_CNTL
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
+#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
+#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
+//MMEA0_DSM_CNTLA
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
+//MMEA0_DSM_CNTLB
+#define MMEA0_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT                                                  0x0
+#define MMEA0_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0x2
+#define MMEA0_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT                                                  0x3
+#define MMEA0_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0x5
+#define MMEA0_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT                                                  0x6
+#define MMEA0_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0x8
+#define MMEA0_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT                                                  0x9
+#define MMEA0_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xb
+#define MMEA0_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK                                                    0x00000003L
+#define MMEA0_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00000004L
+#define MMEA0_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK                                                    0x00000018L
+#define MMEA0_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00000020L
+#define MMEA0_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK                                                    0x000000C0L
+#define MMEA0_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00000100L
+#define MMEA0_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK                                                    0x00000600L
+#define MMEA0_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00000800L
+//MMEA0_DSM_CNTL2
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
+#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
+#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
+//MMEA0_DSM_CNTL2A
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
+//MMEA0_DSM_CNTL2B
+#define MMEA0_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT                                                0x0
+#define MMEA0_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT                                                0x2
+#define MMEA0_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT                                                0x3
+#define MMEA0_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT                                                0x5
+#define MMEA0_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT                                                0x6
+#define MMEA0_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT                                                0x8
+#define MMEA0_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT                                                0x9
+#define MMEA0_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT                                                0xb
+#define MMEA0_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK                                                  0x00000003L
+#define MMEA0_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK                                                  0x00000004L
+#define MMEA0_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK                                                  0x00000018L
+#define MMEA0_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK                                                  0x00000020L
+#define MMEA0_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK                                                  0x000000C0L
+#define MMEA0_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK                                                  0x00000100L
+#define MMEA0_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK                                                  0x00000600L
+#define MMEA0_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK                                                  0x00000800L
+//MMEA0_CGTT_CLK_CTRL
+#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
+#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
+#define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
+#define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
+#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
+#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
+#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
+#define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
+#define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
+#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
+//MMEA0_EDC_MODE
+#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
+#define MMEA0_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
+#define MMEA0_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
+#define MMEA0_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
+#define MMEA0_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
+#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
+#define MMEA0_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
+#define MMEA0_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
+#define MMEA0_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
+#define MMEA0_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
+//MMEA0_ERR_STATUS
+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
+#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
+#define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT                                                             0xe
+#define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT                                                           0xf
+#define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT                                                   0x10
+#define MMEA0_ERR_STATUS__LEVEL_INTERRUPT__SHIFT                                                              0x11
+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
+#define MMEA0_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
+#define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED_MASK                                                               0x00004000L
+#define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL_MASK                                                             0x00008000L
+#define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK                                                     0x00010000L
+#define MMEA0_ERR_STATUS__LEVEL_INTERRUPT_MASK                                                                0x00020000L
+//MMEA0_MISC2
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
+#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
+#define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
+#define MMEA0_MISC2__BLOCK_REQUESTS__SHIFT                                                                    0xe
+#define MMEA0_MISC2__REQUESTS_BLOCKED__SHIFT                                                                  0xf
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
+#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
+#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
+#define MMEA0_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
+#define MMEA0_MISC2__BLOCK_REQUESTS_MASK                                                                      0x00004000L
+#define MMEA0_MISC2__REQUESTS_BLOCKED_MASK                                                                    0x00008000L
+//MMEA0_ADDRDEC_SELECT
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
+#define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE__SHIFT                                                         0x14
+#define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE__SHIFT                                                          0x15
+#define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB__SHIFT                                                            0x16
+#define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB__SHIFT                                                             0x17
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
+#define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE_MASK                                                           0x00100000L
+#define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE_MASK                                                            0x00200000L
+#define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB_MASK                                                              0x00400000L
+#define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB_MASK                                                               0x00800000L
+//MMEA0_EDC_CNT3
+#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
+#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
+#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
+#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
+#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0x8
+#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
+#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
+#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
+#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
+#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
+#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000300L
+#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
+//MMEA0_SDP_PRIORITY_OVERRIDE
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT                                                0x0
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT                                               0x4
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT                                          0x9
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT                                          0xa
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT                                           0xb
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT                                           0xc
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT                                            0xd
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT                                            0xe
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT                                                0x10
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT                                               0x14
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT                                          0x19
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT                                          0x1a
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT                                           0x1b
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT                                           0x1c
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT                                            0x1d
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT                                            0x1e
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK                                                  0x0000000FL
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK                                                 0x000001F0L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK                                            0x00000200L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK                                            0x00000400L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK                                             0x00000800L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK                                             0x00001000L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK                                              0x00002000L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK                                              0x00004000L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK                                                  0x000F0000L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK                                                 0x01F00000L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK                                            0x02000000L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK                                            0x04000000L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK                                             0x08000000L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK                                             0x10000000L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK                                              0x20000000L
+#define MMEA0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK                                              0x40000000L
+//MMEA0_MISC_AON
+#define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT                                                     0x0
+#define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT                                                  0x2
+#define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK                                                       0x00000003L
+#define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK                                                    0x00000004L
+
+
+// addressBlock: mmhub_pctldec
+//PCTL_CTRL
+#define PCTL_CTRL__PG_ENABLE__SHIFT                                                                           0x0
+#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT                                                               0x1
+#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT                                                          0xe
+#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT                                                      0x13
+#define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT                                                                   0x14
+#define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT                                                                 0x15
+#define PCTL_CTRL__PG_ENABLE_MASK                                                                             0x00000001L
+#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK                                                                 0x0000000EL
+#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK                                                            0x0007C000L
+#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK                                                        0x00080000L
+#define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK                                                                     0x00100000L
+#define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK                                                                   0x00200000L
+//PCTL_MMHUB_DEEPSLEEP_IB
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT                                                                   0x0
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT                                                                   0x1
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT                                                                   0x2
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT                                                                   0x3
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT                                                                   0x4
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT                                                                   0x5
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT                                                                   0x6
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT                                                                   0x7
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT                                                                   0x8
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT                                                                   0x9
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT                                                                  0xa
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT                                                                  0xb
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT                                                                  0xc
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT                                                                  0xd
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT                                                                  0xe
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT                                                                  0xf
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT                                                                  0x10
+#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT                                                              0x1f
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK                                                                     0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK                                                                     0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK                                                                     0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK                                                                     0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK                                                                     0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK                                                                     0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK                                                                     0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK                                                                     0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK                                                                     0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK                                                                     0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK                                                                    0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK                                                                    0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK                                                                    0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK                                                                    0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK                                                                    0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK                                                                    0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK                                                                    0x00010000L
+#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK                                                                0x80000000L
+//PCTL_MMHUB_DEEPSLEEP_OVERRIDE
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT                                                             0x0
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT                                                             0x1
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT                                                             0x2
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT                                                             0x3
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT                                                             0x4
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT                                                             0x5
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT                                                             0x6
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT                                                             0x7
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT                                                             0x8
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT                                                             0x9
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT                                                            0xa
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT                                                            0xb
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT                                                            0xc
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT                                                            0xd
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT                                                            0xe
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT                                                            0xf
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT                                                            0x10
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT                                                        0x11
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK                                                               0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK                                                               0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK                                                               0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK                                                               0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK                                                               0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK                                                               0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK                                                               0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK                                                               0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK                                                               0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK                                                               0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK                                                              0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK                                                              0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK                                                              0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK                                                              0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK                                                              0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK                                                              0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK                                                              0x00010000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK                                                          0x00020000L
+//PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT                                                          0x0
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT                                                          0x1
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT                                                          0x2
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT                                                          0x3
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT                                                          0x4
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT                                                          0x5
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT                                                          0x6
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT                                                          0x7
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT                                                          0x8
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT                                                          0x9
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT                                                         0xa
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT                                                         0xb
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT                                                         0xc
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT                                                         0xd
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT                                                         0xe
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT                                                         0xf
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT                                                         0x10
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK                                                            0x00000001L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK                                                            0x00000002L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK                                                            0x00000004L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK                                                            0x00000008L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK                                                            0x00000010L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK                                                            0x00000020L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK                                                            0x00000040L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK                                                            0x00000080L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK                                                            0x00000100L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK                                                            0x00000200L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK                                                           0x00000400L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK                                                           0x00000800L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK                                                           0x00001000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK                                                           0x00002000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK                                                           0x00004000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK                                                           0x00008000L
+#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK                                                           0x00010000L
+//PCTL_PG_IGNORE_DEEPSLEEP
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT                                                                  0x0
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT                                                                  0x1
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT                                                                  0x2
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT                                                                  0x3
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT                                                                  0x4
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT                                                                  0x5
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT                                                                  0x6
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT                                                                  0x7
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT                                                                  0x8
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT                                                                  0x9
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT                                                                 0xa
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT                                                                 0xb
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT                                                                 0xc
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT                                                                 0xd
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT                                                                 0xe
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT                                                                 0xf
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT                                                                 0x10
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT                                                             0x11
+#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT                                                               0x12
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK                                                                    0x00000001L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK                                                                    0x00000002L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK                                                                    0x00000004L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK                                                                    0x00000008L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK                                                                    0x00000010L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK                                                                    0x00000020L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK                                                                    0x00000040L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK                                                                    0x00000080L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK                                                                    0x00000100L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK                                                                    0x00000200L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK                                                                   0x00000400L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK                                                                   0x00000800L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK                                                                   0x00001000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK                                                                   0x00002000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK                                                                   0x00004000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK                                                                   0x00008000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK                                                                   0x00010000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK                                                               0x00020000L
+#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK                                                                 0x00040000L
+//PCTL_PG_IGNORE_DEEPSLEEP_IB
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT                                                               0x0
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT                                                               0x1
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT                                                               0x2
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT                                                               0x3
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT                                                               0x4
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT                                                               0x5
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT                                                               0x6
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT                                                               0x7
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT                                                               0x8
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT                                                               0x9
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT                                                              0xa
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT                                                              0xb
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT                                                              0xc
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT                                                              0xd
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT                                                              0xe
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT                                                              0xf
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT                                                              0x10
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT                                                            0x11
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK                                                                 0x00000001L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK                                                                 0x00000002L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK                                                                 0x00000004L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK                                                                 0x00000008L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK                                                                 0x00000010L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK                                                                 0x00000020L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK                                                                 0x00000040L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK                                                                 0x00000080L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK                                                                 0x00000100L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK                                                                 0x00000200L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK                                                                0x00000400L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK                                                                0x00000800L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK                                                                0x00001000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK                                                                0x00002000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK                                                                0x00004000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK                                                                0x00008000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK                                                                0x00010000L
+#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK                                                              0x00020000L
+//PCTL_SLICE0_CFG_DAGB_WRBUSY
+#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT                                                          0x0
+#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
+//PCTL_SLICE0_CFG_DAGB_RDBUSY
+#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT                                                          0x0
+#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
+//PCTL_SLICE0_CFG_DS_ALLOW
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT                                                                  0x0
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT                                                                  0x1
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT                                                                  0x2
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT                                                                  0x3
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT                                                                  0x4
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT                                                                  0x5
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT                                                                  0x6
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT                                                                  0x7
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT                                                                  0x8
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT                                                                  0x9
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT                                                                 0xa
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT                                                                 0xb
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT                                                                 0xc
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT                                                                 0xd
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT                                                                 0xe
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT                                                                 0xf
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT                                                                 0x10
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK                                                                    0x00000001L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK                                                                    0x00000002L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK                                                                    0x00000004L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK                                                                    0x00000008L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK                                                                    0x00000010L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK                                                                    0x00000020L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK                                                                    0x00000040L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK                                                                    0x00000080L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK                                                                    0x00000100L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK                                                                    0x00000200L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK                                                                   0x00000400L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK                                                                   0x00000800L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK                                                                   0x00001000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK                                                                   0x00002000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK                                                                   0x00004000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK                                                                   0x00008000L
+#define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK                                                                   0x00010000L
+//PCTL_SLICE0_CFG_DS_ALLOW_IB
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT                                                               0x0
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT                                                               0x1
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT                                                               0x2
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT                                                               0x3
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT                                                               0x4
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT                                                               0x5
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT                                                               0x6
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT                                                               0x7
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT                                                               0x8
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT                                                               0x9
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT                                                              0xa
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT                                                              0xb
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT                                                              0xc
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT                                                              0xd
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT                                                              0xe
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT                                                              0xf
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT                                                              0x10
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK                                                                 0x00000001L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK                                                                 0x00000002L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK                                                                 0x00000004L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK                                                                 0x00000008L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK                                                                 0x00000010L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK                                                                 0x00000020L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK                                                                 0x00000040L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK                                                                 0x00000080L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK                                                                 0x00000100L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK                                                                 0x00000200L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK                                                                0x00000400L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK                                                                0x00000800L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK                                                                0x00001000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK                                                                0x00002000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK                                                                0x00004000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK                                                                0x00008000L
+#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK                                                                0x00010000L
+//PCTL_SLICE1_CFG_DAGB_WRBUSY
+#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT                                                          0x0
+#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
+//PCTL_SLICE1_CFG_DAGB_RDBUSY
+#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT                                                          0x0
+#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
+//PCTL_SLICE1_CFG_DS_ALLOW
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT                                                                  0x0
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT                                                                  0x1
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT                                                                  0x2
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT                                                                  0x3
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT                                                                  0x4
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT                                                                  0x5
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT                                                                  0x6
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT                                                                  0x7
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT                                                                  0x8
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT                                                                  0x9
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT                                                                 0xa
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT                                                                 0xb
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT                                                                 0xc
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT                                                                 0xd
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT                                                                 0xe
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT                                                                 0xf
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT                                                                 0x10
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK                                                                    0x00000001L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK                                                                    0x00000002L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK                                                                    0x00000004L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK                                                                    0x00000008L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK                                                                    0x00000010L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK                                                                    0x00000020L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK                                                                    0x00000040L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK                                                                    0x00000080L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK                                                                    0x00000100L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK                                                                    0x00000200L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK                                                                   0x00000400L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK                                                                   0x00000800L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK                                                                   0x00001000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK                                                                   0x00002000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK                                                                   0x00004000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK                                                                   0x00008000L
+#define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK                                                                   0x00010000L
+//PCTL_SLICE1_CFG_DS_ALLOW_IB
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT                                                               0x0
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT                                                               0x1
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT                                                               0x2
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT                                                               0x3
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT                                                               0x4
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT                                                               0x5
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT                                                               0x6
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT                                                               0x7
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT                                                               0x8
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT                                                               0x9
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT                                                              0xa
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT                                                              0xb
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT                                                              0xc
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT                                                              0xd
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT                                                              0xe
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT                                                              0xf
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT                                                              0x10
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK                                                                 0x00000001L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK                                                                 0x00000002L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK                                                                 0x00000004L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK                                                                 0x00000008L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK                                                                 0x00000010L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK                                                                 0x00000020L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK                                                                 0x00000040L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK                                                                 0x00000080L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK                                                                 0x00000100L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK                                                                 0x00000200L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK                                                                0x00000400L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK                                                                0x00000800L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK                                                                0x00001000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK                                                                0x00002000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK                                                                0x00004000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK                                                                0x00008000L
+#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK                                                                0x00010000L
+//PCTL_UTCL2_MISC
+#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                            0xb
+#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                           0xc
+#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                            0xf
+#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                   0x10
+#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                    0x11
+#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT                                                               0x12
+#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK                                                              0x00000800L
+#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK                                                             0x00007000L
+#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK                                                              0x00008000L
+#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                     0x00010000L
+#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                      0x00020000L
+#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK                                                                 0x00040000L
+//PCTL_SLICE0_MISC
+#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT                                                           0xa
+#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                          0xb
+#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                           0xe
+#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                  0xf
+#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                            0x10
+#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                   0x11
+#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT                                                              0x12
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT                                                          0x13
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT                                                          0x14
+#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK                                                             0x00000400L
+#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK                                                            0x00003800L
+#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK                                                             0x00004000L
+#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                    0x00008000L
+#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK                                                              0x00010000L
+#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                     0x00020000L
+#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK                                                                0x00040000L
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK                                                            0x00080000L
+#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK                                                            0x00100000L
+//PCTL_SLICE1_MISC
+#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT                                                           0xa
+#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                          0xb
+#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                           0xe
+#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                  0xf
+#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                            0x10
+#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                   0x11
+#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT                                                              0x12
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT                                                          0x13
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT                                                          0x14
+#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK                                                             0x00000400L
+#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK                                                            0x00003800L
+#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK                                                             0x00004000L
+#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                    0x00008000L
+#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK                                                              0x00010000L
+#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                     0x00020000L
+#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK                                                                0x00040000L
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK                                                            0x00080000L
+#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK                                                            0x00100000L
+//PCTL_RENG_CTRL
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT                                                               0x0
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT                                                          0x1
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK                                                                 0x00000001L
+#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK                                                            0x00000002L
+//PCTL_UTCL2_RENG_EXECUTE
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                      0x0
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                 0x1
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                            0x2
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                  0xd
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                        0x00000001L
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                   0x00000002L
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                              0x00001FFCL
+#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                    0x00FFE000L
+//PCTL_SLICE0_RENG_EXECUTE
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                     0x0
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                0x1
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                           0x2
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                 0xc
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                       0x00000001L
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                  0x00000002L
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                             0x00000FFCL
+#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                   0x003FF000L
+//PCTL_SLICE1_RENG_EXECUTE
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                     0x0
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                0x1
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                           0x2
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                 0xc
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                       0x00000001L
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                  0x00000002L
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                             0x00000FFCL
+#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                   0x003FF000L
+//PCTL_UTCL2_RENG_RAM_INDEX
+#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                      0x0
+#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                        0x000007FFL
+//PCTL_UTCL2_RENG_RAM_DATA
+#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                        0x0
+#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                          0xFFFFFFFFL
+//PCTL_SLICE0_RENG_RAM_INDEX
+#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                     0x0
+#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                       0x000003FFL
+//PCTL_SLICE0_RENG_RAM_DATA
+#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                       0x0
+#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                         0xFFFFFFFFL
+//PCTL_SLICE1_RENG_RAM_INDEX
+#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                     0x0
+#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                       0x000003FFL
+//PCTL_SLICE1_RENG_RAM_DATA
+#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                       0x0
+#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                         0xFFFFFFFFL
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                          0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                          0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                            0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                            0xFFFF0000L
+//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT                          0x0
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT                          0x10
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK                            0x0000FFFFL
+#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK                            0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
+//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT                         0x0
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT                         0x10
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK                           0x0000FFFFL
+#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK                           0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
+//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT                         0x0
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT                         0x10
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK                           0x0000FFFFL
+#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK                           0xFFFF0000L
+//PCTL_STATUS
+#define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT                                                                  0x0
+#define PCTL_STATUS__MMHUB_POWER__SHIFT                                                                       0xb
+#define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT                                                              0xc
+#define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT                                                             0xd
+#define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT                                                             0xe
+#define PCTL_STATUS__PGFSM_CMD_STATUS_MASK                                                                    0x00000003L
+#define PCTL_STATUS__MMHUB_POWER_MASK                                                                         0x00000800L
+#define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK                                                                0x00001000L
+#define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK                                                               0x00002000L
+#define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK                                                               0x00004000L
+//PCTL_PERFCOUNTER_LO
+#define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                                0x0
+#define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                  0xFFFFFFFFL
+//PCTL_PERFCOUNTER_HI
+#define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                                0x0
+#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                             0x10
+#define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                  0x0000FFFFL
+#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                               0xFFFF0000L
+//PCTL_PERFCOUNTER0_CFG
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                                0x0
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                            0x8
+#define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                               0x18
+#define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                  0x1c
+#define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                   0x1d
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                  0x000000FFL
+#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
+#define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                 0x0F000000L
+#define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK                                                                    0x10000000L
+#define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK                                                                     0x20000000L
+//PCTL_PERFCOUNTER1_CFG
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                                0x0
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                            0x8
+#define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                               0x18
+#define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                  0x1c
+#define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                   0x1d
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                  0x000000FFL
+#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
+#define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                 0x0F000000L
+#define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK                                                                    0x10000000L
+#define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK                                                                     0x20000000L
+//PCTL_PERFCOUNTER_RSLT_CNTL
+#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                                0x0
+#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                      0x8
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                       0x10
+#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                         0x18
+#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                          0x19
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                               0x1a
+#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                  0x0000000FL
+#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                        0x0000FF00L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                         0x00FF0000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                           0x01000000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                            0x02000000L
+#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                 0x04000000L
+//PCTL_RESERVED_0
+#define PCTL_RESERVED_0__WORD__SHIFT                                                                          0x0
+#define PCTL_RESERVED_0__BYTE__SHIFT                                                                          0x10
+#define PCTL_RESERVED_0__BIT7__SHIFT                                                                          0x18
+#define PCTL_RESERVED_0__BIT6__SHIFT                                                                          0x19
+#define PCTL_RESERVED_0__BIT5__SHIFT                                                                          0x1a
+#define PCTL_RESERVED_0__BIT4__SHIFT                                                                          0x1b
+#define PCTL_RESERVED_0__BIT3__SHIFT                                                                          0x1c
+#define PCTL_RESERVED_0__BIT2__SHIFT                                                                          0x1d
+#define PCTL_RESERVED_0__BIT1__SHIFT                                                                          0x1e
+#define PCTL_RESERVED_0__BIT0__SHIFT                                                                          0x1f
+#define PCTL_RESERVED_0__WORD_MASK                                                                            0x0000FFFFL
+#define PCTL_RESERVED_0__BYTE_MASK                                                                            0x00FF0000L
+#define PCTL_RESERVED_0__BIT7_MASK                                                                            0x01000000L
+#define PCTL_RESERVED_0__BIT6_MASK                                                                            0x02000000L
+#define PCTL_RESERVED_0__BIT5_MASK                                                                            0x04000000L
+#define PCTL_RESERVED_0__BIT4_MASK                                                                            0x08000000L
+#define PCTL_RESERVED_0__BIT3_MASK                                                                            0x10000000L
+#define PCTL_RESERVED_0__BIT2_MASK                                                                            0x20000000L
+#define PCTL_RESERVED_0__BIT1_MASK                                                                            0x40000000L
+#define PCTL_RESERVED_0__BIT0_MASK                                                                            0x80000000L
+//PCTL_RESERVED_1
+#define PCTL_RESERVED_1__WORD__SHIFT                                                                          0x0
+#define PCTL_RESERVED_1__BYTE__SHIFT                                                                          0x10
+#define PCTL_RESERVED_1__BIT7__SHIFT                                                                          0x18
+#define PCTL_RESERVED_1__BIT6__SHIFT                                                                          0x19
+#define PCTL_RESERVED_1__BIT5__SHIFT                                                                          0x1a
+#define PCTL_RESERVED_1__BIT4__SHIFT                                                                          0x1b
+#define PCTL_RESERVED_1__BIT3__SHIFT                                                                          0x1c
+#define PCTL_RESERVED_1__BIT2__SHIFT                                                                          0x1d
+#define PCTL_RESERVED_1__BIT1__SHIFT                                                                          0x1e
+#define PCTL_RESERVED_1__BIT0__SHIFT                                                                          0x1f
+#define PCTL_RESERVED_1__WORD_MASK                                                                            0x0000FFFFL
+#define PCTL_RESERVED_1__BYTE_MASK                                                                            0x00FF0000L
+#define PCTL_RESERVED_1__BIT7_MASK                                                                            0x01000000L
+#define PCTL_RESERVED_1__BIT6_MASK                                                                            0x02000000L
+#define PCTL_RESERVED_1__BIT5_MASK                                                                            0x04000000L
+#define PCTL_RESERVED_1__BIT4_MASK                                                                            0x08000000L
+#define PCTL_RESERVED_1__BIT3_MASK                                                                            0x10000000L
+#define PCTL_RESERVED_1__BIT2_MASK                                                                            0x20000000L
+#define PCTL_RESERVED_1__BIT1_MASK                                                                            0x40000000L
+#define PCTL_RESERVED_1__BIT0_MASK                                                                            0x80000000L
+//PCTL_RESERVED_2
+#define PCTL_RESERVED_2__WORD__SHIFT                                                                          0x0
+#define PCTL_RESERVED_2__BYTE__SHIFT                                                                          0x10
+#define PCTL_RESERVED_2__BIT7__SHIFT                                                                          0x18
+#define PCTL_RESERVED_2__BIT6__SHIFT                                                                          0x19
+#define PCTL_RESERVED_2__BIT5__SHIFT                                                                          0x1a
+#define PCTL_RESERVED_2__BIT4__SHIFT                                                                          0x1b
+#define PCTL_RESERVED_2__BIT3__SHIFT                                                                          0x1c
+#define PCTL_RESERVED_2__BIT2__SHIFT                                                                          0x1d
+#define PCTL_RESERVED_2__BIT1__SHIFT                                                                          0x1e
+#define PCTL_RESERVED_2__BIT0__SHIFT                                                                          0x1f
+#define PCTL_RESERVED_2__WORD_MASK                                                                            0x0000FFFFL
+#define PCTL_RESERVED_2__BYTE_MASK                                                                            0x00FF0000L
+#define PCTL_RESERVED_2__BIT7_MASK                                                                            0x01000000L
+#define PCTL_RESERVED_2__BIT6_MASK                                                                            0x02000000L
+#define PCTL_RESERVED_2__BIT5_MASK                                                                            0x04000000L
+#define PCTL_RESERVED_2__BIT4_MASK                                                                            0x08000000L
+#define PCTL_RESERVED_2__BIT3_MASK                                                                            0x10000000L
+#define PCTL_RESERVED_2__BIT2_MASK                                                                            0x20000000L
+#define PCTL_RESERVED_2__BIT1_MASK                                                                            0x40000000L
+#define PCTL_RESERVED_2__BIT0_MASK                                                                            0x80000000L
+//PCTL_RESERVED_3
+#define PCTL_RESERVED_3__WORD__SHIFT                                                                          0x0
+#define PCTL_RESERVED_3__BYTE__SHIFT                                                                          0x10
+#define PCTL_RESERVED_3__BIT7__SHIFT                                                                          0x18
+#define PCTL_RESERVED_3__BIT6__SHIFT                                                                          0x19
+#define PCTL_RESERVED_3__BIT5__SHIFT                                                                          0x1a
+#define PCTL_RESERVED_3__BIT4__SHIFT                                                                          0x1b
+#define PCTL_RESERVED_3__BIT3__SHIFT                                                                          0x1c
+#define PCTL_RESERVED_3__BIT2__SHIFT                                                                          0x1d
+#define PCTL_RESERVED_3__BIT1__SHIFT                                                                          0x1e
+#define PCTL_RESERVED_3__BIT0__SHIFT                                                                          0x1f
+#define PCTL_RESERVED_3__WORD_MASK                                                                            0x0000FFFFL
+#define PCTL_RESERVED_3__BYTE_MASK                                                                            0x00FF0000L
+#define PCTL_RESERVED_3__BIT7_MASK                                                                            0x01000000L
+#define PCTL_RESERVED_3__BIT6_MASK                                                                            0x02000000L
+#define PCTL_RESERVED_3__BIT5_MASK                                                                            0x04000000L
+#define PCTL_RESERVED_3__BIT4_MASK                                                                            0x08000000L
+#define PCTL_RESERVED_3__BIT3_MASK                                                                            0x10000000L
+#define PCTL_RESERVED_3__BIT2_MASK                                                                            0x20000000L
+#define PCTL_RESERVED_3__BIT1_MASK                                                                            0x40000000L
+#define PCTL_RESERVED_3__BIT0_MASK                                                                            0x80000000L
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pfdec
+//MMMC_VM_MX_L1_TLB0_STATUS
+#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+//MMMC_VM_MX_L1_TLB1_STATUS
+#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+//MMMC_VM_MX_L1_TLB2_STATUS
+#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+//MMMC_VM_MX_L1_TLB3_STATUS
+#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+//MMMC_VM_MX_L1_TLB4_STATUS
+#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+//MMMC_VM_MX_L1_TLB5_STATUS
+#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+//MMMC_VM_MX_L1_TLB6_STATUS
+#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+//MMMC_VM_MX_L1_TLB7_STATUS
+#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT                                                                0x0
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
+#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK                                                                  0x00000001L
+#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1pldec
+//MMMC_VM_MX_L1_PERFCOUNTER0_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                      0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                         0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                          0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK                                                           0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK                                                            0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER1_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                      0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                         0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                          0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK                                                           0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK                                                            0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER2_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                      0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                         0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                          0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK                                                           0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK                                                            0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER3_CFG
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                      0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                         0x1c
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                          0x1d
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK                                                           0x10000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK                                                            0x20000000L
+//MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                             0x8
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                              0x10
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                0x18
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                 0x19
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                      0x1a
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                         0x0000000FL
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                               0x0000FF00L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                0x00FF0000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                  0x01000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                   0x02000000L
+#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                        0x04000000L
+
+
+// addressBlock: mmhub_l1tlb_mmutcl1prdec
+//MMMC_VM_MX_L1_PERFCOUNTER_LO
+#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                         0xFFFFFFFFL
+//MMMC_VM_MX_L1_PERFCOUNTER_HI
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                    0x10
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                         0x0000FFFFL
+#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                      0xFFFF0000L
+
+
+// addressBlock: mmhub_l1tlb_mmvmtlspfdec
+//MMMC_VM_MX_L1_TLS0_CNTL
+#define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x4
+#define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT                 0x5
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT__SHIFT                                                    0x6
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM__SHIFT                                                  0x8
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP__SHIFT                                                   0x9
+#define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT_MASK                                                          0x0000000FL
+#define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00000010L
+#define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK                   0x00000020L
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT_MASK                                                      0x000000C0L
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM_MASK                                                    0x00000100L
+#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP_MASK                                                     0x00000200L
+//MMMC_VM_MX_L1_TLS0_CNTL0
+#define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL0__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL0__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL1
+#define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL1__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL1__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL2
+#define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL2__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL2__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL3
+#define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL3__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL3__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL4
+#define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL4__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL4__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL5
+#define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL5__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL5__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL6
+#define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL6__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL6__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL7
+#define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL7__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL7__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL8
+#define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL8__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL8__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL9
+#define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID__SHIFT                                                        0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL9__EN__SHIFT                                                                   0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE__SHIFT                                                        0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID_MASK                                                          0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL9__EN_MASK                                                                     0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE_MASK                                                          0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL10
+#define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL10__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL10__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL11
+#define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL11__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL11__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL12
+#define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL12__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL12__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL13
+#define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL13__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL13__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL14
+#define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL14__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL14__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL15
+#define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL15__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL15__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL16
+#define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL16__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL16__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL17
+#define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL17__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL17__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL18
+#define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL18__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL18__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL19
+#define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL19__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL19__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL20
+#define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL20__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL20__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL21
+#define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL21__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL21__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL22
+#define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL22__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL22__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL23
+#define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL23__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL23__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL24
+#define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL24__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL24__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL25
+#define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL25__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL25__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL26
+#define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL26__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL26__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL27
+#define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL27__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL27__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL28
+#define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL28__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL28__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL29
+#define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL29__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL29__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL30
+#define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL30__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL30__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL31
+#define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL31__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL31__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL32
+#define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL32__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL32__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL33
+#define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL33__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL33__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL34
+#define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL34__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL34__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL35
+#define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL35__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL35__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL36
+#define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL36__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL36__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_CNTL37
+#define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID__SHIFT                                                       0x0
+#define MMMC_VM_MX_L1_TLS0_CNTL37__EN__SHIFT                                                                  0xc
+#define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE__SHIFT                                                       0xd
+#define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID_MASK                                                         0x000001FFL
+#define MMMC_VM_MX_L1_TLS0_CNTL37__EN_MASK                                                                    0x00001000L
+#define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE_MASK                                                         0x00002000L
+//MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4__SHIFT                                            0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32__SHIFT                                          0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4__SHIFT                                           0x0
+#define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4__SHIFT                                                0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32__SHIFT                                              0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4__SHIFT                                               0x0
+#define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32__SHIFT                              0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32_MASK                                0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6__SHIFT                               0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6_MASK                                 0x0000003FL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32__SHIFT            0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32_MASK              0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6__SHIFT             0x0
+#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6_MASK               0x0000003FL
+//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT                                        0x0
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT                                   0xc
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT                                   0x18
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT                                               0x19
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                             0x1d
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK                                          0x000000FFL
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK                                     0x001FF000L
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK                                     0x01000000L
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK                                                 0x1E000000L
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                               0x20000000L
+//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                          0x0
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                            0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                           0x0
+#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                             0x0000000FL
+//MMVM_L2_SAW_CNTL
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT                                                              0x0
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                0x1
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                0x2
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                0x4
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                            0x8
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                      0x9
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                     0xa
+#define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                     0xb
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                     0xc
+#define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                      0xf
+#define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                     0x12
+#define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                0x13
+#define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                  0x15
+#define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT                                              0x1a
+#define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT                                            0x1c
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK                                                                0x00000001L
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                  0x00000002L
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                  0x0000000CL
+#define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                  0x00000030L
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                              0x00000100L
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                        0x00000200L
+#define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                       0x00000400L
+#define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                       0x00000800L
+#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                       0x00007000L
+#define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                        0x00038000L
+#define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                       0x00040000L
+#define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                  0x00180000L
+#define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                    0x03E00000L
+#define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK                                                0x0C000000L
+#define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK                                              0x70000000L
+//MMVM_L2_SAW_CNTL2
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                      0x0
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                         0x1
+#define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                               0x15
+#define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                             0x16
+#define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT                                                     0x17
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                       0x1a
+#define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                    0x1c
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                        0x00000001L
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK                                                           0x00000002L
+#define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                 0x00200000L
+#define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                               0x00400000L
+#define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK                                                       0x03800000L
+#define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                         0x0C000000L
+#define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                      0x70000000L
+//MMVM_L2_SAW_CNTL3
+#define MMVM_L2_SAW_CNTL3__BANK_SELECT__SHIFT                                                                 0x0
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                        0x6
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                    0x8
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                 0xf
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                 0x14
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                  0x15
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                0x18
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                      0x1c
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                    0x1d
+#define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                        0x1e
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                   0x1f
+#define MMVM_L2_SAW_CNTL3__BANK_SELECT_MASK                                                                   0x0000003FL
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                          0x000000C0L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                      0x00001F00L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                   0x000F8000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                   0x00100000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                    0x00E00000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                  0x0F000000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                        0x10000000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                      0x20000000L
+#define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                          0x40000000L
+#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                     0x80000000L
+//MMVM_L2_SAW_CNTL4
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                 0x0
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT                                       0x6
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT                                         0x7
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT                                          0x8
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT                                       0x9
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT                                         0xa
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT                                          0xb
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT                                       0xc
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT                                         0xd
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT                                          0xe
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT                                       0xf
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT                                         0x10
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT                                          0x11
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT                                               0x12
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                   0x0000003FL
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK                                         0x00000040L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK                                           0x00000080L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK                                            0x00000100L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK                                         0x00000200L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK                                           0x00000400L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK                                            0x00000800L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK                                         0x00001000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK                                           0x00002000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK                                            0x00004000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK                                         0x00008000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK                                           0x00010000L
+#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK                                            0x00020000L
+#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK                                                 0x00040000L
+//MMVM_L2_SAW_CONTEXT0_CNTL
+#define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x3
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x4
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0x6
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0x7
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                   0xb
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xc
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xd
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                  0xe
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                   0x11
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x12
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x13
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                  0x14
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                0x17
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x18
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x1c
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x1d
+#define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000008L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000010L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000040L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00000080L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK                                     0x00000800L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00001000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00002000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK                                    0x00004000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK                                     0x00020000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00040000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00080000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK                                    0x00100000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK                                  0x00800000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x0F000000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x10000000L
+#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x20000000L
+//MMVM_L2_SAW_CONTEXT0_CNTL2
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                 0x0
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT  0x1
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT      0x2
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT              0x3
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT                                      0x4
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                   0x00000001L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK    0x00000002L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK        0x00000004L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK                0x00000008L
+#define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK                                        0x00000010L
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
+//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
+#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
+//MMVM_L2_SAW_CONTEXTS_DISABLE
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                0x0
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                0x1
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                0x2
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                0x3
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                0x4
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                0x5
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                0x6
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                0x7
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                0x8
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                0x9
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                               0xa
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                               0xb
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                               0xc
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                               0xd
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                               0xe
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                               0xf
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                  0x00000001L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                  0x00000002L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                  0x00000004L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                  0x00000008L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                  0x00000010L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                  0x00000020L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                  0x00000040L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                  0x00000080L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                  0x00000100L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                  0x00000200L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                 0x00000400L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                 0x00000800L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                 0x00001000L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                 0x00002000L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                 0x00004000L
+#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                 0x00008000L
+//MMVM_L2_SAW_PIPES_BUSY_LO32
+#define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32__SHIFT                                                   0x0
+#define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32_MASK                                                     0xFFFFFFFFL
+//MMVM_L2_SAW_PIPES_BUSY_HI32
+#define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32__SHIFT                                                   0x0
+#define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32_MASK                                                     0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS__SHIFT                                             0x0
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS__SHIFT                                            0x1
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID__SHIFT                                               0x3
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS_MASK                                               0x00000001L
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS_MASK                                              0x00000006L
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID_MASK                                                 0x000001F8L
+//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                             0x0
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                               0xFFFFFFFFL
+//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                              0x0
+#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                0x0000000FL
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2dec
+//MM_ATC_L2_CNTL
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                            0x0
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                           0x3
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                                0x6
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                               0x7
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT                                       0x8
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT                                      0xb
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                           0xe
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                          0xf
+#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                          0x10
+#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                       0x13
+#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT                                                            0x14
+#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT                                                          0x16
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                              0x00000003L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                             0x00000018L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                                  0x00000040L
+#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                                 0x00000080L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK                                         0x00000300L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK                                        0x00001800L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                             0x00004000L
+#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                            0x00008000L
+#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                            0x00070000L
+#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                         0x00080000L
+#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK                                                              0x00300000L
+#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK                                                            0x0FC00000L
+//MM_ATC_L2_CNTL2
+#define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                                   0x0
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                          0x6
+#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                           0x8
+#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                                  0x9
+#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                            0xc
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                      0xf
+#define MM_ATC_L2_CNTL2__BANK_SELECT_MASK                                                                     0x0000003FL
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                            0x000000C0L
+#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                             0x00000100L
+#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                                    0x00000E00L
+#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                              0x00007000L
+#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                        0x001F8000L
+//MM_ATC_L2_CACHE_DATA0
+#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                     0x0
+#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                       0x1
+#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                       0x2
+#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                               0x18
+#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                       0x00000001L
+#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                         0x00000002L
+#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                         0x00FFFFFCL
+#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                                 0x0F000000L
+//MM_ATC_L2_CACHE_DATA1
+#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                                0x0
+#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                                  0xFFFFFFFFL
+//MM_ATC_L2_CACHE_DATA2
+#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                                   0x0
+#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                     0xFFFFFFFFL
+//MM_ATC_L2_CNTL3
+#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT                                                 0x0
+#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT                                                   0x6
+#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT                                                   0xc
+#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                               0x12
+#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                     0x15
+#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT                                                     0x1b
+#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK                                                   0x0000003FL
+#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK                                                     0x00000FC0L
+#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK                                                     0x0003F000L
+#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                                 0x001C0000L
+#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                       0x07E00000L
+#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK                                                       0x38000000L
+//MM_ATC_L2_CNTL4
+#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT                                              0x0
+#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT                                                0x6
+#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT                                                0xc
+#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK                                                0x0000003FL
+#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK                                                  0x00000FC0L
+#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK                                                  0x0003F000L
+//MM_ATC_L2_CNTL5
+#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                       0x0
+#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                      0xa
+#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                         0x000003FFL
+#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                        0x000FFC00L
+//MM_ATC_L2_MM_GROUP_RT_CLASSES
+#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT                                                  0x0
+#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK                                                    0xFFFFFFFFL
+//MM_ATC_L2_STATUS
+#define MM_ATC_L2_STATUS__BUSY__SHIFT                                                                         0x0
+#define MM_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT                                                            0x1
+#define MM_ATC_L2_STATUS__BUSY_MASK                                                                           0x00000001L
+#define MM_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK                                                              0x3FFFFFFEL
+//MM_ATC_L2_STATUS2
+#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT                                           0x0
+#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT                                               0x8
+#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK                                             0x000000FFL
+#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK                                                 0x0000FF00L
+//MM_ATC_L2_MISC_CG
+#define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                      0x6
+#define MM_ATC_L2_MISC_CG__ENABLE__SHIFT                                                                      0x12
+#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                               0x13
+#define MM_ATC_L2_MISC_CG__OFFDLY_MASK                                                                        0x00000FC0L
+#define MM_ATC_L2_MISC_CG__ENABLE_MASK                                                                        0x00040000L
+#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                                 0x00080000L
+//MM_ATC_L2_MEM_POWER_LS
+#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                               0x0
+#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                                0x6
+#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                                 0x0000003FL
+#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                                  0x00000FC0L
+//MM_ATC_L2_CGTT_CLK_CTRL
+#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                              0x0
+#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                        0x4
+#define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                         0xf
+#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                   0x10
+#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                         0x18
+#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                0x0000000FL
+#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                          0x00000FF0L
+#define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                           0x00008000L
+#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                     0x00FF0000L
+#define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                           0xFF000000L
+//MM_ATC_L2_SDPPORT_CTRL
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT                                                      0x0
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT                                                   0x1
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT                                                  0x2
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT                                               0x3
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT                                                      0x4
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT                                                   0x5
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT                                                        0x6
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT                                                     0x7
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT                                                   0x8
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT                                                0x9
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK                                                        0x00000001L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK                                                     0x00000002L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK                                                    0x00000004L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK                                                 0x00000008L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK                                                        0x00000010L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK                                                     0x00000020L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK                                                          0x00000040L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK                                                       0x00000080L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK                                                     0x00000100L
+#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK                                                  0x00000200L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pfdec
+//MMVM_L2_CNTL
+#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                                  0x0
+#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                    0x1
+#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                    0x2
+#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                    0x4
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                                0x8
+#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                          0x9
+#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                         0xa
+#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                         0xb
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                         0xc
+#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                          0xf
+#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                         0x12
+#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                    0x13
+#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                      0x15
+#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                           0x1a
+#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                                    0x00000001L
+#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                      0x00000002L
+#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                      0x0000000CL
+#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                      0x00000030L
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                                  0x00000100L
+#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                            0x00000200L
+#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                           0x00000400L
+#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                           0x00000800L
+#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                           0x00007000L
+#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                            0x00038000L
+#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                           0x00040000L
+#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                      0x00180000L
+#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                        0x03E00000L
+#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                             0x0C000000L
+//MMVM_L2_CNTL2
+#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                          0x0
+#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                             0x1
+#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                                   0x15
+#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                                 0x16
+#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                          0x17
+#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                           0x1a
+#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                        0x1c
+#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                            0x00000001L
+#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                               0x00000002L
+#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                     0x00200000L
+#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                                   0x00400000L
+#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                            0x03800000L
+#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                             0x0C000000L
+#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                          0x70000000L
+//MMVM_L2_CNTL3
+#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT                                                                     0x0
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                            0x6
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                        0x8
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                     0xf
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                     0x14
+#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                      0x15
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                    0x18
+#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                          0x1c
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                        0x1d
+#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                            0x1e
+#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                       0x1f
+#define MMVM_L2_CNTL3__BANK_SELECT_MASK                                                                       0x0000003FL
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                              0x000000C0L
+#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                          0x00001F00L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                       0x000F8000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                       0x00100000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                        0x00E00000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                      0x0F000000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                            0x10000000L
+#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                          0x20000000L
+#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                              0x40000000L
+#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                         0x80000000L
+//MMVM_L2_STATUS
+#define MMVM_L2_STATUS__L2_BUSY__SHIFT                                                                        0x0
+#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                            0x1
+#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                               0x11
+#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                             0x12
+#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                                 0x13
+#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                                 0x14
+#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                                 0x15
+#define MMVM_L2_STATUS__L2_BUSY_MASK                                                                          0x00000001L
+#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                              0x0001FFFEL
+#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                                 0x00020000L
+#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                               0x00040000L
+#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                                   0x00080000L
+#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                                   0x00100000L
+#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                                   0x00200000L
+//MMVM_DUMMY_PAGE_FAULT_CNTL
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                            0x0
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                         0x1
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                            0x2
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                              0x00000001L
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                           0x00000002L
+#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                              0x000000FCL
+//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                          0x0
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                            0xFFFFFFFFL
+//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                           0x0
+#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                             0x0000000FL
+//MMVM_INVALIDATE_CNTL
+#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT                                                      0x0
+#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT                                                      0x8
+#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK                                                        0x000000FFL
+#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK                                                        0x0000FF00L
+//MMVM_L2_PROTECTION_FAULT_CNTL
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                              0x0
+#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT           0x1
+#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0x2
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x3
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x4
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x5
+#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT               0x6
+#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x7
+#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x8
+#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0x9
+#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0xa
+#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xb
+#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                         0xc
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                              0xd
+#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                        0x1d
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                         0x1e
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                            0x1f
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                0x00000001L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK             0x00000002L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000004L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000008L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000010L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000020L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                 0x00000040L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000080L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000100L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000200L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000400L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000800L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                           0x00001000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                                0x1FFFE000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                          0x20000000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                           0x40000000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                              0x80000000L
+//MMVM_L2_PROTECTION_FAULT_CNTL2
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                                  0x0
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                            0x10
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                      0x11
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                           0x12
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                                   0x13
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                    0x0000FFFFL
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                              0x00010000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                        0x00020000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                             0x00040000L
+#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                                     0x00080000L
+//MMVM_L2_PROTECTION_FAULT_MM_CNTL3
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                0x0
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                  0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_MM_CNTL4
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT               0x0
+#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                 0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_STATUS
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                                   0x0
+#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                                  0x1
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                             0x4
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                                 0x8
+#define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                           0x9
+#define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                            0x12
+#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                        0x13
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                          0x14
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                            0x18
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                          0x19
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                                     0x00000001L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                                    0x0000000EL
+#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                               0x000000F0L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                                   0x00000100L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                             0x0003FE00L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                              0x00040000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                          0x00080000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                            0x00F00000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                              0x01000000L
+#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                            0x3E000000L
+//MMVM_L2_PROTECTION_FAULT_ADDR_LO32
+#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                                     0x0
+#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                       0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_ADDR_HI32
+#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                      0x0
+#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                        0x0000000FL
+//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                            0x0
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                              0xFFFFFFFFL
+//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                             0x0
+#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                               0x0000000FL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                     0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                       0xFFFFFFFFL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                      0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                        0x0000000FL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                    0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                      0xFFFFFFFFL
+//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                     0x0
+#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                       0x0000000FL
+//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                       0x0
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                         0xFFFFFFFFL
+//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                        0x0
+#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                          0x0000000FL
+//MMVM_L2_CNTL4
+#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                     0x0
+#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                                    0x6
+#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                                    0x7
+#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                         0x8
+#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                        0x12
+#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                             0x1c
+#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT                                                                  0x1d
+#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                       0x0000003FL
+#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                      0x00000040L
+#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                      0x00000080L
+#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                           0x0003FF00L
+#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                          0x0FFC0000L
+#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                               0x10000000L
+#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK                                                                    0x20000000L
+//MMVM_L2_MM_GROUP_RT_CLASSES
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                                  0x0
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                                  0x1
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                                  0x2
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                                  0x3
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                                  0x4
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                                  0x5
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                                  0x6
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                                  0x7
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                                  0x8
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                                  0x9
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                                 0xa
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                                 0xb
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                                 0xc
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                                 0xd
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                                 0xe
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                                 0xf
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                                 0x10
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                                 0x11
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                                 0x12
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                                 0x13
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                                 0x14
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                                 0x15
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                                 0x16
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                                 0x17
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                                 0x18
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                                 0x19
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                                 0x1a
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                                 0x1b
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                                 0x1c
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                                 0x1d
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                                 0x1e
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                                 0x1f
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                                    0x00000001L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                                    0x00000002L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                                    0x00000004L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                                    0x00000008L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                                    0x00000010L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                                    0x00000020L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                                    0x00000040L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                                    0x00000080L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                                    0x00000100L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                                    0x00000200L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                                   0x00000400L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                                   0x00000800L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                                   0x00001000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                                   0x00002000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                                   0x00004000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                                   0x00008000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                                   0x00010000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                                   0x00020000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                                   0x00040000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                                   0x00080000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                                   0x00100000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                                   0x00200000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                                   0x00400000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                                   0x00800000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                                   0x01000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                                   0x02000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                                   0x04000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                                   0x08000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                                   0x10000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                                   0x20000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                                   0x40000000L
+#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                                   0x80000000L
+//MMVM_L2_BANK_SELECT_RESERVED_CID
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                      0x0
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                                     0xa
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                       0x14
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                             0x18
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                          0x19
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT                                 0x1a
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                        0x000001FFL
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                       0x0007FC00L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                         0x00100000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                               0x01000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                            0x02000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK                                   0x7C000000L
+//MMVM_L2_BANK_SELECT_RESERVED_CID2
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                                     0x0
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                                    0xa
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                      0x14
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                            0x18
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                         0x19
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT                                0x1a
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                       0x000001FFL
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                      0x0007FC00L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                        0x00100000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                              0x01000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                           0x02000000L
+#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK                                  0x7C000000L
+//MMVM_L2_CACHE_PARITY_CNTL
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                               0x0
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                             0x1
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                                  0x2
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                               0x3
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                             0x4
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                                  0x5
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                                    0x6
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                                  0x9
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                                   0xc
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                                 0x00000001L
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                               0x00000002L
+#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                                    0x00000004L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                                 0x00000008L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                               0x00000010L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                                    0x00000020L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                      0x000001C0L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                                    0x00000E00L
+#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                                     0x0000F000L
+//MMVM_L2_IH_LOG_CNTL
+#define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING__SHIFT                                                            0x0
+#define MMVM_L2_IH_LOG_CNTL__USE_L_BIT__SHIFT                                                                 0x1
+#define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS__SHIFT                                                          0x2
+#define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS__SHIFT                                                      0x14
+#define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING_MASK                                                              0x00000001L
+#define MMVM_L2_IH_LOG_CNTL__USE_L_BIT_MASK                                                                   0x00000002L
+#define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS_MASK                                                            0x000FFFFCL
+#define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS_MASK                                                        0x00100000L
+//MMVM_L2_IH_LOG_BUSY
+#define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY__SHIFT                                                 0x0
+#define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY__SHIFT                                                0x10
+#define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY_MASK                                                   0x0000FFFFL
+#define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY_MASK                                                  0xFFFF0000L
+//MMVM_L2_CGTT_CLK_CTRL
+#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                0x0
+#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                          0x4
+#define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                           0xf
+#define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                     0x10
+#define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                           0x18
+#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                  0x0000000FL
+#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                            0x00000FF0L
+#define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                             0x00008000L
+#define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                       0x00FF0000L
+#define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                             0xFF000000L
+//MMVM_L2_CNTL5
+#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT                                                   0x0
+#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT                                                       0x5
+#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                                                     0x0000001FL
+#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK                                                         0x00003FE0L
+//MMVM_L2_GCR_CNTL
+#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT                                                                   0x0
+#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT                                                                0x1
+#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK                                                                     0x00000001L
+#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK                                                                  0x000003FEL
+//MMVM_L2_CGTT_BUSY_CTRL
+#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT                                                             0x0
+#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT                                                            0x4
+#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK                                                               0x0000000FL
+#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK                                                              0x00000010L
+//MMVM_L2_PTE_CACHE_DUMP_CNTL
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT                                                            0x0
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT                                                             0x1
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT                                                              0x4
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT                                                             0x8
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT                                                             0xc
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT                                                             0x10
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK                                                              0x00000001L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK                                                               0x00000002L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK                                                                0x000000F0L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK                                                               0x00000F00L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK                                                               0x0000F000L
+#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK                                                               0xFFFF0000L
+//MMVM_L2_PTE_CACHE_DUMP_READ
+#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT                                                              0x0
+#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK                                                                0xFFFFFFFFL
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2vcdec
+//MMVM_CONTEXT0_CNTL
+#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT1_CNTL
+#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT2_CNTL
+#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT3_CNTL
+#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT4_CNTL
+#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT5_CNTL
+#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT6_CNTL
+#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT7_CNTL
+#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT8_CNTL
+#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT9_CNTL
+#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
+#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
+#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
+#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
+#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
+#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
+#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
+#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
+#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
+#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
+#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
+#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
+#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
+#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
+#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
+//MMVM_CONTEXT10_CNTL
+#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXT11_CNTL
+#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXT12_CNTL
+#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXT13_CNTL
+#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXT14_CNTL
+#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXT15_CNTL
+#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
+#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
+#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
+#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
+#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
+#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
+#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
+#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
+#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
+#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
+#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
+#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
+#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
+#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
+#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
+//MMVM_CONTEXTS_DISABLE
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                       0x0
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                       0x1
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                       0x2
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                       0x3
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                       0x4
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                       0x5
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                       0x6
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                       0x7
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                       0x8
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                       0x9
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                      0xa
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                      0xb
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                      0xc
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                      0xd
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                      0xe
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                      0xf
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                         0x00000001L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                         0x00000002L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                         0x00000004L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                         0x00000008L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                         0x00000010L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                         0x00000020L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                         0x00000040L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                         0x00000080L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                         0x00000100L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                         0x00000200L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                        0x00000400L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                        0x00000800L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                        0x00001000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                        0x00002000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                        0x00004000L
+#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                        0x00008000L
+//MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT                       0x0
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                         0x5
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                         0xa
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                         0x0000001FL
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                           0x000003E0L
+#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                           0x0000FC00L
+//MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
+#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
+//MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+//MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+//MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+//MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+//MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+//MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
+#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2pldec
+//MMMC_VM_L2_PERFCOUNTER0_CFG
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER1_CFG
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER2_CFG
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER3_CFG
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER4_CFG
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER5_CFG
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER6_CFG
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER7_CFG
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                      0x8
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                         0x18
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                            0x1c
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                             0x1d
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                            0x000000FFL
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                           0x0F000000L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                              0x10000000L
+#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                               0x20000000L
+//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                0x8
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                 0x10
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                   0x18
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                    0x19
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                         0x1a
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                            0x0000000FL
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                  0x0000FF00L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                   0x00FF0000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                     0x01000000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                      0x02000000L
+#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                           0x04000000L
+//MMUTCL2_PERFCOUNTER0_CFG
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                               0x1c
+#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                0x1d
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                  0x20000000L
+//MMUTCL2_PERFCOUNTER1_CFG
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                               0x1c
+#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                0x1d
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                  0x20000000L
+//MMUTCL2_PERFCOUNTER2_CFG
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                               0x1c
+#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                0x1d
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK                                                                  0x20000000L
+//MMUTCL2_PERFCOUNTER3_CFG
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                               0x1c
+#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                                0x1d
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK                                                                  0x20000000L
+//MMUTCL2_PERFCOUNTER_RSLT_CNTL
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                             0x0
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                   0x8
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                    0x10
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                      0x18
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                       0x19
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                            0x1a
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                               0x0000000FL
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                     0x0000FF00L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                      0x00FF0000L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                        0x01000000L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                         0x02000000L
+#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                              0x04000000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2prdec
+//MMMC_VM_L2_PERFCOUNTER_LO
+#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                            0xFFFFFFFFL
+//MMMC_VM_L2_PERFCOUNTER_HI
+#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                          0x0
+#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                       0x10
+#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                            0x0000FFFFL
+#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                         0xFFFF0000L
+//MMUTCL2_PERFCOUNTER_LO
+#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                               0xFFFFFFFFL
+//MMUTCL2_PERFCOUNTER_HI
+#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                             0x0
+#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                          0x10
+#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                               0x0000FFFFL
+#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                            0xFFFF0000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
+//MMMC_VM_FB_SIZE_OFFSET_VF0
+#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT                                                         0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT                                                       0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK                                                           0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF1
+#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT                                                         0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT                                                       0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK                                                           0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF2
+#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT                                                         0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT                                                       0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK                                                           0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF3
+#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT                                                         0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT                                                       0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK                                                           0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF4
+#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT                                                         0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT                                                       0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK                                                           0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF5
+#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT                                                         0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT                                                       0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK                                                           0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF6
+#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT                                                         0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT                                                       0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK                                                           0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF7
+#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT                                                         0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT                                                       0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK                                                           0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF8
+#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT                                                         0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT                                                       0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK                                                           0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF9
+#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT                                                         0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT                                                       0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK                                                           0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK                                                         0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF10
+#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF11
+#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF12
+#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF13
+#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF14
+#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF15
+#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF16
+#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF17
+#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF18
+#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF19
+#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF20
+#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF21
+#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF22
+#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF23
+#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF24
+#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF25
+#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF26
+#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF27
+#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF28
+#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF29
+#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF30
+#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMMC_VM_FB_SIZE_OFFSET_VF31
+#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT                                                        0x0
+#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT                                                      0x10
+#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK                                                          0x0000FFFFL
+#define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK                                                        0xFFFF0000L
+//MMVM_IOMMU_MMIO_CNTRL_1
+#define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT                                                               0x8
+#define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK                                                                 0x00000100L
+//MMMC_VM_MARC_BASE_LO_0
+#define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT                                                         0xc
+#define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK                                                           0xFFFFF000L
+//MMMC_VM_MARC_BASE_LO_1
+#define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT                                                         0xc
+#define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK                                                           0xFFFFF000L
+//MMMC_VM_MARC_BASE_LO_2
+#define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT                                                         0xc
+#define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK                                                           0xFFFFF000L
+//MMMC_VM_MARC_BASE_LO_3
+#define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT                                                         0xc
+#define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK                                                           0xFFFFF000L
+//MMMC_VM_MARC_BASE_HI_0
+#define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT                                                         0x0
+#define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK                                                           0x000FFFFFL
+//MMMC_VM_MARC_BASE_HI_1
+#define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT                                                         0x0
+#define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK                                                           0x000FFFFFL
+//MMMC_VM_MARC_BASE_HI_2
+#define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT                                                         0x0
+#define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK                                                           0x000FFFFFL
+//MMMC_VM_MARC_BASE_HI_3
+#define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT                                                         0x0
+#define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK                                                           0x000FFFFFL
+//MMMC_VM_MARC_RELOC_LO_0
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT                                                         0x0
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT                                                       0x1
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT                                                       0xc
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK                                                           0x00000001L
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK                                                         0x00000002L
+#define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK                                                         0xFFFFF000L
+//MMMC_VM_MARC_RELOC_LO_1
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT                                                         0x0
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT                                                       0x1
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT                                                       0xc
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK                                                           0x00000001L
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK                                                         0x00000002L
+#define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK                                                         0xFFFFF000L
+//MMMC_VM_MARC_RELOC_LO_2
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT                                                         0x0
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT                                                       0x1
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT                                                       0xc
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK                                                           0x00000001L
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK                                                         0x00000002L
+#define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK                                                         0xFFFFF000L
+//MMMC_VM_MARC_RELOC_LO_3
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT                                                         0x0
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT                                                       0x1
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT                                                       0xc
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK                                                           0x00000001L
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK                                                         0x00000002L
+#define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK                                                         0xFFFFF000L
+//MMMC_VM_MARC_RELOC_HI_0
+#define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT                                                       0x0
+#define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK                                                         0x000FFFFFL
+//MMMC_VM_MARC_RELOC_HI_1
+#define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT                                                       0x0
+#define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK                                                         0x000FFFFFL
+//MMMC_VM_MARC_RELOC_HI_2
+#define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT                                                       0x0
+#define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK                                                         0x000FFFFFL
+//MMMC_VM_MARC_RELOC_HI_3
+#define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT                                                       0x0
+#define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK                                                         0x000FFFFFL
+//MMMC_VM_MARC_LEN_LO_0
+#define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT                                                           0xc
+#define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK                                                             0xFFFFF000L
+//MMMC_VM_MARC_LEN_LO_1
+#define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT                                                           0xc
+#define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK                                                             0xFFFFF000L
+//MMMC_VM_MARC_LEN_LO_2
+#define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT                                                           0xc
+#define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK                                                             0xFFFFF000L
+//MMMC_VM_MARC_LEN_LO_3
+#define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT                                                           0xc
+#define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK                                                             0xFFFFF000L
+//MMMC_VM_MARC_LEN_HI_0
+#define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT                                                           0x0
+#define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK                                                             0x000FFFFFL
+//MMMC_VM_MARC_LEN_HI_1
+#define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT                                                           0x0
+#define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK                                                             0x000FFFFFL
+//MMMC_VM_MARC_LEN_HI_2
+#define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT                                                           0x0
+#define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK                                                             0x000FFFFFL
+//MMMC_VM_MARC_LEN_HI_3
+#define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT                                                           0x0
+#define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK                                                             0x000FFFFFL
+//MMVM_IOMMU_CONTROL_REGISTER
+#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                           0x0
+#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                             0x00000001L
+//MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
+#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                                0xd
+#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                                  0x00002000L
+//MMVM_PCIE_ATS_CNTL
+#define MMVM_PCIE_ATS_CNTL__STU__SHIFT                                                                        0x10
+#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                                 0x1f
+#define MMVM_PCIE_ATS_CNTL__STU_MASK                                                                          0x001F0000L
+#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                                   0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_0
+#define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT                                                            0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK                                                              0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_1
+#define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT                                                            0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK                                                              0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_2
+#define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT                                                            0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK                                                              0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_3
+#define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT                                                            0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK                                                              0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_4
+#define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT                                                            0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK                                                              0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_5
+#define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT                                                            0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK                                                              0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_6
+#define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT                                                            0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK                                                              0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_7
+#define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT                                                            0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK                                                              0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_8
+#define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT                                                            0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK                                                              0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_9
+#define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT                                                            0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK                                                              0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_10
+#define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_11
+#define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_12
+#define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_13
+#define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_14
+#define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_15
+#define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_16
+#define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_17
+#define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_18
+#define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_19
+#define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_20
+#define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_21
+#define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_22
+#define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_23
+#define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_24
+#define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_25
+#define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_26
+#define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_27
+#define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_28
+#define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_29
+#define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_30
+#define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK                                                             0x80000000L
+//MMVM_PCIE_ATS_CNTL_VF_31
+#define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE__SHIFT                                                           0x1f
+#define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE_MASK                                                             0x80000000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
+//MMMC_VM_NB_MMIOBASE
+#define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                                  0x0
+#define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                                    0xFFFFFFFFL
+//MMMC_VM_NB_MMIOLIMIT
+#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                                0x0
+#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                                  0xFFFFFFFFL
+//MMMC_VM_NB_PCI_CTRL
+#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                                0x17
+#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                                  0x00800000L
+//MMMC_VM_NB_PCI_ARB
+#define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                                   0x3
+#define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                                     0x00000008L
+//MMMC_VM_NB_TOP_OF_DRAM_SLOT1
+#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                                      0x17
+#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                                        0xFF800000L
+//MMMC_VM_NB_LOWER_TOP_OF_DRAM2
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                          0x0
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                                      0x17
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                            0x00000001L
+#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                                        0xFF800000L
+//MMMC_VM_NB_UPPER_TOP_OF_DRAM2
+#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                                      0x0
+#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                                        0x00000FFFL
+//MMMC_VM_FB_OFFSET
+#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                   0x0
+#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK                                                                     0x00FFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                             0x0
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                               0xFFFFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                             0x0
+#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                               0x0000000FL
+//MMMC_VM_STEERING
+#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                             0x0
+#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK                                                               0x00000003L
+//MMMC_SHARED_VIRT_RESET_REQ
+#define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                                 0x0
+#define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                                 0x1f
+#define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK                                                                   0x7FFFFFFFL
+#define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK                                                                   0x80000000L
+//MMMC_MEM_POWER_LS
+#define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT                                                                    0x0
+#define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT                                                                     0x6
+#define MMMC_MEM_POWER_LS__LS_SETUP_MASK                                                                      0x0000003FL
+#define MMMC_MEM_POWER_LS__LS_HOLD_MASK                                                                       0x00000FC0L
+//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                                  0x0
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                                    0x000FFFFFL
+//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                                    0x0
+#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                                      0x000FFFFFL
+//MMMC_VM_APT_CNTL
+#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                               0x0
+#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                             0x1
+#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT                                                          0x2
+#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                                 0x00000001L
+#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                               0x00000002L
+#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK                                                            0x0000000CL
+//MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                      0x0
+#define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                        0x00000001L
+//MMMC_VM_LOCAL_HBM_ADDRESS_START
+#define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT                                                       0x0
+#define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK                                                         0x000FFFFFL
+//MMMC_VM_LOCAL_HBM_ADDRESS_END
+#define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT                                                         0x0
+#define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK                                                           0x000FFFFFL
+//MMUTCL2_CGTT_CLK_CTRL
+#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                0x0
+#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                          0x4
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT                                                     0xc
+#define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                           0xf
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                     0x10
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                           0x18
+#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                  0x0000000FL
+#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                            0x00000FF0L
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK                                                       0x00007000L
+#define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                             0x00008000L
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                       0x00FF0000L
+#define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                             0xFF000000L
+//MMMC_SHARED_ACTIVE_FCN_ID
+#define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT                                                                0x0
+#define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT                                                                  0x1f
+#define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK                                                                  0x0000001FL
+#define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK                                                                    0x80000000L
+//MMMC_SHARED_VIRT_RESET_REQ2
+#define MMMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT                                                                0x0
+#define MMMC_SHARED_VIRT_RESET_REQ2__VF_MASK                                                                  0x00000001L
+//MMUTCL2_CGTT_BUSY_CTRL
+#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT                                                             0x0
+#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT                                                            0x4
+#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK                                                               0x0000000FL
+#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK                                                              0x00000010L
+//MMUTCL2_HARVEST_BYPASS_GROUPS
+#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT                                                   0x0
+#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
+//MMMC_VM_FB_LOCATION_BASE
+#define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                              0x0
+#define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                0x00FFFFFFL
+//MMMC_VM_FB_LOCATION_TOP
+#define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                0x0
+#define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                  0x00FFFFFFL
+//MMMC_VM_AGP_TOP
+#define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT                                                                       0x0
+#define MMMC_VM_AGP_TOP__AGP_TOP_MASK                                                                         0x00FFFFFFL
+//MMMC_VM_AGP_BOT
+#define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT                                                                       0x0
+#define MMMC_VM_AGP_BOT__AGP_BOT_MASK                                                                         0x00FFFFFFL
+//MMMC_VM_AGP_BASE
+#define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT                                                                     0x0
+#define MMMC_VM_AGP_BASE__AGP_BASE_MASK                                                                       0x00FFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR
+#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                                 0x0
+#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                                   0x3FFFFFFFL
+//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                                0x0
+#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                                  0x3FFFFFFFL
+//MMMC_VM_MX_L1_TLB_CNTL
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                          0x0
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                                     0x3
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                        0x5
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                           0x6
+#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                               0x7
+#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                                  0xb
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                            0x00000001L
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                                       0x00000018L
+#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                          0x00000020L
+#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                             0x00000040L
+#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                                 0x00000780L
+#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                                    0x00003800L
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
+//MM_ATC_L2_PERFCOUNTER_LO
+#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                           0x0
+#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                             0xFFFFFFFFL
+//MM_ATC_L2_PERFCOUNTER_HI
+#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                           0x0
+#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                        0x10
+#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                             0x0000FFFFL
+#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                          0xFFFF0000L
+
+
+// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
+//MM_ATC_L2_PERFCOUNTER0_CFG
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                           0x0
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                       0x8
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                          0x18
+#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                             0x1c
+#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                              0x1d
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                             0x000000FFL
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                         0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                            0x0F000000L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                               0x10000000L
+#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                0x20000000L
+//MM_ATC_L2_PERFCOUNTER1_CFG
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                           0x0
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                       0x8
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                          0x18
+#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                             0x1c
+#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                              0x1d
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                             0x000000FFL
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                         0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                            0x0F000000L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                               0x10000000L
+#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                0x20000000L
+//MM_ATC_L2_PERFCOUNTER_RSLT_CNTL
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                           0x0
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                 0x8
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                  0x10
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                    0x18
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                     0x19
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                          0x1a
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                             0x0000000FL
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                   0x0000FF00L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                    0x00FF0000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                      0x01000000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                       0x02000000L
+#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                            0x04000000L
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2ptdec
+//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT0_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT0_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT0_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT0_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT0_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT1_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT1_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT1_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT1_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT1_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT2_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT2_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT2_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT2_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT2_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT3_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT3_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT3_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT3_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT3_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT4_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT4_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT4_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT4_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT4_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT5_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT5_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT5_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT5_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT5_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT6_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT6_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT6_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT6_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT6_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT7_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT7_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT7_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT7_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT7_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT8_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT8_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT8_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT8_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT8_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
+//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
+//MMVM_CONTEXT9_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT9_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT9_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT9_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                       0x0
+#define MMVM_CONTEXT9_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                         0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_CONTEXT10_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT10_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                        0xFFFFFFFFL
+//MMVM_CONTEXT10_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT10_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT10_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                        0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_CONTEXT11_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT11_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                        0xFFFFFFFFL
+//MMVM_CONTEXT11_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT11_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT11_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                        0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_CONTEXT12_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT12_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                        0xFFFFFFFFL
+//MMVM_CONTEXT12_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT12_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT12_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                        0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_CONTEXT13_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT13_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                        0xFFFFFFFFL
+//MMVM_CONTEXT13_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT13_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT13_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                        0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_CONTEXT14_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT14_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                        0xFFFFFFFFL
+//MMVM_CONTEXT14_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT14_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT14_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                        0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
+//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
+//MMVM_CONTEXT15_PAGE_TABLE_RESERVE0
+#define MMVM_CONTEXT15_PAGE_TABLE_RESERVE0__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_RESERVE0__DUMMY_MASK                                                        0xFFFFFFFFL
+//MMVM_CONTEXT15_PAGE_TABLE_RESERVE1
+#define MMVM_CONTEXT15_PAGE_TABLE_RESERVE1__DUMMY__SHIFT                                                      0x0
+#define MMVM_CONTEXT15_PAGE_TABLE_RESERVE1__DUMMY_MASK                                                        0xFFFFFFFFL
+
+
+// addressBlock: mmhub_mmutcl2_mmvml2indec
+//MMVM_INVALIDATE_ENG0_SEM
+#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG0_REQ
+#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG0_ACK
+#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG0_RESERVE0
+#define MMVM_INVALIDATE_ENG0_RESERVE0__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG0_RESERVE0__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG0_RESERVE1
+#define MMVM_INVALIDATE_ENG0_RESERVE1__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG0_RESERVE1__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG0_RESERVE2
+#define MMVM_INVALIDATE_ENG0_RESERVE2__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG0_RESERVE2__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG1_SEM
+#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG1_REQ
+#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG1_ACK
+#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG1_RESERVE0
+#define MMVM_INVALIDATE_ENG1_RESERVE0__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG1_RESERVE0__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG1_RESERVE1
+#define MMVM_INVALIDATE_ENG1_RESERVE1__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG1_RESERVE1__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG1_RESERVE2
+#define MMVM_INVALIDATE_ENG1_RESERVE2__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG1_RESERVE2__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG2_SEM
+#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG2_REQ
+#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG2_ACK
+#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG2_RESERVE0
+#define MMVM_INVALIDATE_ENG2_RESERVE0__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG2_RESERVE0__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG2_RESERVE1
+#define MMVM_INVALIDATE_ENG2_RESERVE1__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG2_RESERVE1__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG2_RESERVE2
+#define MMVM_INVALIDATE_ENG2_RESERVE2__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG2_RESERVE2__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG3_SEM
+#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG3_REQ
+#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG3_ACK
+#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG3_RESERVE0
+#define MMVM_INVALIDATE_ENG3_RESERVE0__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG3_RESERVE0__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG3_RESERVE1
+#define MMVM_INVALIDATE_ENG3_RESERVE1__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG3_RESERVE1__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG3_RESERVE2
+#define MMVM_INVALIDATE_ENG3_RESERVE2__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG3_RESERVE2__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG4_SEM
+#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG4_REQ
+#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG4_ACK
+#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG4_RESERVE0
+#define MMVM_INVALIDATE_ENG4_RESERVE0__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG4_RESERVE0__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG4_RESERVE1
+#define MMVM_INVALIDATE_ENG4_RESERVE1__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG4_RESERVE1__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG4_RESERVE2
+#define MMVM_INVALIDATE_ENG4_RESERVE2__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG4_RESERVE2__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG5_SEM
+#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG5_REQ
+#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG5_ACK
+#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG5_RESERVE0
+#define MMVM_INVALIDATE_ENG5_RESERVE0__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG5_RESERVE0__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG5_RESERVE1
+#define MMVM_INVALIDATE_ENG5_RESERVE1__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG5_RESERVE1__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG5_RESERVE2
+#define MMVM_INVALIDATE_ENG5_RESERVE2__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG5_RESERVE2__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG6_SEM
+#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG6_REQ
+#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG6_ACK
+#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG6_RESERVE0
+#define MMVM_INVALIDATE_ENG6_RESERVE0__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG6_RESERVE0__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG6_RESERVE1
+#define MMVM_INVALIDATE_ENG6_RESERVE1__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG6_RESERVE1__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG6_RESERVE2
+#define MMVM_INVALIDATE_ENG6_RESERVE2__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG6_RESERVE2__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG7_SEM
+#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG7_REQ
+#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG7_ACK
+#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG7_RESERVE0
+#define MMVM_INVALIDATE_ENG7_RESERVE0__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG7_RESERVE0__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG7_RESERVE1
+#define MMVM_INVALIDATE_ENG7_RESERVE1__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG7_RESERVE1__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG7_RESERVE2
+#define MMVM_INVALIDATE_ENG7_RESERVE2__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG7_RESERVE2__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG8_SEM
+#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG8_REQ
+#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG8_ACK
+#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG8_RESERVE0
+#define MMVM_INVALIDATE_ENG8_RESERVE0__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG8_RESERVE0__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG8_RESERVE1
+#define MMVM_INVALIDATE_ENG8_RESERVE1__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG8_RESERVE1__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG8_RESERVE2
+#define MMVM_INVALIDATE_ENG8_RESERVE2__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG8_RESERVE2__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG9_SEM
+#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                            0x0
+#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                              0x00000001L
+//MMVM_INVALIDATE_ENG9_REQ
+#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
+#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
+#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT                                                          0x19
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
+#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
+#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
+#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK                                                            0x02000000L
+#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
+//MMVM_INVALIDATE_ENG9_ACK
+#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
+#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                            0x10
+#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
+#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                              0x00010000L
+//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
+#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
+//MMVM_INVALIDATE_ENG9_RESERVE0
+#define MMVM_INVALIDATE_ENG9_RESERVE0__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG9_RESERVE0__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG9_RESERVE1
+#define MMVM_INVALIDATE_ENG9_RESERVE1__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG9_RESERVE1__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG9_RESERVE2
+#define MMVM_INVALIDATE_ENG9_RESERVE2__DUMMY__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG9_RESERVE2__DUMMY_MASK                                                             0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG10_SEM
+#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG10_REQ
+#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG10_ACK
+#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG10_RESERVE0
+#define MMVM_INVALIDATE_ENG10_RESERVE0__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG10_RESERVE0__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG10_RESERVE1
+#define MMVM_INVALIDATE_ENG10_RESERVE1__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG10_RESERVE1__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG10_RESERVE2
+#define MMVM_INVALIDATE_ENG10_RESERVE2__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG10_RESERVE2__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG11_SEM
+#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG11_REQ
+#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG11_ACK
+#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG11_RESERVE0
+#define MMVM_INVALIDATE_ENG11_RESERVE0__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG11_RESERVE0__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG11_RESERVE1
+#define MMVM_INVALIDATE_ENG11_RESERVE1__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG11_RESERVE1__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG11_RESERVE2
+#define MMVM_INVALIDATE_ENG11_RESERVE2__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG11_RESERVE2__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG12_SEM
+#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG12_REQ
+#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG12_ACK
+#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG12_RESERVE0
+#define MMVM_INVALIDATE_ENG12_RESERVE0__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG12_RESERVE0__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG12_RESERVE1
+#define MMVM_INVALIDATE_ENG12_RESERVE1__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG12_RESERVE1__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG12_RESERVE2
+#define MMVM_INVALIDATE_ENG12_RESERVE2__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG12_RESERVE2__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG13_SEM
+#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG13_REQ
+#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG13_ACK
+#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG13_RESERVE0
+#define MMVM_INVALIDATE_ENG13_RESERVE0__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG13_RESERVE0__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG13_RESERVE1
+#define MMVM_INVALIDATE_ENG13_RESERVE1__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG13_RESERVE1__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG13_RESERVE2
+#define MMVM_INVALIDATE_ENG13_RESERVE2__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG13_RESERVE2__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG14_SEM
+#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG14_REQ
+#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG14_ACK
+#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG14_RESERVE0
+#define MMVM_INVALIDATE_ENG14_RESERVE0__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG14_RESERVE0__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG14_RESERVE1
+#define MMVM_INVALIDATE_ENG14_RESERVE1__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG14_RESERVE1__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG14_RESERVE2
+#define MMVM_INVALIDATE_ENG14_RESERVE2__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG14_RESERVE2__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG15_SEM
+#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG15_REQ
+#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG15_ACK
+#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG15_RESERVE0
+#define MMVM_INVALIDATE_ENG15_RESERVE0__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG15_RESERVE0__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG15_RESERVE1
+#define MMVM_INVALIDATE_ENG15_RESERVE1__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG15_RESERVE1__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG15_RESERVE2
+#define MMVM_INVALIDATE_ENG15_RESERVE2__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG15_RESERVE2__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG16_SEM
+#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG16_REQ
+#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG16_ACK
+#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG16_RESERVE0
+#define MMVM_INVALIDATE_ENG16_RESERVE0__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG16_RESERVE0__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG16_RESERVE1
+#define MMVM_INVALIDATE_ENG16_RESERVE1__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG16_RESERVE1__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG16_RESERVE2
+#define MMVM_INVALIDATE_ENG16_RESERVE2__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG16_RESERVE2__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG17_SEM
+#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                           0x0
+#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                             0x00000001L
+//MMVM_INVALIDATE_ENG17_REQ
+#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                          0x10
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
+#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
+#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT                                                         0x19
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
+#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
+#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
+#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK                                                           0x02000000L
+#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
+//MMVM_INVALIDATE_ENG17_ACK
+#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
+#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                           0x10
+#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
+#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                             0x00010000L
+//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
+//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
+#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
+//MMVM_INVALIDATE_ENG17_RESERVE0
+#define MMVM_INVALIDATE_ENG17_RESERVE0__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG17_RESERVE0__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG17_RESERVE1
+#define MMVM_INVALIDATE_ENG17_RESERVE1__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG17_RESERVE1__DUMMY_MASK                                                            0xFFFFFFFFL
+//MMVM_INVALIDATE_ENG17_RESERVE2
+#define MMVM_INVALIDATE_ENG17_RESERVE2__DUMMY__SHIFT                                                          0x0
+#define MMVM_INVALIDATE_ENG17_RESERVE2__DUMMY_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpfdec
+//MML2TLB_TLB0_STATUS
+#define MML2TLB_TLB0_STATUS__BUSY__SHIFT                                                                      0x0
+#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                       0x1
+#define MML2TLB_TLB0_STATUS__BUSY_MASK                                                                        0x00000001L
+#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                                         0x00000002L
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbpldec
+//MML2TLB_PERFCOUNTER0_CFG
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                               0x1c
+#define MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                0x1d
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK                                                                  0x20000000L
+//MML2TLB_PERFCOUNTER1_CFG
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                               0x1c
+#define MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                0x1d
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK                                                                  0x20000000L
+//MML2TLB_PERFCOUNTER2_CFG
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                               0x1c
+#define MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                0x1d
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK                                                                  0x20000000L
+//MML2TLB_PERFCOUNTER3_CFG
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                         0x8
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                            0x18
+#define MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                               0x1c
+#define MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                                0x1d
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                               0x000000FFL
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
+#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                              0x0F000000L
+#define MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK                                                                 0x10000000L
+#define MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK                                                                  0x20000000L
+//MML2TLB_PERFCOUNTER_RSLT_CNTL
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                             0x0
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                   0x8
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                    0x10
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                      0x18
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                       0x19
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                            0x1a
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                               0x0000000FL
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                     0x0000FF00L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                      0x00FF0000L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                        0x01000000L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                         0x02000000L
+#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                              0x04000000L
+
+
+// addressBlock: mmhub_mmutcl2_mml2tlbprdec
+//MML2TLB_PERFCOUNTER_LO
+#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK                                                               0xFFFFFFFFL
+//MML2TLB_PERFCOUNTER_HI
+#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                             0x0
+#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                          0x10
+#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK                                                               0x0000FFFFL
+#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                            0xFFFF0000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_5_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_5_0_offset.h
new file mode 100644
index 000000000000..10f005114fea
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_5_0_offset.h
@@ -0,0 +1,400 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mp_11_5_0_OFFSET_HEADER
+#define _mp_11_5_0_OFFSET_HEADER
+
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+// base address: 0x0
+#define mmMP0_SMN_C2PMSG_32                                                                            0x0060
+#define mmMP0_SMN_C2PMSG_32_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_33                                                                            0x0061
+#define mmMP0_SMN_C2PMSG_33_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_34                                                                            0x0062
+#define mmMP0_SMN_C2PMSG_34_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_35                                                                            0x0063
+#define mmMP0_SMN_C2PMSG_35_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_36                                                                            0x0064
+#define mmMP0_SMN_C2PMSG_36_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_37                                                                            0x0065
+#define mmMP0_SMN_C2PMSG_37_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_38                                                                            0x0066
+#define mmMP0_SMN_C2PMSG_38_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_39                                                                            0x0067
+#define mmMP0_SMN_C2PMSG_39_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_40                                                                            0x0068
+#define mmMP0_SMN_C2PMSG_40_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_41                                                                            0x0069
+#define mmMP0_SMN_C2PMSG_41_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_42                                                                            0x006a
+#define mmMP0_SMN_C2PMSG_42_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_43                                                                            0x006b
+#define mmMP0_SMN_C2PMSG_43_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_44                                                                            0x006c
+#define mmMP0_SMN_C2PMSG_44_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_45                                                                            0x006d
+#define mmMP0_SMN_C2PMSG_45_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_46                                                                            0x006e
+#define mmMP0_SMN_C2PMSG_46_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_47                                                                            0x006f
+#define mmMP0_SMN_C2PMSG_47_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_48                                                                            0x0070
+#define mmMP0_SMN_C2PMSG_48_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_49                                                                            0x0071
+#define mmMP0_SMN_C2PMSG_49_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_50                                                                            0x0072
+#define mmMP0_SMN_C2PMSG_50_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_51                                                                            0x0073
+#define mmMP0_SMN_C2PMSG_51_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_52                                                                            0x0074
+#define mmMP0_SMN_C2PMSG_52_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_53                                                                            0x0075
+#define mmMP0_SMN_C2PMSG_53_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_54                                                                            0x0076
+#define mmMP0_SMN_C2PMSG_54_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_55                                                                            0x0077
+#define mmMP0_SMN_C2PMSG_55_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_56                                                                            0x0078
+#define mmMP0_SMN_C2PMSG_56_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_57                                                                            0x0079
+#define mmMP0_SMN_C2PMSG_57_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_58                                                                            0x007a
+#define mmMP0_SMN_C2PMSG_58_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_59                                                                            0x007b
+#define mmMP0_SMN_C2PMSG_59_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_60                                                                            0x007c
+#define mmMP0_SMN_C2PMSG_60_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_61                                                                            0x007d
+#define mmMP0_SMN_C2PMSG_61_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_62                                                                            0x007e
+#define mmMP0_SMN_C2PMSG_62_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_63                                                                            0x007f
+#define mmMP0_SMN_C2PMSG_63_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_64                                                                            0x0080
+#define mmMP0_SMN_C2PMSG_64_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_65                                                                            0x0081
+#define mmMP0_SMN_C2PMSG_65_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_66                                                                            0x0082
+#define mmMP0_SMN_C2PMSG_66_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_67                                                                            0x0083
+#define mmMP0_SMN_C2PMSG_67_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_68                                                                            0x0084
+#define mmMP0_SMN_C2PMSG_68_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_69                                                                            0x0085
+#define mmMP0_SMN_C2PMSG_69_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_70                                                                            0x0086
+#define mmMP0_SMN_C2PMSG_70_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_71                                                                            0x0087
+#define mmMP0_SMN_C2PMSG_71_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_72                                                                            0x0088
+#define mmMP0_SMN_C2PMSG_72_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_73                                                                            0x0089
+#define mmMP0_SMN_C2PMSG_73_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_74                                                                            0x008a
+#define mmMP0_SMN_C2PMSG_74_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_75                                                                            0x008b
+#define mmMP0_SMN_C2PMSG_75_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_76                                                                            0x008c
+#define mmMP0_SMN_C2PMSG_76_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_77                                                                            0x008d
+#define mmMP0_SMN_C2PMSG_77_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_78                                                                            0x008e
+#define mmMP0_SMN_C2PMSG_78_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_79                                                                            0x008f
+#define mmMP0_SMN_C2PMSG_79_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_80                                                                            0x0090
+#define mmMP0_SMN_C2PMSG_80_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_81                                                                            0x0091
+#define mmMP0_SMN_C2PMSG_81_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_82                                                                            0x0092
+#define mmMP0_SMN_C2PMSG_82_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_83                                                                            0x0093
+#define mmMP0_SMN_C2PMSG_83_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_84                                                                            0x0094
+#define mmMP0_SMN_C2PMSG_84_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_85                                                                            0x0095
+#define mmMP0_SMN_C2PMSG_85_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_86                                                                            0x0096
+#define mmMP0_SMN_C2PMSG_86_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_87                                                                            0x0097
+#define mmMP0_SMN_C2PMSG_87_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_88                                                                            0x0098
+#define mmMP0_SMN_C2PMSG_88_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_89                                                                            0x0099
+#define mmMP0_SMN_C2PMSG_89_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_90                                                                            0x009a
+#define mmMP0_SMN_C2PMSG_90_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_91                                                                            0x009b
+#define mmMP0_SMN_C2PMSG_91_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_92                                                                            0x009c
+#define mmMP0_SMN_C2PMSG_92_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_93                                                                            0x009d
+#define mmMP0_SMN_C2PMSG_93_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_94                                                                            0x009e
+#define mmMP0_SMN_C2PMSG_94_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_95                                                                            0x009f
+#define mmMP0_SMN_C2PMSG_95_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_96                                                                            0x00a0
+#define mmMP0_SMN_C2PMSG_96_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_97                                                                            0x00a1
+#define mmMP0_SMN_C2PMSG_97_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_98                                                                            0x00a2
+#define mmMP0_SMN_C2PMSG_98_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_99                                                                            0x00a3
+#define mmMP0_SMN_C2PMSG_99_BASE_IDX                                                                   0
+#define mmMP0_SMN_C2PMSG_100                                                                           0x00a4
+#define mmMP0_SMN_C2PMSG_100_BASE_IDX                                                                  0
+#define mmMP0_SMN_C2PMSG_101                                                                           0x00a5
+#define mmMP0_SMN_C2PMSG_101_BASE_IDX                                                                  0
+#define mmMP0_SMN_C2PMSG_102                                                                           0x00a6
+#define mmMP0_SMN_C2PMSG_102_BASE_IDX                                                                  0
+#define mmMP0_SMN_C2PMSG_103                                                                           0x00a7
+#define mmMP0_SMN_C2PMSG_103_BASE_IDX                                                                  0
+#define mmMP0_SMN_IH_CREDIT                                                                            0x00c1
+#define mmMP0_SMN_IH_CREDIT_BASE_IDX                                                                   0
+#define mmMP0_SMN_IH_SW_INT                                                                            0x00c2
+#define mmMP0_SMN_IH_SW_INT_BASE_IDX                                                                   0
+#define mmMP0_SMN_IH_SW_INT_CTRL                                                                       0x00c3
+#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+// base address: 0x0
+#define mmMP1_SMN_C2PMSG_32                                                                            0x0260
+#define mmMP1_SMN_C2PMSG_32_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_33                                                                            0x0261
+#define mmMP1_SMN_C2PMSG_33_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_34                                                                            0x0262
+#define mmMP1_SMN_C2PMSG_34_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_35                                                                            0x0263
+#define mmMP1_SMN_C2PMSG_35_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_36                                                                            0x0264
+#define mmMP1_SMN_C2PMSG_36_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_37                                                                            0x0265
+#define mmMP1_SMN_C2PMSG_37_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_38                                                                            0x0266
+#define mmMP1_SMN_C2PMSG_38_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_39                                                                            0x0267
+#define mmMP1_SMN_C2PMSG_39_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_40                                                                            0x0268
+#define mmMP1_SMN_C2PMSG_40_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_41                                                                            0x0269
+#define mmMP1_SMN_C2PMSG_41_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_42                                                                            0x026a
+#define mmMP1_SMN_C2PMSG_42_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_43                                                                            0x026b
+#define mmMP1_SMN_C2PMSG_43_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_44                                                                            0x026c
+#define mmMP1_SMN_C2PMSG_44_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_45                                                                            0x026d
+#define mmMP1_SMN_C2PMSG_45_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_46                                                                            0x026e
+#define mmMP1_SMN_C2PMSG_46_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_47                                                                            0x026f
+#define mmMP1_SMN_C2PMSG_47_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_48                                                                            0x0270
+#define mmMP1_SMN_C2PMSG_48_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_49                                                                            0x0271
+#define mmMP1_SMN_C2PMSG_49_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_50                                                                            0x0272
+#define mmMP1_SMN_C2PMSG_50_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_51                                                                            0x0273
+#define mmMP1_SMN_C2PMSG_51_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_52                                                                            0x0274
+#define mmMP1_SMN_C2PMSG_52_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_53                                                                            0x0275
+#define mmMP1_SMN_C2PMSG_53_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_54                                                                            0x0276
+#define mmMP1_SMN_C2PMSG_54_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_55                                                                            0x0277
+#define mmMP1_SMN_C2PMSG_55_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_56                                                                            0x0278
+#define mmMP1_SMN_C2PMSG_56_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_57                                                                            0x0279
+#define mmMP1_SMN_C2PMSG_57_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_58                                                                            0x027a
+#define mmMP1_SMN_C2PMSG_58_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_59                                                                            0x027b
+#define mmMP1_SMN_C2PMSG_59_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_60                                                                            0x027c
+#define mmMP1_SMN_C2PMSG_60_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_61                                                                            0x027d
+#define mmMP1_SMN_C2PMSG_61_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_62                                                                            0x027e
+#define mmMP1_SMN_C2PMSG_62_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_63                                                                            0x027f
+#define mmMP1_SMN_C2PMSG_63_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_64                                                                            0x0280
+#define mmMP1_SMN_C2PMSG_64_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_65                                                                            0x0281
+#define mmMP1_SMN_C2PMSG_65_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_66                                                                            0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_67                                                                            0x0283
+#define mmMP1_SMN_C2PMSG_67_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_68                                                                            0x0284
+#define mmMP1_SMN_C2PMSG_68_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_69                                                                            0x0285
+#define mmMP1_SMN_C2PMSG_69_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_70                                                                            0x0286
+#define mmMP1_SMN_C2PMSG_70_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_71                                                                            0x0287
+#define mmMP1_SMN_C2PMSG_71_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_72                                                                            0x0288
+#define mmMP1_SMN_C2PMSG_72_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_73                                                                            0x0289
+#define mmMP1_SMN_C2PMSG_73_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_74                                                                            0x028a
+#define mmMP1_SMN_C2PMSG_74_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_75                                                                            0x028b
+#define mmMP1_SMN_C2PMSG_75_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_76                                                                            0x028c
+#define mmMP1_SMN_C2PMSG_76_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_77                                                                            0x028d
+#define mmMP1_SMN_C2PMSG_77_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_78                                                                            0x028e
+#define mmMP1_SMN_C2PMSG_78_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_79                                                                            0x028f
+#define mmMP1_SMN_C2PMSG_79_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_80                                                                            0x0290
+#define mmMP1_SMN_C2PMSG_80_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_81                                                                            0x0291
+#define mmMP1_SMN_C2PMSG_81_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_82                                                                            0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_83                                                                            0x0293
+#define mmMP1_SMN_C2PMSG_83_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_84                                                                            0x0294
+#define mmMP1_SMN_C2PMSG_84_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_85                                                                            0x0295
+#define mmMP1_SMN_C2PMSG_85_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_86                                                                            0x0296
+#define mmMP1_SMN_C2PMSG_86_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_87                                                                            0x0297
+#define mmMP1_SMN_C2PMSG_87_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_88                                                                            0x0298
+#define mmMP1_SMN_C2PMSG_88_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_89                                                                            0x0299
+#define mmMP1_SMN_C2PMSG_89_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_90                                                                            0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_91                                                                            0x029b
+#define mmMP1_SMN_C2PMSG_91_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_92                                                                            0x029c
+#define mmMP1_SMN_C2PMSG_92_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_93                                                                            0x029d
+#define mmMP1_SMN_C2PMSG_93_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_94                                                                            0x029e
+#define mmMP1_SMN_C2PMSG_94_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_95                                                                            0x029f
+#define mmMP1_SMN_C2PMSG_95_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_96                                                                            0x02a0
+#define mmMP1_SMN_C2PMSG_96_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_97                                                                            0x02a1
+#define mmMP1_SMN_C2PMSG_97_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_98                                                                            0x02a2
+#define mmMP1_SMN_C2PMSG_98_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_99                                                                            0x02a3
+#define mmMP1_SMN_C2PMSG_99_BASE_IDX                                                                   0
+#define mmMP1_SMN_C2PMSG_100                                                                           0x02a4
+#define mmMP1_SMN_C2PMSG_100_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_101                                                                           0x02a5
+#define mmMP1_SMN_C2PMSG_101_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_102                                                                           0x02a6
+#define mmMP1_SMN_C2PMSG_102_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_103                                                                           0x02a7
+#define mmMP1_SMN_C2PMSG_103_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_104                                                                           0x02a8
+#define mmMP1_SMN_C2PMSG_104_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_105                                                                           0x02a9
+#define mmMP1_SMN_C2PMSG_105_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_106                                                                           0x02aa
+#define mmMP1_SMN_C2PMSG_106_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_107                                                                           0x02ab
+#define mmMP1_SMN_C2PMSG_107_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_108                                                                           0x02ac
+#define mmMP1_SMN_C2PMSG_108_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_109                                                                           0x02ad
+#define mmMP1_SMN_C2PMSG_109_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_110                                                                           0x02ae
+#define mmMP1_SMN_C2PMSG_110_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_111                                                                           0x02af
+#define mmMP1_SMN_C2PMSG_111_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_112                                                                           0x02b0
+#define mmMP1_SMN_C2PMSG_112_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_113                                                                           0x02b1
+#define mmMP1_SMN_C2PMSG_113_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_114                                                                           0x02b2
+#define mmMP1_SMN_C2PMSG_114_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_115                                                                           0x02b3
+#define mmMP1_SMN_C2PMSG_115_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_116                                                                           0x02b4
+#define mmMP1_SMN_C2PMSG_116_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_117                                                                           0x02b5
+#define mmMP1_SMN_C2PMSG_117_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_118                                                                           0x02b6
+#define mmMP1_SMN_C2PMSG_118_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_119                                                                           0x02b7
+#define mmMP1_SMN_C2PMSG_119_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_120                                                                           0x02b8
+#define mmMP1_SMN_C2PMSG_120_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_121                                                                           0x02b9
+#define mmMP1_SMN_C2PMSG_121_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_122                                                                           0x02ba
+#define mmMP1_SMN_C2PMSG_122_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_123                                                                           0x02bb
+#define mmMP1_SMN_C2PMSG_123_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_124                                                                           0x02bc
+#define mmMP1_SMN_C2PMSG_124_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_125                                                                           0x02bd
+#define mmMP1_SMN_C2PMSG_125_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_126                                                                           0x02be
+#define mmMP1_SMN_C2PMSG_126_BASE_IDX                                                                  0
+#define mmMP1_SMN_C2PMSG_127                                                                           0x02bf
+#define mmMP1_SMN_C2PMSG_127_BASE_IDX                                                                  0
+#define mmMP1_SMN_IH_CREDIT                                                                            0x02c1
+#define mmMP1_SMN_IH_CREDIT_BASE_IDX                                                                   0
+#define mmMP1_SMN_IH_SW_INT                                                                            0x02c2
+#define mmMP1_SMN_IH_SW_INT_BASE_IDX                                                                   0
+#define mmMP1_SMN_IH_SW_INT_CTRL                                                                       0x02c3
+#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
+#define mmMP1_SMN_FPS_CNT                                                                              0x02c4
+#define mmMP1_SMN_FPS_CNT_BASE_IDX                                                                     0
+#define mmMP1_SMN_EXT_SCRATCH0                                                                         0x03c0
+#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX                                                                0
+#define mmMP1_SMN_EXT_SCRATCH1                                                                         0x03c1
+#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX                                                                0
+#define mmMP1_SMN_EXT_SCRATCH2                                                                         0x03c2
+#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX                                                                0
+#define mmMP1_SMN_EXT_SCRATCH3                                                                         0x03c3
+#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX                                                                0
+#define mmMP1_SMN_EXT_SCRATCH4                                                                         0x03c4
+#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX                                                                0
+#define mmMP1_SMN_EXT_SCRATCH5                                                                         0x03c5
+#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX                                                                0
+#define mmMP1_SMN_EXT_SCRATCH6                                                                         0x03c6
+#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX                                                                0
+#define mmMP1_SMN_EXT_SCRATCH7                                                                         0x03c7
+#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX                                                                0
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_5_0_sh_mask.h
new file mode 100644
index 000000000000..3381337cafb9
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_5_0_sh_mask.h
@@ -0,0 +1,942 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _mp_11_5_0_SH_MASK_HEADER
+#define _mp_11_5_0_SH_MASK_HEADER
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+//MP0_SMN_C2PMSG_32
+#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_33
+#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_34
+#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_35
+#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_36
+#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_37
+#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_38
+#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_39
+#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_40
+#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_41
+#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_42
+#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_43
+#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_44
+#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_45
+#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_46
+#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_47
+#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_48
+#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_49
+#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_50
+#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_51
+#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_52
+#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_53
+#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_54
+#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_55
+#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_56
+#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_57
+#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_58
+#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_59
+#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_60
+#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_61
+#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_62
+#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_63
+#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_64
+#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_65
+#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_66
+#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_67
+#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_68
+#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_69
+#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_70
+#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_71
+#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_72
+#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_73
+#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_74
+#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_75
+#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_76
+#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_77
+#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_78
+#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_79
+#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_80
+#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_81
+#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_82
+#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_83
+#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_84
+#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_85
+#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_86
+#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_87
+#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_88
+#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_89
+#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_90
+#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_91
+#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_92
+#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_93
+#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_94
+#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_95
+#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_96
+#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_97
+#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_98
+#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_99
+#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_100
+#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_C2PMSG_101
+#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_C2PMSG_102
+#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_C2PMSG_103
+#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_IH_CREDIT
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
+#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
+#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
+//MP0_SMN_IH_SW_INT
+#define MP0_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
+#define MP0_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
+#define MP0_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
+#define MP0_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
+//MP0_SMN_IH_SW_INT_CTRL
+#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
+#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
+#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
+#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+//MP1_SMN_C2PMSG_32
+#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_33
+#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_34
+#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_35
+#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_36
+#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_37
+#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_38
+#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_39
+#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_40
+#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_41
+#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_42
+#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_43
+#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_44
+#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_45
+#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_46
+#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_47
+#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_48
+#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_49
+#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_50
+#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_51
+#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_52
+#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_53
+#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_54
+#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_55
+#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_56
+#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_57
+#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_58
+#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_59
+#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_60
+#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_61
+#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_62
+#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_63
+#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_64
+#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_65
+#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_66
+#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_67
+#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_68
+#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_69
+#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_70
+#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_71
+#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_72
+#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_73
+#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_74
+#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_75
+#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_76
+#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_77
+#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_78
+#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_79
+#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_80
+#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_81
+#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_82
+#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_83
+#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_84
+#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_85
+#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_86
+#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_87
+#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_88
+#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_89
+#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_90
+#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_91
+#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_92
+#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_93
+#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_94
+#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_95
+#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_96
+#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_97
+#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_98
+#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_99
+#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_100
+#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_C2PMSG_101
+#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_C2PMSG_102
+#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_C2PMSG_103
+#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_IH_CREDIT
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
+#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
+#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
+//MP1_SMN_IH_SW_INT
+#define MP1_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
+#define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
+#define MP1_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
+#define MP1_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
+//MP1_SMN_IH_SW_INT_CTRL
+#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
+#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
+#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
+#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
+//MP1_SMN_FPS_CNT
+#define MP1_SMN_FPS_CNT__COUNT__SHIFT                                                                         0x0
+#define MP1_SMN_FPS_CNT__COUNT_MASK                                                                           0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH0
+#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH0__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH1
+#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH1__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH2
+#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH2__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH3
+#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH3__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH4
+#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH4__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH5
+#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH5__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH6
+#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH6__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH7
+#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH7__DATA_MASK                                                                       0xFFFFFFFFL
+
+
+// addressBlock: mp_SmuMp1Pub_CruDec
+//MP1_CRU1_MP1_FIRMWARE_FLAGS
+#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT                                                0x0
+#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT                                                          0x1
+#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK                                                  0x00000001L
+#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK                                                            0xFFFFFFFEL
+//MP1_CRU1_MP1_PUB_SCRATCH0
+#define MP1_CRU1_MP1_PUB_SCRATCH0__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_PUB_SCRATCH0__DATA_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_PUB_SCRATCH1
+#define MP1_CRU1_MP1_PUB_SCRATCH1__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_PUB_SCRATCH1__DATA_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_PUB_SCRATCH2
+#define MP1_CRU1_MP1_PUB_SCRATCH2__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_PUB_SCRATCH2__DATA_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_PUB_SCRATCH3
+#define MP1_CRU1_MP1_PUB_SCRATCH3__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_PUB_SCRATCH3__DATA_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_0
+#define MP1_CRU1_MP1_C2PMSG_0__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_C2PMSG_0__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_1
+#define MP1_CRU1_MP1_C2PMSG_1__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_C2PMSG_1__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_2
+#define MP1_CRU1_MP1_C2PMSG_2__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_C2PMSG_2__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_3
+#define MP1_CRU1_MP1_C2PMSG_3__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_C2PMSG_3__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_4
+#define MP1_CRU1_MP1_C2PMSG_4__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_C2PMSG_4__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_5
+#define MP1_CRU1_MP1_C2PMSG_5__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_C2PMSG_5__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_6
+#define MP1_CRU1_MP1_C2PMSG_6__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_C2PMSG_6__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_7
+#define MP1_CRU1_MP1_C2PMSG_7__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_C2PMSG_7__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_8
+#define MP1_CRU1_MP1_C2PMSG_8__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_C2PMSG_8__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_9
+#define MP1_CRU1_MP1_C2PMSG_9__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_C2PMSG_9__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_10
+#define MP1_CRU1_MP1_C2PMSG_10__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_10__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_11
+#define MP1_CRU1_MP1_C2PMSG_11__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_11__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_12
+#define MP1_CRU1_MP1_C2PMSG_12__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_12__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_13
+#define MP1_CRU1_MP1_C2PMSG_13__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_13__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_14
+#define MP1_CRU1_MP1_C2PMSG_14__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_14__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_15
+#define MP1_CRU1_MP1_C2PMSG_15__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_15__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_16
+#define MP1_CRU1_MP1_C2PMSG_16__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_16__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_17
+#define MP1_CRU1_MP1_C2PMSG_17__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_17__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_18
+#define MP1_CRU1_MP1_C2PMSG_18__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_18__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_19
+#define MP1_CRU1_MP1_C2PMSG_19__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_19__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_20
+#define MP1_CRU1_MP1_C2PMSG_20__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_20__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_21
+#define MP1_CRU1_MP1_C2PMSG_21__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_21__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_22
+#define MP1_CRU1_MP1_C2PMSG_22__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_22__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_23
+#define MP1_CRU1_MP1_C2PMSG_23__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_23__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_24
+#define MP1_CRU1_MP1_C2PMSG_24__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_24__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_25
+#define MP1_CRU1_MP1_C2PMSG_25__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_25__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_26
+#define MP1_CRU1_MP1_C2PMSG_26__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_26__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_27
+#define MP1_CRU1_MP1_C2PMSG_27__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_27__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_28
+#define MP1_CRU1_MP1_C2PMSG_28__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_28__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_29
+#define MP1_CRU1_MP1_C2PMSG_29__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_29__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_30
+#define MP1_CRU1_MP1_C2PMSG_30__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_30__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_31
+#define MP1_CRU1_MP1_C2PMSG_31__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_31__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_P2CMSG_0
+#define MP1_CRU1_MP1_P2CMSG_0__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_P2CMSG_0__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_P2CMSG_1
+#define MP1_CRU1_MP1_P2CMSG_1__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_P2CMSG_1__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_P2CMSG_2
+#define MP1_CRU1_MP1_P2CMSG_2__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_P2CMSG_2__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_P2CMSG_3
+#define MP1_CRU1_MP1_P2CMSG_3__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_P2CMSG_3__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_P2CMSG_INTEN
+#define MP1_CRU1_MP1_P2CMSG_INTEN__INTEN__SHIFT                                                               0x0
+#define MP1_CRU1_MP1_P2CMSG_INTEN__INTEN_MASK                                                                 0x0000000FL
+//MP1_CRU1_MP1_P2CMSG_INTSTS
+#define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS0__SHIFT                                                            0x0
+#define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS1__SHIFT                                                            0x1
+#define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS2__SHIFT                                                            0x2
+#define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS3__SHIFT                                                            0x3
+#define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS0_MASK                                                              0x00000001L
+#define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS1_MASK                                                              0x00000002L
+#define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS2_MASK                                                              0x00000004L
+#define MP1_CRU1_MP1_P2CMSG_INTSTS__INTSTS3_MASK                                                              0x00000008L
+//MP1_CRU1_MP1_P2SMSG_0
+#define MP1_CRU1_MP1_P2SMSG_0__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_P2SMSG_0__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_P2SMSG_1
+#define MP1_CRU1_MP1_P2SMSG_1__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_P2SMSG_1__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_P2SMSG_2
+#define MP1_CRU1_MP1_P2SMSG_2__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_P2SMSG_2__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_P2SMSG_3
+#define MP1_CRU1_MP1_P2SMSG_3__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_P2SMSG_3__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_P2SMSG_INTSTS
+#define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS0__SHIFT                                                            0x0
+#define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS1__SHIFT                                                            0x1
+#define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS2__SHIFT                                                            0x2
+#define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS3__SHIFT                                                            0x3
+#define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS0_MASK                                                              0x00000001L
+#define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS1_MASK                                                              0x00000002L
+#define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS2_MASK                                                              0x00000004L
+#define MP1_CRU1_MP1_P2SMSG_INTSTS__INTSTS3_MASK                                                              0x00000008L
+//MP1_CRU1_MP1_S2PMSG_0
+#define MP1_CRU1_MP1_S2PMSG_0__CONTENT__SHIFT                                                                 0x0
+#define MP1_CRU1_MP1_S2PMSG_0__CONTENT_MASK                                                                   0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_32
+#define MP1_CRU1_MP1_C2PMSG_32__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_32__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_33
+#define MP1_CRU1_MP1_C2PMSG_33__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_33__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_34
+#define MP1_CRU1_MP1_C2PMSG_34__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_34__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_35
+#define MP1_CRU1_MP1_C2PMSG_35__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_35__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_36
+#define MP1_CRU1_MP1_C2PMSG_36__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_36__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_37
+#define MP1_CRU1_MP1_C2PMSG_37__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_37__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_38
+#define MP1_CRU1_MP1_C2PMSG_38__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_38__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_39
+#define MP1_CRU1_MP1_C2PMSG_39__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_39__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_40
+#define MP1_CRU1_MP1_C2PMSG_40__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_40__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_41
+#define MP1_CRU1_MP1_C2PMSG_41__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_41__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_42
+#define MP1_CRU1_MP1_C2PMSG_42__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_42__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_43
+#define MP1_CRU1_MP1_C2PMSG_43__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_43__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_44
+#define MP1_CRU1_MP1_C2PMSG_44__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_44__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_45
+#define MP1_CRU1_MP1_C2PMSG_45__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_45__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_46
+#define MP1_CRU1_MP1_C2PMSG_46__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_46__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_47
+#define MP1_CRU1_MP1_C2PMSG_47__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_47__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_48
+#define MP1_CRU1_MP1_C2PMSG_48__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_48__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_49
+#define MP1_CRU1_MP1_C2PMSG_49__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_49__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_50
+#define MP1_CRU1_MP1_C2PMSG_50__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_50__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_51
+#define MP1_CRU1_MP1_C2PMSG_51__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_51__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_52
+#define MP1_CRU1_MP1_C2PMSG_52__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_52__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_53
+#define MP1_CRU1_MP1_C2PMSG_53__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_53__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_54
+#define MP1_CRU1_MP1_C2PMSG_54__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_54__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_55
+#define MP1_CRU1_MP1_C2PMSG_55__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_55__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_56
+#define MP1_CRU1_MP1_C2PMSG_56__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_56__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_57
+#define MP1_CRU1_MP1_C2PMSG_57__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_57__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_58
+#define MP1_CRU1_MP1_C2PMSG_58__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_58__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_59
+#define MP1_CRU1_MP1_C2PMSG_59__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_59__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_60
+#define MP1_CRU1_MP1_C2PMSG_60__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_60__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_61
+#define MP1_CRU1_MP1_C2PMSG_61__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_61__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_62
+#define MP1_CRU1_MP1_C2PMSG_62__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_62__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_63
+#define MP1_CRU1_MP1_C2PMSG_63__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_63__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_64
+#define MP1_CRU1_MP1_C2PMSG_64__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_64__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_65
+#define MP1_CRU1_MP1_C2PMSG_65__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_65__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_66
+#define MP1_CRU1_MP1_C2PMSG_66__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_66__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_67
+#define MP1_CRU1_MP1_C2PMSG_67__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_67__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_68
+#define MP1_CRU1_MP1_C2PMSG_68__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_68__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_69
+#define MP1_CRU1_MP1_C2PMSG_69__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_69__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_70
+#define MP1_CRU1_MP1_C2PMSG_70__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_70__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_71
+#define MP1_CRU1_MP1_C2PMSG_71__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_71__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_72
+#define MP1_CRU1_MP1_C2PMSG_72__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_72__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_73
+#define MP1_CRU1_MP1_C2PMSG_73__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_73__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_74
+#define MP1_CRU1_MP1_C2PMSG_74__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_74__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_75
+#define MP1_CRU1_MP1_C2PMSG_75__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_75__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_76
+#define MP1_CRU1_MP1_C2PMSG_76__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_76__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_77
+#define MP1_CRU1_MP1_C2PMSG_77__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_77__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_78
+#define MP1_CRU1_MP1_C2PMSG_78__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_78__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_79
+#define MP1_CRU1_MP1_C2PMSG_79__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_79__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_80
+#define MP1_CRU1_MP1_C2PMSG_80__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_80__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_81
+#define MP1_CRU1_MP1_C2PMSG_81__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_81__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_82
+#define MP1_CRU1_MP1_C2PMSG_82__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_82__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_83
+#define MP1_CRU1_MP1_C2PMSG_83__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_83__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_84
+#define MP1_CRU1_MP1_C2PMSG_84__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_84__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_85
+#define MP1_CRU1_MP1_C2PMSG_85__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_85__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_86
+#define MP1_CRU1_MP1_C2PMSG_86__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_86__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_87
+#define MP1_CRU1_MP1_C2PMSG_87__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_87__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_88
+#define MP1_CRU1_MP1_C2PMSG_88__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_88__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_89
+#define MP1_CRU1_MP1_C2PMSG_89__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_89__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_90
+#define MP1_CRU1_MP1_C2PMSG_90__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_90__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_91
+#define MP1_CRU1_MP1_C2PMSG_91__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_91__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_92
+#define MP1_CRU1_MP1_C2PMSG_92__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_92__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_93
+#define MP1_CRU1_MP1_C2PMSG_93__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_93__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_94
+#define MP1_CRU1_MP1_C2PMSG_94__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_94__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_95
+#define MP1_CRU1_MP1_C2PMSG_95__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_95__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_96
+#define MP1_CRU1_MP1_C2PMSG_96__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_96__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_97
+#define MP1_CRU1_MP1_C2PMSG_97__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_97__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_98
+#define MP1_CRU1_MP1_C2PMSG_98__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_98__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_99
+#define MP1_CRU1_MP1_C2PMSG_99__CONTENT__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_C2PMSG_99__CONTENT_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_100
+#define MP1_CRU1_MP1_C2PMSG_100__CONTENT__SHIFT                                                               0x0
+#define MP1_CRU1_MP1_C2PMSG_100__CONTENT_MASK                                                                 0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_101
+#define MP1_CRU1_MP1_C2PMSG_101__CONTENT__SHIFT                                                               0x0
+#define MP1_CRU1_MP1_C2PMSG_101__CONTENT_MASK                                                                 0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_102
+#define MP1_CRU1_MP1_C2PMSG_102__CONTENT__SHIFT                                                               0x0
+#define MP1_CRU1_MP1_C2PMSG_102__CONTENT_MASK                                                                 0xFFFFFFFFL
+//MP1_CRU1_MP1_C2PMSG_103
+#define MP1_CRU1_MP1_C2PMSG_103__CONTENT__SHIFT                                                               0x0
+#define MP1_CRU1_MP1_C2PMSG_103__CONTENT_MASK                                                                 0xFFFFFFFFL
+//MP1_CRU1_MP1_IH_CREDIT
+#define MP1_CRU1_MP1_IH_CREDIT__CREDIT_VALUE__SHIFT                                                           0x0
+#define MP1_CRU1_MP1_IH_CREDIT__CLIENT_ID__SHIFT                                                              0x10
+#define MP1_CRU1_MP1_IH_CREDIT__CREDIT_VALUE_MASK                                                             0x00000003L
+#define MP1_CRU1_MP1_IH_CREDIT__CLIENT_ID_MASK                                                                0x00FF0000L
+//MP1_CRU1_MP1_IH_SW_INT
+#define MP1_CRU1_MP1_IH_SW_INT__ID__SHIFT                                                                     0x0
+#define MP1_CRU1_MP1_IH_SW_INT__VALID__SHIFT                                                                  0x8
+#define MP1_CRU1_MP1_IH_SW_INT__ID_MASK                                                                       0x000000FFL
+#define MP1_CRU1_MP1_IH_SW_INT__VALID_MASK                                                                    0x00000100L
+//MP1_CRU1_MP1_IH_SW_INT_CTRL
+#define MP1_CRU1_MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                          0x0
+#define MP1_CRU1_MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                           0x8
+#define MP1_CRU1_MP1_IH_SW_INT_CTRL__INT_MASK_MASK                                                            0x00000001L
+#define MP1_CRU1_MP1_IH_SW_INT_CTRL__INT_ACK_MASK                                                             0x00000100L
+//MP1_CRU1_MP1_FPS_CNT
+#define MP1_CRU1_MP1_FPS_CNT__COUNT__SHIFT                                                                    0x0
+#define MP1_CRU1_MP1_FPS_CNT__COUNT_MASK                                                                      0xFFFFFFFFL
+//MP1_CRU1_MP1_EXT_SCRATCH0
+#define MP1_CRU1_MP1_EXT_SCRATCH0__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_EXT_SCRATCH0__DATA_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_EXT_SCRATCH1
+#define MP1_CRU1_MP1_EXT_SCRATCH1__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_EXT_SCRATCH1__DATA_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_EXT_SCRATCH2
+#define MP1_CRU1_MP1_EXT_SCRATCH2__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_EXT_SCRATCH2__DATA_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_EXT_SCRATCH3
+#define MP1_CRU1_MP1_EXT_SCRATCH3__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_EXT_SCRATCH3__DATA_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_EXT_SCRATCH4
+#define MP1_CRU1_MP1_EXT_SCRATCH4__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_EXT_SCRATCH4__DATA_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_EXT_SCRATCH5
+#define MP1_CRU1_MP1_EXT_SCRATCH5__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_EXT_SCRATCH5__DATA_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_EXT_SCRATCH6
+#define MP1_CRU1_MP1_EXT_SCRATCH6__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_EXT_SCRATCH6__DATA_MASK                                                                  0xFFFFFFFFL
+//MP1_CRU1_MP1_EXT_SCRATCH7
+#define MP1_CRU1_MP1_EXT_SCRATCH7__DATA__SHIFT                                                                0x0
+#define MP1_CRU1_MP1_EXT_SCRATCH7__DATA_MASK                                                                  0xFFFFFFFFL
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_offset.h
new file mode 100644
index 000000000000..79eae0256dbd
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_offset.h
@@ -0,0 +1,31873 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbio_7_2_0_OFFSET_HEADER
+#define _nbio_7_2_0_OFFSET_HEADER
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_RC_VENDOR_ID                                                                    0x0000
+#define cfgBIF_CFG_DEV0_RC_DEVICE_ID                                                                    0x0002
+#define cfgBIF_CFG_DEV0_RC_COMMAND                                                                      0x0004
+#define cfgBIF_CFG_DEV0_RC_STATUS                                                                       0x0006
+#define cfgBIF_CFG_DEV0_RC_REVISION_ID                                                                  0x0008
+#define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE                                                               0x0009
+#define cfgBIF_CFG_DEV0_RC_SUB_CLASS                                                                    0x000a
+#define cfgBIF_CFG_DEV0_RC_BASE_CLASS                                                                   0x000b
+#define cfgBIF_CFG_DEV0_RC_CACHE_LINE                                                                   0x000c
+#define cfgBIF_CFG_DEV0_RC_LATENCY                                                                      0x000d
+#define cfgBIF_CFG_DEV0_RC_HEADER                                                                       0x000e
+#define cfgBIF_CFG_DEV0_RC_BIST                                                                         0x000f
+#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_1                                                                  0x0010
+#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_2                                                                  0x0014
+#define cfgBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY                                                       0x0018
+#define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT                                                                0x001c
+#define cfgBIF_CFG_DEV0_RC_SECONDARY_STATUS                                                             0x001e
+#define cfgBIF_CFG_DEV0_RC_MEM_BASE_LIMIT                                                               0x0020
+#define cfgBIF_CFG_DEV0_RC_PREF_BASE_LIMIT                                                              0x0024
+#define cfgBIF_CFG_DEV0_RC_PREF_BASE_UPPER                                                              0x0028
+#define cfgBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER                                                             0x002c
+#define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI                                                             0x0030
+#define cfgBIF_CFG_DEV0_RC_CAP_PTR                                                                      0x0034
+#define cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR                                                                0x0038
+#define cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE                                                               0x003c
+#define cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN                                                                0x003d
+#define cfgBIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL                                                              0x003e
+#define cfgBIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL                                                              0x0040
+#define cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST                                                                 0x0050
+#define cfgBIF_CFG_DEV0_RC_PMI_CAP                                                                      0x0052
+#define cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL                                                              0x0054
+#define cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST                                                                0x0058
+#define cfgBIF_CFG_DEV0_RC_PCIE_CAP                                                                     0x005a
+#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP                                                                   0x005c
+#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL                                                                  0x0060
+#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS                                                                0x0062
+#define cfgBIF_CFG_DEV0_RC_LINK_CAP                                                                     0x0064
+#define cfgBIF_CFG_DEV0_RC_LINK_CNTL                                                                    0x0068
+#define cfgBIF_CFG_DEV0_RC_LINK_STATUS                                                                  0x006a
+#define cfgBIF_CFG_DEV0_RC_SLOT_CAP                                                                     0x006c
+#define cfgBIF_CFG_DEV0_RC_SLOT_CNTL                                                                    0x0070
+#define cfgBIF_CFG_DEV0_RC_SLOT_STATUS                                                                  0x0072
+#define cfgBIF_CFG_DEV0_RC_ROOT_CNTL                                                                    0x0074
+#define cfgBIF_CFG_DEV0_RC_ROOT_CAP                                                                     0x0076
+#define cfgBIF_CFG_DEV0_RC_ROOT_STATUS                                                                  0x0078
+#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP2                                                                  0x007c
+#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2                                                                 0x0080
+#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2                                                               0x0082
+#define cfgBIF_CFG_DEV0_RC_LINK_CAP2                                                                    0x0084
+#define cfgBIF_CFG_DEV0_RC_LINK_CNTL2                                                                   0x0088
+#define cfgBIF_CFG_DEV0_RC_LINK_STATUS2                                                                 0x008a
+#define cfgBIF_CFG_DEV0_RC_SLOT_CAP2                                                                    0x008c
+#define cfgBIF_CFG_DEV0_RC_SLOT_CNTL2                                                                   0x0090
+#define cfgBIF_CFG_DEV0_RC_SLOT_STATUS2                                                                 0x0092
+#define cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST                                                                 0x00a0
+#define cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL                                                                 0x00a2
+#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO                                                              0x00a4
+#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI                                                              0x00a8
+#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA                                                                 0x00a8
+#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA                                                             0x00aa
+#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64                                                              0x00ac
+#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64                                                          0x00ae
+#define cfgBIF_CFG_DEV0_RC_SSID_CAP_LIST                                                                0x00c0
+#define cfgBIF_CFG_DEV0_RC_SSID_CAP                                                                     0x00c4
+#define cfgBIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST                                                             0x00c8
+#define cfgBIF_CFG_DEV0_RC_MSI_MAP_CAP                                                                  0x00ca
+#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                            0x0100
+#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR                                                     0x0104
+#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1                                                        0x0108
+#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2                                                        0x010c
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST                                                         0x0110
+#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1                                                        0x0114
+#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2                                                        0x0118
+#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL                                                            0x011c
+#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS                                                          0x011e
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP                                                        0x0120
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL                                                       0x0124
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS                                                     0x012a
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP                                                        0x012c
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL                                                       0x0130
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS                                                     0x0136
+#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                             0x0140
+#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1                                                      0x0144
+#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2                                                      0x0148
+#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                0x0150
+#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS                                                       0x0154
+#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK                                                         0x0158
+#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY                                                     0x015c
+#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS                                                         0x0160
+#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK                                                           0x0164
+#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL                                                        0x0168
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0                                                                0x016c
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1                                                                0x0170
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2                                                                0x0174
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3                                                                0x0178
+#define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD                                                            0x017c
+#define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS                                                         0x0180
+#define cfgBIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID                                                              0x0184
+#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0                                                         0x0188
+#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1                                                         0x018c
+#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2                                                         0x0190
+#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3                                                         0x0194
+#define cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST                                                  0x0270
+#define cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3                                                              0x0274
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS                                                       0x0278
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL                                                0x027c
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL                                                0x027e
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL                                                0x0280
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL                                                0x0282
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL                                                0x0284
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL                                                0x0286
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL                                                0x0288
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL                                                0x028a
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL                                                0x028c
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL                                                0x028e
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL                                               0x0290
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL                                               0x0292
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL                                               0x0294
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL                                               0x0296
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL                                               0x0298
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL                                               0x029a
+#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST                                                        0x02a0
+#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP                                                                 0x02a4
+#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL                                                                0x02a6
+#define cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST                                                        0x0400
+#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP                                                        0x0404
+#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS                                                     0x0408
+#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST                                                   0x0410
+#define cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT                                                                0x0414
+#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT                                                               0x0418
+#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT                                                             0x041c
+#define cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT                                            0x0420
+#define cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT                                             0x0424
+#define cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT                                             0x0428
+#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT                                                0x0430
+#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT                                                0x0431
+#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT                                                0x0432
+#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT                                                0x0433
+#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT                                                0x0434
+#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT                                                0x0435
+#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT                                                0x0436
+#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT                                                0x0437
+#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT                                                0x0438
+#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT                                                0x0439
+#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT                                               0x043a
+#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT                                               0x043b
+#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT                                               0x043c
+#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT                                               0x043d
+#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT                                               0x043e
+#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT                                               0x043f
+#define cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST                                                  0x0440
+#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP                                                           0x0444
+#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS                                                        0x0446
+#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL                                                   0x0448
+#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS                                                 0x044a
+#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL                                                   0x044c
+#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS                                                 0x044e
+#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL                                                   0x0450
+#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS                                                 0x0452
+#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL                                                   0x0454
+#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS                                                 0x0456
+#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL                                                   0x0458
+#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS                                                 0x045a
+#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL                                                   0x045c
+#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS                                                 0x045e
+#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL                                                   0x0460
+#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS                                                 0x0462
+#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL                                                   0x0464
+#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS                                                 0x0466
+#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL                                                   0x0468
+#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS                                                 0x046a
+#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL                                                   0x046c
+#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS                                                 0x046e
+#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL                                                  0x0470
+#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS                                                0x0472
+#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL                                                  0x0474
+#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS                                                0x0476
+#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL                                                  0x0478
+#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS                                                0x047a
+#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL                                                  0x047c
+#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS                                                0x047e
+#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL                                                  0x0480
+#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS                                                0x0482
+#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL                                                  0x0484
+#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS                                                0x0486
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV1_RC_VENDOR_ID                                                                    0x0000
+#define cfgBIF_CFG_DEV1_RC_DEVICE_ID                                                                    0x0002
+#define cfgBIF_CFG_DEV1_RC_COMMAND                                                                      0x0004
+#define cfgBIF_CFG_DEV1_RC_STATUS                                                                       0x0006
+#define cfgBIF_CFG_DEV1_RC_REVISION_ID                                                                  0x0008
+#define cfgBIF_CFG_DEV1_RC_PROG_INTERFACE                                                               0x0009
+#define cfgBIF_CFG_DEV1_RC_SUB_CLASS                                                                    0x000a
+#define cfgBIF_CFG_DEV1_RC_BASE_CLASS                                                                   0x000b
+#define cfgBIF_CFG_DEV1_RC_CACHE_LINE                                                                   0x000c
+#define cfgBIF_CFG_DEV1_RC_LATENCY                                                                      0x000d
+#define cfgBIF_CFG_DEV1_RC_HEADER                                                                       0x000e
+#define cfgBIF_CFG_DEV1_RC_BIST                                                                         0x000f
+#define cfgBIF_CFG_DEV1_RC_BASE_ADDR_1                                                                  0x0010
+#define cfgBIF_CFG_DEV1_RC_BASE_ADDR_2                                                                  0x0014
+#define cfgBIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY                                                       0x0018
+#define cfgBIF_CFG_DEV1_RC_IO_BASE_LIMIT                                                                0x001c
+#define cfgBIF_CFG_DEV1_RC_SECONDARY_STATUS                                                             0x001e
+#define cfgBIF_CFG_DEV1_RC_MEM_BASE_LIMIT                                                               0x0020
+#define cfgBIF_CFG_DEV1_RC_PREF_BASE_LIMIT                                                              0x0024
+#define cfgBIF_CFG_DEV1_RC_PREF_BASE_UPPER                                                              0x0028
+#define cfgBIF_CFG_DEV1_RC_PREF_LIMIT_UPPER                                                             0x002c
+#define cfgBIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI                                                             0x0030
+#define cfgBIF_CFG_DEV1_RC_CAP_PTR                                                                      0x0034
+#define cfgBIF_CFG_DEV1_RC_ROM_BASE_ADDR                                                                0x0038
+#define cfgBIF_CFG_DEV1_RC_INTERRUPT_LINE                                                               0x003c
+#define cfgBIF_CFG_DEV1_RC_INTERRUPT_PIN                                                                0x003d
+#define cfgBIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL                                                              0x003e
+#define cfgBIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL                                                              0x0040
+#define cfgBIF_CFG_DEV1_RC_PMI_CAP_LIST                                                                 0x0050
+#define cfgBIF_CFG_DEV1_RC_PMI_CAP                                                                      0x0052
+#define cfgBIF_CFG_DEV1_RC_PMI_STATUS_CNTL                                                              0x0054
+#define cfgBIF_CFG_DEV1_RC_PCIE_CAP_LIST                                                                0x0058
+#define cfgBIF_CFG_DEV1_RC_PCIE_CAP                                                                     0x005a
+#define cfgBIF_CFG_DEV1_RC_DEVICE_CAP                                                                   0x005c
+#define cfgBIF_CFG_DEV1_RC_DEVICE_CNTL                                                                  0x0060
+#define cfgBIF_CFG_DEV1_RC_DEVICE_STATUS                                                                0x0062
+#define cfgBIF_CFG_DEV1_RC_LINK_CAP                                                                     0x0064
+#define cfgBIF_CFG_DEV1_RC_LINK_CNTL                                                                    0x0068
+#define cfgBIF_CFG_DEV1_RC_LINK_STATUS                                                                  0x006a
+#define cfgBIF_CFG_DEV1_RC_SLOT_CAP                                                                     0x006c
+#define cfgBIF_CFG_DEV1_RC_SLOT_CNTL                                                                    0x0070
+#define cfgBIF_CFG_DEV1_RC_SLOT_STATUS                                                                  0x0072
+#define cfgBIF_CFG_DEV1_RC_ROOT_CNTL                                                                    0x0074
+#define cfgBIF_CFG_DEV1_RC_ROOT_CAP                                                                     0x0076
+#define cfgBIF_CFG_DEV1_RC_ROOT_STATUS                                                                  0x0078
+#define cfgBIF_CFG_DEV1_RC_DEVICE_CAP2                                                                  0x007c
+#define cfgBIF_CFG_DEV1_RC_DEVICE_CNTL2                                                                 0x0080
+#define cfgBIF_CFG_DEV1_RC_DEVICE_STATUS2                                                               0x0082
+#define cfgBIF_CFG_DEV1_RC_LINK_CAP2                                                                    0x0084
+#define cfgBIF_CFG_DEV1_RC_LINK_CNTL2                                                                   0x0088
+#define cfgBIF_CFG_DEV1_RC_LINK_STATUS2                                                                 0x008a
+#define cfgBIF_CFG_DEV1_RC_SLOT_CAP2                                                                    0x008c
+#define cfgBIF_CFG_DEV1_RC_SLOT_CNTL2                                                                   0x0090
+#define cfgBIF_CFG_DEV1_RC_SLOT_STATUS2                                                                 0x0092
+#define cfgBIF_CFG_DEV1_RC_MSI_CAP_LIST                                                                 0x00a0
+#define cfgBIF_CFG_DEV1_RC_MSI_MSG_CNTL                                                                 0x00a2
+#define cfgBIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO                                                              0x00a4
+#define cfgBIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI                                                              0x00a8
+#define cfgBIF_CFG_DEV1_RC_MSI_MSG_DATA                                                                 0x00a8
+#define cfgBIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA                                                             0x00aa
+#define cfgBIF_CFG_DEV1_RC_MSI_MSG_DATA_64                                                              0x00ac
+#define cfgBIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64                                                          0x00ae
+#define cfgBIF_CFG_DEV1_RC_SSID_CAP_LIST                                                                0x00c0
+#define cfgBIF_CFG_DEV1_RC_SSID_CAP                                                                     0x00c4
+#define cfgBIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST                                                             0x00c8
+#define cfgBIF_CFG_DEV1_RC_MSI_MAP_CAP                                                                  0x00ca
+#define cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                            0x0100
+#define cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR                                                     0x0104
+#define cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1                                                        0x0108
+#define cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2                                                        0x010c
+#define cfgBIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST                                                         0x0110
+#define cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1                                                        0x0114
+#define cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2                                                        0x0118
+#define cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL                                                            0x011c
+#define cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS                                                          0x011e
+#define cfgBIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP                                                        0x0120
+#define cfgBIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL                                                       0x0124
+#define cfgBIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS                                                     0x012a
+#define cfgBIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP                                                        0x012c
+#define cfgBIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL                                                       0x0130
+#define cfgBIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS                                                     0x0136
+#define cfgBIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                             0x0140
+#define cfgBIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1                                                      0x0144
+#define cfgBIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2                                                      0x0148
+#define cfgBIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                0x0150
+#define cfgBIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS                                                       0x0154
+#define cfgBIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK                                                         0x0158
+#define cfgBIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY                                                     0x015c
+#define cfgBIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS                                                         0x0160
+#define cfgBIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK                                                           0x0164
+#define cfgBIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL                                                        0x0168
+#define cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG0                                                                0x016c
+#define cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG1                                                                0x0170
+#define cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG2                                                                0x0174
+#define cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG3                                                                0x0178
+#define cfgBIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD                                                            0x017c
+#define cfgBIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS                                                         0x0180
+#define cfgBIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID                                                              0x0184
+#define cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0                                                         0x0188
+#define cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1                                                         0x018c
+#define cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2                                                         0x0190
+#define cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3                                                         0x0194
+#define cfgBIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST                                                  0x0270
+#define cfgBIF_CFG_DEV1_RC_PCIE_LINK_CNTL3                                                              0x0274
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS                                                       0x0278
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL                                                0x027c
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL                                                0x027e
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL                                                0x0280
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL                                                0x0282
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL                                                0x0284
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL                                                0x0286
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL                                                0x0288
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL                                                0x028a
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL                                                0x028c
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL                                                0x028e
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL                                               0x0290
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL                                               0x0292
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL                                               0x0294
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL                                               0x0296
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL                                               0x0298
+#define cfgBIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL                                               0x029a
+#define cfgBIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST                                                        0x02a0
+#define cfgBIF_CFG_DEV1_RC_PCIE_ACS_CAP                                                                 0x02a4
+#define cfgBIF_CFG_DEV1_RC_PCIE_ACS_CNTL                                                                0x02a6
+#define cfgBIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST                                                        0x0400
+#define cfgBIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP                                                        0x0404
+#define cfgBIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS                                                     0x0408
+#define cfgBIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST                                                   0x0410
+#define cfgBIF_CFG_DEV1_RC_LINK_CAP_16GT                                                                0x0414
+#define cfgBIF_CFG_DEV1_RC_LINK_CNTL_16GT                                                               0x0418
+#define cfgBIF_CFG_DEV1_RC_LINK_STATUS_16GT                                                             0x041c
+#define cfgBIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT                                            0x0420
+#define cfgBIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT                                             0x0424
+#define cfgBIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT                                             0x0428
+#define cfgBIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT                                                0x0430
+#define cfgBIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT                                                0x0431
+#define cfgBIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT                                                0x0432
+#define cfgBIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT                                                0x0433
+#define cfgBIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT                                                0x0434
+#define cfgBIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT                                                0x0435
+#define cfgBIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT                                                0x0436
+#define cfgBIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT                                                0x0437
+#define cfgBIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT                                                0x0438
+#define cfgBIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT                                                0x0439
+#define cfgBIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT                                               0x043a
+#define cfgBIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT                                               0x043b
+#define cfgBIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT                                               0x043c
+#define cfgBIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT                                               0x043d
+#define cfgBIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT                                               0x043e
+#define cfgBIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT                                               0x043f
+#define cfgBIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST                                                  0x0440
+#define cfgBIF_CFG_DEV1_RC_MARGINING_PORT_CAP                                                           0x0444
+#define cfgBIF_CFG_DEV1_RC_MARGINING_PORT_STATUS                                                        0x0446
+#define cfgBIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL                                                   0x0448
+#define cfgBIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS                                                 0x044a
+#define cfgBIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL                                                   0x044c
+#define cfgBIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS                                                 0x044e
+#define cfgBIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL                                                   0x0450
+#define cfgBIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS                                                 0x0452
+#define cfgBIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL                                                   0x0454
+#define cfgBIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS                                                 0x0456
+#define cfgBIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL                                                   0x0458
+#define cfgBIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS                                                 0x045a
+#define cfgBIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL                                                   0x045c
+#define cfgBIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS                                                 0x045e
+#define cfgBIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL                                                   0x0460
+#define cfgBIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS                                                 0x0462
+#define cfgBIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL                                                   0x0464
+#define cfgBIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS                                                 0x0466
+#define cfgBIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL                                                   0x0468
+#define cfgBIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS                                                 0x046a
+#define cfgBIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL                                                   0x046c
+#define cfgBIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS                                                 0x046e
+#define cfgBIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL                                                  0x0470
+#define cfgBIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS                                                0x0472
+#define cfgBIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL                                                  0x0474
+#define cfgBIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS                                                0x0476
+#define cfgBIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL                                                  0x0478
+#define cfgBIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS                                                0x047a
+#define cfgBIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL                                                  0x047c
+#define cfgBIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS                                                0x047e
+#define cfgBIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL                                                  0x0480
+#define cfgBIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS                                                0x0482
+#define cfgBIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL                                                  0x0484
+#define cfgBIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS                                                0x0486
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID                                                                  0x0000
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID                                                                  0x0002
+#define cfgBIF_CFG_DEV0_EPF0_COMMAND                                                                    0x0004
+#define cfgBIF_CFG_DEV0_EPF0_STATUS                                                                     0x0006
+#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID                                                                0x0008
+#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE                                                             0x0009
+#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS                                                                  0x000a
+#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS                                                                 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE                                                                 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_LATENCY                                                                    0x000d
+#define cfgBIF_CFG_DEV0_EPF0_HEADER                                                                     0x000e
+#define cfgBIF_CFG_DEV0_EPF0_BIST                                                                       0x000f
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1                                                                0x0010
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2                                                                0x0014
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3                                                                0x0018
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4                                                                0x001c
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5                                                                0x0020
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6                                                                0x0024
+#define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR                                                            0x0028
+#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID                                                                 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR                                                              0x0030
+#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR                                                                    0x0034
+#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE                                                             0x003c
+#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN                                                              0x003d
+#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT                                                                  0x003e
+#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY                                                                0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST                                                            0x0048
+#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W                                                               0x004c
+#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST                                                               0x0050
+#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP                                                                    0x0052
+#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL                                                            0x0054
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST                                                              0x0064
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP                                                                   0x0066
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP                                                                 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL                                                                0x006c
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS                                                              0x006e
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP                                                                   0x0070
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL                                                                  0x0074
+#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS                                                                0x0076
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2                                                                0x0088
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2                                                               0x008c
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2                                                             0x008e
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2                                                                  0x0090
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2                                                                 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2                                                               0x0096
+#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST                                                               0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL                                                               0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO                                                            0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI                                                            0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA                                                               0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA                                                           0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK                                                                   0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64                                                            0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64                                                        0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64                                                             0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST                                                              0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL                                                              0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE                                                                 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA                                                                   0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                          0x0100
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR                                                   0x0104
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1                                                      0x0108
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2                                                      0x010c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST                                                       0x0110
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1                                                      0x0114
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2                                                      0x0118
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL                                                          0x011c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS                                                        0x011e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP                                                      0x0120
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL                                                     0x0124
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS                                                   0x012a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP                                                      0x012c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL                                                     0x0130
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS                                                   0x0136
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                           0x0140
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1                                                    0x0144
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2                                                    0x0148
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                              0x0150
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS                                                     0x0154
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK                                                       0x0158
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY                                                   0x015c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS                                                       0x0160
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK                                                         0x0164
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL                                                      0x0168
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0                                                              0x016c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1                                                              0x0170
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2                                                              0x0174
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3                                                              0x0178
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0                                                       0x0188
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1                                                       0x018c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2                                                       0x0190
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3                                                       0x0194
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST                                                      0x0200
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP                                                              0x0204
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL                                                             0x0208
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP                                                              0x020c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL                                                             0x0210
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP                                                              0x0214
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL                                                             0x0218
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP                                                              0x021c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL                                                             0x0220
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP                                                              0x0224
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL                                                             0x0228
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP                                                              0x022c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL                                                             0x0230
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                               0x0240
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT                                                0x0244
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA                                                       0x0248
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP                                                        0x024c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST                                                      0x0250
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP                                                               0x0254
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR                                                 0x0258
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS                                                            0x025c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL                                                              0x025e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                              0x0260
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                              0x0261
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                              0x0262
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                              0x0263
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                              0x0264
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                              0x0265
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                              0x0266
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                              0x0267
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST                                                0x0270
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3                                                            0x0274
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS                                                     0x0278
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL                                              0x027c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL                                              0x027e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL                                              0x0280
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL                                              0x0282
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL                                              0x0284
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL                                              0x0286
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL                                              0x0288
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL                                              0x028a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL                                              0x028c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL                                              0x028e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL                                             0x0290
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL                                             0x0292
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL                                             0x0294
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL                                             0x0296
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL                                             0x0298
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL                                             0x029a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST                                                      0x02a0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP                                                               0x02a4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL                                                              0x02a6
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST                                                      0x02b0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP                                                               0x02b4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL                                                              0x02b6
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST                                                 0x02c0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL                                                         0x02c4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS                                                       0x02c6
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY                                            0x02c8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC                                               0x02cc
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST                                                    0x02d0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP                                                             0x02d4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL                                                            0x02d6
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST                                                       0x02f0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP                                                                0x02f4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL                                                               0x02f6
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0                                                              0x02f8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1                                                              0x02fc
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0                                                               0x0300
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1                                                               0x0304
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0                                                         0x0308
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1                                                         0x030c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0                                               0x0310
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1                                               0x0314
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST                                                      0x0320
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP                                                               0x0324
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST                                                      0x0328
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP                                                               0x032c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL                                                              0x032e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST                                                    0x0330
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP                                                             0x0334
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL                                                         0x0338
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS                                                          0x033a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS                                                     0x033c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS                                                       0x033e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS                                                         0x0340
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK                                                   0x0342
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET                                                 0x0344
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE                                                       0x0346
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID                                                    0x034a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                             0x034c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                                0x0350
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0                                                  0x0354
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1                                                  0x0358
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2                                                  0x035c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3                                                  0x0360
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4                                                  0x0364
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5                                                  0x0368
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                                 0x036c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST                                                 0x0370
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP                                                          0x0374
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL                                                         0x0378
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST                                                      0x0400
+#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP                                                      0x0404
+#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS                                                   0x0408
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST                                                 0x0410
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT                                                              0x0414
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT                                                             0x0418
+#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT                                                           0x041c
+#define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                          0x0420
+#define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT                                           0x0424
+#define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT                                           0x0428
+#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT                                              0x0430
+#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT                                              0x0431
+#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT                                              0x0432
+#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT                                              0x0433
+#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT                                              0x0434
+#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT                                              0x0435
+#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT                                              0x0436
+#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT                                              0x0437
+#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT                                              0x0438
+#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT                                              0x0439
+#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT                                             0x043a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT                                             0x043b
+#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT                                             0x043c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT                                             0x043d
+#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT                                             0x043e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT                                             0x043f
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST                                                0x0440
+#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP                                                         0x0444
+#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS                                                      0x0446
+#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL                                                 0x0448
+#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS                                               0x044a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL                                                 0x044c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS                                               0x044e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL                                                 0x0450
+#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS                                               0x0452
+#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL                                                 0x0454
+#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS                                               0x0456
+#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL                                                 0x0458
+#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS                                               0x045a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL                                                 0x045c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS                                               0x045e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL                                                 0x0460
+#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS                                               0x0462
+#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL                                                 0x0464
+#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS                                               0x0466
+#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL                                                 0x0468
+#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS                                               0x046a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL                                                 0x046c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS                                               0x046e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL                                                0x0470
+#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS                                              0x0472
+#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL                                                0x0474
+#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS                                              0x0476
+#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL                                                0x0478
+#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS                                              0x047a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL                                                0x047c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS                                              0x047e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL                                                0x0480
+#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS                                              0x0482
+#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL                                                0x0484
+#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS                                              0x0486
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                            0x04c0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP                                                    0x04c4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL                                                   0x04c8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP                                                    0x04cc
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL                                                   0x04d0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP                                                    0x04d4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL                                                   0x04d8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP                                                    0x04dc
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL                                                   0x04e0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP                                                    0x04e4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL                                                   0x04e8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP                                                    0x04ec
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL                                                   0x04f0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                   0x0500
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                            0x0504
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                               0x0508
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                                0x050c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                                0x0510
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                              0x0514
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                              0x0518
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                              0x051c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                              0x0520
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                                    0x0524
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                   0x0528
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                                    0x052c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                     0x0530
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                       0x0534
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                     0x0538
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                     0x053c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                     0x0540
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                     0x0544
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                     0x0548
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                     0x054c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                     0x0550
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                     0x0554
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                     0x0558
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                     0x055c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                                    0x0560
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                                    0x0564
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                                    0x0568
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                                    0x056c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                                    0x0570
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                                    0x0574
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB                                    0x0578
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB                                    0x057c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB                                    0x0580
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB                                    0x0584
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB                                    0x0588
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB                                    0x058c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB                                    0x0590
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB                                    0x0594
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB                                    0x0598
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB                                    0x059c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB                                    0x05a0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB                                    0x05a4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB                                    0x05a8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB                                    0x05ac
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB                                    0x05b0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0                                 0x05c0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1                                 0x05c4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2                                 0x05c8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3                                 0x05cc
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4                                 0x05d0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5                                 0x05d4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6                                 0x05d8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7                                 0x05dc
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8                                 0x05e0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0                                 0x05f0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1                                 0x05f4
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2                                 0x05f8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3                                 0x05fc
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4                                 0x0600
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5                                 0x0604
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6                                 0x0608
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7                                 0x060c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8                                 0x0610
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0                                 0x0620
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1                                 0x0624
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2                                 0x0628
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3                                 0x062c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4                                 0x0630
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5                                 0x0634
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6                                 0x0638
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7                                 0x063c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8                                 0x0640
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0                                0x0650
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1                                0x0654
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2                                0x0658
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3                                0x065c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4                                0x0660
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5                                0x0664
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6                                0x0668
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7                                0x066c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8                                0x0670
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF1_VENDOR_ID                                                                  0x0000
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_ID                                                                  0x0002
+#define cfgBIF_CFG_DEV0_EPF1_COMMAND                                                                    0x0004
+#define cfgBIF_CFG_DEV0_EPF1_STATUS                                                                     0x0006
+#define cfgBIF_CFG_DEV0_EPF1_REVISION_ID                                                                0x0008
+#define cfgBIF_CFG_DEV0_EPF1_PROG_INTERFACE                                                             0x0009
+#define cfgBIF_CFG_DEV0_EPF1_SUB_CLASS                                                                  0x000a
+#define cfgBIF_CFG_DEV0_EPF1_BASE_CLASS                                                                 0x000b
+#define cfgBIF_CFG_DEV0_EPF1_CACHE_LINE                                                                 0x000c
+#define cfgBIF_CFG_DEV0_EPF1_LATENCY                                                                    0x000d
+#define cfgBIF_CFG_DEV0_EPF1_HEADER                                                                     0x000e
+#define cfgBIF_CFG_DEV0_EPF1_BIST                                                                       0x000f
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_1                                                                0x0010
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_2                                                                0x0014
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_3                                                                0x0018
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_4                                                                0x001c
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_5                                                                0x0020
+#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_6                                                                0x0024
+#define cfgBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR                                                            0x0028
+#define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID                                                                 0x002c
+#define cfgBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR                                                              0x0030
+#define cfgBIF_CFG_DEV0_EPF1_CAP_PTR                                                                    0x0034
+#define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_LINE                                                             0x003c
+#define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_PIN                                                              0x003d
+#define cfgBIF_CFG_DEV0_EPF1_MIN_GRANT                                                                  0x003e
+#define cfgBIF_CFG_DEV0_EPF1_MAX_LATENCY                                                                0x003f
+#define cfgBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST                                                            0x0048
+#define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID_W                                                               0x004c
+#define cfgBIF_CFG_DEV0_EPF1_PMI_CAP_LIST                                                               0x0050
+#define cfgBIF_CFG_DEV0_EPF1_PMI_CAP                                                                    0x0052
+#define cfgBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL                                                            0x0054
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST                                                              0x0064
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP                                                                   0x0066
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP                                                                 0x0068
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL                                                                0x006c
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS                                                              0x006e
+#define cfgBIF_CFG_DEV0_EPF1_LINK_CAP                                                                   0x0070
+#define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL                                                                  0x0074
+#define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS                                                                0x0076
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP2                                                                0x0088
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL2                                                               0x008c
+#define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS2                                                             0x008e
+#define cfgBIF_CFG_DEV0_EPF1_LINK_CAP2                                                                  0x0090
+#define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL2                                                                 0x0094
+#define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS2                                                               0x0096
+#define cfgBIF_CFG_DEV0_EPF1_MSI_CAP_LIST                                                               0x00a0
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL                                                               0x00a2
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO                                                            0x00a4
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI                                                            0x00a8
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA                                                               0x00a8
+#define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA                                                           0x00aa
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MASK                                                                   0x00ac
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64                                                            0x00ac
+#define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64                                                        0x00ae
+#define cfgBIF_CFG_DEV0_EPF1_MSI_MASK_64                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING_64                                                             0x00b4
+#define cfgBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST                                                              0x00c0
+#define cfgBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL                                                              0x00c2
+#define cfgBIF_CFG_DEV0_EPF1_MSIX_TABLE                                                                 0x00c4
+#define cfgBIF_CFG_DEV0_EPF1_MSIX_PBA                                                                   0x00c8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                          0x0100
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR                                                   0x0104
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1                                                      0x0108
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2                                                      0x010c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST                                                       0x0110
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1                                                      0x0114
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2                                                      0x0118
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL                                                          0x011c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS                                                        0x011e
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP                                                      0x0120
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL                                                     0x0124
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS                                                   0x012a
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP                                                      0x012c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL                                                     0x0130
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS                                                   0x0136
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                           0x0140
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1                                                    0x0144
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2                                                    0x0148
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                              0x0150
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS                                                     0x0154
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK                                                       0x0158
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY                                                   0x015c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS                                                       0x0160
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK                                                         0x0164
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL                                                      0x0168
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0                                                              0x016c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1                                                              0x0170
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2                                                              0x0174
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3                                                              0x0178
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0                                                       0x0188
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1                                                       0x018c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2                                                       0x0190
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3                                                       0x0194
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST                                                      0x0200
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP                                                              0x0204
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL                                                             0x0208
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP                                                              0x020c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL                                                             0x0210
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP                                                              0x0214
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL                                                             0x0218
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP                                                              0x021c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL                                                             0x0220
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP                                                              0x0224
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL                                                             0x0228
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP                                                              0x022c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL                                                             0x0230
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                               0x0240
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT                                                0x0244
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA                                                       0x0248
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP                                                        0x024c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST                                                      0x0250
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP                                                               0x0254
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR                                                 0x0258
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS                                                            0x025c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL                                                              0x025e
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                              0x0260
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                              0x0261
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                              0x0262
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                              0x0263
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                              0x0264
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                              0x0265
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                              0x0266
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                              0x0267
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST                                                0x0270
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3                                                            0x0274
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS                                                     0x0278
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL                                              0x027c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL                                              0x027e
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL                                              0x0280
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL                                              0x0282
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL                                              0x0284
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL                                              0x0286
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL                                              0x0288
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL                                              0x028a
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL                                              0x028c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL                                              0x028e
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL                                             0x0290
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL                                             0x0292
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL                                             0x0294
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL                                             0x0296
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL                                             0x0298
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL                                             0x029a
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST                                                      0x02a0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP                                                               0x02a4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL                                                              0x02a6
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST                                                      0x02b0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ATS_CAP                                                               0x02b4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL                                                              0x02b6
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST                                                 0x02c0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL                                                         0x02c4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS                                                       0x02c6
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY                                            0x02c8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC                                               0x02cc
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST                                                    0x02d0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP                                                             0x02d4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL                                                            0x02d6
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST                                                       0x02f0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_CAP                                                                0x02f4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL                                                               0x02f6
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0                                                              0x02f8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1                                                              0x02fc
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0                                                               0x0300
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1                                                               0x0304
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0                                                         0x0308
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1                                                         0x030c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0                                               0x0310
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1                                               0x0314
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST                                                      0x0320
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP                                                               0x0324
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST                                                      0x0328
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP                                                               0x032c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL                                                              0x032e
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST                                                    0x0330
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP                                                             0x0334
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL                                                         0x0338
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS                                                          0x033a
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS                                                     0x033c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS                                                       0x033e
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS                                                         0x0340
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK                                                   0x0342
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET                                                 0x0344
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE                                                       0x0346
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID                                                    0x034a
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                             0x034c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                                0x0350
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0                                                  0x0354
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1                                                  0x0358
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2                                                  0x035c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3                                                  0x0360
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4                                                  0x0364
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5                                                  0x0368
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                                 0x036c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST                                                 0x0370
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP                                                          0x0374
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL                                                         0x0378
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST                                                      0x0400
+#define cfgBIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP                                                      0x0404
+#define cfgBIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS                                                   0x0408
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST                                                 0x0410
+#define cfgBIF_CFG_DEV0_EPF1_LINK_CAP_16GT                                                              0x0414
+#define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL_16GT                                                             0x0418
+#define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS_16GT                                                           0x041c
+#define cfgBIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                          0x0420
+#define cfgBIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT                                           0x0424
+#define cfgBIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT                                           0x0428
+#define cfgBIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT                                              0x0430
+#define cfgBIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT                                              0x0431
+#define cfgBIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT                                              0x0432
+#define cfgBIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT                                              0x0433
+#define cfgBIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT                                              0x0434
+#define cfgBIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT                                              0x0435
+#define cfgBIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT                                              0x0436
+#define cfgBIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT                                              0x0437
+#define cfgBIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT                                              0x0438
+#define cfgBIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT                                              0x0439
+#define cfgBIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT                                             0x043a
+#define cfgBIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT                                             0x043b
+#define cfgBIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT                                             0x043c
+#define cfgBIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT                                             0x043d
+#define cfgBIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT                                             0x043e
+#define cfgBIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT                                             0x043f
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST                                                0x0440
+#define cfgBIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP                                                         0x0444
+#define cfgBIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS                                                      0x0446
+#define cfgBIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL                                                 0x0448
+#define cfgBIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS                                               0x044a
+#define cfgBIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL                                                 0x044c
+#define cfgBIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS                                               0x044e
+#define cfgBIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL                                                 0x0450
+#define cfgBIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS                                               0x0452
+#define cfgBIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL                                                 0x0454
+#define cfgBIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS                                               0x0456
+#define cfgBIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL                                                 0x0458
+#define cfgBIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS                                               0x045a
+#define cfgBIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL                                                 0x045c
+#define cfgBIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS                                               0x045e
+#define cfgBIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL                                                 0x0460
+#define cfgBIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS                                               0x0462
+#define cfgBIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL                                                 0x0464
+#define cfgBIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS                                               0x0466
+#define cfgBIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL                                                 0x0468
+#define cfgBIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS                                               0x046a
+#define cfgBIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL                                                 0x046c
+#define cfgBIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS                                               0x046e
+#define cfgBIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL                                                0x0470
+#define cfgBIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS                                              0x0472
+#define cfgBIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL                                                0x0474
+#define cfgBIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS                                              0x0476
+#define cfgBIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL                                                0x0478
+#define cfgBIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS                                              0x047a
+#define cfgBIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL                                                0x047c
+#define cfgBIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS                                              0x047e
+#define cfgBIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL                                                0x0480
+#define cfgBIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS                                              0x0482
+#define cfgBIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL                                                0x0484
+#define cfgBIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS                                              0x0486
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                            0x04c0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP                                                    0x04c4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL                                                   0x04c8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP                                                    0x04cc
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL                                                   0x04d0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP                                                    0x04d4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL                                                   0x04d8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP                                                    0x04dc
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL                                                   0x04e0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP                                                    0x04e4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL                                                   0x04e8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP                                                    0x04ec
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL                                                   0x04f0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                   0x0500
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                            0x0504
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                               0x0508
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                                0x050c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                                0x0510
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                              0x0514
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                              0x0518
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                              0x051c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                              0x0520
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                                    0x0524
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                   0x0528
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                                    0x052c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                     0x0530
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                       0x0534
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                     0x0538
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                     0x053c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                     0x0540
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                     0x0544
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                     0x0548
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                     0x054c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                     0x0550
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                     0x0554
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                     0x0558
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                     0x055c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                                    0x0560
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                                    0x0564
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                                    0x0568
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                                    0x056c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                                    0x0570
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                                    0x0574
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB                                    0x0578
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB                                    0x057c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB                                    0x0580
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB                                    0x0584
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB                                    0x0588
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB                                    0x058c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB                                    0x0590
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB                                    0x0594
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB                                    0x0598
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB                                    0x059c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB                                    0x05a0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB                                    0x05a4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB                                    0x05a8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB                                    0x05ac
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB                                    0x05b0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0                                 0x05c0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1                                 0x05c4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2                                 0x05c8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3                                 0x05cc
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4                                 0x05d0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5                                 0x05d4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6                                 0x05d8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7                                 0x05dc
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8                                 0x05e0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0                                 0x05f0
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1                                 0x05f4
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2                                 0x05f8
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3                                 0x05fc
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4                                 0x0600
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5                                 0x0604
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6                                 0x0608
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7                                 0x060c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8                                 0x0610
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0                                 0x0620
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1                                 0x0624
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2                                 0x0628
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3                                 0x062c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4                                 0x0630
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5                                 0x0634
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6                                 0x0638
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7                                 0x063c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8                                 0x0640
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0                                0x0650
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1                                0x0654
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2                                0x0658
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3                                0x065c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4                                0x0660
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5                                0x0664
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6                                0x0668
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7                                0x066c
+#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8                                0x0670
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF2_VENDOR_ID                                                                  0x0000
+#define cfgBIF_CFG_DEV0_EPF2_DEVICE_ID                                                                  0x0002
+#define cfgBIF_CFG_DEV0_EPF2_COMMAND                                                                    0x0004
+#define cfgBIF_CFG_DEV0_EPF2_STATUS                                                                     0x0006
+#define cfgBIF_CFG_DEV0_EPF2_REVISION_ID                                                                0x0008
+#define cfgBIF_CFG_DEV0_EPF2_PROG_INTERFACE                                                             0x0009
+#define cfgBIF_CFG_DEV0_EPF2_SUB_CLASS                                                                  0x000a
+#define cfgBIF_CFG_DEV0_EPF2_BASE_CLASS                                                                 0x000b
+#define cfgBIF_CFG_DEV0_EPF2_CACHE_LINE                                                                 0x000c
+#define cfgBIF_CFG_DEV0_EPF2_LATENCY                                                                    0x000d
+#define cfgBIF_CFG_DEV0_EPF2_HEADER                                                                     0x000e
+#define cfgBIF_CFG_DEV0_EPF2_BIST                                                                       0x000f
+#define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_1                                                                0x0010
+#define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_2                                                                0x0014
+#define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_3                                                                0x0018
+#define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_4                                                                0x001c
+#define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_5                                                                0x0020
+#define cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_6                                                                0x0024
+#define cfgBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR                                                            0x0028
+#define cfgBIF_CFG_DEV0_EPF2_ADAPTER_ID                                                                 0x002c
+#define cfgBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR                                                              0x0030
+#define cfgBIF_CFG_DEV0_EPF2_CAP_PTR                                                                    0x0034
+#define cfgBIF_CFG_DEV0_EPF2_INTERRUPT_LINE                                                             0x003c
+#define cfgBIF_CFG_DEV0_EPF2_INTERRUPT_PIN                                                              0x003d
+#define cfgBIF_CFG_DEV0_EPF2_MIN_GRANT                                                                  0x003e
+#define cfgBIF_CFG_DEV0_EPF2_MAX_LATENCY                                                                0x003f
+#define cfgBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST                                                            0x0048
+#define cfgBIF_CFG_DEV0_EPF2_ADAPTER_ID_W                                                               0x004c
+#define cfgBIF_CFG_DEV0_EPF2_PMI_CAP_LIST                                                               0x0050
+#define cfgBIF_CFG_DEV0_EPF2_PMI_CAP                                                                    0x0052
+#define cfgBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL                                                            0x0054
+#define cfgBIF_CFG_DEV0_EPF2_SBRN                                                                       0x0060
+#define cfgBIF_CFG_DEV0_EPF2_FLADJ                                                                      0x0061
+#define cfgBIF_CFG_DEV0_EPF2_DBESL_DBESLD                                                               0x0062
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST                                                              0x0064
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_CAP                                                                   0x0066
+#define cfgBIF_CFG_DEV0_EPF2_DEVICE_CAP                                                                 0x0068
+#define cfgBIF_CFG_DEV0_EPF2_DEVICE_CNTL                                                                0x006c
+#define cfgBIF_CFG_DEV0_EPF2_DEVICE_STATUS                                                              0x006e
+#define cfgBIF_CFG_DEV0_EPF2_LINK_CAP                                                                   0x0070
+#define cfgBIF_CFG_DEV0_EPF2_LINK_CNTL                                                                  0x0074
+#define cfgBIF_CFG_DEV0_EPF2_LINK_STATUS                                                                0x0076
+#define cfgBIF_CFG_DEV0_EPF2_DEVICE_CAP2                                                                0x0088
+#define cfgBIF_CFG_DEV0_EPF2_DEVICE_CNTL2                                                               0x008c
+#define cfgBIF_CFG_DEV0_EPF2_DEVICE_STATUS2                                                             0x008e
+#define cfgBIF_CFG_DEV0_EPF2_LINK_CAP2                                                                  0x0090
+#define cfgBIF_CFG_DEV0_EPF2_LINK_CNTL2                                                                 0x0094
+#define cfgBIF_CFG_DEV0_EPF2_LINK_STATUS2                                                               0x0096
+#define cfgBIF_CFG_DEV0_EPF2_MSI_CAP_LIST                                                               0x00a0
+#define cfgBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL                                                               0x00a2
+#define cfgBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO                                                            0x00a4
+#define cfgBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI                                                            0x00a8
+#define cfgBIF_CFG_DEV0_EPF2_MSI_MSG_DATA                                                               0x00a8
+#define cfgBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA                                                           0x00aa
+#define cfgBIF_CFG_DEV0_EPF2_MSI_MASK                                                                   0x00ac
+#define cfgBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64                                                            0x00ac
+#define cfgBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64                                                        0x00ae
+#define cfgBIF_CFG_DEV0_EPF2_MSI_MASK_64                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF2_MSI_PENDING                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF2_MSI_PENDING_64                                                             0x00b4
+#define cfgBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST                                                              0x00c0
+#define cfgBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL                                                              0x00c2
+#define cfgBIF_CFG_DEV0_EPF2_MSIX_TABLE                                                                 0x00c4
+#define cfgBIF_CFG_DEV0_EPF2_MSIX_PBA                                                                   0x00c8
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                          0x0100
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR                                                   0x0104
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1                                                      0x0108
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2                                                      0x010c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                              0x0150
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS                                                     0x0154
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK                                                       0x0158
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY                                                   0x015c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS                                                       0x0160
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK                                                         0x0164
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL                                                      0x0168
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0                                                              0x016c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1                                                              0x0170
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2                                                              0x0174
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3                                                              0x0178
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0                                                       0x0188
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1                                                       0x018c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2                                                       0x0190
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3                                                       0x0194
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST                                                      0x0200
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP                                                              0x0204
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL                                                             0x0208
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP                                                              0x020c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL                                                             0x0210
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP                                                              0x0214
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL                                                             0x0218
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP                                                              0x021c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL                                                             0x0220
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP                                                              0x0224
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL                                                             0x0228
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP                                                              0x022c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL                                                             0x0230
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST                                               0x0240
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT                                                0x0244
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA                                                       0x0248
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP                                                        0x024c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST                                                      0x0250
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP                                                               0x0254
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR                                                 0x0258
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS                                                            0x025c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL                                                              0x025e
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                              0x0260
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                              0x0261
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                              0x0262
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                              0x0263
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                              0x0264
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                              0x0265
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                              0x0266
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                              0x0267
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST                                                      0x02a0
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP                                                               0x02a4
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL                                                              0x02a6
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST                                                    0x02d0
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP                                                             0x02d4
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL                                                            0x02d6
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST                                                      0x0328
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP                                                               0x032c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL                                                              0x032e
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST                                                 0x0370
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP                                                          0x0374
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL                                                         0x0378
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0                                                        0x037c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1                                                        0x037e
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2                                                        0x0380
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3                                                        0x0382
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4                                                        0x0384
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5                                                        0x0386
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6                                                        0x0388
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7                                                        0x038a
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8                                                        0x038c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9                                                        0x038e
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10                                                       0x0390
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11                                                       0x0392
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12                                                       0x0394
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13                                                       0x0396
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14                                                       0x0398
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15                                                       0x039a
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16                                                       0x039c
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17                                                       0x039e
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18                                                       0x03a0
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19                                                       0x03a2
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20                                                       0x03a4
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21                                                       0x03a6
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22                                                       0x03a8
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23                                                       0x03aa
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24                                                       0x03ac
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25                                                       0x03ae
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26                                                       0x03b0
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27                                                       0x03b2
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28                                                       0x03b4
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29                                                       0x03b6
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30                                                       0x03b8
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31                                                       0x03ba
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32                                                       0x03bc
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33                                                       0x03be
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34                                                       0x03c0
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35                                                       0x03c2
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36                                                       0x03c4
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37                                                       0x03c6
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38                                                       0x03c8
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39                                                       0x03ca
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40                                                       0x03cc
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41                                                       0x03ce
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42                                                       0x03d0
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43                                                       0x03d2
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44                                                       0x03d4
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45                                                       0x03d6
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46                                                       0x03d8
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47                                                       0x03da
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48                                                       0x03dc
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49                                                       0x03de
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50                                                       0x03e0
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51                                                       0x03e2
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52                                                       0x03e4
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53                                                       0x03e6
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54                                                       0x03e8
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55                                                       0x03ea
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56                                                       0x03ec
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57                                                       0x03ee
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58                                                       0x03f0
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59                                                       0x03f2
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60                                                       0x03f4
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61                                                       0x03f6
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62                                                       0x03f8
+#define cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63                                                       0x03fa
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF3_VENDOR_ID                                                                  0x0000
+#define cfgBIF_CFG_DEV0_EPF3_DEVICE_ID                                                                  0x0002
+#define cfgBIF_CFG_DEV0_EPF3_COMMAND                                                                    0x0004
+#define cfgBIF_CFG_DEV0_EPF3_STATUS                                                                     0x0006
+#define cfgBIF_CFG_DEV0_EPF3_REVISION_ID                                                                0x0008
+#define cfgBIF_CFG_DEV0_EPF3_PROG_INTERFACE                                                             0x0009
+#define cfgBIF_CFG_DEV0_EPF3_SUB_CLASS                                                                  0x000a
+#define cfgBIF_CFG_DEV0_EPF3_BASE_CLASS                                                                 0x000b
+#define cfgBIF_CFG_DEV0_EPF3_CACHE_LINE                                                                 0x000c
+#define cfgBIF_CFG_DEV0_EPF3_LATENCY                                                                    0x000d
+#define cfgBIF_CFG_DEV0_EPF3_HEADER                                                                     0x000e
+#define cfgBIF_CFG_DEV0_EPF3_BIST                                                                       0x000f
+#define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_1                                                                0x0010
+#define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_2                                                                0x0014
+#define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_3                                                                0x0018
+#define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_4                                                                0x001c
+#define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_5                                                                0x0020
+#define cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_6                                                                0x0024
+#define cfgBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR                                                            0x0028
+#define cfgBIF_CFG_DEV0_EPF3_ADAPTER_ID                                                                 0x002c
+#define cfgBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR                                                              0x0030
+#define cfgBIF_CFG_DEV0_EPF3_CAP_PTR                                                                    0x0034
+#define cfgBIF_CFG_DEV0_EPF3_INTERRUPT_LINE                                                             0x003c
+#define cfgBIF_CFG_DEV0_EPF3_INTERRUPT_PIN                                                              0x003d
+#define cfgBIF_CFG_DEV0_EPF3_MIN_GRANT                                                                  0x003e
+#define cfgBIF_CFG_DEV0_EPF3_MAX_LATENCY                                                                0x003f
+#define cfgBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST                                                            0x0048
+#define cfgBIF_CFG_DEV0_EPF3_ADAPTER_ID_W                                                               0x004c
+#define cfgBIF_CFG_DEV0_EPF3_PMI_CAP_LIST                                                               0x0050
+#define cfgBIF_CFG_DEV0_EPF3_PMI_CAP                                                                    0x0052
+#define cfgBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL                                                            0x0054
+#define cfgBIF_CFG_DEV0_EPF3_SBRN                                                                       0x0060
+#define cfgBIF_CFG_DEV0_EPF3_FLADJ                                                                      0x0061
+#define cfgBIF_CFG_DEV0_EPF3_DBESL_DBESLD                                                               0x0062
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST                                                              0x0064
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_CAP                                                                   0x0066
+#define cfgBIF_CFG_DEV0_EPF3_DEVICE_CAP                                                                 0x0068
+#define cfgBIF_CFG_DEV0_EPF3_DEVICE_CNTL                                                                0x006c
+#define cfgBIF_CFG_DEV0_EPF3_DEVICE_STATUS                                                              0x006e
+#define cfgBIF_CFG_DEV0_EPF3_LINK_CAP                                                                   0x0070
+#define cfgBIF_CFG_DEV0_EPF3_LINK_CNTL                                                                  0x0074
+#define cfgBIF_CFG_DEV0_EPF3_LINK_STATUS                                                                0x0076
+#define cfgBIF_CFG_DEV0_EPF3_DEVICE_CAP2                                                                0x0088
+#define cfgBIF_CFG_DEV0_EPF3_DEVICE_CNTL2                                                               0x008c
+#define cfgBIF_CFG_DEV0_EPF3_DEVICE_STATUS2                                                             0x008e
+#define cfgBIF_CFG_DEV0_EPF3_LINK_CAP2                                                                  0x0090
+#define cfgBIF_CFG_DEV0_EPF3_LINK_CNTL2                                                                 0x0094
+#define cfgBIF_CFG_DEV0_EPF3_LINK_STATUS2                                                               0x0096
+#define cfgBIF_CFG_DEV0_EPF3_MSI_CAP_LIST                                                               0x00a0
+#define cfgBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL                                                               0x00a2
+#define cfgBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO                                                            0x00a4
+#define cfgBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI                                                            0x00a8
+#define cfgBIF_CFG_DEV0_EPF3_MSI_MSG_DATA                                                               0x00a8
+#define cfgBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA                                                           0x00aa
+#define cfgBIF_CFG_DEV0_EPF3_MSI_MASK                                                                   0x00ac
+#define cfgBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64                                                            0x00ac
+#define cfgBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64                                                        0x00ae
+#define cfgBIF_CFG_DEV0_EPF3_MSI_MASK_64                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF3_MSI_PENDING                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF3_MSI_PENDING_64                                                             0x00b4
+#define cfgBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST                                                              0x00c0
+#define cfgBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL                                                              0x00c2
+#define cfgBIF_CFG_DEV0_EPF3_MSIX_TABLE                                                                 0x00c4
+#define cfgBIF_CFG_DEV0_EPF3_MSIX_PBA                                                                   0x00c8
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                          0x0100
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR                                                   0x0104
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1                                                      0x0108
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2                                                      0x010c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                              0x0150
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS                                                     0x0154
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK                                                       0x0158
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY                                                   0x015c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS                                                       0x0160
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK                                                         0x0164
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL                                                      0x0168
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0                                                              0x016c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1                                                              0x0170
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2                                                              0x0174
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3                                                              0x0178
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0                                                       0x0188
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1                                                       0x018c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2                                                       0x0190
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3                                                       0x0194
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST                                                      0x0200
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP                                                              0x0204
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL                                                             0x0208
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP                                                              0x020c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL                                                             0x0210
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP                                                              0x0214
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL                                                             0x0218
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP                                                              0x021c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL                                                             0x0220
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP                                                              0x0224
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL                                                             0x0228
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP                                                              0x022c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL                                                             0x0230
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST                                               0x0240
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT                                                0x0244
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA                                                       0x0248
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP                                                        0x024c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST                                                      0x0250
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP                                                               0x0254
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR                                                 0x0258
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS                                                            0x025c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL                                                              0x025e
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                              0x0260
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                              0x0261
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                              0x0262
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                              0x0263
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                              0x0264
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                              0x0265
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                              0x0266
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                              0x0267
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST                                                      0x02a0
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP                                                               0x02a4
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL                                                              0x02a6
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST                                                    0x02d0
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP                                                             0x02d4
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL                                                            0x02d6
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST                                                      0x0328
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP                                                               0x032c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL                                                              0x032e
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST                                                 0x0370
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP                                                          0x0374
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL                                                         0x0378
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0                                                        0x037c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1                                                        0x037e
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2                                                        0x0380
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3                                                        0x0382
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4                                                        0x0384
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5                                                        0x0386
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6                                                        0x0388
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7                                                        0x038a
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8                                                        0x038c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9                                                        0x038e
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10                                                       0x0390
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11                                                       0x0392
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12                                                       0x0394
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13                                                       0x0396
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14                                                       0x0398
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15                                                       0x039a
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16                                                       0x039c
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17                                                       0x039e
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18                                                       0x03a0
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19                                                       0x03a2
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20                                                       0x03a4
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21                                                       0x03a6
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22                                                       0x03a8
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23                                                       0x03aa
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24                                                       0x03ac
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25                                                       0x03ae
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26                                                       0x03b0
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27                                                       0x03b2
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28                                                       0x03b4
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29                                                       0x03b6
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30                                                       0x03b8
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31                                                       0x03ba
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32                                                       0x03bc
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33                                                       0x03be
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34                                                       0x03c0
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35                                                       0x03c2
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36                                                       0x03c4
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37                                                       0x03c6
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38                                                       0x03c8
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39                                                       0x03ca
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40                                                       0x03cc
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41                                                       0x03ce
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42                                                       0x03d0
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43                                                       0x03d2
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44                                                       0x03d4
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45                                                       0x03d6
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46                                                       0x03d8
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47                                                       0x03da
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48                                                       0x03dc
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49                                                       0x03de
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50                                                       0x03e0
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51                                                       0x03e2
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52                                                       0x03e4
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53                                                       0x03e6
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54                                                       0x03e8
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55                                                       0x03ea
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56                                                       0x03ec
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57                                                       0x03ee
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58                                                       0x03f0
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59                                                       0x03f2
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60                                                       0x03f4
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61                                                       0x03f6
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62                                                       0x03f8
+#define cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63                                                       0x03fa
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF4_VENDOR_ID                                                                  0x0000
+#define cfgBIF_CFG_DEV0_EPF4_DEVICE_ID                                                                  0x0002
+#define cfgBIF_CFG_DEV0_EPF4_COMMAND                                                                    0x0004
+#define cfgBIF_CFG_DEV0_EPF4_STATUS                                                                     0x0006
+#define cfgBIF_CFG_DEV0_EPF4_REVISION_ID                                                                0x0008
+#define cfgBIF_CFG_DEV0_EPF4_PROG_INTERFACE                                                             0x0009
+#define cfgBIF_CFG_DEV0_EPF4_SUB_CLASS                                                                  0x000a
+#define cfgBIF_CFG_DEV0_EPF4_BASE_CLASS                                                                 0x000b
+#define cfgBIF_CFG_DEV0_EPF4_CACHE_LINE                                                                 0x000c
+#define cfgBIF_CFG_DEV0_EPF4_LATENCY                                                                    0x000d
+#define cfgBIF_CFG_DEV0_EPF4_HEADER                                                                     0x000e
+#define cfgBIF_CFG_DEV0_EPF4_BIST                                                                       0x000f
+#define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_1                                                                0x0010
+#define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_2                                                                0x0014
+#define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_3                                                                0x0018
+#define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_4                                                                0x001c
+#define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_5                                                                0x0020
+#define cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_6                                                                0x0024
+#define cfgBIF_CFG_DEV0_EPF4_CARDBUS_CIS_PTR                                                            0x0028
+#define cfgBIF_CFG_DEV0_EPF4_ADAPTER_ID                                                                 0x002c
+#define cfgBIF_CFG_DEV0_EPF4_ROM_BASE_ADDR                                                              0x0030
+#define cfgBIF_CFG_DEV0_EPF4_CAP_PTR                                                                    0x0034
+#define cfgBIF_CFG_DEV0_EPF4_INTERRUPT_LINE                                                             0x003c
+#define cfgBIF_CFG_DEV0_EPF4_INTERRUPT_PIN                                                              0x003d
+#define cfgBIF_CFG_DEV0_EPF4_MIN_GRANT                                                                  0x003e
+#define cfgBIF_CFG_DEV0_EPF4_MAX_LATENCY                                                                0x003f
+#define cfgBIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST                                                            0x0048
+#define cfgBIF_CFG_DEV0_EPF4_ADAPTER_ID_W                                                               0x004c
+#define cfgBIF_CFG_DEV0_EPF4_PMI_CAP_LIST                                                               0x0050
+#define cfgBIF_CFG_DEV0_EPF4_PMI_CAP                                                                    0x0052
+#define cfgBIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL                                                            0x0054
+#define cfgBIF_CFG_DEV0_EPF4_SBRN                                                                       0x0060
+#define cfgBIF_CFG_DEV0_EPF4_FLADJ                                                                      0x0061
+#define cfgBIF_CFG_DEV0_EPF4_DBESL_DBESLD                                                               0x0062
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_CAP_LIST                                                              0x0064
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_CAP                                                                   0x0066
+#define cfgBIF_CFG_DEV0_EPF4_DEVICE_CAP                                                                 0x0068
+#define cfgBIF_CFG_DEV0_EPF4_DEVICE_CNTL                                                                0x006c
+#define cfgBIF_CFG_DEV0_EPF4_DEVICE_STATUS                                                              0x006e
+#define cfgBIF_CFG_DEV0_EPF4_LINK_CAP                                                                   0x0070
+#define cfgBIF_CFG_DEV0_EPF4_LINK_CNTL                                                                  0x0074
+#define cfgBIF_CFG_DEV0_EPF4_LINK_STATUS                                                                0x0076
+#define cfgBIF_CFG_DEV0_EPF4_DEVICE_CAP2                                                                0x0088
+#define cfgBIF_CFG_DEV0_EPF4_DEVICE_CNTL2                                                               0x008c
+#define cfgBIF_CFG_DEV0_EPF4_DEVICE_STATUS2                                                             0x008e
+#define cfgBIF_CFG_DEV0_EPF4_LINK_CAP2                                                                  0x0090
+#define cfgBIF_CFG_DEV0_EPF4_LINK_CNTL2                                                                 0x0094
+#define cfgBIF_CFG_DEV0_EPF4_LINK_STATUS2                                                               0x0096
+#define cfgBIF_CFG_DEV0_EPF4_MSI_CAP_LIST                                                               0x00a0
+#define cfgBIF_CFG_DEV0_EPF4_MSI_MSG_CNTL                                                               0x00a2
+#define cfgBIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO                                                            0x00a4
+#define cfgBIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI                                                            0x00a8
+#define cfgBIF_CFG_DEV0_EPF4_MSI_MSG_DATA                                                               0x00a8
+#define cfgBIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA                                                           0x00aa
+#define cfgBIF_CFG_DEV0_EPF4_MSI_MASK                                                                   0x00ac
+#define cfgBIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64                                                            0x00ac
+#define cfgBIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64                                                        0x00ae
+#define cfgBIF_CFG_DEV0_EPF4_MSI_MASK_64                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF4_MSI_PENDING                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF4_MSI_PENDING_64                                                             0x00b4
+#define cfgBIF_CFG_DEV0_EPF4_MSIX_CAP_LIST                                                              0x00c0
+#define cfgBIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL                                                              0x00c2
+#define cfgBIF_CFG_DEV0_EPF4_MSIX_TABLE                                                                 0x00c4
+#define cfgBIF_CFG_DEV0_EPF4_MSIX_PBA                                                                   0x00c8
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                          0x0100
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR                                                   0x0104
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1                                                      0x0108
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2                                                      0x010c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                              0x0150
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS                                                     0x0154
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK                                                       0x0158
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY                                                   0x015c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS                                                       0x0160
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK                                                         0x0164
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL                                                      0x0168
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0                                                              0x016c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1                                                              0x0170
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2                                                              0x0174
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3                                                              0x0178
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0                                                       0x0188
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1                                                       0x018c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2                                                       0x0190
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3                                                       0x0194
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST                                                      0x0200
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP                                                              0x0204
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL                                                             0x0208
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP                                                              0x020c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL                                                             0x0210
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP                                                              0x0214
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL                                                             0x0218
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP                                                              0x021c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL                                                             0x0220
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP                                                              0x0224
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL                                                             0x0228
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP                                                              0x022c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL                                                             0x0230
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST                                               0x0240
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT                                                0x0244
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA                                                       0x0248
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP                                                        0x024c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST                                                      0x0250
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_CAP                                                               0x0254
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR                                                 0x0258
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS                                                            0x025c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL                                                              0x025e
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                              0x0260
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                              0x0261
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                              0x0262
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                              0x0263
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                              0x0264
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                              0x0265
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                              0x0266
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                              0x0267
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST                                                      0x02a0
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_ACS_CAP                                                               0x02a4
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL                                                              0x02a6
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST                                                    0x02d0
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_PASID_CAP                                                             0x02d4
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL                                                            0x02d6
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST                                                      0x0328
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_ARI_CAP                                                               0x032c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL                                                              0x032e
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST                                                 0x0370
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP                                                          0x0374
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL                                                         0x0378
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0                                                        0x037c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1                                                        0x037e
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2                                                        0x0380
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3                                                        0x0382
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4                                                        0x0384
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5                                                        0x0386
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6                                                        0x0388
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7                                                        0x038a
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8                                                        0x038c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9                                                        0x038e
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10                                                       0x0390
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11                                                       0x0392
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12                                                       0x0394
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13                                                       0x0396
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14                                                       0x0398
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15                                                       0x039a
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16                                                       0x039c
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17                                                       0x039e
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18                                                       0x03a0
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19                                                       0x03a2
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20                                                       0x03a4
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21                                                       0x03a6
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22                                                       0x03a8
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23                                                       0x03aa
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24                                                       0x03ac
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25                                                       0x03ae
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26                                                       0x03b0
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27                                                       0x03b2
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28                                                       0x03b4
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29                                                       0x03b6
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30                                                       0x03b8
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31                                                       0x03ba
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32                                                       0x03bc
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33                                                       0x03be
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34                                                       0x03c0
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35                                                       0x03c2
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36                                                       0x03c4
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37                                                       0x03c6
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38                                                       0x03c8
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39                                                       0x03ca
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40                                                       0x03cc
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41                                                       0x03ce
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42                                                       0x03d0
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43                                                       0x03d2
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44                                                       0x03d4
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45                                                       0x03d6
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46                                                       0x03d8
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47                                                       0x03da
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48                                                       0x03dc
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49                                                       0x03de
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50                                                       0x03e0
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51                                                       0x03e2
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52                                                       0x03e4
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53                                                       0x03e6
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54                                                       0x03e8
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55                                                       0x03ea
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56                                                       0x03ec
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57                                                       0x03ee
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58                                                       0x03f0
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59                                                       0x03f2
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60                                                       0x03f4
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61                                                       0x03f6
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62                                                       0x03f8
+#define cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63                                                       0x03fa
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF5_VENDOR_ID                                                                  0x0000
+#define cfgBIF_CFG_DEV0_EPF5_DEVICE_ID                                                                  0x0002
+#define cfgBIF_CFG_DEV0_EPF5_COMMAND                                                                    0x0004
+#define cfgBIF_CFG_DEV0_EPF5_STATUS                                                                     0x0006
+#define cfgBIF_CFG_DEV0_EPF5_REVISION_ID                                                                0x0008
+#define cfgBIF_CFG_DEV0_EPF5_PROG_INTERFACE                                                             0x0009
+#define cfgBIF_CFG_DEV0_EPF5_SUB_CLASS                                                                  0x000a
+#define cfgBIF_CFG_DEV0_EPF5_BASE_CLASS                                                                 0x000b
+#define cfgBIF_CFG_DEV0_EPF5_CACHE_LINE                                                                 0x000c
+#define cfgBIF_CFG_DEV0_EPF5_LATENCY                                                                    0x000d
+#define cfgBIF_CFG_DEV0_EPF5_HEADER                                                                     0x000e
+#define cfgBIF_CFG_DEV0_EPF5_BIST                                                                       0x000f
+#define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_1                                                                0x0010
+#define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_2                                                                0x0014
+#define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_3                                                                0x0018
+#define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_4                                                                0x001c
+#define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_5                                                                0x0020
+#define cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_6                                                                0x0024
+#define cfgBIF_CFG_DEV0_EPF5_CARDBUS_CIS_PTR                                                            0x0028
+#define cfgBIF_CFG_DEV0_EPF5_ADAPTER_ID                                                                 0x002c
+#define cfgBIF_CFG_DEV0_EPF5_ROM_BASE_ADDR                                                              0x0030
+#define cfgBIF_CFG_DEV0_EPF5_CAP_PTR                                                                    0x0034
+#define cfgBIF_CFG_DEV0_EPF5_INTERRUPT_LINE                                                             0x003c
+#define cfgBIF_CFG_DEV0_EPF5_INTERRUPT_PIN                                                              0x003d
+#define cfgBIF_CFG_DEV0_EPF5_MIN_GRANT                                                                  0x003e
+#define cfgBIF_CFG_DEV0_EPF5_MAX_LATENCY                                                                0x003f
+#define cfgBIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST                                                            0x0048
+#define cfgBIF_CFG_DEV0_EPF5_ADAPTER_ID_W                                                               0x004c
+#define cfgBIF_CFG_DEV0_EPF5_PMI_CAP_LIST                                                               0x0050
+#define cfgBIF_CFG_DEV0_EPF5_PMI_CAP                                                                    0x0052
+#define cfgBIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL                                                            0x0054
+#define cfgBIF_CFG_DEV0_EPF5_SBRN                                                                       0x0060
+#define cfgBIF_CFG_DEV0_EPF5_FLADJ                                                                      0x0061
+#define cfgBIF_CFG_DEV0_EPF5_DBESL_DBESLD                                                               0x0062
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_CAP_LIST                                                              0x0064
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_CAP                                                                   0x0066
+#define cfgBIF_CFG_DEV0_EPF5_DEVICE_CAP                                                                 0x0068
+#define cfgBIF_CFG_DEV0_EPF5_DEVICE_CNTL                                                                0x006c
+#define cfgBIF_CFG_DEV0_EPF5_DEVICE_STATUS                                                              0x006e
+#define cfgBIF_CFG_DEV0_EPF5_LINK_CAP                                                                   0x0070
+#define cfgBIF_CFG_DEV0_EPF5_LINK_CNTL                                                                  0x0074
+#define cfgBIF_CFG_DEV0_EPF5_LINK_STATUS                                                                0x0076
+#define cfgBIF_CFG_DEV0_EPF5_DEVICE_CAP2                                                                0x0088
+#define cfgBIF_CFG_DEV0_EPF5_DEVICE_CNTL2                                                               0x008c
+#define cfgBIF_CFG_DEV0_EPF5_DEVICE_STATUS2                                                             0x008e
+#define cfgBIF_CFG_DEV0_EPF5_LINK_CAP2                                                                  0x0090
+#define cfgBIF_CFG_DEV0_EPF5_LINK_CNTL2                                                                 0x0094
+#define cfgBIF_CFG_DEV0_EPF5_LINK_STATUS2                                                               0x0096
+#define cfgBIF_CFG_DEV0_EPF5_MSI_CAP_LIST                                                               0x00a0
+#define cfgBIF_CFG_DEV0_EPF5_MSI_MSG_CNTL                                                               0x00a2
+#define cfgBIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO                                                            0x00a4
+#define cfgBIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI                                                            0x00a8
+#define cfgBIF_CFG_DEV0_EPF5_MSI_MSG_DATA                                                               0x00a8
+#define cfgBIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA                                                           0x00aa
+#define cfgBIF_CFG_DEV0_EPF5_MSI_MASK                                                                   0x00ac
+#define cfgBIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64                                                            0x00ac
+#define cfgBIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64                                                        0x00ae
+#define cfgBIF_CFG_DEV0_EPF5_MSI_MASK_64                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF5_MSI_PENDING                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF5_MSI_PENDING_64                                                             0x00b4
+#define cfgBIF_CFG_DEV0_EPF5_MSIX_CAP_LIST                                                              0x00c0
+#define cfgBIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL                                                              0x00c2
+#define cfgBIF_CFG_DEV0_EPF5_MSIX_TABLE                                                                 0x00c4
+#define cfgBIF_CFG_DEV0_EPF5_MSIX_PBA                                                                   0x00c8
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                          0x0100
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR                                                   0x0104
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1                                                      0x0108
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2                                                      0x010c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                              0x0150
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS                                                     0x0154
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK                                                       0x0158
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY                                                   0x015c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS                                                       0x0160
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK                                                         0x0164
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL                                                      0x0168
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0                                                              0x016c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1                                                              0x0170
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2                                                              0x0174
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3                                                              0x0178
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0                                                       0x0188
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1                                                       0x018c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2                                                       0x0190
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3                                                       0x0194
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST                                                      0x0200
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP                                                              0x0204
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL                                                             0x0208
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP                                                              0x020c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL                                                             0x0210
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP                                                              0x0214
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL                                                             0x0218
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP                                                              0x021c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL                                                             0x0220
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP                                                              0x0224
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL                                                             0x0228
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP                                                              0x022c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL                                                             0x0230
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST                                               0x0240
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT                                                0x0244
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA                                                       0x0248
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP                                                        0x024c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST                                                      0x0250
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_CAP                                                               0x0254
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR                                                 0x0258
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS                                                            0x025c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL                                                              0x025e
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                              0x0260
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                              0x0261
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                              0x0262
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                              0x0263
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                              0x0264
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                              0x0265
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                              0x0266
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                              0x0267
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST                                                      0x02a0
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_ACS_CAP                                                               0x02a4
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL                                                              0x02a6
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST                                                    0x02d0
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_PASID_CAP                                                             0x02d4
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL                                                            0x02d6
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST                                                      0x0328
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_ARI_CAP                                                               0x032c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL                                                              0x032e
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST                                                 0x0370
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP                                                          0x0374
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL                                                         0x0378
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0                                                        0x037c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1                                                        0x037e
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2                                                        0x0380
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3                                                        0x0382
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4                                                        0x0384
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5                                                        0x0386
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6                                                        0x0388
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7                                                        0x038a
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8                                                        0x038c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9                                                        0x038e
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10                                                       0x0390
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11                                                       0x0392
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12                                                       0x0394
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13                                                       0x0396
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14                                                       0x0398
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15                                                       0x039a
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16                                                       0x039c
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17                                                       0x039e
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18                                                       0x03a0
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19                                                       0x03a2
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20                                                       0x03a4
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21                                                       0x03a6
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22                                                       0x03a8
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23                                                       0x03aa
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24                                                       0x03ac
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25                                                       0x03ae
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26                                                       0x03b0
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27                                                       0x03b2
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28                                                       0x03b4
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29                                                       0x03b6
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30                                                       0x03b8
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31                                                       0x03ba
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32                                                       0x03bc
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33                                                       0x03be
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34                                                       0x03c0
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35                                                       0x03c2
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36                                                       0x03c4
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37                                                       0x03c6
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38                                                       0x03c8
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39                                                       0x03ca
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40                                                       0x03cc
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41                                                       0x03ce
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42                                                       0x03d0
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43                                                       0x03d2
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44                                                       0x03d4
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45                                                       0x03d6
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46                                                       0x03d8
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47                                                       0x03da
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48                                                       0x03dc
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49                                                       0x03de
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50                                                       0x03e0
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51                                                       0x03e2
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52                                                       0x03e4
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53                                                       0x03e6
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54                                                       0x03e8
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55                                                       0x03ea
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56                                                       0x03ec
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57                                                       0x03ee
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58                                                       0x03f0
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59                                                       0x03f2
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60                                                       0x03f4
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61                                                       0x03f6
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62                                                       0x03f8
+#define cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63                                                       0x03fa
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF6_VENDOR_ID                                                                  0x0000
+#define cfgBIF_CFG_DEV0_EPF6_DEVICE_ID                                                                  0x0002
+#define cfgBIF_CFG_DEV0_EPF6_COMMAND                                                                    0x0004
+#define cfgBIF_CFG_DEV0_EPF6_STATUS                                                                     0x0006
+#define cfgBIF_CFG_DEV0_EPF6_REVISION_ID                                                                0x0008
+#define cfgBIF_CFG_DEV0_EPF6_PROG_INTERFACE                                                             0x0009
+#define cfgBIF_CFG_DEV0_EPF6_SUB_CLASS                                                                  0x000a
+#define cfgBIF_CFG_DEV0_EPF6_BASE_CLASS                                                                 0x000b
+#define cfgBIF_CFG_DEV0_EPF6_CACHE_LINE                                                                 0x000c
+#define cfgBIF_CFG_DEV0_EPF6_LATENCY                                                                    0x000d
+#define cfgBIF_CFG_DEV0_EPF6_HEADER                                                                     0x000e
+#define cfgBIF_CFG_DEV0_EPF6_BIST                                                                       0x000f
+#define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_1                                                                0x0010
+#define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_2                                                                0x0014
+#define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_3                                                                0x0018
+#define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_4                                                                0x001c
+#define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_5                                                                0x0020
+#define cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_6                                                                0x0024
+#define cfgBIF_CFG_DEV0_EPF6_CARDBUS_CIS_PTR                                                            0x0028
+#define cfgBIF_CFG_DEV0_EPF6_ADAPTER_ID                                                                 0x002c
+#define cfgBIF_CFG_DEV0_EPF6_ROM_BASE_ADDR                                                              0x0030
+#define cfgBIF_CFG_DEV0_EPF6_CAP_PTR                                                                    0x0034
+#define cfgBIF_CFG_DEV0_EPF6_INTERRUPT_LINE                                                             0x003c
+#define cfgBIF_CFG_DEV0_EPF6_INTERRUPT_PIN                                                              0x003d
+#define cfgBIF_CFG_DEV0_EPF6_MIN_GRANT                                                                  0x003e
+#define cfgBIF_CFG_DEV0_EPF6_MAX_LATENCY                                                                0x003f
+#define cfgBIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST                                                            0x0048
+#define cfgBIF_CFG_DEV0_EPF6_ADAPTER_ID_W                                                               0x004c
+#define cfgBIF_CFG_DEV0_EPF6_PMI_CAP_LIST                                                               0x0050
+#define cfgBIF_CFG_DEV0_EPF6_PMI_CAP                                                                    0x0052
+#define cfgBIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL                                                            0x0054
+#define cfgBIF_CFG_DEV0_EPF6_SBRN                                                                       0x0060
+#define cfgBIF_CFG_DEV0_EPF6_FLADJ                                                                      0x0061
+#define cfgBIF_CFG_DEV0_EPF6_DBESL_DBESLD                                                               0x0062
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_CAP_LIST                                                              0x0064
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_CAP                                                                   0x0066
+#define cfgBIF_CFG_DEV0_EPF6_DEVICE_CAP                                                                 0x0068
+#define cfgBIF_CFG_DEV0_EPF6_DEVICE_CNTL                                                                0x006c
+#define cfgBIF_CFG_DEV0_EPF6_DEVICE_STATUS                                                              0x006e
+#define cfgBIF_CFG_DEV0_EPF6_LINK_CAP                                                                   0x0070
+#define cfgBIF_CFG_DEV0_EPF6_LINK_CNTL                                                                  0x0074
+#define cfgBIF_CFG_DEV0_EPF6_LINK_STATUS                                                                0x0076
+#define cfgBIF_CFG_DEV0_EPF6_DEVICE_CAP2                                                                0x0088
+#define cfgBIF_CFG_DEV0_EPF6_DEVICE_CNTL2                                                               0x008c
+#define cfgBIF_CFG_DEV0_EPF6_DEVICE_STATUS2                                                             0x008e
+#define cfgBIF_CFG_DEV0_EPF6_LINK_CAP2                                                                  0x0090
+#define cfgBIF_CFG_DEV0_EPF6_LINK_CNTL2                                                                 0x0094
+#define cfgBIF_CFG_DEV0_EPF6_LINK_STATUS2                                                               0x0096
+#define cfgBIF_CFG_DEV0_EPF6_MSI_CAP_LIST                                                               0x00a0
+#define cfgBIF_CFG_DEV0_EPF6_MSI_MSG_CNTL                                                               0x00a2
+#define cfgBIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO                                                            0x00a4
+#define cfgBIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI                                                            0x00a8
+#define cfgBIF_CFG_DEV0_EPF6_MSI_MSG_DATA                                                               0x00a8
+#define cfgBIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA                                                           0x00aa
+#define cfgBIF_CFG_DEV0_EPF6_MSI_MASK                                                                   0x00ac
+#define cfgBIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64                                                            0x00ac
+#define cfgBIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64                                                        0x00ae
+#define cfgBIF_CFG_DEV0_EPF6_MSI_MASK_64                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF6_MSI_PENDING                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF6_MSI_PENDING_64                                                             0x00b4
+#define cfgBIF_CFG_DEV0_EPF6_MSIX_CAP_LIST                                                              0x00c0
+#define cfgBIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL                                                              0x00c2
+#define cfgBIF_CFG_DEV0_EPF6_MSIX_TABLE                                                                 0x00c4
+#define cfgBIF_CFG_DEV0_EPF6_MSIX_PBA                                                                   0x00c8
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                          0x0100
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR                                                   0x0104
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1                                                      0x0108
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2                                                      0x010c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                              0x0150
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS                                                     0x0154
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK                                                       0x0158
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY                                                   0x015c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS                                                       0x0160
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK                                                         0x0164
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL                                                      0x0168
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0                                                              0x016c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1                                                              0x0170
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2                                                              0x0174
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3                                                              0x0178
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0                                                       0x0188
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1                                                       0x018c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2                                                       0x0190
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3                                                       0x0194
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST                                                      0x0200
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP                                                              0x0204
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL                                                             0x0208
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP                                                              0x020c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL                                                             0x0210
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP                                                              0x0214
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL                                                             0x0218
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP                                                              0x021c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL                                                             0x0220
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP                                                              0x0224
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL                                                             0x0228
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP                                                              0x022c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL                                                             0x0230
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST                                               0x0240
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT                                                0x0244
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA                                                       0x0248
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP                                                        0x024c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST                                                      0x0250
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_CAP                                                               0x0254
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR                                                 0x0258
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS                                                            0x025c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL                                                              0x025e
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                              0x0260
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                              0x0261
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                              0x0262
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                              0x0263
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                              0x0264
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                              0x0265
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                              0x0266
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                              0x0267
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST                                                      0x02a0
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_ACS_CAP                                                               0x02a4
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL                                                              0x02a6
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST                                                    0x02d0
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_PASID_CAP                                                             0x02d4
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL                                                            0x02d6
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST                                                      0x0328
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_ARI_CAP                                                               0x032c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL                                                              0x032e
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST                                                 0x0370
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP                                                          0x0374
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL                                                         0x0378
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0                                                        0x037c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1                                                        0x037e
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2                                                        0x0380
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3                                                        0x0382
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4                                                        0x0384
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5                                                        0x0386
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6                                                        0x0388
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7                                                        0x038a
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8                                                        0x038c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9                                                        0x038e
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10                                                       0x0390
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11                                                       0x0392
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12                                                       0x0394
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13                                                       0x0396
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14                                                       0x0398
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15                                                       0x039a
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16                                                       0x039c
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17                                                       0x039e
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18                                                       0x03a0
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19                                                       0x03a2
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20                                                       0x03a4
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21                                                       0x03a6
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22                                                       0x03a8
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23                                                       0x03aa
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24                                                       0x03ac
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25                                                       0x03ae
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26                                                       0x03b0
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27                                                       0x03b2
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28                                                       0x03b4
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29                                                       0x03b6
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30                                                       0x03b8
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31                                                       0x03ba
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32                                                       0x03bc
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33                                                       0x03be
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34                                                       0x03c0
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35                                                       0x03c2
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36                                                       0x03c4
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37                                                       0x03c6
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38                                                       0x03c8
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39                                                       0x03ca
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40                                                       0x03cc
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41                                                       0x03ce
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42                                                       0x03d0
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43                                                       0x03d2
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44                                                       0x03d4
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45                                                       0x03d6
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46                                                       0x03d8
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47                                                       0x03da
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48                                                       0x03dc
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49                                                       0x03de
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50                                                       0x03e0
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51                                                       0x03e2
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52                                                       0x03e4
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53                                                       0x03e6
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54                                                       0x03e8
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55                                                       0x03ea
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56                                                       0x03ec
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57                                                       0x03ee
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58                                                       0x03f0
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59                                                       0x03f2
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60                                                       0x03f4
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61                                                       0x03f6
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62                                                       0x03f8
+#define cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63                                                       0x03fa
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+// base address: 0x0
+#define cfgBIFPLR0_VENDOR_ID                                                                            0x0000
+#define cfgBIFPLR0_DEVICE_ID                                                                            0x0002
+#define cfgBIFPLR0_COMMAND                                                                              0x0004
+#define cfgBIFPLR0_STATUS                                                                               0x0006
+#define cfgBIFPLR0_REVISION_ID                                                                          0x0008
+#define cfgBIFPLR0_PROG_INTERFACE                                                                       0x0009
+#define cfgBIFPLR0_SUB_CLASS                                                                            0x000a
+#define cfgBIFPLR0_BASE_CLASS                                                                           0x000b
+#define cfgBIFPLR0_CACHE_LINE                                                                           0x000c
+#define cfgBIFPLR0_LATENCY                                                                              0x000d
+#define cfgBIFPLR0_HEADER                                                                               0x000e
+#define cfgBIFPLR0_BIST                                                                                 0x000f
+#define cfgBIFPLR0_SUB_BUS_NUMBER_LATENCY                                                               0x0018
+#define cfgBIFPLR0_IO_BASE_LIMIT                                                                        0x001c
+#define cfgBIFPLR0_SECONDARY_STATUS                                                                     0x001e
+#define cfgBIFPLR0_MEM_BASE_LIMIT                                                                       0x0020
+#define cfgBIFPLR0_PREF_BASE_LIMIT                                                                      0x0024
+#define cfgBIFPLR0_PREF_BASE_UPPER                                                                      0x0028
+#define cfgBIFPLR0_PREF_LIMIT_UPPER                                                                     0x002c
+#define cfgBIFPLR0_IO_BASE_LIMIT_HI                                                                     0x0030
+#define cfgBIFPLR0_CAP_PTR                                                                              0x0034
+#define cfgBIFPLR0_ROM_BASE_ADDR                                                                        0x0038
+#define cfgBIFPLR0_INTERRUPT_LINE                                                                       0x003c
+#define cfgBIFPLR0_INTERRUPT_PIN                                                                        0x003d
+#define cfgBIFPLR0_IRQ_BRIDGE_CNTL                                                                      0x003e
+#define cfgBIFPLR0_EXT_BRIDGE_CNTL                                                                      0x0040
+#define cfgBIFPLR0_VENDOR_CAP_LIST                                                                      0x0048
+#define cfgBIFPLR0_ADAPTER_ID_W                                                                         0x004c
+#define cfgBIFPLR0_PMI_CAP_LIST                                                                         0x0050
+#define cfgBIFPLR0_PMI_CAP                                                                              0x0052
+#define cfgBIFPLR0_PMI_STATUS_CNTL                                                                      0x0054
+#define cfgBIFPLR0_PCIE_CAP_LIST                                                                        0x0058
+#define cfgBIFPLR0_PCIE_CAP                                                                             0x005a
+#define cfgBIFPLR0_DEVICE_CAP                                                                           0x005c
+#define cfgBIFPLR0_DEVICE_CNTL                                                                          0x0060
+#define cfgBIFPLR0_DEVICE_STATUS                                                                        0x0062
+#define cfgBIFPLR0_LINK_CAP                                                                             0x0064
+#define cfgBIFPLR0_LINK_CNTL                                                                            0x0068
+#define cfgBIFPLR0_LINK_STATUS                                                                          0x006a
+#define cfgBIFPLR0_SLOT_CAP                                                                             0x006c
+#define cfgBIFPLR0_SLOT_CNTL                                                                            0x0070
+#define cfgBIFPLR0_SLOT_STATUS                                                                          0x0072
+#define cfgBIFPLR0_ROOT_CNTL                                                                            0x0074
+#define cfgBIFPLR0_ROOT_CAP                                                                             0x0076
+#define cfgBIFPLR0_ROOT_STATUS                                                                          0x0078
+#define cfgBIFPLR0_DEVICE_CAP2                                                                          0x007c
+#define cfgBIFPLR0_DEVICE_CNTL2                                                                         0x0080
+#define cfgBIFPLR0_DEVICE_STATUS2                                                                       0x0082
+#define cfgBIFPLR0_LINK_CAP2                                                                            0x0084
+#define cfgBIFPLR0_LINK_CNTL2                                                                           0x0088
+#define cfgBIFPLR0_LINK_STATUS2                                                                         0x008a
+#define cfgBIFPLR0_SLOT_CAP2                                                                            0x008c
+#define cfgBIFPLR0_SLOT_CNTL2                                                                           0x0090
+#define cfgBIFPLR0_SLOT_STATUS2                                                                         0x0092
+#define cfgBIFPLR0_MSI_CAP_LIST                                                                         0x00a0
+#define cfgBIFPLR0_MSI_MSG_CNTL                                                                         0x00a2
+#define cfgBIFPLR0_MSI_MSG_ADDR_LO                                                                      0x00a4
+#define cfgBIFPLR0_MSI_MSG_ADDR_HI                                                                      0x00a8
+#define cfgBIFPLR0_MSI_MSG_DATA                                                                         0x00a8
+#define cfgBIFPLR0_MSI_MSG_DATA_64                                                                      0x00ac
+#define cfgBIFPLR0_SSID_CAP_LIST                                                                        0x00c0
+#define cfgBIFPLR0_SSID_CAP                                                                             0x00c4
+#define cfgBIFPLR0_MSI_MAP_CAP_LIST                                                                     0x00c8
+#define cfgBIFPLR0_MSI_MAP_CAP                                                                          0x00ca
+#define cfgBIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                    0x0100
+#define cfgBIFPLR0_PCIE_VENDOR_SPECIFIC_HDR                                                             0x0104
+#define cfgBIFPLR0_PCIE_VENDOR_SPECIFIC1                                                                0x0108
+#define cfgBIFPLR0_PCIE_VENDOR_SPECIFIC2                                                                0x010c
+#define cfgBIFPLR0_PCIE_VC_ENH_CAP_LIST                                                                 0x0110
+#define cfgBIFPLR0_PCIE_PORT_VC_CAP_REG1                                                                0x0114
+#define cfgBIFPLR0_PCIE_PORT_VC_CAP_REG2                                                                0x0118
+#define cfgBIFPLR0_PCIE_PORT_VC_CNTL                                                                    0x011c
+#define cfgBIFPLR0_PCIE_PORT_VC_STATUS                                                                  0x011e
+#define cfgBIFPLR0_PCIE_VC0_RESOURCE_CAP                                                                0x0120
+#define cfgBIFPLR0_PCIE_VC0_RESOURCE_CNTL                                                               0x0124
+#define cfgBIFPLR0_PCIE_VC0_RESOURCE_STATUS                                                             0x012a
+#define cfgBIFPLR0_PCIE_VC1_RESOURCE_CAP                                                                0x012c
+#define cfgBIFPLR0_PCIE_VC1_RESOURCE_CNTL                                                               0x0130
+#define cfgBIFPLR0_PCIE_VC1_RESOURCE_STATUS                                                             0x0136
+#define cfgBIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                     0x0140
+#define cfgBIFPLR0_PCIE_DEV_SERIAL_NUM_DW1                                                              0x0144
+#define cfgBIFPLR0_PCIE_DEV_SERIAL_NUM_DW2                                                              0x0148
+#define cfgBIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                        0x0150
+#define cfgBIFPLR0_PCIE_UNCORR_ERR_STATUS                                                               0x0154
+#define cfgBIFPLR0_PCIE_UNCORR_ERR_MASK                                                                 0x0158
+#define cfgBIFPLR0_PCIE_UNCORR_ERR_SEVERITY                                                             0x015c
+#define cfgBIFPLR0_PCIE_CORR_ERR_STATUS                                                                 0x0160
+#define cfgBIFPLR0_PCIE_CORR_ERR_MASK                                                                   0x0164
+#define cfgBIFPLR0_PCIE_ADV_ERR_CAP_CNTL                                                                0x0168
+#define cfgBIFPLR0_PCIE_HDR_LOG0                                                                        0x016c
+#define cfgBIFPLR0_PCIE_HDR_LOG1                                                                        0x0170
+#define cfgBIFPLR0_PCIE_HDR_LOG2                                                                        0x0174
+#define cfgBIFPLR0_PCIE_HDR_LOG3                                                                        0x0178
+#define cfgBIFPLR0_PCIE_ROOT_ERR_CMD                                                                    0x017c
+#define cfgBIFPLR0_PCIE_ROOT_ERR_STATUS                                                                 0x0180
+#define cfgBIFPLR0_PCIE_ERR_SRC_ID                                                                      0x0184
+#define cfgBIFPLR0_PCIE_TLP_PREFIX_LOG0                                                                 0x0188
+#define cfgBIFPLR0_PCIE_TLP_PREFIX_LOG1                                                                 0x018c
+#define cfgBIFPLR0_PCIE_TLP_PREFIX_LOG2                                                                 0x0190
+#define cfgBIFPLR0_PCIE_TLP_PREFIX_LOG3                                                                 0x0194
+#define cfgBIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST                                                          0x0270
+#define cfgBIFPLR0_PCIE_LINK_CNTL3                                                                      0x0274
+#define cfgBIFPLR0_PCIE_LANE_ERROR_STATUS                                                               0x0278
+#define cfgBIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL                                                        0x027c
+#define cfgBIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL                                                        0x027e
+#define cfgBIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL                                                        0x0280
+#define cfgBIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL                                                        0x0282
+#define cfgBIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL                                                        0x0284
+#define cfgBIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL                                                        0x0286
+#define cfgBIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL                                                        0x0288
+#define cfgBIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL                                                        0x028a
+#define cfgBIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL                                                        0x028c
+#define cfgBIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL                                                        0x028e
+#define cfgBIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL                                                       0x0290
+#define cfgBIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL                                                       0x0292
+#define cfgBIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL                                                       0x0294
+#define cfgBIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL                                                       0x0296
+#define cfgBIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL                                                       0x0298
+#define cfgBIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL                                                       0x029a
+#define cfgBIFPLR0_PCIE_ACS_ENH_CAP_LIST                                                                0x02a0
+#define cfgBIFPLR0_PCIE_ACS_CAP                                                                         0x02a4
+#define cfgBIFPLR0_PCIE_ACS_CNTL                                                                        0x02a6
+#define cfgBIFPLR0_PCIE_MC_ENH_CAP_LIST                                                                 0x02f0
+#define cfgBIFPLR0_PCIE_MC_CAP                                                                          0x02f4
+#define cfgBIFPLR0_PCIE_MC_CNTL                                                                         0x02f6
+#define cfgBIFPLR0_PCIE_MC_ADDR0                                                                        0x02f8
+#define cfgBIFPLR0_PCIE_MC_ADDR1                                                                        0x02fc
+#define cfgBIFPLR0_PCIE_MC_RCV0                                                                         0x0300
+#define cfgBIFPLR0_PCIE_MC_RCV1                                                                         0x0304
+#define cfgBIFPLR0_PCIE_MC_BLOCK_ALL0                                                                   0x0308
+#define cfgBIFPLR0_PCIE_MC_BLOCK_ALL1                                                                   0x030c
+#define cfgBIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_0                                                         0x0310
+#define cfgBIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_1                                                         0x0314
+#define cfgBIFPLR0_PCIE_MC_OVERLAY_BAR0                                                                 0x0318
+#define cfgBIFPLR0_PCIE_MC_OVERLAY_BAR1                                                                 0x031c
+#define cfgBIFPLR0_PCIE_L1_PM_SUB_CAP_LIST                                                              0x0370
+#define cfgBIFPLR0_PCIE_L1_PM_SUB_CAP                                                                   0x0374
+#define cfgBIFPLR0_PCIE_L1_PM_SUB_CNTL                                                                  0x0378
+#define cfgBIFPLR0_PCIE_L1_PM_SUB_CNTL2                                                                 0x037c
+#define cfgBIFPLR0_PCIE_DPC_ENH_CAP_LIST                                                                0x0380
+#define cfgBIFPLR0_PCIE_DPC_CAP_LIST                                                                    0x0384
+#define cfgBIFPLR0_PCIE_DPC_CNTL                                                                        0x0386
+#define cfgBIFPLR0_PCIE_DPC_STATUS                                                                      0x0388
+#define cfgBIFPLR0_PCIE_DPC_ERROR_SOURCE_ID                                                             0x038a
+#define cfgBIFPLR0_PCIE_RP_PIO_STATUS                                                                   0x038c
+#define cfgBIFPLR0_PCIE_RP_PIO_MASK                                                                     0x0390
+#define cfgBIFPLR0_PCIE_RP_PIO_SEVERITY                                                                 0x0394
+#define cfgBIFPLR0_PCIE_RP_PIO_SYSERROR                                                                 0x0398
+#define cfgBIFPLR0_PCIE_RP_PIO_EXCEPTION                                                                0x039c
+#define cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG0                                                                 0x03a0
+#define cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG1                                                                 0x03a4
+#define cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG2                                                                 0x03a8
+#define cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG3                                                                 0x03ac
+#define cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG0                                                              0x03b4
+#define cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG1                                                              0x03b8
+#define cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG2                                                              0x03bc
+#define cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG3                                                              0x03c0
+#define cfgBIFPLR0_PCIE_ESM_CAP_LIST                                                                    0x03c4
+#define cfgBIFPLR0_PCIE_ESM_HEADER_1                                                                    0x03c8
+#define cfgBIFPLR0_PCIE_ESM_HEADER_2                                                                    0x03cc
+#define cfgBIFPLR0_PCIE_ESM_STATUS                                                                      0x03ce
+#define cfgBIFPLR0_PCIE_ESM_CTRL                                                                        0x03d0
+#define cfgBIFPLR0_PCIE_ESM_CAP_1                                                                       0x03d4
+#define cfgBIFPLR0_PCIE_ESM_CAP_2                                                                       0x03d8
+#define cfgBIFPLR0_PCIE_ESM_CAP_3                                                                       0x03dc
+#define cfgBIFPLR0_PCIE_ESM_CAP_4                                                                       0x03e0
+#define cfgBIFPLR0_PCIE_ESM_CAP_5                                                                       0x03e4
+#define cfgBIFPLR0_PCIE_ESM_CAP_6                                                                       0x03e8
+#define cfgBIFPLR0_PCIE_ESM_CAP_7                                                                       0x03ec
+#define cfgBIFPLR0_PCIE_DLF_ENH_CAP_LIST                                                                0x0400
+#define cfgBIFPLR0_DATA_LINK_FEATURE_CAP                                                                0x0404
+#define cfgBIFPLR0_DATA_LINK_FEATURE_STATUS                                                             0x0408
+#define cfgBIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST                                                           0x0410
+#define cfgBIFPLR0_LINK_CAP_16GT                                                                        0x0414
+#define cfgBIFPLR0_LINK_CNTL_16GT                                                                       0x0418
+#define cfgBIFPLR0_LINK_STATUS_16GT                                                                     0x041c
+#define cfgBIFPLR0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                    0x0420
+#define cfgBIFPLR0_RTM1_PARITY_MISMATCH_STATUS_16GT                                                     0x0424
+#define cfgBIFPLR0_RTM2_PARITY_MISMATCH_STATUS_16GT                                                     0x0428
+#define cfgBIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT                                                        0x0430
+#define cfgBIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT                                                        0x0431
+#define cfgBIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT                                                        0x0432
+#define cfgBIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT                                                        0x0433
+#define cfgBIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT                                                        0x0434
+#define cfgBIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT                                                        0x0435
+#define cfgBIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT                                                        0x0436
+#define cfgBIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT                                                        0x0437
+#define cfgBIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT                                                        0x0438
+#define cfgBIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT                                                        0x0439
+#define cfgBIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT                                                       0x043a
+#define cfgBIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT                                                       0x043b
+#define cfgBIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT                                                       0x043c
+#define cfgBIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT                                                       0x043d
+#define cfgBIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT                                                       0x043e
+#define cfgBIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT                                                       0x043f
+#define cfgBIFPLR0_PCIE_MARGINING_ENH_CAP_LIST                                                          0x0440
+#define cfgBIFPLR0_MARGINING_PORT_CAP                                                                   0x0444
+#define cfgBIFPLR0_MARGINING_PORT_STATUS                                                                0x0446
+#define cfgBIFPLR0_LANE_0_MARGINING_LANE_CNTL                                                           0x0448
+#define cfgBIFPLR0_LANE_0_MARGINING_LANE_STATUS                                                         0x044a
+#define cfgBIFPLR0_LANE_1_MARGINING_LANE_CNTL                                                           0x044c
+#define cfgBIFPLR0_LANE_1_MARGINING_LANE_STATUS                                                         0x044e
+#define cfgBIFPLR0_LANE_2_MARGINING_LANE_CNTL                                                           0x0450
+#define cfgBIFPLR0_LANE_2_MARGINING_LANE_STATUS                                                         0x0452
+#define cfgBIFPLR0_LANE_3_MARGINING_LANE_CNTL                                                           0x0454
+#define cfgBIFPLR0_LANE_3_MARGINING_LANE_STATUS                                                         0x0456
+#define cfgBIFPLR0_LANE_4_MARGINING_LANE_CNTL                                                           0x0458
+#define cfgBIFPLR0_LANE_4_MARGINING_LANE_STATUS                                                         0x045a
+#define cfgBIFPLR0_LANE_5_MARGINING_LANE_CNTL                                                           0x045c
+#define cfgBIFPLR0_LANE_5_MARGINING_LANE_STATUS                                                         0x045e
+#define cfgBIFPLR0_LANE_6_MARGINING_LANE_CNTL                                                           0x0460
+#define cfgBIFPLR0_LANE_6_MARGINING_LANE_STATUS                                                         0x0462
+#define cfgBIFPLR0_LANE_7_MARGINING_LANE_CNTL                                                           0x0464
+#define cfgBIFPLR0_LANE_7_MARGINING_LANE_STATUS                                                         0x0466
+#define cfgBIFPLR0_LANE_8_MARGINING_LANE_CNTL                                                           0x0468
+#define cfgBIFPLR0_LANE_8_MARGINING_LANE_STATUS                                                         0x046a
+#define cfgBIFPLR0_LANE_9_MARGINING_LANE_CNTL                                                           0x046c
+#define cfgBIFPLR0_LANE_9_MARGINING_LANE_STATUS                                                         0x046e
+#define cfgBIFPLR0_LANE_10_MARGINING_LANE_CNTL                                                          0x0470
+#define cfgBIFPLR0_LANE_10_MARGINING_LANE_STATUS                                                        0x0472
+#define cfgBIFPLR0_LANE_11_MARGINING_LANE_CNTL                                                          0x0474
+#define cfgBIFPLR0_LANE_11_MARGINING_LANE_STATUS                                                        0x0476
+#define cfgBIFPLR0_LANE_12_MARGINING_LANE_CNTL                                                          0x0478
+#define cfgBIFPLR0_LANE_12_MARGINING_LANE_STATUS                                                        0x047a
+#define cfgBIFPLR0_LANE_13_MARGINING_LANE_CNTL                                                          0x047c
+#define cfgBIFPLR0_LANE_13_MARGINING_LANE_STATUS                                                        0x047e
+#define cfgBIFPLR0_LANE_14_MARGINING_LANE_CNTL                                                          0x0480
+#define cfgBIFPLR0_LANE_14_MARGINING_LANE_STATUS                                                        0x0482
+#define cfgBIFPLR0_LANE_15_MARGINING_LANE_CNTL                                                          0x0484
+#define cfgBIFPLR0_LANE_15_MARGINING_LANE_STATUS                                                        0x0486
+#define cfgBIFPLR0_PCIE_CCIX_CAP_LIST                                                                   0x0488
+#define cfgBIFPLR0_PCIE_CCIX_HEADER_1                                                                   0x048c
+#define cfgBIFPLR0_PCIE_CCIX_HEADER_2                                                                   0x0490
+#define cfgBIFPLR0_PCIE_CCIX_CAP                                                                        0x0492
+#define cfgBIFPLR0_PCIE_CCIX_ESM_REQD_CAP                                                               0x0494
+#define cfgBIFPLR0_PCIE_CCIX_ESM_OPTL_CAP                                                               0x0498
+#define cfgBIFPLR0_PCIE_CCIX_ESM_STATUS                                                                 0x049c
+#define cfgBIFPLR0_PCIE_CCIX_ESM_CNTL                                                                   0x04a0
+#define cfgBIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                    0x04a4
+#define cfgBIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                    0x04a5
+#define cfgBIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                    0x04a6
+#define cfgBIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                    0x04a7
+#define cfgBIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                    0x04a8
+#define cfgBIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                    0x04a9
+#define cfgBIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                    0x04aa
+#define cfgBIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                    0x04ab
+#define cfgBIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                    0x04ac
+#define cfgBIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                    0x04ad
+#define cfgBIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                   0x04ae
+#define cfgBIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                   0x04af
+#define cfgBIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                   0x04b0
+#define cfgBIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                   0x04b1
+#define cfgBIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                   0x04b2
+#define cfgBIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                   0x04b3
+#define cfgBIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                    0x04b4
+#define cfgBIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                    0x04b5
+#define cfgBIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                    0x04b6
+#define cfgBIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                    0x04b7
+#define cfgBIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                    0x04b8
+#define cfgBIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                    0x04b9
+#define cfgBIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                    0x04ba
+#define cfgBIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                    0x04bb
+#define cfgBIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                    0x04bc
+#define cfgBIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                    0x04bd
+#define cfgBIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                   0x04be
+#define cfgBIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                   0x04bf
+#define cfgBIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                   0x04c0
+#define cfgBIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                   0x04c1
+#define cfgBIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                   0x04c2
+#define cfgBIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                   0x04c3
+#define cfgBIFPLR0_PCIE_CCIX_TRANS_CAP                                                                  0x04c4
+#define cfgBIFPLR0_PCIE_CCIX_TRANS_CNTL                                                                 0x04c8
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+// base address: 0x0
+#define cfgBIFPLR1_VENDOR_ID                                                                            0x0000
+#define cfgBIFPLR1_DEVICE_ID                                                                            0x0002
+#define cfgBIFPLR1_COMMAND                                                                              0x0004
+#define cfgBIFPLR1_STATUS                                                                               0x0006
+#define cfgBIFPLR1_REVISION_ID                                                                          0x0008
+#define cfgBIFPLR1_PROG_INTERFACE                                                                       0x0009
+#define cfgBIFPLR1_SUB_CLASS                                                                            0x000a
+#define cfgBIFPLR1_BASE_CLASS                                                                           0x000b
+#define cfgBIFPLR1_CACHE_LINE                                                                           0x000c
+#define cfgBIFPLR1_LATENCY                                                                              0x000d
+#define cfgBIFPLR1_HEADER                                                                               0x000e
+#define cfgBIFPLR1_BIST                                                                                 0x000f
+#define cfgBIFPLR1_SUB_BUS_NUMBER_LATENCY                                                               0x0018
+#define cfgBIFPLR1_IO_BASE_LIMIT                                                                        0x001c
+#define cfgBIFPLR1_SECONDARY_STATUS                                                                     0x001e
+#define cfgBIFPLR1_MEM_BASE_LIMIT                                                                       0x0020
+#define cfgBIFPLR1_PREF_BASE_LIMIT                                                                      0x0024
+#define cfgBIFPLR1_PREF_BASE_UPPER                                                                      0x0028
+#define cfgBIFPLR1_PREF_LIMIT_UPPER                                                                     0x002c
+#define cfgBIFPLR1_IO_BASE_LIMIT_HI                                                                     0x0030
+#define cfgBIFPLR1_CAP_PTR                                                                              0x0034
+#define cfgBIFPLR1_ROM_BASE_ADDR                                                                        0x0038
+#define cfgBIFPLR1_INTERRUPT_LINE                                                                       0x003c
+#define cfgBIFPLR1_INTERRUPT_PIN                                                                        0x003d
+#define cfgBIFPLR1_IRQ_BRIDGE_CNTL                                                                      0x003e
+#define cfgBIFPLR1_EXT_BRIDGE_CNTL                                                                      0x0040
+#define cfgBIFPLR1_VENDOR_CAP_LIST                                                                      0x0048
+#define cfgBIFPLR1_ADAPTER_ID_W                                                                         0x004c
+#define cfgBIFPLR1_PMI_CAP_LIST                                                                         0x0050
+#define cfgBIFPLR1_PMI_CAP                                                                              0x0052
+#define cfgBIFPLR1_PMI_STATUS_CNTL                                                                      0x0054
+#define cfgBIFPLR1_PCIE_CAP_LIST                                                                        0x0058
+#define cfgBIFPLR1_PCIE_CAP                                                                             0x005a
+#define cfgBIFPLR1_DEVICE_CAP                                                                           0x005c
+#define cfgBIFPLR1_DEVICE_CNTL                                                                          0x0060
+#define cfgBIFPLR1_DEVICE_STATUS                                                                        0x0062
+#define cfgBIFPLR1_LINK_CAP                                                                             0x0064
+#define cfgBIFPLR1_LINK_CNTL                                                                            0x0068
+#define cfgBIFPLR1_LINK_STATUS                                                                          0x006a
+#define cfgBIFPLR1_SLOT_CAP                                                                             0x006c
+#define cfgBIFPLR1_SLOT_CNTL                                                                            0x0070
+#define cfgBIFPLR1_SLOT_STATUS                                                                          0x0072
+#define cfgBIFPLR1_ROOT_CNTL                                                                            0x0074
+#define cfgBIFPLR1_ROOT_CAP                                                                             0x0076
+#define cfgBIFPLR1_ROOT_STATUS                                                                          0x0078
+#define cfgBIFPLR1_DEVICE_CAP2                                                                          0x007c
+#define cfgBIFPLR1_DEVICE_CNTL2                                                                         0x0080
+#define cfgBIFPLR1_DEVICE_STATUS2                                                                       0x0082
+#define cfgBIFPLR1_LINK_CAP2                                                                            0x0084
+#define cfgBIFPLR1_LINK_CNTL2                                                                           0x0088
+#define cfgBIFPLR1_LINK_STATUS2                                                                         0x008a
+#define cfgBIFPLR1_SLOT_CAP2                                                                            0x008c
+#define cfgBIFPLR1_SLOT_CNTL2                                                                           0x0090
+#define cfgBIFPLR1_SLOT_STATUS2                                                                         0x0092
+#define cfgBIFPLR1_MSI_CAP_LIST                                                                         0x00a0
+#define cfgBIFPLR1_MSI_MSG_CNTL                                                                         0x00a2
+#define cfgBIFPLR1_MSI_MSG_ADDR_LO                                                                      0x00a4
+#define cfgBIFPLR1_MSI_MSG_ADDR_HI                                                                      0x00a8
+#define cfgBIFPLR1_MSI_MSG_DATA                                                                         0x00a8
+#define cfgBIFPLR1_MSI_MSG_DATA_64                                                                      0x00ac
+#define cfgBIFPLR1_SSID_CAP_LIST                                                                        0x00c0
+#define cfgBIFPLR1_SSID_CAP                                                                             0x00c4
+#define cfgBIFPLR1_MSI_MAP_CAP_LIST                                                                     0x00c8
+#define cfgBIFPLR1_MSI_MAP_CAP                                                                          0x00ca
+#define cfgBIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                    0x0100
+#define cfgBIFPLR1_PCIE_VENDOR_SPECIFIC_HDR                                                             0x0104
+#define cfgBIFPLR1_PCIE_VENDOR_SPECIFIC1                                                                0x0108
+#define cfgBIFPLR1_PCIE_VENDOR_SPECIFIC2                                                                0x010c
+#define cfgBIFPLR1_PCIE_VC_ENH_CAP_LIST                                                                 0x0110
+#define cfgBIFPLR1_PCIE_PORT_VC_CAP_REG1                                                                0x0114
+#define cfgBIFPLR1_PCIE_PORT_VC_CAP_REG2                                                                0x0118
+#define cfgBIFPLR1_PCIE_PORT_VC_CNTL                                                                    0x011c
+#define cfgBIFPLR1_PCIE_PORT_VC_STATUS                                                                  0x011e
+#define cfgBIFPLR1_PCIE_VC0_RESOURCE_CAP                                                                0x0120
+#define cfgBIFPLR1_PCIE_VC0_RESOURCE_CNTL                                                               0x0124
+#define cfgBIFPLR1_PCIE_VC0_RESOURCE_STATUS                                                             0x012a
+#define cfgBIFPLR1_PCIE_VC1_RESOURCE_CAP                                                                0x012c
+#define cfgBIFPLR1_PCIE_VC1_RESOURCE_CNTL                                                               0x0130
+#define cfgBIFPLR1_PCIE_VC1_RESOURCE_STATUS                                                             0x0136
+#define cfgBIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                     0x0140
+#define cfgBIFPLR1_PCIE_DEV_SERIAL_NUM_DW1                                                              0x0144
+#define cfgBIFPLR1_PCIE_DEV_SERIAL_NUM_DW2                                                              0x0148
+#define cfgBIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                        0x0150
+#define cfgBIFPLR1_PCIE_UNCORR_ERR_STATUS                                                               0x0154
+#define cfgBIFPLR1_PCIE_UNCORR_ERR_MASK                                                                 0x0158
+#define cfgBIFPLR1_PCIE_UNCORR_ERR_SEVERITY                                                             0x015c
+#define cfgBIFPLR1_PCIE_CORR_ERR_STATUS                                                                 0x0160
+#define cfgBIFPLR1_PCIE_CORR_ERR_MASK                                                                   0x0164
+#define cfgBIFPLR1_PCIE_ADV_ERR_CAP_CNTL                                                                0x0168
+#define cfgBIFPLR1_PCIE_HDR_LOG0                                                                        0x016c
+#define cfgBIFPLR1_PCIE_HDR_LOG1                                                                        0x0170
+#define cfgBIFPLR1_PCIE_HDR_LOG2                                                                        0x0174
+#define cfgBIFPLR1_PCIE_HDR_LOG3                                                                        0x0178
+#define cfgBIFPLR1_PCIE_ROOT_ERR_CMD                                                                    0x017c
+#define cfgBIFPLR1_PCIE_ROOT_ERR_STATUS                                                                 0x0180
+#define cfgBIFPLR1_PCIE_ERR_SRC_ID                                                                      0x0184
+#define cfgBIFPLR1_PCIE_TLP_PREFIX_LOG0                                                                 0x0188
+#define cfgBIFPLR1_PCIE_TLP_PREFIX_LOG1                                                                 0x018c
+#define cfgBIFPLR1_PCIE_TLP_PREFIX_LOG2                                                                 0x0190
+#define cfgBIFPLR1_PCIE_TLP_PREFIX_LOG3                                                                 0x0194
+#define cfgBIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST                                                          0x0270
+#define cfgBIFPLR1_PCIE_LINK_CNTL3                                                                      0x0274
+#define cfgBIFPLR1_PCIE_LANE_ERROR_STATUS                                                               0x0278
+#define cfgBIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL                                                        0x027c
+#define cfgBIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL                                                        0x027e
+#define cfgBIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL                                                        0x0280
+#define cfgBIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL                                                        0x0282
+#define cfgBIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL                                                        0x0284
+#define cfgBIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL                                                        0x0286
+#define cfgBIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL                                                        0x0288
+#define cfgBIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL                                                        0x028a
+#define cfgBIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL                                                        0x028c
+#define cfgBIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL                                                        0x028e
+#define cfgBIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL                                                       0x0290
+#define cfgBIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL                                                       0x0292
+#define cfgBIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL                                                       0x0294
+#define cfgBIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL                                                       0x0296
+#define cfgBIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL                                                       0x0298
+#define cfgBIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL                                                       0x029a
+#define cfgBIFPLR1_PCIE_ACS_ENH_CAP_LIST                                                                0x02a0
+#define cfgBIFPLR1_PCIE_ACS_CAP                                                                         0x02a4
+#define cfgBIFPLR1_PCIE_ACS_CNTL                                                                        0x02a6
+#define cfgBIFPLR1_PCIE_MC_ENH_CAP_LIST                                                                 0x02f0
+#define cfgBIFPLR1_PCIE_MC_CAP                                                                          0x02f4
+#define cfgBIFPLR1_PCIE_MC_CNTL                                                                         0x02f6
+#define cfgBIFPLR1_PCIE_MC_ADDR0                                                                        0x02f8
+#define cfgBIFPLR1_PCIE_MC_ADDR1                                                                        0x02fc
+#define cfgBIFPLR1_PCIE_MC_RCV0                                                                         0x0300
+#define cfgBIFPLR1_PCIE_MC_RCV1                                                                         0x0304
+#define cfgBIFPLR1_PCIE_MC_BLOCK_ALL0                                                                   0x0308
+#define cfgBIFPLR1_PCIE_MC_BLOCK_ALL1                                                                   0x030c
+#define cfgBIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_0                                                         0x0310
+#define cfgBIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_1                                                         0x0314
+#define cfgBIFPLR1_PCIE_MC_OVERLAY_BAR0                                                                 0x0318
+#define cfgBIFPLR1_PCIE_MC_OVERLAY_BAR1                                                                 0x031c
+#define cfgBIFPLR1_PCIE_L1_PM_SUB_CAP_LIST                                                              0x0370
+#define cfgBIFPLR1_PCIE_L1_PM_SUB_CAP                                                                   0x0374
+#define cfgBIFPLR1_PCIE_L1_PM_SUB_CNTL                                                                  0x0378
+#define cfgBIFPLR1_PCIE_L1_PM_SUB_CNTL2                                                                 0x037c
+#define cfgBIFPLR1_PCIE_DPC_ENH_CAP_LIST                                                                0x0380
+#define cfgBIFPLR1_PCIE_DPC_CAP_LIST                                                                    0x0384
+#define cfgBIFPLR1_PCIE_DPC_CNTL                                                                        0x0386
+#define cfgBIFPLR1_PCIE_DPC_STATUS                                                                      0x0388
+#define cfgBIFPLR1_PCIE_DPC_ERROR_SOURCE_ID                                                             0x038a
+#define cfgBIFPLR1_PCIE_RP_PIO_STATUS                                                                   0x038c
+#define cfgBIFPLR1_PCIE_RP_PIO_MASK                                                                     0x0390
+#define cfgBIFPLR1_PCIE_RP_PIO_SEVERITY                                                                 0x0394
+#define cfgBIFPLR1_PCIE_RP_PIO_SYSERROR                                                                 0x0398
+#define cfgBIFPLR1_PCIE_RP_PIO_EXCEPTION                                                                0x039c
+#define cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG0                                                                 0x03a0
+#define cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG1                                                                 0x03a4
+#define cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG2                                                                 0x03a8
+#define cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG3                                                                 0x03ac
+#define cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG0                                                              0x03b4
+#define cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG1                                                              0x03b8
+#define cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG2                                                              0x03bc
+#define cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG3                                                              0x03c0
+#define cfgBIFPLR1_PCIE_ESM_CAP_LIST                                                                    0x03c4
+#define cfgBIFPLR1_PCIE_ESM_HEADER_1                                                                    0x03c8
+#define cfgBIFPLR1_PCIE_ESM_HEADER_2                                                                    0x03cc
+#define cfgBIFPLR1_PCIE_ESM_STATUS                                                                      0x03ce
+#define cfgBIFPLR1_PCIE_ESM_CTRL                                                                        0x03d0
+#define cfgBIFPLR1_PCIE_ESM_CAP_1                                                                       0x03d4
+#define cfgBIFPLR1_PCIE_ESM_CAP_2                                                                       0x03d8
+#define cfgBIFPLR1_PCIE_ESM_CAP_3                                                                       0x03dc
+#define cfgBIFPLR1_PCIE_ESM_CAP_4                                                                       0x03e0
+#define cfgBIFPLR1_PCIE_ESM_CAP_5                                                                       0x03e4
+#define cfgBIFPLR1_PCIE_ESM_CAP_6                                                                       0x03e8
+#define cfgBIFPLR1_PCIE_ESM_CAP_7                                                                       0x03ec
+#define cfgBIFPLR1_PCIE_DLF_ENH_CAP_LIST                                                                0x0400
+#define cfgBIFPLR1_DATA_LINK_FEATURE_CAP                                                                0x0404
+#define cfgBIFPLR1_DATA_LINK_FEATURE_STATUS                                                             0x0408
+#define cfgBIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST                                                           0x0410
+#define cfgBIFPLR1_LINK_CAP_16GT                                                                        0x0414
+#define cfgBIFPLR1_LINK_CNTL_16GT                                                                       0x0418
+#define cfgBIFPLR1_LINK_STATUS_16GT                                                                     0x041c
+#define cfgBIFPLR1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                    0x0420
+#define cfgBIFPLR1_RTM1_PARITY_MISMATCH_STATUS_16GT                                                     0x0424
+#define cfgBIFPLR1_RTM2_PARITY_MISMATCH_STATUS_16GT                                                     0x0428
+#define cfgBIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT                                                        0x0430
+#define cfgBIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT                                                        0x0431
+#define cfgBIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT                                                        0x0432
+#define cfgBIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT                                                        0x0433
+#define cfgBIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT                                                        0x0434
+#define cfgBIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT                                                        0x0435
+#define cfgBIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT                                                        0x0436
+#define cfgBIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT                                                        0x0437
+#define cfgBIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT                                                        0x0438
+#define cfgBIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT                                                        0x0439
+#define cfgBIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT                                                       0x043a
+#define cfgBIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT                                                       0x043b
+#define cfgBIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT                                                       0x043c
+#define cfgBIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT                                                       0x043d
+#define cfgBIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT                                                       0x043e
+#define cfgBIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT                                                       0x043f
+#define cfgBIFPLR1_PCIE_MARGINING_ENH_CAP_LIST                                                          0x0440
+#define cfgBIFPLR1_MARGINING_PORT_CAP                                                                   0x0444
+#define cfgBIFPLR1_MARGINING_PORT_STATUS                                                                0x0446
+#define cfgBIFPLR1_LANE_0_MARGINING_LANE_CNTL                                                           0x0448
+#define cfgBIFPLR1_LANE_0_MARGINING_LANE_STATUS                                                         0x044a
+#define cfgBIFPLR1_LANE_1_MARGINING_LANE_CNTL                                                           0x044c
+#define cfgBIFPLR1_LANE_1_MARGINING_LANE_STATUS                                                         0x044e
+#define cfgBIFPLR1_LANE_2_MARGINING_LANE_CNTL                                                           0x0450
+#define cfgBIFPLR1_LANE_2_MARGINING_LANE_STATUS                                                         0x0452
+#define cfgBIFPLR1_LANE_3_MARGINING_LANE_CNTL                                                           0x0454
+#define cfgBIFPLR1_LANE_3_MARGINING_LANE_STATUS                                                         0x0456
+#define cfgBIFPLR1_LANE_4_MARGINING_LANE_CNTL                                                           0x0458
+#define cfgBIFPLR1_LANE_4_MARGINING_LANE_STATUS                                                         0x045a
+#define cfgBIFPLR1_LANE_5_MARGINING_LANE_CNTL                                                           0x045c
+#define cfgBIFPLR1_LANE_5_MARGINING_LANE_STATUS                                                         0x045e
+#define cfgBIFPLR1_LANE_6_MARGINING_LANE_CNTL                                                           0x0460
+#define cfgBIFPLR1_LANE_6_MARGINING_LANE_STATUS                                                         0x0462
+#define cfgBIFPLR1_LANE_7_MARGINING_LANE_CNTL                                                           0x0464
+#define cfgBIFPLR1_LANE_7_MARGINING_LANE_STATUS                                                         0x0466
+#define cfgBIFPLR1_LANE_8_MARGINING_LANE_CNTL                                                           0x0468
+#define cfgBIFPLR1_LANE_8_MARGINING_LANE_STATUS                                                         0x046a
+#define cfgBIFPLR1_LANE_9_MARGINING_LANE_CNTL                                                           0x046c
+#define cfgBIFPLR1_LANE_9_MARGINING_LANE_STATUS                                                         0x046e
+#define cfgBIFPLR1_LANE_10_MARGINING_LANE_CNTL                                                          0x0470
+#define cfgBIFPLR1_LANE_10_MARGINING_LANE_STATUS                                                        0x0472
+#define cfgBIFPLR1_LANE_11_MARGINING_LANE_CNTL                                                          0x0474
+#define cfgBIFPLR1_LANE_11_MARGINING_LANE_STATUS                                                        0x0476
+#define cfgBIFPLR1_LANE_12_MARGINING_LANE_CNTL                                                          0x0478
+#define cfgBIFPLR1_LANE_12_MARGINING_LANE_STATUS                                                        0x047a
+#define cfgBIFPLR1_LANE_13_MARGINING_LANE_CNTL                                                          0x047c
+#define cfgBIFPLR1_LANE_13_MARGINING_LANE_STATUS                                                        0x047e
+#define cfgBIFPLR1_LANE_14_MARGINING_LANE_CNTL                                                          0x0480
+#define cfgBIFPLR1_LANE_14_MARGINING_LANE_STATUS                                                        0x0482
+#define cfgBIFPLR1_LANE_15_MARGINING_LANE_CNTL                                                          0x0484
+#define cfgBIFPLR1_LANE_15_MARGINING_LANE_STATUS                                                        0x0486
+#define cfgBIFPLR1_PCIE_CCIX_CAP_LIST                                                                   0x0488
+#define cfgBIFPLR1_PCIE_CCIX_HEADER_1                                                                   0x048c
+#define cfgBIFPLR1_PCIE_CCIX_HEADER_2                                                                   0x0490
+#define cfgBIFPLR1_PCIE_CCIX_CAP                                                                        0x0492
+#define cfgBIFPLR1_PCIE_CCIX_ESM_REQD_CAP                                                               0x0494
+#define cfgBIFPLR1_PCIE_CCIX_ESM_OPTL_CAP                                                               0x0498
+#define cfgBIFPLR1_PCIE_CCIX_ESM_STATUS                                                                 0x049c
+#define cfgBIFPLR1_PCIE_CCIX_ESM_CNTL                                                                   0x04a0
+#define cfgBIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                    0x04a4
+#define cfgBIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                    0x04a5
+#define cfgBIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                    0x04a6
+#define cfgBIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                    0x04a7
+#define cfgBIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                    0x04a8
+#define cfgBIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                    0x04a9
+#define cfgBIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                    0x04aa
+#define cfgBIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                    0x04ab
+#define cfgBIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                    0x04ac
+#define cfgBIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                    0x04ad
+#define cfgBIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                   0x04ae
+#define cfgBIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                   0x04af
+#define cfgBIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                   0x04b0
+#define cfgBIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                   0x04b1
+#define cfgBIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                   0x04b2
+#define cfgBIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                   0x04b3
+#define cfgBIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                    0x04b4
+#define cfgBIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                    0x04b5
+#define cfgBIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                    0x04b6
+#define cfgBIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                    0x04b7
+#define cfgBIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                    0x04b8
+#define cfgBIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                    0x04b9
+#define cfgBIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                    0x04ba
+#define cfgBIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                    0x04bb
+#define cfgBIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                    0x04bc
+#define cfgBIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                    0x04bd
+#define cfgBIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                   0x04be
+#define cfgBIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                   0x04bf
+#define cfgBIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                   0x04c0
+#define cfgBIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                   0x04c1
+#define cfgBIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                   0x04c2
+#define cfgBIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                   0x04c3
+#define cfgBIFPLR1_PCIE_CCIX_TRANS_CAP                                                                  0x04c4
+#define cfgBIFPLR1_PCIE_CCIX_TRANS_CNTL                                                                 0x04c8
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+// base address: 0x0
+#define cfgBIFPLR2_VENDOR_ID                                                                            0x0000
+#define cfgBIFPLR2_DEVICE_ID                                                                            0x0002
+#define cfgBIFPLR2_COMMAND                                                                              0x0004
+#define cfgBIFPLR2_STATUS                                                                               0x0006
+#define cfgBIFPLR2_REVISION_ID                                                                          0x0008
+#define cfgBIFPLR2_PROG_INTERFACE                                                                       0x0009
+#define cfgBIFPLR2_SUB_CLASS                                                                            0x000a
+#define cfgBIFPLR2_BASE_CLASS                                                                           0x000b
+#define cfgBIFPLR2_CACHE_LINE                                                                           0x000c
+#define cfgBIFPLR2_LATENCY                                                                              0x000d
+#define cfgBIFPLR2_HEADER                                                                               0x000e
+#define cfgBIFPLR2_BIST                                                                                 0x000f
+#define cfgBIFPLR2_SUB_BUS_NUMBER_LATENCY                                                               0x0018
+#define cfgBIFPLR2_IO_BASE_LIMIT                                                                        0x001c
+#define cfgBIFPLR2_SECONDARY_STATUS                                                                     0x001e
+#define cfgBIFPLR2_MEM_BASE_LIMIT                                                                       0x0020
+#define cfgBIFPLR2_PREF_BASE_LIMIT                                                                      0x0024
+#define cfgBIFPLR2_PREF_BASE_UPPER                                                                      0x0028
+#define cfgBIFPLR2_PREF_LIMIT_UPPER                                                                     0x002c
+#define cfgBIFPLR2_IO_BASE_LIMIT_HI                                                                     0x0030
+#define cfgBIFPLR2_CAP_PTR                                                                              0x0034
+#define cfgBIFPLR2_ROM_BASE_ADDR                                                                        0x0038
+#define cfgBIFPLR2_INTERRUPT_LINE                                                                       0x003c
+#define cfgBIFPLR2_INTERRUPT_PIN                                                                        0x003d
+#define cfgBIFPLR2_IRQ_BRIDGE_CNTL                                                                      0x003e
+#define cfgBIFPLR2_EXT_BRIDGE_CNTL                                                                      0x0040
+#define cfgBIFPLR2_VENDOR_CAP_LIST                                                                      0x0048
+#define cfgBIFPLR2_ADAPTER_ID_W                                                                         0x004c
+#define cfgBIFPLR2_PMI_CAP_LIST                                                                         0x0050
+#define cfgBIFPLR2_PMI_CAP                                                                              0x0052
+#define cfgBIFPLR2_PMI_STATUS_CNTL                                                                      0x0054
+#define cfgBIFPLR2_PCIE_CAP_LIST                                                                        0x0058
+#define cfgBIFPLR2_PCIE_CAP                                                                             0x005a
+#define cfgBIFPLR2_DEVICE_CAP                                                                           0x005c
+#define cfgBIFPLR2_DEVICE_CNTL                                                                          0x0060
+#define cfgBIFPLR2_DEVICE_STATUS                                                                        0x0062
+#define cfgBIFPLR2_LINK_CAP                                                                             0x0064
+#define cfgBIFPLR2_LINK_CNTL                                                                            0x0068
+#define cfgBIFPLR2_LINK_STATUS                                                                          0x006a
+#define cfgBIFPLR2_SLOT_CAP                                                                             0x006c
+#define cfgBIFPLR2_SLOT_CNTL                                                                            0x0070
+#define cfgBIFPLR2_SLOT_STATUS                                                                          0x0072
+#define cfgBIFPLR2_ROOT_CNTL                                                                            0x0074
+#define cfgBIFPLR2_ROOT_CAP                                                                             0x0076
+#define cfgBIFPLR2_ROOT_STATUS                                                                          0x0078
+#define cfgBIFPLR2_DEVICE_CAP2                                                                          0x007c
+#define cfgBIFPLR2_DEVICE_CNTL2                                                                         0x0080
+#define cfgBIFPLR2_DEVICE_STATUS2                                                                       0x0082
+#define cfgBIFPLR2_LINK_CAP2                                                                            0x0084
+#define cfgBIFPLR2_LINK_CNTL2                                                                           0x0088
+#define cfgBIFPLR2_LINK_STATUS2                                                                         0x008a
+#define cfgBIFPLR2_SLOT_CAP2                                                                            0x008c
+#define cfgBIFPLR2_SLOT_CNTL2                                                                           0x0090
+#define cfgBIFPLR2_SLOT_STATUS2                                                                         0x0092
+#define cfgBIFPLR2_MSI_CAP_LIST                                                                         0x00a0
+#define cfgBIFPLR2_MSI_MSG_CNTL                                                                         0x00a2
+#define cfgBIFPLR2_MSI_MSG_ADDR_LO                                                                      0x00a4
+#define cfgBIFPLR2_MSI_MSG_ADDR_HI                                                                      0x00a8
+#define cfgBIFPLR2_MSI_MSG_DATA                                                                         0x00a8
+#define cfgBIFPLR2_MSI_MSG_DATA_64                                                                      0x00ac
+#define cfgBIFPLR2_SSID_CAP_LIST                                                                        0x00c0
+#define cfgBIFPLR2_SSID_CAP                                                                             0x00c4
+#define cfgBIFPLR2_MSI_MAP_CAP_LIST                                                                     0x00c8
+#define cfgBIFPLR2_MSI_MAP_CAP                                                                          0x00ca
+#define cfgBIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                    0x0100
+#define cfgBIFPLR2_PCIE_VENDOR_SPECIFIC_HDR                                                             0x0104
+#define cfgBIFPLR2_PCIE_VENDOR_SPECIFIC1                                                                0x0108
+#define cfgBIFPLR2_PCIE_VENDOR_SPECIFIC2                                                                0x010c
+#define cfgBIFPLR2_PCIE_VC_ENH_CAP_LIST                                                                 0x0110
+#define cfgBIFPLR2_PCIE_PORT_VC_CAP_REG1                                                                0x0114
+#define cfgBIFPLR2_PCIE_PORT_VC_CAP_REG2                                                                0x0118
+#define cfgBIFPLR2_PCIE_PORT_VC_CNTL                                                                    0x011c
+#define cfgBIFPLR2_PCIE_PORT_VC_STATUS                                                                  0x011e
+#define cfgBIFPLR2_PCIE_VC0_RESOURCE_CAP                                                                0x0120
+#define cfgBIFPLR2_PCIE_VC0_RESOURCE_CNTL                                                               0x0124
+#define cfgBIFPLR2_PCIE_VC0_RESOURCE_STATUS                                                             0x012a
+#define cfgBIFPLR2_PCIE_VC1_RESOURCE_CAP                                                                0x012c
+#define cfgBIFPLR2_PCIE_VC1_RESOURCE_CNTL                                                               0x0130
+#define cfgBIFPLR2_PCIE_VC1_RESOURCE_STATUS                                                             0x0136
+#define cfgBIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                     0x0140
+#define cfgBIFPLR2_PCIE_DEV_SERIAL_NUM_DW1                                                              0x0144
+#define cfgBIFPLR2_PCIE_DEV_SERIAL_NUM_DW2                                                              0x0148
+#define cfgBIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                        0x0150
+#define cfgBIFPLR2_PCIE_UNCORR_ERR_STATUS                                                               0x0154
+#define cfgBIFPLR2_PCIE_UNCORR_ERR_MASK                                                                 0x0158
+#define cfgBIFPLR2_PCIE_UNCORR_ERR_SEVERITY                                                             0x015c
+#define cfgBIFPLR2_PCIE_CORR_ERR_STATUS                                                                 0x0160
+#define cfgBIFPLR2_PCIE_CORR_ERR_MASK                                                                   0x0164
+#define cfgBIFPLR2_PCIE_ADV_ERR_CAP_CNTL                                                                0x0168
+#define cfgBIFPLR2_PCIE_HDR_LOG0                                                                        0x016c
+#define cfgBIFPLR2_PCIE_HDR_LOG1                                                                        0x0170
+#define cfgBIFPLR2_PCIE_HDR_LOG2                                                                        0x0174
+#define cfgBIFPLR2_PCIE_HDR_LOG3                                                                        0x0178
+#define cfgBIFPLR2_PCIE_ROOT_ERR_CMD                                                                    0x017c
+#define cfgBIFPLR2_PCIE_ROOT_ERR_STATUS                                                                 0x0180
+#define cfgBIFPLR2_PCIE_ERR_SRC_ID                                                                      0x0184
+#define cfgBIFPLR2_PCIE_TLP_PREFIX_LOG0                                                                 0x0188
+#define cfgBIFPLR2_PCIE_TLP_PREFIX_LOG1                                                                 0x018c
+#define cfgBIFPLR2_PCIE_TLP_PREFIX_LOG2                                                                 0x0190
+#define cfgBIFPLR2_PCIE_TLP_PREFIX_LOG3                                                                 0x0194
+#define cfgBIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST                                                          0x0270
+#define cfgBIFPLR2_PCIE_LINK_CNTL3                                                                      0x0274
+#define cfgBIFPLR2_PCIE_LANE_ERROR_STATUS                                                               0x0278
+#define cfgBIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL                                                        0x027c
+#define cfgBIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL                                                        0x027e
+#define cfgBIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL                                                        0x0280
+#define cfgBIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL                                                        0x0282
+#define cfgBIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL                                                        0x0284
+#define cfgBIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL                                                        0x0286
+#define cfgBIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL                                                        0x0288
+#define cfgBIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL                                                        0x028a
+#define cfgBIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL                                                        0x028c
+#define cfgBIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL                                                        0x028e
+#define cfgBIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL                                                       0x0290
+#define cfgBIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL                                                       0x0292
+#define cfgBIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL                                                       0x0294
+#define cfgBIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL                                                       0x0296
+#define cfgBIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL                                                       0x0298
+#define cfgBIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL                                                       0x029a
+#define cfgBIFPLR2_PCIE_ACS_ENH_CAP_LIST                                                                0x02a0
+#define cfgBIFPLR2_PCIE_ACS_CAP                                                                         0x02a4
+#define cfgBIFPLR2_PCIE_ACS_CNTL                                                                        0x02a6
+#define cfgBIFPLR2_PCIE_MC_ENH_CAP_LIST                                                                 0x02f0
+#define cfgBIFPLR2_PCIE_MC_CAP                                                                          0x02f4
+#define cfgBIFPLR2_PCIE_MC_CNTL                                                                         0x02f6
+#define cfgBIFPLR2_PCIE_MC_ADDR0                                                                        0x02f8
+#define cfgBIFPLR2_PCIE_MC_ADDR1                                                                        0x02fc
+#define cfgBIFPLR2_PCIE_MC_RCV0                                                                         0x0300
+#define cfgBIFPLR2_PCIE_MC_RCV1                                                                         0x0304
+#define cfgBIFPLR2_PCIE_MC_BLOCK_ALL0                                                                   0x0308
+#define cfgBIFPLR2_PCIE_MC_BLOCK_ALL1                                                                   0x030c
+#define cfgBIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_0                                                         0x0310
+#define cfgBIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_1                                                         0x0314
+#define cfgBIFPLR2_PCIE_MC_OVERLAY_BAR0                                                                 0x0318
+#define cfgBIFPLR2_PCIE_MC_OVERLAY_BAR1                                                                 0x031c
+#define cfgBIFPLR2_PCIE_L1_PM_SUB_CAP_LIST                                                              0x0370
+#define cfgBIFPLR2_PCIE_L1_PM_SUB_CAP                                                                   0x0374
+#define cfgBIFPLR2_PCIE_L1_PM_SUB_CNTL                                                                  0x0378
+#define cfgBIFPLR2_PCIE_L1_PM_SUB_CNTL2                                                                 0x037c
+#define cfgBIFPLR2_PCIE_DPC_ENH_CAP_LIST                                                                0x0380
+#define cfgBIFPLR2_PCIE_DPC_CAP_LIST                                                                    0x0384
+#define cfgBIFPLR2_PCIE_DPC_CNTL                                                                        0x0386
+#define cfgBIFPLR2_PCIE_DPC_STATUS                                                                      0x0388
+#define cfgBIFPLR2_PCIE_DPC_ERROR_SOURCE_ID                                                             0x038a
+#define cfgBIFPLR2_PCIE_RP_PIO_STATUS                                                                   0x038c
+#define cfgBIFPLR2_PCIE_RP_PIO_MASK                                                                     0x0390
+#define cfgBIFPLR2_PCIE_RP_PIO_SEVERITY                                                                 0x0394
+#define cfgBIFPLR2_PCIE_RP_PIO_SYSERROR                                                                 0x0398
+#define cfgBIFPLR2_PCIE_RP_PIO_EXCEPTION                                                                0x039c
+#define cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG0                                                                 0x03a0
+#define cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG1                                                                 0x03a4
+#define cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG2                                                                 0x03a8
+#define cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG3                                                                 0x03ac
+#define cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG0                                                              0x03b4
+#define cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG1                                                              0x03b8
+#define cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG2                                                              0x03bc
+#define cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG3                                                              0x03c0
+#define cfgBIFPLR2_PCIE_ESM_CAP_LIST                                                                    0x03c4
+#define cfgBIFPLR2_PCIE_ESM_HEADER_1                                                                    0x03c8
+#define cfgBIFPLR2_PCIE_ESM_HEADER_2                                                                    0x03cc
+#define cfgBIFPLR2_PCIE_ESM_STATUS                                                                      0x03ce
+#define cfgBIFPLR2_PCIE_ESM_CTRL                                                                        0x03d0
+#define cfgBIFPLR2_PCIE_ESM_CAP_1                                                                       0x03d4
+#define cfgBIFPLR2_PCIE_ESM_CAP_2                                                                       0x03d8
+#define cfgBIFPLR2_PCIE_ESM_CAP_3                                                                       0x03dc
+#define cfgBIFPLR2_PCIE_ESM_CAP_4                                                                       0x03e0
+#define cfgBIFPLR2_PCIE_ESM_CAP_5                                                                       0x03e4
+#define cfgBIFPLR2_PCIE_ESM_CAP_6                                                                       0x03e8
+#define cfgBIFPLR2_PCIE_ESM_CAP_7                                                                       0x03ec
+#define cfgBIFPLR2_PCIE_DLF_ENH_CAP_LIST                                                                0x0400
+#define cfgBIFPLR2_DATA_LINK_FEATURE_CAP                                                                0x0404
+#define cfgBIFPLR2_DATA_LINK_FEATURE_STATUS                                                             0x0408
+#define cfgBIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST                                                           0x0410
+#define cfgBIFPLR2_LINK_CAP_16GT                                                                        0x0414
+#define cfgBIFPLR2_LINK_CNTL_16GT                                                                       0x0418
+#define cfgBIFPLR2_LINK_STATUS_16GT                                                                     0x041c
+#define cfgBIFPLR2_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                    0x0420
+#define cfgBIFPLR2_RTM1_PARITY_MISMATCH_STATUS_16GT                                                     0x0424
+#define cfgBIFPLR2_RTM2_PARITY_MISMATCH_STATUS_16GT                                                     0x0428
+#define cfgBIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT                                                        0x0430
+#define cfgBIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT                                                        0x0431
+#define cfgBIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT                                                        0x0432
+#define cfgBIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT                                                        0x0433
+#define cfgBIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT                                                        0x0434
+#define cfgBIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT                                                        0x0435
+#define cfgBIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT                                                        0x0436
+#define cfgBIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT                                                        0x0437
+#define cfgBIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT                                                        0x0438
+#define cfgBIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT                                                        0x0439
+#define cfgBIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT                                                       0x043a
+#define cfgBIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT                                                       0x043b
+#define cfgBIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT                                                       0x043c
+#define cfgBIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT                                                       0x043d
+#define cfgBIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT                                                       0x043e
+#define cfgBIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT                                                       0x043f
+#define cfgBIFPLR2_PCIE_MARGINING_ENH_CAP_LIST                                                          0x0440
+#define cfgBIFPLR2_MARGINING_PORT_CAP                                                                   0x0444
+#define cfgBIFPLR2_MARGINING_PORT_STATUS                                                                0x0446
+#define cfgBIFPLR2_LANE_0_MARGINING_LANE_CNTL                                                           0x0448
+#define cfgBIFPLR2_LANE_0_MARGINING_LANE_STATUS                                                         0x044a
+#define cfgBIFPLR2_LANE_1_MARGINING_LANE_CNTL                                                           0x044c
+#define cfgBIFPLR2_LANE_1_MARGINING_LANE_STATUS                                                         0x044e
+#define cfgBIFPLR2_LANE_2_MARGINING_LANE_CNTL                                                           0x0450
+#define cfgBIFPLR2_LANE_2_MARGINING_LANE_STATUS                                                         0x0452
+#define cfgBIFPLR2_LANE_3_MARGINING_LANE_CNTL                                                           0x0454
+#define cfgBIFPLR2_LANE_3_MARGINING_LANE_STATUS                                                         0x0456
+#define cfgBIFPLR2_LANE_4_MARGINING_LANE_CNTL                                                           0x0458
+#define cfgBIFPLR2_LANE_4_MARGINING_LANE_STATUS                                                         0x045a
+#define cfgBIFPLR2_LANE_5_MARGINING_LANE_CNTL                                                           0x045c
+#define cfgBIFPLR2_LANE_5_MARGINING_LANE_STATUS                                                         0x045e
+#define cfgBIFPLR2_LANE_6_MARGINING_LANE_CNTL                                                           0x0460
+#define cfgBIFPLR2_LANE_6_MARGINING_LANE_STATUS                                                         0x0462
+#define cfgBIFPLR2_LANE_7_MARGINING_LANE_CNTL                                                           0x0464
+#define cfgBIFPLR2_LANE_7_MARGINING_LANE_STATUS                                                         0x0466
+#define cfgBIFPLR2_LANE_8_MARGINING_LANE_CNTL                                                           0x0468
+#define cfgBIFPLR2_LANE_8_MARGINING_LANE_STATUS                                                         0x046a
+#define cfgBIFPLR2_LANE_9_MARGINING_LANE_CNTL                                                           0x046c
+#define cfgBIFPLR2_LANE_9_MARGINING_LANE_STATUS                                                         0x046e
+#define cfgBIFPLR2_LANE_10_MARGINING_LANE_CNTL                                                          0x0470
+#define cfgBIFPLR2_LANE_10_MARGINING_LANE_STATUS                                                        0x0472
+#define cfgBIFPLR2_LANE_11_MARGINING_LANE_CNTL                                                          0x0474
+#define cfgBIFPLR2_LANE_11_MARGINING_LANE_STATUS                                                        0x0476
+#define cfgBIFPLR2_LANE_12_MARGINING_LANE_CNTL                                                          0x0478
+#define cfgBIFPLR2_LANE_12_MARGINING_LANE_STATUS                                                        0x047a
+#define cfgBIFPLR2_LANE_13_MARGINING_LANE_CNTL                                                          0x047c
+#define cfgBIFPLR2_LANE_13_MARGINING_LANE_STATUS                                                        0x047e
+#define cfgBIFPLR2_LANE_14_MARGINING_LANE_CNTL                                                          0x0480
+#define cfgBIFPLR2_LANE_14_MARGINING_LANE_STATUS                                                        0x0482
+#define cfgBIFPLR2_LANE_15_MARGINING_LANE_CNTL                                                          0x0484
+#define cfgBIFPLR2_LANE_15_MARGINING_LANE_STATUS                                                        0x0486
+#define cfgBIFPLR2_PCIE_CCIX_CAP_LIST                                                                   0x0488
+#define cfgBIFPLR2_PCIE_CCIX_HEADER_1                                                                   0x048c
+#define cfgBIFPLR2_PCIE_CCIX_HEADER_2                                                                   0x0490
+#define cfgBIFPLR2_PCIE_CCIX_CAP                                                                        0x0492
+#define cfgBIFPLR2_PCIE_CCIX_ESM_REQD_CAP                                                               0x0494
+#define cfgBIFPLR2_PCIE_CCIX_ESM_OPTL_CAP                                                               0x0498
+#define cfgBIFPLR2_PCIE_CCIX_ESM_STATUS                                                                 0x049c
+#define cfgBIFPLR2_PCIE_CCIX_ESM_CNTL                                                                   0x04a0
+#define cfgBIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                    0x04a4
+#define cfgBIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                    0x04a5
+#define cfgBIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                    0x04a6
+#define cfgBIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                    0x04a7
+#define cfgBIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                    0x04a8
+#define cfgBIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                    0x04a9
+#define cfgBIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                    0x04aa
+#define cfgBIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                    0x04ab
+#define cfgBIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                    0x04ac
+#define cfgBIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                    0x04ad
+#define cfgBIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                   0x04ae
+#define cfgBIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                   0x04af
+#define cfgBIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                   0x04b0
+#define cfgBIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                   0x04b1
+#define cfgBIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                   0x04b2
+#define cfgBIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                   0x04b3
+#define cfgBIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                    0x04b4
+#define cfgBIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                    0x04b5
+#define cfgBIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                    0x04b6
+#define cfgBIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                    0x04b7
+#define cfgBIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                    0x04b8
+#define cfgBIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                    0x04b9
+#define cfgBIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                    0x04ba
+#define cfgBIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                    0x04bb
+#define cfgBIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                    0x04bc
+#define cfgBIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                    0x04bd
+#define cfgBIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                   0x04be
+#define cfgBIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                   0x04bf
+#define cfgBIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                   0x04c0
+#define cfgBIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                   0x04c1
+#define cfgBIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                   0x04c2
+#define cfgBIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                   0x04c3
+#define cfgBIFPLR2_PCIE_CCIX_TRANS_CAP                                                                  0x04c4
+#define cfgBIFPLR2_PCIE_CCIX_TRANS_CNTL                                                                 0x04c8
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+// base address: 0x0
+#define cfgBIFPLR3_VENDOR_ID                                                                            0x0000
+#define cfgBIFPLR3_DEVICE_ID                                                                            0x0002
+#define cfgBIFPLR3_COMMAND                                                                              0x0004
+#define cfgBIFPLR3_STATUS                                                                               0x0006
+#define cfgBIFPLR3_REVISION_ID                                                                          0x0008
+#define cfgBIFPLR3_PROG_INTERFACE                                                                       0x0009
+#define cfgBIFPLR3_SUB_CLASS                                                                            0x000a
+#define cfgBIFPLR3_BASE_CLASS                                                                           0x000b
+#define cfgBIFPLR3_CACHE_LINE                                                                           0x000c
+#define cfgBIFPLR3_LATENCY                                                                              0x000d
+#define cfgBIFPLR3_HEADER                                                                               0x000e
+#define cfgBIFPLR3_BIST                                                                                 0x000f
+#define cfgBIFPLR3_SUB_BUS_NUMBER_LATENCY                                                               0x0018
+#define cfgBIFPLR3_IO_BASE_LIMIT                                                                        0x001c
+#define cfgBIFPLR3_SECONDARY_STATUS                                                                     0x001e
+#define cfgBIFPLR3_MEM_BASE_LIMIT                                                                       0x0020
+#define cfgBIFPLR3_PREF_BASE_LIMIT                                                                      0x0024
+#define cfgBIFPLR3_PREF_BASE_UPPER                                                                      0x0028
+#define cfgBIFPLR3_PREF_LIMIT_UPPER                                                                     0x002c
+#define cfgBIFPLR3_IO_BASE_LIMIT_HI                                                                     0x0030
+#define cfgBIFPLR3_CAP_PTR                                                                              0x0034
+#define cfgBIFPLR3_ROM_BASE_ADDR                                                                        0x0038
+#define cfgBIFPLR3_INTERRUPT_LINE                                                                       0x003c
+#define cfgBIFPLR3_INTERRUPT_PIN                                                                        0x003d
+#define cfgBIFPLR3_IRQ_BRIDGE_CNTL                                                                      0x003e
+#define cfgBIFPLR3_EXT_BRIDGE_CNTL                                                                      0x0040
+#define cfgBIFPLR3_VENDOR_CAP_LIST                                                                      0x0048
+#define cfgBIFPLR3_ADAPTER_ID_W                                                                         0x004c
+#define cfgBIFPLR3_PMI_CAP_LIST                                                                         0x0050
+#define cfgBIFPLR3_PMI_CAP                                                                              0x0052
+#define cfgBIFPLR3_PMI_STATUS_CNTL                                                                      0x0054
+#define cfgBIFPLR3_PCIE_CAP_LIST                                                                        0x0058
+#define cfgBIFPLR3_PCIE_CAP                                                                             0x005a
+#define cfgBIFPLR3_DEVICE_CAP                                                                           0x005c
+#define cfgBIFPLR3_DEVICE_CNTL                                                                          0x0060
+#define cfgBIFPLR3_DEVICE_STATUS                                                                        0x0062
+#define cfgBIFPLR3_LINK_CAP                                                                             0x0064
+#define cfgBIFPLR3_LINK_CNTL                                                                            0x0068
+#define cfgBIFPLR3_LINK_STATUS                                                                          0x006a
+#define cfgBIFPLR3_SLOT_CAP                                                                             0x006c
+#define cfgBIFPLR3_SLOT_CNTL                                                                            0x0070
+#define cfgBIFPLR3_SLOT_STATUS                                                                          0x0072
+#define cfgBIFPLR3_ROOT_CNTL                                                                            0x0074
+#define cfgBIFPLR3_ROOT_CAP                                                                             0x0076
+#define cfgBIFPLR3_ROOT_STATUS                                                                          0x0078
+#define cfgBIFPLR3_DEVICE_CAP2                                                                          0x007c
+#define cfgBIFPLR3_DEVICE_CNTL2                                                                         0x0080
+#define cfgBIFPLR3_DEVICE_STATUS2                                                                       0x0082
+#define cfgBIFPLR3_LINK_CAP2                                                                            0x0084
+#define cfgBIFPLR3_LINK_CNTL2                                                                           0x0088
+#define cfgBIFPLR3_LINK_STATUS2                                                                         0x008a
+#define cfgBIFPLR3_SLOT_CAP2                                                                            0x008c
+#define cfgBIFPLR3_SLOT_CNTL2                                                                           0x0090
+#define cfgBIFPLR3_SLOT_STATUS2                                                                         0x0092
+#define cfgBIFPLR3_MSI_CAP_LIST                                                                         0x00a0
+#define cfgBIFPLR3_MSI_MSG_CNTL                                                                         0x00a2
+#define cfgBIFPLR3_MSI_MSG_ADDR_LO                                                                      0x00a4
+#define cfgBIFPLR3_MSI_MSG_ADDR_HI                                                                      0x00a8
+#define cfgBIFPLR3_MSI_MSG_DATA                                                                         0x00a8
+#define cfgBIFPLR3_MSI_MSG_DATA_64                                                                      0x00ac
+#define cfgBIFPLR3_SSID_CAP_LIST                                                                        0x00c0
+#define cfgBIFPLR3_SSID_CAP                                                                             0x00c4
+#define cfgBIFPLR3_MSI_MAP_CAP_LIST                                                                     0x00c8
+#define cfgBIFPLR3_MSI_MAP_CAP                                                                          0x00ca
+#define cfgBIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                    0x0100
+#define cfgBIFPLR3_PCIE_VENDOR_SPECIFIC_HDR                                                             0x0104
+#define cfgBIFPLR3_PCIE_VENDOR_SPECIFIC1                                                                0x0108
+#define cfgBIFPLR3_PCIE_VENDOR_SPECIFIC2                                                                0x010c
+#define cfgBIFPLR3_PCIE_VC_ENH_CAP_LIST                                                                 0x0110
+#define cfgBIFPLR3_PCIE_PORT_VC_CAP_REG1                                                                0x0114
+#define cfgBIFPLR3_PCIE_PORT_VC_CAP_REG2                                                                0x0118
+#define cfgBIFPLR3_PCIE_PORT_VC_CNTL                                                                    0x011c
+#define cfgBIFPLR3_PCIE_PORT_VC_STATUS                                                                  0x011e
+#define cfgBIFPLR3_PCIE_VC0_RESOURCE_CAP                                                                0x0120
+#define cfgBIFPLR3_PCIE_VC0_RESOURCE_CNTL                                                               0x0124
+#define cfgBIFPLR3_PCIE_VC0_RESOURCE_STATUS                                                             0x012a
+#define cfgBIFPLR3_PCIE_VC1_RESOURCE_CAP                                                                0x012c
+#define cfgBIFPLR3_PCIE_VC1_RESOURCE_CNTL                                                               0x0130
+#define cfgBIFPLR3_PCIE_VC1_RESOURCE_STATUS                                                             0x0136
+#define cfgBIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                     0x0140
+#define cfgBIFPLR3_PCIE_DEV_SERIAL_NUM_DW1                                                              0x0144
+#define cfgBIFPLR3_PCIE_DEV_SERIAL_NUM_DW2                                                              0x0148
+#define cfgBIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                        0x0150
+#define cfgBIFPLR3_PCIE_UNCORR_ERR_STATUS                                                               0x0154
+#define cfgBIFPLR3_PCIE_UNCORR_ERR_MASK                                                                 0x0158
+#define cfgBIFPLR3_PCIE_UNCORR_ERR_SEVERITY                                                             0x015c
+#define cfgBIFPLR3_PCIE_CORR_ERR_STATUS                                                                 0x0160
+#define cfgBIFPLR3_PCIE_CORR_ERR_MASK                                                                   0x0164
+#define cfgBIFPLR3_PCIE_ADV_ERR_CAP_CNTL                                                                0x0168
+#define cfgBIFPLR3_PCIE_HDR_LOG0                                                                        0x016c
+#define cfgBIFPLR3_PCIE_HDR_LOG1                                                                        0x0170
+#define cfgBIFPLR3_PCIE_HDR_LOG2                                                                        0x0174
+#define cfgBIFPLR3_PCIE_HDR_LOG3                                                                        0x0178
+#define cfgBIFPLR3_PCIE_ROOT_ERR_CMD                                                                    0x017c
+#define cfgBIFPLR3_PCIE_ROOT_ERR_STATUS                                                                 0x0180
+#define cfgBIFPLR3_PCIE_ERR_SRC_ID                                                                      0x0184
+#define cfgBIFPLR3_PCIE_TLP_PREFIX_LOG0                                                                 0x0188
+#define cfgBIFPLR3_PCIE_TLP_PREFIX_LOG1                                                                 0x018c
+#define cfgBIFPLR3_PCIE_TLP_PREFIX_LOG2                                                                 0x0190
+#define cfgBIFPLR3_PCIE_TLP_PREFIX_LOG3                                                                 0x0194
+#define cfgBIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST                                                          0x0270
+#define cfgBIFPLR3_PCIE_LINK_CNTL3                                                                      0x0274
+#define cfgBIFPLR3_PCIE_LANE_ERROR_STATUS                                                               0x0278
+#define cfgBIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL                                                        0x027c
+#define cfgBIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL                                                        0x027e
+#define cfgBIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL                                                        0x0280
+#define cfgBIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL                                                        0x0282
+#define cfgBIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL                                                        0x0284
+#define cfgBIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL                                                        0x0286
+#define cfgBIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL                                                        0x0288
+#define cfgBIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL                                                        0x028a
+#define cfgBIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL                                                        0x028c
+#define cfgBIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL                                                        0x028e
+#define cfgBIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL                                                       0x0290
+#define cfgBIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL                                                       0x0292
+#define cfgBIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL                                                       0x0294
+#define cfgBIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL                                                       0x0296
+#define cfgBIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL                                                       0x0298
+#define cfgBIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL                                                       0x029a
+#define cfgBIFPLR3_PCIE_ACS_ENH_CAP_LIST                                                                0x02a0
+#define cfgBIFPLR3_PCIE_ACS_CAP                                                                         0x02a4
+#define cfgBIFPLR3_PCIE_ACS_CNTL                                                                        0x02a6
+#define cfgBIFPLR3_PCIE_MC_ENH_CAP_LIST                                                                 0x02f0
+#define cfgBIFPLR3_PCIE_MC_CAP                                                                          0x02f4
+#define cfgBIFPLR3_PCIE_MC_CNTL                                                                         0x02f6
+#define cfgBIFPLR3_PCIE_MC_ADDR0                                                                        0x02f8
+#define cfgBIFPLR3_PCIE_MC_ADDR1                                                                        0x02fc
+#define cfgBIFPLR3_PCIE_MC_RCV0                                                                         0x0300
+#define cfgBIFPLR3_PCIE_MC_RCV1                                                                         0x0304
+#define cfgBIFPLR3_PCIE_MC_BLOCK_ALL0                                                                   0x0308
+#define cfgBIFPLR3_PCIE_MC_BLOCK_ALL1                                                                   0x030c
+#define cfgBIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_0                                                         0x0310
+#define cfgBIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_1                                                         0x0314
+#define cfgBIFPLR3_PCIE_MC_OVERLAY_BAR0                                                                 0x0318
+#define cfgBIFPLR3_PCIE_MC_OVERLAY_BAR1                                                                 0x031c
+#define cfgBIFPLR3_PCIE_L1_PM_SUB_CAP_LIST                                                              0x0370
+#define cfgBIFPLR3_PCIE_L1_PM_SUB_CAP                                                                   0x0374
+#define cfgBIFPLR3_PCIE_L1_PM_SUB_CNTL                                                                  0x0378
+#define cfgBIFPLR3_PCIE_L1_PM_SUB_CNTL2                                                                 0x037c
+#define cfgBIFPLR3_PCIE_DPC_ENH_CAP_LIST                                                                0x0380
+#define cfgBIFPLR3_PCIE_DPC_CAP_LIST                                                                    0x0384
+#define cfgBIFPLR3_PCIE_DPC_CNTL                                                                        0x0386
+#define cfgBIFPLR3_PCIE_DPC_STATUS                                                                      0x0388
+#define cfgBIFPLR3_PCIE_DPC_ERROR_SOURCE_ID                                                             0x038a
+#define cfgBIFPLR3_PCIE_RP_PIO_STATUS                                                                   0x038c
+#define cfgBIFPLR3_PCIE_RP_PIO_MASK                                                                     0x0390
+#define cfgBIFPLR3_PCIE_RP_PIO_SEVERITY                                                                 0x0394
+#define cfgBIFPLR3_PCIE_RP_PIO_SYSERROR                                                                 0x0398
+#define cfgBIFPLR3_PCIE_RP_PIO_EXCEPTION                                                                0x039c
+#define cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG0                                                                 0x03a0
+#define cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG1                                                                 0x03a4
+#define cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG2                                                                 0x03a8
+#define cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG3                                                                 0x03ac
+#define cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG0                                                              0x03b4
+#define cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG1                                                              0x03b8
+#define cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG2                                                              0x03bc
+#define cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG3                                                              0x03c0
+#define cfgBIFPLR3_PCIE_ESM_CAP_LIST                                                                    0x03c4
+#define cfgBIFPLR3_PCIE_ESM_HEADER_1                                                                    0x03c8
+#define cfgBIFPLR3_PCIE_ESM_HEADER_2                                                                    0x03cc
+#define cfgBIFPLR3_PCIE_ESM_STATUS                                                                      0x03ce
+#define cfgBIFPLR3_PCIE_ESM_CTRL                                                                        0x03d0
+#define cfgBIFPLR3_PCIE_ESM_CAP_1                                                                       0x03d4
+#define cfgBIFPLR3_PCIE_ESM_CAP_2                                                                       0x03d8
+#define cfgBIFPLR3_PCIE_ESM_CAP_3                                                                       0x03dc
+#define cfgBIFPLR3_PCIE_ESM_CAP_4                                                                       0x03e0
+#define cfgBIFPLR3_PCIE_ESM_CAP_5                                                                       0x03e4
+#define cfgBIFPLR3_PCIE_ESM_CAP_6                                                                       0x03e8
+#define cfgBIFPLR3_PCIE_ESM_CAP_7                                                                       0x03ec
+#define cfgBIFPLR3_PCIE_DLF_ENH_CAP_LIST                                                                0x0400
+#define cfgBIFPLR3_DATA_LINK_FEATURE_CAP                                                                0x0404
+#define cfgBIFPLR3_DATA_LINK_FEATURE_STATUS                                                             0x0408
+#define cfgBIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST                                                           0x0410
+#define cfgBIFPLR3_LINK_CAP_16GT                                                                        0x0414
+#define cfgBIFPLR3_LINK_CNTL_16GT                                                                       0x0418
+#define cfgBIFPLR3_LINK_STATUS_16GT                                                                     0x041c
+#define cfgBIFPLR3_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                    0x0420
+#define cfgBIFPLR3_RTM1_PARITY_MISMATCH_STATUS_16GT                                                     0x0424
+#define cfgBIFPLR3_RTM2_PARITY_MISMATCH_STATUS_16GT                                                     0x0428
+#define cfgBIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT                                                        0x0430
+#define cfgBIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT                                                        0x0431
+#define cfgBIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT                                                        0x0432
+#define cfgBIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT                                                        0x0433
+#define cfgBIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT                                                        0x0434
+#define cfgBIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT                                                        0x0435
+#define cfgBIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT                                                        0x0436
+#define cfgBIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT                                                        0x0437
+#define cfgBIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT                                                        0x0438
+#define cfgBIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT                                                        0x0439
+#define cfgBIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT                                                       0x043a
+#define cfgBIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT                                                       0x043b
+#define cfgBIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT                                                       0x043c
+#define cfgBIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT                                                       0x043d
+#define cfgBIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT                                                       0x043e
+#define cfgBIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT                                                       0x043f
+#define cfgBIFPLR3_PCIE_MARGINING_ENH_CAP_LIST                                                          0x0440
+#define cfgBIFPLR3_MARGINING_PORT_CAP                                                                   0x0444
+#define cfgBIFPLR3_MARGINING_PORT_STATUS                                                                0x0446
+#define cfgBIFPLR3_LANE_0_MARGINING_LANE_CNTL                                                           0x0448
+#define cfgBIFPLR3_LANE_0_MARGINING_LANE_STATUS                                                         0x044a
+#define cfgBIFPLR3_LANE_1_MARGINING_LANE_CNTL                                                           0x044c
+#define cfgBIFPLR3_LANE_1_MARGINING_LANE_STATUS                                                         0x044e
+#define cfgBIFPLR3_LANE_2_MARGINING_LANE_CNTL                                                           0x0450
+#define cfgBIFPLR3_LANE_2_MARGINING_LANE_STATUS                                                         0x0452
+#define cfgBIFPLR3_LANE_3_MARGINING_LANE_CNTL                                                           0x0454
+#define cfgBIFPLR3_LANE_3_MARGINING_LANE_STATUS                                                         0x0456
+#define cfgBIFPLR3_LANE_4_MARGINING_LANE_CNTL                                                           0x0458
+#define cfgBIFPLR3_LANE_4_MARGINING_LANE_STATUS                                                         0x045a
+#define cfgBIFPLR3_LANE_5_MARGINING_LANE_CNTL                                                           0x045c
+#define cfgBIFPLR3_LANE_5_MARGINING_LANE_STATUS                                                         0x045e
+#define cfgBIFPLR3_LANE_6_MARGINING_LANE_CNTL                                                           0x0460
+#define cfgBIFPLR3_LANE_6_MARGINING_LANE_STATUS                                                         0x0462
+#define cfgBIFPLR3_LANE_7_MARGINING_LANE_CNTL                                                           0x0464
+#define cfgBIFPLR3_LANE_7_MARGINING_LANE_STATUS                                                         0x0466
+#define cfgBIFPLR3_LANE_8_MARGINING_LANE_CNTL                                                           0x0468
+#define cfgBIFPLR3_LANE_8_MARGINING_LANE_STATUS                                                         0x046a
+#define cfgBIFPLR3_LANE_9_MARGINING_LANE_CNTL                                                           0x046c
+#define cfgBIFPLR3_LANE_9_MARGINING_LANE_STATUS                                                         0x046e
+#define cfgBIFPLR3_LANE_10_MARGINING_LANE_CNTL                                                          0x0470
+#define cfgBIFPLR3_LANE_10_MARGINING_LANE_STATUS                                                        0x0472
+#define cfgBIFPLR3_LANE_11_MARGINING_LANE_CNTL                                                          0x0474
+#define cfgBIFPLR3_LANE_11_MARGINING_LANE_STATUS                                                        0x0476
+#define cfgBIFPLR3_LANE_12_MARGINING_LANE_CNTL                                                          0x0478
+#define cfgBIFPLR3_LANE_12_MARGINING_LANE_STATUS                                                        0x047a
+#define cfgBIFPLR3_LANE_13_MARGINING_LANE_CNTL                                                          0x047c
+#define cfgBIFPLR3_LANE_13_MARGINING_LANE_STATUS                                                        0x047e
+#define cfgBIFPLR3_LANE_14_MARGINING_LANE_CNTL                                                          0x0480
+#define cfgBIFPLR3_LANE_14_MARGINING_LANE_STATUS                                                        0x0482
+#define cfgBIFPLR3_LANE_15_MARGINING_LANE_CNTL                                                          0x0484
+#define cfgBIFPLR3_LANE_15_MARGINING_LANE_STATUS                                                        0x0486
+#define cfgBIFPLR3_PCIE_CCIX_CAP_LIST                                                                   0x0488
+#define cfgBIFPLR3_PCIE_CCIX_HEADER_1                                                                   0x048c
+#define cfgBIFPLR3_PCIE_CCIX_HEADER_2                                                                   0x0490
+#define cfgBIFPLR3_PCIE_CCIX_CAP                                                                        0x0492
+#define cfgBIFPLR3_PCIE_CCIX_ESM_REQD_CAP                                                               0x0494
+#define cfgBIFPLR3_PCIE_CCIX_ESM_OPTL_CAP                                                               0x0498
+#define cfgBIFPLR3_PCIE_CCIX_ESM_STATUS                                                                 0x049c
+#define cfgBIFPLR3_PCIE_CCIX_ESM_CNTL                                                                   0x04a0
+#define cfgBIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                    0x04a4
+#define cfgBIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                    0x04a5
+#define cfgBIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                    0x04a6
+#define cfgBIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                    0x04a7
+#define cfgBIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                    0x04a8
+#define cfgBIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                    0x04a9
+#define cfgBIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                    0x04aa
+#define cfgBIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                    0x04ab
+#define cfgBIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                    0x04ac
+#define cfgBIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                    0x04ad
+#define cfgBIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                   0x04ae
+#define cfgBIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                   0x04af
+#define cfgBIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                   0x04b0
+#define cfgBIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                   0x04b1
+#define cfgBIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                   0x04b2
+#define cfgBIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                   0x04b3
+#define cfgBIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                    0x04b4
+#define cfgBIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                    0x04b5
+#define cfgBIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                    0x04b6
+#define cfgBIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                    0x04b7
+#define cfgBIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                    0x04b8
+#define cfgBIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                    0x04b9
+#define cfgBIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                    0x04ba
+#define cfgBIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                    0x04bb
+#define cfgBIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                    0x04bc
+#define cfgBIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                    0x04bd
+#define cfgBIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                   0x04be
+#define cfgBIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                   0x04bf
+#define cfgBIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                   0x04c0
+#define cfgBIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                   0x04c1
+#define cfgBIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                   0x04c2
+#define cfgBIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                   0x04c3
+#define cfgBIFPLR3_PCIE_CCIX_TRANS_CAP                                                                  0x04c4
+#define cfgBIFPLR3_PCIE_CCIX_TRANS_CNTL                                                                 0x04c8
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+// base address: 0x0
+#define cfgBIFPLR4_VENDOR_ID                                                                            0x0000
+#define cfgBIFPLR4_DEVICE_ID                                                                            0x0002
+#define cfgBIFPLR4_COMMAND                                                                              0x0004
+#define cfgBIFPLR4_STATUS                                                                               0x0006
+#define cfgBIFPLR4_REVISION_ID                                                                          0x0008
+#define cfgBIFPLR4_PROG_INTERFACE                                                                       0x0009
+#define cfgBIFPLR4_SUB_CLASS                                                                            0x000a
+#define cfgBIFPLR4_BASE_CLASS                                                                           0x000b
+#define cfgBIFPLR4_CACHE_LINE                                                                           0x000c
+#define cfgBIFPLR4_LATENCY                                                                              0x000d
+#define cfgBIFPLR4_HEADER                                                                               0x000e
+#define cfgBIFPLR4_BIST                                                                                 0x000f
+#define cfgBIFPLR4_SUB_BUS_NUMBER_LATENCY                                                               0x0018
+#define cfgBIFPLR4_IO_BASE_LIMIT                                                                        0x001c
+#define cfgBIFPLR4_SECONDARY_STATUS                                                                     0x001e
+#define cfgBIFPLR4_MEM_BASE_LIMIT                                                                       0x0020
+#define cfgBIFPLR4_PREF_BASE_LIMIT                                                                      0x0024
+#define cfgBIFPLR4_PREF_BASE_UPPER                                                                      0x0028
+#define cfgBIFPLR4_PREF_LIMIT_UPPER                                                                     0x002c
+#define cfgBIFPLR4_IO_BASE_LIMIT_HI                                                                     0x0030
+#define cfgBIFPLR4_CAP_PTR                                                                              0x0034
+#define cfgBIFPLR4_ROM_BASE_ADDR                                                                        0x0038
+#define cfgBIFPLR4_INTERRUPT_LINE                                                                       0x003c
+#define cfgBIFPLR4_INTERRUPT_PIN                                                                        0x003d
+#define cfgBIFPLR4_IRQ_BRIDGE_CNTL                                                                      0x003e
+#define cfgBIFPLR4_EXT_BRIDGE_CNTL                                                                      0x0040
+#define cfgBIFPLR4_VENDOR_CAP_LIST                                                                      0x0048
+#define cfgBIFPLR4_ADAPTER_ID_W                                                                         0x004c
+#define cfgBIFPLR4_PMI_CAP_LIST                                                                         0x0050
+#define cfgBIFPLR4_PMI_CAP                                                                              0x0052
+#define cfgBIFPLR4_PMI_STATUS_CNTL                                                                      0x0054
+#define cfgBIFPLR4_PCIE_CAP_LIST                                                                        0x0058
+#define cfgBIFPLR4_PCIE_CAP                                                                             0x005a
+#define cfgBIFPLR4_DEVICE_CAP                                                                           0x005c
+#define cfgBIFPLR4_DEVICE_CNTL                                                                          0x0060
+#define cfgBIFPLR4_DEVICE_STATUS                                                                        0x0062
+#define cfgBIFPLR4_LINK_CAP                                                                             0x0064
+#define cfgBIFPLR4_LINK_CNTL                                                                            0x0068
+#define cfgBIFPLR4_LINK_STATUS                                                                          0x006a
+#define cfgBIFPLR4_SLOT_CAP                                                                             0x006c
+#define cfgBIFPLR4_SLOT_CNTL                                                                            0x0070
+#define cfgBIFPLR4_SLOT_STATUS                                                                          0x0072
+#define cfgBIFPLR4_ROOT_CNTL                                                                            0x0074
+#define cfgBIFPLR4_ROOT_CAP                                                                             0x0076
+#define cfgBIFPLR4_ROOT_STATUS                                                                          0x0078
+#define cfgBIFPLR4_DEVICE_CAP2                                                                          0x007c
+#define cfgBIFPLR4_DEVICE_CNTL2                                                                         0x0080
+#define cfgBIFPLR4_DEVICE_STATUS2                                                                       0x0082
+#define cfgBIFPLR4_LINK_CAP2                                                                            0x0084
+#define cfgBIFPLR4_LINK_CNTL2                                                                           0x0088
+#define cfgBIFPLR4_LINK_STATUS2                                                                         0x008a
+#define cfgBIFPLR4_SLOT_CAP2                                                                            0x008c
+#define cfgBIFPLR4_SLOT_CNTL2                                                                           0x0090
+#define cfgBIFPLR4_SLOT_STATUS2                                                                         0x0092
+#define cfgBIFPLR4_MSI_CAP_LIST                                                                         0x00a0
+#define cfgBIFPLR4_MSI_MSG_CNTL                                                                         0x00a2
+#define cfgBIFPLR4_MSI_MSG_ADDR_LO                                                                      0x00a4
+#define cfgBIFPLR4_MSI_MSG_ADDR_HI                                                                      0x00a8
+#define cfgBIFPLR4_MSI_MSG_DATA                                                                         0x00a8
+#define cfgBIFPLR4_MSI_MSG_DATA_64                                                                      0x00ac
+#define cfgBIFPLR4_SSID_CAP_LIST                                                                        0x00c0
+#define cfgBIFPLR4_SSID_CAP                                                                             0x00c4
+#define cfgBIFPLR4_MSI_MAP_CAP_LIST                                                                     0x00c8
+#define cfgBIFPLR4_MSI_MAP_CAP                                                                          0x00ca
+#define cfgBIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                    0x0100
+#define cfgBIFPLR4_PCIE_VENDOR_SPECIFIC_HDR                                                             0x0104
+#define cfgBIFPLR4_PCIE_VENDOR_SPECIFIC1                                                                0x0108
+#define cfgBIFPLR4_PCIE_VENDOR_SPECIFIC2                                                                0x010c
+#define cfgBIFPLR4_PCIE_VC_ENH_CAP_LIST                                                                 0x0110
+#define cfgBIFPLR4_PCIE_PORT_VC_CAP_REG1                                                                0x0114
+#define cfgBIFPLR4_PCIE_PORT_VC_CAP_REG2                                                                0x0118
+#define cfgBIFPLR4_PCIE_PORT_VC_CNTL                                                                    0x011c
+#define cfgBIFPLR4_PCIE_PORT_VC_STATUS                                                                  0x011e
+#define cfgBIFPLR4_PCIE_VC0_RESOURCE_CAP                                                                0x0120
+#define cfgBIFPLR4_PCIE_VC0_RESOURCE_CNTL                                                               0x0124
+#define cfgBIFPLR4_PCIE_VC0_RESOURCE_STATUS                                                             0x012a
+#define cfgBIFPLR4_PCIE_VC1_RESOURCE_CAP                                                                0x012c
+#define cfgBIFPLR4_PCIE_VC1_RESOURCE_CNTL                                                               0x0130
+#define cfgBIFPLR4_PCIE_VC1_RESOURCE_STATUS                                                             0x0136
+#define cfgBIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                     0x0140
+#define cfgBIFPLR4_PCIE_DEV_SERIAL_NUM_DW1                                                              0x0144
+#define cfgBIFPLR4_PCIE_DEV_SERIAL_NUM_DW2                                                              0x0148
+#define cfgBIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                        0x0150
+#define cfgBIFPLR4_PCIE_UNCORR_ERR_STATUS                                                               0x0154
+#define cfgBIFPLR4_PCIE_UNCORR_ERR_MASK                                                                 0x0158
+#define cfgBIFPLR4_PCIE_UNCORR_ERR_SEVERITY                                                             0x015c
+#define cfgBIFPLR4_PCIE_CORR_ERR_STATUS                                                                 0x0160
+#define cfgBIFPLR4_PCIE_CORR_ERR_MASK                                                                   0x0164
+#define cfgBIFPLR4_PCIE_ADV_ERR_CAP_CNTL                                                                0x0168
+#define cfgBIFPLR4_PCIE_HDR_LOG0                                                                        0x016c
+#define cfgBIFPLR4_PCIE_HDR_LOG1                                                                        0x0170
+#define cfgBIFPLR4_PCIE_HDR_LOG2                                                                        0x0174
+#define cfgBIFPLR4_PCIE_HDR_LOG3                                                                        0x0178
+#define cfgBIFPLR4_PCIE_ROOT_ERR_CMD                                                                    0x017c
+#define cfgBIFPLR4_PCIE_ROOT_ERR_STATUS                                                                 0x0180
+#define cfgBIFPLR4_PCIE_ERR_SRC_ID                                                                      0x0184
+#define cfgBIFPLR4_PCIE_TLP_PREFIX_LOG0                                                                 0x0188
+#define cfgBIFPLR4_PCIE_TLP_PREFIX_LOG1                                                                 0x018c
+#define cfgBIFPLR4_PCIE_TLP_PREFIX_LOG2                                                                 0x0190
+#define cfgBIFPLR4_PCIE_TLP_PREFIX_LOG3                                                                 0x0194
+#define cfgBIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST                                                          0x0270
+#define cfgBIFPLR4_PCIE_LINK_CNTL3                                                                      0x0274
+#define cfgBIFPLR4_PCIE_LANE_ERROR_STATUS                                                               0x0278
+#define cfgBIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL                                                        0x027c
+#define cfgBIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL                                                        0x027e
+#define cfgBIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL                                                        0x0280
+#define cfgBIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL                                                        0x0282
+#define cfgBIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL                                                        0x0284
+#define cfgBIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL                                                        0x0286
+#define cfgBIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL                                                        0x0288
+#define cfgBIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL                                                        0x028a
+#define cfgBIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL                                                        0x028c
+#define cfgBIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL                                                        0x028e
+#define cfgBIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL                                                       0x0290
+#define cfgBIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL                                                       0x0292
+#define cfgBIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL                                                       0x0294
+#define cfgBIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL                                                       0x0296
+#define cfgBIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL                                                       0x0298
+#define cfgBIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL                                                       0x029a
+#define cfgBIFPLR4_PCIE_ACS_ENH_CAP_LIST                                                                0x02a0
+#define cfgBIFPLR4_PCIE_ACS_CAP                                                                         0x02a4
+#define cfgBIFPLR4_PCIE_ACS_CNTL                                                                        0x02a6
+#define cfgBIFPLR4_PCIE_MC_ENH_CAP_LIST                                                                 0x02f0
+#define cfgBIFPLR4_PCIE_MC_CAP                                                                          0x02f4
+#define cfgBIFPLR4_PCIE_MC_CNTL                                                                         0x02f6
+#define cfgBIFPLR4_PCIE_MC_ADDR0                                                                        0x02f8
+#define cfgBIFPLR4_PCIE_MC_ADDR1                                                                        0x02fc
+#define cfgBIFPLR4_PCIE_MC_RCV0                                                                         0x0300
+#define cfgBIFPLR4_PCIE_MC_RCV1                                                                         0x0304
+#define cfgBIFPLR4_PCIE_MC_BLOCK_ALL0                                                                   0x0308
+#define cfgBIFPLR4_PCIE_MC_BLOCK_ALL1                                                                   0x030c
+#define cfgBIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_0                                                         0x0310
+#define cfgBIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_1                                                         0x0314
+#define cfgBIFPLR4_PCIE_MC_OVERLAY_BAR0                                                                 0x0318
+#define cfgBIFPLR4_PCIE_MC_OVERLAY_BAR1                                                                 0x031c
+#define cfgBIFPLR4_PCIE_L1_PM_SUB_CAP_LIST                                                              0x0370
+#define cfgBIFPLR4_PCIE_L1_PM_SUB_CAP                                                                   0x0374
+#define cfgBIFPLR4_PCIE_L1_PM_SUB_CNTL                                                                  0x0378
+#define cfgBIFPLR4_PCIE_L1_PM_SUB_CNTL2                                                                 0x037c
+#define cfgBIFPLR4_PCIE_DPC_ENH_CAP_LIST                                                                0x0380
+#define cfgBIFPLR4_PCIE_DPC_CAP_LIST                                                                    0x0384
+#define cfgBIFPLR4_PCIE_DPC_CNTL                                                                        0x0386
+#define cfgBIFPLR4_PCIE_DPC_STATUS                                                                      0x0388
+#define cfgBIFPLR4_PCIE_DPC_ERROR_SOURCE_ID                                                             0x038a
+#define cfgBIFPLR4_PCIE_RP_PIO_STATUS                                                                   0x038c
+#define cfgBIFPLR4_PCIE_RP_PIO_MASK                                                                     0x0390
+#define cfgBIFPLR4_PCIE_RP_PIO_SEVERITY                                                                 0x0394
+#define cfgBIFPLR4_PCIE_RP_PIO_SYSERROR                                                                 0x0398
+#define cfgBIFPLR4_PCIE_RP_PIO_EXCEPTION                                                                0x039c
+#define cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG0                                                                 0x03a0
+#define cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG1                                                                 0x03a4
+#define cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG2                                                                 0x03a8
+#define cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG3                                                                 0x03ac
+#define cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG0                                                              0x03b4
+#define cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG1                                                              0x03b8
+#define cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG2                                                              0x03bc
+#define cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG3                                                              0x03c0
+#define cfgBIFPLR4_PCIE_ESM_CAP_LIST                                                                    0x03c4
+#define cfgBIFPLR4_PCIE_ESM_HEADER_1                                                                    0x03c8
+#define cfgBIFPLR4_PCIE_ESM_HEADER_2                                                                    0x03cc
+#define cfgBIFPLR4_PCIE_ESM_STATUS                                                                      0x03ce
+#define cfgBIFPLR4_PCIE_ESM_CTRL                                                                        0x03d0
+#define cfgBIFPLR4_PCIE_ESM_CAP_1                                                                       0x03d4
+#define cfgBIFPLR4_PCIE_ESM_CAP_2                                                                       0x03d8
+#define cfgBIFPLR4_PCIE_ESM_CAP_3                                                                       0x03dc
+#define cfgBIFPLR4_PCIE_ESM_CAP_4                                                                       0x03e0
+#define cfgBIFPLR4_PCIE_ESM_CAP_5                                                                       0x03e4
+#define cfgBIFPLR4_PCIE_ESM_CAP_6                                                                       0x03e8
+#define cfgBIFPLR4_PCIE_ESM_CAP_7                                                                       0x03ec
+#define cfgBIFPLR4_PCIE_DLF_ENH_CAP_LIST                                                                0x0400
+#define cfgBIFPLR4_DATA_LINK_FEATURE_CAP                                                                0x0404
+#define cfgBIFPLR4_DATA_LINK_FEATURE_STATUS                                                             0x0408
+#define cfgBIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST                                                           0x0410
+#define cfgBIFPLR4_LINK_CAP_16GT                                                                        0x0414
+#define cfgBIFPLR4_LINK_CNTL_16GT                                                                       0x0418
+#define cfgBIFPLR4_LINK_STATUS_16GT                                                                     0x041c
+#define cfgBIFPLR4_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                    0x0420
+#define cfgBIFPLR4_RTM1_PARITY_MISMATCH_STATUS_16GT                                                     0x0424
+#define cfgBIFPLR4_RTM2_PARITY_MISMATCH_STATUS_16GT                                                     0x0428
+#define cfgBIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT                                                        0x0430
+#define cfgBIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT                                                        0x0431
+#define cfgBIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT                                                        0x0432
+#define cfgBIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT                                                        0x0433
+#define cfgBIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT                                                        0x0434
+#define cfgBIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT                                                        0x0435
+#define cfgBIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT                                                        0x0436
+#define cfgBIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT                                                        0x0437
+#define cfgBIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT                                                        0x0438
+#define cfgBIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT                                                        0x0439
+#define cfgBIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT                                                       0x043a
+#define cfgBIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT                                                       0x043b
+#define cfgBIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT                                                       0x043c
+#define cfgBIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT                                                       0x043d
+#define cfgBIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT                                                       0x043e
+#define cfgBIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT                                                       0x043f
+#define cfgBIFPLR4_PCIE_MARGINING_ENH_CAP_LIST                                                          0x0440
+#define cfgBIFPLR4_MARGINING_PORT_CAP                                                                   0x0444
+#define cfgBIFPLR4_MARGINING_PORT_STATUS                                                                0x0446
+#define cfgBIFPLR4_LANE_0_MARGINING_LANE_CNTL                                                           0x0448
+#define cfgBIFPLR4_LANE_0_MARGINING_LANE_STATUS                                                         0x044a
+#define cfgBIFPLR4_LANE_1_MARGINING_LANE_CNTL                                                           0x044c
+#define cfgBIFPLR4_LANE_1_MARGINING_LANE_STATUS                                                         0x044e
+#define cfgBIFPLR4_LANE_2_MARGINING_LANE_CNTL                                                           0x0450
+#define cfgBIFPLR4_LANE_2_MARGINING_LANE_STATUS                                                         0x0452
+#define cfgBIFPLR4_LANE_3_MARGINING_LANE_CNTL                                                           0x0454
+#define cfgBIFPLR4_LANE_3_MARGINING_LANE_STATUS                                                         0x0456
+#define cfgBIFPLR4_LANE_4_MARGINING_LANE_CNTL                                                           0x0458
+#define cfgBIFPLR4_LANE_4_MARGINING_LANE_STATUS                                                         0x045a
+#define cfgBIFPLR4_LANE_5_MARGINING_LANE_CNTL                                                           0x045c
+#define cfgBIFPLR4_LANE_5_MARGINING_LANE_STATUS                                                         0x045e
+#define cfgBIFPLR4_LANE_6_MARGINING_LANE_CNTL                                                           0x0460
+#define cfgBIFPLR4_LANE_6_MARGINING_LANE_STATUS                                                         0x0462
+#define cfgBIFPLR4_LANE_7_MARGINING_LANE_CNTL                                                           0x0464
+#define cfgBIFPLR4_LANE_7_MARGINING_LANE_STATUS                                                         0x0466
+#define cfgBIFPLR4_LANE_8_MARGINING_LANE_CNTL                                                           0x0468
+#define cfgBIFPLR4_LANE_8_MARGINING_LANE_STATUS                                                         0x046a
+#define cfgBIFPLR4_LANE_9_MARGINING_LANE_CNTL                                                           0x046c
+#define cfgBIFPLR4_LANE_9_MARGINING_LANE_STATUS                                                         0x046e
+#define cfgBIFPLR4_LANE_10_MARGINING_LANE_CNTL                                                          0x0470
+#define cfgBIFPLR4_LANE_10_MARGINING_LANE_STATUS                                                        0x0472
+#define cfgBIFPLR4_LANE_11_MARGINING_LANE_CNTL                                                          0x0474
+#define cfgBIFPLR4_LANE_11_MARGINING_LANE_STATUS                                                        0x0476
+#define cfgBIFPLR4_LANE_12_MARGINING_LANE_CNTL                                                          0x0478
+#define cfgBIFPLR4_LANE_12_MARGINING_LANE_STATUS                                                        0x047a
+#define cfgBIFPLR4_LANE_13_MARGINING_LANE_CNTL                                                          0x047c
+#define cfgBIFPLR4_LANE_13_MARGINING_LANE_STATUS                                                        0x047e
+#define cfgBIFPLR4_LANE_14_MARGINING_LANE_CNTL                                                          0x0480
+#define cfgBIFPLR4_LANE_14_MARGINING_LANE_STATUS                                                        0x0482
+#define cfgBIFPLR4_LANE_15_MARGINING_LANE_CNTL                                                          0x0484
+#define cfgBIFPLR4_LANE_15_MARGINING_LANE_STATUS                                                        0x0486
+#define cfgBIFPLR4_PCIE_CCIX_CAP_LIST                                                                   0x0488
+#define cfgBIFPLR4_PCIE_CCIX_HEADER_1                                                                   0x048c
+#define cfgBIFPLR4_PCIE_CCIX_HEADER_2                                                                   0x0490
+#define cfgBIFPLR4_PCIE_CCIX_CAP                                                                        0x0492
+#define cfgBIFPLR4_PCIE_CCIX_ESM_REQD_CAP                                                               0x0494
+#define cfgBIFPLR4_PCIE_CCIX_ESM_OPTL_CAP                                                               0x0498
+#define cfgBIFPLR4_PCIE_CCIX_ESM_STATUS                                                                 0x049c
+#define cfgBIFPLR4_PCIE_CCIX_ESM_CNTL                                                                   0x04a0
+#define cfgBIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                    0x04a4
+#define cfgBIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                    0x04a5
+#define cfgBIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                    0x04a6
+#define cfgBIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                    0x04a7
+#define cfgBIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                    0x04a8
+#define cfgBIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                    0x04a9
+#define cfgBIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                    0x04aa
+#define cfgBIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                    0x04ab
+#define cfgBIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                    0x04ac
+#define cfgBIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                    0x04ad
+#define cfgBIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                   0x04ae
+#define cfgBIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                   0x04af
+#define cfgBIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                   0x04b0
+#define cfgBIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                   0x04b1
+#define cfgBIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                   0x04b2
+#define cfgBIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                   0x04b3
+#define cfgBIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                    0x04b4
+#define cfgBIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                    0x04b5
+#define cfgBIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                    0x04b6
+#define cfgBIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                    0x04b7
+#define cfgBIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                    0x04b8
+#define cfgBIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                    0x04b9
+#define cfgBIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                    0x04ba
+#define cfgBIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                    0x04bb
+#define cfgBIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                    0x04bc
+#define cfgBIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                    0x04bd
+#define cfgBIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                   0x04be
+#define cfgBIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                   0x04bf
+#define cfgBIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                   0x04c0
+#define cfgBIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                   0x04c1
+#define cfgBIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                   0x04c2
+#define cfgBIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                   0x04c3
+#define cfgBIFPLR4_PCIE_CCIX_TRANS_CAP                                                                  0x04c4
+#define cfgBIFPLR4_PCIE_CCIX_TRANS_CNTL                                                                 0x04c8
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+// base address: 0x0
+#define cfgBIFPLR5_VENDOR_ID                                                                            0x0000
+#define cfgBIFPLR5_DEVICE_ID                                                                            0x0002
+#define cfgBIFPLR5_COMMAND                                                                              0x0004
+#define cfgBIFPLR5_STATUS                                                                               0x0006
+#define cfgBIFPLR5_REVISION_ID                                                                          0x0008
+#define cfgBIFPLR5_PROG_INTERFACE                                                                       0x0009
+#define cfgBIFPLR5_SUB_CLASS                                                                            0x000a
+#define cfgBIFPLR5_BASE_CLASS                                                                           0x000b
+#define cfgBIFPLR5_CACHE_LINE                                                                           0x000c
+#define cfgBIFPLR5_LATENCY                                                                              0x000d
+#define cfgBIFPLR5_HEADER                                                                               0x000e
+#define cfgBIFPLR5_BIST                                                                                 0x000f
+#define cfgBIFPLR5_SUB_BUS_NUMBER_LATENCY                                                               0x0018
+#define cfgBIFPLR5_IO_BASE_LIMIT                                                                        0x001c
+#define cfgBIFPLR5_SECONDARY_STATUS                                                                     0x001e
+#define cfgBIFPLR5_MEM_BASE_LIMIT                                                                       0x0020
+#define cfgBIFPLR5_PREF_BASE_LIMIT                                                                      0x0024
+#define cfgBIFPLR5_PREF_BASE_UPPER                                                                      0x0028
+#define cfgBIFPLR5_PREF_LIMIT_UPPER                                                                     0x002c
+#define cfgBIFPLR5_IO_BASE_LIMIT_HI                                                                     0x0030
+#define cfgBIFPLR5_CAP_PTR                                                                              0x0034
+#define cfgBIFPLR5_ROM_BASE_ADDR                                                                        0x0038
+#define cfgBIFPLR5_INTERRUPT_LINE                                                                       0x003c
+#define cfgBIFPLR5_INTERRUPT_PIN                                                                        0x003d
+#define cfgBIFPLR5_IRQ_BRIDGE_CNTL                                                                      0x003e
+#define cfgBIFPLR5_EXT_BRIDGE_CNTL                                                                      0x0040
+#define cfgBIFPLR5_VENDOR_CAP_LIST                                                                      0x0048
+#define cfgBIFPLR5_ADAPTER_ID_W                                                                         0x004c
+#define cfgBIFPLR5_PMI_CAP_LIST                                                                         0x0050
+#define cfgBIFPLR5_PMI_CAP                                                                              0x0052
+#define cfgBIFPLR5_PMI_STATUS_CNTL                                                                      0x0054
+#define cfgBIFPLR5_PCIE_CAP_LIST                                                                        0x0058
+#define cfgBIFPLR5_PCIE_CAP                                                                             0x005a
+#define cfgBIFPLR5_DEVICE_CAP                                                                           0x005c
+#define cfgBIFPLR5_DEVICE_CNTL                                                                          0x0060
+#define cfgBIFPLR5_DEVICE_STATUS                                                                        0x0062
+#define cfgBIFPLR5_LINK_CAP                                                                             0x0064
+#define cfgBIFPLR5_LINK_CNTL                                                                            0x0068
+#define cfgBIFPLR5_LINK_STATUS                                                                          0x006a
+#define cfgBIFPLR5_SLOT_CAP                                                                             0x006c
+#define cfgBIFPLR5_SLOT_CNTL                                                                            0x0070
+#define cfgBIFPLR5_SLOT_STATUS                                                                          0x0072
+#define cfgBIFPLR5_ROOT_CNTL                                                                            0x0074
+#define cfgBIFPLR5_ROOT_CAP                                                                             0x0076
+#define cfgBIFPLR5_ROOT_STATUS                                                                          0x0078
+#define cfgBIFPLR5_DEVICE_CAP2                                                                          0x007c
+#define cfgBIFPLR5_DEVICE_CNTL2                                                                         0x0080
+#define cfgBIFPLR5_DEVICE_STATUS2                                                                       0x0082
+#define cfgBIFPLR5_LINK_CAP2                                                                            0x0084
+#define cfgBIFPLR5_LINK_CNTL2                                                                           0x0088
+#define cfgBIFPLR5_LINK_STATUS2                                                                         0x008a
+#define cfgBIFPLR5_SLOT_CAP2                                                                            0x008c
+#define cfgBIFPLR5_SLOT_CNTL2                                                                           0x0090
+#define cfgBIFPLR5_SLOT_STATUS2                                                                         0x0092
+#define cfgBIFPLR5_MSI_CAP_LIST                                                                         0x00a0
+#define cfgBIFPLR5_MSI_MSG_CNTL                                                                         0x00a2
+#define cfgBIFPLR5_MSI_MSG_ADDR_LO                                                                      0x00a4
+#define cfgBIFPLR5_MSI_MSG_ADDR_HI                                                                      0x00a8
+#define cfgBIFPLR5_MSI_MSG_DATA                                                                         0x00a8
+#define cfgBIFPLR5_MSI_MSG_DATA_64                                                                      0x00ac
+#define cfgBIFPLR5_SSID_CAP_LIST                                                                        0x00c0
+#define cfgBIFPLR5_SSID_CAP                                                                             0x00c4
+#define cfgBIFPLR5_MSI_MAP_CAP_LIST                                                                     0x00c8
+#define cfgBIFPLR5_MSI_MAP_CAP                                                                          0x00ca
+#define cfgBIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                    0x0100
+#define cfgBIFPLR5_PCIE_VENDOR_SPECIFIC_HDR                                                             0x0104
+#define cfgBIFPLR5_PCIE_VENDOR_SPECIFIC1                                                                0x0108
+#define cfgBIFPLR5_PCIE_VENDOR_SPECIFIC2                                                                0x010c
+#define cfgBIFPLR5_PCIE_VC_ENH_CAP_LIST                                                                 0x0110
+#define cfgBIFPLR5_PCIE_PORT_VC_CAP_REG1                                                                0x0114
+#define cfgBIFPLR5_PCIE_PORT_VC_CAP_REG2                                                                0x0118
+#define cfgBIFPLR5_PCIE_PORT_VC_CNTL                                                                    0x011c
+#define cfgBIFPLR5_PCIE_PORT_VC_STATUS                                                                  0x011e
+#define cfgBIFPLR5_PCIE_VC0_RESOURCE_CAP                                                                0x0120
+#define cfgBIFPLR5_PCIE_VC0_RESOURCE_CNTL                                                               0x0124
+#define cfgBIFPLR5_PCIE_VC0_RESOURCE_STATUS                                                             0x012a
+#define cfgBIFPLR5_PCIE_VC1_RESOURCE_CAP                                                                0x012c
+#define cfgBIFPLR5_PCIE_VC1_RESOURCE_CNTL                                                               0x0130
+#define cfgBIFPLR5_PCIE_VC1_RESOURCE_STATUS                                                             0x0136
+#define cfgBIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                     0x0140
+#define cfgBIFPLR5_PCIE_DEV_SERIAL_NUM_DW1                                                              0x0144
+#define cfgBIFPLR5_PCIE_DEV_SERIAL_NUM_DW2                                                              0x0148
+#define cfgBIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                        0x0150
+#define cfgBIFPLR5_PCIE_UNCORR_ERR_STATUS                                                               0x0154
+#define cfgBIFPLR5_PCIE_UNCORR_ERR_MASK                                                                 0x0158
+#define cfgBIFPLR5_PCIE_UNCORR_ERR_SEVERITY                                                             0x015c
+#define cfgBIFPLR5_PCIE_CORR_ERR_STATUS                                                                 0x0160
+#define cfgBIFPLR5_PCIE_CORR_ERR_MASK                                                                   0x0164
+#define cfgBIFPLR5_PCIE_ADV_ERR_CAP_CNTL                                                                0x0168
+#define cfgBIFPLR5_PCIE_HDR_LOG0                                                                        0x016c
+#define cfgBIFPLR5_PCIE_HDR_LOG1                                                                        0x0170
+#define cfgBIFPLR5_PCIE_HDR_LOG2                                                                        0x0174
+#define cfgBIFPLR5_PCIE_HDR_LOG3                                                                        0x0178
+#define cfgBIFPLR5_PCIE_ROOT_ERR_CMD                                                                    0x017c
+#define cfgBIFPLR5_PCIE_ROOT_ERR_STATUS                                                                 0x0180
+#define cfgBIFPLR5_PCIE_ERR_SRC_ID                                                                      0x0184
+#define cfgBIFPLR5_PCIE_TLP_PREFIX_LOG0                                                                 0x0188
+#define cfgBIFPLR5_PCIE_TLP_PREFIX_LOG1                                                                 0x018c
+#define cfgBIFPLR5_PCIE_TLP_PREFIX_LOG2                                                                 0x0190
+#define cfgBIFPLR5_PCIE_TLP_PREFIX_LOG3                                                                 0x0194
+#define cfgBIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST                                                          0x0270
+#define cfgBIFPLR5_PCIE_LINK_CNTL3                                                                      0x0274
+#define cfgBIFPLR5_PCIE_LANE_ERROR_STATUS                                                               0x0278
+#define cfgBIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL                                                        0x027c
+#define cfgBIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL                                                        0x027e
+#define cfgBIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL                                                        0x0280
+#define cfgBIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL                                                        0x0282
+#define cfgBIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL                                                        0x0284
+#define cfgBIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL                                                        0x0286
+#define cfgBIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL                                                        0x0288
+#define cfgBIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL                                                        0x028a
+#define cfgBIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL                                                        0x028c
+#define cfgBIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL                                                        0x028e
+#define cfgBIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL                                                       0x0290
+#define cfgBIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL                                                       0x0292
+#define cfgBIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL                                                       0x0294
+#define cfgBIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL                                                       0x0296
+#define cfgBIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL                                                       0x0298
+#define cfgBIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL                                                       0x029a
+#define cfgBIFPLR5_PCIE_ACS_ENH_CAP_LIST                                                                0x02a0
+#define cfgBIFPLR5_PCIE_ACS_CAP                                                                         0x02a4
+#define cfgBIFPLR5_PCIE_ACS_CNTL                                                                        0x02a6
+#define cfgBIFPLR5_PCIE_MC_ENH_CAP_LIST                                                                 0x02f0
+#define cfgBIFPLR5_PCIE_MC_CAP                                                                          0x02f4
+#define cfgBIFPLR5_PCIE_MC_CNTL                                                                         0x02f6
+#define cfgBIFPLR5_PCIE_MC_ADDR0                                                                        0x02f8
+#define cfgBIFPLR5_PCIE_MC_ADDR1                                                                        0x02fc
+#define cfgBIFPLR5_PCIE_MC_RCV0                                                                         0x0300
+#define cfgBIFPLR5_PCIE_MC_RCV1                                                                         0x0304
+#define cfgBIFPLR5_PCIE_MC_BLOCK_ALL0                                                                   0x0308
+#define cfgBIFPLR5_PCIE_MC_BLOCK_ALL1                                                                   0x030c
+#define cfgBIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_0                                                         0x0310
+#define cfgBIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_1                                                         0x0314
+#define cfgBIFPLR5_PCIE_MC_OVERLAY_BAR0                                                                 0x0318
+#define cfgBIFPLR5_PCIE_MC_OVERLAY_BAR1                                                                 0x031c
+#define cfgBIFPLR5_PCIE_L1_PM_SUB_CAP_LIST                                                              0x0370
+#define cfgBIFPLR5_PCIE_L1_PM_SUB_CAP                                                                   0x0374
+#define cfgBIFPLR5_PCIE_L1_PM_SUB_CNTL                                                                  0x0378
+#define cfgBIFPLR5_PCIE_L1_PM_SUB_CNTL2                                                                 0x037c
+#define cfgBIFPLR5_PCIE_DPC_ENH_CAP_LIST                                                                0x0380
+#define cfgBIFPLR5_PCIE_DPC_CAP_LIST                                                                    0x0384
+#define cfgBIFPLR5_PCIE_DPC_CNTL                                                                        0x0386
+#define cfgBIFPLR5_PCIE_DPC_STATUS                                                                      0x0388
+#define cfgBIFPLR5_PCIE_DPC_ERROR_SOURCE_ID                                                             0x038a
+#define cfgBIFPLR5_PCIE_RP_PIO_STATUS                                                                   0x038c
+#define cfgBIFPLR5_PCIE_RP_PIO_MASK                                                                     0x0390
+#define cfgBIFPLR5_PCIE_RP_PIO_SEVERITY                                                                 0x0394
+#define cfgBIFPLR5_PCIE_RP_PIO_SYSERROR                                                                 0x0398
+#define cfgBIFPLR5_PCIE_RP_PIO_EXCEPTION                                                                0x039c
+#define cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG0                                                                 0x03a0
+#define cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG1                                                                 0x03a4
+#define cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG2                                                                 0x03a8
+#define cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG3                                                                 0x03ac
+#define cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG0                                                              0x03b4
+#define cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG1                                                              0x03b8
+#define cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG2                                                              0x03bc
+#define cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG3                                                              0x03c0
+#define cfgBIFPLR5_PCIE_ESM_CAP_LIST                                                                    0x03c4
+#define cfgBIFPLR5_PCIE_ESM_HEADER_1                                                                    0x03c8
+#define cfgBIFPLR5_PCIE_ESM_HEADER_2                                                                    0x03cc
+#define cfgBIFPLR5_PCIE_ESM_STATUS                                                                      0x03ce
+#define cfgBIFPLR5_PCIE_ESM_CTRL                                                                        0x03d0
+#define cfgBIFPLR5_PCIE_ESM_CAP_1                                                                       0x03d4
+#define cfgBIFPLR5_PCIE_ESM_CAP_2                                                                       0x03d8
+#define cfgBIFPLR5_PCIE_ESM_CAP_3                                                                       0x03dc
+#define cfgBIFPLR5_PCIE_ESM_CAP_4                                                                       0x03e0
+#define cfgBIFPLR5_PCIE_ESM_CAP_5                                                                       0x03e4
+#define cfgBIFPLR5_PCIE_ESM_CAP_6                                                                       0x03e8
+#define cfgBIFPLR5_PCIE_ESM_CAP_7                                                                       0x03ec
+#define cfgBIFPLR5_PCIE_DLF_ENH_CAP_LIST                                                                0x0400
+#define cfgBIFPLR5_DATA_LINK_FEATURE_CAP                                                                0x0404
+#define cfgBIFPLR5_DATA_LINK_FEATURE_STATUS                                                             0x0408
+#define cfgBIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST                                                           0x0410
+#define cfgBIFPLR5_LINK_CAP_16GT                                                                        0x0414
+#define cfgBIFPLR5_LINK_CNTL_16GT                                                                       0x0418
+#define cfgBIFPLR5_LINK_STATUS_16GT                                                                     0x041c
+#define cfgBIFPLR5_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                    0x0420
+#define cfgBIFPLR5_RTM1_PARITY_MISMATCH_STATUS_16GT                                                     0x0424
+#define cfgBIFPLR5_RTM2_PARITY_MISMATCH_STATUS_16GT                                                     0x0428
+#define cfgBIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT                                                        0x0430
+#define cfgBIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT                                                        0x0431
+#define cfgBIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT                                                        0x0432
+#define cfgBIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT                                                        0x0433
+#define cfgBIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT                                                        0x0434
+#define cfgBIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT                                                        0x0435
+#define cfgBIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT                                                        0x0436
+#define cfgBIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT                                                        0x0437
+#define cfgBIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT                                                        0x0438
+#define cfgBIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT                                                        0x0439
+#define cfgBIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT                                                       0x043a
+#define cfgBIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT                                                       0x043b
+#define cfgBIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT                                                       0x043c
+#define cfgBIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT                                                       0x043d
+#define cfgBIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT                                                       0x043e
+#define cfgBIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT                                                       0x043f
+#define cfgBIFPLR5_PCIE_MARGINING_ENH_CAP_LIST                                                          0x0440
+#define cfgBIFPLR5_MARGINING_PORT_CAP                                                                   0x0444
+#define cfgBIFPLR5_MARGINING_PORT_STATUS                                                                0x0446
+#define cfgBIFPLR5_LANE_0_MARGINING_LANE_CNTL                                                           0x0448
+#define cfgBIFPLR5_LANE_0_MARGINING_LANE_STATUS                                                         0x044a
+#define cfgBIFPLR5_LANE_1_MARGINING_LANE_CNTL                                                           0x044c
+#define cfgBIFPLR5_LANE_1_MARGINING_LANE_STATUS                                                         0x044e
+#define cfgBIFPLR5_LANE_2_MARGINING_LANE_CNTL                                                           0x0450
+#define cfgBIFPLR5_LANE_2_MARGINING_LANE_STATUS                                                         0x0452
+#define cfgBIFPLR5_LANE_3_MARGINING_LANE_CNTL                                                           0x0454
+#define cfgBIFPLR5_LANE_3_MARGINING_LANE_STATUS                                                         0x0456
+#define cfgBIFPLR5_LANE_4_MARGINING_LANE_CNTL                                                           0x0458
+#define cfgBIFPLR5_LANE_4_MARGINING_LANE_STATUS                                                         0x045a
+#define cfgBIFPLR5_LANE_5_MARGINING_LANE_CNTL                                                           0x045c
+#define cfgBIFPLR5_LANE_5_MARGINING_LANE_STATUS                                                         0x045e
+#define cfgBIFPLR5_LANE_6_MARGINING_LANE_CNTL                                                           0x0460
+#define cfgBIFPLR5_LANE_6_MARGINING_LANE_STATUS                                                         0x0462
+#define cfgBIFPLR5_LANE_7_MARGINING_LANE_CNTL                                                           0x0464
+#define cfgBIFPLR5_LANE_7_MARGINING_LANE_STATUS                                                         0x0466
+#define cfgBIFPLR5_LANE_8_MARGINING_LANE_CNTL                                                           0x0468
+#define cfgBIFPLR5_LANE_8_MARGINING_LANE_STATUS                                                         0x046a
+#define cfgBIFPLR5_LANE_9_MARGINING_LANE_CNTL                                                           0x046c
+#define cfgBIFPLR5_LANE_9_MARGINING_LANE_STATUS                                                         0x046e
+#define cfgBIFPLR5_LANE_10_MARGINING_LANE_CNTL                                                          0x0470
+#define cfgBIFPLR5_LANE_10_MARGINING_LANE_STATUS                                                        0x0472
+#define cfgBIFPLR5_LANE_11_MARGINING_LANE_CNTL                                                          0x0474
+#define cfgBIFPLR5_LANE_11_MARGINING_LANE_STATUS                                                        0x0476
+#define cfgBIFPLR5_LANE_12_MARGINING_LANE_CNTL                                                          0x0478
+#define cfgBIFPLR5_LANE_12_MARGINING_LANE_STATUS                                                        0x047a
+#define cfgBIFPLR5_LANE_13_MARGINING_LANE_CNTL                                                          0x047c
+#define cfgBIFPLR5_LANE_13_MARGINING_LANE_STATUS                                                        0x047e
+#define cfgBIFPLR5_LANE_14_MARGINING_LANE_CNTL                                                          0x0480
+#define cfgBIFPLR5_LANE_14_MARGINING_LANE_STATUS                                                        0x0482
+#define cfgBIFPLR5_LANE_15_MARGINING_LANE_CNTL                                                          0x0484
+#define cfgBIFPLR5_LANE_15_MARGINING_LANE_STATUS                                                        0x0486
+#define cfgBIFPLR5_PCIE_CCIX_CAP_LIST                                                                   0x0488
+#define cfgBIFPLR5_PCIE_CCIX_HEADER_1                                                                   0x048c
+#define cfgBIFPLR5_PCIE_CCIX_HEADER_2                                                                   0x0490
+#define cfgBIFPLR5_PCIE_CCIX_CAP                                                                        0x0492
+#define cfgBIFPLR5_PCIE_CCIX_ESM_REQD_CAP                                                               0x0494
+#define cfgBIFPLR5_PCIE_CCIX_ESM_OPTL_CAP                                                               0x0498
+#define cfgBIFPLR5_PCIE_CCIX_ESM_STATUS                                                                 0x049c
+#define cfgBIFPLR5_PCIE_CCIX_ESM_CNTL                                                                   0x04a0
+#define cfgBIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                    0x04a4
+#define cfgBIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                    0x04a5
+#define cfgBIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                    0x04a6
+#define cfgBIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                    0x04a7
+#define cfgBIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                    0x04a8
+#define cfgBIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                    0x04a9
+#define cfgBIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                    0x04aa
+#define cfgBIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                    0x04ab
+#define cfgBIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                    0x04ac
+#define cfgBIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                    0x04ad
+#define cfgBIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                   0x04ae
+#define cfgBIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                   0x04af
+#define cfgBIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                   0x04b0
+#define cfgBIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                   0x04b1
+#define cfgBIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                   0x04b2
+#define cfgBIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                   0x04b3
+#define cfgBIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                    0x04b4
+#define cfgBIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                    0x04b5
+#define cfgBIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                    0x04b6
+#define cfgBIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                    0x04b7
+#define cfgBIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                    0x04b8
+#define cfgBIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                    0x04b9
+#define cfgBIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                    0x04ba
+#define cfgBIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                    0x04bb
+#define cfgBIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                    0x04bc
+#define cfgBIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                    0x04bd
+#define cfgBIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                   0x04be
+#define cfgBIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                   0x04bf
+#define cfgBIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                   0x04c0
+#define cfgBIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                   0x04c1
+#define cfgBIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                   0x04c2
+#define cfgBIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                   0x04c3
+#define cfgBIFPLR5_PCIE_CCIX_TRANS_CAP                                                                  0x04c4
+#define cfgBIFPLR5_PCIE_CCIX_TRANS_CNTL                                                                 0x04c8
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+// base address: 0x0
+#define cfgBIFPLR6_VENDOR_ID                                                                            0x0000
+#define cfgBIFPLR6_DEVICE_ID                                                                            0x0002
+#define cfgBIFPLR6_COMMAND                                                                              0x0004
+#define cfgBIFPLR6_STATUS                                                                               0x0006
+#define cfgBIFPLR6_REVISION_ID                                                                          0x0008
+#define cfgBIFPLR6_PROG_INTERFACE                                                                       0x0009
+#define cfgBIFPLR6_SUB_CLASS                                                                            0x000a
+#define cfgBIFPLR6_BASE_CLASS                                                                           0x000b
+#define cfgBIFPLR6_CACHE_LINE                                                                           0x000c
+#define cfgBIFPLR6_LATENCY                                                                              0x000d
+#define cfgBIFPLR6_HEADER                                                                               0x000e
+#define cfgBIFPLR6_BIST                                                                                 0x000f
+#define cfgBIFPLR6_SUB_BUS_NUMBER_LATENCY                                                               0x0018
+#define cfgBIFPLR6_IO_BASE_LIMIT                                                                        0x001c
+#define cfgBIFPLR6_SECONDARY_STATUS                                                                     0x001e
+#define cfgBIFPLR6_MEM_BASE_LIMIT                                                                       0x0020
+#define cfgBIFPLR6_PREF_BASE_LIMIT                                                                      0x0024
+#define cfgBIFPLR6_PREF_BASE_UPPER                                                                      0x0028
+#define cfgBIFPLR6_PREF_LIMIT_UPPER                                                                     0x002c
+#define cfgBIFPLR6_IO_BASE_LIMIT_HI                                                                     0x0030
+#define cfgBIFPLR6_CAP_PTR                                                                              0x0034
+#define cfgBIFPLR6_ROM_BASE_ADDR                                                                        0x0038
+#define cfgBIFPLR6_INTERRUPT_LINE                                                                       0x003c
+#define cfgBIFPLR6_INTERRUPT_PIN                                                                        0x003d
+#define cfgBIFPLR6_IRQ_BRIDGE_CNTL                                                                      0x003e
+#define cfgBIFPLR6_EXT_BRIDGE_CNTL                                                                      0x0040
+#define cfgBIFPLR6_VENDOR_CAP_LIST                                                                      0x0048
+#define cfgBIFPLR6_ADAPTER_ID_W                                                                         0x004c
+#define cfgBIFPLR6_PMI_CAP_LIST                                                                         0x0050
+#define cfgBIFPLR6_PMI_CAP                                                                              0x0052
+#define cfgBIFPLR6_PMI_STATUS_CNTL                                                                      0x0054
+#define cfgBIFPLR6_PCIE_CAP_LIST                                                                        0x0058
+#define cfgBIFPLR6_PCIE_CAP                                                                             0x005a
+#define cfgBIFPLR6_DEVICE_CAP                                                                           0x005c
+#define cfgBIFPLR6_DEVICE_CNTL                                                                          0x0060
+#define cfgBIFPLR6_DEVICE_STATUS                                                                        0x0062
+#define cfgBIFPLR6_LINK_CAP                                                                             0x0064
+#define cfgBIFPLR6_LINK_CNTL                                                                            0x0068
+#define cfgBIFPLR6_LINK_STATUS                                                                          0x006a
+#define cfgBIFPLR6_SLOT_CAP                                                                             0x006c
+#define cfgBIFPLR6_SLOT_CNTL                                                                            0x0070
+#define cfgBIFPLR6_SLOT_STATUS                                                                          0x0072
+#define cfgBIFPLR6_ROOT_CNTL                                                                            0x0074
+#define cfgBIFPLR6_ROOT_CAP                                                                             0x0076
+#define cfgBIFPLR6_ROOT_STATUS                                                                          0x0078
+#define cfgBIFPLR6_DEVICE_CAP2                                                                          0x007c
+#define cfgBIFPLR6_DEVICE_CNTL2                                                                         0x0080
+#define cfgBIFPLR6_DEVICE_STATUS2                                                                       0x0082
+#define cfgBIFPLR6_LINK_CAP2                                                                            0x0084
+#define cfgBIFPLR6_LINK_CNTL2                                                                           0x0088
+#define cfgBIFPLR6_LINK_STATUS2                                                                         0x008a
+#define cfgBIFPLR6_SLOT_CAP2                                                                            0x008c
+#define cfgBIFPLR6_SLOT_CNTL2                                                                           0x0090
+#define cfgBIFPLR6_SLOT_STATUS2                                                                         0x0092
+#define cfgBIFPLR6_MSI_CAP_LIST                                                                         0x00a0
+#define cfgBIFPLR6_MSI_MSG_CNTL                                                                         0x00a2
+#define cfgBIFPLR6_MSI_MSG_ADDR_LO                                                                      0x00a4
+#define cfgBIFPLR6_MSI_MSG_ADDR_HI                                                                      0x00a8
+#define cfgBIFPLR6_MSI_MSG_DATA                                                                         0x00a8
+#define cfgBIFPLR6_MSI_MSG_DATA_64                                                                      0x00ac
+#define cfgBIFPLR6_SSID_CAP_LIST                                                                        0x00c0
+#define cfgBIFPLR6_SSID_CAP                                                                             0x00c4
+#define cfgBIFPLR6_MSI_MAP_CAP_LIST                                                                     0x00c8
+#define cfgBIFPLR6_MSI_MAP_CAP                                                                          0x00ca
+#define cfgBIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                    0x0100
+#define cfgBIFPLR6_PCIE_VENDOR_SPECIFIC_HDR                                                             0x0104
+#define cfgBIFPLR6_PCIE_VENDOR_SPECIFIC1                                                                0x0108
+#define cfgBIFPLR6_PCIE_VENDOR_SPECIFIC2                                                                0x010c
+#define cfgBIFPLR6_PCIE_VC_ENH_CAP_LIST                                                                 0x0110
+#define cfgBIFPLR6_PCIE_PORT_VC_CAP_REG1                                                                0x0114
+#define cfgBIFPLR6_PCIE_PORT_VC_CAP_REG2                                                                0x0118
+#define cfgBIFPLR6_PCIE_PORT_VC_CNTL                                                                    0x011c
+#define cfgBIFPLR6_PCIE_PORT_VC_STATUS                                                                  0x011e
+#define cfgBIFPLR6_PCIE_VC0_RESOURCE_CAP                                                                0x0120
+#define cfgBIFPLR6_PCIE_VC0_RESOURCE_CNTL                                                               0x0124
+#define cfgBIFPLR6_PCIE_VC0_RESOURCE_STATUS                                                             0x012a
+#define cfgBIFPLR6_PCIE_VC1_RESOURCE_CAP                                                                0x012c
+#define cfgBIFPLR6_PCIE_VC1_RESOURCE_CNTL                                                               0x0130
+#define cfgBIFPLR6_PCIE_VC1_RESOURCE_STATUS                                                             0x0136
+#define cfgBIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                     0x0140
+#define cfgBIFPLR6_PCIE_DEV_SERIAL_NUM_DW1                                                              0x0144
+#define cfgBIFPLR6_PCIE_DEV_SERIAL_NUM_DW2                                                              0x0148
+#define cfgBIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                        0x0150
+#define cfgBIFPLR6_PCIE_UNCORR_ERR_STATUS                                                               0x0154
+#define cfgBIFPLR6_PCIE_UNCORR_ERR_MASK                                                                 0x0158
+#define cfgBIFPLR6_PCIE_UNCORR_ERR_SEVERITY                                                             0x015c
+#define cfgBIFPLR6_PCIE_CORR_ERR_STATUS                                                                 0x0160
+#define cfgBIFPLR6_PCIE_CORR_ERR_MASK                                                                   0x0164
+#define cfgBIFPLR6_PCIE_ADV_ERR_CAP_CNTL                                                                0x0168
+#define cfgBIFPLR6_PCIE_HDR_LOG0                                                                        0x016c
+#define cfgBIFPLR6_PCIE_HDR_LOG1                                                                        0x0170
+#define cfgBIFPLR6_PCIE_HDR_LOG2                                                                        0x0174
+#define cfgBIFPLR6_PCIE_HDR_LOG3                                                                        0x0178
+#define cfgBIFPLR6_PCIE_ROOT_ERR_CMD                                                                    0x017c
+#define cfgBIFPLR6_PCIE_ROOT_ERR_STATUS                                                                 0x0180
+#define cfgBIFPLR6_PCIE_ERR_SRC_ID                                                                      0x0184
+#define cfgBIFPLR6_PCIE_TLP_PREFIX_LOG0                                                                 0x0188
+#define cfgBIFPLR6_PCIE_TLP_PREFIX_LOG1                                                                 0x018c
+#define cfgBIFPLR6_PCIE_TLP_PREFIX_LOG2                                                                 0x0190
+#define cfgBIFPLR6_PCIE_TLP_PREFIX_LOG3                                                                 0x0194
+#define cfgBIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST                                                          0x0270
+#define cfgBIFPLR6_PCIE_LINK_CNTL3                                                                      0x0274
+#define cfgBIFPLR6_PCIE_LANE_ERROR_STATUS                                                               0x0278
+#define cfgBIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL                                                        0x027c
+#define cfgBIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL                                                        0x027e
+#define cfgBIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL                                                        0x0280
+#define cfgBIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL                                                        0x0282
+#define cfgBIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL                                                        0x0284
+#define cfgBIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL                                                        0x0286
+#define cfgBIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL                                                        0x0288
+#define cfgBIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL                                                        0x028a
+#define cfgBIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL                                                        0x028c
+#define cfgBIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL                                                        0x028e
+#define cfgBIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL                                                       0x0290
+#define cfgBIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL                                                       0x0292
+#define cfgBIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL                                                       0x0294
+#define cfgBIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL                                                       0x0296
+#define cfgBIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL                                                       0x0298
+#define cfgBIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL                                                       0x029a
+#define cfgBIFPLR6_PCIE_ACS_ENH_CAP_LIST                                                                0x02a0
+#define cfgBIFPLR6_PCIE_ACS_CAP                                                                         0x02a4
+#define cfgBIFPLR6_PCIE_ACS_CNTL                                                                        0x02a6
+#define cfgBIFPLR6_PCIE_MC_ENH_CAP_LIST                                                                 0x02f0
+#define cfgBIFPLR6_PCIE_MC_CAP                                                                          0x02f4
+#define cfgBIFPLR6_PCIE_MC_CNTL                                                                         0x02f6
+#define cfgBIFPLR6_PCIE_MC_ADDR0                                                                        0x02f8
+#define cfgBIFPLR6_PCIE_MC_ADDR1                                                                        0x02fc
+#define cfgBIFPLR6_PCIE_MC_RCV0                                                                         0x0300
+#define cfgBIFPLR6_PCIE_MC_RCV1                                                                         0x0304
+#define cfgBIFPLR6_PCIE_MC_BLOCK_ALL0                                                                   0x0308
+#define cfgBIFPLR6_PCIE_MC_BLOCK_ALL1                                                                   0x030c
+#define cfgBIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_0                                                         0x0310
+#define cfgBIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_1                                                         0x0314
+#define cfgBIFPLR6_PCIE_MC_OVERLAY_BAR0                                                                 0x0318
+#define cfgBIFPLR6_PCIE_MC_OVERLAY_BAR1                                                                 0x031c
+#define cfgBIFPLR6_PCIE_L1_PM_SUB_CAP_LIST                                                              0x0370
+#define cfgBIFPLR6_PCIE_L1_PM_SUB_CAP                                                                   0x0374
+#define cfgBIFPLR6_PCIE_L1_PM_SUB_CNTL                                                                  0x0378
+#define cfgBIFPLR6_PCIE_L1_PM_SUB_CNTL2                                                                 0x037c
+#define cfgBIFPLR6_PCIE_DPC_ENH_CAP_LIST                                                                0x0380
+#define cfgBIFPLR6_PCIE_DPC_CAP_LIST                                                                    0x0384
+#define cfgBIFPLR6_PCIE_DPC_CNTL                                                                        0x0386
+#define cfgBIFPLR6_PCIE_DPC_STATUS                                                                      0x0388
+#define cfgBIFPLR6_PCIE_DPC_ERROR_SOURCE_ID                                                             0x038a
+#define cfgBIFPLR6_PCIE_RP_PIO_STATUS                                                                   0x038c
+#define cfgBIFPLR6_PCIE_RP_PIO_MASK                                                                     0x0390
+#define cfgBIFPLR6_PCIE_RP_PIO_SEVERITY                                                                 0x0394
+#define cfgBIFPLR6_PCIE_RP_PIO_SYSERROR                                                                 0x0398
+#define cfgBIFPLR6_PCIE_RP_PIO_EXCEPTION                                                                0x039c
+#define cfgBIFPLR6_PCIE_RP_PIO_HDR_LOG0                                                                 0x03a0
+#define cfgBIFPLR6_PCIE_RP_PIO_HDR_LOG1                                                                 0x03a4
+#define cfgBIFPLR6_PCIE_RP_PIO_HDR_LOG2                                                                 0x03a8
+#define cfgBIFPLR6_PCIE_RP_PIO_HDR_LOG3                                                                 0x03ac
+#define cfgBIFPLR6_PCIE_RP_PIO_PREFIX_LOG0                                                              0x03b4
+#define cfgBIFPLR6_PCIE_RP_PIO_PREFIX_LOG1                                                              0x03b8
+#define cfgBIFPLR6_PCIE_RP_PIO_PREFIX_LOG2                                                              0x03bc
+#define cfgBIFPLR6_PCIE_RP_PIO_PREFIX_LOG3                                                              0x03c0
+#define cfgBIFPLR6_PCIE_ESM_CAP_LIST                                                                    0x03c4
+#define cfgBIFPLR6_PCIE_ESM_HEADER_1                                                                    0x03c8
+#define cfgBIFPLR6_PCIE_ESM_HEADER_2                                                                    0x03cc
+#define cfgBIFPLR6_PCIE_ESM_STATUS                                                                      0x03ce
+#define cfgBIFPLR6_PCIE_ESM_CTRL                                                                        0x03d0
+#define cfgBIFPLR6_PCIE_ESM_CAP_1                                                                       0x03d4
+#define cfgBIFPLR6_PCIE_ESM_CAP_2                                                                       0x03d8
+#define cfgBIFPLR6_PCIE_ESM_CAP_3                                                                       0x03dc
+#define cfgBIFPLR6_PCIE_ESM_CAP_4                                                                       0x03e0
+#define cfgBIFPLR6_PCIE_ESM_CAP_5                                                                       0x03e4
+#define cfgBIFPLR6_PCIE_ESM_CAP_6                                                                       0x03e8
+#define cfgBIFPLR6_PCIE_ESM_CAP_7                                                                       0x03ec
+#define cfgBIFPLR6_PCIE_DLF_ENH_CAP_LIST                                                                0x0400
+#define cfgBIFPLR6_DATA_LINK_FEATURE_CAP                                                                0x0404
+#define cfgBIFPLR6_DATA_LINK_FEATURE_STATUS                                                             0x0408
+#define cfgBIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST                                                           0x0410
+#define cfgBIFPLR6_LINK_CAP_16GT                                                                        0x0414
+#define cfgBIFPLR6_LINK_CNTL_16GT                                                                       0x0418
+#define cfgBIFPLR6_LINK_STATUS_16GT                                                                     0x041c
+#define cfgBIFPLR6_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                    0x0420
+#define cfgBIFPLR6_RTM1_PARITY_MISMATCH_STATUS_16GT                                                     0x0424
+#define cfgBIFPLR6_RTM2_PARITY_MISMATCH_STATUS_16GT                                                     0x0428
+#define cfgBIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT                                                        0x0430
+#define cfgBIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT                                                        0x0431
+#define cfgBIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT                                                        0x0432
+#define cfgBIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT                                                        0x0433
+#define cfgBIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT                                                        0x0434
+#define cfgBIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT                                                        0x0435
+#define cfgBIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT                                                        0x0436
+#define cfgBIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT                                                        0x0437
+#define cfgBIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT                                                        0x0438
+#define cfgBIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT                                                        0x0439
+#define cfgBIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT                                                       0x043a
+#define cfgBIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT                                                       0x043b
+#define cfgBIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT                                                       0x043c
+#define cfgBIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT                                                       0x043d
+#define cfgBIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT                                                       0x043e
+#define cfgBIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT                                                       0x043f
+#define cfgBIFPLR6_PCIE_MARGINING_ENH_CAP_LIST                                                          0x0440
+#define cfgBIFPLR6_MARGINING_PORT_CAP                                                                   0x0444
+#define cfgBIFPLR6_MARGINING_PORT_STATUS                                                                0x0446
+#define cfgBIFPLR6_LANE_0_MARGINING_LANE_CNTL                                                           0x0448
+#define cfgBIFPLR6_LANE_0_MARGINING_LANE_STATUS                                                         0x044a
+#define cfgBIFPLR6_LANE_1_MARGINING_LANE_CNTL                                                           0x044c
+#define cfgBIFPLR6_LANE_1_MARGINING_LANE_STATUS                                                         0x044e
+#define cfgBIFPLR6_LANE_2_MARGINING_LANE_CNTL                                                           0x0450
+#define cfgBIFPLR6_LANE_2_MARGINING_LANE_STATUS                                                         0x0452
+#define cfgBIFPLR6_LANE_3_MARGINING_LANE_CNTL                                                           0x0454
+#define cfgBIFPLR6_LANE_3_MARGINING_LANE_STATUS                                                         0x0456
+#define cfgBIFPLR6_LANE_4_MARGINING_LANE_CNTL                                                           0x0458
+#define cfgBIFPLR6_LANE_4_MARGINING_LANE_STATUS                                                         0x045a
+#define cfgBIFPLR6_LANE_5_MARGINING_LANE_CNTL                                                           0x045c
+#define cfgBIFPLR6_LANE_5_MARGINING_LANE_STATUS                                                         0x045e
+#define cfgBIFPLR6_LANE_6_MARGINING_LANE_CNTL                                                           0x0460
+#define cfgBIFPLR6_LANE_6_MARGINING_LANE_STATUS                                                         0x0462
+#define cfgBIFPLR6_LANE_7_MARGINING_LANE_CNTL                                                           0x0464
+#define cfgBIFPLR6_LANE_7_MARGINING_LANE_STATUS                                                         0x0466
+#define cfgBIFPLR6_LANE_8_MARGINING_LANE_CNTL                                                           0x0468
+#define cfgBIFPLR6_LANE_8_MARGINING_LANE_STATUS                                                         0x046a
+#define cfgBIFPLR6_LANE_9_MARGINING_LANE_CNTL                                                           0x046c
+#define cfgBIFPLR6_LANE_9_MARGINING_LANE_STATUS                                                         0x046e
+#define cfgBIFPLR6_LANE_10_MARGINING_LANE_CNTL                                                          0x0470
+#define cfgBIFPLR6_LANE_10_MARGINING_LANE_STATUS                                                        0x0472
+#define cfgBIFPLR6_LANE_11_MARGINING_LANE_CNTL                                                          0x0474
+#define cfgBIFPLR6_LANE_11_MARGINING_LANE_STATUS                                                        0x0476
+#define cfgBIFPLR6_LANE_12_MARGINING_LANE_CNTL                                                          0x0478
+#define cfgBIFPLR6_LANE_12_MARGINING_LANE_STATUS                                                        0x047a
+#define cfgBIFPLR6_LANE_13_MARGINING_LANE_CNTL                                                          0x047c
+#define cfgBIFPLR6_LANE_13_MARGINING_LANE_STATUS                                                        0x047e
+#define cfgBIFPLR6_LANE_14_MARGINING_LANE_CNTL                                                          0x0480
+#define cfgBIFPLR6_LANE_14_MARGINING_LANE_STATUS                                                        0x0482
+#define cfgBIFPLR6_LANE_15_MARGINING_LANE_CNTL                                                          0x0484
+#define cfgBIFPLR6_LANE_15_MARGINING_LANE_STATUS                                                        0x0486
+#define cfgBIFPLR6_PCIE_CCIX_CAP_LIST                                                                   0x0488
+#define cfgBIFPLR6_PCIE_CCIX_HEADER_1                                                                   0x048c
+#define cfgBIFPLR6_PCIE_CCIX_HEADER_2                                                                   0x0490
+#define cfgBIFPLR6_PCIE_CCIX_CAP                                                                        0x0492
+#define cfgBIFPLR6_PCIE_CCIX_ESM_REQD_CAP                                                               0x0494
+#define cfgBIFPLR6_PCIE_CCIX_ESM_OPTL_CAP                                                               0x0498
+#define cfgBIFPLR6_PCIE_CCIX_ESM_STATUS                                                                 0x049c
+#define cfgBIFPLR6_PCIE_CCIX_ESM_CNTL                                                                   0x04a0
+#define cfgBIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                    0x04a4
+#define cfgBIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                    0x04a5
+#define cfgBIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                    0x04a6
+#define cfgBIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                    0x04a7
+#define cfgBIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                    0x04a8
+#define cfgBIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                    0x04a9
+#define cfgBIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                    0x04aa
+#define cfgBIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                    0x04ab
+#define cfgBIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                    0x04ac
+#define cfgBIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                    0x04ad
+#define cfgBIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                   0x04ae
+#define cfgBIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                   0x04af
+#define cfgBIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                   0x04b0
+#define cfgBIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                   0x04b1
+#define cfgBIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                   0x04b2
+#define cfgBIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                   0x04b3
+#define cfgBIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                    0x04b4
+#define cfgBIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                    0x04b5
+#define cfgBIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                    0x04b6
+#define cfgBIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                    0x04b7
+#define cfgBIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                    0x04b8
+#define cfgBIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                    0x04b9
+#define cfgBIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                    0x04ba
+#define cfgBIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                    0x04bb
+#define cfgBIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                    0x04bc
+#define cfgBIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                    0x04bd
+#define cfgBIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                   0x04be
+#define cfgBIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                   0x04bf
+#define cfgBIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                   0x04c0
+#define cfgBIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                   0x04c1
+#define cfgBIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                   0x04c2
+#define cfgBIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                   0x04c3
+#define cfgBIFPLR6_PCIE_CCIX_TRANS_CAP                                                                  0x04c4
+#define cfgBIFPLR6_PCIE_CCIX_TRANS_CNTL                                                                 0x04c8
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1
+// base address: 0x0
+#define regBIF_BX_PF0_MM_INDEX                                                                          0x0000
+#define regBIF_BX_PF0_MM_INDEX_BASE_IDX                                                                 0
+#define regBIF_BX_PF0_MM_DATA                                                                           0x0001
+#define regBIF_BX_PF0_MM_DATA_BASE_IDX                                                                  0
+#define regBIF_BX_PF0_MM_INDEX_HI                                                                       0x0006
+#define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX                                                              0
+#define regBIF_BX_PF0_RSMU_INDEX                                                                        0x0000
+#define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX                                                               1
+#define regBIF_BX_PF0_RSMU_DATA                                                                         0x0001
+#define regBIF_BX_PF0_RSMU_DATA_BASE_IDX                                                                1
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC:1
+// base address: 0x0
+#define regBIF_BX0_PCIE_INDEX                                                                           0x000c
+#define regBIF_BX0_PCIE_INDEX_BASE_IDX                                                                  0
+#define regBIF_BX0_PCIE_DATA                                                                            0x000d
+#define regBIF_BX0_PCIE_DATA_BASE_IDX                                                                   0
+#define regBIF_BX0_PCIE_INDEX2                                                                          0x000e
+#define regBIF_BX0_PCIE_INDEX2_BASE_IDX                                                                 0
+#define regBIF_BX0_PCIE_DATA2                                                                           0x000f
+#define regBIF_BX0_PCIE_DATA2_BASE_IDX                                                                  0
+#define regBIF_BX0_SBIOS_SCRATCH_0                                                                      0x0034
+#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_1                                                                      0x0035
+#define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_2                                                                      0x0036
+#define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_3                                                                      0x0037
+#define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_0                                                                       0x0038
+#define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_1                                                                       0x0039
+#define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_2                                                                       0x003a
+#define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_3                                                                       0x003b
+#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_4                                                                       0x003c
+#define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_5                                                                       0x003d
+#define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_6                                                                       0x003e
+#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_7                                                                       0x003f
+#define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_8                                                                       0x0040
+#define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_9                                                                       0x0041
+#define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_10                                                                      0x0042
+#define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_11                                                                      0x0043
+#define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_12                                                                      0x0044
+#define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_13                                                                      0x0045
+#define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_14                                                                      0x0046
+#define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_15                                                                      0x0047
+#define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX                                                             1
+#define regBIF_BX0_BIF_RLC_INTR_CNTL                                                                    0x004c
+#define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX                                                           1
+#define regBIF_BX0_BIF_VCE_INTR_CNTL                                                                    0x004d
+#define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX                                                           1
+#define regBIF_BX0_BIF_UVD_INTR_CNTL                                                                    0x004e
+#define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX                                                           1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0                                                                0x006c
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0                                                          0x006d
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1                                                                0x006e
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1                                                          0x006f
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2                                                                0x0070
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2                                                          0x0071
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3                                                                0x0072
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3                                                          0x0073
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4                                                                0x0074
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4                                                          0x0075
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5                                                                0x0076
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5                                                          0x0077
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6                                                                0x0078
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6                                                          0x0079
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7                                                                0x007a
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7                                                          0x007b
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL                                                                 0x007c
+#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX                                                        1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL                                                             0x007d
+#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX                                                    1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL                                                              0x007e
+#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX                                                     1
+#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL                                                     0x007f
+#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX                                            1
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+// base address: 0x0
+#define regRCC_STRAP0_RCC_BIF_STRAP0                                                                    0x0000
+#define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP1                                                                    0x0001
+#define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP2                                                                    0x0002
+#define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP3                                                                    0x0003
+#define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP4                                                                    0x0004
+#define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP5                                                                    0x0005
+#define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP6                                                                    0x0006
+#define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0                                                              0x0007
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1                                                              0x0008
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2                                                              0x0009
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3                                                              0x000a
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4                                                              0x000b
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5                                                              0x000c
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6                                                              0x000d
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7                                                              0x000e
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8                                                              0x000f
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9                                                              0x0010
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0                                                              0x0011
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1                                                              0x0012
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13                                                             0x0013
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14                                                             0x0014
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2                                                              0x0015
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3                                                              0x0016
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4                                                              0x0017
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5                                                              0x0018
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8                                                              0x0019
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9                                                              0x001a
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0                                                              0x001b
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP10                                                             0x001c
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP10_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP11                                                             0x001d
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP11_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP12                                                             0x001e
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP12_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP13                                                             0x001f
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP13_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP14                                                             0x0020
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP14_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2                                                              0x0021
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3                                                              0x0022
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4                                                              0x0023
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5                                                              0x0024
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6                                                              0x0025
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7                                                              0x0026
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX                                                     2
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1:1
+// base address: 0x0
+#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH                                                                0x0027
+#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX                                                       2
+#define regRCC_EP_DEV0_0_EP_PCIE_CNTL                                                                   0x0029
+#define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX                                                          2
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL                                                               0x002a
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX                                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS                                                             0x002b
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX                                                    2
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2                                                               0x002c
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX                                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL                                                               0x002d
+#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX                                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL                                                               0x002e
+#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX                                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL                                                            0x0030
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX                                                   2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0                                               0x0031
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1                                               0x0031
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2                                               0x0031
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3                                               0x0031
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4                                               0x0032
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5                                               0x0032
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6                                               0x0032
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7                                               0x0032
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC                                                             0x0033
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX                                                    2
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2                                                            0x0034
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX                                                   2
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP                                                             0x0036
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX                                                    2
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR                                               0x0037
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL                                                            0x0037
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX                                                   2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                               0x0037
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                               0x0038
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                               0x0038
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                               0x0038
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                               0x0038
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                               0x0039
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                               0x0039
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                               0x0039
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL                                                            0x0039
+#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX                                                   2
+#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED                                                              0x003a
+#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX                                                     2
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL                                                                0x003c
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX                                                       2
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID                                                        0x003d
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX                                               2
+#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL                                                               0x003e
+#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX                                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL                                                                0x003f
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX                                                       2
+#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL                                                          0x0040
+#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX                                                 2
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1:1
+// base address: 0x0
+#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED                                                              0x0042
+#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX                                                     2
+#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH                                                               0x0043
+#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX                                                      2
+#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL                                                                  0x0045
+#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX                                                         2
+#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL                                                           0x0046
+#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX                                                  2
+#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2                                                              0x0047
+#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX                                                     2
+#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL                                                              0x0048
+#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX                                                     2
+#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL                                                              0x0049
+#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX                                                     2
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0                                                              0x004a
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX                                                     2
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC                                                            0x004b
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX                                                   2
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2                                                           0x004c
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX                                                  2
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1:1
+// base address: 0x0
+#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL                                                                0x004f
+#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX                                                       2
+#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL                                                                 0x0050
+#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX                                                        2
+#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL                                                           0x0051
+#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX                                                  2
+#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2                                                                0x0052
+#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX                                                       2
+#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC                                                             0x0053
+#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX                                                    2
+#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP                                                         0x0054
+#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX                                                2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_0_RCC_ERR_LOG                                                                  0x0085
+#define regRCC_DEV0_EPF0_0_RCC_ERR_LOG_BASE_IDX                                                         2
+#define regRCC_DEV0_EPF0_0_RCC_ERR_LOG_1                                                                0x0085
+#define regRCC_DEV0_EPF0_0_RCC_ERR_LOG_1_BASE_IDX                                                       2
+#define regRCC_DEV0_EPF0_0_RCC_ERR_LOG_2                                                                0x0085
+#define regRCC_DEV0_EPF0_0_RCC_ERR_LOG_2_BASE_IDX                                                       2
+#define regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN                                                         0x00c0
+#define regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_BASE_IDX                                                2
+#define regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_1                                                       0x00c0
+#define regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_1_BASE_IDX                                              2
+#define regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_2                                                       0x00c0
+#define regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_2_BASE_IDX                                              2
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE                                                           0x00c3
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_BASE_IDX                                                  2
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_1                                                         0x00c3
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_1_BASE_IDX                                                2
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_2                                                         0x00c3
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_2_BASE_IDX                                                2
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED                                                          0x00c4
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_BASE_IDX                                                 2
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_1                                                        0x00c4
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_1_BASE_IDX                                               2
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_2                                                        0x00c4
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_2_BASE_IDX                                               2
+#define regRCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER                                                      0x00c5
+#define regRCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                             2
+#define regRCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1                                                    0x00c5
+#define regRCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1_BASE_IDX                                           2
+#define regRCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2                                                    0x00c5
+#define regRCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2_BASE_IDX                                           2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1:1
+// base address: 0x0
+#define regRCC_DEV0_0_RCC_ERR_INT_CNTL                                                                  0x0086
+#define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX                                                         2
+#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC                                                                0x0087
+#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX                                                       2
+#define regRCC_DEV0_0_RCC_RESET_EN                                                                      0x0088
+#define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX                                                             2
+#define regRCC_DEV0_0_RCC_VDM_SUPPORT                                                                   0x0089
+#define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX                                                          2
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0                                                            0x008a
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1                                                            0x008b
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_GPUIOV_REGION                                                                 0x008c
+#define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX                                                        2
+#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN                                                                 0x008d
+#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX                                                        2
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL                                                         0x008e
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX                                                2
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET                                                   0x008f
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX                                          2
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE                                                         0x008f
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX                                                2
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0                                                               0x00be
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX                                                      2
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1                                                               0x00bf
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX                                                      2
+#define regRCC_DEV0_0_RCC_BUS_CNTL                                                                      0x00c1
+#define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX                                                             2
+#define regRCC_DEV0_0_RCC_CONFIG_CNTL                                                                   0x00c2
+#define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX                                                          2
+#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE                                                                0x00c6
+#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX                                                       2
+#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE                                                              0x00c7
+#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX                                                     2
+#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE                                                          0x00c8
+#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX                                                 2
+#define regRCC_DEV0_0_RCC_XDMA_LO                                                                       0x00c9
+#define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX                                                              2
+#define regRCC_DEV0_0_RCC_XDMA_HI                                                                       0x00ca
+#define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX                                                              2
+#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC                                                         0x00cb
+#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX                                                2
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1                                                                  0x00cc
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX                                                         2
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST0                                                                  0x00cd
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX                                                         2
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST1                                                                  0x00ce
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX                                                         2
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2                                                                  0x00cf
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX                                                         2
+#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM                                                           0x00d0
+#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX                                                  2
+#define regRCC_DEV0_0_RCC_HOST_BUSNUM                                                                   0x00d1
+#define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX                                                          2
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI                                                            0x00d2
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO                                                            0x00d3
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI                                                            0x00d4
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO                                                            0x00d5
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI                                                            0x00d6
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO                                                            0x00d7
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI                                                            0x00d8
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO                                                            0x00d9
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0                                                              0x00da
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX                                                     2
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1                                                              0x00db
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX                                                     2
+#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL                                                                0x00dd
+#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX                                                       2
+#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL                                                                 0x00de
+#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX                                                        2
+#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE                                                        0x00df
+#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX                                               2
+#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL                                                              0x00e0
+#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX                                                     2
+#define regRCC_DEV0_0_RCC_MH_ARB_CNTL                                                                   0x00e1
+#define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX                                                          2
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1:1
+// base address: 0x0
+#define regBIF_BX0_CC_BIF_BX_STRAP0                                                                     0x00e2
+#define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX                                                            2
+#define regBIF_BX0_CC_BIF_BX_PINSTRAP0                                                                  0x00e4
+#define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX                                                         2
+#define regBIF_BX0_BIF_MM_INDACCESS_CNTL                                                                0x00e6
+#define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX                                                       2
+#define regBIF_BX0_BUS_CNTL                                                                             0x00e7
+#define regBIF_BX0_BUS_CNTL_BASE_IDX                                                                    2
+#define regBIF_BX0_BIF_SCRATCH0                                                                         0x00e8
+#define regBIF_BX0_BIF_SCRATCH0_BASE_IDX                                                                2
+#define regBIF_BX0_BIF_SCRATCH1                                                                         0x00e9
+#define regBIF_BX0_BIF_SCRATCH1_BASE_IDX                                                                2
+#define regBIF_BX0_BX_RESET_EN                                                                          0x00ed
+#define regBIF_BX0_BX_RESET_EN_BASE_IDX                                                                 2
+#define regBIF_BX0_MM_CFGREGS_CNTL                                                                      0x00ee
+#define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX                                                             2
+#define regBIF_BX0_BX_RESET_CNTL                                                                        0x00f0
+#define regBIF_BX0_BX_RESET_CNTL_BASE_IDX                                                               2
+#define regBIF_BX0_INTERRUPT_CNTL                                                                       0x00f1
+#define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX                                                              2
+#define regBIF_BX0_INTERRUPT_CNTL2                                                                      0x00f2
+#define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX                                                             2
+#define regBIF_BX0_CLKREQB_PAD_CNTL                                                                     0x00f8
+#define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX                                                            2
+#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC                                                            0x00fb
+#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX                                                   2
+#define regBIF_BX0_BIF_DOORBELL_CNTL                                                                    0x00fc
+#define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX                                                           2
+#define regBIF_BX0_BIF_DOORBELL_INT_CNTL                                                                0x00fd
+#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX                                                       2
+#define regBIF_BX0_BIF_FB_EN                                                                            0x00ff
+#define regBIF_BX0_BIF_FB_EN_BASE_IDX                                                                   2
+#define regBIF_BX0_BIF_INTR_CNTL                                                                        0x0100
+#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX                                                               2
+#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF                                                             0x0109
+#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX                                                    2
+#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF                                                             0x010a
+#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX                                                    2
+#define regBIF_BX0_MEM_TYPE_CNTL                                                                        0x0111
+#define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX                                                               2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL                                                               0x0113
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX                                                      2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0                                                                  0x0114
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1                                                                  0x0115
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2                                                                  0x0116
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3                                                                  0x0117
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4                                                                  0x0118
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5                                                                  0x0119
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6                                                                  0x011a
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7                                                                  0x011b
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8                                                                  0x011c
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9                                                                  0x011d
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10                                                                 0x011e
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX                                                        2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11                                                                 0x011f
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX                                                        2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12                                                                 0x0120
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX                                                        2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13                                                                 0x0121
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX                                                        2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14                                                                 0x0122
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX                                                        2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15                                                                 0x0123
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX                                                        2
+#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL                                                             0x012d
+#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX                                                    2
+#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL                                                             0x012e
+#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX                                                    2
+#define regBIF_BX0_BIF_RB_CNTL                                                                          0x012f
+#define regBIF_BX0_BIF_RB_CNTL_BASE_IDX                                                                 2
+#define regBIF_BX0_BIF_RB_BASE                                                                          0x0130
+#define regBIF_BX0_BIF_RB_BASE_BASE_IDX                                                                 2
+#define regBIF_BX0_BIF_RB_RPTR                                                                          0x0131
+#define regBIF_BX0_BIF_RB_RPTR_BASE_IDX                                                                 2
+#define regBIF_BX0_BIF_RB_WPTR                                                                          0x0132
+#define regBIF_BX0_BIF_RB_WPTR_BASE_IDX                                                                 2
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI                                                                  0x0133
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX                                                         2
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO                                                                  0x0134
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX                                                         2
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1:1
+// base address: 0x0
+#define regBIF_BX_PF0_BIF_BME_STATUS                                                                    0x00eb
+#define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX                                                           2
+#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG                                                                0x00ec
+#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX                                                       2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                              0x00f3
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                                     2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                               0x00f4
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                                      2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL                                                   0x00f5
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                          2
+#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL                                                      0x00f6
+#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                             2
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL                                                      0x00f7
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                             2
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                                 0x00f9
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                                        2
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                            0x00fa
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                                   2
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ                                                            0x0104
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ_BASE_IDX                                                   2
+#define regBIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ                                                       0x0105
+#define regBIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ_BASE_IDX                                              2
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ                                                                 0x0106
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX                                                        2
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE                                                                0x0107
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX                                                       2
+#define regBIF_BX_PF0_BIF_TRANS_PENDING                                                                 0x0108
+#define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX                                                        2
+#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS                                                          0x0112
+#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                                 2
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO                                                        0x0400
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_1                                                      0x0400
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_2                                                      0x0400
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI                                                        0x0401
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_1                                                      0x0401
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_2                                                      0x0401
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA                                                       0x0402
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                              3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_1                                                     0x0402
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_1_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_2                                                     0x0402
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_2_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL                                                        0x0403
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_1                                                      0x0403
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_2                                                      0x0403
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO                                                        0x0404
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_1                                                      0x0404
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_2                                                      0x0404
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI                                                        0x0405
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_1                                                      0x0405
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_2                                                      0x0405
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA                                                       0x0406
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                              3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_1                                                     0x0406
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_1_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_2                                                     0x0406
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_2_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL                                                        0x0407
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_1                                                      0x0407
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_2                                                      0x0407
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO                                                        0x0408
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_1                                                      0x0408
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_2                                                      0x0408
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI                                                        0x0409
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_1                                                      0x0409
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_2                                                      0x0409
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA                                                       0x040a
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                              3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_1                                                     0x040a
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_1_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_2                                                     0x040a
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_2_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL                                                        0x040b
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_1                                                      0x040b
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_2                                                      0x040b
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO                                                        0x040c
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_1                                                      0x040c
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_2                                                      0x040c
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI                                                        0x040d
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_1                                                      0x040d
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_2                                                      0x040d
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA                                                       0x040e
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                              3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_1                                                     0x040e
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_1_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_2                                                     0x040e
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_2_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL                                                        0x040f
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_BASE_IDX                                               3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_1                                                      0x040f
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_1_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_2                                                      0x040f
+#define regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_2_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_PBA                                                                  0x0800
+#define regRCC_DEV0_EPF0_0_GFXMSIX_PBA_BASE_IDX                                                         3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_PBA_1                                                                0x0800
+#define regRCC_DEV0_EPF0_0_GFXMSIX_PBA_1_BASE_IDX                                                       3
+#define regRCC_DEV0_EPF0_0_GFXMSIX_PBA_2                                                                0x0800
+#define regRCC_DEV0_EPF0_0_GFXMSIX_PBA_2_BASE_IDX                                                       3
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+// base address: 0x1400000
+#define regGDC0_NGDC_SDP_PORT_CTRL                                                                      0x4f0ae2
+#define regGDC0_NGDC_SDP_PORT_CTRL_BASE_IDX                                                             3
+#define regGDC0_SHUB_REGS_IF_CTL                                                                        0x4f0ae3
+#define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX                                                               3
+#define regGDC0_NGDC_SDP_PORT_CTRL_SOCCLK                                                               0x4f0aed
+#define regGDC0_NGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX                                                      3
+#define regGDC0_NGDC_SDP_PORT_CTRL1_SOCCLK                                                              0x4f0aee
+#define regGDC0_NGDC_SDP_PORT_CTRL1_SOCCLK_BASE_IDX                                                     3
+#define regGDC0_NBIF_GFX_DOORBELL_STATUS                                                                0x4f0aef
+#define regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX                                                       3
+#define regGDC0_BIF_SDMA0_DOORBELL_RANGE                                                                0x4f0af0
+#define regGDC0_BIF_SDMA0_DOORBELL_RANGE_BASE_IDX                                                       3
+#define regGDC0_BIF_IH_DOORBELL_RANGE                                                                   0x4f0af2
+#define regGDC0_BIF_IH_DOORBELL_RANGE_BASE_IDX                                                          3
+#define regGDC0_BIF_VCN0_DOORBELL_RANGE                                                                 0x4f0af3
+#define regGDC0_BIF_VCN0_DOORBELL_RANGE_BASE_IDX                                                        3
+#define regGDC0_BIF_RLC_DOORBELL_RANGE                                                                  0x4f0af5
+#define regGDC0_BIF_RLC_DOORBELL_RANGE_BASE_IDX                                                         3
+#define regGDC0_ATDMA_MISC_CNTL                                                                         0x4f0afd
+#define regGDC0_ATDMA_MISC_CNTL_BASE_IDX                                                                3
+#define regGDC0_BIF_DOORBELL_FENCE_CNTL                                                                 0x4f0afe
+#define regGDC0_BIF_DOORBELL_FENCE_CNTL_BASE_IDX                                                        3
+#define regGDC0_S2A_MISC_CNTL                                                                           0x4f0aff
+#define regGDC0_S2A_MISC_CNTL_BASE_IDX                                                                  3
+#define regGDC0_SHUBCLK_DPM_CTRL                                                                        0x4f0b1b
+#define regGDC0_SHUBCLK_DPM_CTRL_BASE_IDX                                                               3
+#define regGDC0_SHUBCLK_DPM_WR_WEIGHT                                                                   0x4f0b1c
+#define regGDC0_SHUBCLK_DPM_WR_WEIGHT_BASE_IDX                                                          3
+#define regGDC0_SHUBCLK_DPM_RD_WEIGHT                                                                   0x4f0b1d
+#define regGDC0_SHUBCLK_DPM_RD_WEIGHT_BASE_IDX                                                          3
+#define regGDC0_SHUBCLK_DPM_WR_CNT                                                                      0x4f0b1e
+#define regGDC0_SHUBCLK_DPM_WR_CNT_BASE_IDX                                                             3
+#define regGDC0_SHUBCLK_DPM_RD_CNT                                                                      0x4f0b1f
+#define regGDC0_SHUBCLK_DPM_RD_CNT_BASE_IDX                                                             3
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect
+// base address: 0x1400000
+#define regOBFF_EMU_CFG_SOCCLK                                                                          0x4f3c10
+#define regOBFF_EMU_CFG_SOCCLK_BASE_IDX                                                                 3
+#define regHST_CLK0_SW0_CL0_CNTL                                                                        0x4f3d40
+#define regHST_CLK0_SW0_CL0_CNTL_BASE_IDX                                                               3
+#define regHST_CLK0_SW0_CL1_CNTL                                                                        0x4f3d41
+#define regHST_CLK0_SW0_CL1_CNTL_BASE_IDX                                                               3
+#define regHST_CLK0_SW0_CL2_CNTL                                                                        0x4f3d42
+#define regHST_CLK0_SW0_CL2_CNTL_BASE_IDX                                                               3
+#define regHST_CLK0_SW1_CL0_CNTL                                                                        0x4f3d60
+#define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX                                                               3
+#define regHST_CLK0_SW1_CL1_CNTL                                                                        0x4f3d61
+#define regHST_CLK0_SW1_CL1_CNTL_BASE_IDX                                                               3
+#define regOBFF_EMU_CFG_SHUBCLK                                                                         0x4f4010
+#define regOBFF_EMU_CFG_SHUBCLK_BASE_IDX                                                                3
+#define regHST_CLK1_SW0_CL0_CNTL                                                                        0x4f4140
+#define regHST_CLK1_SW0_CL0_CNTL_BASE_IDX                                                               3
+#define regOBFF_EMU_CFG_NICCLK                                                                          0x4f4410
+#define regOBFF_EMU_CFG_NICCLK_BASE_IDX                                                                 3
+#define regHST_CLK2_SW0_CL0_CNTL                                                                        0x4f4540
+#define regHST_CLK2_SW0_CL0_CNTL_BASE_IDX                                                               3
+
+
+// addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk
+// base address: 0x1400000
+#define regGDCSOC_ERR_RSP_CNTL                                                                          0x4f5c00
+#define regGDCSOC_ERR_RSP_CNTL_BASE_IDX                                                                 3
+#define regGDCSOC_RAS_CENTRAL_STATUS                                                                    0x4f5c10
+#define regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX                                                           3
+#define regGDCSOC_RAS_LEAF0_CTRL                                                                        0x4f5c20
+#define regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF1_CTRL                                                                        0x4f5c21
+#define regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF2_CTRL                                                                        0x4f5c22
+#define regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF3_CTRL                                                                        0x4f5c23
+#define regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF4_CTRL                                                                        0x4f5c24
+#define regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF5_CTRL                                                                        0x4f5c25
+#define regGDCSOC_RAS_LEAF5_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF0_STATUS                                                                      0x4f5c30
+#define regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF1_STATUS                                                                      0x4f5c31
+#define regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF2_STATUS                                                                      0x4f5c32
+#define regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF3_STATUS                                                                      0x4f5c33
+#define regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF4_STATUS                                                                      0x4f5c34
+#define regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF5_STATUS                                                                      0x4f5c35
+#define regGDCSOC_RAS_LEAF5_STATUS_BASE_IDX                                                             3
+#define regGDCSHUB_ERR_RSP_CNTL                                                                         0x4f5e00
+#define regGDCSHUB_ERR_RSP_CNTL_BASE_IDX                                                                3
+#define regGDCSHUB_RAS_CENTRAL_STATUS                                                                   0x4f5e10
+#define regGDCSHUB_RAS_CENTRAL_STATUS_BASE_IDX                                                          3
+#define regGDCSHUB_RAS_LEAF0_CTRL                                                                       0x4f5e20
+#define regGDCSHUB_RAS_LEAF0_CTRL_BASE_IDX                                                              3
+#define regGDCSHUB_RAS_LEAF1_CTRL                                                                       0x4f5e21
+#define regGDCSHUB_RAS_LEAF1_CTRL_BASE_IDX                                                              3
+#define regGDCSHUB_RAS_LEAF2_CTRL                                                                       0x4f5e22
+#define regGDCSHUB_RAS_LEAF2_CTRL_BASE_IDX                                                              3
+#define regGDCSHUB_RAS_LEAF3_CTRL                                                                       0x4f5e23
+#define regGDCSHUB_RAS_LEAF3_CTRL_BASE_IDX                                                              3
+#define regGDCSHUB_RAS_LEAF0_STATUS                                                                     0x4f5e30
+#define regGDCSHUB_RAS_LEAF0_STATUS_BASE_IDX                                                            3
+#define regGDCSHUB_RAS_LEAF1_STATUS                                                                     0x4f5e31
+#define regGDCSHUB_RAS_LEAF1_STATUS_BASE_IDX                                                            3
+#define regGDCSHUB_RAS_LEAF2_STATUS                                                                     0x4f5e32
+#define regGDCSHUB_RAS_LEAF2_STATUS_BASE_IDX                                                            3
+#define regGDCSHUB_RAS_LEAF3_STATUS                                                                     0x4f5e33
+#define regGDCSHUB_RAS_LEAF3_STATUS_BASE_IDX                                                            3
+#define regGDCNIC_ERR_RSP_CNTL                                                                          0x4f6000
+#define regGDCNIC_ERR_RSP_CNTL_BASE_IDX                                                                 3
+#define regGDCNIC_RAS_CENTRAL_STATUS                                                                    0x4f6010
+#define regGDCNIC_RAS_CENTRAL_STATUS_BASE_IDX                                                           3
+#define regGDCNIC_RAS_LEAF0_CTRL                                                                        0x4f6020
+#define regGDCNIC_RAS_LEAF0_CTRL_BASE_IDX                                                               3
+#define regGDCNIC_RAS_LEAF1_CTRL                                                                        0x4f6021
+#define regGDCNIC_RAS_LEAF1_CTRL_BASE_IDX                                                               3
+#define regGDCNIC_RAS_LEAF2_CTRL                                                                        0x4f6022
+#define regGDCNIC_RAS_LEAF2_CTRL_BASE_IDX                                                               3
+#define regGDCNIC_RAS_LEAF0_STATUS                                                                      0x4f6030
+#define regGDCNIC_RAS_LEAF0_STATUS_BASE_IDX                                                             3
+#define regGDCNIC_RAS_LEAF1_STATUS                                                                      0x4f6031
+#define regGDCNIC_RAS_LEAF1_STATUS_BASE_IDX                                                             3
+#define regGDCNIC_RAS_LEAF2_STATUS                                                                      0x4f6032
+#define regGDCNIC_RAS_LEAF2_STATUS_BASE_IDX                                                             3
+
+
+// addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC
+// base address: 0x1400000
+#define regSHUB_PF_FLR_RST                                                                              0x4f7800
+#define regSHUB_PF_FLR_RST_BASE_IDX                                                                     3
+#define regSHUB_GFX_DRV_VPU_RST                                                                         0x4f7801
+#define regSHUB_GFX_DRV_VPU_RST_BASE_IDX                                                                3
+#define regSHUB_LINK_RESET                                                                              0x4f7802
+#define regSHUB_LINK_RESET_BASE_IDX                                                                     3
+#define regSHUB_HARD_RST_CTRL                                                                           0x4f7810
+#define regSHUB_HARD_RST_CTRL_BASE_IDX                                                                  3
+#define regSHUB_SOFT_RST_CTRL                                                                           0x4f7811
+#define regSHUB_SOFT_RST_CTRL_BASE_IDX                                                                  3
+#define regSHUB_SDP_PORT_RST                                                                            0x4f7812
+#define regSHUB_SDP_PORT_RST_BASE_IDX                                                                   3
+#define regSHUB_RST_MISC_TRL                                                                            0x4f7813
+#define regSHUB_RST_MISC_TRL_BASE_IDX                                                                   3
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+// base address: 0x10100000
+#define regBIF_CFG_DEV0_RC0_VENDOR_ID                                                                   0x0000
+#define regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_DEVICE_ID                                                                   0x0000
+#define regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_COMMAND                                                                     0x0001
+#define regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC0_STATUS                                                                      0x0001
+#define regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX                                                             5
+#define regBIF_CFG_DEV0_RC0_REVISION_ID                                                                 0x0002
+#define regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE                                                              0x0002
+#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_SUB_CLASS                                                                   0x0002
+#define regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_BASE_CLASS                                                                  0x0002
+#define regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC0_CACHE_LINE                                                                  0x0003
+#define regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC0_LATENCY                                                                     0x0003
+#define regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC0_HEADER                                                                      0x0003
+#define regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX                                                             5
+#define regBIF_CFG_DEV0_RC0_BIST                                                                        0x0003
+#define regBIF_CFG_DEV0_RC0_BIST_BASE_IDX                                                               5
+#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1                                                                 0x0004
+#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2                                                                 0x0005
+#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY                                                      0x0006
+#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT                                                               0x0007
+#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS                                                            0x0007
+#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT                                                              0x0008
+#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT                                                             0x0009
+#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER                                                             0x000a
+#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER                                                            0x000b
+#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI                                                            0x000c
+#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_CAP_PTR                                                                     0x000d
+#define regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR                                                               0x000e
+#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE                                                              0x000f
+#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN                                                               0x000f
+#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL                                                             0x000f
+#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL                                                             0x0010
+#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST                                                                0x0014
+#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_PMI_CAP                                                                     0x0014
+#define regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL                                                             0x0015
+#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST                                                               0x0016
+#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_CAP                                                                    0x0016
+#define regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_DEVICE_CAP                                                                  0x0017
+#define regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL                                                                 0x0018
+#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS                                                               0x0018
+#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_LINK_CAP                                                                    0x0019
+#define regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL                                                                   0x001a
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS                                                                 0x001a
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_SLOT_CAP                                                                    0x001b
+#define regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_SLOT_CNTL                                                                   0x001c
+#define regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_SLOT_STATUS                                                                 0x001c
+#define regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_ROOT_CNTL                                                                   0x001d
+#define regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_ROOT_CAP                                                                    0x001d
+#define regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_ROOT_STATUS                                                                 0x001e
+#define regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2                                                                 0x001f
+#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2                                                                0x0020
+#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2                                                              0x0020
+#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_LINK_CAP2                                                                   0x0021
+#define regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL2                                                                  0x0022
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS2                                                                0x0022
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_SLOT_CAP2                                                                   0x0023
+#define regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2                                                                  0x0024
+#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2                                                                0x0024
+#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST                                                                0x0028
+#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL                                                                0x0028
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO                                                             0x0029
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI                                                             0x002a
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA                                                                0x002a
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA                                                            0x002a
+#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64                                                             0x002b
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64                                                         0x002b
+#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST                                                               0x0030
+#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_SSID_CAP                                                                    0x0031
+#define regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST                                                            0x0032
+#define regBIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_MSI_MAP_CAP                                                                 0x0032
+#define regBIF_CFG_DEV0_RC0_MSI_MAP_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                           0x0040
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR                                                    0x0041
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1                                                       0x0042
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2                                                       0x0043
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST                                                        0x0044
+#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1                                                       0x0045
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2                                                       0x0046
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL                                                           0x0047
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS                                                         0x0047
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP                                                       0x0048
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL                                                      0x0049
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS                                                    0x004a
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP                                                       0x004b
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL                                                      0x004c
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS                                                    0x004d
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                            0x0050
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1                                                     0x0051
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2                                                     0x0052
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                               0x0054
+#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS                                                      0x0055
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK                                                        0x0056
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY                                                    0x0057
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS                                                        0x0058
+#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK                                                          0x0059
+#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL                                                       0x005a
+#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0                                                               0x005b
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1                                                               0x005c
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2                                                               0x005d
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3                                                               0x005e
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD                                                           0x005f
+#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS                                                        0x0060
+#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID                                                             0x0061
+#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0                                                        0x0062
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1                                                        0x0063
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2                                                        0x0064
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3                                                        0x0065
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST                                                 0x009c
+#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3                                                             0x009d
+#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS                                                      0x009e
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL                                               0x009f
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL                                               0x009f
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL                                               0x00a0
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL                                               0x00a0
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL                                               0x00a1
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL                                               0x00a1
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL                                               0x00a2
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL                                               0x00a2
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL                                               0x00a3
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL                                               0x00a3
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL                                              0x00a4
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL                                              0x00a4
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL                                              0x00a5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL                                              0x00a5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL                                              0x00a6
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL                                              0x00a6
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST                                                       0x00a8
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP                                                                0x00a9
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL                                                               0x00a9
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST                                                       0x0100
+#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP                                                       0x0101
+#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS                                                    0x0102
+#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST                                                  0x0104
+#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT                                                               0x0105
+#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT                                                              0x0106
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT                                                            0x0107
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                           0x0108
+#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT                                            0x0109
+#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT                                            0x010a
+#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT                                               0x010c
+#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT                                               0x010c
+#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT                                               0x010c
+#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT                                               0x010c
+#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT                                               0x010d
+#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT                                               0x010d
+#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT                                               0x010d
+#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT                                               0x010d
+#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT                                               0x010e
+#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT                                               0x010e
+#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT                                              0x010e
+#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT                                              0x010e
+#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT                                              0x010f
+#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT                                              0x010f
+#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT                                              0x010f
+#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT                                              0x010f
+#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST                                                 0x0110
+#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP                                                          0x0111
+#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS                                                       0x0111
+#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL                                                  0x0112
+#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS                                                0x0112
+#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL                                                  0x0113
+#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS                                                0x0113
+#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL                                                  0x0114
+#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS                                                0x0114
+#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL                                                  0x0115
+#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS                                                0x0115
+#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL                                                  0x0116
+#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS                                                0x0116
+#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL                                                  0x0117
+#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS                                                0x0117
+#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL                                                  0x0118
+#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS                                                0x0118
+#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL                                                  0x0119
+#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS                                                0x0119
+#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL                                                  0x011a
+#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS                                                0x011a
+#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL                                                  0x011b
+#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS                                                0x011b
+#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL                                                 0x011c
+#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS                                               0x011c
+#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL                                                 0x011d
+#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS                                               0x011d
+#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL                                                 0x011e
+#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS                                               0x011e
+#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL                                                 0x011f
+#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS                                               0x011f
+#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL                                                 0x0120
+#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS                                               0x0120
+#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL                                                 0x0121
+#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS                                               0x0121
+#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                      5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+// base address: 0x10101000
+#define regBIF_CFG_DEV1_RC0_VENDOR_ID                                                                   0x0400
+#define regBIF_CFG_DEV1_RC0_VENDOR_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC0_DEVICE_ID                                                                   0x0400
+#define regBIF_CFG_DEV1_RC0_DEVICE_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC0_COMMAND                                                                     0x0401
+#define regBIF_CFG_DEV1_RC0_COMMAND_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_RC0_STATUS                                                                      0x0401
+#define regBIF_CFG_DEV1_RC0_STATUS_BASE_IDX                                                             5
+#define regBIF_CFG_DEV1_RC0_REVISION_ID                                                                 0x0402
+#define regBIF_CFG_DEV1_RC0_REVISION_ID_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC0_PROG_INTERFACE                                                              0x0402
+#define regBIF_CFG_DEV1_RC0_PROG_INTERFACE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_RC0_SUB_CLASS                                                                   0x0402
+#define regBIF_CFG_DEV1_RC0_SUB_CLASS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC0_BASE_CLASS                                                                  0x0402
+#define regBIF_CFG_DEV1_RC0_BASE_CLASS_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_RC0_CACHE_LINE                                                                  0x0403
+#define regBIF_CFG_DEV1_RC0_CACHE_LINE_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_RC0_LATENCY                                                                     0x0403
+#define regBIF_CFG_DEV1_RC0_LATENCY_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_RC0_HEADER                                                                      0x0403
+#define regBIF_CFG_DEV1_RC0_HEADER_BASE_IDX                                                             5
+#define regBIF_CFG_DEV1_RC0_BIST                                                                        0x0403
+#define regBIF_CFG_DEV1_RC0_BIST_BASE_IDX                                                               5
+#define regBIF_CFG_DEV1_RC0_BASE_ADDR_1                                                                 0x0404
+#define regBIF_CFG_DEV1_RC0_BASE_ADDR_1_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC0_BASE_ADDR_2                                                                 0x0405
+#define regBIF_CFG_DEV1_RC0_BASE_ADDR_2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY                                                      0x0406
+#define regBIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_RC0_IO_BASE_LIMIT                                                               0x0407
+#define regBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_SECONDARY_STATUS                                                            0x0407
+#define regBIF_CFG_DEV1_RC0_SECONDARY_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC0_MEM_BASE_LIMIT                                                              0x0408
+#define regBIF_CFG_DEV1_RC0_MEM_BASE_LIMIT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_RC0_PREF_BASE_LIMIT                                                             0x0409
+#define regBIF_CFG_DEV1_RC0_PREF_BASE_LIMIT_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC0_PREF_BASE_UPPER                                                             0x040a
+#define regBIF_CFG_DEV1_RC0_PREF_BASE_UPPER_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER                                                            0x040b
+#define regBIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI                                                            0x040c
+#define regBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC0_CAP_PTR                                                                     0x040d
+#define regBIF_CFG_DEV1_RC0_CAP_PTR_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_RC0_ROM_BASE_ADDR                                                               0x040e
+#define regBIF_CFG_DEV1_RC0_ROM_BASE_ADDR_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_INTERRUPT_LINE                                                              0x040f
+#define regBIF_CFG_DEV1_RC0_INTERRUPT_LINE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_RC0_INTERRUPT_PIN                                                               0x040f
+#define regBIF_CFG_DEV1_RC0_INTERRUPT_PIN_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL                                                             0x040f
+#define regBIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL                                                             0x0410
+#define regBIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC0_PMI_CAP_LIST                                                                0x0414
+#define regBIF_CFG_DEV1_RC0_PMI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC0_PMI_CAP                                                                     0x0414
+#define regBIF_CFG_DEV1_RC0_PMI_CAP_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_RC0_PMI_STATUS_CNTL                                                             0x0415
+#define regBIF_CFG_DEV1_RC0_PMI_STATUS_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC0_PCIE_CAP_LIST                                                               0x0416
+#define regBIF_CFG_DEV1_RC0_PCIE_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_CAP                                                                    0x0416
+#define regBIF_CFG_DEV1_RC0_PCIE_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_RC0_DEVICE_CAP                                                                  0x0417
+#define regBIF_CFG_DEV1_RC0_DEVICE_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_RC0_DEVICE_CNTL                                                                 0x0418
+#define regBIF_CFG_DEV1_RC0_DEVICE_CNTL_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC0_DEVICE_STATUS                                                               0x0418
+#define regBIF_CFG_DEV1_RC0_DEVICE_STATUS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_LINK_CAP                                                                    0x0419
+#define regBIF_CFG_DEV1_RC0_LINK_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_RC0_LINK_CNTL                                                                   0x041a
+#define regBIF_CFG_DEV1_RC0_LINK_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC0_LINK_STATUS                                                                 0x041a
+#define regBIF_CFG_DEV1_RC0_LINK_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC0_SLOT_CAP                                                                    0x041b
+#define regBIF_CFG_DEV1_RC0_SLOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_RC0_SLOT_CNTL                                                                   0x041c
+#define regBIF_CFG_DEV1_RC0_SLOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC0_SLOT_STATUS                                                                 0x041c
+#define regBIF_CFG_DEV1_RC0_SLOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC0_ROOT_CNTL                                                                   0x041d
+#define regBIF_CFG_DEV1_RC0_ROOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC0_ROOT_CAP                                                                    0x041d
+#define regBIF_CFG_DEV1_RC0_ROOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_RC0_ROOT_STATUS                                                                 0x041e
+#define regBIF_CFG_DEV1_RC0_ROOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC0_DEVICE_CAP2                                                                 0x041f
+#define regBIF_CFG_DEV1_RC0_DEVICE_CAP2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC0_DEVICE_CNTL2                                                                0x0420
+#define regBIF_CFG_DEV1_RC0_DEVICE_CNTL2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC0_DEVICE_STATUS2                                                              0x0420
+#define regBIF_CFG_DEV1_RC0_DEVICE_STATUS2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_RC0_LINK_CAP2                                                                   0x0421
+#define regBIF_CFG_DEV1_RC0_LINK_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC0_LINK_CNTL2                                                                  0x0422
+#define regBIF_CFG_DEV1_RC0_LINK_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_RC0_LINK_STATUS2                                                                0x0422
+#define regBIF_CFG_DEV1_RC0_LINK_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC0_SLOT_CAP2                                                                   0x0423
+#define regBIF_CFG_DEV1_RC0_SLOT_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC0_SLOT_CNTL2                                                                  0x0424
+#define regBIF_CFG_DEV1_RC0_SLOT_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_RC0_SLOT_STATUS2                                                                0x0424
+#define regBIF_CFG_DEV1_RC0_SLOT_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC0_MSI_CAP_LIST                                                                0x0428
+#define regBIF_CFG_DEV1_RC0_MSI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC0_MSI_MSG_CNTL                                                                0x0428
+#define regBIF_CFG_DEV1_RC0_MSI_MSG_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO                                                             0x0429
+#define regBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI                                                             0x042a
+#define regBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC0_MSI_MSG_DATA                                                                0x042a
+#define regBIF_CFG_DEV1_RC0_MSI_MSG_DATA_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA                                                            0x042a
+#define regBIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC0_MSI_MSG_DATA_64                                                             0x042b
+#define regBIF_CFG_DEV1_RC0_MSI_MSG_DATA_64_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64                                                         0x042b
+#define regBIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV1_RC0_SSID_CAP_LIST                                                               0x0430
+#define regBIF_CFG_DEV1_RC0_SSID_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_SSID_CAP                                                                    0x0431
+#define regBIF_CFG_DEV1_RC0_SSID_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST                                                            0x0432
+#define regBIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC0_MSI_MAP_CAP                                                                 0x0432
+#define regBIF_CFG_DEV1_RC0_MSI_MAP_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                           0x0440
+#define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR                                                    0x0441
+#define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1                                                       0x0442
+#define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2                                                       0x0443
+#define regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST                                                        0x0444
+#define regBIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1                                                       0x0445
+#define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2                                                       0x0446
+#define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL                                                           0x0447
+#define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS                                                         0x0447
+#define regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS_BASE_IDX                                                5
+#define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP                                                       0x0448
+#define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL                                                      0x0449
+#define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS                                                    0x044a
+#define regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP                                                       0x044b
+#define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL                                                      0x044c
+#define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS                                                    0x044d
+#define regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                            0x0450
+#define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1                                                     0x0451
+#define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2                                                     0x0452
+#define regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                               0x0454
+#define regBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS                                                      0x0455
+#define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK                                                        0x0456
+#define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY                                                    0x0457
+#define regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS                                                        0x0458
+#define regBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK                                                          0x0459
+#define regBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL                                                       0x045a
+#define regBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG0                                                               0x045b
+#define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG0_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG1                                                               0x045c
+#define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG1_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG2                                                               0x045d
+#define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG3                                                               0x045e
+#define regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG3_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD                                                           0x045f
+#define regBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS                                                        0x0460
+#define regBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID                                                             0x0461
+#define regBIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0                                                        0x0462
+#define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1                                                        0x0463
+#define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2                                                        0x0464
+#define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3                                                        0x0465
+#define regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST                                                 0x049c
+#define regBIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3                                                             0x049d
+#define regBIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS                                                      0x049e
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL                                               0x049f
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL                                               0x049f
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL                                               0x04a0
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL                                               0x04a0
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL                                               0x04a1
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL                                               0x04a1
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL                                               0x04a2
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL                                               0x04a2
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL                                               0x04a3
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL                                               0x04a3
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL                                              0x04a4
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL                                              0x04a4
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL                                              0x04a5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL                                              0x04a5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL                                              0x04a6
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL                                              0x04a6
+#define regBIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST                                                       0x04a8
+#define regBIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC0_PCIE_ACS_CAP                                                                0x04a9
+#define regBIF_CFG_DEV1_RC0_PCIE_ACS_CAP_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC0_PCIE_ACS_CNTL                                                               0x04a9
+#define regBIF_CFG_DEV1_RC0_PCIE_ACS_CNTL_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST                                                       0x0500
+#define regBIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP                                                       0x0501
+#define regBIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS                                                    0x0502
+#define regBIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST                                                  0x0504
+#define regBIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC0_LINK_CAP_16GT                                                               0x0505
+#define regBIF_CFG_DEV1_RC0_LINK_CAP_16GT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC0_LINK_CNTL_16GT                                                              0x0506
+#define regBIF_CFG_DEV1_RC0_LINK_CNTL_16GT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_RC0_LINK_STATUS_16GT                                                            0x0507
+#define regBIF_CFG_DEV1_RC0_LINK_STATUS_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                           0x0508
+#define regBIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT                                            0x0509
+#define regBIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT                                            0x050a
+#define regBIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT                                               0x050c
+#define regBIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT                                               0x050c
+#define regBIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT                                               0x050c
+#define regBIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT                                               0x050c
+#define regBIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT                                               0x050d
+#define regBIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT                                               0x050d
+#define regBIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT                                               0x050d
+#define regBIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT                                               0x050d
+#define regBIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT                                               0x050e
+#define regBIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT                                               0x050e
+#define regBIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT                                              0x050e
+#define regBIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT                                              0x050e
+#define regBIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT                                              0x050f
+#define regBIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT                                              0x050f
+#define regBIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT                                              0x050f
+#define regBIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT                                              0x050f
+#define regBIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST                                                 0x0510
+#define regBIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC0_MARGINING_PORT_CAP                                                          0x0511
+#define regBIF_CFG_DEV1_RC0_MARGINING_PORT_CAP_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS                                                       0x0511
+#define regBIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL                                                  0x0512
+#define regBIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS                                                0x0512
+#define regBIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL                                                  0x0513
+#define regBIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS                                                0x0513
+#define regBIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL                                                  0x0514
+#define regBIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS                                                0x0514
+#define regBIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL                                                  0x0515
+#define regBIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS                                                0x0515
+#define regBIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL                                                  0x0516
+#define regBIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS                                                0x0516
+#define regBIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL                                                  0x0517
+#define regBIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS                                                0x0517
+#define regBIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL                                                  0x0518
+#define regBIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS                                                0x0518
+#define regBIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL                                                  0x0519
+#define regBIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS                                                0x0519
+#define regBIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL                                                  0x051a
+#define regBIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS                                                0x051a
+#define regBIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL                                                  0x051b
+#define regBIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS                                                0x051b
+#define regBIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL                                                 0x051c
+#define regBIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS                                               0x051c
+#define regBIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL                                                 0x051d
+#define regBIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS                                               0x051d
+#define regBIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL                                                 0x051e
+#define regBIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS                                               0x051e
+#define regBIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL                                                 0x051f
+#define regBIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS                                               0x051f
+#define regBIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL                                                 0x0520
+#define regBIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS                                               0x0520
+#define regBIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL                                                 0x0521
+#define regBIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS                                               0x0521
+#define regBIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                      5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp
+// base address: 0x10102000
+#define regBIF_CFG_DEV2_RC0_VENDOR_ID                                                                   0x0800
+#define regBIF_CFG_DEV2_RC0_VENDOR_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC0_DEVICE_ID                                                                   0x0800
+#define regBIF_CFG_DEV2_RC0_DEVICE_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC0_COMMAND                                                                     0x0801
+#define regBIF_CFG_DEV2_RC0_COMMAND_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_RC0_STATUS                                                                      0x0801
+#define regBIF_CFG_DEV2_RC0_STATUS_BASE_IDX                                                             5
+#define regBIF_CFG_DEV2_RC0_REVISION_ID                                                                 0x0802
+#define regBIF_CFG_DEV2_RC0_REVISION_ID_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC0_PROG_INTERFACE                                                              0x0802
+#define regBIF_CFG_DEV2_RC0_PROG_INTERFACE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_RC0_SUB_CLASS                                                                   0x0802
+#define regBIF_CFG_DEV2_RC0_SUB_CLASS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC0_BASE_CLASS                                                                  0x0802
+#define regBIF_CFG_DEV2_RC0_BASE_CLASS_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_RC0_CACHE_LINE                                                                  0x0803
+#define regBIF_CFG_DEV2_RC0_CACHE_LINE_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_RC0_LATENCY                                                                     0x0803
+#define regBIF_CFG_DEV2_RC0_LATENCY_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_RC0_HEADER                                                                      0x0803
+#define regBIF_CFG_DEV2_RC0_HEADER_BASE_IDX                                                             5
+#define regBIF_CFG_DEV2_RC0_BIST                                                                        0x0803
+#define regBIF_CFG_DEV2_RC0_BIST_BASE_IDX                                                               5
+#define regBIF_CFG_DEV2_RC0_BASE_ADDR_1                                                                 0x0804
+#define regBIF_CFG_DEV2_RC0_BASE_ADDR_1_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC0_BASE_ADDR_2                                                                 0x0805
+#define regBIF_CFG_DEV2_RC0_BASE_ADDR_2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY                                                      0x0806
+#define regBIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_RC0_IO_BASE_LIMIT                                                               0x0807
+#define regBIF_CFG_DEV2_RC0_IO_BASE_LIMIT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_SECONDARY_STATUS                                                            0x0807
+#define regBIF_CFG_DEV2_RC0_SECONDARY_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC0_MEM_BASE_LIMIT                                                              0x0808
+#define regBIF_CFG_DEV2_RC0_MEM_BASE_LIMIT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_RC0_PREF_BASE_LIMIT                                                             0x0809
+#define regBIF_CFG_DEV2_RC0_PREF_BASE_LIMIT_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC0_PREF_BASE_UPPER                                                             0x080a
+#define regBIF_CFG_DEV2_RC0_PREF_BASE_UPPER_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER                                                            0x080b
+#define regBIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI                                                            0x080c
+#define regBIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC0_CAP_PTR                                                                     0x080d
+#define regBIF_CFG_DEV2_RC0_CAP_PTR_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_RC0_ROM_BASE_ADDR                                                               0x080e
+#define regBIF_CFG_DEV2_RC0_ROM_BASE_ADDR_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_INTERRUPT_LINE                                                              0x080f
+#define regBIF_CFG_DEV2_RC0_INTERRUPT_LINE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_RC0_INTERRUPT_PIN                                                               0x080f
+#define regBIF_CFG_DEV2_RC0_INTERRUPT_PIN_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL                                                             0x080f
+#define regBIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL                                                             0x0810
+#define regBIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC0_PMI_CAP_LIST                                                                0x0814
+#define regBIF_CFG_DEV2_RC0_PMI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC0_PMI_CAP                                                                     0x0814
+#define regBIF_CFG_DEV2_RC0_PMI_CAP_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_RC0_PMI_STATUS_CNTL                                                             0x0815
+#define regBIF_CFG_DEV2_RC0_PMI_STATUS_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC0_PCIE_CAP_LIST                                                               0x0816
+#define regBIF_CFG_DEV2_RC0_PCIE_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_CAP                                                                    0x0816
+#define regBIF_CFG_DEV2_RC0_PCIE_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_RC0_DEVICE_CAP                                                                  0x0817
+#define regBIF_CFG_DEV2_RC0_DEVICE_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_RC0_DEVICE_CNTL                                                                 0x0818
+#define regBIF_CFG_DEV2_RC0_DEVICE_CNTL_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC0_DEVICE_STATUS                                                               0x0818
+#define regBIF_CFG_DEV2_RC0_DEVICE_STATUS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_LINK_CAP                                                                    0x0819
+#define regBIF_CFG_DEV2_RC0_LINK_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_RC0_LINK_CNTL                                                                   0x081a
+#define regBIF_CFG_DEV2_RC0_LINK_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC0_LINK_STATUS                                                                 0x081a
+#define regBIF_CFG_DEV2_RC0_LINK_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC0_SLOT_CAP                                                                    0x081b
+#define regBIF_CFG_DEV2_RC0_SLOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_RC0_SLOT_CNTL                                                                   0x081c
+#define regBIF_CFG_DEV2_RC0_SLOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC0_SLOT_STATUS                                                                 0x081c
+#define regBIF_CFG_DEV2_RC0_SLOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC0_ROOT_CNTL                                                                   0x081d
+#define regBIF_CFG_DEV2_RC0_ROOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC0_ROOT_CAP                                                                    0x081d
+#define regBIF_CFG_DEV2_RC0_ROOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_RC0_ROOT_STATUS                                                                 0x081e
+#define regBIF_CFG_DEV2_RC0_ROOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC0_DEVICE_CAP2                                                                 0x081f
+#define regBIF_CFG_DEV2_RC0_DEVICE_CAP2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC0_DEVICE_CNTL2                                                                0x0820
+#define regBIF_CFG_DEV2_RC0_DEVICE_CNTL2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC0_DEVICE_STATUS2                                                              0x0820
+#define regBIF_CFG_DEV2_RC0_DEVICE_STATUS2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_RC0_LINK_CAP2                                                                   0x0821
+#define regBIF_CFG_DEV2_RC0_LINK_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC0_LINK_CNTL2                                                                  0x0822
+#define regBIF_CFG_DEV2_RC0_LINK_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_RC0_LINK_STATUS2                                                                0x0822
+#define regBIF_CFG_DEV2_RC0_LINK_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC0_SLOT_CAP2                                                                   0x0823
+#define regBIF_CFG_DEV2_RC0_SLOT_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC0_SLOT_CNTL2                                                                  0x0824
+#define regBIF_CFG_DEV2_RC0_SLOT_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_RC0_SLOT_STATUS2                                                                0x0824
+#define regBIF_CFG_DEV2_RC0_SLOT_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC0_MSI_CAP_LIST                                                                0x0828
+#define regBIF_CFG_DEV2_RC0_MSI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC0_MSI_MSG_CNTL                                                                0x0828
+#define regBIF_CFG_DEV2_RC0_MSI_MSG_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO                                                             0x0829
+#define regBIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI                                                             0x082a
+#define regBIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC0_MSI_MSG_DATA                                                                0x082a
+#define regBIF_CFG_DEV2_RC0_MSI_MSG_DATA_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA                                                            0x082a
+#define regBIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC0_MSI_MSG_DATA_64                                                             0x082b
+#define regBIF_CFG_DEV2_RC0_MSI_MSG_DATA_64_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64                                                         0x082b
+#define regBIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_RC0_SSID_CAP_LIST                                                               0x0830
+#define regBIF_CFG_DEV2_RC0_SSID_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_SSID_CAP                                                                    0x0831
+#define regBIF_CFG_DEV2_RC0_SSID_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST                                                            0x0832
+#define regBIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC0_MSI_MAP_CAP                                                                 0x0832
+#define regBIF_CFG_DEV2_RC0_MSI_MAP_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                           0x0840
+#define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR                                                    0x0841
+#define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1                                                       0x0842
+#define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2                                                       0x0843
+#define regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST                                                        0x0844
+#define regBIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1                                                       0x0845
+#define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2                                                       0x0846
+#define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL                                                           0x0847
+#define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS                                                         0x0847
+#define regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP                                                       0x0848
+#define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL                                                      0x0849
+#define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS                                                    0x084a
+#define regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP                                                       0x084b
+#define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL                                                      0x084c
+#define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS                                                    0x084d
+#define regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                            0x0850
+#define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1                                                     0x0851
+#define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2                                                     0x0852
+#define regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                               0x0854
+#define regBIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS                                                      0x0855
+#define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK                                                        0x0856
+#define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY                                                    0x0857
+#define regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS                                                        0x0858
+#define regBIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK                                                          0x0859
+#define regBIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL                                                       0x085a
+#define regBIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG0                                                               0x085b
+#define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG0_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG1                                                               0x085c
+#define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG1_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG2                                                               0x085d
+#define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG3                                                               0x085e
+#define regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG3_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD                                                           0x085f
+#define regBIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS                                                        0x0860
+#define regBIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID                                                             0x0861
+#define regBIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0                                                        0x0862
+#define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1                                                        0x0863
+#define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2                                                        0x0864
+#define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3                                                        0x0865
+#define regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST                                                 0x089c
+#define regBIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3                                                             0x089d
+#define regBIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS                                                      0x089e
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL                                               0x089f
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL                                               0x089f
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL                                               0x08a0
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL                                               0x08a0
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL                                               0x08a1
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL                                               0x08a1
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL                                               0x08a2
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL                                               0x08a2
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL                                               0x08a3
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL                                               0x08a3
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL                                              0x08a4
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL                                              0x08a4
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL                                              0x08a5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL                                              0x08a5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL                                              0x08a6
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL                                              0x08a6
+#define regBIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST                                                       0x08a8
+#define regBIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC0_PCIE_ACS_CAP                                                                0x08a9
+#define regBIF_CFG_DEV2_RC0_PCIE_ACS_CAP_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC0_PCIE_ACS_CNTL                                                               0x08a9
+#define regBIF_CFG_DEV2_RC0_PCIE_ACS_CNTL_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST                                                       0x0900
+#define regBIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP                                                       0x0901
+#define regBIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS                                                    0x0902
+#define regBIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST                                                  0x0904
+#define regBIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC0_LINK_CAP_16GT                                                               0x0905
+#define regBIF_CFG_DEV2_RC0_LINK_CAP_16GT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC0_LINK_CNTL_16GT                                                              0x0906
+#define regBIF_CFG_DEV2_RC0_LINK_CNTL_16GT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_RC0_LINK_STATUS_16GT                                                            0x0907
+#define regBIF_CFG_DEV2_RC0_LINK_STATUS_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                           0x0908
+#define regBIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT                                            0x0909
+#define regBIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT                                            0x090a
+#define regBIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT                                               0x090c
+#define regBIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT                                               0x090c
+#define regBIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT                                               0x090c
+#define regBIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT                                               0x090c
+#define regBIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT                                               0x090d
+#define regBIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT                                               0x090d
+#define regBIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT                                               0x090d
+#define regBIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT                                               0x090d
+#define regBIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT                                               0x090e
+#define regBIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT                                               0x090e
+#define regBIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT                                              0x090e
+#define regBIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT                                              0x090e
+#define regBIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT                                              0x090f
+#define regBIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT                                              0x090f
+#define regBIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT                                              0x090f
+#define regBIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT                                              0x090f
+#define regBIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST                                                 0x0910
+#define regBIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC0_MARGINING_PORT_CAP                                                          0x0911
+#define regBIF_CFG_DEV2_RC0_MARGINING_PORT_CAP_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS                                                       0x0911
+#define regBIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL                                                  0x0912
+#define regBIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS                                                0x0912
+#define regBIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL                                                  0x0913
+#define regBIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS                                                0x0913
+#define regBIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL                                                  0x0914
+#define regBIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS                                                0x0914
+#define regBIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL                                                  0x0915
+#define regBIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS                                                0x0915
+#define regBIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL                                                  0x0916
+#define regBIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS                                                0x0916
+#define regBIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL                                                  0x0917
+#define regBIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS                                                0x0917
+#define regBIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL                                                  0x0918
+#define regBIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS                                                0x0918
+#define regBIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL                                                  0x0919
+#define regBIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS                                                0x0919
+#define regBIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL                                                  0x091a
+#define regBIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS                                                0x091a
+#define regBIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL                                                  0x091b
+#define regBIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS                                                0x091b
+#define regBIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL                                                 0x091c
+#define regBIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS                                               0x091c
+#define regBIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL                                                 0x091d
+#define regBIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS                                               0x091d
+#define regBIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL                                                 0x091e
+#define regBIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS                                               0x091e
+#define regBIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL                                                 0x091f
+#define regBIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS                                               0x091f
+#define regBIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL                                                 0x0920
+#define regBIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS                                               0x0920
+#define regBIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL                                                 0x0921
+#define regBIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS                                               0x0921
+#define regBIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                      5
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+// base address: 0x10120000
+#define regBIF_BX_PF1_MM_INDEX                                                                          0x8000
+#define regBIF_BX_PF1_MM_INDEX_BASE_IDX                                                                 5
+#define regBIF_BX_PF1_MM_DATA                                                                           0x8001
+#define regBIF_BX_PF1_MM_DATA_BASE_IDX                                                                  5
+#define regBIF_BX_PF1_MM_INDEX_HI                                                                       0x8006
+#define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX                                                              5
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+// base address: 0x10120000
+#define regBIF_BX1_PCIE_INDEX                                                                           0x800c
+#define regBIF_BX1_PCIE_INDEX_BASE_IDX                                                                  5
+#define regBIF_BX1_PCIE_DATA                                                                            0x800d
+#define regBIF_BX1_PCIE_DATA_BASE_IDX                                                                   5
+#define regBIF_BX1_PCIE_INDEX2                                                                          0x800e
+#define regBIF_BX1_PCIE_INDEX2_BASE_IDX                                                                 5
+#define regBIF_BX1_PCIE_DATA2                                                                           0x800f
+#define regBIF_BX1_PCIE_DATA2_BASE_IDX                                                                  5
+#define regBIF_BX1_SBIOS_SCRATCH_0                                                                      0x8048
+#define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_1                                                                      0x8049
+#define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_2                                                                      0x804a
+#define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_3                                                                      0x804b
+#define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_0                                                                       0x804c
+#define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_1                                                                       0x804d
+#define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_2                                                                       0x804e
+#define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_3                                                                       0x804f
+#define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_4                                                                       0x8050
+#define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_5                                                                       0x8051
+#define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_6                                                                       0x8052
+#define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_7                                                                       0x8053
+#define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_8                                                                       0x8054
+#define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_9                                                                       0x8055
+#define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_10                                                                      0x8056
+#define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_11                                                                      0x8057
+#define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_12                                                                      0x8058
+#define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_13                                                                      0x8059
+#define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_14                                                                      0x805a
+#define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_15                                                                      0x805b
+#define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX                                                             5
+#define regBIF_BX1_BIF_RLC_INTR_CNTL                                                                    0x8060
+#define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX                                                           5
+#define regBIF_BX1_BIF_VCE_INTR_CNTL                                                                    0x8061
+#define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX                                                           5
+#define regBIF_BX1_BIF_UVD_INTR_CNTL                                                                    0x8062
+#define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX                                                           5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0                                                                0x8080
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0                                                          0x8081
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1                                                                0x8082
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1                                                          0x8083
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2                                                                0x8084
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2                                                          0x8085
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3                                                                0x8086
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3                                                          0x8087
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4                                                                0x8088
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4                                                          0x8089
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5                                                                0x808a
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5                                                          0x808b
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6                                                                0x808c
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6                                                          0x808d
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7                                                                0x808e
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7                                                          0x808f
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL                                                                 0x8090
+#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX                                                        5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL                                                             0x8091
+#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX                                                    5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL                                                              0x8092
+#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX                                                     5
+#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL                                                     0x8093
+#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1:1
+// base address: 0x10120000
+#define regRCC_STRAP1_RCC_BIF_STRAP0                                                                    0x8d20
+#define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP1                                                                    0x8d21
+#define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP2                                                                    0x8d22
+#define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP3                                                                    0x8d23
+#define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP4                                                                    0x8d24
+#define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP5                                                                    0x8d25
+#define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP6                                                                    0x8d26
+#define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0                                                              0x8d27
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1                                                              0x8d28
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2                                                              0x8d29
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3                                                              0x8d2a
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4                                                              0x8d2b
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5                                                              0x8d2c
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6                                                              0x8d2d
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7                                                              0x8d2e
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8                                                              0x8d2f
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9                                                              0x8d30
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0                                                              0x8d31
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1                                                              0x8d32
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13                                                             0x8d33
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14                                                             0x8d34
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2                                                              0x8d35
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3                                                              0x8d36
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4                                                              0x8d37
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5                                                              0x8d38
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8                                                              0x8d39
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9                                                              0x8d3a
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0                                                              0x8d3b
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP10                                                             0x8d3c
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP10_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP11                                                             0x8d3d
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP11_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP12                                                             0x8d3e
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP12_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP13                                                             0x8d3f
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP14                                                             0x8d40
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP14_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2                                                              0x8d41
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3                                                              0x8d42
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4                                                              0x8d43
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5                                                              0x8d44
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6                                                              0x8d45
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7                                                              0x8d46
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX                                                     5
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH                                                                0x8d47
+#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_1_EP_PCIE_CNTL                                                                   0x8d49
+#define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX                                                          5
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL                                                               0x8d4a
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS                                                             0x8d4b
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2                                                               0x8d4c
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL                                                               0x8d4d
+#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL                                                               0x8d4e
+#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL                                                            0x8d50
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0                                               0x8d51
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1                                               0x8d51
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2                                               0x8d51
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3                                               0x8d51
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4                                               0x8d52
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5                                               0x8d52
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6                                               0x8d52
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7                                               0x8d52
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC                                                             0x8d53
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2                                                            0x8d54
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP                                                             0x8d56
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR                                               0x8d57
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL                                                            0x8d57
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                               0x8d57
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                               0x8d58
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                               0x8d58
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                               0x8d58
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                               0x8d58
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                               0x8d59
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                               0x8d59
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                               0x8d59
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL                                                            0x8d59
+#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED                                                              0x8d5a
+#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX                                                     5
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL                                                                0x8d5c
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID                                                        0x8d5d
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX                                               5
+#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL                                                               0x8d5e
+#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL                                                                0x8d5f
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL                                                          0x8d60
+#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED                                                              0x8d62
+#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH                                                               0x8d63
+#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX                                                      5
+#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL                                                                  0x8d65
+#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX                                                         5
+#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL                                                           0x8d66
+#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX                                                  5
+#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2                                                              0x8d67
+#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL                                                              0x8d68
+#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL                                                              0x8d69
+#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0                                                              0x8d6a
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC                                                            0x8d6b
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX                                                   5
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2                                                           0x8d6c
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX                                                  5
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL                                                                0x8d6f
+#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX                                                       5
+#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL                                                                 0x8d70
+#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX                                                        5
+#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL                                                           0x8d71
+#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX                                                  5
+#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2                                                                0x8d72
+#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX                                                       5
+#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC                                                             0x8d73
+#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX                                                    5
+#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP                                                         0x8d74
+#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX                                                5
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_DEV0_1_RCC_ERR_INT_CNTL                                                                  0x8da6
+#define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX                                                         5
+#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC                                                                0x8da7
+#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX                                                       5
+#define regRCC_DEV0_1_RCC_RESET_EN                                                                      0x8da8
+#define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX                                                             5
+#define regRCC_DEV0_1_RCC_VDM_SUPPORT                                                                   0x8da9
+#define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX                                                          5
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0                                                            0x8daa
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1                                                            0x8dab
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_GPUIOV_REGION                                                                 0x8dac
+#define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX                                                        5
+#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN                                                                 0x8dad
+#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX                                                        5
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL                                                         0x8dae
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX                                                5
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET                                                   0x8daf
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX                                          5
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE                                                         0x8daf
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX                                                5
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0                                                               0x8dde
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX                                                      5
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1                                                               0x8ddf
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX                                                      5
+#define regRCC_DEV0_1_RCC_BUS_CNTL                                                                      0x8de1
+#define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX                                                             5
+#define regRCC_DEV0_1_RCC_CONFIG_CNTL                                                                   0x8de2
+#define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX                                                          5
+#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE                                                                0x8de6
+#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX                                                       5
+#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE                                                              0x8de7
+#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX                                                     5
+#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE                                                          0x8de8
+#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX                                                 5
+#define regRCC_DEV0_1_RCC_XDMA_LO                                                                       0x8de9
+#define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX                                                              5
+#define regRCC_DEV0_1_RCC_XDMA_HI                                                                       0x8dea
+#define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX                                                              5
+#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC                                                         0x8deb
+#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX                                                5
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1                                                                  0x8dec
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX                                                         5
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST0                                                                  0x8ded
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX                                                         5
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST1                                                                  0x8dee
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX                                                         5
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2                                                                  0x8def
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX                                                         5
+#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM                                                           0x8df0
+#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX                                                  5
+#define regRCC_DEV0_1_RCC_HOST_BUSNUM                                                                   0x8df1
+#define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX                                                          5
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI                                                            0x8df2
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO                                                            0x8df3
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI                                                            0x8df4
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO                                                            0x8df5
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI                                                            0x8df6
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO                                                            0x8df7
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI                                                            0x8df8
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO                                                            0x8df9
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0                                                              0x8dfa
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX                                                     5
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1                                                              0x8dfb
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX                                                     5
+#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL                                                                0x8dfd
+#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX                                                       5
+#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL                                                                 0x8dfe
+#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX                                                        5
+#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE                                                        0x8dff
+#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX                                               5
+#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL                                                              0x8e00
+#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX                                                     5
+#define regRCC_DEV0_1_RCC_MH_ARB_CNTL                                                                   0x8e01
+#define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX                                                          5
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+// base address: 0x10120000
+#define regBIF_BX1_CC_BIF_BX_STRAP0                                                                     0x8e02
+#define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX                                                            5
+#define regBIF_BX1_CC_BIF_BX_PINSTRAP0                                                                  0x8e04
+#define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX                                                         5
+#define regBIF_BX1_BIF_MM_INDACCESS_CNTL                                                                0x8e06
+#define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX                                                       5
+#define regBIF_BX1_BUS_CNTL                                                                             0x8e07
+#define regBIF_BX1_BUS_CNTL_BASE_IDX                                                                    5
+#define regBIF_BX1_BIF_SCRATCH0                                                                         0x8e08
+#define regBIF_BX1_BIF_SCRATCH0_BASE_IDX                                                                5
+#define regBIF_BX1_BIF_SCRATCH1                                                                         0x8e09
+#define regBIF_BX1_BIF_SCRATCH1_BASE_IDX                                                                5
+#define regBIF_BX1_BX_RESET_EN                                                                          0x8e0d
+#define regBIF_BX1_BX_RESET_EN_BASE_IDX                                                                 5
+#define regBIF_BX1_MM_CFGREGS_CNTL                                                                      0x8e0e
+#define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX                                                             5
+#define regBIF_BX1_BX_RESET_CNTL                                                                        0x8e10
+#define regBIF_BX1_BX_RESET_CNTL_BASE_IDX                                                               5
+#define regBIF_BX1_INTERRUPT_CNTL                                                                       0x8e11
+#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX                                                              5
+#define regBIF_BX1_INTERRUPT_CNTL2                                                                      0x8e12
+#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX                                                             5
+#define regBIF_BX1_CLKREQB_PAD_CNTL                                                                     0x8e18
+#define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX                                                            5
+#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC                                                            0x8e1b
+#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX                                                   5
+#define regBIF_BX1_BIF_DOORBELL_CNTL                                                                    0x8e1c
+#define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX                                                           5
+#define regBIF_BX1_BIF_DOORBELL_INT_CNTL                                                                0x8e1d
+#define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX                                                       5
+#define regBIF_BX1_BIF_FB_EN                                                                            0x8e1f
+#define regBIF_BX1_BIF_FB_EN_BASE_IDX                                                                   5
+#define regBIF_BX1_BIF_INTR_CNTL                                                                        0x8e20
+#define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX                                                               5
+#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF                                                             0x8e29
+#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX                                                    5
+#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF                                                             0x8e2a
+#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX                                                    5
+#define regBIF_BX1_MEM_TYPE_CNTL                                                                        0x8e31
+#define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX                                                               5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL                                                               0x8e33
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX                                                      5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0                                                                  0x8e34
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1                                                                  0x8e35
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2                                                                  0x8e36
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3                                                                  0x8e37
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4                                                                  0x8e38
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5                                                                  0x8e39
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6                                                                  0x8e3a
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7                                                                  0x8e3b
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8                                                                  0x8e3c
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9                                                                  0x8e3d
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10                                                                 0x8e3e
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX                                                        5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11                                                                 0x8e3f
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX                                                        5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12                                                                 0x8e40
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX                                                        5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13                                                                 0x8e41
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX                                                        5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14                                                                 0x8e42
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX                                                        5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15                                                                 0x8e43
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX                                                        5
+#define regBIF_BX1_VF_REGWR_EN                                                                          0x8e44
+#define regBIF_BX1_VF_REGWR_EN_BASE_IDX                                                                 5
+#define regBIF_BX1_VF_DOORBELL_EN                                                                       0x8e45
+#define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX                                                              5
+#define regBIF_BX1_VF_FB_EN                                                                             0x8e46
+#define regBIF_BX1_VF_FB_EN_BASE_IDX                                                                    5
+#define regBIF_BX1_VF_REGWR_STATUS                                                                      0x8e47
+#define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX                                                             5
+#define regBIF_BX1_VF_DOORBELL_STATUS                                                                   0x8e48
+#define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX                                                          5
+#define regBIF_BX1_VF_FB_STATUS                                                                         0x8e49
+#define regBIF_BX1_VF_FB_STATUS_BASE_IDX                                                                5
+#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL                                                             0x8e4d
+#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX                                                    5
+#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL                                                             0x8e4e
+#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX                                                    5
+#define regBIF_BX1_BIF_RB_CNTL                                                                          0x8e4f
+#define regBIF_BX1_BIF_RB_CNTL_BASE_IDX                                                                 5
+#define regBIF_BX1_BIF_RB_BASE                                                                          0x8e50
+#define regBIF_BX1_BIF_RB_BASE_BASE_IDX                                                                 5
+#define regBIF_BX1_BIF_RB_RPTR                                                                          0x8e51
+#define regBIF_BX1_BIF_RB_RPTR_BASE_IDX                                                                 5
+#define regBIF_BX1_BIF_RB_WPTR                                                                          0x8e52
+#define regBIF_BX1_BIF_RB_WPTR_BASE_IDX                                                                 5
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI                                                                  0x8e53
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX                                                         5
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO                                                                  0x8e54
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX                                                         5
+#define regBIF_BX1_MAILBOX_INDEX                                                                        0x8e55
+#define regBIF_BX1_MAILBOX_INDEX_BASE_IDX                                                               5
+#define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE                                                             0x8e63
+#define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX                                                    5
+#define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE                                                             0x8e64
+#define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX                                                    5
+#define regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE                                                         0x8e65
+#define regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX                                                5
+#define regBIF_BX1_BIF_PERSTB_PAD_CNTL                                                                  0x8e68
+#define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX                                                         5
+#define regBIF_BX1_BIF_PX_EN_PAD_CNTL                                                                   0x8e69
+#define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX                                                          5
+#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL                                                               0x8e6a
+#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX                                                      5
+#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL                                                                 0x8e6b
+#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX                                                        5
+#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL                                                                  0x8e6c
+#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX                                                         5
+#define regBIF_BX1_BIF_WAKEB_PAD_CNTL                                                                   0x8e6d
+#define regBIF_BX1_BIF_WAKEB_PAD_CNTL_BASE_IDX                                                          5
+#define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL                                                            0x8e6e
+#define regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX                                                   5
+#define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL                                                           0x8e70
+#define regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL_BASE_IDX                                                  5
+#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0                                                               0x8e71
+#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL0_BASE_IDX                                                      5
+#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1                                                               0x8e72
+#define regBIF_BX1_BIF_S5_MEM_POWER_CTRL1_BASE_IDX                                                      5
+#define regBIF_BX1_BIF_S5_DUMMY_REGS                                                                    0x8e73
+#define regBIF_BX1_BIF_S5_DUMMY_REGS_BASE_IDX                                                           5
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+// base address: 0x10120000
+#define regBIF_BX_PF1_BIF_BME_STATUS                                                                    0x8e0b
+#define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX                                                           5
+#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG                                                                0x8e0c
+#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX                                                       5
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                              0x8e13
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                                     5
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                               0x8e14
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                                      5
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL                                                   0x8e15
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                          5
+#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL                                                      0x8e16
+#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                             5
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL                                                      0x8e17
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                             5
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                                 0x8e19
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                                        5
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                            0x8e1a
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                                   5
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ                                                            0x8e24
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ_BASE_IDX                                                   5
+#define regBIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ                                                       0x8e25
+#define regBIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ_BASE_IDX                                              5
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ                                                                 0x8e26
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX                                                        5
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE                                                                0x8e27
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX                                                       5
+#define regBIF_BX_PF1_BIF_TRANS_PENDING                                                                 0x8e28
+#define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX                                                        5
+#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS                                                          0x8e32
+#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                                 5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0                                                            0x8e56
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1                                                            0x8e57
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2                                                            0x8e58
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3                                                            0x8e59
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0                                                            0x8e5a
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1                                                            0x8e5b
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2                                                            0x8e5c
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3                                                            0x8e5d
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_CONTROL                                                                   0x8e5e
+#define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX                                                          5
+#define regBIF_BX_PF1_MAILBOX_INT_CNTL                                                                  0x8e5f
+#define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX                                                         5
+#define regBIF_BX_PF1_BIF_VMHV_MAILBOX                                                                  0x8e60
+#define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX                                                         5
+
+
+// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal
+// base address: 0x10100000
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0                                                              0xc400
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1                                                              0xc401
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2                                                              0xc402
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3                                                              0xc403
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4                                                              0xc404
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5                                                              0xc405
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6                                                              0xc406
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7                                                              0xc407
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8                                                              0xc408
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9                                                              0xc409
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX                                                     5
+#define regRCC_DEV1_PORT_STRAP0                                                                         0xc480
+#define regRCC_DEV1_PORT_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP1                                                                         0xc481
+#define regRCC_DEV1_PORT_STRAP1_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP2                                                                         0xc482
+#define regRCC_DEV1_PORT_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP3                                                                         0xc483
+#define regRCC_DEV1_PORT_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP4                                                                         0xc484
+#define regRCC_DEV1_PORT_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP5                                                                         0xc485
+#define regRCC_DEV1_PORT_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP6                                                                         0xc486
+#define regRCC_DEV1_PORT_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP7                                                                         0xc487
+#define regRCC_DEV1_PORT_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP8                                                                         0xc488
+#define regRCC_DEV1_PORT_STRAP8_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP9                                                                         0xc489
+#define regRCC_DEV1_PORT_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP0                                                                         0xc500
+#define regRCC_DEV2_PORT_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP1                                                                         0xc501
+#define regRCC_DEV2_PORT_STRAP1_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP2                                                                         0xc502
+#define regRCC_DEV2_PORT_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP3                                                                         0xc503
+#define regRCC_DEV2_PORT_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP4                                                                         0xc504
+#define regRCC_DEV2_PORT_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP5                                                                         0xc505
+#define regRCC_DEV2_PORT_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP6                                                                         0xc506
+#define regRCC_DEV2_PORT_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP7                                                                         0xc507
+#define regRCC_DEV2_PORT_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP8                                                                         0xc508
+#define regRCC_DEV2_PORT_STRAP8_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP9                                                                         0xc509
+#define regRCC_DEV2_PORT_STRAP9_BASE_IDX                                                                5
+#define regRCC_STRAP2_RCC_BIF_STRAP0                                                                    0xc600
+#define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP1                                                                    0xc601
+#define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP2                                                                    0xc602
+#define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP3                                                                    0xc603
+#define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP4                                                                    0xc604
+#define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP5                                                                    0xc605
+#define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP6                                                                    0xc606
+#define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0                                                              0xd000
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1                                                              0xd001
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2                                                              0xd002
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3                                                              0xd003
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4                                                              0xd004
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5                                                              0xd005
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8                                                              0xd008
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9                                                              0xd009
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13                                                             0xd00d
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14                                                             0xd00e
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0                                                              0xd080
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2                                                              0xd082
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3                                                              0xd083
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4                                                              0xd084
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5                                                              0xd085
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6                                                              0xd086
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7                                                              0xd087
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP10                                                             0xd08a
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP10_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP11                                                             0xd08b
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP11_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP12                                                             0xd08c
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP12_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP13                                                             0xd08d
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP14                                                             0xd08e
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP14_BASE_IDX                                                    5
+#define regRCC_DEV0_EPF2_STRAP0                                                                         0xd100
+#define regRCC_DEV0_EPF2_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP2                                                                         0xd102
+#define regRCC_DEV0_EPF2_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP3                                                                         0xd103
+#define regRCC_DEV0_EPF2_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP4                                                                         0xd104
+#define regRCC_DEV0_EPF2_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP5                                                                         0xd105
+#define regRCC_DEV0_EPF2_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP6                                                                         0xd106
+#define regRCC_DEV0_EPF2_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP7                                                                         0xd107
+#define regRCC_DEV0_EPF2_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP10                                                                        0xd10a
+#define regRCC_DEV0_EPF2_STRAP10_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF2_STRAP11                                                                        0xd10b
+#define regRCC_DEV0_EPF2_STRAP11_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF2_STRAP12                                                                        0xd10c
+#define regRCC_DEV0_EPF2_STRAP12_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF2_STRAP13                                                                        0xd10d
+#define regRCC_DEV0_EPF2_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF2_STRAP14                                                                        0xd10e
+#define regRCC_DEV0_EPF2_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP0                                                                         0xd180
+#define regRCC_DEV0_EPF3_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP2                                                                         0xd182
+#define regRCC_DEV0_EPF3_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP3                                                                         0xd183
+#define regRCC_DEV0_EPF3_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP4                                                                         0xd184
+#define regRCC_DEV0_EPF3_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP5                                                                         0xd185
+#define regRCC_DEV0_EPF3_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP6                                                                         0xd186
+#define regRCC_DEV0_EPF3_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP7                                                                         0xd187
+#define regRCC_DEV0_EPF3_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP10                                                                        0xd18a
+#define regRCC_DEV0_EPF3_STRAP10_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP11                                                                        0xd18b
+#define regRCC_DEV0_EPF3_STRAP11_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP12                                                                        0xd18c
+#define regRCC_DEV0_EPF3_STRAP12_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP13                                                                        0xd18d
+#define regRCC_DEV0_EPF3_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP14                                                                        0xd18e
+#define regRCC_DEV0_EPF3_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF4_STRAP0                                                                         0xd200
+#define regRCC_DEV0_EPF4_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP2                                                                         0xd202
+#define regRCC_DEV0_EPF4_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP3                                                                         0xd203
+#define regRCC_DEV0_EPF4_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP4                                                                         0xd204
+#define regRCC_DEV0_EPF4_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP5                                                                         0xd205
+#define regRCC_DEV0_EPF4_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP6                                                                         0xd206
+#define regRCC_DEV0_EPF4_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP7                                                                         0xd207
+#define regRCC_DEV0_EPF4_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP13                                                                        0xd20d
+#define regRCC_DEV0_EPF4_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF4_STRAP14                                                                        0xd20e
+#define regRCC_DEV0_EPF4_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF5_STRAP0                                                                         0xd280
+#define regRCC_DEV0_EPF5_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP2                                                                         0xd282
+#define regRCC_DEV0_EPF5_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP3                                                                         0xd283
+#define regRCC_DEV0_EPF5_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP4                                                                         0xd284
+#define regRCC_DEV0_EPF5_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP5                                                                         0xd285
+#define regRCC_DEV0_EPF5_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP6                                                                         0xd286
+#define regRCC_DEV0_EPF5_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP7                                                                         0xd287
+#define regRCC_DEV0_EPF5_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP13                                                                        0xd28d
+#define regRCC_DEV0_EPF5_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF5_STRAP14                                                                        0xd28e
+#define regRCC_DEV0_EPF5_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF6_STRAP0                                                                         0xd300
+#define regRCC_DEV0_EPF6_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP2                                                                         0xd302
+#define regRCC_DEV0_EPF6_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP3                                                                         0xd303
+#define regRCC_DEV0_EPF6_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP4                                                                         0xd304
+#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP5                                                                         0xd305
+#define regRCC_DEV0_EPF6_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP6                                                                         0xd306
+#define regRCC_DEV0_EPF6_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP7                                                                         0xd307
+#define regRCC_DEV0_EPF6_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP13                                                                        0xd30d
+#define regRCC_DEV0_EPF6_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF6_STRAP14                                                                        0xd30e
+#define regRCC_DEV0_EPF6_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF7_STRAP0                                                                         0xd380
+#define regRCC_DEV0_EPF7_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP2                                                                         0xd382
+#define regRCC_DEV0_EPF7_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP3                                                                         0xd383
+#define regRCC_DEV0_EPF7_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP4                                                                         0xd384
+#define regRCC_DEV0_EPF7_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP5                                                                         0xd385
+#define regRCC_DEV0_EPF7_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP6                                                                         0xd386
+#define regRCC_DEV0_EPF7_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP7                                                                         0xd387
+#define regRCC_DEV0_EPF7_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP13                                                                        0xd38d
+#define regRCC_DEV0_EPF7_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF7_STRAP14                                                                        0xd38e
+#define regRCC_DEV0_EPF7_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF0_STRAP0                                                                         0xd400
+#define regRCC_DEV1_EPF0_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP2                                                                         0xd402
+#define regRCC_DEV1_EPF0_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP3                                                                         0xd403
+#define regRCC_DEV1_EPF0_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP4                                                                         0xd404
+#define regRCC_DEV1_EPF0_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP5                                                                         0xd405
+#define regRCC_DEV1_EPF0_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP6                                                                         0xd406
+#define regRCC_DEV1_EPF0_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP7                                                                         0xd407
+#define regRCC_DEV1_EPF0_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP13                                                                        0xd40d
+#define regRCC_DEV1_EPF0_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF0_STRAP14                                                                        0xd40e
+#define regRCC_DEV1_EPF0_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF1_STRAP0                                                                         0xd480
+#define regRCC_DEV1_EPF1_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP2                                                                         0xd482
+#define regRCC_DEV1_EPF1_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP3                                                                         0xd483
+#define regRCC_DEV1_EPF1_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP4                                                                         0xd484
+#define regRCC_DEV1_EPF1_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP5                                                                         0xd485
+#define regRCC_DEV1_EPF1_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP6                                                                         0xd486
+#define regRCC_DEV1_EPF1_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP7                                                                         0xd487
+#define regRCC_DEV1_EPF1_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP13                                                                        0xd48d
+#define regRCC_DEV1_EPF1_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF1_STRAP14                                                                        0xd48e
+#define regRCC_DEV1_EPF1_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF2_STRAP0                                                                         0xd500
+#define regRCC_DEV1_EPF2_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP2                                                                         0xd502
+#define regRCC_DEV1_EPF2_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP3                                                                         0xd503
+#define regRCC_DEV1_EPF2_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP4                                                                         0xd504
+#define regRCC_DEV1_EPF2_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP5                                                                         0xd505
+#define regRCC_DEV1_EPF2_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP6                                                                         0xd506
+#define regRCC_DEV1_EPF2_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP13                                                                        0xd50d
+#define regRCC_DEV1_EPF2_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF2_STRAP14                                                                        0xd50e
+#define regRCC_DEV1_EPF2_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF3_STRAP0                                                                         0xd580
+#define regRCC_DEV1_EPF3_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP2                                                                         0xd582
+#define regRCC_DEV1_EPF3_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP3                                                                         0xd583
+#define regRCC_DEV1_EPF3_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP4                                                                         0xd584
+#define regRCC_DEV1_EPF3_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP5                                                                         0xd585
+#define regRCC_DEV1_EPF3_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP6                                                                         0xd586
+#define regRCC_DEV1_EPF3_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP13                                                                        0xd58d
+#define regRCC_DEV1_EPF3_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF3_STRAP14                                                                        0xd58e
+#define regRCC_DEV1_EPF3_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF4_STRAP0                                                                         0xd600
+#define regRCC_DEV1_EPF4_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF4_STRAP2                                                                         0xd602
+#define regRCC_DEV1_EPF4_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF4_STRAP3                                                                         0xd603
+#define regRCC_DEV1_EPF4_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF4_STRAP4                                                                         0xd604
+#define regRCC_DEV1_EPF4_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF4_STRAP5                                                                         0xd605
+#define regRCC_DEV1_EPF4_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF4_STRAP6                                                                         0xd606
+#define regRCC_DEV1_EPF4_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF4_STRAP13                                                                        0xd60d
+#define regRCC_DEV1_EPF4_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF4_STRAP14                                                                        0xd60e
+#define regRCC_DEV1_EPF4_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF5_STRAP0                                                                         0xd680
+#define regRCC_DEV1_EPF5_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF5_STRAP2                                                                         0xd682
+#define regRCC_DEV1_EPF5_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF5_STRAP3                                                                         0xd683
+#define regRCC_DEV1_EPF5_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF5_STRAP4                                                                         0xd684
+#define regRCC_DEV1_EPF5_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF5_STRAP5                                                                         0xd685
+#define regRCC_DEV1_EPF5_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF5_STRAP6                                                                         0xd686
+#define regRCC_DEV1_EPF5_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF5_STRAP13                                                                        0xd68d
+#define regRCC_DEV1_EPF5_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF5_STRAP14                                                                        0xd68e
+#define regRCC_DEV1_EPF5_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF0_STRAP0                                                                         0xd800
+#define regRCC_DEV2_EPF0_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP2                                                                         0xd802
+#define regRCC_DEV2_EPF0_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP3                                                                         0xd803
+#define regRCC_DEV2_EPF0_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP4                                                                         0xd804
+#define regRCC_DEV2_EPF0_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP5                                                                         0xd805
+#define regRCC_DEV2_EPF0_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP6                                                                         0xd806
+#define regRCC_DEV2_EPF0_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP7                                                                         0xd807
+#define regRCC_DEV2_EPF0_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP13                                                                        0xd80d
+#define regRCC_DEV2_EPF0_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF0_STRAP14                                                                        0xd80e
+#define regRCC_DEV2_EPF0_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF1_STRAP0                                                                         0xd880
+#define regRCC_DEV2_EPF1_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP2                                                                         0xd882
+#define regRCC_DEV2_EPF1_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP3                                                                         0xd883
+#define regRCC_DEV2_EPF1_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP4                                                                         0xd884
+#define regRCC_DEV2_EPF1_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP5                                                                         0xd885
+#define regRCC_DEV2_EPF1_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP6                                                                         0xd886
+#define regRCC_DEV2_EPF1_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP13                                                                        0xd88d
+#define regRCC_DEV2_EPF1_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF1_STRAP14                                                                        0xd88e
+#define regRCC_DEV2_EPF1_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF2_STRAP0                                                                         0xd900
+#define regRCC_DEV2_EPF2_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP2                                                                         0xd902
+#define regRCC_DEV2_EPF2_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP3                                                                         0xd903
+#define regRCC_DEV2_EPF2_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP4                                                                         0xd904
+#define regRCC_DEV2_EPF2_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP5                                                                         0xd905
+#define regRCC_DEV2_EPF2_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP6                                                                         0xd906
+#define regRCC_DEV2_EPF2_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP13                                                                        0xd90d
+#define regRCC_DEV2_EPF2_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF2_STRAP14                                                                        0xd90e
+#define regRCC_DEV2_EPF2_STRAP14_BASE_IDX                                                               5
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_DEV0_2_RCC_VDM_SUPPORT                                                                   0xc440
+#define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX                                                          5
+#define regRCC_DEV0_2_RCC_BUS_CNTL                                                                      0xc441
+#define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX                                                             5
+#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC                                                         0xc442
+#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX                                                5
+#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL                                                                0xc443
+#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX                                                       5
+#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL                                                                 0xc444
+#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX                                                        5
+#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE                                                        0xc445
+#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX                                               5
+#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL                                                              0xc446
+#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX                                                     5
+#define regRCC_DEV0_2_RCC_MH_ARB_CNTL                                                                   0xc447
+#define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX                                                          5
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0                                                            0xc448
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX                                                   5
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1                                                            0xc449
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                   5
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH                                                                0xc44c
+#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_2_EP_PCIE_CNTL                                                                   0xc44e
+#define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX                                                          5
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL                                                               0xc44f
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS                                                             0xc450
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2                                                               0xc451
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL                                                               0xc452
+#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL                                                               0xc453
+#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL                                                            0xc454
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC                                                             0xc455
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2                                                            0xc456
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP                                                             0xc457
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR                                               0xc458
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL                                                            0xc458
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                               0xc458
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                               0xc459
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                               0xc459
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                               0xc459
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                               0xc459
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                               0xc45a
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                               0xc45a
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                               0xc45a
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL                                                            0xc45c
+#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED                                                              0xc45d
+#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX                                                     5
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL                                                                0xc45f
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID                                                        0xc460
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX                                               5
+#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL                                                               0xc461
+#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL                                                                0xc462
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL                                                          0xc463
+#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED                                                              0xc468
+#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH                                                               0xc469
+#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX                                                      5
+#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL                                                                  0xc46b
+#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX                                                         5
+#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL                                                           0xc46c
+#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX                                                  5
+#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2                                                              0xc46d
+#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL                                                              0xc46e
+#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL                                                              0xc46f
+#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0                                                              0xc470
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC                                                            0xc471
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX                                                   5
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2                                                           0xc472
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX                                                  5
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL                                                                0xc475
+#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX                                                       5
+#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL                                                                 0xc476
+#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX                                                        5
+#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL                                                           0xc477
+#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX                                                  5
+#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2                                                                0xc478
+#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX                                                       5
+#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC                                                             0xc479
+#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX                                                    5
+#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP                                                         0xc47a
+#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX                                                5
+
+
+// addressBlock: nbio_nbif0_rcc_dev1_RCCPORTDEC
+// base address: 0x10131200
+#define regRCC_DEV1_RCC_VDM_SUPPORT                                                                     0xc4c0
+#define regRCC_DEV1_RCC_VDM_SUPPORT_BASE_IDX                                                            5
+#define regRCC_DEV1_RCC_BUS_CNTL                                                                        0xc4c1
+#define regRCC_DEV1_RCC_BUS_CNTL_BASE_IDX                                                               5
+#define regRCC_DEV1_RCC_FEATURES_CONTROL_MISC                                                           0xc4c2
+#define regRCC_DEV1_RCC_FEATURES_CONTROL_MISC_BASE_IDX                                                  5
+#define regRCC_DEV1_RCC_DEV0_LINK_CNTL                                                                  0xc4c3
+#define regRCC_DEV1_RCC_DEV0_LINK_CNTL_BASE_IDX                                                         5
+#define regRCC_DEV1_RCC_CMN_LINK_CNTL                                                                   0xc4c4
+#define regRCC_DEV1_RCC_CMN_LINK_CNTL_BASE_IDX                                                          5
+#define regRCC_DEV1_RCC_EP_REQUESTERID_RESTORE                                                          0xc4c5
+#define regRCC_DEV1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX                                                 5
+#define regRCC_DEV1_RCC_LTR_LSWITCH_CNTL                                                                0xc4c6
+#define regRCC_DEV1_RCC_LTR_LSWITCH_CNTL_BASE_IDX                                                       5
+#define regRCC_DEV1_RCC_MH_ARB_CNTL                                                                     0xc4c7
+#define regRCC_DEV1_RCC_MH_ARB_CNTL_BASE_IDX                                                            5
+#define regRCC_DEV1_RCC_MARGIN_PARAM_CNTL0                                                              0xc4c8
+#define regRCC_DEV1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX                                                     5
+#define regRCC_DEV1_RCC_MARGIN_PARAM_CNTL1                                                              0xc4c9
+#define regRCC_DEV1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                     5
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev1_RCCPORTDEC
+// base address: 0x10131200
+#define regRCC_EP_DEV1_EP_PCIE_SCRATCH                                                                  0xc4cc
+#define regRCC_EP_DEV1_EP_PCIE_SCRATCH_BASE_IDX                                                         5
+#define regRCC_EP_DEV1_EP_PCIE_CNTL                                                                     0xc4ce
+#define regRCC_EP_DEV1_EP_PCIE_CNTL_BASE_IDX                                                            5
+#define regRCC_EP_DEV1_EP_PCIE_INT_CNTL                                                                 0xc4cf
+#define regRCC_EP_DEV1_EP_PCIE_INT_CNTL_BASE_IDX                                                        5
+#define regRCC_EP_DEV1_EP_PCIE_INT_STATUS                                                               0xc4d0
+#define regRCC_EP_DEV1_EP_PCIE_INT_STATUS_BASE_IDX                                                      5
+#define regRCC_EP_DEV1_EP_PCIE_RX_CNTL2                                                                 0xc4d1
+#define regRCC_EP_DEV1_EP_PCIE_RX_CNTL2_BASE_IDX                                                        5
+#define regRCC_EP_DEV1_EP_PCIE_BUS_CNTL                                                                 0xc4d2
+#define regRCC_EP_DEV1_EP_PCIE_BUS_CNTL_BASE_IDX                                                        5
+#define regRCC_EP_DEV1_EP_PCIE_CFG_CNTL                                                                 0xc4d3
+#define regRCC_EP_DEV1_EP_PCIE_CFG_CNTL_BASE_IDX                                                        5
+#define regRCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL                                                              0xc4d4
+#define regRCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL_BASE_IDX                                                     5
+#define regRCC_EP_DEV1_EP_PCIE_STRAP_MISC                                                               0xc4d5
+#define regRCC_EP_DEV1_EP_PCIE_STRAP_MISC_BASE_IDX                                                      5
+#define regRCC_EP_DEV1_EP_PCIE_STRAP_MISC2                                                              0xc4d6
+#define regRCC_EP_DEV1_EP_PCIE_STRAP_MISC2_BASE_IDX                                                     5
+#define regRCC_EP_DEV1_EP_PCIE_F0_DPA_CAP                                                               0xc4d7
+#define regRCC_EP_DEV1_EP_PCIE_F0_DPA_CAP_BASE_IDX                                                      5
+#define regRCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR                                                 0xc4d8
+#define regRCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX                                        5
+#define regRCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL                                                              0xc4d8
+#define regRCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL_BASE_IDX                                                     5
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                                 0xc4d8
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                        5
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                                 0xc4d9
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                        5
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                                 0xc4d9
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                        5
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                                 0xc4d9
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                        5
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                                 0xc4d9
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                        5
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                                 0xc4da
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                        5
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                                 0xc4da
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                        5
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                                 0xc4da
+#define regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                        5
+#define regRCC_EP_DEV1_EP_PCIE_PME_CONTROL                                                              0xc4dc
+#define regRCC_EP_DEV1_EP_PCIE_PME_CONTROL_BASE_IDX                                                     5
+#define regRCC_EP_DEV1_EP_PCIEP_RESERVED                                                                0xc4dd
+#define regRCC_EP_DEV1_EP_PCIEP_RESERVED_BASE_IDX                                                       5
+#define regRCC_EP_DEV1_EP_PCIE_TX_CNTL                                                                  0xc4df
+#define regRCC_EP_DEV1_EP_PCIE_TX_CNTL_BASE_IDX                                                         5
+#define regRCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID                                                          0xc4e0
+#define regRCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX                                                 5
+#define regRCC_EP_DEV1_EP_PCIE_ERR_CNTL                                                                 0xc4e1
+#define regRCC_EP_DEV1_EP_PCIE_ERR_CNTL_BASE_IDX                                                        5
+#define regRCC_EP_DEV1_EP_PCIE_RX_CNTL                                                                  0xc4e2
+#define regRCC_EP_DEV1_EP_PCIE_RX_CNTL_BASE_IDX                                                         5
+#define regRCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL                                                            0xc4e3
+#define regRCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX                                                   5
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev1_RCCPORTDEC
+// base address: 0x10131200
+#define regRCC_DWN_DEV1_DN_PCIE_RESERVED                                                                0xc4e8
+#define regRCC_DWN_DEV1_DN_PCIE_RESERVED_BASE_IDX                                                       5
+#define regRCC_DWN_DEV1_DN_PCIE_SCRATCH                                                                 0xc4e9
+#define regRCC_DWN_DEV1_DN_PCIE_SCRATCH_BASE_IDX                                                        5
+#define regRCC_DWN_DEV1_DN_PCIE_CNTL                                                                    0xc4eb
+#define regRCC_DWN_DEV1_DN_PCIE_CNTL_BASE_IDX                                                           5
+#define regRCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL                                                             0xc4ec
+#define regRCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL_BASE_IDX                                                    5
+#define regRCC_DWN_DEV1_DN_PCIE_RX_CNTL2                                                                0xc4ed
+#define regRCC_DWN_DEV1_DN_PCIE_RX_CNTL2_BASE_IDX                                                       5
+#define regRCC_DWN_DEV1_DN_PCIE_BUS_CNTL                                                                0xc4ee
+#define regRCC_DWN_DEV1_DN_PCIE_BUS_CNTL_BASE_IDX                                                       5
+#define regRCC_DWN_DEV1_DN_PCIE_CFG_CNTL                                                                0xc4ef
+#define regRCC_DWN_DEV1_DN_PCIE_CFG_CNTL_BASE_IDX                                                       5
+#define regRCC_DWN_DEV1_DN_PCIE_STRAP_F0                                                                0xc4f0
+#define regRCC_DWN_DEV1_DN_PCIE_STRAP_F0_BASE_IDX                                                       5
+#define regRCC_DWN_DEV1_DN_PCIE_STRAP_MISC                                                              0xc4f1
+#define regRCC_DWN_DEV1_DN_PCIE_STRAP_MISC_BASE_IDX                                                     5
+#define regRCC_DWN_DEV1_DN_PCIE_STRAP_MISC2                                                             0xc4f2
+#define regRCC_DWN_DEV1_DN_PCIE_STRAP_MISC2_BASE_IDX                                                    5
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev1_RCCPORTDEC
+// base address: 0x10131200
+#define regRCC_DWNP_DEV1_PCIE_ERR_CNTL                                                                  0xc4f5
+#define regRCC_DWNP_DEV1_PCIE_ERR_CNTL_BASE_IDX                                                         5
+#define regRCC_DWNP_DEV1_PCIE_RX_CNTL                                                                   0xc4f6
+#define regRCC_DWNP_DEV1_PCIE_RX_CNTL_BASE_IDX                                                          5
+#define regRCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL                                                             0xc4f7
+#define regRCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL_BASE_IDX                                                    5
+#define regRCC_DWNP_DEV1_PCIE_LC_CNTL2                                                                  0xc4f8
+#define regRCC_DWNP_DEV1_PCIE_LC_CNTL2_BASE_IDX                                                         5
+#define regRCC_DWNP_DEV1_PCIEP_STRAP_MISC                                                               0xc4f9
+#define regRCC_DWNP_DEV1_PCIEP_STRAP_MISC_BASE_IDX                                                      5
+#define regRCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP                                                           0xc4fa
+#define regRCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP_BASE_IDX                                                  5
+
+
+// addressBlock: nbio_nbif0_rcc_dev2_RCCPORTDEC
+// base address: 0x10131400
+#define regRCC_DEV2_RCC_VDM_SUPPORT                                                                     0xc540
+#define regRCC_DEV2_RCC_VDM_SUPPORT_BASE_IDX                                                            5
+#define regRCC_DEV2_RCC_BUS_CNTL                                                                        0xc541
+#define regRCC_DEV2_RCC_BUS_CNTL_BASE_IDX                                                               5
+#define regRCC_DEV2_RCC_FEATURES_CONTROL_MISC                                                           0xc542
+#define regRCC_DEV2_RCC_FEATURES_CONTROL_MISC_BASE_IDX                                                  5
+#define regRCC_DEV2_RCC_DEV0_LINK_CNTL                                                                  0xc543
+#define regRCC_DEV2_RCC_DEV0_LINK_CNTL_BASE_IDX                                                         5
+#define regRCC_DEV2_RCC_CMN_LINK_CNTL                                                                   0xc544
+#define regRCC_DEV2_RCC_CMN_LINK_CNTL_BASE_IDX                                                          5
+#define regRCC_DEV2_RCC_EP_REQUESTERID_RESTORE                                                          0xc545
+#define regRCC_DEV2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX                                                 5
+#define regRCC_DEV2_RCC_LTR_LSWITCH_CNTL                                                                0xc546
+#define regRCC_DEV2_RCC_LTR_LSWITCH_CNTL_BASE_IDX                                                       5
+#define regRCC_DEV2_RCC_MH_ARB_CNTL                                                                     0xc547
+#define regRCC_DEV2_RCC_MH_ARB_CNTL_BASE_IDX                                                            5
+#define regRCC_DEV2_RCC_MARGIN_PARAM_CNTL0                                                              0xc548
+#define regRCC_DEV2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX                                                     5
+#define regRCC_DEV2_RCC_MARGIN_PARAM_CNTL1                                                              0xc549
+#define regRCC_DEV2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                     5
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev2_RCCPORTDEC
+// base address: 0x10131400
+#define regRCC_EP_DEV2_EP_PCIE_SCRATCH                                                                  0xc54c
+#define regRCC_EP_DEV2_EP_PCIE_SCRATCH_BASE_IDX                                                         5
+#define regRCC_EP_DEV2_EP_PCIE_CNTL                                                                     0xc54e
+#define regRCC_EP_DEV2_EP_PCIE_CNTL_BASE_IDX                                                            5
+#define regRCC_EP_DEV2_EP_PCIE_INT_CNTL                                                                 0xc54f
+#define regRCC_EP_DEV2_EP_PCIE_INT_CNTL_BASE_IDX                                                        5
+#define regRCC_EP_DEV2_EP_PCIE_INT_STATUS                                                               0xc550
+#define regRCC_EP_DEV2_EP_PCIE_INT_STATUS_BASE_IDX                                                      5
+#define regRCC_EP_DEV2_EP_PCIE_RX_CNTL2                                                                 0xc551
+#define regRCC_EP_DEV2_EP_PCIE_RX_CNTL2_BASE_IDX                                                        5
+#define regRCC_EP_DEV2_EP_PCIE_BUS_CNTL                                                                 0xc552
+#define regRCC_EP_DEV2_EP_PCIE_BUS_CNTL_BASE_IDX                                                        5
+#define regRCC_EP_DEV2_EP_PCIE_CFG_CNTL                                                                 0xc553
+#define regRCC_EP_DEV2_EP_PCIE_CFG_CNTL_BASE_IDX                                                        5
+#define regRCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL                                                              0xc554
+#define regRCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL_BASE_IDX                                                     5
+#define regRCC_EP_DEV2_EP_PCIE_STRAP_MISC                                                               0xc555
+#define regRCC_EP_DEV2_EP_PCIE_STRAP_MISC_BASE_IDX                                                      5
+#define regRCC_EP_DEV2_EP_PCIE_STRAP_MISC2                                                              0xc556
+#define regRCC_EP_DEV2_EP_PCIE_STRAP_MISC2_BASE_IDX                                                     5
+#define regRCC_EP_DEV2_EP_PCIE_F0_DPA_CAP                                                               0xc557
+#define regRCC_EP_DEV2_EP_PCIE_F0_DPA_CAP_BASE_IDX                                                      5
+#define regRCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR                                                 0xc558
+#define regRCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX                                        5
+#define regRCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL                                                              0xc558
+#define regRCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL_BASE_IDX                                                     5
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                                 0xc558
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                        5
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                                 0xc559
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                        5
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                                 0xc559
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                        5
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                                 0xc559
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                        5
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                                 0xc559
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                        5
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                                 0xc55a
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                        5
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                                 0xc55a
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                        5
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                                 0xc55a
+#define regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                        5
+#define regRCC_EP_DEV2_EP_PCIE_PME_CONTROL                                                              0xc55c
+#define regRCC_EP_DEV2_EP_PCIE_PME_CONTROL_BASE_IDX                                                     5
+#define regRCC_EP_DEV2_EP_PCIEP_RESERVED                                                                0xc55d
+#define regRCC_EP_DEV2_EP_PCIEP_RESERVED_BASE_IDX                                                       5
+#define regRCC_EP_DEV2_EP_PCIE_TX_CNTL                                                                  0xc55f
+#define regRCC_EP_DEV2_EP_PCIE_TX_CNTL_BASE_IDX                                                         5
+#define regRCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID                                                          0xc560
+#define regRCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX                                                 5
+#define regRCC_EP_DEV2_EP_PCIE_ERR_CNTL                                                                 0xc561
+#define regRCC_EP_DEV2_EP_PCIE_ERR_CNTL_BASE_IDX                                                        5
+#define regRCC_EP_DEV2_EP_PCIE_RX_CNTL                                                                  0xc562
+#define regRCC_EP_DEV2_EP_PCIE_RX_CNTL_BASE_IDX                                                         5
+#define regRCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL                                                            0xc563
+#define regRCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX                                                   5
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev2_RCCPORTDEC
+// base address: 0x10131400
+#define regRCC_DWN_DEV2_DN_PCIE_RESERVED                                                                0xc568
+#define regRCC_DWN_DEV2_DN_PCIE_RESERVED_BASE_IDX                                                       5
+#define regRCC_DWN_DEV2_DN_PCIE_SCRATCH                                                                 0xc569
+#define regRCC_DWN_DEV2_DN_PCIE_SCRATCH_BASE_IDX                                                        5
+#define regRCC_DWN_DEV2_DN_PCIE_CNTL                                                                    0xc56b
+#define regRCC_DWN_DEV2_DN_PCIE_CNTL_BASE_IDX                                                           5
+#define regRCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL                                                             0xc56c
+#define regRCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL_BASE_IDX                                                    5
+#define regRCC_DWN_DEV2_DN_PCIE_RX_CNTL2                                                                0xc56d
+#define regRCC_DWN_DEV2_DN_PCIE_RX_CNTL2_BASE_IDX                                                       5
+#define regRCC_DWN_DEV2_DN_PCIE_BUS_CNTL                                                                0xc56e
+#define regRCC_DWN_DEV2_DN_PCIE_BUS_CNTL_BASE_IDX                                                       5
+#define regRCC_DWN_DEV2_DN_PCIE_CFG_CNTL                                                                0xc56f
+#define regRCC_DWN_DEV2_DN_PCIE_CFG_CNTL_BASE_IDX                                                       5
+#define regRCC_DWN_DEV2_DN_PCIE_STRAP_F0                                                                0xc570
+#define regRCC_DWN_DEV2_DN_PCIE_STRAP_F0_BASE_IDX                                                       5
+#define regRCC_DWN_DEV2_DN_PCIE_STRAP_MISC                                                              0xc571
+#define regRCC_DWN_DEV2_DN_PCIE_STRAP_MISC_BASE_IDX                                                     5
+#define regRCC_DWN_DEV2_DN_PCIE_STRAP_MISC2                                                             0xc572
+#define regRCC_DWN_DEV2_DN_PCIE_STRAP_MISC2_BASE_IDX                                                    5
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev2_RCCPORTDEC
+// base address: 0x10131400
+#define regRCC_DWNP_DEV2_PCIE_ERR_CNTL                                                                  0xc575
+#define regRCC_DWNP_DEV2_PCIE_ERR_CNTL_BASE_IDX                                                         5
+#define regRCC_DWNP_DEV2_PCIE_RX_CNTL                                                                   0xc576
+#define regRCC_DWNP_DEV2_PCIE_RX_CNTL_BASE_IDX                                                          5
+#define regRCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL                                                             0xc577
+#define regRCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL_BASE_IDX                                                    5
+#define regRCC_DWNP_DEV2_PCIE_LC_CNTL2                                                                  0xc578
+#define regRCC_DWNP_DEV2_PCIE_LC_CNTL2_BASE_IDX                                                         5
+#define regRCC_DWNP_DEV2_PCIEP_STRAP_MISC                                                               0xc579
+#define regRCC_DWNP_DEV2_PCIEP_STRAP_MISC_BASE_IDX                                                      5
+#define regRCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP                                                           0xc57a
+#define regRCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP_BASE_IDX                                                  5
+
+
+// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk
+// base address: 0x10100000
+#define regNBIF_STRAP_BIOS_CNTL                                                                         0xcc81
+#define regNBIF_STRAP_BIOS_CNTL_BASE_IDX                                                                5
+#define regMISC_SCRATCH                                                                                 0xe800
+#define regMISC_SCRATCH_BASE_IDX                                                                        5
+#define regINTR_LINE_POLARITY                                                                           0xe801
+#define regINTR_LINE_POLARITY_BASE_IDX                                                                  5
+#define regINTR_LINE_ENABLE                                                                             0xe802
+#define regINTR_LINE_ENABLE_BASE_IDX                                                                    5
+#define regOUTSTANDING_VC_ALLOC                                                                         0xe803
+#define regOUTSTANDING_VC_ALLOC_BASE_IDX                                                                5
+#define regBIFC_MISC_CTRL0                                                                              0xe804
+#define regBIFC_MISC_CTRL0_BASE_IDX                                                                     5
+#define regBIFC_MISC_CTRL1                                                                              0xe805
+#define regBIFC_MISC_CTRL1_BASE_IDX                                                                     5
+#define regBIFC_BME_ERR_LOG                                                                             0xe806
+#define regBIFC_BME_ERR_LOG_BASE_IDX                                                                    5
+#define regBIFC_LC_TIMER_CTRL                                                                           0xe807
+#define regBIFC_LC_TIMER_CTRL_BASE_IDX                                                                  5
+#define regBIFC_RCCBIH_BME_ERR_LOG0                                                                     0xe808
+#define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX                                                            5
+#define regBIFC_RCCBIH_BME_ERR_LOG1                                                                     0xe809
+#define regBIFC_RCCBIH_BME_ERR_LOG1_BASE_IDX                                                            5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1                                                            0xe80a
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3                                                            0xe80b
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5                                                            0xe80c
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7                                                            0xe80d
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1                                                            0xe80e
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3                                                            0xe80f
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5                                                            0xe810
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7                                                            0xe811
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1                                                            0xe812
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3                                                            0xe813
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5                                                            0xe814
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7                                                            0xe815
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_CNTL2_DEV0                                                                     0xe81a
+#define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX                                                            5
+#define regBIFC_DMA_ATTR_CNTL2_DEV1                                                                     0xe81b
+#define regBIFC_DMA_ATTR_CNTL2_DEV1_BASE_IDX                                                            5
+#define regBIFC_DMA_ATTR_CNTL2_DEV2                                                                     0xe81c
+#define regBIFC_DMA_ATTR_CNTL2_DEV2_BASE_IDX                                                            5
+#define regBME_DUMMY_CNTL_0                                                                             0xe825
+#define regBME_DUMMY_CNTL_0_BASE_IDX                                                                    5
+#define regBME_DUMMY_CNTL_1                                                                             0xe826
+#define regBME_DUMMY_CNTL_1_BASE_IDX                                                                    5
+#define regBIFC_HSTARB_CNTL                                                                             0xe828
+#define regBIFC_HSTARB_CNTL_BASE_IDX                                                                    5
+#define regBIFC_GSI_CNTL                                                                                0xe829
+#define regBIFC_GSI_CNTL_BASE_IDX                                                                       5
+#define regBIFC_PCIEFUNC_CNTL                                                                           0xe82a
+#define regBIFC_PCIEFUNC_CNTL_BASE_IDX                                                                  5
+#define regBIFC_PASID_CHECK_DIS                                                                         0xe82b
+#define regBIFC_PASID_CHECK_DIS_BASE_IDX                                                                5
+#define regBIFC_SDP_CNTL_0                                                                              0xe82c
+#define regBIFC_SDP_CNTL_0_BASE_IDX                                                                     5
+#define regBIFC_SDP_CNTL_1                                                                              0xe82d
+#define regBIFC_SDP_CNTL_1_BASE_IDX                                                                     5
+#define regBIFC_PASID_STS                                                                               0xe82e
+#define regBIFC_PASID_STS_BASE_IDX                                                                      5
+#define regBIFC_ATHUB_ACT_CNTL                                                                          0xe82f
+#define regBIFC_ATHUB_ACT_CNTL_BASE_IDX                                                                 5
+#define regBIFC_PERF_CNTL_0                                                                             0xe830
+#define regBIFC_PERF_CNTL_0_BASE_IDX                                                                    5
+#define regBIFC_PERF_CNTL_1                                                                             0xe831
+#define regBIFC_PERF_CNTL_1_BASE_IDX                                                                    5
+#define regBIFC_PERF_CNT_MMIO_RD                                                                        0xe832
+#define regBIFC_PERF_CNT_MMIO_RD_BASE_IDX                                                               5
+#define regBIFC_PERF_CNT_MMIO_WR                                                                        0xe833
+#define regBIFC_PERF_CNT_MMIO_WR_BASE_IDX                                                               5
+#define regBIFC_PERF_CNT_DMA_RD                                                                         0xe834
+#define regBIFC_PERF_CNT_DMA_RD_BASE_IDX                                                                5
+#define regBIFC_PERF_CNT_DMA_WR                                                                         0xe835
+#define regBIFC_PERF_CNT_DMA_WR_BASE_IDX                                                                5
+#define regNBIF_REGIF_ERRSET_CTRL                                                                       0xe836
+#define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX                                                              5
+#define regBIFC_SDP_CNTL_2                                                                              0xe837
+#define regBIFC_SDP_CNTL_2_BASE_IDX                                                                     5
+#define regNBIF_PGMST_CTRL                                                                              0xe838
+#define regNBIF_PGMST_CTRL_BASE_IDX                                                                     5
+#define regNBIF_PGSLV_CTRL                                                                              0xe839
+#define regNBIF_PGSLV_CTRL_BASE_IDX                                                                     5
+#define regNBIF_PG_MISC_CTRL                                                                            0xe83a
+#define regNBIF_PG_MISC_CTRL_BASE_IDX                                                                   5
+#define regNBIF_HST_MISC_CTRL                                                                           0xe83b
+#define regNBIF_HST_MISC_CTRL_BASE_IDX                                                                  5
+#define regSMN_MST_EP_CNTL3                                                                             0xe83c
+#define regSMN_MST_EP_CNTL3_BASE_IDX                                                                    5
+#define regSMN_MST_EP_CNTL4                                                                             0xe83d
+#define regSMN_MST_EP_CNTL4_BASE_IDX                                                                    5
+#define regSMN_MST_CNTL1                                                                                0xe83e
+#define regSMN_MST_CNTL1_BASE_IDX                                                                       5
+#define regSMN_MST_EP_CNTL5                                                                             0xe83f
+#define regSMN_MST_EP_CNTL5_BASE_IDX                                                                    5
+#define regBIF_SELFRING_BUFFER_VID                                                                      0xe840
+#define regBIF_SELFRING_BUFFER_VID_BASE_IDX                                                             5
+#define regBIF_SELFRING_VECTOR_CNTL                                                                     0xe841
+#define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX                                                            5
+#define regNBIF_STRAP_WRITE_CTRL                                                                        0xe845
+#define regNBIF_STRAP_WRITE_CTRL_BASE_IDX                                                               5
+#define regNBIF_INTX_DSTATE_MISC_CNTL                                                                   0xe846
+#define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX                                                          5
+#define regNBIF_PENDING_MISC_CNTL                                                                       0xe847
+#define regNBIF_PENDING_MISC_CNTL_BASE_IDX                                                              5
+#define regBIF_GMI_WRR_WEIGHT                                                                           0xe848
+#define regBIF_GMI_WRR_WEIGHT_BASE_IDX                                                                  5
+#define regBIF_GMI_WRR_WEIGHT2                                                                          0xe849
+#define regBIF_GMI_WRR_WEIGHT2_BASE_IDX                                                                 5
+#define regBIF_GMI_WRR_WEIGHT3                                                                          0xe84a
+#define regBIF_GMI_WRR_WEIGHT3_BASE_IDX                                                                 5
+#define regNBIF_PWRBRK_REQUEST                                                                          0xe84c
+#define regNBIF_PWRBRK_REQUEST_BASE_IDX                                                                 5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F0                                                                   0xe850
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F1                                                                   0xe851
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F2                                                                   0xe852
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F2_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F3                                                                   0xe853
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F3_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F4                                                                   0xe854
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F4_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F5                                                                   0xe855
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F5_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F6                                                                   0xe856
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F6_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F7                                                                   0xe857
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F7_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV1_F0                                                                   0xe858
+#define regBIF_ATOMIC_ERR_LOG_DEV1_F0_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV1_F1                                                                   0xe859
+#define regBIF_ATOMIC_ERR_LOG_DEV1_F1_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV2_F0                                                                   0xe85a
+#define regBIF_ATOMIC_ERR_LOG_DEV2_F0_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV2_F1                                                                   0xe85b
+#define regBIF_ATOMIC_ERR_LOG_DEV2_F1_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV2_F2                                                                   0xe85c
+#define regBIF_ATOMIC_ERR_LOG_DEV2_F2_BASE_IDX                                                          5
+#define regBIF_DMA_MP4_ERR_LOG                                                                          0xe870
+#define regBIF_DMA_MP4_ERR_LOG_BASE_IDX                                                                 5
+#define regBIF_PASID_ERR_LOG                                                                            0xe871
+#define regBIF_PASID_ERR_LOG_BASE_IDX                                                                   5
+#define regBIF_PASID_ERR_CLR                                                                            0xe872
+#define regBIF_PASID_ERR_CLR_BASE_IDX                                                                   5
+#define regOBFF_EMU_CFG                                                                                 0xe874
+#define regOBFF_EMU_CFG_BASE_IDX                                                                        5
+#define regEP0_INTR_URGENT_CAP                                                                          0xe875
+#define regEP0_INTR_URGENT_CAP_BASE_IDX                                                                 5
+#define regEP1_INTR_URGENT_CAP                                                                          0xe876
+#define regEP1_INTR_URGENT_CAP_BASE_IDX                                                                 5
+#define regEP2_INTR_URGENT_CAP                                                                          0xe877
+#define regEP2_INTR_URGENT_CAP_BASE_IDX                                                                 5
+#define regEP_PEND_BLOCK_MSK                                                                            0xe87c
+#define regEP_PEND_BLOCK_MSK_BASE_IDX                                                                   5
+#define regNBIF_VWIRE_CTRL                                                                              0xe880
+#define regNBIF_VWIRE_CTRL_BASE_IDX                                                                     5
+#define regNBIF_SMN_VWR_VCHG_DIS_CTRL                                                                   0xe881
+#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX                                                          5
+#define regNBIF_SMN_VWR_VCHG_RST_CTRL0                                                                  0xe882
+#define regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX                                                         5
+#define regNBIF_SMN_VWR_VCHG_TRIG                                                                       0xe884
+#define regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX                                                              5
+#define regNBIF_SMN_VWR_WTRIG_CNTL                                                                      0xe885
+#define regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX                                                             5
+#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1                                                                 0xe886
+#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX                                                        5
+#define regNBIF_MGCG_CTRL_LCLK                                                                          0xe887
+#define regNBIF_MGCG_CTRL_LCLK_BASE_IDX                                                                 5
+#define regNBIF_DS_CTRL_LCLK                                                                            0xe888
+#define regNBIF_DS_CTRL_LCLK_BASE_IDX                                                                   5
+#define regSMN_MST_CNTL0                                                                                0xe889
+#define regSMN_MST_CNTL0_BASE_IDX                                                                       5
+#define regSMN_MST_EP_CNTL1                                                                             0xe88a
+#define regSMN_MST_EP_CNTL1_BASE_IDX                                                                    5
+#define regSMN_MST_EP_CNTL2                                                                             0xe88b
+#define regSMN_MST_EP_CNTL2_BASE_IDX                                                                    5
+#define regNBIF_SDP_VWR_VCHG_DIS_CTRL                                                                   0xe88c
+#define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX                                                          5
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL0                                                                  0xe88d
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX                                                         5
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL1                                                                  0xe88e
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX                                                         5
+#define regNBIF_SDP_VWR_VCHG_TRIG                                                                       0xe88f
+#define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX                                                              5
+#define regNBIF_SHUB_TODET_CTRL                                                                         0xe898
+#define regNBIF_SHUB_TODET_CTRL_BASE_IDX                                                                5
+#define regNBIF_SHUB_TODET_CLIENT_CTRL                                                                  0xe899
+#define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX                                                         5
+#define regNBIF_SHUB_TODET_CLIENT_STATUS                                                                0xe89a
+#define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX                                                       5
+#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL                                                               0xe89b
+#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX                                                      5
+#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC                                                            0xe8c0
+#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX                                                   5
+#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC                                                            0xe8c1
+#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX                                                   5
+#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC                                                              0xe8c2
+#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX                                                     5
+#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC                                                              0xe8c3
+#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX                                                     5
+#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC                                                            0xe8c4
+#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX                                                   5
+#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC                                                            0xe8c5
+#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX                                                   5
+#define regDISCON_HYSTERESIS_HEAD_CTRL                                                                  0xe8c6
+#define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX                                                         5
+#define regBIFC_PCIE_BDF_CNTL0                                                                          0xe8d0
+#define regBIFC_PCIE_BDF_CNTL0_BASE_IDX                                                                 5
+#define regBIFC_PCIE_BDF_CNTL1                                                                          0xe8d1
+#define regBIFC_PCIE_BDF_CNTL1_BASE_IDX                                                                 5
+#define regBIFC_EARLY_WAKEUP_CNTL                                                                       0xe8d2
+#define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX                                                              5
+
+
+// addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk
+// base address: 0x10100000
+#define regHARD_RST_CTRL                                                                                0xe000
+#define regHARD_RST_CTRL_BASE_IDX                                                                       5
+#define regSELF_SOFT_RST                                                                                0xe002
+#define regSELF_SOFT_RST_BASE_IDX                                                                       5
+#define regBIF_GFX_DRV_VPU_RST                                                                          0xe003
+#define regBIF_GFX_DRV_VPU_RST_BASE_IDX                                                                 5
+#define regBIF_RST_MISC_CTRL                                                                            0xe004
+#define regBIF_RST_MISC_CTRL_BASE_IDX                                                                   5
+#define regBIF_RST_MISC_CTRL2                                                                           0xe005
+#define regBIF_RST_MISC_CTRL2_BASE_IDX                                                                  5
+#define regBIF_RST_MISC_CTRL3                                                                           0xe006
+#define regBIF_RST_MISC_CTRL3_BASE_IDX                                                                  5
+#define regDEV0_PF0_FLR_RST_CTRL                                                                        0xe008
+#define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV0_PF1_FLR_RST_CTRL                                                                        0xe009
+#define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV0_PF2_FLR_RST_CTRL                                                                        0xe00a
+#define regDEV0_PF2_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV0_PF3_FLR_RST_CTRL                                                                        0xe00b
+#define regDEV0_PF3_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV0_PF4_FLR_RST_CTRL                                                                        0xe00c
+#define regDEV0_PF4_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV0_PF5_FLR_RST_CTRL                                                                        0xe00d
+#define regDEV0_PF5_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV0_PF6_FLR_RST_CTRL                                                                        0xe00e
+#define regDEV0_PF6_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV0_PF7_FLR_RST_CTRL                                                                        0xe00f
+#define regDEV0_PF7_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regBIF_INST_RESET_INTR_STS                                                                      0xe010
+#define regBIF_INST_RESET_INTR_STS_BASE_IDX                                                             5
+#define regBIF_PF_FLR_INTR_STS                                                                          0xe011
+#define regBIF_PF_FLR_INTR_STS_BASE_IDX                                                                 5
+#define regBIF_D3HOTD0_INTR_STS                                                                         0xe012
+#define regBIF_D3HOTD0_INTR_STS_BASE_IDX                                                                5
+#define regBIF_POWER_INTR_STS                                                                           0xe014
+#define regBIF_POWER_INTR_STS_BASE_IDX                                                                  5
+#define regBIF_PF_DSTATE_INTR_STS                                                                       0xe015
+#define regBIF_PF_DSTATE_INTR_STS_BASE_IDX                                                              5
+#define regSELF_SOFT_RST_2                                                                              0xe016
+#define regSELF_SOFT_RST_2_BASE_IDX                                                                     5
+#define regBIF_INST_RESET_INTR_MASK                                                                     0xe020
+#define regBIF_INST_RESET_INTR_MASK_BASE_IDX                                                            5
+#define regBIF_PF_FLR_INTR_MASK                                                                         0xe021
+#define regBIF_PF_FLR_INTR_MASK_BASE_IDX                                                                5
+#define regBIF_D3HOTD0_INTR_MASK                                                                        0xe022
+#define regBIF_D3HOTD0_INTR_MASK_BASE_IDX                                                               5
+#define regBIF_POWER_INTR_MASK                                                                          0xe024
+#define regBIF_POWER_INTR_MASK_BASE_IDX                                                                 5
+#define regBIF_PF_DSTATE_INTR_MASK                                                                      0xe025
+#define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX                                                             5
+#define regBIF_PF_FLR_RST                                                                               0xe040
+#define regBIF_PF_FLR_RST_BASE_IDX                                                                      5
+#define regBIF_DEV0_PF0_DSTATE_VALUE                                                                    0xe050
+#define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV0_PF1_DSTATE_VALUE                                                                    0xe051
+#define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV0_PF2_DSTATE_VALUE                                                                    0xe052
+#define regBIF_DEV0_PF2_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV0_PF3_DSTATE_VALUE                                                                    0xe053
+#define regBIF_DEV0_PF3_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV0_PF4_DSTATE_VALUE                                                                    0xe054
+#define regBIF_DEV0_PF4_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV0_PF5_DSTATE_VALUE                                                                    0xe055
+#define regBIF_DEV0_PF5_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV0_PF6_DSTATE_VALUE                                                                    0xe056
+#define regBIF_DEV0_PF6_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV0_PF7_DSTATE_VALUE                                                                    0xe057
+#define regBIF_DEV0_PF7_DSTATE_VALUE_BASE_IDX                                                           5
+#define regDEV0_PF0_D3HOTD0_RST_CTRL                                                                    0xe078
+#define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV0_PF1_D3HOTD0_RST_CTRL                                                                    0xe079
+#define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV0_PF2_D3HOTD0_RST_CTRL                                                                    0xe07a
+#define regDEV0_PF2_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV0_PF3_D3HOTD0_RST_CTRL                                                                    0xe07b
+#define regDEV0_PF3_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV0_PF4_D3HOTD0_RST_CTRL                                                                    0xe07c
+#define regDEV0_PF4_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV0_PF5_D3HOTD0_RST_CTRL                                                                    0xe07d
+#define regDEV0_PF5_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV0_PF6_D3HOTD0_RST_CTRL                                                                    0xe07e
+#define regDEV0_PF6_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV0_PF7_D3HOTD0_RST_CTRL                                                                    0xe07f
+#define regDEV0_PF7_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV1_PF0_FLR_RST_CTRL                                                                        0xe200
+#define regDEV1_PF0_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV1_PF1_FLR_RST_CTRL                                                                        0xe201
+#define regDEV1_PF1_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV1_PF2_FLR_RST_CTRL                                                                        0xe202
+#define regDEV1_PF2_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV1_PF3_FLR_RST_CTRL                                                                        0xe203
+#define regDEV1_PF3_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV1_PF4_FLR_RST_CTRL                                                                        0xe204
+#define regDEV1_PF4_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV1_PF5_FLR_RST_CTRL                                                                        0xe205
+#define regDEV1_PF5_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV1_PF6_FLR_RST_CTRL                                                                        0xe206
+#define regDEV1_PF6_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV1_PF7_FLR_RST_CTRL                                                                        0xe207
+#define regDEV1_PF7_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regBIF_DEV1_PF0_DSTATE_VALUE                                                                    0xe208
+#define regBIF_DEV1_PF0_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV1_PF1_DSTATE_VALUE                                                                    0xe209
+#define regBIF_DEV1_PF1_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV1_PF2_DSTATE_VALUE                                                                    0xe20a
+#define regBIF_DEV1_PF2_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV1_PF3_DSTATE_VALUE                                                                    0xe20b
+#define regBIF_DEV1_PF3_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV1_PF4_DSTATE_VALUE                                                                    0xe20c
+#define regBIF_DEV1_PF4_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV1_PF5_DSTATE_VALUE                                                                    0xe20d
+#define regBIF_DEV1_PF5_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV1_PF6_DSTATE_VALUE                                                                    0xe20e
+#define regBIF_DEV1_PF6_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV1_PF7_DSTATE_VALUE                                                                    0xe20f
+#define regBIF_DEV1_PF7_DSTATE_VALUE_BASE_IDX                                                           5
+#define regDEV1_PF0_D3HOTD0_RST_CTRL                                                                    0xe210
+#define regDEV1_PF0_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV1_PF1_D3HOTD0_RST_CTRL                                                                    0xe211
+#define regDEV1_PF1_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV1_PF2_D3HOTD0_RST_CTRL                                                                    0xe212
+#define regDEV1_PF2_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV1_PF3_D3HOTD0_RST_CTRL                                                                    0xe213
+#define regDEV1_PF3_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV1_PF4_D3HOTD0_RST_CTRL                                                                    0xe214
+#define regDEV1_PF4_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV1_PF5_D3HOTD0_RST_CTRL                                                                    0xe215
+#define regDEV1_PF5_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV1_PF6_D3HOTD0_RST_CTRL                                                                    0xe216
+#define regDEV1_PF6_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV1_PF7_D3HOTD0_RST_CTRL                                                                    0xe217
+#define regDEV1_PF7_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV2_PF0_FLR_RST_CTRL                                                                        0xe218
+#define regDEV2_PF0_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV2_PF1_FLR_RST_CTRL                                                                        0xe219
+#define regDEV2_PF1_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV2_PF2_FLR_RST_CTRL                                                                        0xe21a
+#define regDEV2_PF2_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV2_PF3_FLR_RST_CTRL                                                                        0xe21b
+#define regDEV2_PF3_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV2_PF4_FLR_RST_CTRL                                                                        0xe21c
+#define regDEV2_PF4_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV2_PF5_FLR_RST_CTRL                                                                        0xe21d
+#define regDEV2_PF5_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV2_PF6_FLR_RST_CTRL                                                                        0xe21e
+#define regDEV2_PF6_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV2_PF7_FLR_RST_CTRL                                                                        0xe21f
+#define regDEV2_PF7_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regBIF_DEV2_PF0_DSTATE_VALUE                                                                    0xe220
+#define regBIF_DEV2_PF0_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV2_PF1_DSTATE_VALUE                                                                    0xe221
+#define regBIF_DEV2_PF1_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV2_PF2_DSTATE_VALUE                                                                    0xe222
+#define regBIF_DEV2_PF2_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV2_PF3_DSTATE_VALUE                                                                    0xe223
+#define regBIF_DEV2_PF3_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV2_PF4_DSTATE_VALUE                                                                    0xe224
+#define regBIF_DEV2_PF4_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV2_PF5_DSTATE_VALUE                                                                    0xe225
+#define regBIF_DEV2_PF5_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV2_PF6_DSTATE_VALUE                                                                    0xe226
+#define regBIF_DEV2_PF6_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV2_PF7_DSTATE_VALUE                                                                    0xe227
+#define regBIF_DEV2_PF7_DSTATE_VALUE_BASE_IDX                                                           5
+#define regDEV2_PF0_D3HOTD0_RST_CTRL                                                                    0xe228
+#define regDEV2_PF0_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV2_PF1_D3HOTD0_RST_CTRL                                                                    0xe229
+#define regDEV2_PF1_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV2_PF2_D3HOTD0_RST_CTRL                                                                    0xe22a
+#define regDEV2_PF2_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV2_PF3_D3HOTD0_RST_CTRL                                                                    0xe22b
+#define regDEV2_PF3_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV2_PF4_D3HOTD0_RST_CTRL                                                                    0xe22c
+#define regDEV2_PF4_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV2_PF5_D3HOTD0_RST_CTRL                                                                    0xe22d
+#define regDEV2_PF5_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV2_PF6_D3HOTD0_RST_CTRL                                                                    0xe22e
+#define regDEV2_PF6_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV2_PF7_D3HOTD0_RST_CTRL                                                                    0xe22f
+#define regDEV2_PF7_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regBIF_PORT0_DSTATE_VALUE                                                                       0xe230
+#define regBIF_PORT0_DSTATE_VALUE_BASE_IDX                                                              5
+#define regBIF_PORT1_DSTATE_VALUE                                                                       0xe231
+#define regBIF_PORT1_DSTATE_VALUE_BASE_IDX                                                              5
+#define regBIF_PORT2_DSTATE_VALUE                                                                       0xe232
+#define regBIF_PORT2_DSTATE_VALUE_BASE_IDX                                                              5
+
+
+// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk
+// base address: 0x10100000
+#define regBIFL_RAS_CENTRAL_CNTL                                                                        0xe400
+#define regBIFL_RAS_CENTRAL_CNTL_BASE_IDX                                                               5
+#define regBIFL_RAS_CENTRAL_STATUS                                                                      0xe410
+#define regBIFL_RAS_CENTRAL_STATUS_BASE_IDX                                                             5
+#define regBIFL_RAS_LEAF0_CTRL                                                                          0xe420
+#define regBIFL_RAS_LEAF0_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF1_CTRL                                                                          0xe421
+#define regBIFL_RAS_LEAF1_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF2_CTRL                                                                          0xe422
+#define regBIFL_RAS_LEAF2_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF3_CTRL                                                                          0xe423
+#define regBIFL_RAS_LEAF3_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF0_STATUS                                                                        0xe430
+#define regBIFL_RAS_LEAF0_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF1_STATUS                                                                        0xe431
+#define regBIFL_RAS_LEAF1_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF2_STATUS                                                                        0xe432
+#define regBIFL_RAS_LEAF2_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF3_STATUS                                                                        0xe433
+#define regBIFL_RAS_LEAF3_STATUS_BASE_IDX                                                               5
+#define regBIFL_IOHUB_RAS_IH_CNTL                                                                       0xe7fe
+#define regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX                                                              5
+#define regBIFL_RAS_VWR_FROM_IOHUB                                                                      0xe7ff
+#define regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX                                                             5
+
+
+// addressBlock: nbio_nbif0_nbif_sion_SIONDEC
+// base address: 0x10100000
+#define regSION_CL0_RdRsp_BurstTarget_REG0                                                              0xe900
+#define regSION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX                                                     5
+#define regSION_CL0_RdRsp_BurstTarget_REG1                                                              0xe901
+#define regSION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX                                                     5
+#define regSION_CL0_RdRsp_TimeSlot_REG0                                                                 0xe902
+#define regSION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX                                                        5
+#define regSION_CL0_RdRsp_TimeSlot_REG1                                                                 0xe903
+#define regSION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX                                                        5
+#define regSION_CL0_WrRsp_BurstTarget_REG0                                                              0xe904
+#define regSION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX                                                     5
+#define regSION_CL0_WrRsp_BurstTarget_REG1                                                              0xe905
+#define regSION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX                                                     5
+#define regSION_CL0_WrRsp_TimeSlot_REG0                                                                 0xe906
+#define regSION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX                                                        5
+#define regSION_CL0_WrRsp_TimeSlot_REG1                                                                 0xe907
+#define regSION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX                                                        5
+#define regSION_CL0_Req_BurstTarget_REG0                                                                0xe908
+#define regSION_CL0_Req_BurstTarget_REG0_BASE_IDX                                                       5
+#define regSION_CL0_Req_BurstTarget_REG1                                                                0xe909
+#define regSION_CL0_Req_BurstTarget_REG1_BASE_IDX                                                       5
+#define regSION_CL0_Req_TimeSlot_REG0                                                                   0xe90a
+#define regSION_CL0_Req_TimeSlot_REG0_BASE_IDX                                                          5
+#define regSION_CL0_Req_TimeSlot_REG1                                                                   0xe90b
+#define regSION_CL0_Req_TimeSlot_REG1_BASE_IDX                                                          5
+#define regSION_CL0_ReqPoolCredit_Alloc_REG0                                                            0xe90c
+#define regSION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX                                                   5
+#define regSION_CL0_ReqPoolCredit_Alloc_REG1                                                            0xe90d
+#define regSION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX                                                   5
+#define regSION_CL0_DataPoolCredit_Alloc_REG0                                                           0xe90e
+#define regSION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX                                                  5
+#define regSION_CL0_DataPoolCredit_Alloc_REG1                                                           0xe90f
+#define regSION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX                                                  5
+#define regSION_CL0_RdRspPoolCredit_Alloc_REG0                                                          0xe910
+#define regSION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX                                                 5
+#define regSION_CL0_RdRspPoolCredit_Alloc_REG1                                                          0xe911
+#define regSION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX                                                 5
+#define regSION_CL0_WrRspPoolCredit_Alloc_REG0                                                          0xe912
+#define regSION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX                                                 5
+#define regSION_CL0_WrRspPoolCredit_Alloc_REG1                                                          0xe913
+#define regSION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX                                                 5
+#define regSION_CL1_RdRsp_BurstTarget_REG0                                                              0xe914
+#define regSION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX                                                     5
+#define regSION_CL1_RdRsp_BurstTarget_REG1                                                              0xe915
+#define regSION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX                                                     5
+#define regSION_CL1_RdRsp_TimeSlot_REG0                                                                 0xe916
+#define regSION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX                                                        5
+#define regSION_CL1_RdRsp_TimeSlot_REG1                                                                 0xe917
+#define regSION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX                                                        5
+#define regSION_CL1_WrRsp_BurstTarget_REG0                                                              0xe918
+#define regSION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX                                                     5
+#define regSION_CL1_WrRsp_BurstTarget_REG1                                                              0xe919
+#define regSION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX                                                     5
+#define regSION_CL1_WrRsp_TimeSlot_REG0                                                                 0xe91a
+#define regSION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX                                                        5
+#define regSION_CL1_WrRsp_TimeSlot_REG1                                                                 0xe91b
+#define regSION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX                                                        5
+#define regSION_CL1_Req_BurstTarget_REG0                                                                0xe91c
+#define regSION_CL1_Req_BurstTarget_REG0_BASE_IDX                                                       5
+#define regSION_CL1_Req_BurstTarget_REG1                                                                0xe91d
+#define regSION_CL1_Req_BurstTarget_REG1_BASE_IDX                                                       5
+#define regSION_CL1_Req_TimeSlot_REG0                                                                   0xe91e
+#define regSION_CL1_Req_TimeSlot_REG0_BASE_IDX                                                          5
+#define regSION_CL1_Req_TimeSlot_REG1                                                                   0xe91f
+#define regSION_CL1_Req_TimeSlot_REG1_BASE_IDX                                                          5
+#define regSION_CL1_ReqPoolCredit_Alloc_REG0                                                            0xe920
+#define regSION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX                                                   5
+#define regSION_CL1_ReqPoolCredit_Alloc_REG1                                                            0xe921
+#define regSION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX                                                   5
+#define regSION_CL1_DataPoolCredit_Alloc_REG0                                                           0xe922
+#define regSION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX                                                  5
+#define regSION_CL1_DataPoolCredit_Alloc_REG1                                                           0xe923
+#define regSION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX                                                  5
+#define regSION_CL1_RdRspPoolCredit_Alloc_REG0                                                          0xe924
+#define regSION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX                                                 5
+#define regSION_CL1_RdRspPoolCredit_Alloc_REG1                                                          0xe925
+#define regSION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX                                                 5
+#define regSION_CL1_WrRspPoolCredit_Alloc_REG0                                                          0xe926
+#define regSION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX                                                 5
+#define regSION_CL1_WrRspPoolCredit_Alloc_REG1                                                          0xe927
+#define regSION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX                                                 5
+#define regSION_CL2_RdRsp_BurstTarget_REG0                                                              0xe928
+#define regSION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX                                                     5
+#define regSION_CL2_RdRsp_BurstTarget_REG1                                                              0xe929
+#define regSION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX                                                     5
+#define regSION_CL2_RdRsp_TimeSlot_REG0                                                                 0xe92a
+#define regSION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX                                                        5
+#define regSION_CL2_RdRsp_TimeSlot_REG1                                                                 0xe92b
+#define regSION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX                                                        5
+#define regSION_CL2_WrRsp_BurstTarget_REG0                                                              0xe92c
+#define regSION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX                                                     5
+#define regSION_CL2_WrRsp_BurstTarget_REG1                                                              0xe92d
+#define regSION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX                                                     5
+#define regSION_CL2_WrRsp_TimeSlot_REG0                                                                 0xe92e
+#define regSION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX                                                        5
+#define regSION_CL2_WrRsp_TimeSlot_REG1                                                                 0xe92f
+#define regSION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX                                                        5
+#define regSION_CL2_Req_BurstTarget_REG0                                                                0xe930
+#define regSION_CL2_Req_BurstTarget_REG0_BASE_IDX                                                       5
+#define regSION_CL2_Req_BurstTarget_REG1                                                                0xe931
+#define regSION_CL2_Req_BurstTarget_REG1_BASE_IDX                                                       5
+#define regSION_CL2_Req_TimeSlot_REG0                                                                   0xe932
+#define regSION_CL2_Req_TimeSlot_REG0_BASE_IDX                                                          5
+#define regSION_CL2_Req_TimeSlot_REG1                                                                   0xe933
+#define regSION_CL2_Req_TimeSlot_REG1_BASE_IDX                                                          5
+#define regSION_CL2_ReqPoolCredit_Alloc_REG0                                                            0xe934
+#define regSION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX                                                   5
+#define regSION_CL2_ReqPoolCredit_Alloc_REG1                                                            0xe935
+#define regSION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX                                                   5
+#define regSION_CL2_DataPoolCredit_Alloc_REG0                                                           0xe936
+#define regSION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX                                                  5
+#define regSION_CL2_DataPoolCredit_Alloc_REG1                                                           0xe937
+#define regSION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX                                                  5
+#define regSION_CL2_RdRspPoolCredit_Alloc_REG0                                                          0xe938
+#define regSION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX                                                 5
+#define regSION_CL2_RdRspPoolCredit_Alloc_REG1                                                          0xe939
+#define regSION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX                                                 5
+#define regSION_CL2_WrRspPoolCredit_Alloc_REG0                                                          0xe93a
+#define regSION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX                                                 5
+#define regSION_CL2_WrRspPoolCredit_Alloc_REG1                                                          0xe93b
+#define regSION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX                                                 5
+#define regSION_CNTL_REG0                                                                               0xe93c
+#define regSION_CNTL_REG0_BASE_IDX                                                                      5
+#define regSION_CNTL_REG1                                                                               0xe93d
+#define regSION_CNTL_REG1_BASE_IDX                                                                      5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID                                                                0x10000
+#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID                                                                0x10000
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_COMMAND                                                                  0x10001
+#define regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_0_STATUS                                                                   0x10001
+#define regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID                                                              0x10002
+#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE                                                           0x10002
+#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS                                                                0x10002
+#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS                                                               0x10002
+#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE                                                               0x10003
+#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LATENCY                                                                  0x10003
+#define regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_0_HEADER                                                                   0x10003
+#define regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_0_BIST                                                                     0x10003
+#define regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1                                                              0x10004
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2                                                              0x10005
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3                                                              0x10006
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4                                                              0x10007
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5                                                              0x10008
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6                                                              0x10009
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR                                                          0x1000a
+#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID                                                               0x1000b
+#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR                                                            0x1000c
+#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR                                                                  0x1000d
+#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE                                                           0x1000f
+#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN                                                            0x1000f
+#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT                                                                0x1000f
+#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY                                                              0x1000f
+#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST                                                          0x10012
+#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W                                                             0x10013
+#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST                                                             0x10014
+#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP                                                                  0x10014
+#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL                                                          0x10015
+#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST                                                            0x10019
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP                                                                 0x10019
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP                                                               0x1001a
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL                                                              0x1001b
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS                                                            0x1001b
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP                                                                 0x1001c
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL                                                                0x1001d
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS                                                              0x1001d
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2                                                              0x10022
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2                                                             0x10023
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2                                                           0x10023
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2                                                                0x10024
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2                                                               0x10025
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2                                                             0x10025
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST                                                             0x10028
+#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL                                                             0x10028
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO                                                          0x10029
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI                                                          0x1002a
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA                                                             0x1002a
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA                                                         0x1002a
+#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK                                                                 0x1002b
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64                                                          0x1002b
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64                                                      0x1002b
+#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64                                                              0x1002c
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING                                                              0x1002c
+#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64                                                           0x1002d
+#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST                                                            0x10030
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL                                                            0x10030
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE                                                               0x10031
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA                                                                 0x10032
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x10040
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x10041
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1                                                    0x10042
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2                                                    0x10043
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST                                                     0x10044
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1                                                    0x10045
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2                                                    0x10046
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL                                                        0x10047
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS                                                      0x10047
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP                                                    0x10048
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL                                                   0x10049
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS                                                 0x1004a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP                                                    0x1004b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL                                                   0x1004c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS                                                 0x1004d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                         0x10050
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1                                                  0x10051
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2                                                  0x10052
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x10054
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS                                                   0x10055
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK                                                     0x10056
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x10057
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS                                                     0x10058
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK                                                       0x10059
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x1005a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0                                                            0x1005b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1                                                            0x1005c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2                                                            0x1005d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3                                                            0x1005e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0                                                     0x10062
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1                                                     0x10063
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2                                                     0x10064
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3                                                     0x10065
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST                                                    0x10080
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP                                                            0x10081
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL                                                           0x10082
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP                                                            0x10083
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL                                                           0x10084
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP                                                            0x10085
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL                                                           0x10086
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP                                                            0x10087
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL                                                           0x10088
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP                                                            0x10089
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL                                                           0x1008a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP                                                            0x1008b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL                                                           0x1008c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x10090
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x10091
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA                                                     0x10092
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP                                                      0x10093
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST                                                    0x10094
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP                                                             0x10095
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR                                               0x10096
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS                                                          0x10097
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL                                                            0x10097
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x10098
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x10098
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x10098
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x10098
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x10099
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x10099
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x10099
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x10099
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST                                              0x1009c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3                                                          0x1009d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS                                                   0x1009e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL                                            0x1009f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL                                            0x1009f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL                                            0x100a0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL                                            0x100a0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL                                            0x100a1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL                                            0x100a1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL                                            0x100a2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL                                            0x100a2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL                                            0x100a3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL                                            0x100a3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL                                           0x100a4
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL                                           0x100a4
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL                                           0x100a5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL                                           0x100a5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL                                           0x100a6
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL                                           0x100a6
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST                                                    0x100a8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP                                                             0x100a9
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL                                                            0x100a9
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST                                                    0x100ac
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP                                                             0x100ad
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL                                                            0x100ad
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST                                               0x100b0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL                                                       0x100b1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS                                                     0x100b1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY                                          0x100b2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC                                             0x100b3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST                                                  0x100b4
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP                                                           0x100b5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL                                                          0x100b5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST                                                     0x100bc
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP                                                              0x100bd
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL                                                             0x100bd
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0                                                            0x100be
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1                                                            0x100bf
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0                                                             0x100c0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1                                                             0x100c1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0                                                       0x100c2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1                                                       0x100c3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                             0x100c4
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                             0x100c5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST                                                    0x100c8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP                                                             0x100c9
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST                                                    0x100ca
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP                                                             0x100cb
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL                                                            0x100cb
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST                                                  0x100cc
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP                                                           0x100cd
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL                                                       0x100ce
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS                                                        0x100ce
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS                                                   0x100cf
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS                                                     0x100cf
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS                                                       0x100d0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK                                                 0x100d0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET                                               0x100d1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE                                                     0x100d1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID                                                  0x100d2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                           0x100d3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                              0x100d4
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0                                                0x100d5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1                                                0x100d6
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2                                                0x100d7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3                                                0x100d8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4                                                0x100d9
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5                                                0x100da
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                               0x100db
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x100dc
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP                                                        0x100dd
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL                                                       0x100de
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST                                                    0x10100
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP                                                    0x10101
+#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS                                                 0x10102
+#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST                                               0x10104
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT                                                            0x10105
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT                                                           0x10106
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT                                                         0x10107
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0x10108
+#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0x10109
+#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0x1010a
+#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT                                            0x1010c
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT                                            0x1010c
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT                                            0x1010c
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT                                            0x1010c
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT                                            0x1010d
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT                                            0x1010d
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT                                            0x1010d
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT                                            0x1010d
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT                                            0x1010e
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT                                            0x1010e
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT                                           0x1010e
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT                                           0x1010e
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT                                           0x1010f
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT                                           0x1010f
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT                                           0x1010f
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT                                           0x1010f
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST                                              0x10110
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP                                                       0x10111
+#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS                                                    0x10111
+#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL                                               0x10112
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS                                             0x10112
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL                                               0x10113
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS                                             0x10113
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL                                               0x10114
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS                                             0x10114
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL                                               0x10115
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS                                             0x10115
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL                                               0x10116
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS                                             0x10116
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL                                               0x10117
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS                                             0x10117
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL                                               0x10118
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS                                             0x10118
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL                                               0x10119
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS                                             0x10119
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL                                               0x1011a
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS                                             0x1011a
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL                                               0x1011b
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS                                             0x1011b
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL                                              0x1011c
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS                                            0x1011c
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL                                              0x1011d
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS                                            0x1011d
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL                                              0x1011e
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS                                            0x1011e
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL                                              0x1011f
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS                                            0x1011f
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL                                              0x10120
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS                                            0x10120
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL                                              0x10121
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS                                            0x10121
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                          0x10130
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP                                                  0x10131
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL                                                 0x10132
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP                                                  0x10133
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL                                                 0x10134
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP                                                  0x10135
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL                                                 0x10136
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP                                                  0x10137
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL                                                 0x10138
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP                                                  0x10139
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL                                                 0x1013a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP                                                  0x1013b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL                                                 0x1013c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                 0x10140
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                          0x10141
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                             0x10142
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_BASE_IDX                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                              0x10143
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                              0x10144
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                            0x10145
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                            0x10146
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                            0x10147
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                            0x10148
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                                  0x10149
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                 0x1014a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                                  0x1014b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                   0x1014c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                     0x1014d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                   0x1014e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                   0x1014f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                   0x10150
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                   0x10151
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                   0x10152
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                   0x10153
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                   0x10154
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                   0x10155
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                   0x10156
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                   0x10157
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                                  0x10158
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                                  0x10159
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                                  0x1015a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                                  0x1015b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                                  0x1015c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                                  0x1015d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB                                  0x1015e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB                                  0x1015f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB                                  0x10160
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB                                  0x10161
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB                                  0x10162
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB                                  0x10163
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB                                  0x10164
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB                                  0x10165
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB                                  0x10166
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB                                  0x10167
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB                                  0x10168
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB                                  0x10169
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB                                  0x1016a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB                                  0x1016b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB                                  0x1016c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0                               0x10170
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1                               0x10171
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2                               0x10172
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3                               0x10173
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4                               0x10174
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5                               0x10175
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6                               0x10176
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7                               0x10177
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8                               0x10178
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0                               0x1017c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1                               0x1017d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2                               0x1017e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3                               0x1017f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4                               0x10180
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5                               0x10181
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6                               0x10182
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7                               0x10183
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8                               0x10184
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0                               0x10188
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1                               0x10189
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2                               0x1018a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3                               0x1018b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4                               0x1018c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5                               0x1018d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6                               0x1018e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7                               0x1018f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8                               0x10190
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0                              0x10194
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1                              0x10195
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2                              0x10196
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3                              0x10197
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4                              0x10198
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5                              0x10199
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6                              0x1019a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7                              0x1019b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8                              0x1019c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_BASE_IDX                     5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+// base address: 0x10141000
+#define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID                                                                0x10400
+#define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID                                                                0x10400
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_0_COMMAND                                                                  0x10401
+#define regBIF_CFG_DEV0_EPF1_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_0_STATUS                                                                   0x10401
+#define regBIF_CFG_DEV0_EPF1_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF1_0_REVISION_ID                                                              0x10402
+#define regBIF_CFG_DEV0_EPF1_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE                                                           0x10402
+#define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS                                                                0x10402
+#define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS                                                               0x10402
+#define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE                                                               0x10403
+#define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LATENCY                                                                  0x10403
+#define regBIF_CFG_DEV0_EPF1_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_0_HEADER                                                                   0x10403
+#define regBIF_CFG_DEV0_EPF1_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF1_0_BIST                                                                     0x10403
+#define regBIF_CFG_DEV0_EPF1_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1                                                              0x10404
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2                                                              0x10405
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3                                                              0x10406
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4                                                              0x10407
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5                                                              0x10408
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6                                                              0x10409
+#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR                                                          0x1040a
+#define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID                                                               0x1040b
+#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR                                                            0x1040c
+#define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_CAP_PTR                                                                  0x1040d
+#define regBIF_CFG_DEV0_EPF1_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE                                                           0x1040f
+#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN                                                            0x1040f
+#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT                                                                0x1040f
+#define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY                                                              0x1040f
+#define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST                                                          0x10412
+#define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W                                                             0x10413
+#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST                                                             0x10414
+#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP                                                                  0x10414
+#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL                                                          0x10415
+#define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST                                                            0x10419
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP                                                                 0x10419
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP                                                               0x1041a
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL                                                              0x1041b
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS                                                            0x1041b
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP                                                                 0x1041c
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL                                                                0x1041d
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS                                                              0x1041d
+#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2                                                              0x10422
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2                                                             0x10423
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2                                                           0x10423
+#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2                                                                0x10424
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2                                                               0x10425
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2                                                             0x10425
+#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST                                                             0x10428
+#define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL                                                             0x10428
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO                                                          0x10429
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI                                                          0x1042a
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA                                                             0x1042a
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA                                                         0x1042a
+#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK                                                                 0x1042b
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64                                                          0x1042b
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64                                                      0x1042b
+#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64                                                              0x1042c
+#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING                                                              0x1042c
+#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64                                                           0x1042d
+#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST                                                            0x10430
+#define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL                                                            0x10430
+#define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE                                                               0x10431
+#define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA                                                                 0x10432
+#define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x10440
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x10441
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1                                                    0x10442
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2                                                    0x10443
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST                                                     0x10444
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1                                                    0x10445
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2                                                    0x10446
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL                                                        0x10447
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS                                                      0x10447
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP                                                    0x10448
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL                                                   0x10449
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS                                                 0x1044a
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP                                                    0x1044b
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL                                                   0x1044c
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS                                                 0x1044d
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                         0x10450
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1                                                  0x10451
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2                                                  0x10452
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x10454
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS                                                   0x10455
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK                                                     0x10456
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x10457
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS                                                     0x10458
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK                                                       0x10459
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x1045a
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0                                                            0x1045b
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1                                                            0x1045c
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2                                                            0x1045d
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3                                                            0x1045e
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0                                                     0x10462
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1                                                     0x10463
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2                                                     0x10464
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3                                                     0x10465
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST                                                    0x10480
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP                                                            0x10481
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL                                                           0x10482
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP                                                            0x10483
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL                                                           0x10484
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP                                                            0x10485
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL                                                           0x10486
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP                                                            0x10487
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL                                                           0x10488
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP                                                            0x10489
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL                                                           0x1048a
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP                                                            0x1048b
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL                                                           0x1048c
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x10490
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x10491
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA                                                     0x10492
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP                                                      0x10493
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST                                                    0x10494
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP                                                             0x10495
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR                                               0x10496
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS                                                          0x10497
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL                                                            0x10497
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x10498
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x10498
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x10498
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x10498
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x10499
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x10499
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x10499
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x10499
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST                                              0x1049c
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3                                                          0x1049d
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS                                                   0x1049e
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL                                            0x1049f
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL                                            0x1049f
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL                                            0x104a0
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL                                            0x104a0
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL                                            0x104a1
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL                                            0x104a1
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL                                            0x104a2
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL                                            0x104a2
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL                                            0x104a3
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL                                            0x104a3
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL                                           0x104a4
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL                                           0x104a4
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL                                           0x104a5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL                                           0x104a5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL                                           0x104a6
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL                                           0x104a6
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST                                                    0x104a8
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP                                                             0x104a9
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL                                                            0x104a9
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST                                                    0x104ac
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP                                                             0x104ad
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL                                                            0x104ad
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST                                               0x104b0
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL                                                       0x104b1
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS                                                     0x104b1
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY                                          0x104b2
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC                                             0x104b3
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST                                                  0x104b4
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP                                                           0x104b5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL                                                          0x104b5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST                                                     0x104bc
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP                                                              0x104bd
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL                                                             0x104bd
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0                                                            0x104be
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1                                                            0x104bf
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0                                                             0x104c0
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1                                                             0x104c1
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0                                                       0x104c2
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1                                                       0x104c3
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                             0x104c4
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                             0x104c5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST                                                    0x104c8
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP                                                             0x104c9
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST                                                    0x104ca
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP                                                             0x104cb
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL                                                            0x104cb
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST                                                  0x104cc
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP                                                           0x104cd
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL                                                       0x104ce
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS                                                        0x104ce
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS                                                   0x104cf
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS                                                     0x104cf
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS                                                       0x104d0
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK                                                 0x104d0
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET                                               0x104d1
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE                                                     0x104d1
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID                                                  0x104d2
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                           0x104d3
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                              0x104d4
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0                                                0x104d5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1                                                0x104d6
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2                                                0x104d7
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3                                                0x104d8
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4                                                0x104d9
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5                                                0x104da
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                               0x104db
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x104dc
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP                                                        0x104dd
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL                                                       0x104de
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST                                                    0x10500
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP                                                    0x10501
+#define regBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS                                                 0x10502
+#define regBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST                                               0x10504
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT                                                            0x10505
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT                                                           0x10506
+#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT                                                         0x10507
+#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0x10508
+#define regBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0x10509
+#define regBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0x1050a
+#define regBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT                                            0x1050c
+#define regBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT                                            0x1050c
+#define regBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT                                            0x1050c
+#define regBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT                                            0x1050c
+#define regBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT                                            0x1050d
+#define regBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT                                            0x1050d
+#define regBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT                                            0x1050d
+#define regBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT                                            0x1050d
+#define regBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT                                            0x1050e
+#define regBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT                                            0x1050e
+#define regBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT                                           0x1050e
+#define regBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT                                           0x1050e
+#define regBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT                                           0x1050f
+#define regBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT                                           0x1050f
+#define regBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT                                           0x1050f
+#define regBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT                                           0x1050f
+#define regBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST                                              0x10510
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP                                                       0x10511
+#define regBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS                                                    0x10511
+#define regBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL                                               0x10512
+#define regBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS                                             0x10512
+#define regBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL                                               0x10513
+#define regBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS                                             0x10513
+#define regBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL                                               0x10514
+#define regBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS                                             0x10514
+#define regBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL                                               0x10515
+#define regBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS                                             0x10515
+#define regBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL                                               0x10516
+#define regBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS                                             0x10516
+#define regBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL                                               0x10517
+#define regBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS                                             0x10517
+#define regBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL                                               0x10518
+#define regBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS                                             0x10518
+#define regBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL                                               0x10519
+#define regBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS                                             0x10519
+#define regBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL                                               0x1051a
+#define regBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS                                             0x1051a
+#define regBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL                                               0x1051b
+#define regBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS                                             0x1051b
+#define regBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL                                              0x1051c
+#define regBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS                                            0x1051c
+#define regBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL                                              0x1051d
+#define regBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS                                            0x1051d
+#define regBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL                                              0x1051e
+#define regBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS                                            0x1051e
+#define regBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL                                              0x1051f
+#define regBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS                                            0x1051f
+#define regBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL                                              0x10520
+#define regBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS                                            0x10520
+#define regBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL                                              0x10521
+#define regBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS                                            0x10521
+#define regBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                          0x10530
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP                                                  0x10531
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL                                                 0x10532
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP                                                  0x10533
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL                                                 0x10534
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP                                                  0x10535
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL                                                 0x10536
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP                                                  0x10537
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL                                                 0x10538
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP                                                  0x10539
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL                                                 0x1053a
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP                                                  0x1053b
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL                                                 0x1053c
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                 0x10540
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                          0x10541
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                             0x10542
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_BASE_IDX                    5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                              0x10543
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                              0x10544
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                            0x10545
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                            0x10546
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                            0x10547
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                            0x10548
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                                  0x10549
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                 0x1054a
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                                  0x1054b
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                   0x1054c
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                     0x1054d
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX            5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                   0x1054e
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                   0x1054f
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                   0x10550
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                   0x10551
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                   0x10552
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                   0x10553
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                   0x10554
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                   0x10555
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                   0x10556
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                   0x10557
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                                  0x10558
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                                  0x10559
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                                  0x1055a
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                                  0x1055b
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                                  0x1055c
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                                  0x1055d
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB                                  0x1055e
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB                                  0x1055f
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB                                  0x10560
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB                                  0x10561
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB                                  0x10562
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB                                  0x10563
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB                                  0x10564
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB                                  0x10565
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB                                  0x10566
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB                                  0x10567
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB                                  0x10568
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB                                  0x10569
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB                                  0x1056a
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB                                  0x1056b
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB                                  0x1056c
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0                               0x10570
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1                               0x10571
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2                               0x10572
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3                               0x10573
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4                               0x10574
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5                               0x10575
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6                               0x10576
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7                               0x10577
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8                               0x10578
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0                               0x1057c
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1                               0x1057d
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2                               0x1057e
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3                               0x1057f
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4                               0x10580
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5                               0x10581
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6                               0x10582
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7                               0x10583
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8                               0x10584
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0                               0x10588
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1                               0x10589
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2                               0x1058a
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3                               0x1058b
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4                               0x1058c
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5                               0x1058d
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6                               0x1058e
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7                               0x1058f
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8                               0x10590
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0                              0x10594
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1                              0x10595
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2                              0x10596
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3                              0x10597
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4                              0x10598
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5                              0x10599
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6                              0x1059a
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7                              0x1059b
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8                              0x1059c
+#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_BASE_IDX                     5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+// base address: 0x10142000
+#define regBIF_CFG_DEV0_EPF2_0_VENDOR_ID                                                                0x10800
+#define regBIF_CFG_DEV0_EPF2_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_ID                                                                0x10800
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_0_COMMAND                                                                  0x10801
+#define regBIF_CFG_DEV0_EPF2_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF2_0_STATUS                                                                   0x10801
+#define regBIF_CFG_DEV0_EPF2_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF2_0_REVISION_ID                                                              0x10802
+#define regBIF_CFG_DEV0_EPF2_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE                                                           0x10802
+#define regBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_0_SUB_CLASS                                                                0x10802
+#define regBIF_CFG_DEV0_EPF2_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_0_BASE_CLASS                                                               0x10802
+#define regBIF_CFG_DEV0_EPF2_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_0_CACHE_LINE                                                               0x10803
+#define regBIF_CFG_DEV0_EPF2_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_0_LATENCY                                                                  0x10803
+#define regBIF_CFG_DEV0_EPF2_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF2_0_HEADER                                                                   0x10803
+#define regBIF_CFG_DEV0_EPF2_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF2_0_BIST                                                                     0x10803
+#define regBIF_CFG_DEV0_EPF2_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1                                                              0x10804
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2                                                              0x10805
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3                                                              0x10806
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4                                                              0x10807
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5                                                              0x10808
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6                                                              0x10809
+#define regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR                                                          0x1080a
+#define regBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_0_ADAPTER_ID                                                               0x1080b
+#define regBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR                                                            0x1080c
+#define regBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_CAP_PTR                                                                  0x1080d
+#define regBIF_CFG_DEV0_EPF2_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE                                                           0x1080f
+#define regBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN                                                            0x1080f
+#define regBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_MIN_GRANT                                                                0x1080f
+#define regBIF_CFG_DEV0_EPF2_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_0_MAX_LATENCY                                                              0x1080f
+#define regBIF_CFG_DEV0_EPF2_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST                                                          0x10812
+#define regBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W                                                             0x10813
+#define regBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST                                                             0x10814
+#define regBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_0_PMI_CAP                                                                  0x10814
+#define regBIF_CFG_DEV0_EPF2_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL                                                          0x10815
+#define regBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_0_SBRN                                                                     0x10818
+#define regBIF_CFG_DEV0_EPF2_0_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF2_0_FLADJ                                                                    0x10818
+#define regBIF_CFG_DEV0_EPF2_0_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD                                                             0x10818
+#define regBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST                                                            0x10819
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_CAP                                                                 0x10819
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_CAP                                                               0x1081a
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL                                                              0x1081b
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS                                                            0x1081b
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_LINK_CAP                                                                 0x1081c
+#define regBIF_CFG_DEV0_EPF2_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF2_0_LINK_CNTL                                                                0x1081d
+#define regBIF_CFG_DEV0_EPF2_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_0_LINK_STATUS                                                              0x1081d
+#define regBIF_CFG_DEV0_EPF2_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2                                                              0x10822
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2                                                             0x10823
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2                                                           0x10823
+#define regBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_0_LINK_CAP2                                                                0x10824
+#define regBIF_CFG_DEV0_EPF2_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_0_LINK_CNTL2                                                               0x10825
+#define regBIF_CFG_DEV0_EPF2_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_0_LINK_STATUS2                                                             0x10825
+#define regBIF_CFG_DEV0_EPF2_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST                                                             0x10828
+#define regBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL                                                             0x10828
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO                                                          0x10829
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI                                                          0x1082a
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA                                                             0x1082a
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA                                                         0x1082a
+#define regBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MASK                                                                 0x1082b
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64                                                          0x1082b
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64                                                      0x1082b
+#define regBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MASK_64                                                              0x1082c
+#define regBIF_CFG_DEV0_EPF2_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_PENDING                                                              0x1082c
+#define regBIF_CFG_DEV0_EPF2_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64                                                           0x1082d
+#define regBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST                                                            0x10830
+#define regBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL                                                            0x10830
+#define regBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_MSIX_TABLE                                                               0x10831
+#define regBIF_CFG_DEV0_EPF2_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_0_MSIX_PBA                                                                 0x10832
+#define regBIF_CFG_DEV0_EPF2_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x10840
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x10841
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1                                                    0x10842
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2                                                    0x10843
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x10854
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS                                                   0x10855
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK                                                     0x10856
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x10857
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS                                                     0x10858
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK                                                       0x10859
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x1085a
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0                                                            0x1085b
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1                                                            0x1085c
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2                                                            0x1085d
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3                                                            0x1085e
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0                                                     0x10862
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1                                                     0x10863
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2                                                     0x10864
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3                                                     0x10865
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST                                                    0x10880
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP                                                            0x10881
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL                                                           0x10882
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP                                                            0x10883
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL                                                           0x10884
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP                                                            0x10885
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL                                                           0x10886
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP                                                            0x10887
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL                                                           0x10888
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP                                                            0x10889
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL                                                           0x1088a
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP                                                            0x1088b
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL                                                           0x1088c
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x10890
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x10891
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA                                                     0x10892
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP                                                      0x10893
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST                                                    0x10894
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP                                                             0x10895
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR                                               0x10896
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS                                                          0x10897
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL                                                            0x10897
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x10898
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x10898
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x10898
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x10898
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x10899
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x10899
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x10899
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x10899
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST                                                    0x108a8
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP                                                             0x108a9
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL                                                            0x108a9
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST                                                  0x108b4
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP                                                           0x108b5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL                                                          0x108b5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST                                                    0x108ca
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP                                                             0x108cb
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL                                                            0x108cb
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x108dc
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP                                                        0x108dd
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL                                                       0x108de
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0                                                      0x108df
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1                                                      0x108df
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2                                                      0x108e0
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3                                                      0x108e0
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4                                                      0x108e1
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5                                                      0x108e1
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6                                                      0x108e2
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7                                                      0x108e2
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8                                                      0x108e3
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9                                                      0x108e3
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10                                                     0x108e4
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11                                                     0x108e4
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12                                                     0x108e5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13                                                     0x108e5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14                                                     0x108e6
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15                                                     0x108e6
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16                                                     0x108e7
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17                                                     0x108e7
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18                                                     0x108e8
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19                                                     0x108e8
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20                                                     0x108e9
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21                                                     0x108e9
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22                                                     0x108ea
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23                                                     0x108ea
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24                                                     0x108eb
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25                                                     0x108eb
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26                                                     0x108ec
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27                                                     0x108ec
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28                                                     0x108ed
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29                                                     0x108ed
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30                                                     0x108ee
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31                                                     0x108ee
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32                                                     0x108ef
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33                                                     0x108ef
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34                                                     0x108f0
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35                                                     0x108f0
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36                                                     0x108f1
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37                                                     0x108f1
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38                                                     0x108f2
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39                                                     0x108f2
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40                                                     0x108f3
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41                                                     0x108f3
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42                                                     0x108f4
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43                                                     0x108f4
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44                                                     0x108f5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45                                                     0x108f5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46                                                     0x108f6
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47                                                     0x108f6
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48                                                     0x108f7
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49                                                     0x108f7
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50                                                     0x108f8
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51                                                     0x108f8
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52                                                     0x108f9
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53                                                     0x108f9
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54                                                     0x108fa
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55                                                     0x108fa
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56                                                     0x108fb
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57                                                     0x108fb
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58                                                     0x108fc
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59                                                     0x108fc
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60                                                     0x108fd
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61                                                     0x108fd
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62                                                     0x108fe
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63                                                     0x108fe
+#define regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+// base address: 0x10143000
+#define regBIF_CFG_DEV0_EPF3_0_VENDOR_ID                                                                0x10c00
+#define regBIF_CFG_DEV0_EPF3_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_ID                                                                0x10c00
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_0_COMMAND                                                                  0x10c01
+#define regBIF_CFG_DEV0_EPF3_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF3_0_STATUS                                                                   0x10c01
+#define regBIF_CFG_DEV0_EPF3_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF3_0_REVISION_ID                                                              0x10c02
+#define regBIF_CFG_DEV0_EPF3_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE                                                           0x10c02
+#define regBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_0_SUB_CLASS                                                                0x10c02
+#define regBIF_CFG_DEV0_EPF3_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_0_BASE_CLASS                                                               0x10c02
+#define regBIF_CFG_DEV0_EPF3_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_0_CACHE_LINE                                                               0x10c03
+#define regBIF_CFG_DEV0_EPF3_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_0_LATENCY                                                                  0x10c03
+#define regBIF_CFG_DEV0_EPF3_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF3_0_HEADER                                                                   0x10c03
+#define regBIF_CFG_DEV0_EPF3_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF3_0_BIST                                                                     0x10c03
+#define regBIF_CFG_DEV0_EPF3_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1                                                              0x10c04
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2                                                              0x10c05
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3                                                              0x10c06
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4                                                              0x10c07
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5                                                              0x10c08
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6                                                              0x10c09
+#define regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR                                                          0x10c0a
+#define regBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_0_ADAPTER_ID                                                               0x10c0b
+#define regBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR                                                            0x10c0c
+#define regBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_CAP_PTR                                                                  0x10c0d
+#define regBIF_CFG_DEV0_EPF3_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE                                                           0x10c0f
+#define regBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN                                                            0x10c0f
+#define regBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_MIN_GRANT                                                                0x10c0f
+#define regBIF_CFG_DEV0_EPF3_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_0_MAX_LATENCY                                                              0x10c0f
+#define regBIF_CFG_DEV0_EPF3_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST                                                          0x10c12
+#define regBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W                                                             0x10c13
+#define regBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST                                                             0x10c14
+#define regBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_0_PMI_CAP                                                                  0x10c14
+#define regBIF_CFG_DEV0_EPF3_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL                                                          0x10c15
+#define regBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_0_SBRN                                                                     0x10c18
+#define regBIF_CFG_DEV0_EPF3_0_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF3_0_FLADJ                                                                    0x10c18
+#define regBIF_CFG_DEV0_EPF3_0_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD                                                             0x10c18
+#define regBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST                                                            0x10c19
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_CAP                                                                 0x10c19
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_CAP                                                               0x10c1a
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL                                                              0x10c1b
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS                                                            0x10c1b
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_LINK_CAP                                                                 0x10c1c
+#define regBIF_CFG_DEV0_EPF3_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF3_0_LINK_CNTL                                                                0x10c1d
+#define regBIF_CFG_DEV0_EPF3_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_0_LINK_STATUS                                                              0x10c1d
+#define regBIF_CFG_DEV0_EPF3_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2                                                              0x10c22
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2                                                             0x10c23
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2                                                           0x10c23
+#define regBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_0_LINK_CAP2                                                                0x10c24
+#define regBIF_CFG_DEV0_EPF3_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_0_LINK_CNTL2                                                               0x10c25
+#define regBIF_CFG_DEV0_EPF3_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_0_LINK_STATUS2                                                             0x10c25
+#define regBIF_CFG_DEV0_EPF3_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST                                                             0x10c28
+#define regBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL                                                             0x10c28
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO                                                          0x10c29
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI                                                          0x10c2a
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA                                                             0x10c2a
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA                                                         0x10c2a
+#define regBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MASK                                                                 0x10c2b
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64                                                          0x10c2b
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64                                                      0x10c2b
+#define regBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MASK_64                                                              0x10c2c
+#define regBIF_CFG_DEV0_EPF3_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_PENDING                                                              0x10c2c
+#define regBIF_CFG_DEV0_EPF3_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64                                                           0x10c2d
+#define regBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST                                                            0x10c30
+#define regBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL                                                            0x10c30
+#define regBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_MSIX_TABLE                                                               0x10c31
+#define regBIF_CFG_DEV0_EPF3_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_0_MSIX_PBA                                                                 0x10c32
+#define regBIF_CFG_DEV0_EPF3_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x10c40
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x10c41
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1                                                    0x10c42
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2                                                    0x10c43
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x10c54
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS                                                   0x10c55
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK                                                     0x10c56
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x10c57
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS                                                     0x10c58
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK                                                       0x10c59
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x10c5a
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0                                                            0x10c5b
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1                                                            0x10c5c
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2                                                            0x10c5d
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3                                                            0x10c5e
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0                                                     0x10c62
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1                                                     0x10c63
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2                                                     0x10c64
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3                                                     0x10c65
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST                                                    0x10c80
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP                                                            0x10c81
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL                                                           0x10c82
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP                                                            0x10c83
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL                                                           0x10c84
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP                                                            0x10c85
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL                                                           0x10c86
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP                                                            0x10c87
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL                                                           0x10c88
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP                                                            0x10c89
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL                                                           0x10c8a
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP                                                            0x10c8b
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL                                                           0x10c8c
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x10c90
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x10c91
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA                                                     0x10c92
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP                                                      0x10c93
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST                                                    0x10c94
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP                                                             0x10c95
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR                                               0x10c96
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS                                                          0x10c97
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL                                                            0x10c97
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x10c98
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x10c98
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x10c98
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x10c98
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x10c99
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x10c99
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x10c99
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x10c99
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST                                                    0x10ca8
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP                                                             0x10ca9
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL                                                            0x10ca9
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST                                                  0x10cb4
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP                                                           0x10cb5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL                                                          0x10cb5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST                                                    0x10cca
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP                                                             0x10ccb
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL                                                            0x10ccb
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x10cdc
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP                                                        0x10cdd
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL                                                       0x10cde
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0                                                      0x10cdf
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1                                                      0x10cdf
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2                                                      0x10ce0
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3                                                      0x10ce0
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4                                                      0x10ce1
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5                                                      0x10ce1
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6                                                      0x10ce2
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7                                                      0x10ce2
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8                                                      0x10ce3
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9                                                      0x10ce3
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10                                                     0x10ce4
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11                                                     0x10ce4
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12                                                     0x10ce5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13                                                     0x10ce5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14                                                     0x10ce6
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15                                                     0x10ce6
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16                                                     0x10ce7
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17                                                     0x10ce7
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18                                                     0x10ce8
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19                                                     0x10ce8
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20                                                     0x10ce9
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21                                                     0x10ce9
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22                                                     0x10cea
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23                                                     0x10cea
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24                                                     0x10ceb
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25                                                     0x10ceb
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26                                                     0x10cec
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27                                                     0x10cec
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28                                                     0x10ced
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29                                                     0x10ced
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30                                                     0x10cee
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31                                                     0x10cee
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32                                                     0x10cef
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33                                                     0x10cef
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34                                                     0x10cf0
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35                                                     0x10cf0
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36                                                     0x10cf1
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37                                                     0x10cf1
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38                                                     0x10cf2
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39                                                     0x10cf2
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40                                                     0x10cf3
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41                                                     0x10cf3
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42                                                     0x10cf4
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43                                                     0x10cf4
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44                                                     0x10cf5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45                                                     0x10cf5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46                                                     0x10cf6
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47                                                     0x10cf6
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48                                                     0x10cf7
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49                                                     0x10cf7
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50                                                     0x10cf8
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51                                                     0x10cf8
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52                                                     0x10cf9
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53                                                     0x10cf9
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54                                                     0x10cfa
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55                                                     0x10cfa
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56                                                     0x10cfb
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57                                                     0x10cfb
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58                                                     0x10cfc
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59                                                     0x10cfc
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60                                                     0x10cfd
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61                                                     0x10cfd
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62                                                     0x10cfe
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63                                                     0x10cfe
+#define regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+// base address: 0x10144000
+#define regBIF_CFG_DEV0_EPF4_0_VENDOR_ID                                                                0x11000
+#define regBIF_CFG_DEV0_EPF4_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_ID                                                                0x11000
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_0_COMMAND                                                                  0x11001
+#define regBIF_CFG_DEV0_EPF4_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF4_0_STATUS                                                                   0x11001
+#define regBIF_CFG_DEV0_EPF4_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF4_0_REVISION_ID                                                              0x11002
+#define regBIF_CFG_DEV0_EPF4_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_PROG_INTERFACE                                                           0x11002
+#define regBIF_CFG_DEV0_EPF4_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_0_SUB_CLASS                                                                0x11002
+#define regBIF_CFG_DEV0_EPF4_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_0_BASE_CLASS                                                               0x11002
+#define regBIF_CFG_DEV0_EPF4_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_0_CACHE_LINE                                                               0x11003
+#define regBIF_CFG_DEV0_EPF4_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_0_LATENCY                                                                  0x11003
+#define regBIF_CFG_DEV0_EPF4_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF4_0_HEADER                                                                   0x11003
+#define regBIF_CFG_DEV0_EPF4_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF4_0_BIST                                                                     0x11003
+#define regBIF_CFG_DEV0_EPF4_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_1                                                              0x11004
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_2                                                              0x11005
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_3                                                              0x11006
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_4                                                              0x11007
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_5                                                              0x11008
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_6                                                              0x11009
+#define regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_CARDBUS_CIS_PTR                                                          0x1100a
+#define regBIF_CFG_DEV0_EPF4_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_0_ADAPTER_ID                                                               0x1100b
+#define regBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR                                                            0x1100c
+#define regBIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_CAP_PTR                                                                  0x1100d
+#define regBIF_CFG_DEV0_EPF4_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE                                                           0x1100f
+#define regBIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN                                                            0x1100f
+#define regBIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_MIN_GRANT                                                                0x1100f
+#define regBIF_CFG_DEV0_EPF4_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_0_MAX_LATENCY                                                              0x1100f
+#define regBIF_CFG_DEV0_EPF4_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST                                                          0x11012
+#define regBIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W                                                             0x11013
+#define regBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST                                                             0x11014
+#define regBIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_0_PMI_CAP                                                                  0x11014
+#define regBIF_CFG_DEV0_EPF4_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL                                                          0x11015
+#define regBIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_0_SBRN                                                                     0x11018
+#define regBIF_CFG_DEV0_EPF4_0_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF4_0_FLADJ                                                                    0x11018
+#define regBIF_CFG_DEV0_EPF4_0_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF4_0_DBESL_DBESLD                                                             0x11018
+#define regBIF_CFG_DEV0_EPF4_0_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST                                                            0x11019
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_CAP                                                                 0x11019
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_CAP                                                               0x1101a
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL                                                              0x1101b
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS                                                            0x1101b
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_LINK_CAP                                                                 0x1101c
+#define regBIF_CFG_DEV0_EPF4_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF4_0_LINK_CNTL                                                                0x1101d
+#define regBIF_CFG_DEV0_EPF4_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_0_LINK_STATUS                                                              0x1101d
+#define regBIF_CFG_DEV0_EPF4_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_CAP2                                                              0x11022
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2                                                             0x11023
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2                                                           0x11023
+#define regBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_0_LINK_CAP2                                                                0x11024
+#define regBIF_CFG_DEV0_EPF4_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_0_LINK_CNTL2                                                               0x11025
+#define regBIF_CFG_DEV0_EPF4_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_0_LINK_STATUS2                                                             0x11025
+#define regBIF_CFG_DEV0_EPF4_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST                                                             0x11028
+#define regBIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL                                                             0x11028
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO                                                          0x11029
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI                                                          0x1102a
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA                                                             0x1102a
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA                                                         0x1102a
+#define regBIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MASK                                                                 0x1102b
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64                                                          0x1102b
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64                                                      0x1102b
+#define regBIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MASK_64                                                              0x1102c
+#define regBIF_CFG_DEV0_EPF4_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_PENDING                                                              0x1102c
+#define regBIF_CFG_DEV0_EPF4_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_0_MSI_PENDING_64                                                           0x1102d
+#define regBIF_CFG_DEV0_EPF4_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST                                                            0x11030
+#define regBIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL                                                            0x11030
+#define regBIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_MSIX_TABLE                                                               0x11031
+#define regBIF_CFG_DEV0_EPF4_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_0_MSIX_PBA                                                                 0x11032
+#define regBIF_CFG_DEV0_EPF4_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x11040
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x11041
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1                                                    0x11042
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2                                                    0x11043
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x11054
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS                                                   0x11055
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK                                                     0x11056
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x11057
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS                                                     0x11058
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK                                                       0x11059
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x1105a
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0                                                            0x1105b
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1                                                            0x1105c
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2                                                            0x1105d
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3                                                            0x1105e
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0                                                     0x11062
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1                                                     0x11063
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2                                                     0x11064
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3                                                     0x11065
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST                                                    0x11080
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP                                                            0x11081
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL                                                           0x11082
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP                                                            0x11083
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL                                                           0x11084
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP                                                            0x11085
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL                                                           0x11086
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP                                                            0x11087
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL                                                           0x11088
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP                                                            0x11089
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL                                                           0x1108a
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP                                                            0x1108b
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL                                                           0x1108c
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x11090
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x11091
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA                                                     0x11092
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP                                                      0x11093
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST                                                    0x11094
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP                                                             0x11095
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR                                               0x11096
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS                                                          0x11097
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL                                                            0x11097
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x11098
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x11098
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x11098
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x11098
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x11099
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x11099
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x11099
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x11099
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST                                                    0x110a8
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP                                                             0x110a9
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL                                                            0x110a9
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST                                                  0x110b4
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP                                                           0x110b5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL                                                          0x110b5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST                                                    0x110ca
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP                                                             0x110cb
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL                                                            0x110cb
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x110dc
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP                                                        0x110dd
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL                                                       0x110de
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0                                                      0x110df
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1                                                      0x110df
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2                                                      0x110e0
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3                                                      0x110e0
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4                                                      0x110e1
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5                                                      0x110e1
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6                                                      0x110e2
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7                                                      0x110e2
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8                                                      0x110e3
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9                                                      0x110e3
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10                                                     0x110e4
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11                                                     0x110e4
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12                                                     0x110e5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13                                                     0x110e5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14                                                     0x110e6
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15                                                     0x110e6
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16                                                     0x110e7
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17                                                     0x110e7
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18                                                     0x110e8
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19                                                     0x110e8
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20                                                     0x110e9
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21                                                     0x110e9
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22                                                     0x110ea
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23                                                     0x110ea
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24                                                     0x110eb
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25                                                     0x110eb
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26                                                     0x110ec
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27                                                     0x110ec
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28                                                     0x110ed
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29                                                     0x110ed
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30                                                     0x110ee
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31                                                     0x110ee
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32                                                     0x110ef
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33                                                     0x110ef
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34                                                     0x110f0
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35                                                     0x110f0
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36                                                     0x110f1
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37                                                     0x110f1
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38                                                     0x110f2
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39                                                     0x110f2
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40                                                     0x110f3
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41                                                     0x110f3
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42                                                     0x110f4
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43                                                     0x110f4
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44                                                     0x110f5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45                                                     0x110f5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46                                                     0x110f6
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47                                                     0x110f6
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48                                                     0x110f7
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49                                                     0x110f7
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50                                                     0x110f8
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51                                                     0x110f8
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52                                                     0x110f9
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53                                                     0x110f9
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54                                                     0x110fa
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55                                                     0x110fa
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56                                                     0x110fb
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57                                                     0x110fb
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58                                                     0x110fc
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59                                                     0x110fc
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60                                                     0x110fd
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61                                                     0x110fd
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62                                                     0x110fe
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63                                                     0x110fe
+#define regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+// base address: 0x10145000
+#define regBIF_CFG_DEV0_EPF5_0_VENDOR_ID                                                                0x11400
+#define regBIF_CFG_DEV0_EPF5_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_ID                                                                0x11400
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_0_COMMAND                                                                  0x11401
+#define regBIF_CFG_DEV0_EPF5_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF5_0_STATUS                                                                   0x11401
+#define regBIF_CFG_DEV0_EPF5_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF5_0_REVISION_ID                                                              0x11402
+#define regBIF_CFG_DEV0_EPF5_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_PROG_INTERFACE                                                           0x11402
+#define regBIF_CFG_DEV0_EPF5_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_0_SUB_CLASS                                                                0x11402
+#define regBIF_CFG_DEV0_EPF5_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_0_BASE_CLASS                                                               0x11402
+#define regBIF_CFG_DEV0_EPF5_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_0_CACHE_LINE                                                               0x11403
+#define regBIF_CFG_DEV0_EPF5_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_0_LATENCY                                                                  0x11403
+#define regBIF_CFG_DEV0_EPF5_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF5_0_HEADER                                                                   0x11403
+#define regBIF_CFG_DEV0_EPF5_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF5_0_BIST                                                                     0x11403
+#define regBIF_CFG_DEV0_EPF5_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_1                                                              0x11404
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_2                                                              0x11405
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_3                                                              0x11406
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_4                                                              0x11407
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_5                                                              0x11408
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_6                                                              0x11409
+#define regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_CARDBUS_CIS_PTR                                                          0x1140a
+#define regBIF_CFG_DEV0_EPF5_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_0_ADAPTER_ID                                                               0x1140b
+#define regBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR                                                            0x1140c
+#define regBIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_CAP_PTR                                                                  0x1140d
+#define regBIF_CFG_DEV0_EPF5_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE                                                           0x1140f
+#define regBIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN                                                            0x1140f
+#define regBIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_MIN_GRANT                                                                0x1140f
+#define regBIF_CFG_DEV0_EPF5_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_0_MAX_LATENCY                                                              0x1140f
+#define regBIF_CFG_DEV0_EPF5_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST                                                          0x11412
+#define regBIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W                                                             0x11413
+#define regBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST                                                             0x11414
+#define regBIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_0_PMI_CAP                                                                  0x11414
+#define regBIF_CFG_DEV0_EPF5_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL                                                          0x11415
+#define regBIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_0_SBRN                                                                     0x11418
+#define regBIF_CFG_DEV0_EPF5_0_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF5_0_FLADJ                                                                    0x11418
+#define regBIF_CFG_DEV0_EPF5_0_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF5_0_DBESL_DBESLD                                                             0x11418
+#define regBIF_CFG_DEV0_EPF5_0_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST                                                            0x11419
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_CAP                                                                 0x11419
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_CAP                                                               0x1141a
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL                                                              0x1141b
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS                                                            0x1141b
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_LINK_CAP                                                                 0x1141c
+#define regBIF_CFG_DEV0_EPF5_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF5_0_LINK_CNTL                                                                0x1141d
+#define regBIF_CFG_DEV0_EPF5_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_0_LINK_STATUS                                                              0x1141d
+#define regBIF_CFG_DEV0_EPF5_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_CAP2                                                              0x11422
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2                                                             0x11423
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2                                                           0x11423
+#define regBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_0_LINK_CAP2                                                                0x11424
+#define regBIF_CFG_DEV0_EPF5_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_0_LINK_CNTL2                                                               0x11425
+#define regBIF_CFG_DEV0_EPF5_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_0_LINK_STATUS2                                                             0x11425
+#define regBIF_CFG_DEV0_EPF5_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST                                                             0x11428
+#define regBIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL                                                             0x11428
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO                                                          0x11429
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI                                                          0x1142a
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA                                                             0x1142a
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA                                                         0x1142a
+#define regBIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MASK                                                                 0x1142b
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64                                                          0x1142b
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64                                                      0x1142b
+#define regBIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MASK_64                                                              0x1142c
+#define regBIF_CFG_DEV0_EPF5_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_PENDING                                                              0x1142c
+#define regBIF_CFG_DEV0_EPF5_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_0_MSI_PENDING_64                                                           0x1142d
+#define regBIF_CFG_DEV0_EPF5_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST                                                            0x11430
+#define regBIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL                                                            0x11430
+#define regBIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_MSIX_TABLE                                                               0x11431
+#define regBIF_CFG_DEV0_EPF5_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_0_MSIX_PBA                                                                 0x11432
+#define regBIF_CFG_DEV0_EPF5_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x11440
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x11441
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1                                                    0x11442
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2                                                    0x11443
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x11454
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS                                                   0x11455
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK                                                     0x11456
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x11457
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS                                                     0x11458
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK                                                       0x11459
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x1145a
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0                                                            0x1145b
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1                                                            0x1145c
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2                                                            0x1145d
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3                                                            0x1145e
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0                                                     0x11462
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1                                                     0x11463
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2                                                     0x11464
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3                                                     0x11465
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST                                                    0x11480
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP                                                            0x11481
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL                                                           0x11482
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP                                                            0x11483
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL                                                           0x11484
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP                                                            0x11485
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL                                                           0x11486
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP                                                            0x11487
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL                                                           0x11488
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP                                                            0x11489
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL                                                           0x1148a
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP                                                            0x1148b
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL                                                           0x1148c
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x11490
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x11491
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA                                                     0x11492
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP                                                      0x11493
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST                                                    0x11494
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP                                                             0x11495
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR                                               0x11496
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS                                                          0x11497
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL                                                            0x11497
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x11498
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x11498
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x11498
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x11498
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x11499
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x11499
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x11499
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x11499
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST                                                    0x114a8
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP                                                             0x114a9
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL                                                            0x114a9
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST                                                  0x114b4
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP                                                           0x114b5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL                                                          0x114b5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST                                                    0x114ca
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP                                                             0x114cb
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL                                                            0x114cb
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x114dc
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP                                                        0x114dd
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL                                                       0x114de
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0                                                      0x114df
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1                                                      0x114df
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2                                                      0x114e0
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3                                                      0x114e0
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4                                                      0x114e1
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5                                                      0x114e1
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6                                                      0x114e2
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7                                                      0x114e2
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8                                                      0x114e3
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9                                                      0x114e3
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10                                                     0x114e4
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11                                                     0x114e4
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12                                                     0x114e5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13                                                     0x114e5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14                                                     0x114e6
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15                                                     0x114e6
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16                                                     0x114e7
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17                                                     0x114e7
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18                                                     0x114e8
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19                                                     0x114e8
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20                                                     0x114e9
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21                                                     0x114e9
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22                                                     0x114ea
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23                                                     0x114ea
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24                                                     0x114eb
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25                                                     0x114eb
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26                                                     0x114ec
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27                                                     0x114ec
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28                                                     0x114ed
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29                                                     0x114ed
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30                                                     0x114ee
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31                                                     0x114ee
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32                                                     0x114ef
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33                                                     0x114ef
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34                                                     0x114f0
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35                                                     0x114f0
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36                                                     0x114f1
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37                                                     0x114f1
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38                                                     0x114f2
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39                                                     0x114f2
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40                                                     0x114f3
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41                                                     0x114f3
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42                                                     0x114f4
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43                                                     0x114f4
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44                                                     0x114f5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45                                                     0x114f5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46                                                     0x114f6
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47                                                     0x114f6
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48                                                     0x114f7
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49                                                     0x114f7
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50                                                     0x114f8
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51                                                     0x114f8
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52                                                     0x114f9
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53                                                     0x114f9
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54                                                     0x114fa
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55                                                     0x114fa
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56                                                     0x114fb
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57                                                     0x114fb
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58                                                     0x114fc
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59                                                     0x114fc
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60                                                     0x114fd
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61                                                     0x114fd
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62                                                     0x114fe
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63                                                     0x114fe
+#define regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+// base address: 0x10146000
+#define regBIF_CFG_DEV0_EPF6_0_VENDOR_ID                                                                0x11800
+#define regBIF_CFG_DEV0_EPF6_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_ID                                                                0x11800
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_0_COMMAND                                                                  0x11801
+#define regBIF_CFG_DEV0_EPF6_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF6_0_STATUS                                                                   0x11801
+#define regBIF_CFG_DEV0_EPF6_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF6_0_REVISION_ID                                                              0x11802
+#define regBIF_CFG_DEV0_EPF6_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_PROG_INTERFACE                                                           0x11802
+#define regBIF_CFG_DEV0_EPF6_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_0_SUB_CLASS                                                                0x11802
+#define regBIF_CFG_DEV0_EPF6_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_0_BASE_CLASS                                                               0x11802
+#define regBIF_CFG_DEV0_EPF6_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_0_CACHE_LINE                                                               0x11803
+#define regBIF_CFG_DEV0_EPF6_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_0_LATENCY                                                                  0x11803
+#define regBIF_CFG_DEV0_EPF6_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF6_0_HEADER                                                                   0x11803
+#define regBIF_CFG_DEV0_EPF6_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF6_0_BIST                                                                     0x11803
+#define regBIF_CFG_DEV0_EPF6_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_1                                                              0x11804
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_2                                                              0x11805
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_3                                                              0x11806
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_4                                                              0x11807
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_5                                                              0x11808
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_6                                                              0x11809
+#define regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_CARDBUS_CIS_PTR                                                          0x1180a
+#define regBIF_CFG_DEV0_EPF6_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_0_ADAPTER_ID                                                               0x1180b
+#define regBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR                                                            0x1180c
+#define regBIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_CAP_PTR                                                                  0x1180d
+#define regBIF_CFG_DEV0_EPF6_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE                                                           0x1180f
+#define regBIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN                                                            0x1180f
+#define regBIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_MIN_GRANT                                                                0x1180f
+#define regBIF_CFG_DEV0_EPF6_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_0_MAX_LATENCY                                                              0x1180f
+#define regBIF_CFG_DEV0_EPF6_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST                                                          0x11812
+#define regBIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W                                                             0x11813
+#define regBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST                                                             0x11814
+#define regBIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_0_PMI_CAP                                                                  0x11814
+#define regBIF_CFG_DEV0_EPF6_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL                                                          0x11815
+#define regBIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_0_SBRN                                                                     0x11818
+#define regBIF_CFG_DEV0_EPF6_0_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF6_0_FLADJ                                                                    0x11818
+#define regBIF_CFG_DEV0_EPF6_0_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF6_0_DBESL_DBESLD                                                             0x11818
+#define regBIF_CFG_DEV0_EPF6_0_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST                                                            0x11819
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_CAP                                                                 0x11819
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_CAP                                                               0x1181a
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL                                                              0x1181b
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS                                                            0x1181b
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_LINK_CAP                                                                 0x1181c
+#define regBIF_CFG_DEV0_EPF6_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF6_0_LINK_CNTL                                                                0x1181d
+#define regBIF_CFG_DEV0_EPF6_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_0_LINK_STATUS                                                              0x1181d
+#define regBIF_CFG_DEV0_EPF6_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_CAP2                                                              0x11822
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2                                                             0x11823
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2                                                           0x11823
+#define regBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_0_LINK_CAP2                                                                0x11824
+#define regBIF_CFG_DEV0_EPF6_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_0_LINK_CNTL2                                                               0x11825
+#define regBIF_CFG_DEV0_EPF6_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_0_LINK_STATUS2                                                             0x11825
+#define regBIF_CFG_DEV0_EPF6_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST                                                             0x11828
+#define regBIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL                                                             0x11828
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO                                                          0x11829
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI                                                          0x1182a
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA                                                             0x1182a
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA                                                         0x1182a
+#define regBIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MASK                                                                 0x1182b
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64                                                          0x1182b
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64                                                      0x1182b
+#define regBIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MASK_64                                                              0x1182c
+#define regBIF_CFG_DEV0_EPF6_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_PENDING                                                              0x1182c
+#define regBIF_CFG_DEV0_EPF6_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_0_MSI_PENDING_64                                                           0x1182d
+#define regBIF_CFG_DEV0_EPF6_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST                                                            0x11830
+#define regBIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL                                                            0x11830
+#define regBIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_MSIX_TABLE                                                               0x11831
+#define regBIF_CFG_DEV0_EPF6_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_0_MSIX_PBA                                                                 0x11832
+#define regBIF_CFG_DEV0_EPF6_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x11840
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x11841
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1                                                    0x11842
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2                                                    0x11843
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x11854
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS                                                   0x11855
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK                                                     0x11856
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x11857
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS                                                     0x11858
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK                                                       0x11859
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x1185a
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0                                                            0x1185b
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1                                                            0x1185c
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2                                                            0x1185d
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3                                                            0x1185e
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0                                                     0x11862
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1                                                     0x11863
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2                                                     0x11864
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3                                                     0x11865
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST                                                    0x11880
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP                                                            0x11881
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL                                                           0x11882
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP                                                            0x11883
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL                                                           0x11884
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP                                                            0x11885
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL                                                           0x11886
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP                                                            0x11887
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL                                                           0x11888
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP                                                            0x11889
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL                                                           0x1188a
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP                                                            0x1188b
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL                                                           0x1188c
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x11890
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x11891
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA                                                     0x11892
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP                                                      0x11893
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST                                                    0x11894
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP                                                             0x11895
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR                                               0x11896
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS                                                          0x11897
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL                                                            0x11897
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x11898
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x11898
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x11898
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x11898
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x11899
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x11899
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x11899
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x11899
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST                                                    0x118a8
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP                                                             0x118a9
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL                                                            0x118a9
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST                                                  0x118b4
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP                                                           0x118b5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL                                                          0x118b5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST                                                    0x118ca
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP                                                             0x118cb
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL                                                            0x118cb
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x118dc
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP                                                        0x118dd
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL                                                       0x118de
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0                                                      0x118df
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1                                                      0x118df
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2                                                      0x118e0
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3                                                      0x118e0
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4                                                      0x118e1
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5                                                      0x118e1
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6                                                      0x118e2
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7                                                      0x118e2
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8                                                      0x118e3
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9                                                      0x118e3
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10                                                     0x118e4
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11                                                     0x118e4
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12                                                     0x118e5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13                                                     0x118e5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14                                                     0x118e6
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15                                                     0x118e6
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16                                                     0x118e7
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17                                                     0x118e7
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18                                                     0x118e8
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19                                                     0x118e8
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20                                                     0x118e9
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21                                                     0x118e9
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22                                                     0x118ea
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23                                                     0x118ea
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24                                                     0x118eb
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25                                                     0x118eb
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26                                                     0x118ec
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27                                                     0x118ec
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28                                                     0x118ed
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29                                                     0x118ed
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30                                                     0x118ee
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31                                                     0x118ee
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32                                                     0x118ef
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33                                                     0x118ef
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34                                                     0x118f0
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35                                                     0x118f0
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36                                                     0x118f1
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37                                                     0x118f1
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38                                                     0x118f2
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39                                                     0x118f2
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40                                                     0x118f3
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41                                                     0x118f3
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42                                                     0x118f4
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43                                                     0x118f4
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44                                                     0x118f5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45                                                     0x118f5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46                                                     0x118f6
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47                                                     0x118f6
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48                                                     0x118f7
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49                                                     0x118f7
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50                                                     0x118f8
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51                                                     0x118f8
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52                                                     0x118f9
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53                                                     0x118f9
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54                                                     0x118fa
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55                                                     0x118fa
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56                                                     0x118fb
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57                                                     0x118fb
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58                                                     0x118fc
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59                                                     0x118fc
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60                                                     0x118fd
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61                                                     0x118fd
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62                                                     0x118fe
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63                                                     0x118fe
+#define regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp
+// base address: 0x10147000
+#define regBIF_CFG_DEV0_EPF7_0_VENDOR_ID                                                                0x11c00
+#define regBIF_CFG_DEV0_EPF7_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_ID                                                                0x11c00
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_0_COMMAND                                                                  0x11c01
+#define regBIF_CFG_DEV0_EPF7_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF7_0_STATUS                                                                   0x11c01
+#define regBIF_CFG_DEV0_EPF7_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF7_0_REVISION_ID                                                              0x11c02
+#define regBIF_CFG_DEV0_EPF7_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_PROG_INTERFACE                                                           0x11c02
+#define regBIF_CFG_DEV0_EPF7_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_0_SUB_CLASS                                                                0x11c02
+#define regBIF_CFG_DEV0_EPF7_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_0_BASE_CLASS                                                               0x11c02
+#define regBIF_CFG_DEV0_EPF7_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_0_CACHE_LINE                                                               0x11c03
+#define regBIF_CFG_DEV0_EPF7_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_0_LATENCY                                                                  0x11c03
+#define regBIF_CFG_DEV0_EPF7_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF7_0_HEADER                                                                   0x11c03
+#define regBIF_CFG_DEV0_EPF7_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF7_0_BIST                                                                     0x11c03
+#define regBIF_CFG_DEV0_EPF7_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_1                                                              0x11c04
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_2                                                              0x11c05
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_3                                                              0x11c06
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_4                                                              0x11c07
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_5                                                              0x11c08
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_6                                                              0x11c09
+#define regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_CARDBUS_CIS_PTR                                                          0x11c0a
+#define regBIF_CFG_DEV0_EPF7_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_0_ADAPTER_ID                                                               0x11c0b
+#define regBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR                                                            0x11c0c
+#define regBIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_CAP_PTR                                                                  0x11c0d
+#define regBIF_CFG_DEV0_EPF7_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE                                                           0x11c0f
+#define regBIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN                                                            0x11c0f
+#define regBIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_MIN_GRANT                                                                0x11c0f
+#define regBIF_CFG_DEV0_EPF7_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_0_MAX_LATENCY                                                              0x11c0f
+#define regBIF_CFG_DEV0_EPF7_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST                                                          0x11c12
+#define regBIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W                                                             0x11c13
+#define regBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST                                                             0x11c14
+#define regBIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_0_PMI_CAP                                                                  0x11c14
+#define regBIF_CFG_DEV0_EPF7_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL                                                          0x11c15
+#define regBIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_0_SBRN                                                                     0x11c18
+#define regBIF_CFG_DEV0_EPF7_0_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF7_0_FLADJ                                                                    0x11c18
+#define regBIF_CFG_DEV0_EPF7_0_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF7_0_DBESL_DBESLD                                                             0x11c18
+#define regBIF_CFG_DEV0_EPF7_0_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST                                                            0x11c19
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_CAP                                                                 0x11c19
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_CAP                                                               0x11c1a
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL                                                              0x11c1b
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS                                                            0x11c1b
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_LINK_CAP                                                                 0x11c1c
+#define regBIF_CFG_DEV0_EPF7_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF7_0_LINK_CNTL                                                                0x11c1d
+#define regBIF_CFG_DEV0_EPF7_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_0_LINK_STATUS                                                              0x11c1d
+#define regBIF_CFG_DEV0_EPF7_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_CAP2                                                              0x11c22
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2                                                             0x11c23
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2                                                           0x11c23
+#define regBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_0_LINK_CAP2                                                                0x11c24
+#define regBIF_CFG_DEV0_EPF7_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_0_LINK_CNTL2                                                               0x11c25
+#define regBIF_CFG_DEV0_EPF7_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_0_LINK_STATUS2                                                             0x11c25
+#define regBIF_CFG_DEV0_EPF7_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST                                                             0x11c28
+#define regBIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL                                                             0x11c28
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO                                                          0x11c29
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI                                                          0x11c2a
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA                                                             0x11c2a
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA                                                         0x11c2a
+#define regBIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MASK                                                                 0x11c2b
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64                                                          0x11c2b
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64                                                      0x11c2b
+#define regBIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MASK_64                                                              0x11c2c
+#define regBIF_CFG_DEV0_EPF7_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_PENDING                                                              0x11c2c
+#define regBIF_CFG_DEV0_EPF7_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_0_MSI_PENDING_64                                                           0x11c2d
+#define regBIF_CFG_DEV0_EPF7_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST                                                            0x11c30
+#define regBIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL                                                            0x11c30
+#define regBIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_MSIX_TABLE                                                               0x11c31
+#define regBIF_CFG_DEV0_EPF7_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_0_MSIX_PBA                                                                 0x11c32
+#define regBIF_CFG_DEV0_EPF7_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x11c40
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x11c41
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1                                                    0x11c42
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2                                                    0x11c43
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x11c54
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS                                                   0x11c55
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK                                                     0x11c56
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x11c57
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS                                                     0x11c58
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK                                                       0x11c59
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x11c5a
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0                                                            0x11c5b
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1                                                            0x11c5c
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2                                                            0x11c5d
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3                                                            0x11c5e
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0                                                     0x11c62
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1                                                     0x11c63
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2                                                     0x11c64
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3                                                     0x11c65
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST                                                    0x11c80
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP                                                            0x11c81
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL                                                           0x11c82
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP                                                            0x11c83
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL                                                           0x11c84
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP                                                            0x11c85
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL                                                           0x11c86
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP                                                            0x11c87
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL                                                           0x11c88
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP                                                            0x11c89
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL                                                           0x11c8a
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP                                                            0x11c8b
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL                                                           0x11c8c
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x11c90
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x11c91
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA                                                     0x11c92
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP                                                      0x11c93
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST                                                    0x11c94
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP                                                             0x11c95
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR                                               0x11c96
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS                                                          0x11c97
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL                                                            0x11c97
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x11c98
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x11c98
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x11c98
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x11c98
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x11c99
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x11c99
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x11c99
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x11c99
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST                                                    0x11ca8
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP                                                             0x11ca9
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL                                                            0x11ca9
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST                                                  0x11cb4
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP                                                           0x11cb5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL                                                          0x11cb5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST                                                    0x11cca
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP                                                             0x11ccb
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL                                                            0x11ccb
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x11cdc
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP                                                        0x11cdd
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL                                                       0x11cde
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0                                                      0x11cdf
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1                                                      0x11cdf
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2                                                      0x11ce0
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3                                                      0x11ce0
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4                                                      0x11ce1
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5                                                      0x11ce1
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6                                                      0x11ce2
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7                                                      0x11ce2
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8                                                      0x11ce3
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9                                                      0x11ce3
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10                                                     0x11ce4
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11                                                     0x11ce4
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12                                                     0x11ce5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13                                                     0x11ce5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14                                                     0x11ce6
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15                                                     0x11ce6
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16                                                     0x11ce7
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17                                                     0x11ce7
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18                                                     0x11ce8
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19                                                     0x11ce8
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20                                                     0x11ce9
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21                                                     0x11ce9
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22                                                     0x11cea
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23                                                     0x11cea
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24                                                     0x11ceb
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25                                                     0x11ceb
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26                                                     0x11cec
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27                                                     0x11cec
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28                                                     0x11ced
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29                                                     0x11ced
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30                                                     0x11cee
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31                                                     0x11cee
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32                                                     0x11cef
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33                                                     0x11cef
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34                                                     0x11cf0
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35                                                     0x11cf0
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36                                                     0x11cf1
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37                                                     0x11cf1
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38                                                     0x11cf2
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39                                                     0x11cf2
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40                                                     0x11cf3
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41                                                     0x11cf3
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42                                                     0x11cf4
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43                                                     0x11cf4
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44                                                     0x11cf5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45                                                     0x11cf5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46                                                     0x11cf6
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47                                                     0x11cf6
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48                                                     0x11cf7
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49                                                     0x11cf7
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50                                                     0x11cf8
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51                                                     0x11cf8
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52                                                     0x11cf9
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53                                                     0x11cf9
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54                                                     0x11cfa
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55                                                     0x11cfa
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56                                                     0x11cfb
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57                                                     0x11cfb
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58                                                     0x11cfc
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59                                                     0x11cfc
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60                                                     0x11cfd
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61                                                     0x11cfd
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62                                                     0x11cfe
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63                                                     0x11cfe
+#define regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp
+// base address: 0x10148000
+#define regBIF_CFG_DEV1_EPF0_0_VENDOR_ID                                                                0x12000
+#define regBIF_CFG_DEV1_EPF0_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_ID                                                                0x12000
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_0_COMMAND                                                                  0x12001
+#define regBIF_CFG_DEV1_EPF0_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF0_0_STATUS                                                                   0x12001
+#define regBIF_CFG_DEV1_EPF0_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_EPF0_0_REVISION_ID                                                              0x12002
+#define regBIF_CFG_DEV1_EPF0_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_PROG_INTERFACE                                                           0x12002
+#define regBIF_CFG_DEV1_EPF0_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_SUB_CLASS                                                                0x12002
+#define regBIF_CFG_DEV1_EPF0_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_0_BASE_CLASS                                                               0x12002
+#define regBIF_CFG_DEV1_EPF0_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_0_CACHE_LINE                                                               0x12003
+#define regBIF_CFG_DEV1_EPF0_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LATENCY                                                                  0x12003
+#define regBIF_CFG_DEV1_EPF0_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF0_0_HEADER                                                                   0x12003
+#define regBIF_CFG_DEV1_EPF0_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_EPF0_0_BIST                                                                     0x12003
+#define regBIF_CFG_DEV1_EPF0_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_1                                                              0x12004
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_2                                                              0x12005
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_3                                                              0x12006
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_4                                                              0x12007
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_5                                                              0x12008
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_6                                                              0x12009
+#define regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_CARDBUS_CIS_PTR                                                          0x1200a
+#define regBIF_CFG_DEV1_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_0_ADAPTER_ID                                                               0x1200b
+#define regBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR                                                            0x1200c
+#define regBIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_CAP_PTR                                                                  0x1200d
+#define regBIF_CFG_DEV1_EPF0_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE                                                           0x1200f
+#define regBIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN                                                            0x1200f
+#define regBIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_MIN_GRANT                                                                0x1200f
+#define regBIF_CFG_DEV1_EPF0_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_0_MAX_LATENCY                                                              0x1200f
+#define regBIF_CFG_DEV1_EPF0_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST                                                          0x12012
+#define regBIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W                                                             0x12013
+#define regBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST                                                             0x12014
+#define regBIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_PMI_CAP                                                                  0x12014
+#define regBIF_CFG_DEV1_EPF0_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL                                                          0x12015
+#define regBIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_0_SBRN                                                                     0x12018
+#define regBIF_CFG_DEV1_EPF0_0_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_EPF0_0_FLADJ                                                                    0x12018
+#define regBIF_CFG_DEV1_EPF0_0_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_EPF0_0_DBESL_DBESLD                                                             0x12018
+#define regBIF_CFG_DEV1_EPF0_0_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST                                                            0x12019
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_CAP                                                                 0x12019
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_CAP                                                               0x1201a
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL                                                              0x1201b
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS                                                            0x1201b
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CAP                                                                 0x1201c
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL                                                                0x1201d
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS                                                              0x1201d
+#define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_CAP2                                                              0x12022
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2                                                             0x12023
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2                                                           0x12023
+#define regBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CAP2                                                                0x12024
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL2                                                               0x12025
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS2                                                             0x12025
+#define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST                                                             0x12028
+#define regBIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL                                                             0x12028
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO                                                          0x12029
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI                                                          0x1202a
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA                                                             0x1202a
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA                                                         0x1202a
+#define regBIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MASK                                                                 0x1202b
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64                                                          0x1202b
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64                                                      0x1202b
+#define regBIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MASK_64                                                              0x1202c
+#define regBIF_CFG_DEV1_EPF0_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_PENDING                                                              0x1202c
+#define regBIF_CFG_DEV1_EPF0_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_0_MSI_PENDING_64                                                           0x1202d
+#define regBIF_CFG_DEV1_EPF0_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST                                                            0x12030
+#define regBIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL                                                            0x12030
+#define regBIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_MSIX_TABLE                                                               0x12031
+#define regBIF_CFG_DEV1_EPF0_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_0_MSIX_PBA                                                                 0x12032
+#define regBIF_CFG_DEV1_EPF0_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x12040
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x12041
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1                                                    0x12042
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2                                                    0x12043
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST                                                     0x12044
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1                                                    0x12045
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2                                                    0x12046
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL                                                        0x12047
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS                                                      0x12047
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP                                                    0x12048
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL                                                   0x12049
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS                                                 0x1204a
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP                                                    0x1204b
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL                                                   0x1204c
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS                                                 0x1204d
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x12054
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS                                                   0x12055
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK                                                     0x12056
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x12057
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS                                                     0x12058
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK                                                       0x12059
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x1205a
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0                                                            0x1205b
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1                                                            0x1205c
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2                                                            0x1205d
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3                                                            0x1205e
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0                                                     0x12062
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1                                                     0x12063
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2                                                     0x12064
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3                                                     0x12065
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST                                                    0x12080
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP                                                            0x12081
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL                                                           0x12082
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP                                                            0x12083
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL                                                           0x12084
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP                                                            0x12085
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL                                                           0x12086
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP                                                            0x12087
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL                                                           0x12088
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP                                                            0x12089
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL                                                           0x1208a
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP                                                            0x1208b
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL                                                           0x1208c
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x12090
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x12091
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA                                                     0x12092
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP                                                      0x12093
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST                                                    0x12094
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP                                                             0x12095
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR                                               0x12096
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS                                                          0x12097
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL                                                            0x12097
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x12098
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x12098
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x12098
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x12098
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x12099
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x12099
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x12099
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x12099
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST                                              0x1209c
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3                                                          0x1209d
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS                                                   0x1209e
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL                                            0x1209f
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL                                            0x1209f
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL                                            0x120a0
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL                                            0x120a0
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL                                            0x120a1
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL                                            0x120a1
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL                                            0x120a2
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL                                            0x120a2
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL                                            0x120a3
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL                                            0x120a3
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL                                           0x120a4
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL                                           0x120a4
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL                                           0x120a5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL                                           0x120a5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL                                           0x120a6
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL                                           0x120a6
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST                                                    0x120a8
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP                                                             0x120a9
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL                                                            0x120a9
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST                                                  0x120b4
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP                                                           0x120b5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL                                                          0x120b5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST                                                    0x120c8
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP                                                             0x120c9
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST                                                    0x120ca
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP                                                             0x120cb
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL                                                            0x120cb
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x120dc
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP                                                        0x120dd
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL                                                       0x120de
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0                                                      0x120df
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1                                                      0x120df
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2                                                      0x120e0
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3                                                      0x120e0
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4                                                      0x120e1
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5                                                      0x120e1
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6                                                      0x120e2
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7                                                      0x120e2
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8                                                      0x120e3
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9                                                      0x120e3
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10                                                     0x120e4
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11                                                     0x120e4
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12                                                     0x120e5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13                                                     0x120e5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14                                                     0x120e6
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15                                                     0x120e6
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16                                                     0x120e7
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17                                                     0x120e7
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18                                                     0x120e8
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19                                                     0x120e8
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20                                                     0x120e9
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21                                                     0x120e9
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22                                                     0x120ea
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23                                                     0x120ea
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24                                                     0x120eb
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25                                                     0x120eb
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26                                                     0x120ec
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27                                                     0x120ec
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28                                                     0x120ed
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29                                                     0x120ed
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30                                                     0x120ee
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31                                                     0x120ee
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32                                                     0x120ef
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33                                                     0x120ef
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34                                                     0x120f0
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35                                                     0x120f0
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36                                                     0x120f1
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37                                                     0x120f1
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38                                                     0x120f2
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39                                                     0x120f2
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40                                                     0x120f3
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41                                                     0x120f3
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42                                                     0x120f4
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43                                                     0x120f4
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44                                                     0x120f5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45                                                     0x120f5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46                                                     0x120f6
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47                                                     0x120f6
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48                                                     0x120f7
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49                                                     0x120f7
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50                                                     0x120f8
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51                                                     0x120f8
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52                                                     0x120f9
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53                                                     0x120f9
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54                                                     0x120fa
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55                                                     0x120fa
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56                                                     0x120fb
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57                                                     0x120fb
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58                                                     0x120fc
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59                                                     0x120fc
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60                                                     0x120fd
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61                                                     0x120fd
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62                                                     0x120fe
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63                                                     0x120fe
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST                                                    0x12100
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP                                                    0x12101
+#define regBIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS                                                 0x12102
+#define regBIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST                                               0x12104
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT                                                            0x12105
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT                                                           0x12106
+#define regBIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT                                                         0x12107
+#define regBIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT_BASE_IDX                                                5
+#define regBIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0x12108
+#define regBIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                               5
+#define regBIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0x12109
+#define regBIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0x1210a
+#define regBIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT                                            0x1210c
+#define regBIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT                                            0x1210c
+#define regBIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT                                            0x1210c
+#define regBIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT                                            0x1210c
+#define regBIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT                                            0x1210d
+#define regBIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT                                            0x1210d
+#define regBIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT                                            0x1210d
+#define regBIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT                                            0x1210d
+#define regBIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT                                            0x1210e
+#define regBIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT                                            0x1210e
+#define regBIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT                                           0x1210e
+#define regBIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT                                           0x1210e
+#define regBIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT                                           0x1210f
+#define regBIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT                                           0x1210f
+#define regBIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT                                           0x1210f
+#define regBIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT                                           0x1210f
+#define regBIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST                                              0x12110
+#define regBIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP                                                       0x12111
+#define regBIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS                                                    0x12111
+#define regBIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL                                               0x12112
+#define regBIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS                                             0x12112
+#define regBIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL                                               0x12113
+#define regBIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS                                             0x12113
+#define regBIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL                                               0x12114
+#define regBIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS                                             0x12114
+#define regBIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL                                               0x12115
+#define regBIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS                                             0x12115
+#define regBIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL                                               0x12116
+#define regBIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS                                             0x12116
+#define regBIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL                                               0x12117
+#define regBIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS                                             0x12117
+#define regBIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL                                               0x12118
+#define regBIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS                                             0x12118
+#define regBIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL                                               0x12119
+#define regBIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS                                             0x12119
+#define regBIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL                                               0x1211a
+#define regBIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS                                             0x1211a
+#define regBIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL                                               0x1211b
+#define regBIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS                                             0x1211b
+#define regBIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL                                              0x1211c
+#define regBIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS                                            0x1211c
+#define regBIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL                                              0x1211d
+#define regBIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS                                            0x1211d
+#define regBIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL                                              0x1211e
+#define regBIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS                                            0x1211e
+#define regBIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL                                              0x1211f
+#define regBIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS                                            0x1211f
+#define regBIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL                                              0x12120
+#define regBIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS                                            0x12120
+#define regBIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL                                              0x12121
+#define regBIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS                                            0x12121
+#define regBIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                   5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp
+// base address: 0x10149000
+#define regBIF_CFG_DEV1_EPF1_0_VENDOR_ID                                                                0x12400
+#define regBIF_CFG_DEV1_EPF1_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_ID                                                                0x12400
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_0_COMMAND                                                                  0x12401
+#define regBIF_CFG_DEV1_EPF1_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF1_0_STATUS                                                                   0x12401
+#define regBIF_CFG_DEV1_EPF1_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_EPF1_0_REVISION_ID                                                              0x12402
+#define regBIF_CFG_DEV1_EPF1_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_PROG_INTERFACE                                                           0x12402
+#define regBIF_CFG_DEV1_EPF1_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_0_SUB_CLASS                                                                0x12402
+#define regBIF_CFG_DEV1_EPF1_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_0_BASE_CLASS                                                               0x12402
+#define regBIF_CFG_DEV1_EPF1_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_0_CACHE_LINE                                                               0x12403
+#define regBIF_CFG_DEV1_EPF1_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_0_LATENCY                                                                  0x12403
+#define regBIF_CFG_DEV1_EPF1_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF1_0_HEADER                                                                   0x12403
+#define regBIF_CFG_DEV1_EPF1_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_EPF1_0_BIST                                                                     0x12403
+#define regBIF_CFG_DEV1_EPF1_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_1                                                              0x12404
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_2                                                              0x12405
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_3                                                              0x12406
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_4                                                              0x12407
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_5                                                              0x12408
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_6                                                              0x12409
+#define regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_CARDBUS_CIS_PTR                                                          0x1240a
+#define regBIF_CFG_DEV1_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_0_ADAPTER_ID                                                               0x1240b
+#define regBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR                                                            0x1240c
+#define regBIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_CAP_PTR                                                                  0x1240d
+#define regBIF_CFG_DEV1_EPF1_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE                                                           0x1240f
+#define regBIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN                                                            0x1240f
+#define regBIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_MIN_GRANT                                                                0x1240f
+#define regBIF_CFG_DEV1_EPF1_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_0_MAX_LATENCY                                                              0x1240f
+#define regBIF_CFG_DEV1_EPF1_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST                                                          0x12412
+#define regBIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W                                                             0x12413
+#define regBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST                                                             0x12414
+#define regBIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_0_PMI_CAP                                                                  0x12414
+#define regBIF_CFG_DEV1_EPF1_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL                                                          0x12415
+#define regBIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_0_SBRN                                                                     0x12418
+#define regBIF_CFG_DEV1_EPF1_0_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_EPF1_0_FLADJ                                                                    0x12418
+#define regBIF_CFG_DEV1_EPF1_0_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_EPF1_0_DBESL_DBESLD                                                             0x12418
+#define regBIF_CFG_DEV1_EPF1_0_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST                                                            0x12419
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_CAP                                                                 0x12419
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_CAP                                                               0x1241a
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL                                                              0x1241b
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS                                                            0x1241b
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_LINK_CAP                                                                 0x1241c
+#define regBIF_CFG_DEV1_EPF1_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF1_0_LINK_CNTL                                                                0x1241d
+#define regBIF_CFG_DEV1_EPF1_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_0_LINK_STATUS                                                              0x1241d
+#define regBIF_CFG_DEV1_EPF1_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_CAP2                                                              0x12422
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2                                                             0x12423
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2                                                           0x12423
+#define regBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_0_LINK_CAP2                                                                0x12424
+#define regBIF_CFG_DEV1_EPF1_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_0_LINK_CNTL2                                                               0x12425
+#define regBIF_CFG_DEV1_EPF1_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_0_LINK_STATUS2                                                             0x12425
+#define regBIF_CFG_DEV1_EPF1_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST                                                             0x12428
+#define regBIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL                                                             0x12428
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO                                                          0x12429
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI                                                          0x1242a
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA                                                             0x1242a
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA                                                         0x1242a
+#define regBIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MASK                                                                 0x1242b
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64                                                          0x1242b
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64                                                      0x1242b
+#define regBIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MASK_64                                                              0x1242c
+#define regBIF_CFG_DEV1_EPF1_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_PENDING                                                              0x1242c
+#define regBIF_CFG_DEV1_EPF1_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_0_MSI_PENDING_64                                                           0x1242d
+#define regBIF_CFG_DEV1_EPF1_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST                                                            0x12430
+#define regBIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL                                                            0x12430
+#define regBIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_MSIX_TABLE                                                               0x12431
+#define regBIF_CFG_DEV1_EPF1_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_0_MSIX_PBA                                                                 0x12432
+#define regBIF_CFG_DEV1_EPF1_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x12440
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x12441
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1                                                    0x12442
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2                                                    0x12443
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x12454
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS                                                   0x12455
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK                                                     0x12456
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x12457
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS                                                     0x12458
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK                                                       0x12459
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x1245a
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0                                                            0x1245b
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1                                                            0x1245c
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2                                                            0x1245d
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3                                                            0x1245e
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0                                                     0x12462
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1                                                     0x12463
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2                                                     0x12464
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3                                                     0x12465
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST                                                    0x12480
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP                                                            0x12481
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL                                                           0x12482
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP                                                            0x12483
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL                                                           0x12484
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP                                                            0x12485
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL                                                           0x12486
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP                                                            0x12487
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL                                                           0x12488
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP                                                            0x12489
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL                                                           0x1248a
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP                                                            0x1248b
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL                                                           0x1248c
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x12490
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x12491
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA                                                     0x12492
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP                                                      0x12493
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST                                                    0x12494
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP                                                             0x12495
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR                                               0x12496
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS                                                          0x12497
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL                                                            0x12497
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x12498
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x12498
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x12498
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x12498
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x12499
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x12499
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x12499
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x12499
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST                                                    0x124a8
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP                                                             0x124a9
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL                                                            0x124a9
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST                                                  0x124b4
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP                                                           0x124b5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL                                                          0x124b5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST                                                    0x124ca
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP                                                             0x124cb
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL                                                            0x124cb
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x124dc
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP                                                        0x124dd
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL                                                       0x124de
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0                                                      0x124df
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1                                                      0x124df
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2                                                      0x124e0
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3                                                      0x124e0
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4                                                      0x124e1
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5                                                      0x124e1
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6                                                      0x124e2
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7                                                      0x124e2
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8                                                      0x124e3
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9                                                      0x124e3
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10                                                     0x124e4
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11                                                     0x124e4
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12                                                     0x124e5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13                                                     0x124e5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14                                                     0x124e6
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15                                                     0x124e6
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16                                                     0x124e7
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17                                                     0x124e7
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18                                                     0x124e8
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19                                                     0x124e8
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20                                                     0x124e9
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21                                                     0x124e9
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22                                                     0x124ea
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23                                                     0x124ea
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24                                                     0x124eb
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25                                                     0x124eb
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26                                                     0x124ec
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27                                                     0x124ec
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28                                                     0x124ed
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29                                                     0x124ed
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30                                                     0x124ee
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31                                                     0x124ee
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32                                                     0x124ef
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33                                                     0x124ef
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34                                                     0x124f0
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35                                                     0x124f0
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36                                                     0x124f1
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37                                                     0x124f1
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38                                                     0x124f2
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39                                                     0x124f2
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40                                                     0x124f3
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41                                                     0x124f3
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42                                                     0x124f4
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43                                                     0x124f4
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44                                                     0x124f5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45                                                     0x124f5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46                                                     0x124f6
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47                                                     0x124f6
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48                                                     0x124f7
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49                                                     0x124f7
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50                                                     0x124f8
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51                                                     0x124f8
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52                                                     0x124f9
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53                                                     0x124f9
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54                                                     0x124fa
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55                                                     0x124fa
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56                                                     0x124fb
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57                                                     0x124fb
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58                                                     0x124fc
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59                                                     0x124fc
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60                                                     0x124fd
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61                                                     0x124fd
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62                                                     0x124fe
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63                                                     0x124fe
+#define regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp
+// base address: 0x10150000
+#define regBIF_CFG_DEV2_EPF0_0_VENDOR_ID                                                                0x14000
+#define regBIF_CFG_DEV2_EPF0_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_ID                                                                0x14000
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_0_COMMAND                                                                  0x14001
+#define regBIF_CFG_DEV2_EPF0_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF0_0_STATUS                                                                   0x14001
+#define regBIF_CFG_DEV2_EPF0_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF0_0_REVISION_ID                                                              0x14002
+#define regBIF_CFG_DEV2_EPF0_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_PROG_INTERFACE                                                           0x14002
+#define regBIF_CFG_DEV2_EPF0_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_SUB_CLASS                                                                0x14002
+#define regBIF_CFG_DEV2_EPF0_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_0_BASE_CLASS                                                               0x14002
+#define regBIF_CFG_DEV2_EPF0_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_0_CACHE_LINE                                                               0x14003
+#define regBIF_CFG_DEV2_EPF0_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LATENCY                                                                  0x14003
+#define regBIF_CFG_DEV2_EPF0_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF0_0_HEADER                                                                   0x14003
+#define regBIF_CFG_DEV2_EPF0_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF0_0_BIST                                                                     0x14003
+#define regBIF_CFG_DEV2_EPF0_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_1                                                              0x14004
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_2                                                              0x14005
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_3                                                              0x14006
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_4                                                              0x14007
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_5                                                              0x14008
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_6                                                              0x14009
+#define regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_CARDBUS_CIS_PTR                                                          0x1400a
+#define regBIF_CFG_DEV2_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_0_ADAPTER_ID                                                               0x1400b
+#define regBIF_CFG_DEV2_EPF0_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR                                                            0x1400c
+#define regBIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_CAP_PTR                                                                  0x1400d
+#define regBIF_CFG_DEV2_EPF0_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE                                                           0x1400f
+#define regBIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN                                                            0x1400f
+#define regBIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_MIN_GRANT                                                                0x1400f
+#define regBIF_CFG_DEV2_EPF0_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_0_MAX_LATENCY                                                              0x1400f
+#define regBIF_CFG_DEV2_EPF0_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST                                                          0x14012
+#define regBIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W                                                             0x14013
+#define regBIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST                                                             0x14014
+#define regBIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_PMI_CAP                                                                  0x14014
+#define regBIF_CFG_DEV2_EPF0_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL                                                          0x14015
+#define regBIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_0_SBRN                                                                     0x14018
+#define regBIF_CFG_DEV2_EPF0_0_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF0_0_FLADJ                                                                    0x14018
+#define regBIF_CFG_DEV2_EPF0_0_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_EPF0_0_DBESL_DBESLD                                                             0x14018
+#define regBIF_CFG_DEV2_EPF0_0_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST                                                            0x14019
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_CAP                                                                 0x14019
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_CAP                                                               0x1401a
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_CNTL                                                              0x1401b
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_STATUS                                                            0x1401b
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CAP                                                                 0x1401c
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL                                                                0x1401d
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS                                                              0x1401d
+#define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_CAP2                                                              0x14022
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2                                                             0x14023
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2                                                           0x14023
+#define regBIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CAP2                                                                0x14024
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL2                                                               0x14025
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS2                                                             0x14025
+#define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST                                                             0x14028
+#define regBIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL                                                             0x14028
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO                                                          0x14029
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI                                                          0x1402a
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA                                                             0x1402a
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA                                                         0x1402a
+#define regBIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MASK                                                                 0x1402b
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64                                                          0x1402b
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64                                                      0x1402b
+#define regBIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MASK_64                                                              0x1402c
+#define regBIF_CFG_DEV2_EPF0_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_PENDING                                                              0x1402c
+#define regBIF_CFG_DEV2_EPF0_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_0_MSI_PENDING_64                                                           0x1402d
+#define regBIF_CFG_DEV2_EPF0_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST                                                            0x14030
+#define regBIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL                                                            0x14030
+#define regBIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_MSIX_TABLE                                                               0x14031
+#define regBIF_CFG_DEV2_EPF0_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_0_MSIX_PBA                                                                 0x14032
+#define regBIF_CFG_DEV2_EPF0_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x14040
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x14041
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1                                                    0x14042
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2                                                    0x14043
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST                                                     0x14044
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1                                                    0x14045
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2                                                    0x14046
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL                                                        0x14047
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS                                                      0x14047
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP                                                    0x14048
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL                                                   0x14049
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS                                                 0x1404a
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP                                                    0x1404b
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL                                                   0x1404c
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS                                                 0x1404d
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x14054
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS                                                   0x14055
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK                                                     0x14056
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x14057
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS                                                     0x14058
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK                                                       0x14059
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x1405a
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0                                                            0x1405b
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1                                                            0x1405c
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2                                                            0x1405d
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3                                                            0x1405e
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0                                                     0x14062
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1                                                     0x14063
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2                                                     0x14064
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3                                                     0x14065
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST                                                    0x14080
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP                                                            0x14081
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL                                                           0x14082
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP                                                            0x14083
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL                                                           0x14084
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP                                                            0x14085
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL                                                           0x14086
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP                                                            0x14087
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL                                                           0x14088
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP                                                            0x14089
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL                                                           0x1408a
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP                                                            0x1408b
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL                                                           0x1408c
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x14090
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x14091
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA                                                     0x14092
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP                                                      0x14093
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST                                                    0x14094
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP                                                             0x14095
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR                                               0x14096
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS                                                          0x14097
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL                                                            0x14097
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x14098
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x14098
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x14098
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x14098
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x14099
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x14099
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x14099
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x14099
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST                                              0x1409c
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3                                                          0x1409d
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS                                                   0x1409e
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL                                            0x1409f
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL                                            0x1409f
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL                                            0x140a0
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL                                            0x140a0
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL                                            0x140a1
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL                                            0x140a1
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL                                            0x140a2
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL                                            0x140a2
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL                                            0x140a3
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL                                            0x140a3
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL                                           0x140a4
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL                                           0x140a4
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL                                           0x140a5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL                                           0x140a5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL                                           0x140a6
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL                                           0x140a6
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST                                                    0x140a8
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP                                                             0x140a9
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL                                                            0x140a9
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST                                                  0x140b4
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP                                                           0x140b5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL                                                          0x140b5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST                                                    0x140c8
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP                                                             0x140c9
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST                                                    0x140ca
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP                                                             0x140cb
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL                                                            0x140cb
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x140dc
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP                                                        0x140dd
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL                                                       0x140de
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0                                                      0x140df
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1                                                      0x140df
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2                                                      0x140e0
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3                                                      0x140e0
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4                                                      0x140e1
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5                                                      0x140e1
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6                                                      0x140e2
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7                                                      0x140e2
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8                                                      0x140e3
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9                                                      0x140e3
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10                                                     0x140e4
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11                                                     0x140e4
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12                                                     0x140e5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13                                                     0x140e5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14                                                     0x140e6
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15                                                     0x140e6
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16                                                     0x140e7
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17                                                     0x140e7
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18                                                     0x140e8
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19                                                     0x140e8
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20                                                     0x140e9
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21                                                     0x140e9
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22                                                     0x140ea
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23                                                     0x140ea
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24                                                     0x140eb
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25                                                     0x140eb
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26                                                     0x140ec
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27                                                     0x140ec
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28                                                     0x140ed
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29                                                     0x140ed
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30                                                     0x140ee
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31                                                     0x140ee
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32                                                     0x140ef
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33                                                     0x140ef
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34                                                     0x140f0
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35                                                     0x140f0
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36                                                     0x140f1
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37                                                     0x140f1
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38                                                     0x140f2
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39                                                     0x140f2
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40                                                     0x140f3
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41                                                     0x140f3
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42                                                     0x140f4
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43                                                     0x140f4
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44                                                     0x140f5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45                                                     0x140f5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46                                                     0x140f6
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47                                                     0x140f6
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48                                                     0x140f7
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49                                                     0x140f7
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50                                                     0x140f8
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51                                                     0x140f8
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52                                                     0x140f9
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53                                                     0x140f9
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54                                                     0x140fa
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55                                                     0x140fa
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56                                                     0x140fb
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57                                                     0x140fb
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58                                                     0x140fc
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59                                                     0x140fc
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60                                                     0x140fd
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61                                                     0x140fd
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62                                                     0x140fe
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63                                                     0x140fe
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST                                                    0x14100
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP                                                    0x14101
+#define regBIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS                                                 0x14102
+#define regBIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST                                               0x14104
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT                                                            0x14105
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT                                                           0x14106
+#define regBIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT                                                         0x14107
+#define regBIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0x14108
+#define regBIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                               5
+#define regBIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0x14109
+#define regBIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0x1410a
+#define regBIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT                                            0x1410c
+#define regBIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT                                            0x1410c
+#define regBIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT                                            0x1410c
+#define regBIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT                                            0x1410c
+#define regBIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT                                            0x1410d
+#define regBIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT                                            0x1410d
+#define regBIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT                                            0x1410d
+#define regBIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT                                            0x1410d
+#define regBIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT                                            0x1410e
+#define regBIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT                                            0x1410e
+#define regBIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT                                           0x1410e
+#define regBIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT                                           0x1410e
+#define regBIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT                                           0x1410f
+#define regBIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT                                           0x1410f
+#define regBIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT                                           0x1410f
+#define regBIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT                                           0x1410f
+#define regBIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST                                              0x14110
+#define regBIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP                                                       0x14111
+#define regBIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS                                                    0x14111
+#define regBIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL                                               0x14112
+#define regBIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS                                             0x14112
+#define regBIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL                                               0x14113
+#define regBIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS                                             0x14113
+#define regBIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL                                               0x14114
+#define regBIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS                                             0x14114
+#define regBIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL                                               0x14115
+#define regBIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS                                             0x14115
+#define regBIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL                                               0x14116
+#define regBIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS                                             0x14116
+#define regBIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL                                               0x14117
+#define regBIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS                                             0x14117
+#define regBIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL                                               0x14118
+#define regBIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS                                             0x14118
+#define regBIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL                                               0x14119
+#define regBIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS                                             0x14119
+#define regBIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL                                               0x1411a
+#define regBIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS                                             0x1411a
+#define regBIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL                                               0x1411b
+#define regBIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS                                             0x1411b
+#define regBIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL                                              0x1411c
+#define regBIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS                                            0x1411c
+#define regBIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL                                              0x1411d
+#define regBIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS                                            0x1411d
+#define regBIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL                                              0x1411e
+#define regBIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS                                            0x1411e
+#define regBIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL                                              0x1411f
+#define regBIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS                                            0x1411f
+#define regBIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL                                              0x14120
+#define regBIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS                                            0x14120
+#define regBIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL                                              0x14121
+#define regBIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS                                            0x14121
+#define regBIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                   5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf1_bifcfgdecp
+// base address: 0x10151000
+#define regBIF_CFG_DEV2_EPF1_0_VENDOR_ID                                                                0x14400
+#define regBIF_CFG_DEV2_EPF1_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_ID                                                                0x14400
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_0_COMMAND                                                                  0x14401
+#define regBIF_CFG_DEV2_EPF1_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF1_0_STATUS                                                                   0x14401
+#define regBIF_CFG_DEV2_EPF1_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF1_0_REVISION_ID                                                              0x14402
+#define regBIF_CFG_DEV2_EPF1_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_PROG_INTERFACE                                                           0x14402
+#define regBIF_CFG_DEV2_EPF1_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_0_SUB_CLASS                                                                0x14402
+#define regBIF_CFG_DEV2_EPF1_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_0_BASE_CLASS                                                               0x14402
+#define regBIF_CFG_DEV2_EPF1_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_0_CACHE_LINE                                                               0x14403
+#define regBIF_CFG_DEV2_EPF1_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_0_LATENCY                                                                  0x14403
+#define regBIF_CFG_DEV2_EPF1_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF1_0_HEADER                                                                   0x14403
+#define regBIF_CFG_DEV2_EPF1_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF1_0_BIST                                                                     0x14403
+#define regBIF_CFG_DEV2_EPF1_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_1                                                              0x14404
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_2                                                              0x14405
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_3                                                              0x14406
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_4                                                              0x14407
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_5                                                              0x14408
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_6                                                              0x14409
+#define regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_CARDBUS_CIS_PTR                                                          0x1440a
+#define regBIF_CFG_DEV2_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_0_ADAPTER_ID                                                               0x1440b
+#define regBIF_CFG_DEV2_EPF1_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR                                                            0x1440c
+#define regBIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_CAP_PTR                                                                  0x1440d
+#define regBIF_CFG_DEV2_EPF1_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE                                                           0x1440f
+#define regBIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN                                                            0x1440f
+#define regBIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_MIN_GRANT                                                                0x1440f
+#define regBIF_CFG_DEV2_EPF1_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_0_MAX_LATENCY                                                              0x1440f
+#define regBIF_CFG_DEV2_EPF1_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST                                                          0x14412
+#define regBIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W                                                             0x14413
+#define regBIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST                                                             0x14414
+#define regBIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_0_PMI_CAP                                                                  0x14414
+#define regBIF_CFG_DEV2_EPF1_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL                                                          0x14415
+#define regBIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_0_SBRN                                                                     0x14418
+#define regBIF_CFG_DEV2_EPF1_0_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF1_0_FLADJ                                                                    0x14418
+#define regBIF_CFG_DEV2_EPF1_0_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_EPF1_0_DBESL_DBESLD                                                             0x14418
+#define regBIF_CFG_DEV2_EPF1_0_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST                                                            0x14419
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_CAP                                                                 0x14419
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_CAP                                                               0x1441a
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_CNTL                                                              0x1441b
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_STATUS                                                            0x1441b
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_LINK_CAP                                                                 0x1441c
+#define regBIF_CFG_DEV2_EPF1_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF1_0_LINK_CNTL                                                                0x1441d
+#define regBIF_CFG_DEV2_EPF1_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_0_LINK_STATUS                                                              0x1441d
+#define regBIF_CFG_DEV2_EPF1_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_CAP2                                                              0x14422
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2                                                             0x14423
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2                                                           0x14423
+#define regBIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_0_LINK_CAP2                                                                0x14424
+#define regBIF_CFG_DEV2_EPF1_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_0_LINK_CNTL2                                                               0x14425
+#define regBIF_CFG_DEV2_EPF1_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_0_LINK_STATUS2                                                             0x14425
+#define regBIF_CFG_DEV2_EPF1_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST                                                             0x14428
+#define regBIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL                                                             0x14428
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO                                                          0x14429
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI                                                          0x1442a
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA                                                             0x1442a
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA                                                         0x1442a
+#define regBIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MASK                                                                 0x1442b
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64                                                          0x1442b
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64                                                      0x1442b
+#define regBIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MASK_64                                                              0x1442c
+#define regBIF_CFG_DEV2_EPF1_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_PENDING                                                              0x1442c
+#define regBIF_CFG_DEV2_EPF1_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_0_MSI_PENDING_64                                                           0x1442d
+#define regBIF_CFG_DEV2_EPF1_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST                                                            0x14430
+#define regBIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL                                                            0x14430
+#define regBIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_MSIX_TABLE                                                               0x14431
+#define regBIF_CFG_DEV2_EPF1_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_0_MSIX_PBA                                                                 0x14432
+#define regBIF_CFG_DEV2_EPF1_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x14440
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x14441
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1                                                    0x14442
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2                                                    0x14443
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x14454
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS                                                   0x14455
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK                                                     0x14456
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x14457
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS                                                     0x14458
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK                                                       0x14459
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x1445a
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0                                                            0x1445b
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1                                                            0x1445c
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2                                                            0x1445d
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3                                                            0x1445e
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0                                                     0x14462
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1                                                     0x14463
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2                                                     0x14464
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3                                                     0x14465
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST                                                    0x14480
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP                                                            0x14481
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL                                                           0x14482
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP                                                            0x14483
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL                                                           0x14484
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP                                                            0x14485
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL                                                           0x14486
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP                                                            0x14487
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL                                                           0x14488
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP                                                            0x14489
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL                                                           0x1448a
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP                                                            0x1448b
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL                                                           0x1448c
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x14490
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x14491
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA                                                     0x14492
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP                                                      0x14493
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST                                                    0x14494
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP                                                             0x14495
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR                                               0x14496
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS                                                          0x14497
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL                                                            0x14497
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x14498
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x14498
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x14498
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x14498
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x14499
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x14499
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x14499
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x14499
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST                                                    0x144a8
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP                                                             0x144a9
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL                                                            0x144a9
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST                                                  0x144b4
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP                                                           0x144b5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL                                                          0x144b5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST                                                    0x144ca
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP                                                             0x144cb
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL                                                            0x144cb
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x144dc
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP                                                        0x144dd
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL                                                       0x144de
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0                                                      0x144df
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1                                                      0x144df
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2                                                      0x144e0
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3                                                      0x144e0
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4                                                      0x144e1
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5                                                      0x144e1
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6                                                      0x144e2
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7                                                      0x144e2
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8                                                      0x144e3
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9                                                      0x144e3
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10                                                     0x144e4
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11                                                     0x144e4
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12                                                     0x144e5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13                                                     0x144e5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14                                                     0x144e6
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15                                                     0x144e6
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16                                                     0x144e7
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17                                                     0x144e7
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18                                                     0x144e8
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19                                                     0x144e8
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20                                                     0x144e9
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21                                                     0x144e9
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22                                                     0x144ea
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23                                                     0x144ea
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24                                                     0x144eb
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25                                                     0x144eb
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26                                                     0x144ec
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27                                                     0x144ec
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28                                                     0x144ed
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29                                                     0x144ed
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30                                                     0x144ee
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31                                                     0x144ee
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32                                                     0x144ef
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33                                                     0x144ef
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34                                                     0x144f0
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35                                                     0x144f0
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36                                                     0x144f1
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37                                                     0x144f1
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38                                                     0x144f2
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39                                                     0x144f2
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40                                                     0x144f3
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41                                                     0x144f3
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42                                                     0x144f4
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43                                                     0x144f4
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44                                                     0x144f5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45                                                     0x144f5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46                                                     0x144f6
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47                                                     0x144f6
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48                                                     0x144f7
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49                                                     0x144f7
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50                                                     0x144f8
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51                                                     0x144f8
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52                                                     0x144f9
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53                                                     0x144f9
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54                                                     0x144fa
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55                                                     0x144fa
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56                                                     0x144fb
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57                                                     0x144fb
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58                                                     0x144fc
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59                                                     0x144fc
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60                                                     0x144fd
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61                                                     0x144fd
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62                                                     0x144fe
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63                                                     0x144fe
+#define regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf2_bifcfgdecp
+// base address: 0x10152000
+#define regBIF_CFG_DEV2_EPF2_0_VENDOR_ID                                                                0x14800
+#define regBIF_CFG_DEV2_EPF2_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_ID                                                                0x14800
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_0_COMMAND                                                                  0x14801
+#define regBIF_CFG_DEV2_EPF2_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF2_0_STATUS                                                                   0x14801
+#define regBIF_CFG_DEV2_EPF2_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF2_0_REVISION_ID                                                              0x14802
+#define regBIF_CFG_DEV2_EPF2_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_PROG_INTERFACE                                                           0x14802
+#define regBIF_CFG_DEV2_EPF2_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_0_SUB_CLASS                                                                0x14802
+#define regBIF_CFG_DEV2_EPF2_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_0_BASE_CLASS                                                               0x14802
+#define regBIF_CFG_DEV2_EPF2_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_0_CACHE_LINE                                                               0x14803
+#define regBIF_CFG_DEV2_EPF2_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_0_LATENCY                                                                  0x14803
+#define regBIF_CFG_DEV2_EPF2_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF2_0_HEADER                                                                   0x14803
+#define regBIF_CFG_DEV2_EPF2_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF2_0_BIST                                                                     0x14803
+#define regBIF_CFG_DEV2_EPF2_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_1                                                              0x14804
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_2                                                              0x14805
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_3                                                              0x14806
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_4                                                              0x14807
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_5                                                              0x14808
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_6                                                              0x14809
+#define regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_CARDBUS_CIS_PTR                                                          0x1480a
+#define regBIF_CFG_DEV2_EPF2_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_0_ADAPTER_ID                                                               0x1480b
+#define regBIF_CFG_DEV2_EPF2_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR                                                            0x1480c
+#define regBIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_CAP_PTR                                                                  0x1480d
+#define regBIF_CFG_DEV2_EPF2_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE                                                           0x1480f
+#define regBIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN                                                            0x1480f
+#define regBIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_MIN_GRANT                                                                0x1480f
+#define regBIF_CFG_DEV2_EPF2_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_0_MAX_LATENCY                                                              0x1480f
+#define regBIF_CFG_DEV2_EPF2_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST                                                          0x14812
+#define regBIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W                                                             0x14813
+#define regBIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST                                                             0x14814
+#define regBIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_0_PMI_CAP                                                                  0x14814
+#define regBIF_CFG_DEV2_EPF2_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL                                                          0x14815
+#define regBIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_0_SBRN                                                                     0x14818
+#define regBIF_CFG_DEV2_EPF2_0_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF2_0_FLADJ                                                                    0x14818
+#define regBIF_CFG_DEV2_EPF2_0_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_EPF2_0_DBESL_DBESLD                                                             0x14818
+#define regBIF_CFG_DEV2_EPF2_0_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST                                                            0x14819
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_CAP                                                                 0x14819
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_CAP                                                               0x1481a
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_CNTL                                                              0x1481b
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_STATUS                                                            0x1481b
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_LINK_CAP                                                                 0x1481c
+#define regBIF_CFG_DEV2_EPF2_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF2_0_LINK_CNTL                                                                0x1481d
+#define regBIF_CFG_DEV2_EPF2_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_0_LINK_STATUS                                                              0x1481d
+#define regBIF_CFG_DEV2_EPF2_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_CAP2                                                              0x14822
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2                                                             0x14823
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2                                                           0x14823
+#define regBIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_0_LINK_CAP2                                                                0x14824
+#define regBIF_CFG_DEV2_EPF2_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_0_LINK_CNTL2                                                               0x14825
+#define regBIF_CFG_DEV2_EPF2_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_0_LINK_STATUS2                                                             0x14825
+#define regBIF_CFG_DEV2_EPF2_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST                                                             0x14828
+#define regBIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL                                                             0x14828
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO                                                          0x14829
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI                                                          0x1482a
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA                                                             0x1482a
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA                                                         0x1482a
+#define regBIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MASK                                                                 0x1482b
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64                                                          0x1482b
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64                                                      0x1482b
+#define regBIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MASK_64                                                              0x1482c
+#define regBIF_CFG_DEV2_EPF2_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_PENDING                                                              0x1482c
+#define regBIF_CFG_DEV2_EPF2_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_0_MSI_PENDING_64                                                           0x1482d
+#define regBIF_CFG_DEV2_EPF2_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST                                                            0x14830
+#define regBIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL                                                            0x14830
+#define regBIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_MSIX_TABLE                                                               0x14831
+#define regBIF_CFG_DEV2_EPF2_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_0_MSIX_PBA                                                                 0x14832
+#define regBIF_CFG_DEV2_EPF2_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x14840
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x14841
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1                                                    0x14842
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2                                                    0x14843
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x14854
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS                                                   0x14855
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK                                                     0x14856
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x14857
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS                                                     0x14858
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK                                                       0x14859
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x1485a
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0                                                            0x1485b
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1                                                            0x1485c
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2                                                            0x1485d
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3                                                            0x1485e
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0                                                     0x14862
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1                                                     0x14863
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2                                                     0x14864
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3                                                     0x14865
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST                                                    0x14880
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP                                                            0x14881
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL                                                           0x14882
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP                                                            0x14883
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL                                                           0x14884
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP                                                            0x14885
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL                                                           0x14886
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP                                                            0x14887
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL                                                           0x14888
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP                                                            0x14889
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL                                                           0x1488a
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP                                                            0x1488b
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL                                                           0x1488c
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x14890
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x14891
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA                                                     0x14892
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP                                                      0x14893
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST                                                    0x14894
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP                                                             0x14895
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR                                               0x14896
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS                                                          0x14897
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL                                                            0x14897
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x14898
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x14898
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x14898
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x14898
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x14899
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x14899
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x14899
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x14899
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST                                                    0x148a8
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP                                                             0x148a9
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL                                                            0x148a9
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST                                                  0x148b4
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP                                                           0x148b5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL                                                          0x148b5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST                                                    0x148ca
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP                                                             0x148cb
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL                                                            0x148cb
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x148dc
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP                                                        0x148dd
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL                                                       0x148de
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0                                                      0x148df
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1                                                      0x148df
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2                                                      0x148e0
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3                                                      0x148e0
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4                                                      0x148e1
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5                                                      0x148e1
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6                                                      0x148e2
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7                                                      0x148e2
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8                                                      0x148e3
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9                                                      0x148e3
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10                                                     0x148e4
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11                                                     0x148e4
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12                                                     0x148e5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13                                                     0x148e5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14                                                     0x148e6
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15                                                     0x148e6
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16                                                     0x148e7
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17                                                     0x148e7
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18                                                     0x148e8
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19                                                     0x148e8
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20                                                     0x148e9
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21                                                     0x148e9
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22                                                     0x148ea
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23                                                     0x148ea
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24                                                     0x148eb
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25                                                     0x148eb
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26                                                     0x148ec
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27                                                     0x148ec
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28                                                     0x148ed
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29                                                     0x148ed
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30                                                     0x148ee
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31                                                     0x148ee
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32                                                     0x148ef
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33                                                     0x148ef
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34                                                     0x148f0
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35                                                     0x148f0
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36                                                     0x148f1
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37                                                     0x148f1
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38                                                     0x148f2
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39                                                     0x148f2
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40                                                     0x148f3
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41                                                     0x148f3
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42                                                     0x148f4
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43                                                     0x148f4
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44                                                     0x148f5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45                                                     0x148f5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46                                                     0x148f6
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47                                                     0x148f6
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48                                                     0x148f7
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49                                                     0x148f7
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50                                                     0x148f8
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51                                                     0x148f8
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52                                                     0x148f9
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53                                                     0x148f9
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54                                                     0x148fa
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55                                                     0x148fa
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56                                                     0x148fb
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57                                                     0x148fb
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58                                                     0x148fc
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59                                                     0x148fc
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60                                                     0x148fd
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61                                                     0x148fd
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62                                                     0x148fe
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63                                                     0x148fe
+#define regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+// base address: 0x11100000
+#define regBIFPLR0_0_VENDOR_ID                                                                          0x400000
+#define regBIFPLR0_0_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR0_0_DEVICE_ID                                                                          0x400000
+#define regBIFPLR0_0_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR0_0_COMMAND                                                                            0x400001
+#define regBIFPLR0_0_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR0_0_STATUS                                                                             0x400001
+#define regBIFPLR0_0_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR0_0_REVISION_ID                                                                        0x400002
+#define regBIFPLR0_0_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR0_0_PROG_INTERFACE                                                                     0x400002
+#define regBIFPLR0_0_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR0_0_SUB_CLASS                                                                          0x400002
+#define regBIFPLR0_0_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR0_0_BASE_CLASS                                                                         0x400002
+#define regBIFPLR0_0_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR0_0_CACHE_LINE                                                                         0x400003
+#define regBIFPLR0_0_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR0_0_LATENCY                                                                            0x400003
+#define regBIFPLR0_0_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR0_0_HEADER                                                                             0x400003
+#define regBIFPLR0_0_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR0_0_BIST                                                                               0x400003
+#define regBIFPLR0_0_BIST_BASE_IDX                                                                      5
+#define regBIFPLR0_0_SUB_BUS_NUMBER_LATENCY                                                             0x400006
+#define regBIFPLR0_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR0_0_IO_BASE_LIMIT                                                                      0x400007
+#define regBIFPLR0_0_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR0_0_SECONDARY_STATUS                                                                   0x400007
+#define regBIFPLR0_0_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR0_0_MEM_BASE_LIMIT                                                                     0x400008
+#define regBIFPLR0_0_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR0_0_PREF_BASE_LIMIT                                                                    0x400009
+#define regBIFPLR0_0_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR0_0_PREF_BASE_UPPER                                                                    0x40000a
+#define regBIFPLR0_0_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR0_0_PREF_LIMIT_UPPER                                                                   0x40000b
+#define regBIFPLR0_0_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR0_0_IO_BASE_LIMIT_HI                                                                   0x40000c
+#define regBIFPLR0_0_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR0_0_CAP_PTR                                                                            0x40000d
+#define regBIFPLR0_0_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR0_0_ROM_BASE_ADDR                                                                      0x40000e
+#define regBIFPLR0_0_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR0_0_INTERRUPT_LINE                                                                     0x40000f
+#define regBIFPLR0_0_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR0_0_INTERRUPT_PIN                                                                      0x40000f
+#define regBIFPLR0_0_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR0_0_IRQ_BRIDGE_CNTL                                                                    0x40000f
+#define regBIFPLR0_0_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR0_0_EXT_BRIDGE_CNTL                                                                    0x400010
+#define regBIFPLR0_0_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR0_0_VENDOR_CAP_LIST                                                                    0x400012
+#define regBIFPLR0_0_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR0_0_ADAPTER_ID_W                                                                       0x400013
+#define regBIFPLR0_0_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR0_0_PMI_CAP_LIST                                                                       0x400014
+#define regBIFPLR0_0_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR0_0_PMI_CAP                                                                            0x400014
+#define regBIFPLR0_0_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR0_0_PMI_STATUS_CNTL                                                                    0x400015
+#define regBIFPLR0_0_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR0_0_PCIE_CAP_LIST                                                                      0x400016
+#define regBIFPLR0_0_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR0_0_PCIE_CAP                                                                           0x400016
+#define regBIFPLR0_0_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR0_0_DEVICE_CAP                                                                         0x400017
+#define regBIFPLR0_0_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR0_0_DEVICE_CNTL                                                                        0x400018
+#define regBIFPLR0_0_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR0_0_DEVICE_STATUS                                                                      0x400018
+#define regBIFPLR0_0_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR0_0_LINK_CAP                                                                           0x400019
+#define regBIFPLR0_0_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR0_0_LINK_CNTL                                                                          0x40001a
+#define regBIFPLR0_0_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR0_0_LINK_STATUS                                                                        0x40001a
+#define regBIFPLR0_0_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR0_0_SLOT_CAP                                                                           0x40001b
+#define regBIFPLR0_0_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR0_0_SLOT_CNTL                                                                          0x40001c
+#define regBIFPLR0_0_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR0_0_SLOT_STATUS                                                                        0x40001c
+#define regBIFPLR0_0_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR0_0_ROOT_CNTL                                                                          0x40001d
+#define regBIFPLR0_0_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR0_0_ROOT_CAP                                                                           0x40001d
+#define regBIFPLR0_0_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR0_0_ROOT_STATUS                                                                        0x40001e
+#define regBIFPLR0_0_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR0_0_DEVICE_CAP2                                                                        0x40001f
+#define regBIFPLR0_0_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR0_0_DEVICE_CNTL2                                                                       0x400020
+#define regBIFPLR0_0_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR0_0_DEVICE_STATUS2                                                                     0x400020
+#define regBIFPLR0_0_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR0_0_LINK_CAP2                                                                          0x400021
+#define regBIFPLR0_0_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR0_0_LINK_CNTL2                                                                         0x400022
+#define regBIFPLR0_0_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR0_0_LINK_STATUS2                                                                       0x400022
+#define regBIFPLR0_0_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR0_0_SLOT_CAP2                                                                          0x400023
+#define regBIFPLR0_0_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR0_0_SLOT_CNTL2                                                                         0x400024
+#define regBIFPLR0_0_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR0_0_SLOT_STATUS2                                                                       0x400024
+#define regBIFPLR0_0_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR0_0_MSI_CAP_LIST                                                                       0x400028
+#define regBIFPLR0_0_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR0_0_MSI_MSG_CNTL                                                                       0x400028
+#define regBIFPLR0_0_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR0_0_MSI_MSG_ADDR_LO                                                                    0x400029
+#define regBIFPLR0_0_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR0_0_MSI_MSG_ADDR_HI                                                                    0x40002a
+#define regBIFPLR0_0_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR0_0_MSI_MSG_DATA                                                                       0x40002a
+#define regBIFPLR0_0_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR0_0_MSI_MSG_DATA_64                                                                    0x40002b
+#define regBIFPLR0_0_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR0_0_SSID_CAP_LIST                                                                      0x400030
+#define regBIFPLR0_0_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR0_0_SSID_CAP                                                                           0x400031
+#define regBIFPLR0_0_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR0_0_MSI_MAP_CAP_LIST                                                                   0x400032
+#define regBIFPLR0_0_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR0_0_MSI_MAP_CAP                                                                        0x400032
+#define regBIFPLR0_0_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x400040
+#define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR                                                           0x400041
+#define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC1                                                              0x400042
+#define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC2                                                              0x400043
+#define regBIFPLR0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR0_0_PCIE_VC_ENH_CAP_LIST                                                               0x400044
+#define regBIFPLR0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_PORT_VC_CAP_REG1                                                              0x400045
+#define regBIFPLR0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR0_0_PCIE_PORT_VC_CAP_REG2                                                              0x400046
+#define regBIFPLR0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR0_0_PCIE_PORT_VC_CNTL                                                                  0x400047
+#define regBIFPLR0_0_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR0_0_PCIE_PORT_VC_STATUS                                                                0x400047
+#define regBIFPLR0_0_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR0_0_PCIE_VC0_RESOURCE_CAP                                                              0x400048
+#define regBIFPLR0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR0_0_PCIE_VC0_RESOURCE_CNTL                                                             0x400049
+#define regBIFPLR0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR0_0_PCIE_VC0_RESOURCE_STATUS                                                           0x40004a
+#define regBIFPLR0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR0_0_PCIE_VC1_RESOURCE_CAP                                                              0x40004b
+#define regBIFPLR0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR0_0_PCIE_VC1_RESOURCE_CNTL                                                             0x40004c
+#define regBIFPLR0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR0_0_PCIE_VC1_RESOURCE_STATUS                                                           0x40004d
+#define regBIFPLR0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x400050
+#define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1                                                            0x400051
+#define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2                                                            0x400052
+#define regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x400054
+#define regBIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_UNCORR_ERR_STATUS                                                             0x400055
+#define regBIFPLR0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR0_0_PCIE_UNCORR_ERR_MASK                                                               0x400056
+#define regBIFPLR0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY                                                           0x400057
+#define regBIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR0_0_PCIE_CORR_ERR_STATUS                                                               0x400058
+#define regBIFPLR0_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_CORR_ERR_MASK                                                                 0x400059
+#define regBIFPLR0_0_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL                                                              0x40005a
+#define regBIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR0_0_PCIE_HDR_LOG0                                                                      0x40005b
+#define regBIFPLR0_0_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR0_0_PCIE_HDR_LOG1                                                                      0x40005c
+#define regBIFPLR0_0_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR0_0_PCIE_HDR_LOG2                                                                      0x40005d
+#define regBIFPLR0_0_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR0_0_PCIE_HDR_LOG3                                                                      0x40005e
+#define regBIFPLR0_0_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR0_0_PCIE_ROOT_ERR_CMD                                                                  0x40005f
+#define regBIFPLR0_0_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR0_0_PCIE_ROOT_ERR_STATUS                                                               0x400060
+#define regBIFPLR0_0_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_ERR_SRC_ID                                                                    0x400061
+#define regBIFPLR0_0_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG0                                                               0x400062
+#define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG1                                                               0x400063
+#define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG2                                                               0x400064
+#define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG3                                                               0x400065
+#define regBIFPLR0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x40009c
+#define regBIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR0_0_PCIE_LINK_CNTL3                                                                    0x40009d
+#define regBIFPLR0_0_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR0_0_PCIE_LANE_ERROR_STATUS                                                             0x40009e
+#define regBIFPLR0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x40009f
+#define regBIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x40009f
+#define regBIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x4000a0
+#define regBIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x4000a0
+#define regBIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x4000a1
+#define regBIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x4000a1
+#define regBIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x4000a2
+#define regBIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x4000a2
+#define regBIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x4000a3
+#define regBIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x4000a3
+#define regBIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x4000a4
+#define regBIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x4000a4
+#define regBIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x4000a5
+#define regBIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x4000a5
+#define regBIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x4000a6
+#define regBIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x4000a6
+#define regBIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_0_PCIE_ACS_ENH_CAP_LIST                                                              0x4000a8
+#define regBIFPLR0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR0_0_PCIE_ACS_CAP                                                                       0x4000a9
+#define regBIFPLR0_0_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR0_0_PCIE_ACS_CNTL                                                                      0x4000a9
+#define regBIFPLR0_0_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR0_0_PCIE_MC_ENH_CAP_LIST                                                               0x4000bc
+#define regBIFPLR0_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_MC_CAP                                                                        0x4000bd
+#define regBIFPLR0_0_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR0_0_PCIE_MC_CNTL                                                                       0x4000bd
+#define regBIFPLR0_0_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR0_0_PCIE_MC_ADDR0                                                                      0x4000be
+#define regBIFPLR0_0_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR0_0_PCIE_MC_ADDR1                                                                      0x4000bf
+#define regBIFPLR0_0_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR0_0_PCIE_MC_RCV0                                                                       0x4000c0
+#define regBIFPLR0_0_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR0_0_PCIE_MC_RCV1                                                                       0x4000c1
+#define regBIFPLR0_0_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR0_0_PCIE_MC_BLOCK_ALL0                                                                 0x4000c2
+#define regBIFPLR0_0_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR0_0_PCIE_MC_BLOCK_ALL1                                                                 0x4000c3
+#define regBIFPLR0_0_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x4000c4
+#define regBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x4000c5
+#define regBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR0_0_PCIE_MC_OVERLAY_BAR0                                                               0x4000c6
+#define regBIFPLR0_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_MC_OVERLAY_BAR1                                                               0x4000c7
+#define regBIFPLR0_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST                                                            0x4000dc
+#define regBIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR0_0_PCIE_L1_PM_SUB_CAP                                                                 0x4000dd
+#define regBIFPLR0_0_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR0_0_PCIE_L1_PM_SUB_CNTL                                                                0x4000de
+#define regBIFPLR0_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR0_0_PCIE_L1_PM_SUB_CNTL2                                                               0x4000df
+#define regBIFPLR0_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_DPC_ENH_CAP_LIST                                                              0x4000e0
+#define regBIFPLR0_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR0_0_PCIE_DPC_CAP_LIST                                                                  0x4000e1
+#define regBIFPLR0_0_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR0_0_PCIE_DPC_CNTL                                                                      0x4000e1
+#define regBIFPLR0_0_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR0_0_PCIE_DPC_STATUS                                                                    0x4000e2
+#define regBIFPLR0_0_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID                                                           0x4000e2
+#define regBIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR0_0_PCIE_RP_PIO_STATUS                                                                 0x4000e3
+#define regBIFPLR0_0_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR0_0_PCIE_RP_PIO_MASK                                                                   0x4000e4
+#define regBIFPLR0_0_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR0_0_PCIE_RP_PIO_SEVERITY                                                               0x4000e5
+#define regBIFPLR0_0_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_RP_PIO_SYSERROR                                                               0x4000e6
+#define regBIFPLR0_0_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_RP_PIO_EXCEPTION                                                              0x4000e7
+#define regBIFPLR0_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG0                                                               0x4000e8
+#define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG1                                                               0x4000e9
+#define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG2                                                               0x4000ea
+#define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG3                                                               0x4000eb
+#define regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0                                                            0x4000ed
+#define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1                                                            0x4000ee
+#define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2                                                            0x4000ef
+#define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3                                                            0x4000f0
+#define regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR0_0_PCIE_ESM_CAP_LIST                                                                  0x4000f1
+#define regBIFPLR0_0_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR0_0_PCIE_ESM_HEADER_1                                                                  0x4000f2
+#define regBIFPLR0_0_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR0_0_PCIE_ESM_HEADER_2                                                                  0x4000f3
+#define regBIFPLR0_0_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR0_0_PCIE_ESM_STATUS                                                                    0x4000f3
+#define regBIFPLR0_0_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR0_0_PCIE_ESM_CTRL                                                                      0x4000f4
+#define regBIFPLR0_0_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR0_0_PCIE_ESM_CAP_1                                                                     0x4000f5
+#define regBIFPLR0_0_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR0_0_PCIE_ESM_CAP_2                                                                     0x4000f6
+#define regBIFPLR0_0_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR0_0_PCIE_ESM_CAP_3                                                                     0x4000f7
+#define regBIFPLR0_0_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR0_0_PCIE_ESM_CAP_4                                                                     0x4000f8
+#define regBIFPLR0_0_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR0_0_PCIE_ESM_CAP_5                                                                     0x4000f9
+#define regBIFPLR0_0_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR0_0_PCIE_ESM_CAP_6                                                                     0x4000fa
+#define regBIFPLR0_0_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR0_0_PCIE_ESM_CAP_7                                                                     0x4000fb
+#define regBIFPLR0_0_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR0_0_PCIE_DLF_ENH_CAP_LIST                                                              0x400100
+#define regBIFPLR0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR0_0_DATA_LINK_FEATURE_CAP                                                              0x400101
+#define regBIFPLR0_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR0_0_DATA_LINK_FEATURE_STATUS                                                           0x400102
+#define regBIFPLR0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x400104
+#define regBIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR0_0_LINK_CAP_16GT                                                                      0x400105
+#define regBIFPLR0_0_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR0_0_LINK_CNTL_16GT                                                                     0x400106
+#define regBIFPLR0_0_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR0_0_LINK_STATUS_16GT                                                                   0x400107
+#define regBIFPLR0_0_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x400108
+#define regBIFPLR0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR0_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x400109
+#define regBIFPLR0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR0_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x40010a
+#define regBIFPLR0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x40010c
+#define regBIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x40010c
+#define regBIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x40010c
+#define regBIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x40010c
+#define regBIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x40010d
+#define regBIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x40010d
+#define regBIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x40010d
+#define regBIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x40010d
+#define regBIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x40010e
+#define regBIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x40010e
+#define regBIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x40010e
+#define regBIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x40010e
+#define regBIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x40010f
+#define regBIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x40010f
+#define regBIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x40010f
+#define regBIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x40010f
+#define regBIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST                                                        0x400110
+#define regBIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR0_0_MARGINING_PORT_CAP                                                                 0x400111
+#define regBIFPLR0_0_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR0_0_MARGINING_PORT_STATUS                                                              0x400111
+#define regBIFPLR0_0_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR0_0_LANE_0_MARGINING_LANE_CNTL                                                         0x400112
+#define regBIFPLR0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_0_LANE_0_MARGINING_LANE_STATUS                                                       0x400112
+#define regBIFPLR0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_0_LANE_1_MARGINING_LANE_CNTL                                                         0x400113
+#define regBIFPLR0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_0_LANE_1_MARGINING_LANE_STATUS                                                       0x400113
+#define regBIFPLR0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_0_LANE_2_MARGINING_LANE_CNTL                                                         0x400114
+#define regBIFPLR0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_0_LANE_2_MARGINING_LANE_STATUS                                                       0x400114
+#define regBIFPLR0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_0_LANE_3_MARGINING_LANE_CNTL                                                         0x400115
+#define regBIFPLR0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_0_LANE_3_MARGINING_LANE_STATUS                                                       0x400115
+#define regBIFPLR0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_0_LANE_4_MARGINING_LANE_CNTL                                                         0x400116
+#define regBIFPLR0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_0_LANE_4_MARGINING_LANE_STATUS                                                       0x400116
+#define regBIFPLR0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_0_LANE_5_MARGINING_LANE_CNTL                                                         0x400117
+#define regBIFPLR0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_0_LANE_5_MARGINING_LANE_STATUS                                                       0x400117
+#define regBIFPLR0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_0_LANE_6_MARGINING_LANE_CNTL                                                         0x400118
+#define regBIFPLR0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_0_LANE_6_MARGINING_LANE_STATUS                                                       0x400118
+#define regBIFPLR0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_0_LANE_7_MARGINING_LANE_CNTL                                                         0x400119
+#define regBIFPLR0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_0_LANE_7_MARGINING_LANE_STATUS                                                       0x400119
+#define regBIFPLR0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_0_LANE_8_MARGINING_LANE_CNTL                                                         0x40011a
+#define regBIFPLR0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_0_LANE_8_MARGINING_LANE_STATUS                                                       0x40011a
+#define regBIFPLR0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_0_LANE_9_MARGINING_LANE_CNTL                                                         0x40011b
+#define regBIFPLR0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_0_LANE_9_MARGINING_LANE_STATUS                                                       0x40011b
+#define regBIFPLR0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_0_LANE_10_MARGINING_LANE_CNTL                                                        0x40011c
+#define regBIFPLR0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_0_LANE_10_MARGINING_LANE_STATUS                                                      0x40011c
+#define regBIFPLR0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_11_MARGINING_LANE_CNTL                                                        0x40011d
+#define regBIFPLR0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_0_LANE_11_MARGINING_LANE_STATUS                                                      0x40011d
+#define regBIFPLR0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_12_MARGINING_LANE_CNTL                                                        0x40011e
+#define regBIFPLR0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_0_LANE_12_MARGINING_LANE_STATUS                                                      0x40011e
+#define regBIFPLR0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_13_MARGINING_LANE_CNTL                                                        0x40011f
+#define regBIFPLR0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_0_LANE_13_MARGINING_LANE_STATUS                                                      0x40011f
+#define regBIFPLR0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_14_MARGINING_LANE_CNTL                                                        0x400120
+#define regBIFPLR0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_0_LANE_14_MARGINING_LANE_STATUS                                                      0x400120
+#define regBIFPLR0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_0_LANE_15_MARGINING_LANE_CNTL                                                        0x400121
+#define regBIFPLR0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_0_LANE_15_MARGINING_LANE_STATUS                                                      0x400121
+#define regBIFPLR0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_0_PCIE_CCIX_CAP_LIST                                                                 0x400122
+#define regBIFPLR0_0_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR0_0_PCIE_CCIX_HEADER_1                                                                 0x400123
+#define regBIFPLR0_0_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR0_0_PCIE_CCIX_HEADER_2                                                                 0x400124
+#define regBIFPLR0_0_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR0_0_PCIE_CCIX_CAP                                                                      0x400124
+#define regBIFPLR0_0_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP                                                             0x400125
+#define regBIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR0_0_PCIE_CCIX_ESM_OPTL_CAP                                                             0x400126
+#define regBIFPLR0_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR0_0_PCIE_CCIX_ESM_STATUS                                                               0x400127
+#define regBIFPLR0_0_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR0_0_PCIE_CCIX_ESM_CNTL                                                                 0x400128
+#define regBIFPLR0_0_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x400129
+#define regBIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x400129
+#define regBIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x400129
+#define regBIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x400129
+#define regBIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x40012a
+#define regBIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x40012a
+#define regBIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x40012a
+#define regBIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x40012a
+#define regBIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x40012b
+#define regBIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x40012b
+#define regBIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x40012b
+#define regBIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x40012b
+#define regBIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x40012c
+#define regBIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x40012c
+#define regBIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x40012c
+#define regBIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x40012c
+#define regBIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x40012d
+#define regBIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x40012d
+#define regBIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x40012d
+#define regBIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x40012d
+#define regBIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x40012e
+#define regBIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x40012e
+#define regBIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x40012e
+#define regBIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x40012e
+#define regBIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x40012f
+#define regBIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x40012f
+#define regBIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x40012f
+#define regBIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x40012f
+#define regBIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x400130
+#define regBIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x400130
+#define regBIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x400130
+#define regBIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x400130
+#define regBIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_0_PCIE_CCIX_TRANS_CAP                                                                0x400131
+#define regBIFPLR0_0_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR0_0_PCIE_CCIX_TRANS_CNTL                                                               0x400132
+#define regBIFPLR0_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+// base address: 0x11101000
+#define regBIFPLR1_0_VENDOR_ID                                                                          0x400400
+#define regBIFPLR1_0_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR1_0_DEVICE_ID                                                                          0x400400
+#define regBIFPLR1_0_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR1_0_COMMAND                                                                            0x400401
+#define regBIFPLR1_0_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR1_0_STATUS                                                                             0x400401
+#define regBIFPLR1_0_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR1_0_REVISION_ID                                                                        0x400402
+#define regBIFPLR1_0_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR1_0_PROG_INTERFACE                                                                     0x400402
+#define regBIFPLR1_0_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR1_0_SUB_CLASS                                                                          0x400402
+#define regBIFPLR1_0_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR1_0_BASE_CLASS                                                                         0x400402
+#define regBIFPLR1_0_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR1_0_CACHE_LINE                                                                         0x400403
+#define regBIFPLR1_0_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR1_0_LATENCY                                                                            0x400403
+#define regBIFPLR1_0_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR1_0_HEADER                                                                             0x400403
+#define regBIFPLR1_0_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR1_0_BIST                                                                               0x400403
+#define regBIFPLR1_0_BIST_BASE_IDX                                                                      5
+#define regBIFPLR1_0_SUB_BUS_NUMBER_LATENCY                                                             0x400406
+#define regBIFPLR1_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR1_0_IO_BASE_LIMIT                                                                      0x400407
+#define regBIFPLR1_0_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR1_0_SECONDARY_STATUS                                                                   0x400407
+#define regBIFPLR1_0_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR1_0_MEM_BASE_LIMIT                                                                     0x400408
+#define regBIFPLR1_0_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR1_0_PREF_BASE_LIMIT                                                                    0x400409
+#define regBIFPLR1_0_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR1_0_PREF_BASE_UPPER                                                                    0x40040a
+#define regBIFPLR1_0_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR1_0_PREF_LIMIT_UPPER                                                                   0x40040b
+#define regBIFPLR1_0_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR1_0_IO_BASE_LIMIT_HI                                                                   0x40040c
+#define regBIFPLR1_0_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR1_0_CAP_PTR                                                                            0x40040d
+#define regBIFPLR1_0_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR1_0_ROM_BASE_ADDR                                                                      0x40040e
+#define regBIFPLR1_0_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR1_0_INTERRUPT_LINE                                                                     0x40040f
+#define regBIFPLR1_0_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR1_0_INTERRUPT_PIN                                                                      0x40040f
+#define regBIFPLR1_0_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR1_0_IRQ_BRIDGE_CNTL                                                                    0x40040f
+#define regBIFPLR1_0_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR1_0_EXT_BRIDGE_CNTL                                                                    0x400410
+#define regBIFPLR1_0_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR1_0_VENDOR_CAP_LIST                                                                    0x400412
+#define regBIFPLR1_0_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR1_0_ADAPTER_ID_W                                                                       0x400413
+#define regBIFPLR1_0_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR1_0_PMI_CAP_LIST                                                                       0x400414
+#define regBIFPLR1_0_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR1_0_PMI_CAP                                                                            0x400414
+#define regBIFPLR1_0_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR1_0_PMI_STATUS_CNTL                                                                    0x400415
+#define regBIFPLR1_0_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR1_0_PCIE_CAP_LIST                                                                      0x400416
+#define regBIFPLR1_0_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR1_0_PCIE_CAP                                                                           0x400416
+#define regBIFPLR1_0_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR1_0_DEVICE_CAP                                                                         0x400417
+#define regBIFPLR1_0_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR1_0_DEVICE_CNTL                                                                        0x400418
+#define regBIFPLR1_0_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR1_0_DEVICE_STATUS                                                                      0x400418
+#define regBIFPLR1_0_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR1_0_LINK_CAP                                                                           0x400419
+#define regBIFPLR1_0_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR1_0_LINK_CNTL                                                                          0x40041a
+#define regBIFPLR1_0_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR1_0_LINK_STATUS                                                                        0x40041a
+#define regBIFPLR1_0_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR1_0_SLOT_CAP                                                                           0x40041b
+#define regBIFPLR1_0_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR1_0_SLOT_CNTL                                                                          0x40041c
+#define regBIFPLR1_0_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR1_0_SLOT_STATUS                                                                        0x40041c
+#define regBIFPLR1_0_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR1_0_ROOT_CNTL                                                                          0x40041d
+#define regBIFPLR1_0_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR1_0_ROOT_CAP                                                                           0x40041d
+#define regBIFPLR1_0_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR1_0_ROOT_STATUS                                                                        0x40041e
+#define regBIFPLR1_0_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR1_0_DEVICE_CAP2                                                                        0x40041f
+#define regBIFPLR1_0_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR1_0_DEVICE_CNTL2                                                                       0x400420
+#define regBIFPLR1_0_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR1_0_DEVICE_STATUS2                                                                     0x400420
+#define regBIFPLR1_0_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR1_0_LINK_CAP2                                                                          0x400421
+#define regBIFPLR1_0_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR1_0_LINK_CNTL2                                                                         0x400422
+#define regBIFPLR1_0_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR1_0_LINK_STATUS2                                                                       0x400422
+#define regBIFPLR1_0_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR1_0_SLOT_CAP2                                                                          0x400423
+#define regBIFPLR1_0_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR1_0_SLOT_CNTL2                                                                         0x400424
+#define regBIFPLR1_0_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR1_0_SLOT_STATUS2                                                                       0x400424
+#define regBIFPLR1_0_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR1_0_MSI_CAP_LIST                                                                       0x400428
+#define regBIFPLR1_0_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR1_0_MSI_MSG_CNTL                                                                       0x400428
+#define regBIFPLR1_0_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR1_0_MSI_MSG_ADDR_LO                                                                    0x400429
+#define regBIFPLR1_0_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR1_0_MSI_MSG_ADDR_HI                                                                    0x40042a
+#define regBIFPLR1_0_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR1_0_MSI_MSG_DATA                                                                       0x40042a
+#define regBIFPLR1_0_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR1_0_MSI_MSG_DATA_64                                                                    0x40042b
+#define regBIFPLR1_0_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR1_0_SSID_CAP_LIST                                                                      0x400430
+#define regBIFPLR1_0_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR1_0_SSID_CAP                                                                           0x400431
+#define regBIFPLR1_0_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR1_0_MSI_MAP_CAP_LIST                                                                   0x400432
+#define regBIFPLR1_0_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR1_0_MSI_MAP_CAP                                                                        0x400432
+#define regBIFPLR1_0_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x400440
+#define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR                                                           0x400441
+#define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC1                                                              0x400442
+#define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC2                                                              0x400443
+#define regBIFPLR1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR1_0_PCIE_VC_ENH_CAP_LIST                                                               0x400444
+#define regBIFPLR1_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_PORT_VC_CAP_REG1                                                              0x400445
+#define regBIFPLR1_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR1_0_PCIE_PORT_VC_CAP_REG2                                                              0x400446
+#define regBIFPLR1_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR1_0_PCIE_PORT_VC_CNTL                                                                  0x400447
+#define regBIFPLR1_0_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR1_0_PCIE_PORT_VC_STATUS                                                                0x400447
+#define regBIFPLR1_0_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR1_0_PCIE_VC0_RESOURCE_CAP                                                              0x400448
+#define regBIFPLR1_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR1_0_PCIE_VC0_RESOURCE_CNTL                                                             0x400449
+#define regBIFPLR1_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR1_0_PCIE_VC0_RESOURCE_STATUS                                                           0x40044a
+#define regBIFPLR1_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR1_0_PCIE_VC1_RESOURCE_CAP                                                              0x40044b
+#define regBIFPLR1_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR1_0_PCIE_VC1_RESOURCE_CNTL                                                             0x40044c
+#define regBIFPLR1_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR1_0_PCIE_VC1_RESOURCE_STATUS                                                           0x40044d
+#define regBIFPLR1_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x400450
+#define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1                                                            0x400451
+#define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2                                                            0x400452
+#define regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x400454
+#define regBIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_UNCORR_ERR_STATUS                                                             0x400455
+#define regBIFPLR1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR1_0_PCIE_UNCORR_ERR_MASK                                                               0x400456
+#define regBIFPLR1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY                                                           0x400457
+#define regBIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR1_0_PCIE_CORR_ERR_STATUS                                                               0x400458
+#define regBIFPLR1_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_CORR_ERR_MASK                                                                 0x400459
+#define regBIFPLR1_0_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL                                                              0x40045a
+#define regBIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR1_0_PCIE_HDR_LOG0                                                                      0x40045b
+#define regBIFPLR1_0_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR1_0_PCIE_HDR_LOG1                                                                      0x40045c
+#define regBIFPLR1_0_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR1_0_PCIE_HDR_LOG2                                                                      0x40045d
+#define regBIFPLR1_0_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR1_0_PCIE_HDR_LOG3                                                                      0x40045e
+#define regBIFPLR1_0_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR1_0_PCIE_ROOT_ERR_CMD                                                                  0x40045f
+#define regBIFPLR1_0_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR1_0_PCIE_ROOT_ERR_STATUS                                                               0x400460
+#define regBIFPLR1_0_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_ERR_SRC_ID                                                                    0x400461
+#define regBIFPLR1_0_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG0                                                               0x400462
+#define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG1                                                               0x400463
+#define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG2                                                               0x400464
+#define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG3                                                               0x400465
+#define regBIFPLR1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x40049c
+#define regBIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR1_0_PCIE_LINK_CNTL3                                                                    0x40049d
+#define regBIFPLR1_0_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR1_0_PCIE_LANE_ERROR_STATUS                                                             0x40049e
+#define regBIFPLR1_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x40049f
+#define regBIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x40049f
+#define regBIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x4004a0
+#define regBIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x4004a0
+#define regBIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x4004a1
+#define regBIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x4004a1
+#define regBIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x4004a2
+#define regBIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x4004a2
+#define regBIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x4004a3
+#define regBIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x4004a3
+#define regBIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x4004a4
+#define regBIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x4004a4
+#define regBIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x4004a5
+#define regBIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x4004a5
+#define regBIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x4004a6
+#define regBIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x4004a6
+#define regBIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_0_PCIE_ACS_ENH_CAP_LIST                                                              0x4004a8
+#define regBIFPLR1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR1_0_PCIE_ACS_CAP                                                                       0x4004a9
+#define regBIFPLR1_0_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR1_0_PCIE_ACS_CNTL                                                                      0x4004a9
+#define regBIFPLR1_0_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR1_0_PCIE_MC_ENH_CAP_LIST                                                               0x4004bc
+#define regBIFPLR1_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_MC_CAP                                                                        0x4004bd
+#define regBIFPLR1_0_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR1_0_PCIE_MC_CNTL                                                                       0x4004bd
+#define regBIFPLR1_0_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR1_0_PCIE_MC_ADDR0                                                                      0x4004be
+#define regBIFPLR1_0_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR1_0_PCIE_MC_ADDR1                                                                      0x4004bf
+#define regBIFPLR1_0_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR1_0_PCIE_MC_RCV0                                                                       0x4004c0
+#define regBIFPLR1_0_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR1_0_PCIE_MC_RCV1                                                                       0x4004c1
+#define regBIFPLR1_0_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR1_0_PCIE_MC_BLOCK_ALL0                                                                 0x4004c2
+#define regBIFPLR1_0_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR1_0_PCIE_MC_BLOCK_ALL1                                                                 0x4004c3
+#define regBIFPLR1_0_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x4004c4
+#define regBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x4004c5
+#define regBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR1_0_PCIE_MC_OVERLAY_BAR0                                                               0x4004c6
+#define regBIFPLR1_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_MC_OVERLAY_BAR1                                                               0x4004c7
+#define regBIFPLR1_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST                                                            0x4004dc
+#define regBIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR1_0_PCIE_L1_PM_SUB_CAP                                                                 0x4004dd
+#define regBIFPLR1_0_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR1_0_PCIE_L1_PM_SUB_CNTL                                                                0x4004de
+#define regBIFPLR1_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR1_0_PCIE_L1_PM_SUB_CNTL2                                                               0x4004df
+#define regBIFPLR1_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_DPC_ENH_CAP_LIST                                                              0x4004e0
+#define regBIFPLR1_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR1_0_PCIE_DPC_CAP_LIST                                                                  0x4004e1
+#define regBIFPLR1_0_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR1_0_PCIE_DPC_CNTL                                                                      0x4004e1
+#define regBIFPLR1_0_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR1_0_PCIE_DPC_STATUS                                                                    0x4004e2
+#define regBIFPLR1_0_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID                                                           0x4004e2
+#define regBIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR1_0_PCIE_RP_PIO_STATUS                                                                 0x4004e3
+#define regBIFPLR1_0_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR1_0_PCIE_RP_PIO_MASK                                                                   0x4004e4
+#define regBIFPLR1_0_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR1_0_PCIE_RP_PIO_SEVERITY                                                               0x4004e5
+#define regBIFPLR1_0_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_RP_PIO_SYSERROR                                                               0x4004e6
+#define regBIFPLR1_0_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_RP_PIO_EXCEPTION                                                              0x4004e7
+#define regBIFPLR1_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG0                                                               0x4004e8
+#define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG1                                                               0x4004e9
+#define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG2                                                               0x4004ea
+#define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG3                                                               0x4004eb
+#define regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0                                                            0x4004ed
+#define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1                                                            0x4004ee
+#define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2                                                            0x4004ef
+#define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3                                                            0x4004f0
+#define regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR1_0_PCIE_ESM_CAP_LIST                                                                  0x4004f1
+#define regBIFPLR1_0_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR1_0_PCIE_ESM_HEADER_1                                                                  0x4004f2
+#define regBIFPLR1_0_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR1_0_PCIE_ESM_HEADER_2                                                                  0x4004f3
+#define regBIFPLR1_0_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR1_0_PCIE_ESM_STATUS                                                                    0x4004f3
+#define regBIFPLR1_0_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR1_0_PCIE_ESM_CTRL                                                                      0x4004f4
+#define regBIFPLR1_0_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR1_0_PCIE_ESM_CAP_1                                                                     0x4004f5
+#define regBIFPLR1_0_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR1_0_PCIE_ESM_CAP_2                                                                     0x4004f6
+#define regBIFPLR1_0_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR1_0_PCIE_ESM_CAP_3                                                                     0x4004f7
+#define regBIFPLR1_0_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR1_0_PCIE_ESM_CAP_4                                                                     0x4004f8
+#define regBIFPLR1_0_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR1_0_PCIE_ESM_CAP_5                                                                     0x4004f9
+#define regBIFPLR1_0_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR1_0_PCIE_ESM_CAP_6                                                                     0x4004fa
+#define regBIFPLR1_0_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR1_0_PCIE_ESM_CAP_7                                                                     0x4004fb
+#define regBIFPLR1_0_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR1_0_PCIE_DLF_ENH_CAP_LIST                                                              0x400500
+#define regBIFPLR1_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR1_0_DATA_LINK_FEATURE_CAP                                                              0x400501
+#define regBIFPLR1_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR1_0_DATA_LINK_FEATURE_STATUS                                                           0x400502
+#define regBIFPLR1_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x400504
+#define regBIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR1_0_LINK_CAP_16GT                                                                      0x400505
+#define regBIFPLR1_0_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR1_0_LINK_CNTL_16GT                                                                     0x400506
+#define regBIFPLR1_0_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR1_0_LINK_STATUS_16GT                                                                   0x400507
+#define regBIFPLR1_0_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x400508
+#define regBIFPLR1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR1_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x400509
+#define regBIFPLR1_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR1_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x40050a
+#define regBIFPLR1_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x40050c
+#define regBIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x40050c
+#define regBIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x40050c
+#define regBIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x40050c
+#define regBIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x40050d
+#define regBIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x40050d
+#define regBIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x40050d
+#define regBIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x40050d
+#define regBIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x40050e
+#define regBIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x40050e
+#define regBIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x40050e
+#define regBIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x40050e
+#define regBIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x40050f
+#define regBIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x40050f
+#define regBIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x40050f
+#define regBIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x40050f
+#define regBIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST                                                        0x400510
+#define regBIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR1_0_MARGINING_PORT_CAP                                                                 0x400511
+#define regBIFPLR1_0_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR1_0_MARGINING_PORT_STATUS                                                              0x400511
+#define regBIFPLR1_0_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR1_0_LANE_0_MARGINING_LANE_CNTL                                                         0x400512
+#define regBIFPLR1_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_0_LANE_0_MARGINING_LANE_STATUS                                                       0x400512
+#define regBIFPLR1_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_0_LANE_1_MARGINING_LANE_CNTL                                                         0x400513
+#define regBIFPLR1_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_0_LANE_1_MARGINING_LANE_STATUS                                                       0x400513
+#define regBIFPLR1_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_0_LANE_2_MARGINING_LANE_CNTL                                                         0x400514
+#define regBIFPLR1_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_0_LANE_2_MARGINING_LANE_STATUS                                                       0x400514
+#define regBIFPLR1_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_0_LANE_3_MARGINING_LANE_CNTL                                                         0x400515
+#define regBIFPLR1_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_0_LANE_3_MARGINING_LANE_STATUS                                                       0x400515
+#define regBIFPLR1_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_0_LANE_4_MARGINING_LANE_CNTL                                                         0x400516
+#define regBIFPLR1_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_0_LANE_4_MARGINING_LANE_STATUS                                                       0x400516
+#define regBIFPLR1_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_0_LANE_5_MARGINING_LANE_CNTL                                                         0x400517
+#define regBIFPLR1_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_0_LANE_5_MARGINING_LANE_STATUS                                                       0x400517
+#define regBIFPLR1_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_0_LANE_6_MARGINING_LANE_CNTL                                                         0x400518
+#define regBIFPLR1_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_0_LANE_6_MARGINING_LANE_STATUS                                                       0x400518
+#define regBIFPLR1_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_0_LANE_7_MARGINING_LANE_CNTL                                                         0x400519
+#define regBIFPLR1_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_0_LANE_7_MARGINING_LANE_STATUS                                                       0x400519
+#define regBIFPLR1_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_0_LANE_8_MARGINING_LANE_CNTL                                                         0x40051a
+#define regBIFPLR1_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_0_LANE_8_MARGINING_LANE_STATUS                                                       0x40051a
+#define regBIFPLR1_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_0_LANE_9_MARGINING_LANE_CNTL                                                         0x40051b
+#define regBIFPLR1_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_0_LANE_9_MARGINING_LANE_STATUS                                                       0x40051b
+#define regBIFPLR1_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_0_LANE_10_MARGINING_LANE_CNTL                                                        0x40051c
+#define regBIFPLR1_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_0_LANE_10_MARGINING_LANE_STATUS                                                      0x40051c
+#define regBIFPLR1_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_11_MARGINING_LANE_CNTL                                                        0x40051d
+#define regBIFPLR1_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_0_LANE_11_MARGINING_LANE_STATUS                                                      0x40051d
+#define regBIFPLR1_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_12_MARGINING_LANE_CNTL                                                        0x40051e
+#define regBIFPLR1_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_0_LANE_12_MARGINING_LANE_STATUS                                                      0x40051e
+#define regBIFPLR1_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_13_MARGINING_LANE_CNTL                                                        0x40051f
+#define regBIFPLR1_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_0_LANE_13_MARGINING_LANE_STATUS                                                      0x40051f
+#define regBIFPLR1_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_14_MARGINING_LANE_CNTL                                                        0x400520
+#define regBIFPLR1_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_0_LANE_14_MARGINING_LANE_STATUS                                                      0x400520
+#define regBIFPLR1_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_0_LANE_15_MARGINING_LANE_CNTL                                                        0x400521
+#define regBIFPLR1_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_0_LANE_15_MARGINING_LANE_STATUS                                                      0x400521
+#define regBIFPLR1_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_0_PCIE_CCIX_CAP_LIST                                                                 0x400522
+#define regBIFPLR1_0_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR1_0_PCIE_CCIX_HEADER_1                                                                 0x400523
+#define regBIFPLR1_0_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR1_0_PCIE_CCIX_HEADER_2                                                                 0x400524
+#define regBIFPLR1_0_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR1_0_PCIE_CCIX_CAP                                                                      0x400524
+#define regBIFPLR1_0_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP                                                             0x400525
+#define regBIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR1_0_PCIE_CCIX_ESM_OPTL_CAP                                                             0x400526
+#define regBIFPLR1_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR1_0_PCIE_CCIX_ESM_STATUS                                                               0x400527
+#define regBIFPLR1_0_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR1_0_PCIE_CCIX_ESM_CNTL                                                                 0x400528
+#define regBIFPLR1_0_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x400529
+#define regBIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x400529
+#define regBIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x400529
+#define regBIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x400529
+#define regBIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x40052a
+#define regBIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x40052a
+#define regBIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x40052a
+#define regBIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x40052a
+#define regBIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x40052b
+#define regBIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x40052b
+#define regBIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x40052b
+#define regBIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x40052b
+#define regBIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x40052c
+#define regBIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x40052c
+#define regBIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x40052c
+#define regBIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x40052c
+#define regBIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x40052d
+#define regBIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x40052d
+#define regBIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x40052d
+#define regBIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x40052d
+#define regBIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x40052e
+#define regBIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x40052e
+#define regBIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x40052e
+#define regBIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x40052e
+#define regBIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x40052f
+#define regBIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x40052f
+#define regBIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x40052f
+#define regBIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x40052f
+#define regBIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x400530
+#define regBIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x400530
+#define regBIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x400530
+#define regBIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x400530
+#define regBIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_0_PCIE_CCIX_TRANS_CAP                                                                0x400531
+#define regBIFPLR1_0_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR1_0_PCIE_CCIX_TRANS_CNTL                                                               0x400532
+#define regBIFPLR1_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+// base address: 0x11102000
+#define regBIFPLR2_0_VENDOR_ID                                                                          0x400800
+#define regBIFPLR2_0_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR2_0_DEVICE_ID                                                                          0x400800
+#define regBIFPLR2_0_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR2_0_COMMAND                                                                            0x400801
+#define regBIFPLR2_0_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR2_0_STATUS                                                                             0x400801
+#define regBIFPLR2_0_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR2_0_REVISION_ID                                                                        0x400802
+#define regBIFPLR2_0_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR2_0_PROG_INTERFACE                                                                     0x400802
+#define regBIFPLR2_0_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR2_0_SUB_CLASS                                                                          0x400802
+#define regBIFPLR2_0_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR2_0_BASE_CLASS                                                                         0x400802
+#define regBIFPLR2_0_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR2_0_CACHE_LINE                                                                         0x400803
+#define regBIFPLR2_0_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR2_0_LATENCY                                                                            0x400803
+#define regBIFPLR2_0_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR2_0_HEADER                                                                             0x400803
+#define regBIFPLR2_0_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR2_0_BIST                                                                               0x400803
+#define regBIFPLR2_0_BIST_BASE_IDX                                                                      5
+#define regBIFPLR2_0_SUB_BUS_NUMBER_LATENCY                                                             0x400806
+#define regBIFPLR2_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR2_0_IO_BASE_LIMIT                                                                      0x400807
+#define regBIFPLR2_0_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR2_0_SECONDARY_STATUS                                                                   0x400807
+#define regBIFPLR2_0_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR2_0_MEM_BASE_LIMIT                                                                     0x400808
+#define regBIFPLR2_0_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR2_0_PREF_BASE_LIMIT                                                                    0x400809
+#define regBIFPLR2_0_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR2_0_PREF_BASE_UPPER                                                                    0x40080a
+#define regBIFPLR2_0_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR2_0_PREF_LIMIT_UPPER                                                                   0x40080b
+#define regBIFPLR2_0_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR2_0_IO_BASE_LIMIT_HI                                                                   0x40080c
+#define regBIFPLR2_0_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR2_0_CAP_PTR                                                                            0x40080d
+#define regBIFPLR2_0_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR2_0_ROM_BASE_ADDR                                                                      0x40080e
+#define regBIFPLR2_0_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR2_0_INTERRUPT_LINE                                                                     0x40080f
+#define regBIFPLR2_0_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR2_0_INTERRUPT_PIN                                                                      0x40080f
+#define regBIFPLR2_0_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR2_0_IRQ_BRIDGE_CNTL                                                                    0x40080f
+#define regBIFPLR2_0_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR2_0_EXT_BRIDGE_CNTL                                                                    0x400810
+#define regBIFPLR2_0_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR2_0_VENDOR_CAP_LIST                                                                    0x400812
+#define regBIFPLR2_0_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR2_0_ADAPTER_ID_W                                                                       0x400813
+#define regBIFPLR2_0_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR2_0_PMI_CAP_LIST                                                                       0x400814
+#define regBIFPLR2_0_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR2_0_PMI_CAP                                                                            0x400814
+#define regBIFPLR2_0_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR2_0_PMI_STATUS_CNTL                                                                    0x400815
+#define regBIFPLR2_0_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR2_0_PCIE_CAP_LIST                                                                      0x400816
+#define regBIFPLR2_0_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR2_0_PCIE_CAP                                                                           0x400816
+#define regBIFPLR2_0_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR2_0_DEVICE_CAP                                                                         0x400817
+#define regBIFPLR2_0_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR2_0_DEVICE_CNTL                                                                        0x400818
+#define regBIFPLR2_0_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR2_0_DEVICE_STATUS                                                                      0x400818
+#define regBIFPLR2_0_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR2_0_LINK_CAP                                                                           0x400819
+#define regBIFPLR2_0_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR2_0_LINK_CNTL                                                                          0x40081a
+#define regBIFPLR2_0_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR2_0_LINK_STATUS                                                                        0x40081a
+#define regBIFPLR2_0_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR2_0_SLOT_CAP                                                                           0x40081b
+#define regBIFPLR2_0_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR2_0_SLOT_CNTL                                                                          0x40081c
+#define regBIFPLR2_0_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR2_0_SLOT_STATUS                                                                        0x40081c
+#define regBIFPLR2_0_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR2_0_ROOT_CNTL                                                                          0x40081d
+#define regBIFPLR2_0_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR2_0_ROOT_CAP                                                                           0x40081d
+#define regBIFPLR2_0_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR2_0_ROOT_STATUS                                                                        0x40081e
+#define regBIFPLR2_0_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR2_0_DEVICE_CAP2                                                                        0x40081f
+#define regBIFPLR2_0_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR2_0_DEVICE_CNTL2                                                                       0x400820
+#define regBIFPLR2_0_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR2_0_DEVICE_STATUS2                                                                     0x400820
+#define regBIFPLR2_0_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR2_0_LINK_CAP2                                                                          0x400821
+#define regBIFPLR2_0_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR2_0_LINK_CNTL2                                                                         0x400822
+#define regBIFPLR2_0_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR2_0_LINK_STATUS2                                                                       0x400822
+#define regBIFPLR2_0_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR2_0_SLOT_CAP2                                                                          0x400823
+#define regBIFPLR2_0_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR2_0_SLOT_CNTL2                                                                         0x400824
+#define regBIFPLR2_0_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR2_0_SLOT_STATUS2                                                                       0x400824
+#define regBIFPLR2_0_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR2_0_MSI_CAP_LIST                                                                       0x400828
+#define regBIFPLR2_0_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR2_0_MSI_MSG_CNTL                                                                       0x400828
+#define regBIFPLR2_0_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR2_0_MSI_MSG_ADDR_LO                                                                    0x400829
+#define regBIFPLR2_0_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR2_0_MSI_MSG_ADDR_HI                                                                    0x40082a
+#define regBIFPLR2_0_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR2_0_MSI_MSG_DATA                                                                       0x40082a
+#define regBIFPLR2_0_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR2_0_MSI_MSG_DATA_64                                                                    0x40082b
+#define regBIFPLR2_0_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR2_0_SSID_CAP_LIST                                                                      0x400830
+#define regBIFPLR2_0_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR2_0_SSID_CAP                                                                           0x400831
+#define regBIFPLR2_0_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR2_0_MSI_MAP_CAP_LIST                                                                   0x400832
+#define regBIFPLR2_0_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR2_0_MSI_MAP_CAP                                                                        0x400832
+#define regBIFPLR2_0_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x400840
+#define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR                                                           0x400841
+#define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC1                                                              0x400842
+#define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC2                                                              0x400843
+#define regBIFPLR2_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR2_0_PCIE_VC_ENH_CAP_LIST                                                               0x400844
+#define regBIFPLR2_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_PORT_VC_CAP_REG1                                                              0x400845
+#define regBIFPLR2_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR2_0_PCIE_PORT_VC_CAP_REG2                                                              0x400846
+#define regBIFPLR2_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR2_0_PCIE_PORT_VC_CNTL                                                                  0x400847
+#define regBIFPLR2_0_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR2_0_PCIE_PORT_VC_STATUS                                                                0x400847
+#define regBIFPLR2_0_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR2_0_PCIE_VC0_RESOURCE_CAP                                                              0x400848
+#define regBIFPLR2_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR2_0_PCIE_VC0_RESOURCE_CNTL                                                             0x400849
+#define regBIFPLR2_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR2_0_PCIE_VC0_RESOURCE_STATUS                                                           0x40084a
+#define regBIFPLR2_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR2_0_PCIE_VC1_RESOURCE_CAP                                                              0x40084b
+#define regBIFPLR2_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR2_0_PCIE_VC1_RESOURCE_CNTL                                                             0x40084c
+#define regBIFPLR2_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR2_0_PCIE_VC1_RESOURCE_STATUS                                                           0x40084d
+#define regBIFPLR2_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x400850
+#define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1                                                            0x400851
+#define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2                                                            0x400852
+#define regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x400854
+#define regBIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_UNCORR_ERR_STATUS                                                             0x400855
+#define regBIFPLR2_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR2_0_PCIE_UNCORR_ERR_MASK                                                               0x400856
+#define regBIFPLR2_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY                                                           0x400857
+#define regBIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR2_0_PCIE_CORR_ERR_STATUS                                                               0x400858
+#define regBIFPLR2_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_CORR_ERR_MASK                                                                 0x400859
+#define regBIFPLR2_0_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL                                                              0x40085a
+#define regBIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR2_0_PCIE_HDR_LOG0                                                                      0x40085b
+#define regBIFPLR2_0_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR2_0_PCIE_HDR_LOG1                                                                      0x40085c
+#define regBIFPLR2_0_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR2_0_PCIE_HDR_LOG2                                                                      0x40085d
+#define regBIFPLR2_0_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR2_0_PCIE_HDR_LOG3                                                                      0x40085e
+#define regBIFPLR2_0_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR2_0_PCIE_ROOT_ERR_CMD                                                                  0x40085f
+#define regBIFPLR2_0_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR2_0_PCIE_ROOT_ERR_STATUS                                                               0x400860
+#define regBIFPLR2_0_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_ERR_SRC_ID                                                                    0x400861
+#define regBIFPLR2_0_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG0                                                               0x400862
+#define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG1                                                               0x400863
+#define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG2                                                               0x400864
+#define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG3                                                               0x400865
+#define regBIFPLR2_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x40089c
+#define regBIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR2_0_PCIE_LINK_CNTL3                                                                    0x40089d
+#define regBIFPLR2_0_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR2_0_PCIE_LANE_ERROR_STATUS                                                             0x40089e
+#define regBIFPLR2_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x40089f
+#define regBIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x40089f
+#define regBIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x4008a0
+#define regBIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x4008a0
+#define regBIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x4008a1
+#define regBIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x4008a1
+#define regBIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x4008a2
+#define regBIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x4008a2
+#define regBIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x4008a3
+#define regBIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x4008a3
+#define regBIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x4008a4
+#define regBIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x4008a4
+#define regBIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x4008a5
+#define regBIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x4008a5
+#define regBIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x4008a6
+#define regBIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x4008a6
+#define regBIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_0_PCIE_ACS_ENH_CAP_LIST                                                              0x4008a8
+#define regBIFPLR2_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR2_0_PCIE_ACS_CAP                                                                       0x4008a9
+#define regBIFPLR2_0_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR2_0_PCIE_ACS_CNTL                                                                      0x4008a9
+#define regBIFPLR2_0_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR2_0_PCIE_MC_ENH_CAP_LIST                                                               0x4008bc
+#define regBIFPLR2_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_MC_CAP                                                                        0x4008bd
+#define regBIFPLR2_0_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR2_0_PCIE_MC_CNTL                                                                       0x4008bd
+#define regBIFPLR2_0_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR2_0_PCIE_MC_ADDR0                                                                      0x4008be
+#define regBIFPLR2_0_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR2_0_PCIE_MC_ADDR1                                                                      0x4008bf
+#define regBIFPLR2_0_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR2_0_PCIE_MC_RCV0                                                                       0x4008c0
+#define regBIFPLR2_0_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR2_0_PCIE_MC_RCV1                                                                       0x4008c1
+#define regBIFPLR2_0_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR2_0_PCIE_MC_BLOCK_ALL0                                                                 0x4008c2
+#define regBIFPLR2_0_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR2_0_PCIE_MC_BLOCK_ALL1                                                                 0x4008c3
+#define regBIFPLR2_0_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x4008c4
+#define regBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x4008c5
+#define regBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR2_0_PCIE_MC_OVERLAY_BAR0                                                               0x4008c6
+#define regBIFPLR2_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_MC_OVERLAY_BAR1                                                               0x4008c7
+#define regBIFPLR2_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST                                                            0x4008dc
+#define regBIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR2_0_PCIE_L1_PM_SUB_CAP                                                                 0x4008dd
+#define regBIFPLR2_0_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR2_0_PCIE_L1_PM_SUB_CNTL                                                                0x4008de
+#define regBIFPLR2_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR2_0_PCIE_L1_PM_SUB_CNTL2                                                               0x4008df
+#define regBIFPLR2_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_DPC_ENH_CAP_LIST                                                              0x4008e0
+#define regBIFPLR2_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR2_0_PCIE_DPC_CAP_LIST                                                                  0x4008e1
+#define regBIFPLR2_0_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR2_0_PCIE_DPC_CNTL                                                                      0x4008e1
+#define regBIFPLR2_0_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR2_0_PCIE_DPC_STATUS                                                                    0x4008e2
+#define regBIFPLR2_0_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID                                                           0x4008e2
+#define regBIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR2_0_PCIE_RP_PIO_STATUS                                                                 0x4008e3
+#define regBIFPLR2_0_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR2_0_PCIE_RP_PIO_MASK                                                                   0x4008e4
+#define regBIFPLR2_0_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR2_0_PCIE_RP_PIO_SEVERITY                                                               0x4008e5
+#define regBIFPLR2_0_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_RP_PIO_SYSERROR                                                               0x4008e6
+#define regBIFPLR2_0_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_RP_PIO_EXCEPTION                                                              0x4008e7
+#define regBIFPLR2_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG0                                                               0x4008e8
+#define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG1                                                               0x4008e9
+#define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG2                                                               0x4008ea
+#define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG3                                                               0x4008eb
+#define regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0                                                            0x4008ed
+#define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1                                                            0x4008ee
+#define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2                                                            0x4008ef
+#define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3                                                            0x4008f0
+#define regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR2_0_PCIE_ESM_CAP_LIST                                                                  0x4008f1
+#define regBIFPLR2_0_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR2_0_PCIE_ESM_HEADER_1                                                                  0x4008f2
+#define regBIFPLR2_0_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR2_0_PCIE_ESM_HEADER_2                                                                  0x4008f3
+#define regBIFPLR2_0_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR2_0_PCIE_ESM_STATUS                                                                    0x4008f3
+#define regBIFPLR2_0_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR2_0_PCIE_ESM_CTRL                                                                      0x4008f4
+#define regBIFPLR2_0_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR2_0_PCIE_ESM_CAP_1                                                                     0x4008f5
+#define regBIFPLR2_0_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR2_0_PCIE_ESM_CAP_2                                                                     0x4008f6
+#define regBIFPLR2_0_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR2_0_PCIE_ESM_CAP_3                                                                     0x4008f7
+#define regBIFPLR2_0_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR2_0_PCIE_ESM_CAP_4                                                                     0x4008f8
+#define regBIFPLR2_0_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR2_0_PCIE_ESM_CAP_5                                                                     0x4008f9
+#define regBIFPLR2_0_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR2_0_PCIE_ESM_CAP_6                                                                     0x4008fa
+#define regBIFPLR2_0_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR2_0_PCIE_ESM_CAP_7                                                                     0x4008fb
+#define regBIFPLR2_0_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR2_0_PCIE_DLF_ENH_CAP_LIST                                                              0x400900
+#define regBIFPLR2_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR2_0_DATA_LINK_FEATURE_CAP                                                              0x400901
+#define regBIFPLR2_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR2_0_DATA_LINK_FEATURE_STATUS                                                           0x400902
+#define regBIFPLR2_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x400904
+#define regBIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR2_0_LINK_CAP_16GT                                                                      0x400905
+#define regBIFPLR2_0_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR2_0_LINK_CNTL_16GT                                                                     0x400906
+#define regBIFPLR2_0_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR2_0_LINK_STATUS_16GT                                                                   0x400907
+#define regBIFPLR2_0_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR2_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x400908
+#define regBIFPLR2_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR2_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x400909
+#define regBIFPLR2_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR2_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x40090a
+#define regBIFPLR2_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x40090c
+#define regBIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x40090c
+#define regBIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x40090c
+#define regBIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x40090c
+#define regBIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x40090d
+#define regBIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x40090d
+#define regBIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x40090d
+#define regBIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x40090d
+#define regBIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x40090e
+#define regBIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x40090e
+#define regBIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x40090e
+#define regBIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x40090e
+#define regBIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x40090f
+#define regBIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x40090f
+#define regBIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x40090f
+#define regBIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x40090f
+#define regBIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST                                                        0x400910
+#define regBIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR2_0_MARGINING_PORT_CAP                                                                 0x400911
+#define regBIFPLR2_0_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR2_0_MARGINING_PORT_STATUS                                                              0x400911
+#define regBIFPLR2_0_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR2_0_LANE_0_MARGINING_LANE_CNTL                                                         0x400912
+#define regBIFPLR2_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_0_LANE_0_MARGINING_LANE_STATUS                                                       0x400912
+#define regBIFPLR2_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_0_LANE_1_MARGINING_LANE_CNTL                                                         0x400913
+#define regBIFPLR2_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_0_LANE_1_MARGINING_LANE_STATUS                                                       0x400913
+#define regBIFPLR2_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_0_LANE_2_MARGINING_LANE_CNTL                                                         0x400914
+#define regBIFPLR2_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_0_LANE_2_MARGINING_LANE_STATUS                                                       0x400914
+#define regBIFPLR2_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_0_LANE_3_MARGINING_LANE_CNTL                                                         0x400915
+#define regBIFPLR2_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_0_LANE_3_MARGINING_LANE_STATUS                                                       0x400915
+#define regBIFPLR2_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_0_LANE_4_MARGINING_LANE_CNTL                                                         0x400916
+#define regBIFPLR2_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_0_LANE_4_MARGINING_LANE_STATUS                                                       0x400916
+#define regBIFPLR2_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_0_LANE_5_MARGINING_LANE_CNTL                                                         0x400917
+#define regBIFPLR2_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_0_LANE_5_MARGINING_LANE_STATUS                                                       0x400917
+#define regBIFPLR2_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_0_LANE_6_MARGINING_LANE_CNTL                                                         0x400918
+#define regBIFPLR2_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_0_LANE_6_MARGINING_LANE_STATUS                                                       0x400918
+#define regBIFPLR2_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_0_LANE_7_MARGINING_LANE_CNTL                                                         0x400919
+#define regBIFPLR2_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_0_LANE_7_MARGINING_LANE_STATUS                                                       0x400919
+#define regBIFPLR2_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_0_LANE_8_MARGINING_LANE_CNTL                                                         0x40091a
+#define regBIFPLR2_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_0_LANE_8_MARGINING_LANE_STATUS                                                       0x40091a
+#define regBIFPLR2_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_0_LANE_9_MARGINING_LANE_CNTL                                                         0x40091b
+#define regBIFPLR2_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_0_LANE_9_MARGINING_LANE_STATUS                                                       0x40091b
+#define regBIFPLR2_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_0_LANE_10_MARGINING_LANE_CNTL                                                        0x40091c
+#define regBIFPLR2_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_0_LANE_10_MARGINING_LANE_STATUS                                                      0x40091c
+#define regBIFPLR2_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_11_MARGINING_LANE_CNTL                                                        0x40091d
+#define regBIFPLR2_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_0_LANE_11_MARGINING_LANE_STATUS                                                      0x40091d
+#define regBIFPLR2_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_12_MARGINING_LANE_CNTL                                                        0x40091e
+#define regBIFPLR2_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_0_LANE_12_MARGINING_LANE_STATUS                                                      0x40091e
+#define regBIFPLR2_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_13_MARGINING_LANE_CNTL                                                        0x40091f
+#define regBIFPLR2_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_0_LANE_13_MARGINING_LANE_STATUS                                                      0x40091f
+#define regBIFPLR2_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_14_MARGINING_LANE_CNTL                                                        0x400920
+#define regBIFPLR2_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_0_LANE_14_MARGINING_LANE_STATUS                                                      0x400920
+#define regBIFPLR2_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_0_LANE_15_MARGINING_LANE_CNTL                                                        0x400921
+#define regBIFPLR2_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_0_LANE_15_MARGINING_LANE_STATUS                                                      0x400921
+#define regBIFPLR2_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_0_PCIE_CCIX_CAP_LIST                                                                 0x400922
+#define regBIFPLR2_0_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR2_0_PCIE_CCIX_HEADER_1                                                                 0x400923
+#define regBIFPLR2_0_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR2_0_PCIE_CCIX_HEADER_2                                                                 0x400924
+#define regBIFPLR2_0_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR2_0_PCIE_CCIX_CAP                                                                      0x400924
+#define regBIFPLR2_0_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP                                                             0x400925
+#define regBIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR2_0_PCIE_CCIX_ESM_OPTL_CAP                                                             0x400926
+#define regBIFPLR2_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR2_0_PCIE_CCIX_ESM_STATUS                                                               0x400927
+#define regBIFPLR2_0_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR2_0_PCIE_CCIX_ESM_CNTL                                                                 0x400928
+#define regBIFPLR2_0_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x400929
+#define regBIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x400929
+#define regBIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x400929
+#define regBIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x400929
+#define regBIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x40092a
+#define regBIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x40092a
+#define regBIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x40092a
+#define regBIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x40092a
+#define regBIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x40092b
+#define regBIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x40092b
+#define regBIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x40092b
+#define regBIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x40092b
+#define regBIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x40092c
+#define regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x40092c
+#define regBIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x40092c
+#define regBIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x40092c
+#define regBIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x40092d
+#define regBIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x40092d
+#define regBIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x40092d
+#define regBIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x40092d
+#define regBIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x40092e
+#define regBIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x40092e
+#define regBIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x40092e
+#define regBIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x40092e
+#define regBIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x40092f
+#define regBIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x40092f
+#define regBIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x40092f
+#define regBIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x40092f
+#define regBIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x400930
+#define regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x400930
+#define regBIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x400930
+#define regBIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x400930
+#define regBIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_0_PCIE_CCIX_TRANS_CAP                                                                0x400931
+#define regBIFPLR2_0_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR2_0_PCIE_CCIX_TRANS_CNTL                                                               0x400932
+#define regBIFPLR2_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+// base address: 0x11103000
+#define regBIFPLR3_0_VENDOR_ID                                                                          0x400c00
+#define regBIFPLR3_0_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR3_0_DEVICE_ID                                                                          0x400c00
+#define regBIFPLR3_0_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR3_0_COMMAND                                                                            0x400c01
+#define regBIFPLR3_0_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR3_0_STATUS                                                                             0x400c01
+#define regBIFPLR3_0_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR3_0_REVISION_ID                                                                        0x400c02
+#define regBIFPLR3_0_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR3_0_PROG_INTERFACE                                                                     0x400c02
+#define regBIFPLR3_0_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR3_0_SUB_CLASS                                                                          0x400c02
+#define regBIFPLR3_0_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR3_0_BASE_CLASS                                                                         0x400c02
+#define regBIFPLR3_0_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR3_0_CACHE_LINE                                                                         0x400c03
+#define regBIFPLR3_0_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR3_0_LATENCY                                                                            0x400c03
+#define regBIFPLR3_0_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR3_0_HEADER                                                                             0x400c03
+#define regBIFPLR3_0_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR3_0_BIST                                                                               0x400c03
+#define regBIFPLR3_0_BIST_BASE_IDX                                                                      5
+#define regBIFPLR3_0_SUB_BUS_NUMBER_LATENCY                                                             0x400c06
+#define regBIFPLR3_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR3_0_IO_BASE_LIMIT                                                                      0x400c07
+#define regBIFPLR3_0_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR3_0_SECONDARY_STATUS                                                                   0x400c07
+#define regBIFPLR3_0_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR3_0_MEM_BASE_LIMIT                                                                     0x400c08
+#define regBIFPLR3_0_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR3_0_PREF_BASE_LIMIT                                                                    0x400c09
+#define regBIFPLR3_0_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR3_0_PREF_BASE_UPPER                                                                    0x400c0a
+#define regBIFPLR3_0_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR3_0_PREF_LIMIT_UPPER                                                                   0x400c0b
+#define regBIFPLR3_0_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR3_0_IO_BASE_LIMIT_HI                                                                   0x400c0c
+#define regBIFPLR3_0_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR3_0_CAP_PTR                                                                            0x400c0d
+#define regBIFPLR3_0_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR3_0_ROM_BASE_ADDR                                                                      0x400c0e
+#define regBIFPLR3_0_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR3_0_INTERRUPT_LINE                                                                     0x400c0f
+#define regBIFPLR3_0_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR3_0_INTERRUPT_PIN                                                                      0x400c0f
+#define regBIFPLR3_0_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR3_0_IRQ_BRIDGE_CNTL                                                                    0x400c0f
+#define regBIFPLR3_0_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR3_0_EXT_BRIDGE_CNTL                                                                    0x400c10
+#define regBIFPLR3_0_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR3_0_VENDOR_CAP_LIST                                                                    0x400c12
+#define regBIFPLR3_0_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR3_0_ADAPTER_ID_W                                                                       0x400c13
+#define regBIFPLR3_0_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR3_0_PMI_CAP_LIST                                                                       0x400c14
+#define regBIFPLR3_0_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR3_0_PMI_CAP                                                                            0x400c14
+#define regBIFPLR3_0_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR3_0_PMI_STATUS_CNTL                                                                    0x400c15
+#define regBIFPLR3_0_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR3_0_PCIE_CAP_LIST                                                                      0x400c16
+#define regBIFPLR3_0_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR3_0_PCIE_CAP                                                                           0x400c16
+#define regBIFPLR3_0_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR3_0_DEVICE_CAP                                                                         0x400c17
+#define regBIFPLR3_0_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR3_0_DEVICE_CNTL                                                                        0x400c18
+#define regBIFPLR3_0_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR3_0_DEVICE_STATUS                                                                      0x400c18
+#define regBIFPLR3_0_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR3_0_LINK_CAP                                                                           0x400c19
+#define regBIFPLR3_0_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR3_0_LINK_CNTL                                                                          0x400c1a
+#define regBIFPLR3_0_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR3_0_LINK_STATUS                                                                        0x400c1a
+#define regBIFPLR3_0_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR3_0_SLOT_CAP                                                                           0x400c1b
+#define regBIFPLR3_0_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR3_0_SLOT_CNTL                                                                          0x400c1c
+#define regBIFPLR3_0_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR3_0_SLOT_STATUS                                                                        0x400c1c
+#define regBIFPLR3_0_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR3_0_ROOT_CNTL                                                                          0x400c1d
+#define regBIFPLR3_0_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR3_0_ROOT_CAP                                                                           0x400c1d
+#define regBIFPLR3_0_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR3_0_ROOT_STATUS                                                                        0x400c1e
+#define regBIFPLR3_0_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR3_0_DEVICE_CAP2                                                                        0x400c1f
+#define regBIFPLR3_0_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR3_0_DEVICE_CNTL2                                                                       0x400c20
+#define regBIFPLR3_0_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR3_0_DEVICE_STATUS2                                                                     0x400c20
+#define regBIFPLR3_0_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR3_0_LINK_CAP2                                                                          0x400c21
+#define regBIFPLR3_0_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR3_0_LINK_CNTL2                                                                         0x400c22
+#define regBIFPLR3_0_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR3_0_LINK_STATUS2                                                                       0x400c22
+#define regBIFPLR3_0_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR3_0_SLOT_CAP2                                                                          0x400c23
+#define regBIFPLR3_0_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR3_0_SLOT_CNTL2                                                                         0x400c24
+#define regBIFPLR3_0_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR3_0_SLOT_STATUS2                                                                       0x400c24
+#define regBIFPLR3_0_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR3_0_MSI_CAP_LIST                                                                       0x400c28
+#define regBIFPLR3_0_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR3_0_MSI_MSG_CNTL                                                                       0x400c28
+#define regBIFPLR3_0_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR3_0_MSI_MSG_ADDR_LO                                                                    0x400c29
+#define regBIFPLR3_0_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR3_0_MSI_MSG_ADDR_HI                                                                    0x400c2a
+#define regBIFPLR3_0_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR3_0_MSI_MSG_DATA                                                                       0x400c2a
+#define regBIFPLR3_0_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR3_0_MSI_MSG_DATA_64                                                                    0x400c2b
+#define regBIFPLR3_0_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR3_0_SSID_CAP_LIST                                                                      0x400c30
+#define regBIFPLR3_0_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR3_0_SSID_CAP                                                                           0x400c31
+#define regBIFPLR3_0_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR3_0_MSI_MAP_CAP_LIST                                                                   0x400c32
+#define regBIFPLR3_0_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR3_0_MSI_MAP_CAP                                                                        0x400c32
+#define regBIFPLR3_0_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x400c40
+#define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR                                                           0x400c41
+#define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC1                                                              0x400c42
+#define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC2                                                              0x400c43
+#define regBIFPLR3_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR3_0_PCIE_VC_ENH_CAP_LIST                                                               0x400c44
+#define regBIFPLR3_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_PORT_VC_CAP_REG1                                                              0x400c45
+#define regBIFPLR3_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR3_0_PCIE_PORT_VC_CAP_REG2                                                              0x400c46
+#define regBIFPLR3_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR3_0_PCIE_PORT_VC_CNTL                                                                  0x400c47
+#define regBIFPLR3_0_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR3_0_PCIE_PORT_VC_STATUS                                                                0x400c47
+#define regBIFPLR3_0_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR3_0_PCIE_VC0_RESOURCE_CAP                                                              0x400c48
+#define regBIFPLR3_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR3_0_PCIE_VC0_RESOURCE_CNTL                                                             0x400c49
+#define regBIFPLR3_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR3_0_PCIE_VC0_RESOURCE_STATUS                                                           0x400c4a
+#define regBIFPLR3_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR3_0_PCIE_VC1_RESOURCE_CAP                                                              0x400c4b
+#define regBIFPLR3_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR3_0_PCIE_VC1_RESOURCE_CNTL                                                             0x400c4c
+#define regBIFPLR3_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR3_0_PCIE_VC1_RESOURCE_STATUS                                                           0x400c4d
+#define regBIFPLR3_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x400c50
+#define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1                                                            0x400c51
+#define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2                                                            0x400c52
+#define regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x400c54
+#define regBIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_UNCORR_ERR_STATUS                                                             0x400c55
+#define regBIFPLR3_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR3_0_PCIE_UNCORR_ERR_MASK                                                               0x400c56
+#define regBIFPLR3_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY                                                           0x400c57
+#define regBIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR3_0_PCIE_CORR_ERR_STATUS                                                               0x400c58
+#define regBIFPLR3_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_CORR_ERR_MASK                                                                 0x400c59
+#define regBIFPLR3_0_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL                                                              0x400c5a
+#define regBIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR3_0_PCIE_HDR_LOG0                                                                      0x400c5b
+#define regBIFPLR3_0_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR3_0_PCIE_HDR_LOG1                                                                      0x400c5c
+#define regBIFPLR3_0_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR3_0_PCIE_HDR_LOG2                                                                      0x400c5d
+#define regBIFPLR3_0_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR3_0_PCIE_HDR_LOG3                                                                      0x400c5e
+#define regBIFPLR3_0_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR3_0_PCIE_ROOT_ERR_CMD                                                                  0x400c5f
+#define regBIFPLR3_0_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR3_0_PCIE_ROOT_ERR_STATUS                                                               0x400c60
+#define regBIFPLR3_0_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_ERR_SRC_ID                                                                    0x400c61
+#define regBIFPLR3_0_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG0                                                               0x400c62
+#define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG1                                                               0x400c63
+#define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG2                                                               0x400c64
+#define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG3                                                               0x400c65
+#define regBIFPLR3_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x400c9c
+#define regBIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR3_0_PCIE_LINK_CNTL3                                                                    0x400c9d
+#define regBIFPLR3_0_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR3_0_PCIE_LANE_ERROR_STATUS                                                             0x400c9e
+#define regBIFPLR3_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x400c9f
+#define regBIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x400c9f
+#define regBIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x400ca0
+#define regBIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x400ca0
+#define regBIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x400ca1
+#define regBIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x400ca1
+#define regBIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x400ca2
+#define regBIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x400ca2
+#define regBIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x400ca3
+#define regBIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x400ca3
+#define regBIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x400ca4
+#define regBIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x400ca4
+#define regBIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x400ca5
+#define regBIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x400ca5
+#define regBIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x400ca6
+#define regBIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x400ca6
+#define regBIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_0_PCIE_ACS_ENH_CAP_LIST                                                              0x400ca8
+#define regBIFPLR3_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR3_0_PCIE_ACS_CAP                                                                       0x400ca9
+#define regBIFPLR3_0_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR3_0_PCIE_ACS_CNTL                                                                      0x400ca9
+#define regBIFPLR3_0_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR3_0_PCIE_MC_ENH_CAP_LIST                                                               0x400cbc
+#define regBIFPLR3_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_MC_CAP                                                                        0x400cbd
+#define regBIFPLR3_0_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR3_0_PCIE_MC_CNTL                                                                       0x400cbd
+#define regBIFPLR3_0_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR3_0_PCIE_MC_ADDR0                                                                      0x400cbe
+#define regBIFPLR3_0_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR3_0_PCIE_MC_ADDR1                                                                      0x400cbf
+#define regBIFPLR3_0_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR3_0_PCIE_MC_RCV0                                                                       0x400cc0
+#define regBIFPLR3_0_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR3_0_PCIE_MC_RCV1                                                                       0x400cc1
+#define regBIFPLR3_0_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR3_0_PCIE_MC_BLOCK_ALL0                                                                 0x400cc2
+#define regBIFPLR3_0_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR3_0_PCIE_MC_BLOCK_ALL1                                                                 0x400cc3
+#define regBIFPLR3_0_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x400cc4
+#define regBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x400cc5
+#define regBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR3_0_PCIE_MC_OVERLAY_BAR0                                                               0x400cc6
+#define regBIFPLR3_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_MC_OVERLAY_BAR1                                                               0x400cc7
+#define regBIFPLR3_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST                                                            0x400cdc
+#define regBIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR3_0_PCIE_L1_PM_SUB_CAP                                                                 0x400cdd
+#define regBIFPLR3_0_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR3_0_PCIE_L1_PM_SUB_CNTL                                                                0x400cde
+#define regBIFPLR3_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR3_0_PCIE_L1_PM_SUB_CNTL2                                                               0x400cdf
+#define regBIFPLR3_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_DPC_ENH_CAP_LIST                                                              0x400ce0
+#define regBIFPLR3_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR3_0_PCIE_DPC_CAP_LIST                                                                  0x400ce1
+#define regBIFPLR3_0_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR3_0_PCIE_DPC_CNTL                                                                      0x400ce1
+#define regBIFPLR3_0_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR3_0_PCIE_DPC_STATUS                                                                    0x400ce2
+#define regBIFPLR3_0_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID                                                           0x400ce2
+#define regBIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR3_0_PCIE_RP_PIO_STATUS                                                                 0x400ce3
+#define regBIFPLR3_0_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR3_0_PCIE_RP_PIO_MASK                                                                   0x400ce4
+#define regBIFPLR3_0_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR3_0_PCIE_RP_PIO_SEVERITY                                                               0x400ce5
+#define regBIFPLR3_0_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_RP_PIO_SYSERROR                                                               0x400ce6
+#define regBIFPLR3_0_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_RP_PIO_EXCEPTION                                                              0x400ce7
+#define regBIFPLR3_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG0                                                               0x400ce8
+#define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG1                                                               0x400ce9
+#define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG2                                                               0x400cea
+#define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG3                                                               0x400ceb
+#define regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0                                                            0x400ced
+#define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1                                                            0x400cee
+#define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2                                                            0x400cef
+#define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3                                                            0x400cf0
+#define regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR3_0_PCIE_ESM_CAP_LIST                                                                  0x400cf1
+#define regBIFPLR3_0_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR3_0_PCIE_ESM_HEADER_1                                                                  0x400cf2
+#define regBIFPLR3_0_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR3_0_PCIE_ESM_HEADER_2                                                                  0x400cf3
+#define regBIFPLR3_0_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR3_0_PCIE_ESM_STATUS                                                                    0x400cf3
+#define regBIFPLR3_0_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR3_0_PCIE_ESM_CTRL                                                                      0x400cf4
+#define regBIFPLR3_0_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR3_0_PCIE_ESM_CAP_1                                                                     0x400cf5
+#define regBIFPLR3_0_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR3_0_PCIE_ESM_CAP_2                                                                     0x400cf6
+#define regBIFPLR3_0_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR3_0_PCIE_ESM_CAP_3                                                                     0x400cf7
+#define regBIFPLR3_0_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR3_0_PCIE_ESM_CAP_4                                                                     0x400cf8
+#define regBIFPLR3_0_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR3_0_PCIE_ESM_CAP_5                                                                     0x400cf9
+#define regBIFPLR3_0_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR3_0_PCIE_ESM_CAP_6                                                                     0x400cfa
+#define regBIFPLR3_0_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR3_0_PCIE_ESM_CAP_7                                                                     0x400cfb
+#define regBIFPLR3_0_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR3_0_PCIE_DLF_ENH_CAP_LIST                                                              0x400d00
+#define regBIFPLR3_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR3_0_DATA_LINK_FEATURE_CAP                                                              0x400d01
+#define regBIFPLR3_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR3_0_DATA_LINK_FEATURE_STATUS                                                           0x400d02
+#define regBIFPLR3_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x400d04
+#define regBIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR3_0_LINK_CAP_16GT                                                                      0x400d05
+#define regBIFPLR3_0_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR3_0_LINK_CNTL_16GT                                                                     0x400d06
+#define regBIFPLR3_0_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR3_0_LINK_STATUS_16GT                                                                   0x400d07
+#define regBIFPLR3_0_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR3_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x400d08
+#define regBIFPLR3_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR3_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x400d09
+#define regBIFPLR3_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR3_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x400d0a
+#define regBIFPLR3_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x400d0c
+#define regBIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x400d0c
+#define regBIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x400d0c
+#define regBIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x400d0c
+#define regBIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x400d0d
+#define regBIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x400d0d
+#define regBIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x400d0d
+#define regBIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x400d0d
+#define regBIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x400d0e
+#define regBIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x400d0e
+#define regBIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x400d0e
+#define regBIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x400d0e
+#define regBIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x400d0f
+#define regBIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x400d0f
+#define regBIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x400d0f
+#define regBIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x400d0f
+#define regBIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST                                                        0x400d10
+#define regBIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR3_0_MARGINING_PORT_CAP                                                                 0x400d11
+#define regBIFPLR3_0_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR3_0_MARGINING_PORT_STATUS                                                              0x400d11
+#define regBIFPLR3_0_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR3_0_LANE_0_MARGINING_LANE_CNTL                                                         0x400d12
+#define regBIFPLR3_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_0_LANE_0_MARGINING_LANE_STATUS                                                       0x400d12
+#define regBIFPLR3_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_0_LANE_1_MARGINING_LANE_CNTL                                                         0x400d13
+#define regBIFPLR3_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_0_LANE_1_MARGINING_LANE_STATUS                                                       0x400d13
+#define regBIFPLR3_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_0_LANE_2_MARGINING_LANE_CNTL                                                         0x400d14
+#define regBIFPLR3_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_0_LANE_2_MARGINING_LANE_STATUS                                                       0x400d14
+#define regBIFPLR3_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_0_LANE_3_MARGINING_LANE_CNTL                                                         0x400d15
+#define regBIFPLR3_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_0_LANE_3_MARGINING_LANE_STATUS                                                       0x400d15
+#define regBIFPLR3_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_0_LANE_4_MARGINING_LANE_CNTL                                                         0x400d16
+#define regBIFPLR3_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_0_LANE_4_MARGINING_LANE_STATUS                                                       0x400d16
+#define regBIFPLR3_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_0_LANE_5_MARGINING_LANE_CNTL                                                         0x400d17
+#define regBIFPLR3_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_0_LANE_5_MARGINING_LANE_STATUS                                                       0x400d17
+#define regBIFPLR3_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_0_LANE_6_MARGINING_LANE_CNTL                                                         0x400d18
+#define regBIFPLR3_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_0_LANE_6_MARGINING_LANE_STATUS                                                       0x400d18
+#define regBIFPLR3_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_0_LANE_7_MARGINING_LANE_CNTL                                                         0x400d19
+#define regBIFPLR3_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_0_LANE_7_MARGINING_LANE_STATUS                                                       0x400d19
+#define regBIFPLR3_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_0_LANE_8_MARGINING_LANE_CNTL                                                         0x400d1a
+#define regBIFPLR3_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_0_LANE_8_MARGINING_LANE_STATUS                                                       0x400d1a
+#define regBIFPLR3_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_0_LANE_9_MARGINING_LANE_CNTL                                                         0x400d1b
+#define regBIFPLR3_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_0_LANE_9_MARGINING_LANE_STATUS                                                       0x400d1b
+#define regBIFPLR3_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_0_LANE_10_MARGINING_LANE_CNTL                                                        0x400d1c
+#define regBIFPLR3_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_0_LANE_10_MARGINING_LANE_STATUS                                                      0x400d1c
+#define regBIFPLR3_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_11_MARGINING_LANE_CNTL                                                        0x400d1d
+#define regBIFPLR3_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_0_LANE_11_MARGINING_LANE_STATUS                                                      0x400d1d
+#define regBIFPLR3_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_12_MARGINING_LANE_CNTL                                                        0x400d1e
+#define regBIFPLR3_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_0_LANE_12_MARGINING_LANE_STATUS                                                      0x400d1e
+#define regBIFPLR3_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_13_MARGINING_LANE_CNTL                                                        0x400d1f
+#define regBIFPLR3_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_0_LANE_13_MARGINING_LANE_STATUS                                                      0x400d1f
+#define regBIFPLR3_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_14_MARGINING_LANE_CNTL                                                        0x400d20
+#define regBIFPLR3_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_0_LANE_14_MARGINING_LANE_STATUS                                                      0x400d20
+#define regBIFPLR3_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_0_LANE_15_MARGINING_LANE_CNTL                                                        0x400d21
+#define regBIFPLR3_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_0_LANE_15_MARGINING_LANE_STATUS                                                      0x400d21
+#define regBIFPLR3_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_0_PCIE_CCIX_CAP_LIST                                                                 0x400d22
+#define regBIFPLR3_0_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR3_0_PCIE_CCIX_HEADER_1                                                                 0x400d23
+#define regBIFPLR3_0_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR3_0_PCIE_CCIX_HEADER_2                                                                 0x400d24
+#define regBIFPLR3_0_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR3_0_PCIE_CCIX_CAP                                                                      0x400d24
+#define regBIFPLR3_0_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP                                                             0x400d25
+#define regBIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR3_0_PCIE_CCIX_ESM_OPTL_CAP                                                             0x400d26
+#define regBIFPLR3_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR3_0_PCIE_CCIX_ESM_STATUS                                                               0x400d27
+#define regBIFPLR3_0_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR3_0_PCIE_CCIX_ESM_CNTL                                                                 0x400d28
+#define regBIFPLR3_0_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x400d29
+#define regBIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x400d29
+#define regBIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x400d29
+#define regBIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x400d29
+#define regBIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x400d2a
+#define regBIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x400d2a
+#define regBIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x400d2a
+#define regBIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x400d2a
+#define regBIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x400d2b
+#define regBIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x400d2b
+#define regBIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x400d2b
+#define regBIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x400d2b
+#define regBIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x400d2c
+#define regBIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x400d2c
+#define regBIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x400d2c
+#define regBIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x400d2c
+#define regBIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x400d2d
+#define regBIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x400d2d
+#define regBIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x400d2d
+#define regBIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x400d2d
+#define regBIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x400d2e
+#define regBIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x400d2e
+#define regBIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x400d2e
+#define regBIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x400d2e
+#define regBIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x400d2f
+#define regBIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x400d2f
+#define regBIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x400d2f
+#define regBIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x400d2f
+#define regBIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x400d30
+#define regBIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x400d30
+#define regBIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x400d30
+#define regBIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x400d30
+#define regBIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_0_PCIE_CCIX_TRANS_CAP                                                                0x400d31
+#define regBIFPLR3_0_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR3_0_PCIE_CCIX_TRANS_CNTL                                                               0x400d32
+#define regBIFPLR3_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+// base address: 0x11104000
+#define regBIFPLR4_0_VENDOR_ID                                                                          0x401000
+#define regBIFPLR4_0_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR4_0_DEVICE_ID                                                                          0x401000
+#define regBIFPLR4_0_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR4_0_COMMAND                                                                            0x401001
+#define regBIFPLR4_0_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR4_0_STATUS                                                                             0x401001
+#define regBIFPLR4_0_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR4_0_REVISION_ID                                                                        0x401002
+#define regBIFPLR4_0_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR4_0_PROG_INTERFACE                                                                     0x401002
+#define regBIFPLR4_0_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR4_0_SUB_CLASS                                                                          0x401002
+#define regBIFPLR4_0_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR4_0_BASE_CLASS                                                                         0x401002
+#define regBIFPLR4_0_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR4_0_CACHE_LINE                                                                         0x401003
+#define regBIFPLR4_0_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR4_0_LATENCY                                                                            0x401003
+#define regBIFPLR4_0_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR4_0_HEADER                                                                             0x401003
+#define regBIFPLR4_0_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR4_0_BIST                                                                               0x401003
+#define regBIFPLR4_0_BIST_BASE_IDX                                                                      5
+#define regBIFPLR4_0_SUB_BUS_NUMBER_LATENCY                                                             0x401006
+#define regBIFPLR4_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR4_0_IO_BASE_LIMIT                                                                      0x401007
+#define regBIFPLR4_0_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR4_0_SECONDARY_STATUS                                                                   0x401007
+#define regBIFPLR4_0_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR4_0_MEM_BASE_LIMIT                                                                     0x401008
+#define regBIFPLR4_0_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR4_0_PREF_BASE_LIMIT                                                                    0x401009
+#define regBIFPLR4_0_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR4_0_PREF_BASE_UPPER                                                                    0x40100a
+#define regBIFPLR4_0_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR4_0_PREF_LIMIT_UPPER                                                                   0x40100b
+#define regBIFPLR4_0_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR4_0_IO_BASE_LIMIT_HI                                                                   0x40100c
+#define regBIFPLR4_0_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR4_0_CAP_PTR                                                                            0x40100d
+#define regBIFPLR4_0_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR4_0_ROM_BASE_ADDR                                                                      0x40100e
+#define regBIFPLR4_0_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR4_0_INTERRUPT_LINE                                                                     0x40100f
+#define regBIFPLR4_0_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR4_0_INTERRUPT_PIN                                                                      0x40100f
+#define regBIFPLR4_0_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR4_0_IRQ_BRIDGE_CNTL                                                                    0x40100f
+#define regBIFPLR4_0_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR4_0_EXT_BRIDGE_CNTL                                                                    0x401010
+#define regBIFPLR4_0_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR4_0_VENDOR_CAP_LIST                                                                    0x401012
+#define regBIFPLR4_0_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR4_0_ADAPTER_ID_W                                                                       0x401013
+#define regBIFPLR4_0_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR4_0_PMI_CAP_LIST                                                                       0x401014
+#define regBIFPLR4_0_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR4_0_PMI_CAP                                                                            0x401014
+#define regBIFPLR4_0_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR4_0_PMI_STATUS_CNTL                                                                    0x401015
+#define regBIFPLR4_0_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR4_0_PCIE_CAP_LIST                                                                      0x401016
+#define regBIFPLR4_0_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR4_0_PCIE_CAP                                                                           0x401016
+#define regBIFPLR4_0_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR4_0_DEVICE_CAP                                                                         0x401017
+#define regBIFPLR4_0_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR4_0_DEVICE_CNTL                                                                        0x401018
+#define regBIFPLR4_0_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR4_0_DEVICE_STATUS                                                                      0x401018
+#define regBIFPLR4_0_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR4_0_LINK_CAP                                                                           0x401019
+#define regBIFPLR4_0_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR4_0_LINK_CNTL                                                                          0x40101a
+#define regBIFPLR4_0_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR4_0_LINK_STATUS                                                                        0x40101a
+#define regBIFPLR4_0_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR4_0_SLOT_CAP                                                                           0x40101b
+#define regBIFPLR4_0_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR4_0_SLOT_CNTL                                                                          0x40101c
+#define regBIFPLR4_0_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR4_0_SLOT_STATUS                                                                        0x40101c
+#define regBIFPLR4_0_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR4_0_ROOT_CNTL                                                                          0x40101d
+#define regBIFPLR4_0_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR4_0_ROOT_CAP                                                                           0x40101d
+#define regBIFPLR4_0_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR4_0_ROOT_STATUS                                                                        0x40101e
+#define regBIFPLR4_0_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR4_0_DEVICE_CAP2                                                                        0x40101f
+#define regBIFPLR4_0_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR4_0_DEVICE_CNTL2                                                                       0x401020
+#define regBIFPLR4_0_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR4_0_DEVICE_STATUS2                                                                     0x401020
+#define regBIFPLR4_0_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR4_0_LINK_CAP2                                                                          0x401021
+#define regBIFPLR4_0_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR4_0_LINK_CNTL2                                                                         0x401022
+#define regBIFPLR4_0_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR4_0_LINK_STATUS2                                                                       0x401022
+#define regBIFPLR4_0_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR4_0_SLOT_CAP2                                                                          0x401023
+#define regBIFPLR4_0_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR4_0_SLOT_CNTL2                                                                         0x401024
+#define regBIFPLR4_0_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR4_0_SLOT_STATUS2                                                                       0x401024
+#define regBIFPLR4_0_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR4_0_MSI_CAP_LIST                                                                       0x401028
+#define regBIFPLR4_0_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR4_0_MSI_MSG_CNTL                                                                       0x401028
+#define regBIFPLR4_0_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR4_0_MSI_MSG_ADDR_LO                                                                    0x401029
+#define regBIFPLR4_0_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR4_0_MSI_MSG_ADDR_HI                                                                    0x40102a
+#define regBIFPLR4_0_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR4_0_MSI_MSG_DATA                                                                       0x40102a
+#define regBIFPLR4_0_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR4_0_MSI_MSG_DATA_64                                                                    0x40102b
+#define regBIFPLR4_0_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR4_0_SSID_CAP_LIST                                                                      0x401030
+#define regBIFPLR4_0_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR4_0_SSID_CAP                                                                           0x401031
+#define regBIFPLR4_0_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR4_0_MSI_MAP_CAP_LIST                                                                   0x401032
+#define regBIFPLR4_0_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR4_0_MSI_MAP_CAP                                                                        0x401032
+#define regBIFPLR4_0_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x401040
+#define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR                                                           0x401041
+#define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC1                                                              0x401042
+#define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC2                                                              0x401043
+#define regBIFPLR4_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR4_0_PCIE_VC_ENH_CAP_LIST                                                               0x401044
+#define regBIFPLR4_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_PORT_VC_CAP_REG1                                                              0x401045
+#define regBIFPLR4_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR4_0_PCIE_PORT_VC_CAP_REG2                                                              0x401046
+#define regBIFPLR4_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR4_0_PCIE_PORT_VC_CNTL                                                                  0x401047
+#define regBIFPLR4_0_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR4_0_PCIE_PORT_VC_STATUS                                                                0x401047
+#define regBIFPLR4_0_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR4_0_PCIE_VC0_RESOURCE_CAP                                                              0x401048
+#define regBIFPLR4_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR4_0_PCIE_VC0_RESOURCE_CNTL                                                             0x401049
+#define regBIFPLR4_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR4_0_PCIE_VC0_RESOURCE_STATUS                                                           0x40104a
+#define regBIFPLR4_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR4_0_PCIE_VC1_RESOURCE_CAP                                                              0x40104b
+#define regBIFPLR4_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR4_0_PCIE_VC1_RESOURCE_CNTL                                                             0x40104c
+#define regBIFPLR4_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR4_0_PCIE_VC1_RESOURCE_STATUS                                                           0x40104d
+#define regBIFPLR4_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x401050
+#define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1                                                            0x401051
+#define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2                                                            0x401052
+#define regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x401054
+#define regBIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_UNCORR_ERR_STATUS                                                             0x401055
+#define regBIFPLR4_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR4_0_PCIE_UNCORR_ERR_MASK                                                               0x401056
+#define regBIFPLR4_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY                                                           0x401057
+#define regBIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR4_0_PCIE_CORR_ERR_STATUS                                                               0x401058
+#define regBIFPLR4_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_CORR_ERR_MASK                                                                 0x401059
+#define regBIFPLR4_0_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL                                                              0x40105a
+#define regBIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR4_0_PCIE_HDR_LOG0                                                                      0x40105b
+#define regBIFPLR4_0_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR4_0_PCIE_HDR_LOG1                                                                      0x40105c
+#define regBIFPLR4_0_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR4_0_PCIE_HDR_LOG2                                                                      0x40105d
+#define regBIFPLR4_0_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR4_0_PCIE_HDR_LOG3                                                                      0x40105e
+#define regBIFPLR4_0_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR4_0_PCIE_ROOT_ERR_CMD                                                                  0x40105f
+#define regBIFPLR4_0_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR4_0_PCIE_ROOT_ERR_STATUS                                                               0x401060
+#define regBIFPLR4_0_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_ERR_SRC_ID                                                                    0x401061
+#define regBIFPLR4_0_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG0                                                               0x401062
+#define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG1                                                               0x401063
+#define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG2                                                               0x401064
+#define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG3                                                               0x401065
+#define regBIFPLR4_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x40109c
+#define regBIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR4_0_PCIE_LINK_CNTL3                                                                    0x40109d
+#define regBIFPLR4_0_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR4_0_PCIE_LANE_ERROR_STATUS                                                             0x40109e
+#define regBIFPLR4_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x40109f
+#define regBIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x40109f
+#define regBIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x4010a0
+#define regBIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x4010a0
+#define regBIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x4010a1
+#define regBIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x4010a1
+#define regBIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x4010a2
+#define regBIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x4010a2
+#define regBIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x4010a3
+#define regBIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x4010a3
+#define regBIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x4010a4
+#define regBIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x4010a4
+#define regBIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x4010a5
+#define regBIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x4010a5
+#define regBIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x4010a6
+#define regBIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x4010a6
+#define regBIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_0_PCIE_ACS_ENH_CAP_LIST                                                              0x4010a8
+#define regBIFPLR4_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR4_0_PCIE_ACS_CAP                                                                       0x4010a9
+#define regBIFPLR4_0_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR4_0_PCIE_ACS_CNTL                                                                      0x4010a9
+#define regBIFPLR4_0_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR4_0_PCIE_MC_ENH_CAP_LIST                                                               0x4010bc
+#define regBIFPLR4_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_MC_CAP                                                                        0x4010bd
+#define regBIFPLR4_0_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR4_0_PCIE_MC_CNTL                                                                       0x4010bd
+#define regBIFPLR4_0_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR4_0_PCIE_MC_ADDR0                                                                      0x4010be
+#define regBIFPLR4_0_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR4_0_PCIE_MC_ADDR1                                                                      0x4010bf
+#define regBIFPLR4_0_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR4_0_PCIE_MC_RCV0                                                                       0x4010c0
+#define regBIFPLR4_0_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR4_0_PCIE_MC_RCV1                                                                       0x4010c1
+#define regBIFPLR4_0_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR4_0_PCIE_MC_BLOCK_ALL0                                                                 0x4010c2
+#define regBIFPLR4_0_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR4_0_PCIE_MC_BLOCK_ALL1                                                                 0x4010c3
+#define regBIFPLR4_0_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x4010c4
+#define regBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x4010c5
+#define regBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR4_0_PCIE_MC_OVERLAY_BAR0                                                               0x4010c6
+#define regBIFPLR4_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_MC_OVERLAY_BAR1                                                               0x4010c7
+#define regBIFPLR4_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST                                                            0x4010dc
+#define regBIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR4_0_PCIE_L1_PM_SUB_CAP                                                                 0x4010dd
+#define regBIFPLR4_0_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR4_0_PCIE_L1_PM_SUB_CNTL                                                                0x4010de
+#define regBIFPLR4_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR4_0_PCIE_L1_PM_SUB_CNTL2                                                               0x4010df
+#define regBIFPLR4_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_DPC_ENH_CAP_LIST                                                              0x4010e0
+#define regBIFPLR4_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR4_0_PCIE_DPC_CAP_LIST                                                                  0x4010e1
+#define regBIFPLR4_0_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR4_0_PCIE_DPC_CNTL                                                                      0x4010e1
+#define regBIFPLR4_0_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR4_0_PCIE_DPC_STATUS                                                                    0x4010e2
+#define regBIFPLR4_0_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID                                                           0x4010e2
+#define regBIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR4_0_PCIE_RP_PIO_STATUS                                                                 0x4010e3
+#define regBIFPLR4_0_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR4_0_PCIE_RP_PIO_MASK                                                                   0x4010e4
+#define regBIFPLR4_0_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR4_0_PCIE_RP_PIO_SEVERITY                                                               0x4010e5
+#define regBIFPLR4_0_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_RP_PIO_SYSERROR                                                               0x4010e6
+#define regBIFPLR4_0_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_RP_PIO_EXCEPTION                                                              0x4010e7
+#define regBIFPLR4_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG0                                                               0x4010e8
+#define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG1                                                               0x4010e9
+#define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG2                                                               0x4010ea
+#define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG3                                                               0x4010eb
+#define regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0                                                            0x4010ed
+#define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1                                                            0x4010ee
+#define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2                                                            0x4010ef
+#define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3                                                            0x4010f0
+#define regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR4_0_PCIE_ESM_CAP_LIST                                                                  0x4010f1
+#define regBIFPLR4_0_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR4_0_PCIE_ESM_HEADER_1                                                                  0x4010f2
+#define regBIFPLR4_0_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR4_0_PCIE_ESM_HEADER_2                                                                  0x4010f3
+#define regBIFPLR4_0_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR4_0_PCIE_ESM_STATUS                                                                    0x4010f3
+#define regBIFPLR4_0_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR4_0_PCIE_ESM_CTRL                                                                      0x4010f4
+#define regBIFPLR4_0_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR4_0_PCIE_ESM_CAP_1                                                                     0x4010f5
+#define regBIFPLR4_0_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR4_0_PCIE_ESM_CAP_2                                                                     0x4010f6
+#define regBIFPLR4_0_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR4_0_PCIE_ESM_CAP_3                                                                     0x4010f7
+#define regBIFPLR4_0_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR4_0_PCIE_ESM_CAP_4                                                                     0x4010f8
+#define regBIFPLR4_0_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR4_0_PCIE_ESM_CAP_5                                                                     0x4010f9
+#define regBIFPLR4_0_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR4_0_PCIE_ESM_CAP_6                                                                     0x4010fa
+#define regBIFPLR4_0_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR4_0_PCIE_ESM_CAP_7                                                                     0x4010fb
+#define regBIFPLR4_0_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR4_0_PCIE_DLF_ENH_CAP_LIST                                                              0x401100
+#define regBIFPLR4_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR4_0_DATA_LINK_FEATURE_CAP                                                              0x401101
+#define regBIFPLR4_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR4_0_DATA_LINK_FEATURE_STATUS                                                           0x401102
+#define regBIFPLR4_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x401104
+#define regBIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR4_0_LINK_CAP_16GT                                                                      0x401105
+#define regBIFPLR4_0_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR4_0_LINK_CNTL_16GT                                                                     0x401106
+#define regBIFPLR4_0_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR4_0_LINK_STATUS_16GT                                                                   0x401107
+#define regBIFPLR4_0_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR4_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x401108
+#define regBIFPLR4_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR4_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x401109
+#define regBIFPLR4_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR4_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x40110a
+#define regBIFPLR4_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x40110c
+#define regBIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x40110c
+#define regBIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x40110c
+#define regBIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x40110c
+#define regBIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x40110d
+#define regBIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x40110d
+#define regBIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x40110d
+#define regBIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x40110d
+#define regBIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x40110e
+#define regBIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x40110e
+#define regBIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x40110e
+#define regBIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x40110e
+#define regBIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x40110f
+#define regBIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x40110f
+#define regBIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x40110f
+#define regBIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x40110f
+#define regBIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST                                                        0x401110
+#define regBIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR4_0_MARGINING_PORT_CAP                                                                 0x401111
+#define regBIFPLR4_0_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR4_0_MARGINING_PORT_STATUS                                                              0x401111
+#define regBIFPLR4_0_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR4_0_LANE_0_MARGINING_LANE_CNTL                                                         0x401112
+#define regBIFPLR4_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_0_LANE_0_MARGINING_LANE_STATUS                                                       0x401112
+#define regBIFPLR4_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_0_LANE_1_MARGINING_LANE_CNTL                                                         0x401113
+#define regBIFPLR4_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_0_LANE_1_MARGINING_LANE_STATUS                                                       0x401113
+#define regBIFPLR4_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_0_LANE_2_MARGINING_LANE_CNTL                                                         0x401114
+#define regBIFPLR4_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_0_LANE_2_MARGINING_LANE_STATUS                                                       0x401114
+#define regBIFPLR4_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_0_LANE_3_MARGINING_LANE_CNTL                                                         0x401115
+#define regBIFPLR4_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_0_LANE_3_MARGINING_LANE_STATUS                                                       0x401115
+#define regBIFPLR4_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_0_LANE_4_MARGINING_LANE_CNTL                                                         0x401116
+#define regBIFPLR4_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_0_LANE_4_MARGINING_LANE_STATUS                                                       0x401116
+#define regBIFPLR4_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_0_LANE_5_MARGINING_LANE_CNTL                                                         0x401117
+#define regBIFPLR4_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_0_LANE_5_MARGINING_LANE_STATUS                                                       0x401117
+#define regBIFPLR4_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_0_LANE_6_MARGINING_LANE_CNTL                                                         0x401118
+#define regBIFPLR4_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_0_LANE_6_MARGINING_LANE_STATUS                                                       0x401118
+#define regBIFPLR4_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_0_LANE_7_MARGINING_LANE_CNTL                                                         0x401119
+#define regBIFPLR4_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_0_LANE_7_MARGINING_LANE_STATUS                                                       0x401119
+#define regBIFPLR4_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_0_LANE_8_MARGINING_LANE_CNTL                                                         0x40111a
+#define regBIFPLR4_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_0_LANE_8_MARGINING_LANE_STATUS                                                       0x40111a
+#define regBIFPLR4_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_0_LANE_9_MARGINING_LANE_CNTL                                                         0x40111b
+#define regBIFPLR4_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_0_LANE_9_MARGINING_LANE_STATUS                                                       0x40111b
+#define regBIFPLR4_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_0_LANE_10_MARGINING_LANE_CNTL                                                        0x40111c
+#define regBIFPLR4_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_0_LANE_10_MARGINING_LANE_STATUS                                                      0x40111c
+#define regBIFPLR4_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_11_MARGINING_LANE_CNTL                                                        0x40111d
+#define regBIFPLR4_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_0_LANE_11_MARGINING_LANE_STATUS                                                      0x40111d
+#define regBIFPLR4_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_12_MARGINING_LANE_CNTL                                                        0x40111e
+#define regBIFPLR4_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_0_LANE_12_MARGINING_LANE_STATUS                                                      0x40111e
+#define regBIFPLR4_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_13_MARGINING_LANE_CNTL                                                        0x40111f
+#define regBIFPLR4_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_0_LANE_13_MARGINING_LANE_STATUS                                                      0x40111f
+#define regBIFPLR4_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_14_MARGINING_LANE_CNTL                                                        0x401120
+#define regBIFPLR4_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_0_LANE_14_MARGINING_LANE_STATUS                                                      0x401120
+#define regBIFPLR4_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_0_LANE_15_MARGINING_LANE_CNTL                                                        0x401121
+#define regBIFPLR4_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_0_LANE_15_MARGINING_LANE_STATUS                                                      0x401121
+#define regBIFPLR4_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_0_PCIE_CCIX_CAP_LIST                                                                 0x401122
+#define regBIFPLR4_0_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR4_0_PCIE_CCIX_HEADER_1                                                                 0x401123
+#define regBIFPLR4_0_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR4_0_PCIE_CCIX_HEADER_2                                                                 0x401124
+#define regBIFPLR4_0_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR4_0_PCIE_CCIX_CAP                                                                      0x401124
+#define regBIFPLR4_0_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP                                                             0x401125
+#define regBIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR4_0_PCIE_CCIX_ESM_OPTL_CAP                                                             0x401126
+#define regBIFPLR4_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR4_0_PCIE_CCIX_ESM_STATUS                                                               0x401127
+#define regBIFPLR4_0_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR4_0_PCIE_CCIX_ESM_CNTL                                                                 0x401128
+#define regBIFPLR4_0_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x401129
+#define regBIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x401129
+#define regBIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x401129
+#define regBIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x401129
+#define regBIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x40112a
+#define regBIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x40112a
+#define regBIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x40112a
+#define regBIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x40112a
+#define regBIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x40112b
+#define regBIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x40112b
+#define regBIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x40112b
+#define regBIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x40112b
+#define regBIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x40112c
+#define regBIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x40112c
+#define regBIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x40112c
+#define regBIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x40112c
+#define regBIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x40112d
+#define regBIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x40112d
+#define regBIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x40112d
+#define regBIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x40112d
+#define regBIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x40112e
+#define regBIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x40112e
+#define regBIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x40112e
+#define regBIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x40112e
+#define regBIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x40112f
+#define regBIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x40112f
+#define regBIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x40112f
+#define regBIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x40112f
+#define regBIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x401130
+#define regBIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x401130
+#define regBIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x401130
+#define regBIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x401130
+#define regBIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_0_PCIE_CCIX_TRANS_CAP                                                                0x401131
+#define regBIFPLR4_0_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR4_0_PCIE_CCIX_TRANS_CNTL                                                               0x401132
+#define regBIFPLR4_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+// base address: 0x11105000
+#define regBIFPLR5_0_VENDOR_ID                                                                          0x401400
+#define regBIFPLR5_0_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR5_0_DEVICE_ID                                                                          0x401400
+#define regBIFPLR5_0_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR5_0_COMMAND                                                                            0x401401
+#define regBIFPLR5_0_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR5_0_STATUS                                                                             0x401401
+#define regBIFPLR5_0_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR5_0_REVISION_ID                                                                        0x401402
+#define regBIFPLR5_0_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR5_0_PROG_INTERFACE                                                                     0x401402
+#define regBIFPLR5_0_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR5_0_SUB_CLASS                                                                          0x401402
+#define regBIFPLR5_0_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR5_0_BASE_CLASS                                                                         0x401402
+#define regBIFPLR5_0_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR5_0_CACHE_LINE                                                                         0x401403
+#define regBIFPLR5_0_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR5_0_LATENCY                                                                            0x401403
+#define regBIFPLR5_0_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR5_0_HEADER                                                                             0x401403
+#define regBIFPLR5_0_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR5_0_BIST                                                                               0x401403
+#define regBIFPLR5_0_BIST_BASE_IDX                                                                      5
+#define regBIFPLR5_0_SUB_BUS_NUMBER_LATENCY                                                             0x401406
+#define regBIFPLR5_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR5_0_IO_BASE_LIMIT                                                                      0x401407
+#define regBIFPLR5_0_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR5_0_SECONDARY_STATUS                                                                   0x401407
+#define regBIFPLR5_0_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR5_0_MEM_BASE_LIMIT                                                                     0x401408
+#define regBIFPLR5_0_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR5_0_PREF_BASE_LIMIT                                                                    0x401409
+#define regBIFPLR5_0_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR5_0_PREF_BASE_UPPER                                                                    0x40140a
+#define regBIFPLR5_0_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR5_0_PREF_LIMIT_UPPER                                                                   0x40140b
+#define regBIFPLR5_0_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR5_0_IO_BASE_LIMIT_HI                                                                   0x40140c
+#define regBIFPLR5_0_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR5_0_CAP_PTR                                                                            0x40140d
+#define regBIFPLR5_0_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR5_0_ROM_BASE_ADDR                                                                      0x40140e
+#define regBIFPLR5_0_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR5_0_INTERRUPT_LINE                                                                     0x40140f
+#define regBIFPLR5_0_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR5_0_INTERRUPT_PIN                                                                      0x40140f
+#define regBIFPLR5_0_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR5_0_IRQ_BRIDGE_CNTL                                                                    0x40140f
+#define regBIFPLR5_0_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR5_0_EXT_BRIDGE_CNTL                                                                    0x401410
+#define regBIFPLR5_0_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR5_0_VENDOR_CAP_LIST                                                                    0x401412
+#define regBIFPLR5_0_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR5_0_ADAPTER_ID_W                                                                       0x401413
+#define regBIFPLR5_0_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR5_0_PMI_CAP_LIST                                                                       0x401414
+#define regBIFPLR5_0_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR5_0_PMI_CAP                                                                            0x401414
+#define regBIFPLR5_0_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR5_0_PMI_STATUS_CNTL                                                                    0x401415
+#define regBIFPLR5_0_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR5_0_PCIE_CAP_LIST                                                                      0x401416
+#define regBIFPLR5_0_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR5_0_PCIE_CAP                                                                           0x401416
+#define regBIFPLR5_0_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR5_0_DEVICE_CAP                                                                         0x401417
+#define regBIFPLR5_0_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR5_0_DEVICE_CNTL                                                                        0x401418
+#define regBIFPLR5_0_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR5_0_DEVICE_STATUS                                                                      0x401418
+#define regBIFPLR5_0_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR5_0_LINK_CAP                                                                           0x401419
+#define regBIFPLR5_0_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR5_0_LINK_CNTL                                                                          0x40141a
+#define regBIFPLR5_0_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR5_0_LINK_STATUS                                                                        0x40141a
+#define regBIFPLR5_0_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR5_0_SLOT_CAP                                                                           0x40141b
+#define regBIFPLR5_0_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR5_0_SLOT_CNTL                                                                          0x40141c
+#define regBIFPLR5_0_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR5_0_SLOT_STATUS                                                                        0x40141c
+#define regBIFPLR5_0_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR5_0_ROOT_CNTL                                                                          0x40141d
+#define regBIFPLR5_0_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR5_0_ROOT_CAP                                                                           0x40141d
+#define regBIFPLR5_0_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR5_0_ROOT_STATUS                                                                        0x40141e
+#define regBIFPLR5_0_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR5_0_DEVICE_CAP2                                                                        0x40141f
+#define regBIFPLR5_0_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR5_0_DEVICE_CNTL2                                                                       0x401420
+#define regBIFPLR5_0_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR5_0_DEVICE_STATUS2                                                                     0x401420
+#define regBIFPLR5_0_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR5_0_LINK_CAP2                                                                          0x401421
+#define regBIFPLR5_0_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR5_0_LINK_CNTL2                                                                         0x401422
+#define regBIFPLR5_0_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR5_0_LINK_STATUS2                                                                       0x401422
+#define regBIFPLR5_0_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR5_0_SLOT_CAP2                                                                          0x401423
+#define regBIFPLR5_0_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR5_0_SLOT_CNTL2                                                                         0x401424
+#define regBIFPLR5_0_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR5_0_SLOT_STATUS2                                                                       0x401424
+#define regBIFPLR5_0_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR5_0_MSI_CAP_LIST                                                                       0x401428
+#define regBIFPLR5_0_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR5_0_MSI_MSG_CNTL                                                                       0x401428
+#define regBIFPLR5_0_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR5_0_MSI_MSG_ADDR_LO                                                                    0x401429
+#define regBIFPLR5_0_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR5_0_MSI_MSG_ADDR_HI                                                                    0x40142a
+#define regBIFPLR5_0_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR5_0_MSI_MSG_DATA                                                                       0x40142a
+#define regBIFPLR5_0_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR5_0_MSI_MSG_DATA_64                                                                    0x40142b
+#define regBIFPLR5_0_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR5_0_SSID_CAP_LIST                                                                      0x401430
+#define regBIFPLR5_0_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR5_0_SSID_CAP                                                                           0x401431
+#define regBIFPLR5_0_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR5_0_MSI_MAP_CAP_LIST                                                                   0x401432
+#define regBIFPLR5_0_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR5_0_MSI_MAP_CAP                                                                        0x401432
+#define regBIFPLR5_0_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x401440
+#define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR                                                           0x401441
+#define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC1                                                              0x401442
+#define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC2                                                              0x401443
+#define regBIFPLR5_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR5_0_PCIE_VC_ENH_CAP_LIST                                                               0x401444
+#define regBIFPLR5_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_PORT_VC_CAP_REG1                                                              0x401445
+#define regBIFPLR5_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR5_0_PCIE_PORT_VC_CAP_REG2                                                              0x401446
+#define regBIFPLR5_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR5_0_PCIE_PORT_VC_CNTL                                                                  0x401447
+#define regBIFPLR5_0_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR5_0_PCIE_PORT_VC_STATUS                                                                0x401447
+#define regBIFPLR5_0_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR5_0_PCIE_VC0_RESOURCE_CAP                                                              0x401448
+#define regBIFPLR5_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR5_0_PCIE_VC0_RESOURCE_CNTL                                                             0x401449
+#define regBIFPLR5_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR5_0_PCIE_VC0_RESOURCE_STATUS                                                           0x40144a
+#define regBIFPLR5_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR5_0_PCIE_VC1_RESOURCE_CAP                                                              0x40144b
+#define regBIFPLR5_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR5_0_PCIE_VC1_RESOURCE_CNTL                                                             0x40144c
+#define regBIFPLR5_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR5_0_PCIE_VC1_RESOURCE_STATUS                                                           0x40144d
+#define regBIFPLR5_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x401450
+#define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1                                                            0x401451
+#define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2                                                            0x401452
+#define regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x401454
+#define regBIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_UNCORR_ERR_STATUS                                                             0x401455
+#define regBIFPLR5_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR5_0_PCIE_UNCORR_ERR_MASK                                                               0x401456
+#define regBIFPLR5_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY                                                           0x401457
+#define regBIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR5_0_PCIE_CORR_ERR_STATUS                                                               0x401458
+#define regBIFPLR5_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_CORR_ERR_MASK                                                                 0x401459
+#define regBIFPLR5_0_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL                                                              0x40145a
+#define regBIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR5_0_PCIE_HDR_LOG0                                                                      0x40145b
+#define regBIFPLR5_0_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR5_0_PCIE_HDR_LOG1                                                                      0x40145c
+#define regBIFPLR5_0_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR5_0_PCIE_HDR_LOG2                                                                      0x40145d
+#define regBIFPLR5_0_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR5_0_PCIE_HDR_LOG3                                                                      0x40145e
+#define regBIFPLR5_0_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR5_0_PCIE_ROOT_ERR_CMD                                                                  0x40145f
+#define regBIFPLR5_0_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR5_0_PCIE_ROOT_ERR_STATUS                                                               0x401460
+#define regBIFPLR5_0_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_ERR_SRC_ID                                                                    0x401461
+#define regBIFPLR5_0_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG0                                                               0x401462
+#define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG1                                                               0x401463
+#define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG2                                                               0x401464
+#define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG3                                                               0x401465
+#define regBIFPLR5_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x40149c
+#define regBIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR5_0_PCIE_LINK_CNTL3                                                                    0x40149d
+#define regBIFPLR5_0_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR5_0_PCIE_LANE_ERROR_STATUS                                                             0x40149e
+#define regBIFPLR5_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x40149f
+#define regBIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x40149f
+#define regBIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x4014a0
+#define regBIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x4014a0
+#define regBIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x4014a1
+#define regBIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x4014a1
+#define regBIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x4014a2
+#define regBIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x4014a2
+#define regBIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x4014a3
+#define regBIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x4014a3
+#define regBIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x4014a4
+#define regBIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x4014a4
+#define regBIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x4014a5
+#define regBIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x4014a5
+#define regBIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x4014a6
+#define regBIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x4014a6
+#define regBIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_0_PCIE_ACS_ENH_CAP_LIST                                                              0x4014a8
+#define regBIFPLR5_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR5_0_PCIE_ACS_CAP                                                                       0x4014a9
+#define regBIFPLR5_0_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR5_0_PCIE_ACS_CNTL                                                                      0x4014a9
+#define regBIFPLR5_0_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR5_0_PCIE_MC_ENH_CAP_LIST                                                               0x4014bc
+#define regBIFPLR5_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_MC_CAP                                                                        0x4014bd
+#define regBIFPLR5_0_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR5_0_PCIE_MC_CNTL                                                                       0x4014bd
+#define regBIFPLR5_0_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR5_0_PCIE_MC_ADDR0                                                                      0x4014be
+#define regBIFPLR5_0_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR5_0_PCIE_MC_ADDR1                                                                      0x4014bf
+#define regBIFPLR5_0_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR5_0_PCIE_MC_RCV0                                                                       0x4014c0
+#define regBIFPLR5_0_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR5_0_PCIE_MC_RCV1                                                                       0x4014c1
+#define regBIFPLR5_0_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR5_0_PCIE_MC_BLOCK_ALL0                                                                 0x4014c2
+#define regBIFPLR5_0_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR5_0_PCIE_MC_BLOCK_ALL1                                                                 0x4014c3
+#define regBIFPLR5_0_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x4014c4
+#define regBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x4014c5
+#define regBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR5_0_PCIE_MC_OVERLAY_BAR0                                                               0x4014c6
+#define regBIFPLR5_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_MC_OVERLAY_BAR1                                                               0x4014c7
+#define regBIFPLR5_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST                                                            0x4014dc
+#define regBIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR5_0_PCIE_L1_PM_SUB_CAP                                                                 0x4014dd
+#define regBIFPLR5_0_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR5_0_PCIE_L1_PM_SUB_CNTL                                                                0x4014de
+#define regBIFPLR5_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR5_0_PCIE_L1_PM_SUB_CNTL2                                                               0x4014df
+#define regBIFPLR5_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_DPC_ENH_CAP_LIST                                                              0x4014e0
+#define regBIFPLR5_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR5_0_PCIE_DPC_CAP_LIST                                                                  0x4014e1
+#define regBIFPLR5_0_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR5_0_PCIE_DPC_CNTL                                                                      0x4014e1
+#define regBIFPLR5_0_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR5_0_PCIE_DPC_STATUS                                                                    0x4014e2
+#define regBIFPLR5_0_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID                                                           0x4014e2
+#define regBIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR5_0_PCIE_RP_PIO_STATUS                                                                 0x4014e3
+#define regBIFPLR5_0_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR5_0_PCIE_RP_PIO_MASK                                                                   0x4014e4
+#define regBIFPLR5_0_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR5_0_PCIE_RP_PIO_SEVERITY                                                               0x4014e5
+#define regBIFPLR5_0_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_RP_PIO_SYSERROR                                                               0x4014e6
+#define regBIFPLR5_0_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_RP_PIO_EXCEPTION                                                              0x4014e7
+#define regBIFPLR5_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG0                                                               0x4014e8
+#define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG1                                                               0x4014e9
+#define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG2                                                               0x4014ea
+#define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG3                                                               0x4014eb
+#define regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0                                                            0x4014ed
+#define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1                                                            0x4014ee
+#define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2                                                            0x4014ef
+#define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3                                                            0x4014f0
+#define regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR5_0_PCIE_ESM_CAP_LIST                                                                  0x4014f1
+#define regBIFPLR5_0_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR5_0_PCIE_ESM_HEADER_1                                                                  0x4014f2
+#define regBIFPLR5_0_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR5_0_PCIE_ESM_HEADER_2                                                                  0x4014f3
+#define regBIFPLR5_0_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR5_0_PCIE_ESM_STATUS                                                                    0x4014f3
+#define regBIFPLR5_0_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR5_0_PCIE_ESM_CTRL                                                                      0x4014f4
+#define regBIFPLR5_0_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR5_0_PCIE_ESM_CAP_1                                                                     0x4014f5
+#define regBIFPLR5_0_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR5_0_PCIE_ESM_CAP_2                                                                     0x4014f6
+#define regBIFPLR5_0_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR5_0_PCIE_ESM_CAP_3                                                                     0x4014f7
+#define regBIFPLR5_0_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR5_0_PCIE_ESM_CAP_4                                                                     0x4014f8
+#define regBIFPLR5_0_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR5_0_PCIE_ESM_CAP_5                                                                     0x4014f9
+#define regBIFPLR5_0_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR5_0_PCIE_ESM_CAP_6                                                                     0x4014fa
+#define regBIFPLR5_0_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR5_0_PCIE_ESM_CAP_7                                                                     0x4014fb
+#define regBIFPLR5_0_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR5_0_PCIE_DLF_ENH_CAP_LIST                                                              0x401500
+#define regBIFPLR5_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR5_0_DATA_LINK_FEATURE_CAP                                                              0x401501
+#define regBIFPLR5_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR5_0_DATA_LINK_FEATURE_STATUS                                                           0x401502
+#define regBIFPLR5_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x401504
+#define regBIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR5_0_LINK_CAP_16GT                                                                      0x401505
+#define regBIFPLR5_0_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR5_0_LINK_CNTL_16GT                                                                     0x401506
+#define regBIFPLR5_0_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR5_0_LINK_STATUS_16GT                                                                   0x401507
+#define regBIFPLR5_0_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR5_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x401508
+#define regBIFPLR5_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR5_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x401509
+#define regBIFPLR5_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR5_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x40150a
+#define regBIFPLR5_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x40150c
+#define regBIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x40150c
+#define regBIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x40150c
+#define regBIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x40150c
+#define regBIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x40150d
+#define regBIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x40150d
+#define regBIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x40150d
+#define regBIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x40150d
+#define regBIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x40150e
+#define regBIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x40150e
+#define regBIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x40150e
+#define regBIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x40150e
+#define regBIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x40150f
+#define regBIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x40150f
+#define regBIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x40150f
+#define regBIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x40150f
+#define regBIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST                                                        0x401510
+#define regBIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR5_0_MARGINING_PORT_CAP                                                                 0x401511
+#define regBIFPLR5_0_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR5_0_MARGINING_PORT_STATUS                                                              0x401511
+#define regBIFPLR5_0_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR5_0_LANE_0_MARGINING_LANE_CNTL                                                         0x401512
+#define regBIFPLR5_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_0_LANE_0_MARGINING_LANE_STATUS                                                       0x401512
+#define regBIFPLR5_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_0_LANE_1_MARGINING_LANE_CNTL                                                         0x401513
+#define regBIFPLR5_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_0_LANE_1_MARGINING_LANE_STATUS                                                       0x401513
+#define regBIFPLR5_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_0_LANE_2_MARGINING_LANE_CNTL                                                         0x401514
+#define regBIFPLR5_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_0_LANE_2_MARGINING_LANE_STATUS                                                       0x401514
+#define regBIFPLR5_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_0_LANE_3_MARGINING_LANE_CNTL                                                         0x401515
+#define regBIFPLR5_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_0_LANE_3_MARGINING_LANE_STATUS                                                       0x401515
+#define regBIFPLR5_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_0_LANE_4_MARGINING_LANE_CNTL                                                         0x401516
+#define regBIFPLR5_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_0_LANE_4_MARGINING_LANE_STATUS                                                       0x401516
+#define regBIFPLR5_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_0_LANE_5_MARGINING_LANE_CNTL                                                         0x401517
+#define regBIFPLR5_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_0_LANE_5_MARGINING_LANE_STATUS                                                       0x401517
+#define regBIFPLR5_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_0_LANE_6_MARGINING_LANE_CNTL                                                         0x401518
+#define regBIFPLR5_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_0_LANE_6_MARGINING_LANE_STATUS                                                       0x401518
+#define regBIFPLR5_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_0_LANE_7_MARGINING_LANE_CNTL                                                         0x401519
+#define regBIFPLR5_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_0_LANE_7_MARGINING_LANE_STATUS                                                       0x401519
+#define regBIFPLR5_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_0_LANE_8_MARGINING_LANE_CNTL                                                         0x40151a
+#define regBIFPLR5_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_0_LANE_8_MARGINING_LANE_STATUS                                                       0x40151a
+#define regBIFPLR5_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_0_LANE_9_MARGINING_LANE_CNTL                                                         0x40151b
+#define regBIFPLR5_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_0_LANE_9_MARGINING_LANE_STATUS                                                       0x40151b
+#define regBIFPLR5_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_0_LANE_10_MARGINING_LANE_CNTL                                                        0x40151c
+#define regBIFPLR5_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_0_LANE_10_MARGINING_LANE_STATUS                                                      0x40151c
+#define regBIFPLR5_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_11_MARGINING_LANE_CNTL                                                        0x40151d
+#define regBIFPLR5_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_0_LANE_11_MARGINING_LANE_STATUS                                                      0x40151d
+#define regBIFPLR5_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_12_MARGINING_LANE_CNTL                                                        0x40151e
+#define regBIFPLR5_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_0_LANE_12_MARGINING_LANE_STATUS                                                      0x40151e
+#define regBIFPLR5_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_13_MARGINING_LANE_CNTL                                                        0x40151f
+#define regBIFPLR5_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_0_LANE_13_MARGINING_LANE_STATUS                                                      0x40151f
+#define regBIFPLR5_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_14_MARGINING_LANE_CNTL                                                        0x401520
+#define regBIFPLR5_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_0_LANE_14_MARGINING_LANE_STATUS                                                      0x401520
+#define regBIFPLR5_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_0_LANE_15_MARGINING_LANE_CNTL                                                        0x401521
+#define regBIFPLR5_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_0_LANE_15_MARGINING_LANE_STATUS                                                      0x401521
+#define regBIFPLR5_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_0_PCIE_CCIX_CAP_LIST                                                                 0x401522
+#define regBIFPLR5_0_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR5_0_PCIE_CCIX_HEADER_1                                                                 0x401523
+#define regBIFPLR5_0_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR5_0_PCIE_CCIX_HEADER_2                                                                 0x401524
+#define regBIFPLR5_0_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR5_0_PCIE_CCIX_CAP                                                                      0x401524
+#define regBIFPLR5_0_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP                                                             0x401525
+#define regBIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR5_0_PCIE_CCIX_ESM_OPTL_CAP                                                             0x401526
+#define regBIFPLR5_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR5_0_PCIE_CCIX_ESM_STATUS                                                               0x401527
+#define regBIFPLR5_0_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR5_0_PCIE_CCIX_ESM_CNTL                                                                 0x401528
+#define regBIFPLR5_0_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x401529
+#define regBIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x401529
+#define regBIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x401529
+#define regBIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x401529
+#define regBIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x40152a
+#define regBIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x40152a
+#define regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x40152a
+#define regBIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x40152a
+#define regBIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x40152b
+#define regBIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x40152b
+#define regBIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x40152b
+#define regBIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x40152b
+#define regBIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x40152c
+#define regBIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x40152c
+#define regBIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x40152c
+#define regBIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x40152c
+#define regBIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x40152d
+#define regBIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x40152d
+#define regBIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x40152d
+#define regBIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x40152d
+#define regBIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x40152e
+#define regBIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x40152e
+#define regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x40152e
+#define regBIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x40152e
+#define regBIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x40152f
+#define regBIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x40152f
+#define regBIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x40152f
+#define regBIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x40152f
+#define regBIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x401530
+#define regBIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x401530
+#define regBIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x401530
+#define regBIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x401530
+#define regBIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_0_PCIE_CCIX_TRANS_CAP                                                                0x401531
+#define regBIFPLR5_0_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR5_0_PCIE_CCIX_TRANS_CNTL                                                               0x401532
+#define regBIFPLR5_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+// base address: 0x11106000
+#define regBIFPLR6_0_VENDOR_ID                                                                          0x401800
+#define regBIFPLR6_0_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR6_0_DEVICE_ID                                                                          0x401800
+#define regBIFPLR6_0_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR6_0_COMMAND                                                                            0x401801
+#define regBIFPLR6_0_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR6_0_STATUS                                                                             0x401801
+#define regBIFPLR6_0_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR6_0_REVISION_ID                                                                        0x401802
+#define regBIFPLR6_0_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR6_0_PROG_INTERFACE                                                                     0x401802
+#define regBIFPLR6_0_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR6_0_SUB_CLASS                                                                          0x401802
+#define regBIFPLR6_0_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR6_0_BASE_CLASS                                                                         0x401802
+#define regBIFPLR6_0_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR6_0_CACHE_LINE                                                                         0x401803
+#define regBIFPLR6_0_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR6_0_LATENCY                                                                            0x401803
+#define regBIFPLR6_0_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR6_0_HEADER                                                                             0x401803
+#define regBIFPLR6_0_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR6_0_BIST                                                                               0x401803
+#define regBIFPLR6_0_BIST_BASE_IDX                                                                      5
+#define regBIFPLR6_0_SUB_BUS_NUMBER_LATENCY                                                             0x401806
+#define regBIFPLR6_0_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR6_0_IO_BASE_LIMIT                                                                      0x401807
+#define regBIFPLR6_0_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR6_0_SECONDARY_STATUS                                                                   0x401807
+#define regBIFPLR6_0_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR6_0_MEM_BASE_LIMIT                                                                     0x401808
+#define regBIFPLR6_0_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR6_0_PREF_BASE_LIMIT                                                                    0x401809
+#define regBIFPLR6_0_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR6_0_PREF_BASE_UPPER                                                                    0x40180a
+#define regBIFPLR6_0_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR6_0_PREF_LIMIT_UPPER                                                                   0x40180b
+#define regBIFPLR6_0_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR6_0_IO_BASE_LIMIT_HI                                                                   0x40180c
+#define regBIFPLR6_0_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR6_0_CAP_PTR                                                                            0x40180d
+#define regBIFPLR6_0_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR6_0_ROM_BASE_ADDR                                                                      0x40180e
+#define regBIFPLR6_0_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR6_0_INTERRUPT_LINE                                                                     0x40180f
+#define regBIFPLR6_0_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR6_0_INTERRUPT_PIN                                                                      0x40180f
+#define regBIFPLR6_0_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR6_0_IRQ_BRIDGE_CNTL                                                                    0x40180f
+#define regBIFPLR6_0_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR6_0_EXT_BRIDGE_CNTL                                                                    0x401810
+#define regBIFPLR6_0_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR6_0_VENDOR_CAP_LIST                                                                    0x401812
+#define regBIFPLR6_0_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR6_0_ADAPTER_ID_W                                                                       0x401813
+#define regBIFPLR6_0_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR6_0_PMI_CAP_LIST                                                                       0x401814
+#define regBIFPLR6_0_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR6_0_PMI_CAP                                                                            0x401814
+#define regBIFPLR6_0_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR6_0_PMI_STATUS_CNTL                                                                    0x401815
+#define regBIFPLR6_0_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR6_0_PCIE_CAP_LIST                                                                      0x401816
+#define regBIFPLR6_0_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR6_0_PCIE_CAP                                                                           0x401816
+#define regBIFPLR6_0_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR6_0_DEVICE_CAP                                                                         0x401817
+#define regBIFPLR6_0_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR6_0_DEVICE_CNTL                                                                        0x401818
+#define regBIFPLR6_0_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR6_0_DEVICE_STATUS                                                                      0x401818
+#define regBIFPLR6_0_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR6_0_LINK_CAP                                                                           0x401819
+#define regBIFPLR6_0_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR6_0_LINK_CNTL                                                                          0x40181a
+#define regBIFPLR6_0_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR6_0_LINK_STATUS                                                                        0x40181a
+#define regBIFPLR6_0_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR6_0_SLOT_CAP                                                                           0x40181b
+#define regBIFPLR6_0_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR6_0_SLOT_CNTL                                                                          0x40181c
+#define regBIFPLR6_0_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR6_0_SLOT_STATUS                                                                        0x40181c
+#define regBIFPLR6_0_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR6_0_ROOT_CNTL                                                                          0x40181d
+#define regBIFPLR6_0_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR6_0_ROOT_CAP                                                                           0x40181d
+#define regBIFPLR6_0_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR6_0_ROOT_STATUS                                                                        0x40181e
+#define regBIFPLR6_0_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR6_0_DEVICE_CAP2                                                                        0x40181f
+#define regBIFPLR6_0_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR6_0_DEVICE_CNTL2                                                                       0x401820
+#define regBIFPLR6_0_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR6_0_DEVICE_STATUS2                                                                     0x401820
+#define regBIFPLR6_0_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR6_0_LINK_CAP2                                                                          0x401821
+#define regBIFPLR6_0_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR6_0_LINK_CNTL2                                                                         0x401822
+#define regBIFPLR6_0_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR6_0_LINK_STATUS2                                                                       0x401822
+#define regBIFPLR6_0_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR6_0_SLOT_CAP2                                                                          0x401823
+#define regBIFPLR6_0_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR6_0_SLOT_CNTL2                                                                         0x401824
+#define regBIFPLR6_0_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR6_0_SLOT_STATUS2                                                                       0x401824
+#define regBIFPLR6_0_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR6_0_MSI_CAP_LIST                                                                       0x401828
+#define regBIFPLR6_0_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR6_0_MSI_MSG_CNTL                                                                       0x401828
+#define regBIFPLR6_0_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR6_0_MSI_MSG_ADDR_LO                                                                    0x401829
+#define regBIFPLR6_0_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR6_0_MSI_MSG_ADDR_HI                                                                    0x40182a
+#define regBIFPLR6_0_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR6_0_MSI_MSG_DATA                                                                       0x40182a
+#define regBIFPLR6_0_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR6_0_MSI_MSG_DATA_64                                                                    0x40182b
+#define regBIFPLR6_0_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR6_0_SSID_CAP_LIST                                                                      0x401830
+#define regBIFPLR6_0_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR6_0_SSID_CAP                                                                           0x401831
+#define regBIFPLR6_0_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR6_0_MSI_MAP_CAP_LIST                                                                   0x401832
+#define regBIFPLR6_0_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR6_0_MSI_MAP_CAP                                                                        0x401832
+#define regBIFPLR6_0_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x401840
+#define regBIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR                                                           0x401841
+#define regBIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR6_0_PCIE_VENDOR_SPECIFIC1                                                              0x401842
+#define regBIFPLR6_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR6_0_PCIE_VENDOR_SPECIFIC2                                                              0x401843
+#define regBIFPLR6_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR6_0_PCIE_VC_ENH_CAP_LIST                                                               0x401844
+#define regBIFPLR6_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_PORT_VC_CAP_REG1                                                              0x401845
+#define regBIFPLR6_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR6_0_PCIE_PORT_VC_CAP_REG2                                                              0x401846
+#define regBIFPLR6_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR6_0_PCIE_PORT_VC_CNTL                                                                  0x401847
+#define regBIFPLR6_0_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR6_0_PCIE_PORT_VC_STATUS                                                                0x401847
+#define regBIFPLR6_0_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR6_0_PCIE_VC0_RESOURCE_CAP                                                              0x401848
+#define regBIFPLR6_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR6_0_PCIE_VC0_RESOURCE_CNTL                                                             0x401849
+#define regBIFPLR6_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR6_0_PCIE_VC0_RESOURCE_STATUS                                                           0x40184a
+#define regBIFPLR6_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR6_0_PCIE_VC1_RESOURCE_CAP                                                              0x40184b
+#define regBIFPLR6_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR6_0_PCIE_VC1_RESOURCE_CNTL                                                             0x40184c
+#define regBIFPLR6_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR6_0_PCIE_VC1_RESOURCE_STATUS                                                           0x40184d
+#define regBIFPLR6_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x401850
+#define regBIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1                                                            0x401851
+#define regBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2                                                            0x401852
+#define regBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x401854
+#define regBIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_UNCORR_ERR_STATUS                                                             0x401855
+#define regBIFPLR6_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR6_0_PCIE_UNCORR_ERR_MASK                                                               0x401856
+#define regBIFPLR6_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY                                                           0x401857
+#define regBIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR6_0_PCIE_CORR_ERR_STATUS                                                               0x401858
+#define regBIFPLR6_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_CORR_ERR_MASK                                                                 0x401859
+#define regBIFPLR6_0_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL                                                              0x40185a
+#define regBIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR6_0_PCIE_HDR_LOG0                                                                      0x40185b
+#define regBIFPLR6_0_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR6_0_PCIE_HDR_LOG1                                                                      0x40185c
+#define regBIFPLR6_0_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR6_0_PCIE_HDR_LOG2                                                                      0x40185d
+#define regBIFPLR6_0_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR6_0_PCIE_HDR_LOG3                                                                      0x40185e
+#define regBIFPLR6_0_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR6_0_PCIE_ROOT_ERR_CMD                                                                  0x40185f
+#define regBIFPLR6_0_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR6_0_PCIE_ROOT_ERR_STATUS                                                               0x401860
+#define regBIFPLR6_0_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_ERR_SRC_ID                                                                    0x401861
+#define regBIFPLR6_0_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR6_0_PCIE_TLP_PREFIX_LOG0                                                               0x401862
+#define regBIFPLR6_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_TLP_PREFIX_LOG1                                                               0x401863
+#define regBIFPLR6_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_TLP_PREFIX_LOG2                                                               0x401864
+#define regBIFPLR6_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_TLP_PREFIX_LOG3                                                               0x401865
+#define regBIFPLR6_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x40189c
+#define regBIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR6_0_PCIE_LINK_CNTL3                                                                    0x40189d
+#define regBIFPLR6_0_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR6_0_PCIE_LANE_ERROR_STATUS                                                             0x40189e
+#define regBIFPLR6_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x40189f
+#define regBIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x40189f
+#define regBIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x4018a0
+#define regBIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x4018a0
+#define regBIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x4018a1
+#define regBIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x4018a1
+#define regBIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x4018a2
+#define regBIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x4018a2
+#define regBIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x4018a3
+#define regBIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x4018a3
+#define regBIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x4018a4
+#define regBIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x4018a4
+#define regBIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x4018a5
+#define regBIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x4018a5
+#define regBIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x4018a6
+#define regBIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x4018a6
+#define regBIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_0_PCIE_ACS_ENH_CAP_LIST                                                              0x4018a8
+#define regBIFPLR6_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR6_0_PCIE_ACS_CAP                                                                       0x4018a9
+#define regBIFPLR6_0_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR6_0_PCIE_ACS_CNTL                                                                      0x4018a9
+#define regBIFPLR6_0_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR6_0_PCIE_MC_ENH_CAP_LIST                                                               0x4018bc
+#define regBIFPLR6_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_MC_CAP                                                                        0x4018bd
+#define regBIFPLR6_0_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR6_0_PCIE_MC_CNTL                                                                       0x4018bd
+#define regBIFPLR6_0_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR6_0_PCIE_MC_ADDR0                                                                      0x4018be
+#define regBIFPLR6_0_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR6_0_PCIE_MC_ADDR1                                                                      0x4018bf
+#define regBIFPLR6_0_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR6_0_PCIE_MC_RCV0                                                                       0x4018c0
+#define regBIFPLR6_0_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR6_0_PCIE_MC_RCV1                                                                       0x4018c1
+#define regBIFPLR6_0_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR6_0_PCIE_MC_BLOCK_ALL0                                                                 0x4018c2
+#define regBIFPLR6_0_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR6_0_PCIE_MC_BLOCK_ALL1                                                                 0x4018c3
+#define regBIFPLR6_0_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x4018c4
+#define regBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x4018c5
+#define regBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR6_0_PCIE_MC_OVERLAY_BAR0                                                               0x4018c6
+#define regBIFPLR6_0_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_MC_OVERLAY_BAR1                                                               0x4018c7
+#define regBIFPLR6_0_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST                                                            0x4018dc
+#define regBIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR6_0_PCIE_L1_PM_SUB_CAP                                                                 0x4018dd
+#define regBIFPLR6_0_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR6_0_PCIE_L1_PM_SUB_CNTL                                                                0x4018de
+#define regBIFPLR6_0_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR6_0_PCIE_L1_PM_SUB_CNTL2                                                               0x4018df
+#define regBIFPLR6_0_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_DPC_ENH_CAP_LIST                                                              0x4018e0
+#define regBIFPLR6_0_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR6_0_PCIE_DPC_CAP_LIST                                                                  0x4018e1
+#define regBIFPLR6_0_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR6_0_PCIE_DPC_CNTL                                                                      0x4018e1
+#define regBIFPLR6_0_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR6_0_PCIE_DPC_STATUS                                                                    0x4018e2
+#define regBIFPLR6_0_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID                                                           0x4018e2
+#define regBIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR6_0_PCIE_RP_PIO_STATUS                                                                 0x4018e3
+#define regBIFPLR6_0_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR6_0_PCIE_RP_PIO_MASK                                                                   0x4018e4
+#define regBIFPLR6_0_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR6_0_PCIE_RP_PIO_SEVERITY                                                               0x4018e5
+#define regBIFPLR6_0_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_RP_PIO_SYSERROR                                                               0x4018e6
+#define regBIFPLR6_0_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_RP_PIO_EXCEPTION                                                              0x4018e7
+#define regBIFPLR6_0_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG0                                                               0x4018e8
+#define regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG1                                                               0x4018e9
+#define regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG2                                                               0x4018ea
+#define regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG3                                                               0x4018eb
+#define regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0                                                            0x4018ed
+#define regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1                                                            0x4018ee
+#define regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2                                                            0x4018ef
+#define regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3                                                            0x4018f0
+#define regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR6_0_PCIE_ESM_CAP_LIST                                                                  0x4018f1
+#define regBIFPLR6_0_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR6_0_PCIE_ESM_HEADER_1                                                                  0x4018f2
+#define regBIFPLR6_0_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR6_0_PCIE_ESM_HEADER_2                                                                  0x4018f3
+#define regBIFPLR6_0_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR6_0_PCIE_ESM_STATUS                                                                    0x4018f3
+#define regBIFPLR6_0_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR6_0_PCIE_ESM_CTRL                                                                      0x4018f4
+#define regBIFPLR6_0_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR6_0_PCIE_ESM_CAP_1                                                                     0x4018f5
+#define regBIFPLR6_0_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR6_0_PCIE_ESM_CAP_2                                                                     0x4018f6
+#define regBIFPLR6_0_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR6_0_PCIE_ESM_CAP_3                                                                     0x4018f7
+#define regBIFPLR6_0_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR6_0_PCIE_ESM_CAP_4                                                                     0x4018f8
+#define regBIFPLR6_0_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR6_0_PCIE_ESM_CAP_5                                                                     0x4018f9
+#define regBIFPLR6_0_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR6_0_PCIE_ESM_CAP_6                                                                     0x4018fa
+#define regBIFPLR6_0_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR6_0_PCIE_ESM_CAP_7                                                                     0x4018fb
+#define regBIFPLR6_0_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR6_0_PCIE_DLF_ENH_CAP_LIST                                                              0x401900
+#define regBIFPLR6_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR6_0_DATA_LINK_FEATURE_CAP                                                              0x401901
+#define regBIFPLR6_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR6_0_DATA_LINK_FEATURE_STATUS                                                           0x401902
+#define regBIFPLR6_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x401904
+#define regBIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR6_0_LINK_CAP_16GT                                                                      0x401905
+#define regBIFPLR6_0_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR6_0_LINK_CNTL_16GT                                                                     0x401906
+#define regBIFPLR6_0_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR6_0_LINK_STATUS_16GT                                                                   0x401907
+#define regBIFPLR6_0_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR6_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x401908
+#define regBIFPLR6_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR6_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x401909
+#define regBIFPLR6_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR6_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x40190a
+#define regBIFPLR6_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x40190c
+#define regBIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x40190c
+#define regBIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x40190c
+#define regBIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x40190c
+#define regBIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x40190d
+#define regBIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x40190d
+#define regBIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x40190d
+#define regBIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x40190d
+#define regBIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x40190e
+#define regBIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x40190e
+#define regBIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x40190e
+#define regBIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x40190e
+#define regBIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x40190f
+#define regBIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x40190f
+#define regBIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x40190f
+#define regBIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x40190f
+#define regBIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST                                                        0x401910
+#define regBIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR6_0_MARGINING_PORT_CAP                                                                 0x401911
+#define regBIFPLR6_0_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR6_0_MARGINING_PORT_STATUS                                                              0x401911
+#define regBIFPLR6_0_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR6_0_LANE_0_MARGINING_LANE_CNTL                                                         0x401912
+#define regBIFPLR6_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_0_LANE_0_MARGINING_LANE_STATUS                                                       0x401912
+#define regBIFPLR6_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_0_LANE_1_MARGINING_LANE_CNTL                                                         0x401913
+#define regBIFPLR6_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_0_LANE_1_MARGINING_LANE_STATUS                                                       0x401913
+#define regBIFPLR6_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_0_LANE_2_MARGINING_LANE_CNTL                                                         0x401914
+#define regBIFPLR6_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_0_LANE_2_MARGINING_LANE_STATUS                                                       0x401914
+#define regBIFPLR6_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_0_LANE_3_MARGINING_LANE_CNTL                                                         0x401915
+#define regBIFPLR6_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_0_LANE_3_MARGINING_LANE_STATUS                                                       0x401915
+#define regBIFPLR6_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_0_LANE_4_MARGINING_LANE_CNTL                                                         0x401916
+#define regBIFPLR6_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_0_LANE_4_MARGINING_LANE_STATUS                                                       0x401916
+#define regBIFPLR6_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_0_LANE_5_MARGINING_LANE_CNTL                                                         0x401917
+#define regBIFPLR6_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_0_LANE_5_MARGINING_LANE_STATUS                                                       0x401917
+#define regBIFPLR6_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_0_LANE_6_MARGINING_LANE_CNTL                                                         0x401918
+#define regBIFPLR6_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_0_LANE_6_MARGINING_LANE_STATUS                                                       0x401918
+#define regBIFPLR6_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_0_LANE_7_MARGINING_LANE_CNTL                                                         0x401919
+#define regBIFPLR6_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_0_LANE_7_MARGINING_LANE_STATUS                                                       0x401919
+#define regBIFPLR6_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_0_LANE_8_MARGINING_LANE_CNTL                                                         0x40191a
+#define regBIFPLR6_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_0_LANE_8_MARGINING_LANE_STATUS                                                       0x40191a
+#define regBIFPLR6_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_0_LANE_9_MARGINING_LANE_CNTL                                                         0x40191b
+#define regBIFPLR6_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_0_LANE_9_MARGINING_LANE_STATUS                                                       0x40191b
+#define regBIFPLR6_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_0_LANE_10_MARGINING_LANE_CNTL                                                        0x40191c
+#define regBIFPLR6_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_0_LANE_10_MARGINING_LANE_STATUS                                                      0x40191c
+#define regBIFPLR6_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_11_MARGINING_LANE_CNTL                                                        0x40191d
+#define regBIFPLR6_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_0_LANE_11_MARGINING_LANE_STATUS                                                      0x40191d
+#define regBIFPLR6_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_12_MARGINING_LANE_CNTL                                                        0x40191e
+#define regBIFPLR6_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_0_LANE_12_MARGINING_LANE_STATUS                                                      0x40191e
+#define regBIFPLR6_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_13_MARGINING_LANE_CNTL                                                        0x40191f
+#define regBIFPLR6_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_0_LANE_13_MARGINING_LANE_STATUS                                                      0x40191f
+#define regBIFPLR6_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_14_MARGINING_LANE_CNTL                                                        0x401920
+#define regBIFPLR6_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_0_LANE_14_MARGINING_LANE_STATUS                                                      0x401920
+#define regBIFPLR6_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_0_LANE_15_MARGINING_LANE_CNTL                                                        0x401921
+#define regBIFPLR6_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_0_LANE_15_MARGINING_LANE_STATUS                                                      0x401921
+#define regBIFPLR6_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_0_PCIE_CCIX_CAP_LIST                                                                 0x401922
+#define regBIFPLR6_0_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR6_0_PCIE_CCIX_HEADER_1                                                                 0x401923
+#define regBIFPLR6_0_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR6_0_PCIE_CCIX_HEADER_2                                                                 0x401924
+#define regBIFPLR6_0_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR6_0_PCIE_CCIX_CAP                                                                      0x401924
+#define regBIFPLR6_0_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP                                                             0x401925
+#define regBIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR6_0_PCIE_CCIX_ESM_OPTL_CAP                                                             0x401926
+#define regBIFPLR6_0_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR6_0_PCIE_CCIX_ESM_STATUS                                                               0x401927
+#define regBIFPLR6_0_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR6_0_PCIE_CCIX_ESM_CNTL                                                                 0x401928
+#define regBIFPLR6_0_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x401929
+#define regBIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x401929
+#define regBIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x401929
+#define regBIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x401929
+#define regBIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x40192a
+#define regBIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x40192a
+#define regBIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x40192a
+#define regBIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x40192a
+#define regBIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x40192b
+#define regBIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x40192b
+#define regBIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x40192b
+#define regBIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x40192b
+#define regBIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x40192c
+#define regBIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x40192c
+#define regBIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x40192c
+#define regBIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x40192c
+#define regBIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x40192d
+#define regBIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x40192d
+#define regBIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x40192d
+#define regBIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x40192d
+#define regBIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x40192e
+#define regBIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x40192e
+#define regBIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x40192e
+#define regBIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x40192e
+#define regBIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x40192f
+#define regBIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x40192f
+#define regBIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x40192f
+#define regBIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x40192f
+#define regBIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x401930
+#define regBIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x401930
+#define regBIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x401930
+#define regBIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x401930
+#define regBIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_0_PCIE_CCIX_TRANS_CAP                                                                0x401931
+#define regBIFPLR6_0_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR6_0_PCIE_CCIX_TRANS_CNTL                                                               0x401932
+#define regBIFPLR6_0_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifp0_pciedir_p
+// base address: 0x11140000
+#define regBIFP0_PCIEP_RESERVED                                                                         0x410000
+#define regBIFP0_PCIEP_RESERVED_BASE_IDX                                                                5
+#define regBIFP0_PCIEP_SCRATCH                                                                          0x410001
+#define regBIFP0_PCIEP_SCRATCH_BASE_IDX                                                                 5
+#define regBIFP0_PCIEP_PORT_CNTL                                                                        0x410010
+#define regBIFP0_PCIEP_PORT_CNTL_BASE_IDX                                                               5
+#define regBIFP0_PCIE_TX_CNTL                                                                           0x410020
+#define regBIFP0_PCIE_TX_CNTL_BASE_IDX                                                                  5
+#define regBIFP0_PCIE_TX_REQUESTER_ID                                                                   0x410021
+#define regBIFP0_PCIE_TX_REQUESTER_ID_BASE_IDX                                                          5
+#define regBIFP0_PCIE_TX_VENDOR_SPECIFIC                                                                0x410022
+#define regBIFP0_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP0_PCIE_TX_REQUEST_NUM_CNTL                                                               0x410023
+#define regBIFP0_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX                                                      5
+#define regBIFP0_PCIE_TX_SEQ                                                                            0x410024
+#define regBIFP0_PCIE_TX_SEQ_BASE_IDX                                                                   5
+#define regBIFP0_PCIE_TX_REPLAY                                                                         0x410025
+#define regBIFP0_PCIE_TX_REPLAY_BASE_IDX                                                                5
+#define regBIFP0_PCIE_TX_ACK_LATENCY_LIMIT                                                              0x410026
+#define regBIFP0_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX                                                     5
+#define regBIFP0_PCIE_TX_NOP_DLLP                                                                       0x410027
+#define regBIFP0_PCIE_TX_NOP_DLLP_BASE_IDX                                                              5
+#define regBIFP0_PCIE_TX_CNTL_2                                                                         0x410028
+#define regBIFP0_PCIE_TX_CNTL_2_BASE_IDX                                                                5
+#define regBIFP0_PCIE_TX_SKID_CTRL                                                                      0x41002f
+#define regBIFP0_PCIE_TX_SKID_CTRL_BASE_IDX                                                             5
+#define regBIFP0_PCIE_TX_CREDITS_ADVT_P                                                                 0x410030
+#define regBIFP0_PCIE_TX_CREDITS_ADVT_P_BASE_IDX                                                        5
+#define regBIFP0_PCIE_TX_CREDITS_ADVT_NP                                                                0x410031
+#define regBIFP0_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX                                                       5
+#define regBIFP0_PCIE_TX_CREDITS_ADVT_CPL                                                               0x410032
+#define regBIFP0_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX                                                      5
+#define regBIFP0_PCIE_TX_CREDITS_INIT_P                                                                 0x410033
+#define regBIFP0_PCIE_TX_CREDITS_INIT_P_BASE_IDX                                                        5
+#define regBIFP0_PCIE_TX_CREDITS_INIT_NP                                                                0x410034
+#define regBIFP0_PCIE_TX_CREDITS_INIT_NP_BASE_IDX                                                       5
+#define regBIFP0_PCIE_TX_CREDITS_INIT_CPL                                                               0x410035
+#define regBIFP0_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX                                                      5
+#define regBIFP0_PCIE_TX_CREDITS_STATUS                                                                 0x410036
+#define regBIFP0_PCIE_TX_CREDITS_STATUS_BASE_IDX                                                        5
+#define regBIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD                                                          0x410037
+#define regBIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX                                                 5
+#define regBIFP0_PCIE_TX_CCIX_PORT_CNTL0                                                                0x410038
+#define regBIFP0_PCIE_TX_CCIX_PORT_CNTL0_BASE_IDX                                                       5
+#define regBIFP0_PCIE_TX_CCIX_PORT_CNTL1                                                                0x410039
+#define regBIFP0_PCIE_TX_CCIX_PORT_CNTL1_BASE_IDX                                                       5
+#define regBIFP0_PCIE_CCIX_STACKED_BASE                                                                 0x41003a
+#define regBIFP0_PCIE_CCIX_STACKED_BASE_BASE_IDX                                                        5
+#define regBIFP0_PCIE_CCIX_STACKED_LIMIT                                                                0x41003b
+#define regBIFP0_PCIE_CCIX_STACKED_LIMIT_BASE_IDX                                                       5
+#define regBIFP0_PCIE_CCIX_MISC_STATUS                                                                  0x410041
+#define regBIFP0_PCIE_CCIX_MISC_STATUS_BASE_IDX                                                         5
+#define regBIFP0_PCIE_P_PORT_LANE_STATUS                                                                0x410050
+#define regBIFP0_PCIE_P_PORT_LANE_STATUS_BASE_IDX                                                       5
+#define regBIFP0_PCIE_FC_P                                                                              0x410060
+#define regBIFP0_PCIE_FC_P_BASE_IDX                                                                     5
+#define regBIFP0_PCIE_FC_NP                                                                             0x410061
+#define regBIFP0_PCIE_FC_NP_BASE_IDX                                                                    5
+#define regBIFP0_PCIE_FC_CPL                                                                            0x410062
+#define regBIFP0_PCIE_FC_CPL_BASE_IDX                                                                   5
+#define regBIFP0_PCIE_FC_P_VC1                                                                          0x410063
+#define regBIFP0_PCIE_FC_P_VC1_BASE_IDX                                                                 5
+#define regBIFP0_PCIE_FC_NP_VC1                                                                         0x410064
+#define regBIFP0_PCIE_FC_NP_VC1_BASE_IDX                                                                5
+#define regBIFP0_PCIE_FC_CPL_VC1                                                                        0x410065
+#define regBIFP0_PCIE_FC_CPL_VC1_BASE_IDX                                                               5
+#define regBIFP0_PCIE_ERR_CNTL                                                                          0x41006a
+#define regBIFP0_PCIE_ERR_CNTL_BASE_IDX                                                                 5
+#define regBIFP0_PCIE_RX_CNTL                                                                           0x410070
+#define regBIFP0_PCIE_RX_CNTL_BASE_IDX                                                                  5
+#define regBIFP0_PCIE_RX_EXPECTED_SEQNUM                                                                0x410071
+#define regBIFP0_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX                                                       5
+#define regBIFP0_PCIE_RX_VENDOR_SPECIFIC                                                                0x410072
+#define regBIFP0_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP0_PCIE_RX_CNTL3                                                                          0x410074
+#define regBIFP0_PCIE_RX_CNTL3_BASE_IDX                                                                 5
+#define regBIFP0_PCIE_RX_CREDITS_ALLOCATED_P                                                            0x410080
+#define regBIFP0_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX                                                   5
+#define regBIFP0_PCIE_RX_CREDITS_ALLOCATED_NP                                                           0x410081
+#define regBIFP0_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX                                                  5
+#define regBIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL                                                          0x410082
+#define regBIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX                                                 5
+#define regBIFP0_PCIEP_ERROR_INJECT_PHYSICAL                                                            0x410083
+#define regBIFP0_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX                                                   5
+#define regBIFP0_PCIEP_ERROR_INJECT_TRANSACTION                                                         0x410084
+#define regBIFP0_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX                                                5
+#define regBIFP0_PCIEP_NAK_COUNTER                                                                      0x410086
+#define regBIFP0_PCIEP_NAK_COUNTER_BASE_IDX                                                             5
+#define regBIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS                                                      0x410088
+#define regBIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_BASE_IDX                                             5
+#define regBIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES                                                 0x410089
+#define regBIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_BASE_IDX                                        5
+#define regBIFP0_PCIE_AER_PRIV_UNCORRECTABLE_MASK                                                       0x41008c
+#define regBIFP0_PCIE_AER_PRIV_UNCORRECTABLE_MASK_BASE_IDX                                              5
+#define regBIFP0_PCIE_AER_PRIV_TRIGGER                                                                  0x41008d
+#define regBIFP0_PCIE_AER_PRIV_TRIGGER_BASE_IDX                                                         5
+#define regBIFP0_PCIE_LC_CNTL                                                                           0x4100a0
+#define regBIFP0_PCIE_LC_CNTL_BASE_IDX                                                                  5
+#define regBIFP0_PCIE_LC_TRAINING_CNTL                                                                  0x4100a1
+#define regBIFP0_PCIE_LC_TRAINING_CNTL_BASE_IDX                                                         5
+#define regBIFP0_PCIE_LC_LINK_WIDTH_CNTL                                                                0x4100a2
+#define regBIFP0_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX                                                       5
+#define regBIFP0_PCIE_LC_N_FTS_CNTL                                                                     0x4100a3
+#define regBIFP0_PCIE_LC_N_FTS_CNTL_BASE_IDX                                                            5
+#define regBIFP0_PCIE_LC_SPEED_CNTL                                                                     0x4100a4
+#define regBIFP0_PCIE_LC_SPEED_CNTL_BASE_IDX                                                            5
+#define regBIFP0_PCIE_LC_STATE0                                                                         0x4100a5
+#define regBIFP0_PCIE_LC_STATE0_BASE_IDX                                                                5
+#define regBIFP0_PCIE_LC_STATE1                                                                         0x4100a6
+#define regBIFP0_PCIE_LC_STATE1_BASE_IDX                                                                5
+#define regBIFP0_PCIE_LC_STATE2                                                                         0x4100a7
+#define regBIFP0_PCIE_LC_STATE2_BASE_IDX                                                                5
+#define regBIFP0_PCIE_LC_STATE3                                                                         0x4100a8
+#define regBIFP0_PCIE_LC_STATE3_BASE_IDX                                                                5
+#define regBIFP0_PCIE_LC_STATE4                                                                         0x4100a9
+#define regBIFP0_PCIE_LC_STATE4_BASE_IDX                                                                5
+#define regBIFP0_PCIE_LC_STATE5                                                                         0x4100aa
+#define regBIFP0_PCIE_LC_STATE5_BASE_IDX                                                                5
+#define regBIFP0_PCIE_LINK_MANAGEMENT_CNTL2                                                             0x4100ab
+#define regBIFP0_PCIE_LINK_MANAGEMENT_CNTL2_BASE_IDX                                                    5
+#define regBIFP0_PCIE_LC_CNTL2                                                                          0x4100b1
+#define regBIFP0_PCIE_LC_CNTL2_BASE_IDX                                                                 5
+#define regBIFP0_PCIE_LC_BW_CHANGE_CNTL                                                                 0x4100b2
+#define regBIFP0_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX                                                        5
+#define regBIFP0_PCIE_LC_CDR_CNTL                                                                       0x4100b3
+#define regBIFP0_PCIE_LC_CDR_CNTL_BASE_IDX                                                              5
+#define regBIFP0_PCIE_LC_LANE_CNTL                                                                      0x4100b4
+#define regBIFP0_PCIE_LC_LANE_CNTL_BASE_IDX                                                             5
+#define regBIFP0_PCIE_LC_CNTL3                                                                          0x4100b5
+#define regBIFP0_PCIE_LC_CNTL3_BASE_IDX                                                                 5
+#define regBIFP0_PCIE_LC_CNTL4                                                                          0x4100b6
+#define regBIFP0_PCIE_LC_CNTL4_BASE_IDX                                                                 5
+#define regBIFP0_PCIE_LC_CNTL5                                                                          0x4100b7
+#define regBIFP0_PCIE_LC_CNTL5_BASE_IDX                                                                 5
+#define regBIFP0_PCIE_LC_FORCE_COEFF                                                                    0x4100b8
+#define regBIFP0_PCIE_LC_FORCE_COEFF_BASE_IDX                                                           5
+#define regBIFP0_PCIE_LC_BEST_EQ_SETTINGS                                                               0x4100b9
+#define regBIFP0_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX                                                      5
+#define regBIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF                                                             0x4100ba
+#define regBIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX                                                    5
+#define regBIFP0_PCIE_LC_CNTL6                                                                          0x4100bb
+#define regBIFP0_PCIE_LC_CNTL6_BASE_IDX                                                                 5
+#define regBIFP0_PCIE_LC_CNTL7                                                                          0x4100bc
+#define regBIFP0_PCIE_LC_CNTL7_BASE_IDX                                                                 5
+#define regBIFP0_PCIE_LINK_MANAGEMENT_STATUS                                                            0x4100bd
+#define regBIFP0_PCIE_LINK_MANAGEMENT_STATUS_BASE_IDX                                                   5
+#define regBIFP0_PCIE_LINK_MANAGEMENT_MASK                                                              0x4100be
+#define regBIFP0_PCIE_LINK_MANAGEMENT_MASK_BASE_IDX                                                     5
+#define regBIFP0_PCIE_LINK_MANAGEMENT_CNTL                                                              0x4100bf
+#define regBIFP0_PCIE_LINK_MANAGEMENT_CNTL_BASE_IDX                                                     5
+#define regBIFP0_PCIEP_STRAP_LC                                                                         0x4100c0
+#define regBIFP0_PCIEP_STRAP_LC_BASE_IDX                                                                5
+#define regBIFP0_PCIEP_STRAP_MISC                                                                       0x4100c1
+#define regBIFP0_PCIEP_STRAP_MISC_BASE_IDX                                                              5
+#define regBIFP0_PCIEP_STRAP_LC2                                                                        0x4100c2
+#define regBIFP0_PCIEP_STRAP_LC2_BASE_IDX                                                               5
+#define regBIFP0_PCIE_LC_L1_PM_SUBSTATE                                                                 0x4100c6
+#define regBIFP0_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX                                                        5
+#define regBIFP0_PCIE_LC_L1_PM_SUBSTATE2                                                                0x4100c7
+#define regBIFP0_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX                                                       5
+#define regBIFP0_PCIE_LC_PORT_ORDER                                                                     0x4100c8
+#define regBIFP0_PCIE_LC_PORT_ORDER_BASE_IDX                                                            5
+#define regBIFP0_PCIEP_BCH_ECC_CNTL                                                                     0x4100d0
+#define regBIFP0_PCIEP_BCH_ECC_CNTL_BASE_IDX                                                            5
+#define regBIFP0_PCIEP_HPGI_PRIVATE                                                                     0x4100d2
+#define regBIFP0_PCIEP_HPGI_PRIVATE_BASE_IDX                                                            5
+#define regBIFP0_PCIEP_HPGI                                                                             0x4100da
+#define regBIFP0_PCIEP_HPGI_BASE_IDX                                                                    5
+#define regBIFP0_PCIEP_HCNT_DESCRIPTOR                                                                  0x4100db
+#define regBIFP0_PCIEP_HCNT_DESCRIPTOR_BASE_IDX                                                         5
+#define regBIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK                                                            0x4100dc
+#define regBIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_BASE_IDX                                                   5
+#define regBIFP0_PCIE_LC_CNTL8                                                                          0x4100dd
+#define regBIFP0_PCIE_LC_CNTL8_BASE_IDX                                                                 5
+#define regBIFP0_PCIE_LC_CNTL9                                                                          0x4100de
+#define regBIFP0_PCIE_LC_CNTL9_BASE_IDX                                                                 5
+#define regBIFP0_PCIE_LC_FORCE_COEFF2                                                                   0x4100df
+#define regBIFP0_PCIE_LC_FORCE_COEFF2_BASE_IDX                                                          5
+#define regBIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2                                                            0x4100e0
+#define regBIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX                                                   5
+#define regBIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC                                                         0x4100e1
+#define regBIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC_BASE_IDX                                                5
+#define regBIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES                                                  0x4100e2
+#define regBIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX                                         5
+#define regBIFP0_PCIE_LC_CNTL10                                                                         0x4100e3
+#define regBIFP0_PCIE_LC_CNTL10_BASE_IDX                                                                5
+#define regBIFP0_PCIE_LC_CNTL11                                                                         0x4100e4
+#define regBIFP0_PCIE_LC_CNTL11_BASE_IDX                                                                5
+#define regBIFP0_PCIE_LC_CNTL12                                                                         0x4100e5
+#define regBIFP0_PCIE_LC_CNTL12_BASE_IDX                                                                5
+#define regBIFP0_PCIE_LC_SAVE_RESTORE_1                                                                 0x4100e6
+#define regBIFP0_PCIE_LC_SAVE_RESTORE_1_BASE_IDX                                                        5
+#define regBIFP0_PCIE_LC_SAVE_RESTORE_2                                                                 0x4100e7
+#define regBIFP0_PCIE_LC_SAVE_RESTORE_2_BASE_IDX                                                        5
+#define regBIFP0_PCIE_LC_SAVE_RESTORE_3                                                                 0x4100e8
+#define regBIFP0_PCIE_LC_SAVE_RESTORE_3_BASE_IDX                                                        5
+
+
+// addressBlock: nbio_pcie0_bifp1_pciedir_p
+// base address: 0x11141000
+#define regBIFP1_PCIEP_RESERVED                                                                         0x410400
+#define regBIFP1_PCIEP_RESERVED_BASE_IDX                                                                5
+#define regBIFP1_PCIEP_SCRATCH                                                                          0x410401
+#define regBIFP1_PCIEP_SCRATCH_BASE_IDX                                                                 5
+#define regBIFP1_PCIEP_PORT_CNTL                                                                        0x410410
+#define regBIFP1_PCIEP_PORT_CNTL_BASE_IDX                                                               5
+#define regBIFP1_PCIE_TX_CNTL                                                                           0x410420
+#define regBIFP1_PCIE_TX_CNTL_BASE_IDX                                                                  5
+#define regBIFP1_PCIE_TX_REQUESTER_ID                                                                   0x410421
+#define regBIFP1_PCIE_TX_REQUESTER_ID_BASE_IDX                                                          5
+#define regBIFP1_PCIE_TX_VENDOR_SPECIFIC                                                                0x410422
+#define regBIFP1_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP1_PCIE_TX_REQUEST_NUM_CNTL                                                               0x410423
+#define regBIFP1_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX                                                      5
+#define regBIFP1_PCIE_TX_SEQ                                                                            0x410424
+#define regBIFP1_PCIE_TX_SEQ_BASE_IDX                                                                   5
+#define regBIFP1_PCIE_TX_REPLAY                                                                         0x410425
+#define regBIFP1_PCIE_TX_REPLAY_BASE_IDX                                                                5
+#define regBIFP1_PCIE_TX_ACK_LATENCY_LIMIT                                                              0x410426
+#define regBIFP1_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX                                                     5
+#define regBIFP1_PCIE_TX_NOP_DLLP                                                                       0x410427
+#define regBIFP1_PCIE_TX_NOP_DLLP_BASE_IDX                                                              5
+#define regBIFP1_PCIE_TX_CNTL_2                                                                         0x410428
+#define regBIFP1_PCIE_TX_CNTL_2_BASE_IDX                                                                5
+#define regBIFP1_PCIE_TX_SKID_CTRL                                                                      0x41042f
+#define regBIFP1_PCIE_TX_SKID_CTRL_BASE_IDX                                                             5
+#define regBIFP1_PCIE_TX_CREDITS_ADVT_P                                                                 0x410430
+#define regBIFP1_PCIE_TX_CREDITS_ADVT_P_BASE_IDX                                                        5
+#define regBIFP1_PCIE_TX_CREDITS_ADVT_NP                                                                0x410431
+#define regBIFP1_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX                                                       5
+#define regBIFP1_PCIE_TX_CREDITS_ADVT_CPL                                                               0x410432
+#define regBIFP1_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX                                                      5
+#define regBIFP1_PCIE_TX_CREDITS_INIT_P                                                                 0x410433
+#define regBIFP1_PCIE_TX_CREDITS_INIT_P_BASE_IDX                                                        5
+#define regBIFP1_PCIE_TX_CREDITS_INIT_NP                                                                0x410434
+#define regBIFP1_PCIE_TX_CREDITS_INIT_NP_BASE_IDX                                                       5
+#define regBIFP1_PCIE_TX_CREDITS_INIT_CPL                                                               0x410435
+#define regBIFP1_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX                                                      5
+#define regBIFP1_PCIE_TX_CREDITS_STATUS                                                                 0x410436
+#define regBIFP1_PCIE_TX_CREDITS_STATUS_BASE_IDX                                                        5
+#define regBIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD                                                          0x410437
+#define regBIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX                                                 5
+#define regBIFP1_PCIE_TX_CCIX_PORT_CNTL0                                                                0x410438
+#define regBIFP1_PCIE_TX_CCIX_PORT_CNTL0_BASE_IDX                                                       5
+#define regBIFP1_PCIE_TX_CCIX_PORT_CNTL1                                                                0x410439
+#define regBIFP1_PCIE_TX_CCIX_PORT_CNTL1_BASE_IDX                                                       5
+#define regBIFP1_PCIE_CCIX_STACKED_BASE                                                                 0x41043a
+#define regBIFP1_PCIE_CCIX_STACKED_BASE_BASE_IDX                                                        5
+#define regBIFP1_PCIE_CCIX_STACKED_LIMIT                                                                0x41043b
+#define regBIFP1_PCIE_CCIX_STACKED_LIMIT_BASE_IDX                                                       5
+#define regBIFP1_PCIE_CCIX_MISC_STATUS                                                                  0x410441
+#define regBIFP1_PCIE_CCIX_MISC_STATUS_BASE_IDX                                                         5
+#define regBIFP1_PCIE_P_PORT_LANE_STATUS                                                                0x410450
+#define regBIFP1_PCIE_P_PORT_LANE_STATUS_BASE_IDX                                                       5
+#define regBIFP1_PCIE_FC_P                                                                              0x410460
+#define regBIFP1_PCIE_FC_P_BASE_IDX                                                                     5
+#define regBIFP1_PCIE_FC_NP                                                                             0x410461
+#define regBIFP1_PCIE_FC_NP_BASE_IDX                                                                    5
+#define regBIFP1_PCIE_FC_CPL                                                                            0x410462
+#define regBIFP1_PCIE_FC_CPL_BASE_IDX                                                                   5
+#define regBIFP1_PCIE_FC_P_VC1                                                                          0x410463
+#define regBIFP1_PCIE_FC_P_VC1_BASE_IDX                                                                 5
+#define regBIFP1_PCIE_FC_NP_VC1                                                                         0x410464
+#define regBIFP1_PCIE_FC_NP_VC1_BASE_IDX                                                                5
+#define regBIFP1_PCIE_FC_CPL_VC1                                                                        0x410465
+#define regBIFP1_PCIE_FC_CPL_VC1_BASE_IDX                                                               5
+#define regBIFP1_PCIE_ERR_CNTL                                                                          0x41046a
+#define regBIFP1_PCIE_ERR_CNTL_BASE_IDX                                                                 5
+#define regBIFP1_PCIE_RX_CNTL                                                                           0x410470
+#define regBIFP1_PCIE_RX_CNTL_BASE_IDX                                                                  5
+#define regBIFP1_PCIE_RX_EXPECTED_SEQNUM                                                                0x410471
+#define regBIFP1_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX                                                       5
+#define regBIFP1_PCIE_RX_VENDOR_SPECIFIC                                                                0x410472
+#define regBIFP1_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP1_PCIE_RX_CNTL3                                                                          0x410474
+#define regBIFP1_PCIE_RX_CNTL3_BASE_IDX                                                                 5
+#define regBIFP1_PCIE_RX_CREDITS_ALLOCATED_P                                                            0x410480
+#define regBIFP1_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX                                                   5
+#define regBIFP1_PCIE_RX_CREDITS_ALLOCATED_NP                                                           0x410481
+#define regBIFP1_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX                                                  5
+#define regBIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL                                                          0x410482
+#define regBIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX                                                 5
+#define regBIFP1_PCIEP_ERROR_INJECT_PHYSICAL                                                            0x410483
+#define regBIFP1_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX                                                   5
+#define regBIFP1_PCIEP_ERROR_INJECT_TRANSACTION                                                         0x410484
+#define regBIFP1_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX                                                5
+#define regBIFP1_PCIEP_NAK_COUNTER                                                                      0x410486
+#define regBIFP1_PCIEP_NAK_COUNTER_BASE_IDX                                                             5
+#define regBIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS                                                      0x410488
+#define regBIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_BASE_IDX                                             5
+#define regBIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES                                                 0x410489
+#define regBIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_BASE_IDX                                        5
+#define regBIFP1_PCIE_AER_PRIV_UNCORRECTABLE_MASK                                                       0x41048c
+#define regBIFP1_PCIE_AER_PRIV_UNCORRECTABLE_MASK_BASE_IDX                                              5
+#define regBIFP1_PCIE_AER_PRIV_TRIGGER                                                                  0x41048d
+#define regBIFP1_PCIE_AER_PRIV_TRIGGER_BASE_IDX                                                         5
+#define regBIFP1_PCIE_LC_CNTL                                                                           0x4104a0
+#define regBIFP1_PCIE_LC_CNTL_BASE_IDX                                                                  5
+#define regBIFP1_PCIE_LC_TRAINING_CNTL                                                                  0x4104a1
+#define regBIFP1_PCIE_LC_TRAINING_CNTL_BASE_IDX                                                         5
+#define regBIFP1_PCIE_LC_LINK_WIDTH_CNTL                                                                0x4104a2
+#define regBIFP1_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX                                                       5
+#define regBIFP1_PCIE_LC_N_FTS_CNTL                                                                     0x4104a3
+#define regBIFP1_PCIE_LC_N_FTS_CNTL_BASE_IDX                                                            5
+#define regBIFP1_PCIE_LC_SPEED_CNTL                                                                     0x4104a4
+#define regBIFP1_PCIE_LC_SPEED_CNTL_BASE_IDX                                                            5
+#define regBIFP1_PCIE_LC_STATE0                                                                         0x4104a5
+#define regBIFP1_PCIE_LC_STATE0_BASE_IDX                                                                5
+#define regBIFP1_PCIE_LC_STATE1                                                                         0x4104a6
+#define regBIFP1_PCIE_LC_STATE1_BASE_IDX                                                                5
+#define regBIFP1_PCIE_LC_STATE2                                                                         0x4104a7
+#define regBIFP1_PCIE_LC_STATE2_BASE_IDX                                                                5
+#define regBIFP1_PCIE_LC_STATE3                                                                         0x4104a8
+#define regBIFP1_PCIE_LC_STATE3_BASE_IDX                                                                5
+#define regBIFP1_PCIE_LC_STATE4                                                                         0x4104a9
+#define regBIFP1_PCIE_LC_STATE4_BASE_IDX                                                                5
+#define regBIFP1_PCIE_LC_STATE5                                                                         0x4104aa
+#define regBIFP1_PCIE_LC_STATE5_BASE_IDX                                                                5
+#define regBIFP1_PCIE_LINK_MANAGEMENT_CNTL2                                                             0x4104ab
+#define regBIFP1_PCIE_LINK_MANAGEMENT_CNTL2_BASE_IDX                                                    5
+#define regBIFP1_PCIE_LC_CNTL2                                                                          0x4104b1
+#define regBIFP1_PCIE_LC_CNTL2_BASE_IDX                                                                 5
+#define regBIFP1_PCIE_LC_BW_CHANGE_CNTL                                                                 0x4104b2
+#define regBIFP1_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX                                                        5
+#define regBIFP1_PCIE_LC_CDR_CNTL                                                                       0x4104b3
+#define regBIFP1_PCIE_LC_CDR_CNTL_BASE_IDX                                                              5
+#define regBIFP1_PCIE_LC_LANE_CNTL                                                                      0x4104b4
+#define regBIFP1_PCIE_LC_LANE_CNTL_BASE_IDX                                                             5
+#define regBIFP1_PCIE_LC_CNTL3                                                                          0x4104b5
+#define regBIFP1_PCIE_LC_CNTL3_BASE_IDX                                                                 5
+#define regBIFP1_PCIE_LC_CNTL4                                                                          0x4104b6
+#define regBIFP1_PCIE_LC_CNTL4_BASE_IDX                                                                 5
+#define regBIFP1_PCIE_LC_CNTL5                                                                          0x4104b7
+#define regBIFP1_PCIE_LC_CNTL5_BASE_IDX                                                                 5
+#define regBIFP1_PCIE_LC_FORCE_COEFF                                                                    0x4104b8
+#define regBIFP1_PCIE_LC_FORCE_COEFF_BASE_IDX                                                           5
+#define regBIFP1_PCIE_LC_BEST_EQ_SETTINGS                                                               0x4104b9
+#define regBIFP1_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX                                                      5
+#define regBIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF                                                             0x4104ba
+#define regBIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX                                                    5
+#define regBIFP1_PCIE_LC_CNTL6                                                                          0x4104bb
+#define regBIFP1_PCIE_LC_CNTL6_BASE_IDX                                                                 5
+#define regBIFP1_PCIE_LC_CNTL7                                                                          0x4104bc
+#define regBIFP1_PCIE_LC_CNTL7_BASE_IDX                                                                 5
+#define regBIFP1_PCIE_LINK_MANAGEMENT_STATUS                                                            0x4104bd
+#define regBIFP1_PCIE_LINK_MANAGEMENT_STATUS_BASE_IDX                                                   5
+#define regBIFP1_PCIE_LINK_MANAGEMENT_MASK                                                              0x4104be
+#define regBIFP1_PCIE_LINK_MANAGEMENT_MASK_BASE_IDX                                                     5
+#define regBIFP1_PCIE_LINK_MANAGEMENT_CNTL                                                              0x4104bf
+#define regBIFP1_PCIE_LINK_MANAGEMENT_CNTL_BASE_IDX                                                     5
+#define regBIFP1_PCIEP_STRAP_LC                                                                         0x4104c0
+#define regBIFP1_PCIEP_STRAP_LC_BASE_IDX                                                                5
+#define regBIFP1_PCIEP_STRAP_MISC                                                                       0x4104c1
+#define regBIFP1_PCIEP_STRAP_MISC_BASE_IDX                                                              5
+#define regBIFP1_PCIEP_STRAP_LC2                                                                        0x4104c2
+#define regBIFP1_PCIEP_STRAP_LC2_BASE_IDX                                                               5
+#define regBIFP1_PCIE_LC_L1_PM_SUBSTATE                                                                 0x4104c6
+#define regBIFP1_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX                                                        5
+#define regBIFP1_PCIE_LC_L1_PM_SUBSTATE2                                                                0x4104c7
+#define regBIFP1_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX                                                       5
+#define regBIFP1_PCIE_LC_PORT_ORDER                                                                     0x4104c8
+#define regBIFP1_PCIE_LC_PORT_ORDER_BASE_IDX                                                            5
+#define regBIFP1_PCIEP_BCH_ECC_CNTL                                                                     0x4104d0
+#define regBIFP1_PCIEP_BCH_ECC_CNTL_BASE_IDX                                                            5
+#define regBIFP1_PCIEP_HPGI_PRIVATE                                                                     0x4104d2
+#define regBIFP1_PCIEP_HPGI_PRIVATE_BASE_IDX                                                            5
+#define regBIFP1_PCIEP_HPGI                                                                             0x4104da
+#define regBIFP1_PCIEP_HPGI_BASE_IDX                                                                    5
+#define regBIFP1_PCIEP_HCNT_DESCRIPTOR                                                                  0x4104db
+#define regBIFP1_PCIEP_HCNT_DESCRIPTOR_BASE_IDX                                                         5
+#define regBIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK                                                            0x4104dc
+#define regBIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_BASE_IDX                                                   5
+#define regBIFP1_PCIE_LC_CNTL8                                                                          0x4104dd
+#define regBIFP1_PCIE_LC_CNTL8_BASE_IDX                                                                 5
+#define regBIFP1_PCIE_LC_CNTL9                                                                          0x4104de
+#define regBIFP1_PCIE_LC_CNTL9_BASE_IDX                                                                 5
+#define regBIFP1_PCIE_LC_FORCE_COEFF2                                                                   0x4104df
+#define regBIFP1_PCIE_LC_FORCE_COEFF2_BASE_IDX                                                          5
+#define regBIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2                                                            0x4104e0
+#define regBIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX                                                   5
+#define regBIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC                                                         0x4104e1
+#define regBIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC_BASE_IDX                                                5
+#define regBIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES                                                  0x4104e2
+#define regBIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX                                         5
+#define regBIFP1_PCIE_LC_CNTL10                                                                         0x4104e3
+#define regBIFP1_PCIE_LC_CNTL10_BASE_IDX                                                                5
+#define regBIFP1_PCIE_LC_CNTL11                                                                         0x4104e4
+#define regBIFP1_PCIE_LC_CNTL11_BASE_IDX                                                                5
+#define regBIFP1_PCIE_LC_CNTL12                                                                         0x4104e5
+#define regBIFP1_PCIE_LC_CNTL12_BASE_IDX                                                                5
+#define regBIFP1_PCIE_LC_SAVE_RESTORE_1                                                                 0x4104e6
+#define regBIFP1_PCIE_LC_SAVE_RESTORE_1_BASE_IDX                                                        5
+#define regBIFP1_PCIE_LC_SAVE_RESTORE_2                                                                 0x4104e7
+#define regBIFP1_PCIE_LC_SAVE_RESTORE_2_BASE_IDX                                                        5
+#define regBIFP1_PCIE_LC_SAVE_RESTORE_3                                                                 0x4104e8
+#define regBIFP1_PCIE_LC_SAVE_RESTORE_3_BASE_IDX                                                        5
+
+
+// addressBlock: nbio_pcie0_bifp2_pciedir_p
+// base address: 0x11142000
+#define regBIFP2_PCIEP_RESERVED                                                                         0x410800
+#define regBIFP2_PCIEP_RESERVED_BASE_IDX                                                                5
+#define regBIFP2_PCIEP_SCRATCH                                                                          0x410801
+#define regBIFP2_PCIEP_SCRATCH_BASE_IDX                                                                 5
+#define regBIFP2_PCIEP_PORT_CNTL                                                                        0x410810
+#define regBIFP2_PCIEP_PORT_CNTL_BASE_IDX                                                               5
+#define regBIFP2_PCIE_TX_CNTL                                                                           0x410820
+#define regBIFP2_PCIE_TX_CNTL_BASE_IDX                                                                  5
+#define regBIFP2_PCIE_TX_REQUESTER_ID                                                                   0x410821
+#define regBIFP2_PCIE_TX_REQUESTER_ID_BASE_IDX                                                          5
+#define regBIFP2_PCIE_TX_VENDOR_SPECIFIC                                                                0x410822
+#define regBIFP2_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP2_PCIE_TX_REQUEST_NUM_CNTL                                                               0x410823
+#define regBIFP2_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX                                                      5
+#define regBIFP2_PCIE_TX_SEQ                                                                            0x410824
+#define regBIFP2_PCIE_TX_SEQ_BASE_IDX                                                                   5
+#define regBIFP2_PCIE_TX_REPLAY                                                                         0x410825
+#define regBIFP2_PCIE_TX_REPLAY_BASE_IDX                                                                5
+#define regBIFP2_PCIE_TX_ACK_LATENCY_LIMIT                                                              0x410826
+#define regBIFP2_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX                                                     5
+#define regBIFP2_PCIE_TX_NOP_DLLP                                                                       0x410827
+#define regBIFP2_PCIE_TX_NOP_DLLP_BASE_IDX                                                              5
+#define regBIFP2_PCIE_TX_CNTL_2                                                                         0x410828
+#define regBIFP2_PCIE_TX_CNTL_2_BASE_IDX                                                                5
+#define regBIFP2_PCIE_TX_SKID_CTRL                                                                      0x41082f
+#define regBIFP2_PCIE_TX_SKID_CTRL_BASE_IDX                                                             5
+#define regBIFP2_PCIE_TX_CREDITS_ADVT_P                                                                 0x410830
+#define regBIFP2_PCIE_TX_CREDITS_ADVT_P_BASE_IDX                                                        5
+#define regBIFP2_PCIE_TX_CREDITS_ADVT_NP                                                                0x410831
+#define regBIFP2_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX                                                       5
+#define regBIFP2_PCIE_TX_CREDITS_ADVT_CPL                                                               0x410832
+#define regBIFP2_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX                                                      5
+#define regBIFP2_PCIE_TX_CREDITS_INIT_P                                                                 0x410833
+#define regBIFP2_PCIE_TX_CREDITS_INIT_P_BASE_IDX                                                        5
+#define regBIFP2_PCIE_TX_CREDITS_INIT_NP                                                                0x410834
+#define regBIFP2_PCIE_TX_CREDITS_INIT_NP_BASE_IDX                                                       5
+#define regBIFP2_PCIE_TX_CREDITS_INIT_CPL                                                               0x410835
+#define regBIFP2_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX                                                      5
+#define regBIFP2_PCIE_TX_CREDITS_STATUS                                                                 0x410836
+#define regBIFP2_PCIE_TX_CREDITS_STATUS_BASE_IDX                                                        5
+#define regBIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD                                                          0x410837
+#define regBIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX                                                 5
+#define regBIFP2_PCIE_TX_CCIX_PORT_CNTL0                                                                0x410838
+#define regBIFP2_PCIE_TX_CCIX_PORT_CNTL0_BASE_IDX                                                       5
+#define regBIFP2_PCIE_TX_CCIX_PORT_CNTL1                                                                0x410839
+#define regBIFP2_PCIE_TX_CCIX_PORT_CNTL1_BASE_IDX                                                       5
+#define regBIFP2_PCIE_CCIX_STACKED_BASE                                                                 0x41083a
+#define regBIFP2_PCIE_CCIX_STACKED_BASE_BASE_IDX                                                        5
+#define regBIFP2_PCIE_CCIX_STACKED_LIMIT                                                                0x41083b
+#define regBIFP2_PCIE_CCIX_STACKED_LIMIT_BASE_IDX                                                       5
+#define regBIFP2_PCIE_CCIX_MISC_STATUS                                                                  0x410841
+#define regBIFP2_PCIE_CCIX_MISC_STATUS_BASE_IDX                                                         5
+#define regBIFP2_PCIE_P_PORT_LANE_STATUS                                                                0x410850
+#define regBIFP2_PCIE_P_PORT_LANE_STATUS_BASE_IDX                                                       5
+#define regBIFP2_PCIE_FC_P                                                                              0x410860
+#define regBIFP2_PCIE_FC_P_BASE_IDX                                                                     5
+#define regBIFP2_PCIE_FC_NP                                                                             0x410861
+#define regBIFP2_PCIE_FC_NP_BASE_IDX                                                                    5
+#define regBIFP2_PCIE_FC_CPL                                                                            0x410862
+#define regBIFP2_PCIE_FC_CPL_BASE_IDX                                                                   5
+#define regBIFP2_PCIE_FC_P_VC1                                                                          0x410863
+#define regBIFP2_PCIE_FC_P_VC1_BASE_IDX                                                                 5
+#define regBIFP2_PCIE_FC_NP_VC1                                                                         0x410864
+#define regBIFP2_PCIE_FC_NP_VC1_BASE_IDX                                                                5
+#define regBIFP2_PCIE_FC_CPL_VC1                                                                        0x410865
+#define regBIFP2_PCIE_FC_CPL_VC1_BASE_IDX                                                               5
+#define regBIFP2_PCIE_ERR_CNTL                                                                          0x41086a
+#define regBIFP2_PCIE_ERR_CNTL_BASE_IDX                                                                 5
+#define regBIFP2_PCIE_RX_CNTL                                                                           0x410870
+#define regBIFP2_PCIE_RX_CNTL_BASE_IDX                                                                  5
+#define regBIFP2_PCIE_RX_EXPECTED_SEQNUM                                                                0x410871
+#define regBIFP2_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX                                                       5
+#define regBIFP2_PCIE_RX_VENDOR_SPECIFIC                                                                0x410872
+#define regBIFP2_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP2_PCIE_RX_CNTL3                                                                          0x410874
+#define regBIFP2_PCIE_RX_CNTL3_BASE_IDX                                                                 5
+#define regBIFP2_PCIE_RX_CREDITS_ALLOCATED_P                                                            0x410880
+#define regBIFP2_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX                                                   5
+#define regBIFP2_PCIE_RX_CREDITS_ALLOCATED_NP                                                           0x410881
+#define regBIFP2_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX                                                  5
+#define regBIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL                                                          0x410882
+#define regBIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX                                                 5
+#define regBIFP2_PCIEP_ERROR_INJECT_PHYSICAL                                                            0x410883
+#define regBIFP2_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX                                                   5
+#define regBIFP2_PCIEP_ERROR_INJECT_TRANSACTION                                                         0x410884
+#define regBIFP2_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX                                                5
+#define regBIFP2_PCIEP_NAK_COUNTER                                                                      0x410886
+#define regBIFP2_PCIEP_NAK_COUNTER_BASE_IDX                                                             5
+#define regBIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS                                                      0x410888
+#define regBIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_BASE_IDX                                             5
+#define regBIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES                                                 0x410889
+#define regBIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_BASE_IDX                                        5
+#define regBIFP2_PCIE_AER_PRIV_UNCORRECTABLE_MASK                                                       0x41088c
+#define regBIFP2_PCIE_AER_PRIV_UNCORRECTABLE_MASK_BASE_IDX                                              5
+#define regBIFP2_PCIE_AER_PRIV_TRIGGER                                                                  0x41088d
+#define regBIFP2_PCIE_AER_PRIV_TRIGGER_BASE_IDX                                                         5
+#define regBIFP2_PCIE_LC_CNTL                                                                           0x4108a0
+#define regBIFP2_PCIE_LC_CNTL_BASE_IDX                                                                  5
+#define regBIFP2_PCIE_LC_TRAINING_CNTL                                                                  0x4108a1
+#define regBIFP2_PCIE_LC_TRAINING_CNTL_BASE_IDX                                                         5
+#define regBIFP2_PCIE_LC_LINK_WIDTH_CNTL                                                                0x4108a2
+#define regBIFP2_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX                                                       5
+#define regBIFP2_PCIE_LC_N_FTS_CNTL                                                                     0x4108a3
+#define regBIFP2_PCIE_LC_N_FTS_CNTL_BASE_IDX                                                            5
+#define regBIFP2_PCIE_LC_SPEED_CNTL                                                                     0x4108a4
+#define regBIFP2_PCIE_LC_SPEED_CNTL_BASE_IDX                                                            5
+#define regBIFP2_PCIE_LC_STATE0                                                                         0x4108a5
+#define regBIFP2_PCIE_LC_STATE0_BASE_IDX                                                                5
+#define regBIFP2_PCIE_LC_STATE1                                                                         0x4108a6
+#define regBIFP2_PCIE_LC_STATE1_BASE_IDX                                                                5
+#define regBIFP2_PCIE_LC_STATE2                                                                         0x4108a7
+#define regBIFP2_PCIE_LC_STATE2_BASE_IDX                                                                5
+#define regBIFP2_PCIE_LC_STATE3                                                                         0x4108a8
+#define regBIFP2_PCIE_LC_STATE3_BASE_IDX                                                                5
+#define regBIFP2_PCIE_LC_STATE4                                                                         0x4108a9
+#define regBIFP2_PCIE_LC_STATE4_BASE_IDX                                                                5
+#define regBIFP2_PCIE_LC_STATE5                                                                         0x4108aa
+#define regBIFP2_PCIE_LC_STATE5_BASE_IDX                                                                5
+#define regBIFP2_PCIE_LINK_MANAGEMENT_CNTL2                                                             0x4108ab
+#define regBIFP2_PCIE_LINK_MANAGEMENT_CNTL2_BASE_IDX                                                    5
+#define regBIFP2_PCIE_LC_CNTL2                                                                          0x4108b1
+#define regBIFP2_PCIE_LC_CNTL2_BASE_IDX                                                                 5
+#define regBIFP2_PCIE_LC_BW_CHANGE_CNTL                                                                 0x4108b2
+#define regBIFP2_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX                                                        5
+#define regBIFP2_PCIE_LC_CDR_CNTL                                                                       0x4108b3
+#define regBIFP2_PCIE_LC_CDR_CNTL_BASE_IDX                                                              5
+#define regBIFP2_PCIE_LC_LANE_CNTL                                                                      0x4108b4
+#define regBIFP2_PCIE_LC_LANE_CNTL_BASE_IDX                                                             5
+#define regBIFP2_PCIE_LC_CNTL3                                                                          0x4108b5
+#define regBIFP2_PCIE_LC_CNTL3_BASE_IDX                                                                 5
+#define regBIFP2_PCIE_LC_CNTL4                                                                          0x4108b6
+#define regBIFP2_PCIE_LC_CNTL4_BASE_IDX                                                                 5
+#define regBIFP2_PCIE_LC_CNTL5                                                                          0x4108b7
+#define regBIFP2_PCIE_LC_CNTL5_BASE_IDX                                                                 5
+#define regBIFP2_PCIE_LC_FORCE_COEFF                                                                    0x4108b8
+#define regBIFP2_PCIE_LC_FORCE_COEFF_BASE_IDX                                                           5
+#define regBIFP2_PCIE_LC_BEST_EQ_SETTINGS                                                               0x4108b9
+#define regBIFP2_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX                                                      5
+#define regBIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF                                                             0x4108ba
+#define regBIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX                                                    5
+#define regBIFP2_PCIE_LC_CNTL6                                                                          0x4108bb
+#define regBIFP2_PCIE_LC_CNTL6_BASE_IDX                                                                 5
+#define regBIFP2_PCIE_LC_CNTL7                                                                          0x4108bc
+#define regBIFP2_PCIE_LC_CNTL7_BASE_IDX                                                                 5
+#define regBIFP2_PCIE_LINK_MANAGEMENT_STATUS                                                            0x4108bd
+#define regBIFP2_PCIE_LINK_MANAGEMENT_STATUS_BASE_IDX                                                   5
+#define regBIFP2_PCIE_LINK_MANAGEMENT_MASK                                                              0x4108be
+#define regBIFP2_PCIE_LINK_MANAGEMENT_MASK_BASE_IDX                                                     5
+#define regBIFP2_PCIE_LINK_MANAGEMENT_CNTL                                                              0x4108bf
+#define regBIFP2_PCIE_LINK_MANAGEMENT_CNTL_BASE_IDX                                                     5
+#define regBIFP2_PCIEP_STRAP_LC                                                                         0x4108c0
+#define regBIFP2_PCIEP_STRAP_LC_BASE_IDX                                                                5
+#define regBIFP2_PCIEP_STRAP_MISC                                                                       0x4108c1
+#define regBIFP2_PCIEP_STRAP_MISC_BASE_IDX                                                              5
+#define regBIFP2_PCIEP_STRAP_LC2                                                                        0x4108c2
+#define regBIFP2_PCIEP_STRAP_LC2_BASE_IDX                                                               5
+#define regBIFP2_PCIE_LC_L1_PM_SUBSTATE                                                                 0x4108c6
+#define regBIFP2_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX                                                        5
+#define regBIFP2_PCIE_LC_L1_PM_SUBSTATE2                                                                0x4108c7
+#define regBIFP2_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX                                                       5
+#define regBIFP2_PCIE_LC_PORT_ORDER                                                                     0x4108c8
+#define regBIFP2_PCIE_LC_PORT_ORDER_BASE_IDX                                                            5
+#define regBIFP2_PCIEP_BCH_ECC_CNTL                                                                     0x4108d0
+#define regBIFP2_PCIEP_BCH_ECC_CNTL_BASE_IDX                                                            5
+#define regBIFP2_PCIEP_HPGI_PRIVATE                                                                     0x4108d2
+#define regBIFP2_PCIEP_HPGI_PRIVATE_BASE_IDX                                                            5
+#define regBIFP2_PCIEP_HPGI                                                                             0x4108da
+#define regBIFP2_PCIEP_HPGI_BASE_IDX                                                                    5
+#define regBIFP2_PCIEP_HCNT_DESCRIPTOR                                                                  0x4108db
+#define regBIFP2_PCIEP_HCNT_DESCRIPTOR_BASE_IDX                                                         5
+#define regBIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK                                                            0x4108dc
+#define regBIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_BASE_IDX                                                   5
+#define regBIFP2_PCIE_LC_CNTL8                                                                          0x4108dd
+#define regBIFP2_PCIE_LC_CNTL8_BASE_IDX                                                                 5
+#define regBIFP2_PCIE_LC_CNTL9                                                                          0x4108de
+#define regBIFP2_PCIE_LC_CNTL9_BASE_IDX                                                                 5
+#define regBIFP2_PCIE_LC_FORCE_COEFF2                                                                   0x4108df
+#define regBIFP2_PCIE_LC_FORCE_COEFF2_BASE_IDX                                                          5
+#define regBIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2                                                            0x4108e0
+#define regBIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX                                                   5
+#define regBIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC                                                         0x4108e1
+#define regBIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC_BASE_IDX                                                5
+#define regBIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES                                                  0x4108e2
+#define regBIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX                                         5
+#define regBIFP2_PCIE_LC_CNTL10                                                                         0x4108e3
+#define regBIFP2_PCIE_LC_CNTL10_BASE_IDX                                                                5
+#define regBIFP2_PCIE_LC_CNTL11                                                                         0x4108e4
+#define regBIFP2_PCIE_LC_CNTL11_BASE_IDX                                                                5
+#define regBIFP2_PCIE_LC_CNTL12                                                                         0x4108e5
+#define regBIFP2_PCIE_LC_CNTL12_BASE_IDX                                                                5
+#define regBIFP2_PCIE_LC_SAVE_RESTORE_1                                                                 0x4108e6
+#define regBIFP2_PCIE_LC_SAVE_RESTORE_1_BASE_IDX                                                        5
+#define regBIFP2_PCIE_LC_SAVE_RESTORE_2                                                                 0x4108e7
+#define regBIFP2_PCIE_LC_SAVE_RESTORE_2_BASE_IDX                                                        5
+#define regBIFP2_PCIE_LC_SAVE_RESTORE_3                                                                 0x4108e8
+#define regBIFP2_PCIE_LC_SAVE_RESTORE_3_BASE_IDX                                                        5
+
+
+// addressBlock: nbio_pcie0_bifp3_pciedir_p
+// base address: 0x11143000
+#define regBIFP3_PCIEP_RESERVED                                                                         0x410c00
+#define regBIFP3_PCIEP_RESERVED_BASE_IDX                                                                5
+#define regBIFP3_PCIEP_SCRATCH                                                                          0x410c01
+#define regBIFP3_PCIEP_SCRATCH_BASE_IDX                                                                 5
+#define regBIFP3_PCIEP_PORT_CNTL                                                                        0x410c10
+#define regBIFP3_PCIEP_PORT_CNTL_BASE_IDX                                                               5
+#define regBIFP3_PCIE_TX_CNTL                                                                           0x410c20
+#define regBIFP3_PCIE_TX_CNTL_BASE_IDX                                                                  5
+#define regBIFP3_PCIE_TX_REQUESTER_ID                                                                   0x410c21
+#define regBIFP3_PCIE_TX_REQUESTER_ID_BASE_IDX                                                          5
+#define regBIFP3_PCIE_TX_VENDOR_SPECIFIC                                                                0x410c22
+#define regBIFP3_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP3_PCIE_TX_REQUEST_NUM_CNTL                                                               0x410c23
+#define regBIFP3_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX                                                      5
+#define regBIFP3_PCIE_TX_SEQ                                                                            0x410c24
+#define regBIFP3_PCIE_TX_SEQ_BASE_IDX                                                                   5
+#define regBIFP3_PCIE_TX_REPLAY                                                                         0x410c25
+#define regBIFP3_PCIE_TX_REPLAY_BASE_IDX                                                                5
+#define regBIFP3_PCIE_TX_ACK_LATENCY_LIMIT                                                              0x410c26
+#define regBIFP3_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX                                                     5
+#define regBIFP3_PCIE_TX_NOP_DLLP                                                                       0x410c27
+#define regBIFP3_PCIE_TX_NOP_DLLP_BASE_IDX                                                              5
+#define regBIFP3_PCIE_TX_CNTL_2                                                                         0x410c28
+#define regBIFP3_PCIE_TX_CNTL_2_BASE_IDX                                                                5
+#define regBIFP3_PCIE_TX_SKID_CTRL                                                                      0x410c2f
+#define regBIFP3_PCIE_TX_SKID_CTRL_BASE_IDX                                                             5
+#define regBIFP3_PCIE_TX_CREDITS_ADVT_P                                                                 0x410c30
+#define regBIFP3_PCIE_TX_CREDITS_ADVT_P_BASE_IDX                                                        5
+#define regBIFP3_PCIE_TX_CREDITS_ADVT_NP                                                                0x410c31
+#define regBIFP3_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX                                                       5
+#define regBIFP3_PCIE_TX_CREDITS_ADVT_CPL                                                               0x410c32
+#define regBIFP3_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX                                                      5
+#define regBIFP3_PCIE_TX_CREDITS_INIT_P                                                                 0x410c33
+#define regBIFP3_PCIE_TX_CREDITS_INIT_P_BASE_IDX                                                        5
+#define regBIFP3_PCIE_TX_CREDITS_INIT_NP                                                                0x410c34
+#define regBIFP3_PCIE_TX_CREDITS_INIT_NP_BASE_IDX                                                       5
+#define regBIFP3_PCIE_TX_CREDITS_INIT_CPL                                                               0x410c35
+#define regBIFP3_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX                                                      5
+#define regBIFP3_PCIE_TX_CREDITS_STATUS                                                                 0x410c36
+#define regBIFP3_PCIE_TX_CREDITS_STATUS_BASE_IDX                                                        5
+#define regBIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD                                                          0x410c37
+#define regBIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX                                                 5
+#define regBIFP3_PCIE_TX_CCIX_PORT_CNTL0                                                                0x410c38
+#define regBIFP3_PCIE_TX_CCIX_PORT_CNTL0_BASE_IDX                                                       5
+#define regBIFP3_PCIE_TX_CCIX_PORT_CNTL1                                                                0x410c39
+#define regBIFP3_PCIE_TX_CCIX_PORT_CNTL1_BASE_IDX                                                       5
+#define regBIFP3_PCIE_CCIX_STACKED_BASE                                                                 0x410c3a
+#define regBIFP3_PCIE_CCIX_STACKED_BASE_BASE_IDX                                                        5
+#define regBIFP3_PCIE_CCIX_STACKED_LIMIT                                                                0x410c3b
+#define regBIFP3_PCIE_CCIX_STACKED_LIMIT_BASE_IDX                                                       5
+#define regBIFP3_PCIE_CCIX_MISC_STATUS                                                                  0x410c41
+#define regBIFP3_PCIE_CCIX_MISC_STATUS_BASE_IDX                                                         5
+#define regBIFP3_PCIE_P_PORT_LANE_STATUS                                                                0x410c50
+#define regBIFP3_PCIE_P_PORT_LANE_STATUS_BASE_IDX                                                       5
+#define regBIFP3_PCIE_FC_P                                                                              0x410c60
+#define regBIFP3_PCIE_FC_P_BASE_IDX                                                                     5
+#define regBIFP3_PCIE_FC_NP                                                                             0x410c61
+#define regBIFP3_PCIE_FC_NP_BASE_IDX                                                                    5
+#define regBIFP3_PCIE_FC_CPL                                                                            0x410c62
+#define regBIFP3_PCIE_FC_CPL_BASE_IDX                                                                   5
+#define regBIFP3_PCIE_FC_P_VC1                                                                          0x410c63
+#define regBIFP3_PCIE_FC_P_VC1_BASE_IDX                                                                 5
+#define regBIFP3_PCIE_FC_NP_VC1                                                                         0x410c64
+#define regBIFP3_PCIE_FC_NP_VC1_BASE_IDX                                                                5
+#define regBIFP3_PCIE_FC_CPL_VC1                                                                        0x410c65
+#define regBIFP3_PCIE_FC_CPL_VC1_BASE_IDX                                                               5
+#define regBIFP3_PCIE_ERR_CNTL                                                                          0x410c6a
+#define regBIFP3_PCIE_ERR_CNTL_BASE_IDX                                                                 5
+#define regBIFP3_PCIE_RX_CNTL                                                                           0x410c70
+#define regBIFP3_PCIE_RX_CNTL_BASE_IDX                                                                  5
+#define regBIFP3_PCIE_RX_EXPECTED_SEQNUM                                                                0x410c71
+#define regBIFP3_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX                                                       5
+#define regBIFP3_PCIE_RX_VENDOR_SPECIFIC                                                                0x410c72
+#define regBIFP3_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP3_PCIE_RX_CNTL3                                                                          0x410c74
+#define regBIFP3_PCIE_RX_CNTL3_BASE_IDX                                                                 5
+#define regBIFP3_PCIE_RX_CREDITS_ALLOCATED_P                                                            0x410c80
+#define regBIFP3_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX                                                   5
+#define regBIFP3_PCIE_RX_CREDITS_ALLOCATED_NP                                                           0x410c81
+#define regBIFP3_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX                                                  5
+#define regBIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL                                                          0x410c82
+#define regBIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX                                                 5
+#define regBIFP3_PCIEP_ERROR_INJECT_PHYSICAL                                                            0x410c83
+#define regBIFP3_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX                                                   5
+#define regBIFP3_PCIEP_ERROR_INJECT_TRANSACTION                                                         0x410c84
+#define regBIFP3_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX                                                5
+#define regBIFP3_PCIEP_NAK_COUNTER                                                                      0x410c86
+#define regBIFP3_PCIEP_NAK_COUNTER_BASE_IDX                                                             5
+#define regBIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS                                                      0x410c88
+#define regBIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_BASE_IDX                                             5
+#define regBIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES                                                 0x410c89
+#define regBIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_BASE_IDX                                        5
+#define regBIFP3_PCIE_AER_PRIV_UNCORRECTABLE_MASK                                                       0x410c8c
+#define regBIFP3_PCIE_AER_PRIV_UNCORRECTABLE_MASK_BASE_IDX                                              5
+#define regBIFP3_PCIE_AER_PRIV_TRIGGER                                                                  0x410c8d
+#define regBIFP3_PCIE_AER_PRIV_TRIGGER_BASE_IDX                                                         5
+#define regBIFP3_PCIE_LC_CNTL                                                                           0x410ca0
+#define regBIFP3_PCIE_LC_CNTL_BASE_IDX                                                                  5
+#define regBIFP3_PCIE_LC_TRAINING_CNTL                                                                  0x410ca1
+#define regBIFP3_PCIE_LC_TRAINING_CNTL_BASE_IDX                                                         5
+#define regBIFP3_PCIE_LC_LINK_WIDTH_CNTL                                                                0x410ca2
+#define regBIFP3_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX                                                       5
+#define regBIFP3_PCIE_LC_N_FTS_CNTL                                                                     0x410ca3
+#define regBIFP3_PCIE_LC_N_FTS_CNTL_BASE_IDX                                                            5
+#define regBIFP3_PCIE_LC_SPEED_CNTL                                                                     0x410ca4
+#define regBIFP3_PCIE_LC_SPEED_CNTL_BASE_IDX                                                            5
+#define regBIFP3_PCIE_LC_STATE0                                                                         0x410ca5
+#define regBIFP3_PCIE_LC_STATE0_BASE_IDX                                                                5
+#define regBIFP3_PCIE_LC_STATE1                                                                         0x410ca6
+#define regBIFP3_PCIE_LC_STATE1_BASE_IDX                                                                5
+#define regBIFP3_PCIE_LC_STATE2                                                                         0x410ca7
+#define regBIFP3_PCIE_LC_STATE2_BASE_IDX                                                                5
+#define regBIFP3_PCIE_LC_STATE3                                                                         0x410ca8
+#define regBIFP3_PCIE_LC_STATE3_BASE_IDX                                                                5
+#define regBIFP3_PCIE_LC_STATE4                                                                         0x410ca9
+#define regBIFP3_PCIE_LC_STATE4_BASE_IDX                                                                5
+#define regBIFP3_PCIE_LC_STATE5                                                                         0x410caa
+#define regBIFP3_PCIE_LC_STATE5_BASE_IDX                                                                5
+#define regBIFP3_PCIE_LINK_MANAGEMENT_CNTL2                                                             0x410cab
+#define regBIFP3_PCIE_LINK_MANAGEMENT_CNTL2_BASE_IDX                                                    5
+#define regBIFP3_PCIE_LC_CNTL2                                                                          0x410cb1
+#define regBIFP3_PCIE_LC_CNTL2_BASE_IDX                                                                 5
+#define regBIFP3_PCIE_LC_BW_CHANGE_CNTL                                                                 0x410cb2
+#define regBIFP3_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX                                                        5
+#define regBIFP3_PCIE_LC_CDR_CNTL                                                                       0x410cb3
+#define regBIFP3_PCIE_LC_CDR_CNTL_BASE_IDX                                                              5
+#define regBIFP3_PCIE_LC_LANE_CNTL                                                                      0x410cb4
+#define regBIFP3_PCIE_LC_LANE_CNTL_BASE_IDX                                                             5
+#define regBIFP3_PCIE_LC_CNTL3                                                                          0x410cb5
+#define regBIFP3_PCIE_LC_CNTL3_BASE_IDX                                                                 5
+#define regBIFP3_PCIE_LC_CNTL4                                                                          0x410cb6
+#define regBIFP3_PCIE_LC_CNTL4_BASE_IDX                                                                 5
+#define regBIFP3_PCIE_LC_CNTL5                                                                          0x410cb7
+#define regBIFP3_PCIE_LC_CNTL5_BASE_IDX                                                                 5
+#define regBIFP3_PCIE_LC_FORCE_COEFF                                                                    0x410cb8
+#define regBIFP3_PCIE_LC_FORCE_COEFF_BASE_IDX                                                           5
+#define regBIFP3_PCIE_LC_BEST_EQ_SETTINGS                                                               0x410cb9
+#define regBIFP3_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX                                                      5
+#define regBIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF                                                             0x410cba
+#define regBIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX                                                    5
+#define regBIFP3_PCIE_LC_CNTL6                                                                          0x410cbb
+#define regBIFP3_PCIE_LC_CNTL6_BASE_IDX                                                                 5
+#define regBIFP3_PCIE_LC_CNTL7                                                                          0x410cbc
+#define regBIFP3_PCIE_LC_CNTL7_BASE_IDX                                                                 5
+#define regBIFP3_PCIE_LINK_MANAGEMENT_STATUS                                                            0x410cbd
+#define regBIFP3_PCIE_LINK_MANAGEMENT_STATUS_BASE_IDX                                                   5
+#define regBIFP3_PCIE_LINK_MANAGEMENT_MASK                                                              0x410cbe
+#define regBIFP3_PCIE_LINK_MANAGEMENT_MASK_BASE_IDX                                                     5
+#define regBIFP3_PCIE_LINK_MANAGEMENT_CNTL                                                              0x410cbf
+#define regBIFP3_PCIE_LINK_MANAGEMENT_CNTL_BASE_IDX                                                     5
+#define regBIFP3_PCIEP_STRAP_LC                                                                         0x410cc0
+#define regBIFP3_PCIEP_STRAP_LC_BASE_IDX                                                                5
+#define regBIFP3_PCIEP_STRAP_MISC                                                                       0x410cc1
+#define regBIFP3_PCIEP_STRAP_MISC_BASE_IDX                                                              5
+#define regBIFP3_PCIEP_STRAP_LC2                                                                        0x410cc2
+#define regBIFP3_PCIEP_STRAP_LC2_BASE_IDX                                                               5
+#define regBIFP3_PCIE_LC_L1_PM_SUBSTATE                                                                 0x410cc6
+#define regBIFP3_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX                                                        5
+#define regBIFP3_PCIE_LC_L1_PM_SUBSTATE2                                                                0x410cc7
+#define regBIFP3_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX                                                       5
+#define regBIFP3_PCIE_LC_PORT_ORDER                                                                     0x410cc8
+#define regBIFP3_PCIE_LC_PORT_ORDER_BASE_IDX                                                            5
+#define regBIFP3_PCIEP_BCH_ECC_CNTL                                                                     0x410cd0
+#define regBIFP3_PCIEP_BCH_ECC_CNTL_BASE_IDX                                                            5
+#define regBIFP3_PCIEP_HPGI_PRIVATE                                                                     0x410cd2
+#define regBIFP3_PCIEP_HPGI_PRIVATE_BASE_IDX                                                            5
+#define regBIFP3_PCIEP_HPGI                                                                             0x410cda
+#define regBIFP3_PCIEP_HPGI_BASE_IDX                                                                    5
+#define regBIFP3_PCIEP_HCNT_DESCRIPTOR                                                                  0x410cdb
+#define regBIFP3_PCIEP_HCNT_DESCRIPTOR_BASE_IDX                                                         5
+#define regBIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK                                                            0x410cdc
+#define regBIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_BASE_IDX                                                   5
+#define regBIFP3_PCIE_LC_CNTL8                                                                          0x410cdd
+#define regBIFP3_PCIE_LC_CNTL8_BASE_IDX                                                                 5
+#define regBIFP3_PCIE_LC_CNTL9                                                                          0x410cde
+#define regBIFP3_PCIE_LC_CNTL9_BASE_IDX                                                                 5
+#define regBIFP3_PCIE_LC_FORCE_COEFF2                                                                   0x410cdf
+#define regBIFP3_PCIE_LC_FORCE_COEFF2_BASE_IDX                                                          5
+#define regBIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2                                                            0x410ce0
+#define regBIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX                                                   5
+#define regBIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC                                                         0x410ce1
+#define regBIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC_BASE_IDX                                                5
+#define regBIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES                                                  0x410ce2
+#define regBIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX                                         5
+#define regBIFP3_PCIE_LC_CNTL10                                                                         0x410ce3
+#define regBIFP3_PCIE_LC_CNTL10_BASE_IDX                                                                5
+#define regBIFP3_PCIE_LC_CNTL11                                                                         0x410ce4
+#define regBIFP3_PCIE_LC_CNTL11_BASE_IDX                                                                5
+#define regBIFP3_PCIE_LC_CNTL12                                                                         0x410ce5
+#define regBIFP3_PCIE_LC_CNTL12_BASE_IDX                                                                5
+#define regBIFP3_PCIE_LC_SAVE_RESTORE_1                                                                 0x410ce6
+#define regBIFP3_PCIE_LC_SAVE_RESTORE_1_BASE_IDX                                                        5
+#define regBIFP3_PCIE_LC_SAVE_RESTORE_2                                                                 0x410ce7
+#define regBIFP3_PCIE_LC_SAVE_RESTORE_2_BASE_IDX                                                        5
+#define regBIFP3_PCIE_LC_SAVE_RESTORE_3                                                                 0x410ce8
+#define regBIFP3_PCIE_LC_SAVE_RESTORE_3_BASE_IDX                                                        5
+
+
+// addressBlock: nbio_pcie0_bifp4_pciedir_p
+// base address: 0x11144000
+#define regBIFP4_PCIEP_RESERVED                                                                         0x411000
+#define regBIFP4_PCIEP_RESERVED_BASE_IDX                                                                5
+#define regBIFP4_PCIEP_SCRATCH                                                                          0x411001
+#define regBIFP4_PCIEP_SCRATCH_BASE_IDX                                                                 5
+#define regBIFP4_PCIEP_PORT_CNTL                                                                        0x411010
+#define regBIFP4_PCIEP_PORT_CNTL_BASE_IDX                                                               5
+#define regBIFP4_PCIE_TX_CNTL                                                                           0x411020
+#define regBIFP4_PCIE_TX_CNTL_BASE_IDX                                                                  5
+#define regBIFP4_PCIE_TX_REQUESTER_ID                                                                   0x411021
+#define regBIFP4_PCIE_TX_REQUESTER_ID_BASE_IDX                                                          5
+#define regBIFP4_PCIE_TX_VENDOR_SPECIFIC                                                                0x411022
+#define regBIFP4_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP4_PCIE_TX_REQUEST_NUM_CNTL                                                               0x411023
+#define regBIFP4_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX                                                      5
+#define regBIFP4_PCIE_TX_SEQ                                                                            0x411024
+#define regBIFP4_PCIE_TX_SEQ_BASE_IDX                                                                   5
+#define regBIFP4_PCIE_TX_REPLAY                                                                         0x411025
+#define regBIFP4_PCIE_TX_REPLAY_BASE_IDX                                                                5
+#define regBIFP4_PCIE_TX_ACK_LATENCY_LIMIT                                                              0x411026
+#define regBIFP4_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX                                                     5
+#define regBIFP4_PCIE_TX_NOP_DLLP                                                                       0x411027
+#define regBIFP4_PCIE_TX_NOP_DLLP_BASE_IDX                                                              5
+#define regBIFP4_PCIE_TX_CNTL_2                                                                         0x411028
+#define regBIFP4_PCIE_TX_CNTL_2_BASE_IDX                                                                5
+#define regBIFP4_PCIE_TX_SKID_CTRL                                                                      0x41102f
+#define regBIFP4_PCIE_TX_SKID_CTRL_BASE_IDX                                                             5
+#define regBIFP4_PCIE_TX_CREDITS_ADVT_P                                                                 0x411030
+#define regBIFP4_PCIE_TX_CREDITS_ADVT_P_BASE_IDX                                                        5
+#define regBIFP4_PCIE_TX_CREDITS_ADVT_NP                                                                0x411031
+#define regBIFP4_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX                                                       5
+#define regBIFP4_PCIE_TX_CREDITS_ADVT_CPL                                                               0x411032
+#define regBIFP4_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX                                                      5
+#define regBIFP4_PCIE_TX_CREDITS_INIT_P                                                                 0x411033
+#define regBIFP4_PCIE_TX_CREDITS_INIT_P_BASE_IDX                                                        5
+#define regBIFP4_PCIE_TX_CREDITS_INIT_NP                                                                0x411034
+#define regBIFP4_PCIE_TX_CREDITS_INIT_NP_BASE_IDX                                                       5
+#define regBIFP4_PCIE_TX_CREDITS_INIT_CPL                                                               0x411035
+#define regBIFP4_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX                                                      5
+#define regBIFP4_PCIE_TX_CREDITS_STATUS                                                                 0x411036
+#define regBIFP4_PCIE_TX_CREDITS_STATUS_BASE_IDX                                                        5
+#define regBIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD                                                          0x411037
+#define regBIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX                                                 5
+#define regBIFP4_PCIE_TX_CCIX_PORT_CNTL0                                                                0x411038
+#define regBIFP4_PCIE_TX_CCIX_PORT_CNTL0_BASE_IDX                                                       5
+#define regBIFP4_PCIE_TX_CCIX_PORT_CNTL1                                                                0x411039
+#define regBIFP4_PCIE_TX_CCIX_PORT_CNTL1_BASE_IDX                                                       5
+#define regBIFP4_PCIE_CCIX_STACKED_BASE                                                                 0x41103a
+#define regBIFP4_PCIE_CCIX_STACKED_BASE_BASE_IDX                                                        5
+#define regBIFP4_PCIE_CCIX_STACKED_LIMIT                                                                0x41103b
+#define regBIFP4_PCIE_CCIX_STACKED_LIMIT_BASE_IDX                                                       5
+#define regBIFP4_PCIE_CCIX_MISC_STATUS                                                                  0x411041
+#define regBIFP4_PCIE_CCIX_MISC_STATUS_BASE_IDX                                                         5
+#define regBIFP4_PCIE_P_PORT_LANE_STATUS                                                                0x411050
+#define regBIFP4_PCIE_P_PORT_LANE_STATUS_BASE_IDX                                                       5
+#define regBIFP4_PCIE_FC_P                                                                              0x411060
+#define regBIFP4_PCIE_FC_P_BASE_IDX                                                                     5
+#define regBIFP4_PCIE_FC_NP                                                                             0x411061
+#define regBIFP4_PCIE_FC_NP_BASE_IDX                                                                    5
+#define regBIFP4_PCIE_FC_CPL                                                                            0x411062
+#define regBIFP4_PCIE_FC_CPL_BASE_IDX                                                                   5
+#define regBIFP4_PCIE_FC_P_VC1                                                                          0x411063
+#define regBIFP4_PCIE_FC_P_VC1_BASE_IDX                                                                 5
+#define regBIFP4_PCIE_FC_NP_VC1                                                                         0x411064
+#define regBIFP4_PCIE_FC_NP_VC1_BASE_IDX                                                                5
+#define regBIFP4_PCIE_FC_CPL_VC1                                                                        0x411065
+#define regBIFP4_PCIE_FC_CPL_VC1_BASE_IDX                                                               5
+#define regBIFP4_PCIE_ERR_CNTL                                                                          0x41106a
+#define regBIFP4_PCIE_ERR_CNTL_BASE_IDX                                                                 5
+#define regBIFP4_PCIE_RX_CNTL                                                                           0x411070
+#define regBIFP4_PCIE_RX_CNTL_BASE_IDX                                                                  5
+#define regBIFP4_PCIE_RX_EXPECTED_SEQNUM                                                                0x411071
+#define regBIFP4_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX                                                       5
+#define regBIFP4_PCIE_RX_VENDOR_SPECIFIC                                                                0x411072
+#define regBIFP4_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP4_PCIE_RX_CNTL3                                                                          0x411074
+#define regBIFP4_PCIE_RX_CNTL3_BASE_IDX                                                                 5
+#define regBIFP4_PCIE_RX_CREDITS_ALLOCATED_P                                                            0x411080
+#define regBIFP4_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX                                                   5
+#define regBIFP4_PCIE_RX_CREDITS_ALLOCATED_NP                                                           0x411081
+#define regBIFP4_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX                                                  5
+#define regBIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL                                                          0x411082
+#define regBIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX                                                 5
+#define regBIFP4_PCIEP_ERROR_INJECT_PHYSICAL                                                            0x411083
+#define regBIFP4_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX                                                   5
+#define regBIFP4_PCIEP_ERROR_INJECT_TRANSACTION                                                         0x411084
+#define regBIFP4_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX                                                5
+#define regBIFP4_PCIEP_NAK_COUNTER                                                                      0x411086
+#define regBIFP4_PCIEP_NAK_COUNTER_BASE_IDX                                                             5
+#define regBIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS                                                      0x411088
+#define regBIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_BASE_IDX                                             5
+#define regBIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES                                                 0x411089
+#define regBIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_BASE_IDX                                        5
+#define regBIFP4_PCIE_AER_PRIV_UNCORRECTABLE_MASK                                                       0x41108c
+#define regBIFP4_PCIE_AER_PRIV_UNCORRECTABLE_MASK_BASE_IDX                                              5
+#define regBIFP4_PCIE_AER_PRIV_TRIGGER                                                                  0x41108d
+#define regBIFP4_PCIE_AER_PRIV_TRIGGER_BASE_IDX                                                         5
+#define regBIFP4_PCIE_LC_CNTL                                                                           0x4110a0
+#define regBIFP4_PCIE_LC_CNTL_BASE_IDX                                                                  5
+#define regBIFP4_PCIE_LC_TRAINING_CNTL                                                                  0x4110a1
+#define regBIFP4_PCIE_LC_TRAINING_CNTL_BASE_IDX                                                         5
+#define regBIFP4_PCIE_LC_LINK_WIDTH_CNTL                                                                0x4110a2
+#define regBIFP4_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX                                                       5
+#define regBIFP4_PCIE_LC_N_FTS_CNTL                                                                     0x4110a3
+#define regBIFP4_PCIE_LC_N_FTS_CNTL_BASE_IDX                                                            5
+#define regBIFP4_PCIE_LC_SPEED_CNTL                                                                     0x4110a4
+#define regBIFP4_PCIE_LC_SPEED_CNTL_BASE_IDX                                                            5
+#define regBIFP4_PCIE_LC_STATE0                                                                         0x4110a5
+#define regBIFP4_PCIE_LC_STATE0_BASE_IDX                                                                5
+#define regBIFP4_PCIE_LC_STATE1                                                                         0x4110a6
+#define regBIFP4_PCIE_LC_STATE1_BASE_IDX                                                                5
+#define regBIFP4_PCIE_LC_STATE2                                                                         0x4110a7
+#define regBIFP4_PCIE_LC_STATE2_BASE_IDX                                                                5
+#define regBIFP4_PCIE_LC_STATE3                                                                         0x4110a8
+#define regBIFP4_PCIE_LC_STATE3_BASE_IDX                                                                5
+#define regBIFP4_PCIE_LC_STATE4                                                                         0x4110a9
+#define regBIFP4_PCIE_LC_STATE4_BASE_IDX                                                                5
+#define regBIFP4_PCIE_LC_STATE5                                                                         0x4110aa
+#define regBIFP4_PCIE_LC_STATE5_BASE_IDX                                                                5
+#define regBIFP4_PCIE_LINK_MANAGEMENT_CNTL2                                                             0x4110ab
+#define regBIFP4_PCIE_LINK_MANAGEMENT_CNTL2_BASE_IDX                                                    5
+#define regBIFP4_PCIE_LC_CNTL2                                                                          0x4110b1
+#define regBIFP4_PCIE_LC_CNTL2_BASE_IDX                                                                 5
+#define regBIFP4_PCIE_LC_BW_CHANGE_CNTL                                                                 0x4110b2
+#define regBIFP4_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX                                                        5
+#define regBIFP4_PCIE_LC_CDR_CNTL                                                                       0x4110b3
+#define regBIFP4_PCIE_LC_CDR_CNTL_BASE_IDX                                                              5
+#define regBIFP4_PCIE_LC_LANE_CNTL                                                                      0x4110b4
+#define regBIFP4_PCIE_LC_LANE_CNTL_BASE_IDX                                                             5
+#define regBIFP4_PCIE_LC_CNTL3                                                                          0x4110b5
+#define regBIFP4_PCIE_LC_CNTL3_BASE_IDX                                                                 5
+#define regBIFP4_PCIE_LC_CNTL4                                                                          0x4110b6
+#define regBIFP4_PCIE_LC_CNTL4_BASE_IDX                                                                 5
+#define regBIFP4_PCIE_LC_CNTL5                                                                          0x4110b7
+#define regBIFP4_PCIE_LC_CNTL5_BASE_IDX                                                                 5
+#define regBIFP4_PCIE_LC_FORCE_COEFF                                                                    0x4110b8
+#define regBIFP4_PCIE_LC_FORCE_COEFF_BASE_IDX                                                           5
+#define regBIFP4_PCIE_LC_BEST_EQ_SETTINGS                                                               0x4110b9
+#define regBIFP4_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX                                                      5
+#define regBIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF                                                             0x4110ba
+#define regBIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX                                                    5
+#define regBIFP4_PCIE_LC_CNTL6                                                                          0x4110bb
+#define regBIFP4_PCIE_LC_CNTL6_BASE_IDX                                                                 5
+#define regBIFP4_PCIE_LC_CNTL7                                                                          0x4110bc
+#define regBIFP4_PCIE_LC_CNTL7_BASE_IDX                                                                 5
+#define regBIFP4_PCIE_LINK_MANAGEMENT_STATUS                                                            0x4110bd
+#define regBIFP4_PCIE_LINK_MANAGEMENT_STATUS_BASE_IDX                                                   5
+#define regBIFP4_PCIE_LINK_MANAGEMENT_MASK                                                              0x4110be
+#define regBIFP4_PCIE_LINK_MANAGEMENT_MASK_BASE_IDX                                                     5
+#define regBIFP4_PCIE_LINK_MANAGEMENT_CNTL                                                              0x4110bf
+#define regBIFP4_PCIE_LINK_MANAGEMENT_CNTL_BASE_IDX                                                     5
+#define regBIFP4_PCIEP_STRAP_LC                                                                         0x4110c0
+#define regBIFP4_PCIEP_STRAP_LC_BASE_IDX                                                                5
+#define regBIFP4_PCIEP_STRAP_MISC                                                                       0x4110c1
+#define regBIFP4_PCIEP_STRAP_MISC_BASE_IDX                                                              5
+#define regBIFP4_PCIEP_STRAP_LC2                                                                        0x4110c2
+#define regBIFP4_PCIEP_STRAP_LC2_BASE_IDX                                                               5
+#define regBIFP4_PCIE_LC_L1_PM_SUBSTATE                                                                 0x4110c6
+#define regBIFP4_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX                                                        5
+#define regBIFP4_PCIE_LC_L1_PM_SUBSTATE2                                                                0x4110c7
+#define regBIFP4_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX                                                       5
+#define regBIFP4_PCIE_LC_PORT_ORDER                                                                     0x4110c8
+#define regBIFP4_PCIE_LC_PORT_ORDER_BASE_IDX                                                            5
+#define regBIFP4_PCIEP_BCH_ECC_CNTL                                                                     0x4110d0
+#define regBIFP4_PCIEP_BCH_ECC_CNTL_BASE_IDX                                                            5
+#define regBIFP4_PCIEP_HPGI_PRIVATE                                                                     0x4110d2
+#define regBIFP4_PCIEP_HPGI_PRIVATE_BASE_IDX                                                            5
+#define regBIFP4_PCIEP_HPGI                                                                             0x4110da
+#define regBIFP4_PCIEP_HPGI_BASE_IDX                                                                    5
+#define regBIFP4_PCIEP_HCNT_DESCRIPTOR                                                                  0x4110db
+#define regBIFP4_PCIEP_HCNT_DESCRIPTOR_BASE_IDX                                                         5
+#define regBIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK                                                            0x4110dc
+#define regBIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_BASE_IDX                                                   5
+#define regBIFP4_PCIE_LC_CNTL8                                                                          0x4110dd
+#define regBIFP4_PCIE_LC_CNTL8_BASE_IDX                                                                 5
+#define regBIFP4_PCIE_LC_CNTL9                                                                          0x4110de
+#define regBIFP4_PCIE_LC_CNTL9_BASE_IDX                                                                 5
+#define regBIFP4_PCIE_LC_FORCE_COEFF2                                                                   0x4110df
+#define regBIFP4_PCIE_LC_FORCE_COEFF2_BASE_IDX                                                          5
+#define regBIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2                                                            0x4110e0
+#define regBIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX                                                   5
+#define regBIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC                                                         0x4110e1
+#define regBIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC_BASE_IDX                                                5
+#define regBIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES                                                  0x4110e2
+#define regBIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX                                         5
+#define regBIFP4_PCIE_LC_CNTL10                                                                         0x4110e3
+#define regBIFP4_PCIE_LC_CNTL10_BASE_IDX                                                                5
+#define regBIFP4_PCIE_LC_CNTL11                                                                         0x4110e4
+#define regBIFP4_PCIE_LC_CNTL11_BASE_IDX                                                                5
+#define regBIFP4_PCIE_LC_CNTL12                                                                         0x4110e5
+#define regBIFP4_PCIE_LC_CNTL12_BASE_IDX                                                                5
+#define regBIFP4_PCIE_LC_SAVE_RESTORE_1                                                                 0x4110e6
+#define regBIFP4_PCIE_LC_SAVE_RESTORE_1_BASE_IDX                                                        5
+#define regBIFP4_PCIE_LC_SAVE_RESTORE_2                                                                 0x4110e7
+#define regBIFP4_PCIE_LC_SAVE_RESTORE_2_BASE_IDX                                                        5
+#define regBIFP4_PCIE_LC_SAVE_RESTORE_3                                                                 0x4110e8
+#define regBIFP4_PCIE_LC_SAVE_RESTORE_3_BASE_IDX                                                        5
+
+
+// addressBlock: nbio_pcie0_bifp5_pciedir_p
+// base address: 0x11145000
+#define regBIFP5_PCIEP_RESERVED                                                                         0x411400
+#define regBIFP5_PCIEP_RESERVED_BASE_IDX                                                                5
+#define regBIFP5_PCIEP_SCRATCH                                                                          0x411401
+#define regBIFP5_PCIEP_SCRATCH_BASE_IDX                                                                 5
+#define regBIFP5_PCIEP_PORT_CNTL                                                                        0x411410
+#define regBIFP5_PCIEP_PORT_CNTL_BASE_IDX                                                               5
+#define regBIFP5_PCIE_TX_CNTL                                                                           0x411420
+#define regBIFP5_PCIE_TX_CNTL_BASE_IDX                                                                  5
+#define regBIFP5_PCIE_TX_REQUESTER_ID                                                                   0x411421
+#define regBIFP5_PCIE_TX_REQUESTER_ID_BASE_IDX                                                          5
+#define regBIFP5_PCIE_TX_VENDOR_SPECIFIC                                                                0x411422
+#define regBIFP5_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP5_PCIE_TX_REQUEST_NUM_CNTL                                                               0x411423
+#define regBIFP5_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX                                                      5
+#define regBIFP5_PCIE_TX_SEQ                                                                            0x411424
+#define regBIFP5_PCIE_TX_SEQ_BASE_IDX                                                                   5
+#define regBIFP5_PCIE_TX_REPLAY                                                                         0x411425
+#define regBIFP5_PCIE_TX_REPLAY_BASE_IDX                                                                5
+#define regBIFP5_PCIE_TX_ACK_LATENCY_LIMIT                                                              0x411426
+#define regBIFP5_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX                                                     5
+#define regBIFP5_PCIE_TX_NOP_DLLP                                                                       0x411427
+#define regBIFP5_PCIE_TX_NOP_DLLP_BASE_IDX                                                              5
+#define regBIFP5_PCIE_TX_CNTL_2                                                                         0x411428
+#define regBIFP5_PCIE_TX_CNTL_2_BASE_IDX                                                                5
+#define regBIFP5_PCIE_TX_SKID_CTRL                                                                      0x41142f
+#define regBIFP5_PCIE_TX_SKID_CTRL_BASE_IDX                                                             5
+#define regBIFP5_PCIE_TX_CREDITS_ADVT_P                                                                 0x411430
+#define regBIFP5_PCIE_TX_CREDITS_ADVT_P_BASE_IDX                                                        5
+#define regBIFP5_PCIE_TX_CREDITS_ADVT_NP                                                                0x411431
+#define regBIFP5_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX                                                       5
+#define regBIFP5_PCIE_TX_CREDITS_ADVT_CPL                                                               0x411432
+#define regBIFP5_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX                                                      5
+#define regBIFP5_PCIE_TX_CREDITS_INIT_P                                                                 0x411433
+#define regBIFP5_PCIE_TX_CREDITS_INIT_P_BASE_IDX                                                        5
+#define regBIFP5_PCIE_TX_CREDITS_INIT_NP                                                                0x411434
+#define regBIFP5_PCIE_TX_CREDITS_INIT_NP_BASE_IDX                                                       5
+#define regBIFP5_PCIE_TX_CREDITS_INIT_CPL                                                               0x411435
+#define regBIFP5_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX                                                      5
+#define regBIFP5_PCIE_TX_CREDITS_STATUS                                                                 0x411436
+#define regBIFP5_PCIE_TX_CREDITS_STATUS_BASE_IDX                                                        5
+#define regBIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD                                                          0x411437
+#define regBIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX                                                 5
+#define regBIFP5_PCIE_TX_CCIX_PORT_CNTL0                                                                0x411438
+#define regBIFP5_PCIE_TX_CCIX_PORT_CNTL0_BASE_IDX                                                       5
+#define regBIFP5_PCIE_TX_CCIX_PORT_CNTL1                                                                0x411439
+#define regBIFP5_PCIE_TX_CCIX_PORT_CNTL1_BASE_IDX                                                       5
+#define regBIFP5_PCIE_CCIX_STACKED_BASE                                                                 0x41143a
+#define regBIFP5_PCIE_CCIX_STACKED_BASE_BASE_IDX                                                        5
+#define regBIFP5_PCIE_CCIX_STACKED_LIMIT                                                                0x41143b
+#define regBIFP5_PCIE_CCIX_STACKED_LIMIT_BASE_IDX                                                       5
+#define regBIFP5_PCIE_CCIX_MISC_STATUS                                                                  0x411441
+#define regBIFP5_PCIE_CCIX_MISC_STATUS_BASE_IDX                                                         5
+#define regBIFP5_PCIE_P_PORT_LANE_STATUS                                                                0x411450
+#define regBIFP5_PCIE_P_PORT_LANE_STATUS_BASE_IDX                                                       5
+#define regBIFP5_PCIE_FC_P                                                                              0x411460
+#define regBIFP5_PCIE_FC_P_BASE_IDX                                                                     5
+#define regBIFP5_PCIE_FC_NP                                                                             0x411461
+#define regBIFP5_PCIE_FC_NP_BASE_IDX                                                                    5
+#define regBIFP5_PCIE_FC_CPL                                                                            0x411462
+#define regBIFP5_PCIE_FC_CPL_BASE_IDX                                                                   5
+#define regBIFP5_PCIE_FC_P_VC1                                                                          0x411463
+#define regBIFP5_PCIE_FC_P_VC1_BASE_IDX                                                                 5
+#define regBIFP5_PCIE_FC_NP_VC1                                                                         0x411464
+#define regBIFP5_PCIE_FC_NP_VC1_BASE_IDX                                                                5
+#define regBIFP5_PCIE_FC_CPL_VC1                                                                        0x411465
+#define regBIFP5_PCIE_FC_CPL_VC1_BASE_IDX                                                               5
+#define regBIFP5_PCIE_ERR_CNTL                                                                          0x41146a
+#define regBIFP5_PCIE_ERR_CNTL_BASE_IDX                                                                 5
+#define regBIFP5_PCIE_RX_CNTL                                                                           0x411470
+#define regBIFP5_PCIE_RX_CNTL_BASE_IDX                                                                  5
+#define regBIFP5_PCIE_RX_EXPECTED_SEQNUM                                                                0x411471
+#define regBIFP5_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX                                                       5
+#define regBIFP5_PCIE_RX_VENDOR_SPECIFIC                                                                0x411472
+#define regBIFP5_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP5_PCIE_RX_CNTL3                                                                          0x411474
+#define regBIFP5_PCIE_RX_CNTL3_BASE_IDX                                                                 5
+#define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_P                                                            0x411480
+#define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX                                                   5
+#define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_NP                                                           0x411481
+#define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX                                                  5
+#define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL                                                          0x411482
+#define regBIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX                                                 5
+#define regBIFP5_PCIEP_ERROR_INJECT_PHYSICAL                                                            0x411483
+#define regBIFP5_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX                                                   5
+#define regBIFP5_PCIEP_ERROR_INJECT_TRANSACTION                                                         0x411484
+#define regBIFP5_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX                                                5
+#define regBIFP5_PCIEP_NAK_COUNTER                                                                      0x411486
+#define regBIFP5_PCIEP_NAK_COUNTER_BASE_IDX                                                             5
+#define regBIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS                                                      0x411488
+#define regBIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_BASE_IDX                                             5
+#define regBIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES                                                 0x411489
+#define regBIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_BASE_IDX                                        5
+#define regBIFP5_PCIE_AER_PRIV_UNCORRECTABLE_MASK                                                       0x41148c
+#define regBIFP5_PCIE_AER_PRIV_UNCORRECTABLE_MASK_BASE_IDX                                              5
+#define regBIFP5_PCIE_AER_PRIV_TRIGGER                                                                  0x41148d
+#define regBIFP5_PCIE_AER_PRIV_TRIGGER_BASE_IDX                                                         5
+#define regBIFP5_PCIE_LC_CNTL                                                                           0x4114a0
+#define regBIFP5_PCIE_LC_CNTL_BASE_IDX                                                                  5
+#define regBIFP5_PCIE_LC_TRAINING_CNTL                                                                  0x4114a1
+#define regBIFP5_PCIE_LC_TRAINING_CNTL_BASE_IDX                                                         5
+#define regBIFP5_PCIE_LC_LINK_WIDTH_CNTL                                                                0x4114a2
+#define regBIFP5_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX                                                       5
+#define regBIFP5_PCIE_LC_N_FTS_CNTL                                                                     0x4114a3
+#define regBIFP5_PCIE_LC_N_FTS_CNTL_BASE_IDX                                                            5
+#define regBIFP5_PCIE_LC_SPEED_CNTL                                                                     0x4114a4
+#define regBIFP5_PCIE_LC_SPEED_CNTL_BASE_IDX                                                            5
+#define regBIFP5_PCIE_LC_STATE0                                                                         0x4114a5
+#define regBIFP5_PCIE_LC_STATE0_BASE_IDX                                                                5
+#define regBIFP5_PCIE_LC_STATE1                                                                         0x4114a6
+#define regBIFP5_PCIE_LC_STATE1_BASE_IDX                                                                5
+#define regBIFP5_PCIE_LC_STATE2                                                                         0x4114a7
+#define regBIFP5_PCIE_LC_STATE2_BASE_IDX                                                                5
+#define regBIFP5_PCIE_LC_STATE3                                                                         0x4114a8
+#define regBIFP5_PCIE_LC_STATE3_BASE_IDX                                                                5
+#define regBIFP5_PCIE_LC_STATE4                                                                         0x4114a9
+#define regBIFP5_PCIE_LC_STATE4_BASE_IDX                                                                5
+#define regBIFP5_PCIE_LC_STATE5                                                                         0x4114aa
+#define regBIFP5_PCIE_LC_STATE5_BASE_IDX                                                                5
+#define regBIFP5_PCIE_LINK_MANAGEMENT_CNTL2                                                             0x4114ab
+#define regBIFP5_PCIE_LINK_MANAGEMENT_CNTL2_BASE_IDX                                                    5
+#define regBIFP5_PCIE_LC_CNTL2                                                                          0x4114b1
+#define regBIFP5_PCIE_LC_CNTL2_BASE_IDX                                                                 5
+#define regBIFP5_PCIE_LC_BW_CHANGE_CNTL                                                                 0x4114b2
+#define regBIFP5_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX                                                        5
+#define regBIFP5_PCIE_LC_CDR_CNTL                                                                       0x4114b3
+#define regBIFP5_PCIE_LC_CDR_CNTL_BASE_IDX                                                              5
+#define regBIFP5_PCIE_LC_LANE_CNTL                                                                      0x4114b4
+#define regBIFP5_PCIE_LC_LANE_CNTL_BASE_IDX                                                             5
+#define regBIFP5_PCIE_LC_CNTL3                                                                          0x4114b5
+#define regBIFP5_PCIE_LC_CNTL3_BASE_IDX                                                                 5
+#define regBIFP5_PCIE_LC_CNTL4                                                                          0x4114b6
+#define regBIFP5_PCIE_LC_CNTL4_BASE_IDX                                                                 5
+#define regBIFP5_PCIE_LC_CNTL5                                                                          0x4114b7
+#define regBIFP5_PCIE_LC_CNTL5_BASE_IDX                                                                 5
+#define regBIFP5_PCIE_LC_FORCE_COEFF                                                                    0x4114b8
+#define regBIFP5_PCIE_LC_FORCE_COEFF_BASE_IDX                                                           5
+#define regBIFP5_PCIE_LC_BEST_EQ_SETTINGS                                                               0x4114b9
+#define regBIFP5_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX                                                      5
+#define regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF                                                             0x4114ba
+#define regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX                                                    5
+#define regBIFP5_PCIE_LC_CNTL6                                                                          0x4114bb
+#define regBIFP5_PCIE_LC_CNTL6_BASE_IDX                                                                 5
+#define regBIFP5_PCIE_LC_CNTL7                                                                          0x4114bc
+#define regBIFP5_PCIE_LC_CNTL7_BASE_IDX                                                                 5
+#define regBIFP5_PCIE_LINK_MANAGEMENT_STATUS                                                            0x4114bd
+#define regBIFP5_PCIE_LINK_MANAGEMENT_STATUS_BASE_IDX                                                   5
+#define regBIFP5_PCIE_LINK_MANAGEMENT_MASK                                                              0x4114be
+#define regBIFP5_PCIE_LINK_MANAGEMENT_MASK_BASE_IDX                                                     5
+#define regBIFP5_PCIE_LINK_MANAGEMENT_CNTL                                                              0x4114bf
+#define regBIFP5_PCIE_LINK_MANAGEMENT_CNTL_BASE_IDX                                                     5
+#define regBIFP5_PCIEP_STRAP_LC                                                                         0x4114c0
+#define regBIFP5_PCIEP_STRAP_LC_BASE_IDX                                                                5
+#define regBIFP5_PCIEP_STRAP_MISC                                                                       0x4114c1
+#define regBIFP5_PCIEP_STRAP_MISC_BASE_IDX                                                              5
+#define regBIFP5_PCIEP_STRAP_LC2                                                                        0x4114c2
+#define regBIFP5_PCIEP_STRAP_LC2_BASE_IDX                                                               5
+#define regBIFP5_PCIE_LC_L1_PM_SUBSTATE                                                                 0x4114c6
+#define regBIFP5_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX                                                        5
+#define regBIFP5_PCIE_LC_L1_PM_SUBSTATE2                                                                0x4114c7
+#define regBIFP5_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX                                                       5
+#define regBIFP5_PCIE_LC_PORT_ORDER                                                                     0x4114c8
+#define regBIFP5_PCIE_LC_PORT_ORDER_BASE_IDX                                                            5
+#define regBIFP5_PCIEP_BCH_ECC_CNTL                                                                     0x4114d0
+#define regBIFP5_PCIEP_BCH_ECC_CNTL_BASE_IDX                                                            5
+#define regBIFP5_PCIEP_HPGI_PRIVATE                                                                     0x4114d2
+#define regBIFP5_PCIEP_HPGI_PRIVATE_BASE_IDX                                                            5
+#define regBIFP5_PCIEP_HPGI                                                                             0x4114da
+#define regBIFP5_PCIEP_HPGI_BASE_IDX                                                                    5
+#define regBIFP5_PCIEP_HCNT_DESCRIPTOR                                                                  0x4114db
+#define regBIFP5_PCIEP_HCNT_DESCRIPTOR_BASE_IDX                                                         5
+#define regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK                                                            0x4114dc
+#define regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_BASE_IDX                                                   5
+#define regBIFP5_PCIE_LC_CNTL8                                                                          0x4114dd
+#define regBIFP5_PCIE_LC_CNTL8_BASE_IDX                                                                 5
+#define regBIFP5_PCIE_LC_CNTL9                                                                          0x4114de
+#define regBIFP5_PCIE_LC_CNTL9_BASE_IDX                                                                 5
+#define regBIFP5_PCIE_LC_FORCE_COEFF2                                                                   0x4114df
+#define regBIFP5_PCIE_LC_FORCE_COEFF2_BASE_IDX                                                          5
+#define regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2                                                            0x4114e0
+#define regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX                                                   5
+#define regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC                                                         0x4114e1
+#define regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC_BASE_IDX                                                5
+#define regBIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES                                                  0x4114e2
+#define regBIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX                                         5
+#define regBIFP5_PCIE_LC_CNTL10                                                                         0x4114e3
+#define regBIFP5_PCIE_LC_CNTL10_BASE_IDX                                                                5
+#define regBIFP5_PCIE_LC_CNTL11                                                                         0x4114e4
+#define regBIFP5_PCIE_LC_CNTL11_BASE_IDX                                                                5
+#define regBIFP5_PCIE_LC_CNTL12                                                                         0x4114e5
+#define regBIFP5_PCIE_LC_CNTL12_BASE_IDX                                                                5
+#define regBIFP5_PCIE_LC_SAVE_RESTORE_1                                                                 0x4114e6
+#define regBIFP5_PCIE_LC_SAVE_RESTORE_1_BASE_IDX                                                        5
+#define regBIFP5_PCIE_LC_SAVE_RESTORE_2                                                                 0x4114e7
+#define regBIFP5_PCIE_LC_SAVE_RESTORE_2_BASE_IDX                                                        5
+#define regBIFP5_PCIE_LC_SAVE_RESTORE_3                                                                 0x4114e8
+#define regBIFP5_PCIE_LC_SAVE_RESTORE_3_BASE_IDX                                                        5
+
+
+// addressBlock: nbio_pcie0_bifp6_pciedir_p
+// base address: 0x11146000
+#define regBIFP6_PCIEP_RESERVED                                                                         0x411800
+#define regBIFP6_PCIEP_RESERVED_BASE_IDX                                                                5
+#define regBIFP6_PCIEP_SCRATCH                                                                          0x411801
+#define regBIFP6_PCIEP_SCRATCH_BASE_IDX                                                                 5
+#define regBIFP6_PCIEP_PORT_CNTL                                                                        0x411810
+#define regBIFP6_PCIEP_PORT_CNTL_BASE_IDX                                                               5
+#define regBIFP6_PCIE_TX_CNTL                                                                           0x411820
+#define regBIFP6_PCIE_TX_CNTL_BASE_IDX                                                                  5
+#define regBIFP6_PCIE_TX_REQUESTER_ID                                                                   0x411821
+#define regBIFP6_PCIE_TX_REQUESTER_ID_BASE_IDX                                                          5
+#define regBIFP6_PCIE_TX_VENDOR_SPECIFIC                                                                0x411822
+#define regBIFP6_PCIE_TX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP6_PCIE_TX_REQUEST_NUM_CNTL                                                               0x411823
+#define regBIFP6_PCIE_TX_REQUEST_NUM_CNTL_BASE_IDX                                                      5
+#define regBIFP6_PCIE_TX_SEQ                                                                            0x411824
+#define regBIFP6_PCIE_TX_SEQ_BASE_IDX                                                                   5
+#define regBIFP6_PCIE_TX_REPLAY                                                                         0x411825
+#define regBIFP6_PCIE_TX_REPLAY_BASE_IDX                                                                5
+#define regBIFP6_PCIE_TX_ACK_LATENCY_LIMIT                                                              0x411826
+#define regBIFP6_PCIE_TX_ACK_LATENCY_LIMIT_BASE_IDX                                                     5
+#define regBIFP6_PCIE_TX_NOP_DLLP                                                                       0x411827
+#define regBIFP6_PCIE_TX_NOP_DLLP_BASE_IDX                                                              5
+#define regBIFP6_PCIE_TX_CNTL_2                                                                         0x411828
+#define regBIFP6_PCIE_TX_CNTL_2_BASE_IDX                                                                5
+#define regBIFP6_PCIE_TX_SKID_CTRL                                                                      0x41182f
+#define regBIFP6_PCIE_TX_SKID_CTRL_BASE_IDX                                                             5
+#define regBIFP6_PCIE_TX_CREDITS_ADVT_P                                                                 0x411830
+#define regBIFP6_PCIE_TX_CREDITS_ADVT_P_BASE_IDX                                                        5
+#define regBIFP6_PCIE_TX_CREDITS_ADVT_NP                                                                0x411831
+#define regBIFP6_PCIE_TX_CREDITS_ADVT_NP_BASE_IDX                                                       5
+#define regBIFP6_PCIE_TX_CREDITS_ADVT_CPL                                                               0x411832
+#define regBIFP6_PCIE_TX_CREDITS_ADVT_CPL_BASE_IDX                                                      5
+#define regBIFP6_PCIE_TX_CREDITS_INIT_P                                                                 0x411833
+#define regBIFP6_PCIE_TX_CREDITS_INIT_P_BASE_IDX                                                        5
+#define regBIFP6_PCIE_TX_CREDITS_INIT_NP                                                                0x411834
+#define regBIFP6_PCIE_TX_CREDITS_INIT_NP_BASE_IDX                                                       5
+#define regBIFP6_PCIE_TX_CREDITS_INIT_CPL                                                               0x411835
+#define regBIFP6_PCIE_TX_CREDITS_INIT_CPL_BASE_IDX                                                      5
+#define regBIFP6_PCIE_TX_CREDITS_STATUS                                                                 0x411836
+#define regBIFP6_PCIE_TX_CREDITS_STATUS_BASE_IDX                                                        5
+#define regBIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD                                                          0x411837
+#define regBIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD_BASE_IDX                                                 5
+#define regBIFP6_PCIE_TX_CCIX_PORT_CNTL0                                                                0x411838
+#define regBIFP6_PCIE_TX_CCIX_PORT_CNTL0_BASE_IDX                                                       5
+#define regBIFP6_PCIE_TX_CCIX_PORT_CNTL1                                                                0x411839
+#define regBIFP6_PCIE_TX_CCIX_PORT_CNTL1_BASE_IDX                                                       5
+#define regBIFP6_PCIE_CCIX_STACKED_BASE                                                                 0x41183a
+#define regBIFP6_PCIE_CCIX_STACKED_BASE_BASE_IDX                                                        5
+#define regBIFP6_PCIE_CCIX_STACKED_LIMIT                                                                0x41183b
+#define regBIFP6_PCIE_CCIX_STACKED_LIMIT_BASE_IDX                                                       5
+#define regBIFP6_PCIE_CCIX_MISC_STATUS                                                                  0x411841
+#define regBIFP6_PCIE_CCIX_MISC_STATUS_BASE_IDX                                                         5
+#define regBIFP6_PCIE_P_PORT_LANE_STATUS                                                                0x411850
+#define regBIFP6_PCIE_P_PORT_LANE_STATUS_BASE_IDX                                                       5
+#define regBIFP6_PCIE_FC_P                                                                              0x411860
+#define regBIFP6_PCIE_FC_P_BASE_IDX                                                                     5
+#define regBIFP6_PCIE_FC_NP                                                                             0x411861
+#define regBIFP6_PCIE_FC_NP_BASE_IDX                                                                    5
+#define regBIFP6_PCIE_FC_CPL                                                                            0x411862
+#define regBIFP6_PCIE_FC_CPL_BASE_IDX                                                                   5
+#define regBIFP6_PCIE_FC_P_VC1                                                                          0x411863
+#define regBIFP6_PCIE_FC_P_VC1_BASE_IDX                                                                 5
+#define regBIFP6_PCIE_FC_NP_VC1                                                                         0x411864
+#define regBIFP6_PCIE_FC_NP_VC1_BASE_IDX                                                                5
+#define regBIFP6_PCIE_FC_CPL_VC1                                                                        0x411865
+#define regBIFP6_PCIE_FC_CPL_VC1_BASE_IDX                                                               5
+#define regBIFP6_PCIE_ERR_CNTL                                                                          0x41186a
+#define regBIFP6_PCIE_ERR_CNTL_BASE_IDX                                                                 5
+#define regBIFP6_PCIE_RX_CNTL                                                                           0x411870
+#define regBIFP6_PCIE_RX_CNTL_BASE_IDX                                                                  5
+#define regBIFP6_PCIE_RX_EXPECTED_SEQNUM                                                                0x411871
+#define regBIFP6_PCIE_RX_EXPECTED_SEQNUM_BASE_IDX                                                       5
+#define regBIFP6_PCIE_RX_VENDOR_SPECIFIC                                                                0x411872
+#define regBIFP6_PCIE_RX_VENDOR_SPECIFIC_BASE_IDX                                                       5
+#define regBIFP6_PCIE_RX_CNTL3                                                                          0x411874
+#define regBIFP6_PCIE_RX_CNTL3_BASE_IDX                                                                 5
+#define regBIFP6_PCIE_RX_CREDITS_ALLOCATED_P                                                            0x411880
+#define regBIFP6_PCIE_RX_CREDITS_ALLOCATED_P_BASE_IDX                                                   5
+#define regBIFP6_PCIE_RX_CREDITS_ALLOCATED_NP                                                           0x411881
+#define regBIFP6_PCIE_RX_CREDITS_ALLOCATED_NP_BASE_IDX                                                  5
+#define regBIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL                                                          0x411882
+#define regBIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL_BASE_IDX                                                 5
+#define regBIFP6_PCIEP_ERROR_INJECT_PHYSICAL                                                            0x411883
+#define regBIFP6_PCIEP_ERROR_INJECT_PHYSICAL_BASE_IDX                                                   5
+#define regBIFP6_PCIEP_ERROR_INJECT_TRANSACTION                                                         0x411884
+#define regBIFP6_PCIEP_ERROR_INJECT_TRANSACTION_BASE_IDX                                                5
+#define regBIFP6_PCIEP_NAK_COUNTER                                                                      0x411886
+#define regBIFP6_PCIEP_NAK_COUNTER_BASE_IDX                                                             5
+#define regBIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS                                                      0x411888
+#define regBIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_BASE_IDX                                             5
+#define regBIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES                                                 0x411889
+#define regBIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_BASE_IDX                                        5
+#define regBIFP6_PCIE_AER_PRIV_UNCORRECTABLE_MASK                                                       0x41188c
+#define regBIFP6_PCIE_AER_PRIV_UNCORRECTABLE_MASK_BASE_IDX                                              5
+#define regBIFP6_PCIE_AER_PRIV_TRIGGER                                                                  0x41188d
+#define regBIFP6_PCIE_AER_PRIV_TRIGGER_BASE_IDX                                                         5
+#define regBIFP6_PCIE_LC_CNTL                                                                           0x4118a0
+#define regBIFP6_PCIE_LC_CNTL_BASE_IDX                                                                  5
+#define regBIFP6_PCIE_LC_TRAINING_CNTL                                                                  0x4118a1
+#define regBIFP6_PCIE_LC_TRAINING_CNTL_BASE_IDX                                                         5
+#define regBIFP6_PCIE_LC_LINK_WIDTH_CNTL                                                                0x4118a2
+#define regBIFP6_PCIE_LC_LINK_WIDTH_CNTL_BASE_IDX                                                       5
+#define regBIFP6_PCIE_LC_N_FTS_CNTL                                                                     0x4118a3
+#define regBIFP6_PCIE_LC_N_FTS_CNTL_BASE_IDX                                                            5
+#define regBIFP6_PCIE_LC_SPEED_CNTL                                                                     0x4118a4
+#define regBIFP6_PCIE_LC_SPEED_CNTL_BASE_IDX                                                            5
+#define regBIFP6_PCIE_LC_STATE0                                                                         0x4118a5
+#define regBIFP6_PCIE_LC_STATE0_BASE_IDX                                                                5
+#define regBIFP6_PCIE_LC_STATE1                                                                         0x4118a6
+#define regBIFP6_PCIE_LC_STATE1_BASE_IDX                                                                5
+#define regBIFP6_PCIE_LC_STATE2                                                                         0x4118a7
+#define regBIFP6_PCIE_LC_STATE2_BASE_IDX                                                                5
+#define regBIFP6_PCIE_LC_STATE3                                                                         0x4118a8
+#define regBIFP6_PCIE_LC_STATE3_BASE_IDX                                                                5
+#define regBIFP6_PCIE_LC_STATE4                                                                         0x4118a9
+#define regBIFP6_PCIE_LC_STATE4_BASE_IDX                                                                5
+#define regBIFP6_PCIE_LC_STATE5                                                                         0x4118aa
+#define regBIFP6_PCIE_LC_STATE5_BASE_IDX                                                                5
+#define regBIFP6_PCIE_LINK_MANAGEMENT_CNTL2                                                             0x4118ab
+#define regBIFP6_PCIE_LINK_MANAGEMENT_CNTL2_BASE_IDX                                                    5
+#define regBIFP6_PCIE_LC_CNTL2                                                                          0x4118b1
+#define regBIFP6_PCIE_LC_CNTL2_BASE_IDX                                                                 5
+#define regBIFP6_PCIE_LC_BW_CHANGE_CNTL                                                                 0x4118b2
+#define regBIFP6_PCIE_LC_BW_CHANGE_CNTL_BASE_IDX                                                        5
+#define regBIFP6_PCIE_LC_CDR_CNTL                                                                       0x4118b3
+#define regBIFP6_PCIE_LC_CDR_CNTL_BASE_IDX                                                              5
+#define regBIFP6_PCIE_LC_LANE_CNTL                                                                      0x4118b4
+#define regBIFP6_PCIE_LC_LANE_CNTL_BASE_IDX                                                             5
+#define regBIFP6_PCIE_LC_CNTL3                                                                          0x4118b5
+#define regBIFP6_PCIE_LC_CNTL3_BASE_IDX                                                                 5
+#define regBIFP6_PCIE_LC_CNTL4                                                                          0x4118b6
+#define regBIFP6_PCIE_LC_CNTL4_BASE_IDX                                                                 5
+#define regBIFP6_PCIE_LC_CNTL5                                                                          0x4118b7
+#define regBIFP6_PCIE_LC_CNTL5_BASE_IDX                                                                 5
+#define regBIFP6_PCIE_LC_FORCE_COEFF                                                                    0x4118b8
+#define regBIFP6_PCIE_LC_FORCE_COEFF_BASE_IDX                                                           5
+#define regBIFP6_PCIE_LC_BEST_EQ_SETTINGS                                                               0x4118b9
+#define regBIFP6_PCIE_LC_BEST_EQ_SETTINGS_BASE_IDX                                                      5
+#define regBIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF                                                             0x4118ba
+#define regBIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF_BASE_IDX                                                    5
+#define regBIFP6_PCIE_LC_CNTL6                                                                          0x4118bb
+#define regBIFP6_PCIE_LC_CNTL6_BASE_IDX                                                                 5
+#define regBIFP6_PCIE_LC_CNTL7                                                                          0x4118bc
+#define regBIFP6_PCIE_LC_CNTL7_BASE_IDX                                                                 5
+#define regBIFP6_PCIE_LINK_MANAGEMENT_STATUS                                                            0x4118bd
+#define regBIFP6_PCIE_LINK_MANAGEMENT_STATUS_BASE_IDX                                                   5
+#define regBIFP6_PCIE_LINK_MANAGEMENT_MASK                                                              0x4118be
+#define regBIFP6_PCIE_LINK_MANAGEMENT_MASK_BASE_IDX                                                     5
+#define regBIFP6_PCIE_LINK_MANAGEMENT_CNTL                                                              0x4118bf
+#define regBIFP6_PCIE_LINK_MANAGEMENT_CNTL_BASE_IDX                                                     5
+#define regBIFP6_PCIEP_STRAP_LC                                                                         0x4118c0
+#define regBIFP6_PCIEP_STRAP_LC_BASE_IDX                                                                5
+#define regBIFP6_PCIEP_STRAP_MISC                                                                       0x4118c1
+#define regBIFP6_PCIEP_STRAP_MISC_BASE_IDX                                                              5
+#define regBIFP6_PCIEP_STRAP_LC2                                                                        0x4118c2
+#define regBIFP6_PCIEP_STRAP_LC2_BASE_IDX                                                               5
+#define regBIFP6_PCIE_LC_L1_PM_SUBSTATE                                                                 0x4118c6
+#define regBIFP6_PCIE_LC_L1_PM_SUBSTATE_BASE_IDX                                                        5
+#define regBIFP6_PCIE_LC_L1_PM_SUBSTATE2                                                                0x4118c7
+#define regBIFP6_PCIE_LC_L1_PM_SUBSTATE2_BASE_IDX                                                       5
+#define regBIFP6_PCIE_LC_PORT_ORDER                                                                     0x4118c8
+#define regBIFP6_PCIE_LC_PORT_ORDER_BASE_IDX                                                            5
+#define regBIFP6_PCIEP_BCH_ECC_CNTL                                                                     0x4118d0
+#define regBIFP6_PCIEP_BCH_ECC_CNTL_BASE_IDX                                                            5
+#define regBIFP6_PCIEP_HPGI_PRIVATE                                                                     0x4118d2
+#define regBIFP6_PCIEP_HPGI_PRIVATE_BASE_IDX                                                            5
+#define regBIFP6_PCIEP_HPGI                                                                             0x4118da
+#define regBIFP6_PCIEP_HPGI_BASE_IDX                                                                    5
+#define regBIFP6_PCIEP_HCNT_DESCRIPTOR                                                                  0x4118db
+#define regBIFP6_PCIEP_HCNT_DESCRIPTOR_BASE_IDX                                                         5
+#define regBIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK                                                            0x4118dc
+#define regBIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_BASE_IDX                                                   5
+#define regBIFP6_PCIE_LC_CNTL8                                                                          0x4118dd
+#define regBIFP6_PCIE_LC_CNTL8_BASE_IDX                                                                 5
+#define regBIFP6_PCIE_LC_CNTL9                                                                          0x4118de
+#define regBIFP6_PCIE_LC_CNTL9_BASE_IDX                                                                 5
+#define regBIFP6_PCIE_LC_FORCE_COEFF2                                                                   0x4118df
+#define regBIFP6_PCIE_LC_FORCE_COEFF2_BASE_IDX                                                          5
+#define regBIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2                                                            0x4118e0
+#define regBIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2_BASE_IDX                                                   5
+#define regBIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC                                                         0x4118e1
+#define regBIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC_BASE_IDX                                                5
+#define regBIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES                                                  0x4118e2
+#define regBIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES_BASE_IDX                                         5
+#define regBIFP6_PCIE_LC_CNTL10                                                                         0x4118e3
+#define regBIFP6_PCIE_LC_CNTL10_BASE_IDX                                                                5
+#define regBIFP6_PCIE_LC_CNTL11                                                                         0x4118e4
+#define regBIFP6_PCIE_LC_CNTL11_BASE_IDX                                                                5
+#define regBIFP6_PCIE_LC_CNTL12                                                                         0x4118e5
+#define regBIFP6_PCIE_LC_CNTL12_BASE_IDX                                                                5
+#define regBIFP6_PCIE_LC_SAVE_RESTORE_1                                                                 0x4118e6
+#define regBIFP6_PCIE_LC_SAVE_RESTORE_1_BASE_IDX                                                        5
+#define regBIFP6_PCIE_LC_SAVE_RESTORE_2                                                                 0x4118e7
+#define regBIFP6_PCIE_LC_SAVE_RESTORE_2_BASE_IDX                                                        5
+#define regBIFP6_PCIE_LC_SAVE_RESTORE_3                                                                 0x4118e8
+#define regBIFP6_PCIE_LC_SAVE_RESTORE_3_BASE_IDX                                                        5
+
+
+// addressBlock: nbio_pcie0_pciedir
+// base address: 0x11180000
+#define regPCIE_RESERVED                                                                                0x420000
+#define regPCIE_RESERVED_BASE_IDX                                                                       5
+#define regPCIE_SCRATCH                                                                                 0x420001
+#define regPCIE_SCRATCH_BASE_IDX                                                                        5
+#define regPCIE_RX_NUM_NAK                                                                              0x42000e
+#define regPCIE_RX_NUM_NAK_BASE_IDX                                                                     5
+#define regPCIE_RX_NUM_NAK_GENERATED                                                                    0x42000f
+#define regPCIE_RX_NUM_NAK_GENERATED_BASE_IDX                                                           5
+#define regPCIE_CNTL                                                                                    0x420010
+#define regPCIE_CNTL_BASE_IDX                                                                           5
+#define regPCIE_CONFIG_CNTL                                                                             0x420011
+#define regPCIE_CONFIG_CNTL_BASE_IDX                                                                    5
+#define regPCIE_TX_TRACKING_ADDR_LO                                                                     0x420013
+#define regPCIE_TX_TRACKING_ADDR_LO_BASE_IDX                                                            5
+#define regPCIE_TX_TRACKING_ADDR_HI                                                                     0x420014
+#define regPCIE_TX_TRACKING_ADDR_HI_BASE_IDX                                                            5
+#define regPCIE_TX_TRACKING_CTRL_STATUS                                                                 0x420015
+#define regPCIE_TX_TRACKING_CTRL_STATUS_BASE_IDX                                                        5
+#define regPCIE_TX_CTRL_4                                                                               0x420017
+#define regPCIE_TX_CTRL_4_BASE_IDX                                                                      5
+#define regPCIE_MST_CTRL_1                                                                              0x420018
+#define regPCIE_MST_CTRL_1_BASE_IDX                                                                     5
+#define regPCIE_COMMON_AER_MASK                                                                         0x42001a
+#define regPCIE_COMMON_AER_MASK_BASE_IDX                                                                5
+#define regPCIE_CNTL2                                                                                   0x42001c
+#define regPCIE_CNTL2_BASE_IDX                                                                          5
+#define regPCIE_RX_CNTL2                                                                                0x42001d
+#define regPCIE_RX_CNTL2_BASE_IDX                                                                       5
+#define regPCIE_TX_F0_ATTR_CNTL                                                                         0x42001e
+#define regPCIE_TX_F0_ATTR_CNTL_BASE_IDX                                                                5
+#define regPCIE_TX_SWUS_ATTR_CNTL                                                                       0x42001f
+#define regPCIE_TX_SWUS_ATTR_CNTL_BASE_IDX                                                              5
+#define regPCIE_CI_CNTL                                                                                 0x420020
+#define regPCIE_CI_CNTL_BASE_IDX                                                                        5
+#define regPCIE_BUS_CNTL                                                                                0x420021
+#define regPCIE_BUS_CNTL_BASE_IDX                                                                       5
+#define regPCIE_LC_STATE6                                                                               0x420022
+#define regPCIE_LC_STATE6_BASE_IDX                                                                      5
+#define regPCIE_LC_STATE7                                                                               0x420023
+#define regPCIE_LC_STATE7_BASE_IDX                                                                      5
+#define regPCIE_LC_STATE8                                                                               0x420024
+#define regPCIE_LC_STATE8_BASE_IDX                                                                      5
+#define regPCIE_LC_STATE9                                                                               0x420025
+#define regPCIE_LC_STATE9_BASE_IDX                                                                      5
+#define regPCIE_LC_STATE10                                                                              0x420026
+#define regPCIE_LC_STATE10_BASE_IDX                                                                     5
+#define regPCIE_LC_STATE11                                                                              0x420027
+#define regPCIE_LC_STATE11_BASE_IDX                                                                     5
+#define regPCIE_LC_STATUS1                                                                              0x420028
+#define regPCIE_LC_STATUS1_BASE_IDX                                                                     5
+#define regPCIE_LC_STATUS2                                                                              0x420029
+#define regPCIE_LC_STATUS2_BASE_IDX                                                                     5
+#define regPCIE_TX_CNTL3                                                                                0x42002a
+#define regPCIE_TX_CNTL3_BASE_IDX                                                                       5
+#define regPCIE_TX_STATUS                                                                               0x42002b
+#define regPCIE_TX_STATUS_BASE_IDX                                                                      5
+#define regPCIE_WPR_CNTL                                                                                0x420030
+#define regPCIE_WPR_CNTL_BASE_IDX                                                                       5
+#define regPCIE_RX_LAST_TLP0                                                                            0x420031
+#define regPCIE_RX_LAST_TLP0_BASE_IDX                                                                   5
+#define regPCIE_RX_LAST_TLP1                                                                            0x420032
+#define regPCIE_RX_LAST_TLP1_BASE_IDX                                                                   5
+#define regPCIE_RX_LAST_TLP2                                                                            0x420033
+#define regPCIE_RX_LAST_TLP2_BASE_IDX                                                                   5
+#define regPCIE_RX_LAST_TLP3                                                                            0x420034
+#define regPCIE_RX_LAST_TLP3_BASE_IDX                                                                   5
+#define regPCIE_TX_LAST_TLP0                                                                            0x420035
+#define regPCIE_TX_LAST_TLP0_BASE_IDX                                                                   5
+#define regPCIE_TX_LAST_TLP1                                                                            0x420036
+#define regPCIE_TX_LAST_TLP1_BASE_IDX                                                                   5
+#define regPCIE_TX_LAST_TLP2                                                                            0x420037
+#define regPCIE_TX_LAST_TLP2_BASE_IDX                                                                   5
+#define regPCIE_TX_LAST_TLP3                                                                            0x420038
+#define regPCIE_TX_LAST_TLP3_BASE_IDX                                                                   5
+#define regPCIE_I2C_REG_ADDR_EXPAND                                                                     0x42003a
+#define regPCIE_I2C_REG_ADDR_EXPAND_BASE_IDX                                                            5
+#define regPCIE_I2C_REG_DATA                                                                            0x42003b
+#define regPCIE_I2C_REG_DATA_BASE_IDX                                                                   5
+#define regPCIE_CFG_CNTL                                                                                0x42003c
+#define regPCIE_CFG_CNTL_BASE_IDX                                                                       5
+#define regPCIE_LC_PM_CNTL                                                                              0x42003d
+#define regPCIE_LC_PM_CNTL_BASE_IDX                                                                     5
+#define regPCIE_LC_PORT_ORDER_CNTL                                                                      0x42003e
+#define regPCIE_LC_PORT_ORDER_CNTL_BASE_IDX                                                             5
+#define regPCIE_P_CNTL                                                                                  0x420040
+#define regPCIE_P_CNTL_BASE_IDX                                                                         5
+#define regPCIE_P_BUF_STATUS                                                                            0x420041
+#define regPCIE_P_BUF_STATUS_BASE_IDX                                                                   5
+#define regPCIE_P_DECODER_STATUS                                                                        0x420042
+#define regPCIE_P_DECODER_STATUS_BASE_IDX                                                               5
+#define regPCIE_P_MISC_STATUS                                                                           0x420043
+#define regPCIE_P_MISC_STATUS_BASE_IDX                                                                  5
+#define regPCIE_P_RCV_L0S_FTS_DET                                                                       0x420050
+#define regPCIE_P_RCV_L0S_FTS_DET_BASE_IDX                                                              5
+#define regPCIE_TX_CCIX_CNTL0                                                                           0x420054
+#define regPCIE_TX_CCIX_CNTL0_BASE_IDX                                                                  5
+#define regPCIE_TX_CCIX_CNTL1                                                                           0x420055
+#define regPCIE_TX_CCIX_CNTL1_BASE_IDX                                                                  5
+#define regPCIE_TX_CCIX_PORT_MAP                                                                        0x420056
+#define regPCIE_TX_CCIX_PORT_MAP_BASE_IDX                                                               5
+#define regPCIE_TX_CCIX_ERR_CTL                                                                         0x420057
+#define regPCIE_TX_CCIX_ERR_CTL_BASE_IDX                                                                5
+#define regPCIE_RX_CCIX_CTL0                                                                            0x420058
+#define regPCIE_RX_CCIX_CTL0_BASE_IDX                                                                   5
+#define regPCIE_RX_AD                                                                                   0x420062
+#define regPCIE_RX_AD_BASE_IDX                                                                          5
+#define regPCIE_SDP_CTRL                                                                                0x420063
+#define regPCIE_SDP_CTRL_BASE_IDX                                                                       5
+#define regNBIO_CLKREQb_MAP_CNTL                                                                        0x420064
+#define regNBIO_CLKREQb_MAP_CNTL_BASE_IDX                                                               5
+#define regPCIE_SDP_SWUS_SLV_ATTR_CTRL                                                                  0x420065
+#define regPCIE_SDP_SWUS_SLV_ATTR_CTRL_BASE_IDX                                                         5
+#define regPCIE_SDP_RC_SLV_ATTR_CTRL                                                                    0x420066
+#define regPCIE_SDP_RC_SLV_ATTR_CTRL_BASE_IDX                                                           5
+#define regPCIE_PERF_COUNT_CNTL                                                                         0x420080
+#define regPCIE_PERF_COUNT_CNTL_BASE_IDX                                                                5
+#define regPCIE_PERF_CNTL_TXCLK1                                                                        0x420081
+#define regPCIE_PERF_CNTL_TXCLK1_BASE_IDX                                                               5
+#define regPCIE_PERF_COUNT0_TXCLK1                                                                      0x420082
+#define regPCIE_PERF_COUNT0_TXCLK1_BASE_IDX                                                             5
+#define regPCIE_PERF_COUNT1_TXCLK1                                                                      0x420083
+#define regPCIE_PERF_COUNT1_TXCLK1_BASE_IDX                                                             5
+#define regPCIE_PERF_CNTL_TXCLK2                                                                        0x420084
+#define regPCIE_PERF_CNTL_TXCLK2_BASE_IDX                                                               5
+#define regPCIE_PERF_COUNT0_TXCLK2                                                                      0x420085
+#define regPCIE_PERF_COUNT0_TXCLK2_BASE_IDX                                                             5
+#define regPCIE_PERF_COUNT1_TXCLK2                                                                      0x420086
+#define regPCIE_PERF_COUNT1_TXCLK2_BASE_IDX                                                             5
+#define regPCIE_PERF_CNTL_TXCLK3                                                                        0x420087
+#define regPCIE_PERF_CNTL_TXCLK3_BASE_IDX                                                               5
+#define regPCIE_PERF_COUNT0_TXCLK3                                                                      0x420088
+#define regPCIE_PERF_COUNT0_TXCLK3_BASE_IDX                                                             5
+#define regPCIE_PERF_COUNT1_TXCLK3                                                                      0x420089
+#define regPCIE_PERF_COUNT1_TXCLK3_BASE_IDX                                                             5
+#define regPCIE_PERF_CNTL_TXCLK4                                                                        0x42008a
+#define regPCIE_PERF_CNTL_TXCLK4_BASE_IDX                                                               5
+#define regPCIE_PERF_COUNT0_TXCLK4                                                                      0x42008b
+#define regPCIE_PERF_COUNT0_TXCLK4_BASE_IDX                                                             5
+#define regPCIE_PERF_COUNT1_TXCLK4                                                                      0x42008c
+#define regPCIE_PERF_COUNT1_TXCLK4_BASE_IDX                                                             5
+#define regPCIE_PERF_CNTL_SCLK1                                                                         0x42008d
+#define regPCIE_PERF_CNTL_SCLK1_BASE_IDX                                                                5
+#define regPCIE_PERF_COUNT0_SCLK1                                                                       0x42008e
+#define regPCIE_PERF_COUNT0_SCLK1_BASE_IDX                                                              5
+#define regPCIE_PERF_COUNT1_SCLK1                                                                       0x42008f
+#define regPCIE_PERF_COUNT1_SCLK1_BASE_IDX                                                              5
+#define regPCIE_PERF_CNTL_SCLK2                                                                         0x420090
+#define regPCIE_PERF_CNTL_SCLK2_BASE_IDX                                                                5
+#define regPCIE_PERF_COUNT0_SCLK2                                                                       0x420091
+#define regPCIE_PERF_COUNT0_SCLK2_BASE_IDX                                                              5
+#define regPCIE_PERF_COUNT1_SCLK2                                                                       0x420092
+#define regPCIE_PERF_COUNT1_SCLK2_BASE_IDX                                                              5
+#define regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL                                                             0x420093
+#define regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL_BASE_IDX                                                    5
+#define regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL                                                             0x420094
+#define regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL_BASE_IDX                                                    5
+#define regPCIE_STRAP_F0                                                                                0x4200b0
+#define regPCIE_STRAP_F0_BASE_IDX                                                                       5
+#define regPCIE_STRAP_NTB                                                                               0x4200b1
+#define regPCIE_STRAP_NTB_BASE_IDX                                                                      5
+#define regPCIE_STRAP_MISC                                                                              0x4200c0
+#define regPCIE_STRAP_MISC_BASE_IDX                                                                     5
+#define regPCIE_STRAP_MISC2                                                                             0x4200c1
+#define regPCIE_STRAP_MISC2_BASE_IDX                                                                    5
+#define regPCIE_STRAP_PI                                                                                0x4200c2
+#define regPCIE_STRAP_PI_BASE_IDX                                                                       5
+#define regPCIE_STRAP_I2C_BD                                                                            0x4200c4
+#define regPCIE_STRAP_I2C_BD_BASE_IDX                                                                   5
+#define regPCIE_PRBS_CLR                                                                                0x4200c8
+#define regPCIE_PRBS_CLR_BASE_IDX                                                                       5
+#define regPCIE_PRBS_STATUS1                                                                            0x4200c9
+#define regPCIE_PRBS_STATUS1_BASE_IDX                                                                   5
+#define regPCIE_PRBS_STATUS2                                                                            0x4200ca
+#define regPCIE_PRBS_STATUS2_BASE_IDX                                                                   5
+#define regPCIE_PRBS_FREERUN                                                                            0x4200cb
+#define regPCIE_PRBS_FREERUN_BASE_IDX                                                                   5
+#define regPCIE_PRBS_MISC                                                                               0x4200cc
+#define regPCIE_PRBS_MISC_BASE_IDX                                                                      5
+#define regPCIE_PRBS_USER_PATTERN                                                                       0x4200cd
+#define regPCIE_PRBS_USER_PATTERN_BASE_IDX                                                              5
+#define regPCIE_PRBS_LO_BITCNT                                                                          0x4200ce
+#define regPCIE_PRBS_LO_BITCNT_BASE_IDX                                                                 5
+#define regPCIE_PRBS_HI_BITCNT                                                                          0x4200cf
+#define regPCIE_PRBS_HI_BITCNT_BASE_IDX                                                                 5
+#define regPCIE_PRBS_ERRCNT_0                                                                           0x4200d0
+#define regPCIE_PRBS_ERRCNT_0_BASE_IDX                                                                  5
+#define regPCIE_PRBS_ERRCNT_1                                                                           0x4200d1
+#define regPCIE_PRBS_ERRCNT_1_BASE_IDX                                                                  5
+#define regPCIE_PRBS_ERRCNT_2                                                                           0x4200d2
+#define regPCIE_PRBS_ERRCNT_2_BASE_IDX                                                                  5
+#define regPCIE_PRBS_ERRCNT_3                                                                           0x4200d3
+#define regPCIE_PRBS_ERRCNT_3_BASE_IDX                                                                  5
+#define regPCIE_PRBS_ERRCNT_4                                                                           0x4200d4
+#define regPCIE_PRBS_ERRCNT_4_BASE_IDX                                                                  5
+#define regPCIE_PRBS_ERRCNT_5                                                                           0x4200d5
+#define regPCIE_PRBS_ERRCNT_5_BASE_IDX                                                                  5
+#define regPCIE_PRBS_ERRCNT_6                                                                           0x4200d6
+#define regPCIE_PRBS_ERRCNT_6_BASE_IDX                                                                  5
+#define regPCIE_PRBS_ERRCNT_7                                                                           0x4200d7
+#define regPCIE_PRBS_ERRCNT_7_BASE_IDX                                                                  5
+#define regPCIE_PRBS_ERRCNT_8                                                                           0x4200d8
+#define regPCIE_PRBS_ERRCNT_8_BASE_IDX                                                                  5
+#define regPCIE_PRBS_ERRCNT_9                                                                           0x4200d9
+#define regPCIE_PRBS_ERRCNT_9_BASE_IDX                                                                  5
+#define regPCIE_PRBS_ERRCNT_10                                                                          0x4200da
+#define regPCIE_PRBS_ERRCNT_10_BASE_IDX                                                                 5
+#define regPCIE_PRBS_ERRCNT_11                                                                          0x4200db
+#define regPCIE_PRBS_ERRCNT_11_BASE_IDX                                                                 5
+#define regPCIE_PRBS_ERRCNT_12                                                                          0x4200dc
+#define regPCIE_PRBS_ERRCNT_12_BASE_IDX                                                                 5
+#define regPCIE_PRBS_ERRCNT_13                                                                          0x4200dd
+#define regPCIE_PRBS_ERRCNT_13_BASE_IDX                                                                 5
+#define regPCIE_PRBS_ERRCNT_14                                                                          0x4200de
+#define regPCIE_PRBS_ERRCNT_14_BASE_IDX                                                                 5
+#define regPCIE_PRBS_ERRCNT_15                                                                          0x4200df
+#define regPCIE_PRBS_ERRCNT_15_BASE_IDX                                                                 5
+#define regSWRST_COMMAND_STATUS                                                                         0x420100
+#define regSWRST_COMMAND_STATUS_BASE_IDX                                                                5
+#define regSWRST_GENERAL_CONTROL                                                                        0x420101
+#define regSWRST_GENERAL_CONTROL_BASE_IDX                                                               5
+#define regSWRST_COMMAND_0                                                                              0x420102
+#define regSWRST_COMMAND_0_BASE_IDX                                                                     5
+#define regSWRST_COMMAND_1                                                                              0x420103
+#define regSWRST_COMMAND_1_BASE_IDX                                                                     5
+#define regSWRST_CONTROL_0                                                                              0x420104
+#define regSWRST_CONTROL_0_BASE_IDX                                                                     5
+#define regSWRST_CONTROL_1                                                                              0x420105
+#define regSWRST_CONTROL_1_BASE_IDX                                                                     5
+#define regSWRST_CONTROL_2                                                                              0x420106
+#define regSWRST_CONTROL_2_BASE_IDX                                                                     5
+#define regSWRST_CONTROL_3                                                                              0x420107
+#define regSWRST_CONTROL_3_BASE_IDX                                                                     5
+#define regSWRST_CONTROL_4                                                                              0x420108
+#define regSWRST_CONTROL_4_BASE_IDX                                                                     5
+#define regSWRST_CONTROL_5                                                                              0x420109
+#define regSWRST_CONTROL_5_BASE_IDX                                                                     5
+#define regSWRST_CONTROL_6                                                                              0x42010a
+#define regSWRST_CONTROL_6_BASE_IDX                                                                     5
+#define regSWRST_EP_COMMAND_0                                                                           0x42010b
+#define regSWRST_EP_COMMAND_0_BASE_IDX                                                                  5
+#define regSWRST_EP_CONTROL_0                                                                           0x42010c
+#define regSWRST_EP_CONTROL_0_BASE_IDX                                                                  5
+#define regCPM_CONTROL                                                                                  0x420118
+#define regCPM_CONTROL_BASE_IDX                                                                         5
+#define regCPM_SPLIT_CONTROL                                                                            0x420119
+#define regCPM_SPLIT_CONTROL_BASE_IDX                                                                   5
+#define regCPM_CONTROL_EXT                                                                              0x42011a
+#define regCPM_CONTROL_EXT_BASE_IDX                                                                     5
+#define regSMN_APERTURE_ID_A                                                                            0x42011d
+#define regSMN_APERTURE_ID_A_BASE_IDX                                                                   5
+#define regSMN_APERTURE_ID_B                                                                            0x42011e
+#define regSMN_APERTURE_ID_B_BASE_IDX                                                                   5
+#define regLNCNT_CONTROL                                                                                0x420125
+#define regLNCNT_CONTROL_BASE_IDX                                                                       5
+#define regLNCNT_QUAN_THRD                                                                              0x420127
+#define regLNCNT_QUAN_THRD_BASE_IDX                                                                     5
+#define regLNCNT_WEIGHT                                                                                 0x420128
+#define regLNCNT_WEIGHT_BASE_IDX                                                                        5
+#define regPCIE_PGMST_CNTL                                                                              0x420130
+#define regPCIE_PGMST_CNTL_BASE_IDX                                                                     5
+#define regPCIE_PGSLV_CNTL                                                                              0x420131
+#define regPCIE_PGSLV_CNTL_BASE_IDX                                                                     5
+#define regLC_CPM_CONTROL_0                                                                             0x420133
+#define regLC_CPM_CONTROL_0_BASE_IDX                                                                    5
+#define regLC_CPM_CONTROL_1                                                                             0x420134
+#define regLC_CPM_CONTROL_1_BASE_IDX                                                                    5
+#define regPCIE_RXMARGIN_CONTROL_CAPABILITIES                                                           0x420135
+#define regPCIE_RXMARGIN_CONTROL_CAPABILITIES_BASE_IDX                                                  5
+#define regPCIE_RXMARGIN_1_SETTINGS                                                                     0x420136
+#define regPCIE_RXMARGIN_1_SETTINGS_BASE_IDX                                                            5
+#define regPCIE_RXMARGIN_2_SETTINGS                                                                     0x420137
+#define regPCIE_RXMARGIN_2_SETTINGS_BASE_IDX                                                            5
+#define regPCIE_PRESENCE_DETECT_SELECT                                                                  0x420138
+#define regPCIE_PRESENCE_DETECT_SELECT_BASE_IDX                                                         5
+
+
+// addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec
+// base address: 0x13b07000
+#define regFASTREG_APERTURE                                                                             0xe81c00
+#define regFASTREG_APERTURE_BASE_IDX                                                                    5
+
+
+// addressBlock: nbio_iohub_nb_misc_misc_cfgdec
+// base address: 0x13b10000
+#define regNBIO_LCLK_DS_MASK                                                                            0xe84009
+#define regNBIO_LCLK_DS_MASK_BASE_IDX                                                                   5
+#define regSB_LOCATION                                                                                  0xe8401f
+#define regSB_LOCATION_BASE_IDX                                                                         5
+#define regSW_US_LOCATION                                                                               0xe84020
+#define regSW_US_LOCATION_BASE_IDX                                                                      5
+#define regSW_NMI_CNTL                                                                                  0xe84042
+#define regSW_NMI_CNTL_BASE_IDX                                                                         5
+#define regSW_SMI_CNTL                                                                                  0xe84043
+#define regSW_SMI_CNTL_BASE_IDX                                                                         5
+#define regSW_SCI_CNTL                                                                                  0xe84044
+#define regSW_SCI_CNTL_BASE_IDX                                                                         5
+#define regAPML_SW_STATUS                                                                               0xe84045
+#define regAPML_SW_STATUS_BASE_IDX                                                                      5
+#define regSW_GIC_SPI_CNTL                                                                              0xe84047
+#define regSW_GIC_SPI_CNTL_BASE_IDX                                                                     5
+#define regSW_SYNCFLOOD_CNTL                                                                            0xe84049
+#define regSW_SYNCFLOOD_CNTL_BASE_IDX                                                                   5
+#define regCAM_CONTROL                                                                                  0xe84052
+#define regCAM_CONTROL_BASE_IDX                                                                         5
+#define regCAM_TARGET_INDEX_ADDR_BOTTOM                                                                 0xe84053
+#define regCAM_TARGET_INDEX_ADDR_BOTTOM_BASE_IDX                                                        5
+#define regCAM_TARGET_INDEX_ADDR_TOP                                                                    0xe84054
+#define regCAM_TARGET_INDEX_ADDR_TOP_BASE_IDX                                                           5
+#define regCAM_TARGET_INDEX_DATA                                                                        0xe84055
+#define regCAM_TARGET_INDEX_DATA_BASE_IDX                                                               5
+#define regCAM_TARGET_INDEX_DATA_MASK                                                                   0xe84056
+#define regCAM_TARGET_INDEX_DATA_MASK_BASE_IDX                                                          5
+#define regCAM_TARGET_DATA_ADDR_BOTTOM                                                                  0xe84057
+#define regCAM_TARGET_DATA_ADDR_BOTTOM_BASE_IDX                                                         5
+#define regCAM_TARGET_DATA_ADDR_TOP                                                                     0xe84059
+#define regCAM_TARGET_DATA_ADDR_TOP_BASE_IDX                                                            5
+#define regCAM_TARGET_DATA                                                                              0xe8405a
+#define regCAM_TARGET_DATA_BASE_IDX                                                                     5
+#define regCAM_TARGET_DATA_MASK                                                                         0xe8405b
+#define regCAM_TARGET_DATA_MASK_BASE_IDX                                                                5
+#define regP_DMA_DROPPED_LOG_LOWER                                                                      0xe84060
+#define regP_DMA_DROPPED_LOG_LOWER_BASE_IDX                                                             5
+#define regP_DMA_DROPPED_LOG_UPPER                                                                      0xe84061
+#define regP_DMA_DROPPED_LOG_UPPER_BASE_IDX                                                             5
+#define regNP_DMA_DROPPED_LOG_LOWER                                                                     0xe84062
+#define regNP_DMA_DROPPED_LOG_LOWER_BASE_IDX                                                            5
+#define regNP_DMA_DROPPED_LOG_UPPER                                                                     0xe84063
+#define regNP_DMA_DROPPED_LOG_UPPER_BASE_IDX                                                            5
+#define regPCIE_VDM_NODE0_CTRL4                                                                         0xe84064
+#define regPCIE_VDM_NODE0_CTRL4_BASE_IDX                                                                5
+#define regPCIE_VDM_CNTL2                                                                               0xe8408c
+#define regPCIE_VDM_CNTL2_BASE_IDX                                                                      5
+#define regPCIE_VDM_CNTL3                                                                               0xe8408d
+#define regPCIE_VDM_CNTL3_BASE_IDX                                                                      5
+#define regSTALL_CONTROL_XBARPORT0_0                                                                    0xe84090
+#define regSTALL_CONTROL_XBARPORT0_0_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT0_1                                                                    0xe84091
+#define regSTALL_CONTROL_XBARPORT0_1_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT1_0                                                                    0xe84093
+#define regSTALL_CONTROL_XBARPORT1_0_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT1_1                                                                    0xe84094
+#define regSTALL_CONTROL_XBARPORT1_1_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT2_0                                                                    0xe84096
+#define regSTALL_CONTROL_XBARPORT2_0_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT2_1                                                                    0xe84097
+#define regSTALL_CONTROL_XBARPORT2_1_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT3_0                                                                    0xe84099
+#define regSTALL_CONTROL_XBARPORT3_0_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT3_1                                                                    0xe8409a
+#define regSTALL_CONTROL_XBARPORT3_1_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT4_0                                                                    0xe8409c
+#define regSTALL_CONTROL_XBARPORT4_0_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT4_1                                                                    0xe8409d
+#define regSTALL_CONTROL_XBARPORT4_1_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT5_0                                                                    0xe8409f
+#define regSTALL_CONTROL_XBARPORT5_0_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT5_1                                                                    0xe840a0
+#define regSTALL_CONTROL_XBARPORT5_1_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT6_0                                                                    0xe840a2
+#define regSTALL_CONTROL_XBARPORT6_0_BASE_IDX                                                           5
+#define regSTALL_CONTROL_XBARPORT6_1                                                                    0xe840a3
+#define regSTALL_CONTROL_XBARPORT6_1_BASE_IDX                                                           5
+#define regFASTREG_BASE_ADDR_LO                                                                         0xe840c0
+#define regFASTREG_BASE_ADDR_LO_BASE_IDX                                                                5
+#define regFASTREG_BASE_ADDR_HI                                                                         0xe840c1
+#define regFASTREG_BASE_ADDR_HI_BASE_IDX                                                                5
+#define regFASTREGCNTL_BASE_ADDR_LO                                                                     0xe840c2
+#define regFASTREGCNTL_BASE_ADDR_LO_BASE_IDX                                                            5
+#define regFASTREGCNTL_BASE_ADDR_HI                                                                     0xe840c3
+#define regFASTREGCNTL_BASE_ADDR_HI_BASE_IDX                                                            5
+#define regSCRATCH_4                                                                                    0xe840fc
+#define regSCRATCH_4_BASE_IDX                                                                           5
+#define regSCRATCH_5                                                                                    0xe840fd
+#define regSCRATCH_5_BASE_IDX                                                                           5
+#define regTRAP_STATUS                                                                                  0xe84100
+#define regTRAP_STATUS_BASE_IDX                                                                         5
+#define regTRAP_REQUEST0                                                                                0xe84101
+#define regTRAP_REQUEST0_BASE_IDX                                                                       5
+#define regTRAP_REQUEST1                                                                                0xe84102
+#define regTRAP_REQUEST1_BASE_IDX                                                                       5
+#define regTRAP_REQUEST2                                                                                0xe84103
+#define regTRAP_REQUEST2_BASE_IDX                                                                       5
+#define regTRAP_REQUEST3                                                                                0xe84104
+#define regTRAP_REQUEST3_BASE_IDX                                                                       5
+#define regTRAP_REQUEST4                                                                                0xe84105
+#define regTRAP_REQUEST4_BASE_IDX                                                                       5
+#define regTRAP_REQUEST5                                                                                0xe84106
+#define regTRAP_REQUEST5_BASE_IDX                                                                       5
+#define regTRAP_REQUEST_DATASTRB0                                                                       0xe84108
+#define regTRAP_REQUEST_DATASTRB0_BASE_IDX                                                              5
+#define regTRAP_REQUEST_DATASTRB1                                                                       0xe84109
+#define regTRAP_REQUEST_DATASTRB1_BASE_IDX                                                              5
+#define regTRAP_REQUEST_DATA0                                                                           0xe84110
+#define regTRAP_REQUEST_DATA0_BASE_IDX                                                                  5
+#define regTRAP_REQUEST_DATA1                                                                           0xe84111
+#define regTRAP_REQUEST_DATA1_BASE_IDX                                                                  5
+#define regTRAP_REQUEST_DATA2                                                                           0xe84112
+#define regTRAP_REQUEST_DATA2_BASE_IDX                                                                  5
+#define regTRAP_REQUEST_DATA3                                                                           0xe84113
+#define regTRAP_REQUEST_DATA3_BASE_IDX                                                                  5
+#define regTRAP_REQUEST_DATA4                                                                           0xe84114
+#define regTRAP_REQUEST_DATA4_BASE_IDX                                                                  5
+#define regTRAP_REQUEST_DATA5                                                                           0xe84115
+#define regTRAP_REQUEST_DATA5_BASE_IDX                                                                  5
+#define regTRAP_REQUEST_DATA6                                                                           0xe84116
+#define regTRAP_REQUEST_DATA6_BASE_IDX                                                                  5
+#define regTRAP_REQUEST_DATA7                                                                           0xe84117
+#define regTRAP_REQUEST_DATA7_BASE_IDX                                                                  5
+#define regTRAP_REQUEST_DATA8                                                                           0xe84118
+#define regTRAP_REQUEST_DATA8_BASE_IDX                                                                  5
+#define regTRAP_REQUEST_DATA9                                                                           0xe84119
+#define regTRAP_REQUEST_DATA9_BASE_IDX                                                                  5
+#define regTRAP_REQUEST_DATA10                                                                          0xe8411a
+#define regTRAP_REQUEST_DATA10_BASE_IDX                                                                 5
+#define regTRAP_REQUEST_DATA11                                                                          0xe8411b
+#define regTRAP_REQUEST_DATA11_BASE_IDX                                                                 5
+#define regTRAP_REQUEST_DATA12                                                                          0xe8411c
+#define regTRAP_REQUEST_DATA12_BASE_IDX                                                                 5
+#define regTRAP_REQUEST_DATA13                                                                          0xe8411d
+#define regTRAP_REQUEST_DATA13_BASE_IDX                                                                 5
+#define regTRAP_REQUEST_DATA14                                                                          0xe8411e
+#define regTRAP_REQUEST_DATA14_BASE_IDX                                                                 5
+#define regTRAP_REQUEST_DATA15                                                                          0xe8411f
+#define regTRAP_REQUEST_DATA15_BASE_IDX                                                                 5
+#define regTRAP_RESPONSE_CONTROL                                                                        0xe84130
+#define regTRAP_RESPONSE_CONTROL_BASE_IDX                                                               5
+#define regTRAP_RESPONSE0                                                                               0xe84131
+#define regTRAP_RESPONSE0_BASE_IDX                                                                      5
+#define regTRAP_RESPONSE_DATA0                                                                          0xe84140
+#define regTRAP_RESPONSE_DATA0_BASE_IDX                                                                 5
+#define regTRAP_RESPONSE_DATA1                                                                          0xe84141
+#define regTRAP_RESPONSE_DATA1_BASE_IDX                                                                 5
+#define regTRAP_RESPONSE_DATA2                                                                          0xe84142
+#define regTRAP_RESPONSE_DATA2_BASE_IDX                                                                 5
+#define regTRAP_RESPONSE_DATA3                                                                          0xe84143
+#define regTRAP_RESPONSE_DATA3_BASE_IDX                                                                 5
+#define regTRAP_RESPONSE_DATA4                                                                          0xe84144
+#define regTRAP_RESPONSE_DATA4_BASE_IDX                                                                 5
+#define regTRAP_RESPONSE_DATA5                                                                          0xe84145
+#define regTRAP_RESPONSE_DATA5_BASE_IDX                                                                 5
+#define regTRAP_RESPONSE_DATA6                                                                          0xe84146
+#define regTRAP_RESPONSE_DATA6_BASE_IDX                                                                 5
+#define regTRAP_RESPONSE_DATA7                                                                          0xe84147
+#define regTRAP_RESPONSE_DATA7_BASE_IDX                                                                 5
+#define regTRAP_RESPONSE_DATA8                                                                          0xe84148
+#define regTRAP_RESPONSE_DATA8_BASE_IDX                                                                 5
+#define regTRAP_RESPONSE_DATA9                                                                          0xe84149
+#define regTRAP_RESPONSE_DATA9_BASE_IDX                                                                 5
+#define regTRAP_RESPONSE_DATA10                                                                         0xe8414a
+#define regTRAP_RESPONSE_DATA10_BASE_IDX                                                                5
+#define regTRAP_RESPONSE_DATA11                                                                         0xe8414b
+#define regTRAP_RESPONSE_DATA11_BASE_IDX                                                                5
+#define regTRAP_RESPONSE_DATA12                                                                         0xe8414c
+#define regTRAP_RESPONSE_DATA12_BASE_IDX                                                                5
+#define regTRAP_RESPONSE_DATA13                                                                         0xe8414d
+#define regTRAP_RESPONSE_DATA13_BASE_IDX                                                                5
+#define regTRAP_RESPONSE_DATA14                                                                         0xe8414e
+#define regTRAP_RESPONSE_DATA14_BASE_IDX                                                                5
+#define regTRAP_RESPONSE_DATA15                                                                         0xe8414f
+#define regTRAP_RESPONSE_DATA15_BASE_IDX                                                                5
+#define regTRAP0_CONTROL0                                                                               0xe84200
+#define regTRAP0_CONTROL0_BASE_IDX                                                                      5
+#define regTRAP0_ADDRESS_LO                                                                             0xe84202
+#define regTRAP0_ADDRESS_LO_BASE_IDX                                                                    5
+#define regTRAP0_ADDRESS_HI                                                                             0xe84203
+#define regTRAP0_ADDRESS_HI_BASE_IDX                                                                    5
+#define regTRAP0_COMMAND                                                                                0xe84204
+#define regTRAP0_COMMAND_BASE_IDX                                                                       5
+#define regTRAP0_ADDRESS_LO_MASK                                                                        0xe84206
+#define regTRAP0_ADDRESS_LO_MASK_BASE_IDX                                                               5
+#define regTRAP0_ADDRESS_HI_MASK                                                                        0xe84207
+#define regTRAP0_ADDRESS_HI_MASK_BASE_IDX                                                               5
+#define regTRAP0_COMMAND_MASK                                                                           0xe84208
+#define regTRAP0_COMMAND_MASK_BASE_IDX                                                                  5
+#define regTRAP1_CONTROL0                                                                               0xe84210
+#define regTRAP1_CONTROL0_BASE_IDX                                                                      5
+#define regTRAP1_ADDRESS_LO                                                                             0xe84212
+#define regTRAP1_ADDRESS_LO_BASE_IDX                                                                    5
+#define regTRAP1_ADDRESS_HI                                                                             0xe84213
+#define regTRAP1_ADDRESS_HI_BASE_IDX                                                                    5
+#define regTRAP1_COMMAND                                                                                0xe84214
+#define regTRAP1_COMMAND_BASE_IDX                                                                       5
+#define regTRAP1_ADDRESS_LO_MASK                                                                        0xe84216
+#define regTRAP1_ADDRESS_LO_MASK_BASE_IDX                                                               5
+#define regTRAP1_ADDRESS_HI_MASK                                                                        0xe84217
+#define regTRAP1_ADDRESS_HI_MASK_BASE_IDX                                                               5
+#define regTRAP1_COMMAND_MASK                                                                           0xe84218
+#define regTRAP1_COMMAND_MASK_BASE_IDX                                                                  5
+#define regTRAP2_CONTROL0                                                                               0xe84220
+#define regTRAP2_CONTROL0_BASE_IDX                                                                      5
+#define regTRAP2_ADDRESS_LO                                                                             0xe84222
+#define regTRAP2_ADDRESS_LO_BASE_IDX                                                                    5
+#define regTRAP2_ADDRESS_HI                                                                             0xe84223
+#define regTRAP2_ADDRESS_HI_BASE_IDX                                                                    5
+#define regTRAP2_COMMAND                                                                                0xe84224
+#define regTRAP2_COMMAND_BASE_IDX                                                                       5
+#define regTRAP2_ADDRESS_LO_MASK                                                                        0xe84226
+#define regTRAP2_ADDRESS_LO_MASK_BASE_IDX                                                               5
+#define regTRAP2_ADDRESS_HI_MASK                                                                        0xe84227
+#define regTRAP2_ADDRESS_HI_MASK_BASE_IDX                                                               5
+#define regTRAP2_COMMAND_MASK                                                                           0xe84228
+#define regTRAP2_COMMAND_MASK_BASE_IDX                                                                  5
+#define regTRAP3_CONTROL0                                                                               0xe84230
+#define regTRAP3_CONTROL0_BASE_IDX                                                                      5
+#define regTRAP3_ADDRESS_LO                                                                             0xe84232
+#define regTRAP3_ADDRESS_LO_BASE_IDX                                                                    5
+#define regTRAP3_ADDRESS_HI                                                                             0xe84233
+#define regTRAP3_ADDRESS_HI_BASE_IDX                                                                    5
+#define regTRAP3_COMMAND                                                                                0xe84234
+#define regTRAP3_COMMAND_BASE_IDX                                                                       5
+#define regTRAP3_ADDRESS_LO_MASK                                                                        0xe84236
+#define regTRAP3_ADDRESS_LO_MASK_BASE_IDX                                                               5
+#define regTRAP3_ADDRESS_HI_MASK                                                                        0xe84237
+#define regTRAP3_ADDRESS_HI_MASK_BASE_IDX                                                               5
+#define regTRAP3_COMMAND_MASK                                                                           0xe84238
+#define regTRAP3_COMMAND_MASK_BASE_IDX                                                                  5
+#define regTRAP4_CONTROL0                                                                               0xe84240
+#define regTRAP4_CONTROL0_BASE_IDX                                                                      5
+#define regTRAP4_ADDRESS_LO                                                                             0xe84242
+#define regTRAP4_ADDRESS_LO_BASE_IDX                                                                    5
+#define regTRAP4_ADDRESS_HI                                                                             0xe84243
+#define regTRAP4_ADDRESS_HI_BASE_IDX                                                                    5
+#define regTRAP4_COMMAND                                                                                0xe84244
+#define regTRAP4_COMMAND_BASE_IDX                                                                       5
+#define regTRAP4_ADDRESS_LO_MASK                                                                        0xe84246
+#define regTRAP4_ADDRESS_LO_MASK_BASE_IDX                                                               5
+#define regTRAP4_ADDRESS_HI_MASK                                                                        0xe84247
+#define regTRAP4_ADDRESS_HI_MASK_BASE_IDX                                                               5
+#define regTRAP4_COMMAND_MASK                                                                           0xe84248
+#define regTRAP4_COMMAND_MASK_BASE_IDX                                                                  5
+#define regTRAP5_CONTROL0                                                                               0xe84250
+#define regTRAP5_CONTROL0_BASE_IDX                                                                      5
+#define regTRAP5_ADDRESS_LO                                                                             0xe84252
+#define regTRAP5_ADDRESS_LO_BASE_IDX                                                                    5
+#define regTRAP5_ADDRESS_HI                                                                             0xe84253
+#define regTRAP5_ADDRESS_HI_BASE_IDX                                                                    5
+#define regTRAP5_COMMAND                                                                                0xe84254
+#define regTRAP5_COMMAND_BASE_IDX                                                                       5
+#define regTRAP5_ADDRESS_LO_MASK                                                                        0xe84256
+#define regTRAP5_ADDRESS_LO_MASK_BASE_IDX                                                               5
+#define regTRAP5_ADDRESS_HI_MASK                                                                        0xe84257
+#define regTRAP5_ADDRESS_HI_MASK_BASE_IDX                                                               5
+#define regTRAP5_COMMAND_MASK                                                                           0xe84258
+#define regTRAP5_COMMAND_MASK_BASE_IDX                                                                  5
+#define regTRAP6_CONTROL0                                                                               0xe84260
+#define regTRAP6_CONTROL0_BASE_IDX                                                                      5
+#define regTRAP6_ADDRESS_LO                                                                             0xe84262
+#define regTRAP6_ADDRESS_LO_BASE_IDX                                                                    5
+#define regTRAP6_ADDRESS_HI                                                                             0xe84263
+#define regTRAP6_ADDRESS_HI_BASE_IDX                                                                    5
+#define regTRAP6_COMMAND                                                                                0xe84264
+#define regTRAP6_COMMAND_BASE_IDX                                                                       5
+#define regTRAP6_ADDRESS_LO_MASK                                                                        0xe84266
+#define regTRAP6_ADDRESS_LO_MASK_BASE_IDX                                                               5
+#define regTRAP6_ADDRESS_HI_MASK                                                                        0xe84267
+#define regTRAP6_ADDRESS_HI_MASK_BASE_IDX                                                               5
+#define regTRAP6_COMMAND_MASK                                                                           0xe84268
+#define regTRAP6_COMMAND_MASK_BASE_IDX                                                                  5
+#define regTRAP7_CONTROL0                                                                               0xe84270
+#define regTRAP7_CONTROL0_BASE_IDX                                                                      5
+#define regTRAP7_ADDRESS_LO                                                                             0xe84272
+#define regTRAP7_ADDRESS_LO_BASE_IDX                                                                    5
+#define regTRAP7_ADDRESS_HI                                                                             0xe84273
+#define regTRAP7_ADDRESS_HI_BASE_IDX                                                                    5
+#define regTRAP7_COMMAND                                                                                0xe84274
+#define regTRAP7_COMMAND_BASE_IDX                                                                       5
+#define regTRAP7_ADDRESS_LO_MASK                                                                        0xe84276
+#define regTRAP7_ADDRESS_LO_MASK_BASE_IDX                                                               5
+#define regTRAP7_ADDRESS_HI_MASK                                                                        0xe84277
+#define regTRAP7_ADDRESS_HI_MASK_BASE_IDX                                                               5
+#define regTRAP7_COMMAND_MASK                                                                           0xe84278
+#define regTRAP7_COMMAND_MASK_BASE_IDX                                                                  5
+#define regTRAP8_CONTROL0                                                                               0xe84280
+#define regTRAP8_CONTROL0_BASE_IDX                                                                      5
+#define regTRAP8_ADDRESS_LO                                                                             0xe84282
+#define regTRAP8_ADDRESS_LO_BASE_IDX                                                                    5
+#define regTRAP8_ADDRESS_HI                                                                             0xe84283
+#define regTRAP8_ADDRESS_HI_BASE_IDX                                                                    5
+#define regTRAP8_COMMAND                                                                                0xe84284
+#define regTRAP8_COMMAND_BASE_IDX                                                                       5
+#define regTRAP8_ADDRESS_LO_MASK                                                                        0xe84286
+#define regTRAP8_ADDRESS_LO_MASK_BASE_IDX                                                               5
+#define regTRAP8_ADDRESS_HI_MASK                                                                        0xe84287
+#define regTRAP8_ADDRESS_HI_MASK_BASE_IDX                                                               5
+#define regTRAP8_COMMAND_MASK                                                                           0xe84288
+#define regTRAP8_COMMAND_MASK_BASE_IDX                                                                  5
+#define regTRAP9_CONTROL0                                                                               0xe84290
+#define regTRAP9_CONTROL0_BASE_IDX                                                                      5
+#define regTRAP9_ADDRESS_LO                                                                             0xe84292
+#define regTRAP9_ADDRESS_LO_BASE_IDX                                                                    5
+#define regTRAP9_ADDRESS_HI                                                                             0xe84293
+#define regTRAP9_ADDRESS_HI_BASE_IDX                                                                    5
+#define regTRAP9_COMMAND                                                                                0xe84294
+#define regTRAP9_COMMAND_BASE_IDX                                                                       5
+#define regTRAP9_ADDRESS_LO_MASK                                                                        0xe84296
+#define regTRAP9_ADDRESS_LO_MASK_BASE_IDX                                                               5
+#define regTRAP9_ADDRESS_HI_MASK                                                                        0xe84297
+#define regTRAP9_ADDRESS_HI_MASK_BASE_IDX                                                               5
+#define regTRAP9_COMMAND_MASK                                                                           0xe84298
+#define regTRAP9_COMMAND_MASK_BASE_IDX                                                                  5
+#define regTRAP10_CONTROL0                                                                              0xe842a0
+#define regTRAP10_CONTROL0_BASE_IDX                                                                     5
+#define regTRAP10_ADDRESS_LO                                                                            0xe842a2
+#define regTRAP10_ADDRESS_LO_BASE_IDX                                                                   5
+#define regTRAP10_ADDRESS_HI                                                                            0xe842a3
+#define regTRAP10_ADDRESS_HI_BASE_IDX                                                                   5
+#define regTRAP10_COMMAND                                                                               0xe842a4
+#define regTRAP10_COMMAND_BASE_IDX                                                                      5
+#define regTRAP10_ADDRESS_LO_MASK                                                                       0xe842a6
+#define regTRAP10_ADDRESS_LO_MASK_BASE_IDX                                                              5
+#define regTRAP10_ADDRESS_HI_MASK                                                                       0xe842a7
+#define regTRAP10_ADDRESS_HI_MASK_BASE_IDX                                                              5
+#define regTRAP10_COMMAND_MASK                                                                          0xe842a8
+#define regTRAP10_COMMAND_MASK_BASE_IDX                                                                 5
+#define regTRAP11_CONTROL0                                                                              0xe842b0
+#define regTRAP11_CONTROL0_BASE_IDX                                                                     5
+#define regTRAP11_ADDRESS_LO                                                                            0xe842b2
+#define regTRAP11_ADDRESS_LO_BASE_IDX                                                                   5
+#define regTRAP11_ADDRESS_HI                                                                            0xe842b3
+#define regTRAP11_ADDRESS_HI_BASE_IDX                                                                   5
+#define regTRAP11_COMMAND                                                                               0xe842b4
+#define regTRAP11_COMMAND_BASE_IDX                                                                      5
+#define regTRAP11_ADDRESS_LO_MASK                                                                       0xe842b6
+#define regTRAP11_ADDRESS_LO_MASK_BASE_IDX                                                              5
+#define regTRAP11_ADDRESS_HI_MASK                                                                       0xe842b7
+#define regTRAP11_ADDRESS_HI_MASK_BASE_IDX                                                              5
+#define regTRAP11_COMMAND_MASK                                                                          0xe842b8
+#define regTRAP11_COMMAND_MASK_BASE_IDX                                                                 5
+#define regTRAP12_CONTROL0                                                                              0xe842c0
+#define regTRAP12_CONTROL0_BASE_IDX                                                                     5
+#define regTRAP12_ADDRESS_LO                                                                            0xe842c2
+#define regTRAP12_ADDRESS_LO_BASE_IDX                                                                   5
+#define regTRAP12_ADDRESS_HI                                                                            0xe842c3
+#define regTRAP12_ADDRESS_HI_BASE_IDX                                                                   5
+#define regTRAP12_COMMAND                                                                               0xe842c4
+#define regTRAP12_COMMAND_BASE_IDX                                                                      5
+#define regTRAP12_ADDRESS_LO_MASK                                                                       0xe842c6
+#define regTRAP12_ADDRESS_LO_MASK_BASE_IDX                                                              5
+#define regTRAP12_ADDRESS_HI_MASK                                                                       0xe842c7
+#define regTRAP12_ADDRESS_HI_MASK_BASE_IDX                                                              5
+#define regTRAP12_COMMAND_MASK                                                                          0xe842c8
+#define regTRAP12_COMMAND_MASK_BASE_IDX                                                                 5
+#define regTRAP13_CONTROL0                                                                              0xe842d0
+#define regTRAP13_CONTROL0_BASE_IDX                                                                     5
+#define regTRAP13_ADDRESS_LO                                                                            0xe842d2
+#define regTRAP13_ADDRESS_LO_BASE_IDX                                                                   5
+#define regTRAP13_ADDRESS_HI                                                                            0xe842d3
+#define regTRAP13_ADDRESS_HI_BASE_IDX                                                                   5
+#define regTRAP13_COMMAND                                                                               0xe842d4
+#define regTRAP13_COMMAND_BASE_IDX                                                                      5
+#define regTRAP13_ADDRESS_LO_MASK                                                                       0xe842d6
+#define regTRAP13_ADDRESS_LO_MASK_BASE_IDX                                                              5
+#define regTRAP13_ADDRESS_HI_MASK                                                                       0xe842d7
+#define regTRAP13_ADDRESS_HI_MASK_BASE_IDX                                                              5
+#define regTRAP13_COMMAND_MASK                                                                          0xe842d8
+#define regTRAP13_COMMAND_MASK_BASE_IDX                                                                 5
+#define regTRAP14_CONTROL0                                                                              0xe842e0
+#define regTRAP14_CONTROL0_BASE_IDX                                                                     5
+#define regTRAP14_ADDRESS_LO                                                                            0xe842e2
+#define regTRAP14_ADDRESS_LO_BASE_IDX                                                                   5
+#define regTRAP14_ADDRESS_HI                                                                            0xe842e3
+#define regTRAP14_ADDRESS_HI_BASE_IDX                                                                   5
+#define regTRAP14_COMMAND                                                                               0xe842e4
+#define regTRAP14_COMMAND_BASE_IDX                                                                      5
+#define regTRAP14_ADDRESS_LO_MASK                                                                       0xe842e6
+#define regTRAP14_ADDRESS_LO_MASK_BASE_IDX                                                              5
+#define regTRAP14_ADDRESS_HI_MASK                                                                       0xe842e7
+#define regTRAP14_ADDRESS_HI_MASK_BASE_IDX                                                              5
+#define regTRAP14_COMMAND_MASK                                                                          0xe842e8
+#define regTRAP14_COMMAND_MASK_BASE_IDX                                                                 5
+#define regTRAP15_CONTROL0                                                                              0xe842f0
+#define regTRAP15_CONTROL0_BASE_IDX                                                                     5
+#define regTRAP15_ADDRESS_LO                                                                            0xe842f2
+#define regTRAP15_ADDRESS_LO_BASE_IDX                                                                   5
+#define regTRAP15_ADDRESS_HI                                                                            0xe842f3
+#define regTRAP15_ADDRESS_HI_BASE_IDX                                                                   5
+#define regTRAP15_COMMAND                                                                               0xe842f4
+#define regTRAP15_COMMAND_BASE_IDX                                                                      5
+#define regTRAP15_ADDRESS_LO_MASK                                                                       0xe842f6
+#define regTRAP15_ADDRESS_LO_MASK_BASE_IDX                                                              5
+#define regTRAP15_ADDRESS_HI_MASK                                                                       0xe842f7
+#define regTRAP15_ADDRESS_HI_MASK_BASE_IDX                                                              5
+#define regTRAP15_COMMAND_MASK                                                                          0xe842f8
+#define regTRAP15_COMMAND_MASK_BASE_IDX                                                                 5
+#define regSB_COMMAND                                                                                   0xe85000
+#define regSB_COMMAND_BASE_IDX                                                                          5
+#define regSB_SUB_BUS_NUMBER_LATENCY                                                                    0xe85001
+#define regSB_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                           5
+#define regSB_IO_BASE_LIMIT                                                                             0xe85002
+#define regSB_IO_BASE_LIMIT_BASE_IDX                                                                    5
+#define regSB_MEM_BASE_LIMIT                                                                            0xe85003
+#define regSB_MEM_BASE_LIMIT_BASE_IDX                                                                   5
+#define regSB_PREF_BASE_LIMIT                                                                           0xe85004
+#define regSB_PREF_BASE_LIMIT_BASE_IDX                                                                  5
+#define regSB_PREF_BASE_UPPER                                                                           0xe85005
+#define regSB_PREF_BASE_UPPER_BASE_IDX                                                                  5
+#define regSB_PREF_LIMIT_UPPER                                                                          0xe85006
+#define regSB_PREF_LIMIT_UPPER_BASE_IDX                                                                 5
+#define regSB_IO_BASE_LIMIT_HI                                                                          0xe85007
+#define regSB_IO_BASE_LIMIT_HI_BASE_IDX                                                                 5
+#define regSB_IRQ_BRIDGE_CNTL                                                                           0xe85008
+#define regSB_IRQ_BRIDGE_CNTL_BASE_IDX                                                                  5
+#define regSB_EXT_BRIDGE_CNTL                                                                           0xe85009
+#define regSB_EXT_BRIDGE_CNTL_BASE_IDX                                                                  5
+#define regSB_PMI_STATUS_CNTL                                                                           0xe8500a
+#define regSB_PMI_STATUS_CNTL_BASE_IDX                                                                  5
+#define regSB_SLOT_CAP                                                                                  0xe8500b
+#define regSB_SLOT_CAP_BASE_IDX                                                                         5
+#define regSB_ROOT_CNTL                                                                                 0xe8500c
+#define regSB_ROOT_CNTL_BASE_IDX                                                                        5
+#define regSB_DEVICE_CNTL2                                                                              0xe8500d
+#define regSB_DEVICE_CNTL2_BASE_IDX                                                                     5
+#define regMCA_SMN_INT_REQ_ADDR                                                                         0xe85020
+#define regMCA_SMN_INT_REQ_ADDR_BASE_IDX                                                                5
+#define regMCA_SMN_INT_MCM_ADDR                                                                         0xe85021
+#define regMCA_SMN_INT_MCM_ADDR_BASE_IDX                                                                5
+#define regMCA_SMN_INT_APERTUREID                                                                       0xe85022
+#define regMCA_SMN_INT_APERTUREID_BASE_IDX                                                              5
+#define regMCA_SMN_INT_CONTROL                                                                          0xe85023
+#define regMCA_SMN_INT_CONTROL_BASE_IDX                                                                 5
+
+
+// addressBlock: nbio_iohub_nb_security_security_cfgdec
+// base address: 0x13b18000
+
+
+// addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec
+// base address: 0x13b20000
+#define regPARITY_CONTROL_0                                                                             0xe88000
+#define regPARITY_CONTROL_0_BASE_IDX                                                                    5
+#define regPARITY_CONTROL_1                                                                             0xe88001
+#define regPARITY_CONTROL_1_BASE_IDX                                                                    5
+#define regPARITY_SEVERITY_CONTROL_UNCORR_0                                                             0xe88002
+#define regPARITY_SEVERITY_CONTROL_UNCORR_0_BASE_IDX                                                    5
+#define regPARITY_SEVERITY_CONTROL_CORR_0                                                               0xe88004
+#define regPARITY_SEVERITY_CONTROL_CORR_0_BASE_IDX                                                      5
+#define regPARITY_SEVERITY_CONTROL_UCP_0                                                                0xe88006
+#define regPARITY_SEVERITY_CONTROL_UCP_0_BASE_IDX                                                       5
+#define regRAS_GLOBAL_STATUS_LO                                                                         0xe88008
+#define regRAS_GLOBAL_STATUS_LO_BASE_IDX                                                                5
+#define regRAS_GLOBAL_STATUS_HI                                                                         0xe88009
+#define regRAS_GLOBAL_STATUS_HI_BASE_IDX                                                                5
+#define regPARITY_ERROR_STATUS_UNCORR_GRP0                                                              0xe8800a
+#define regPARITY_ERROR_STATUS_UNCORR_GRP0_BASE_IDX                                                     5
+#define regPARITY_ERROR_STATUS_UNCORR_GRP1                                                              0xe8800b
+#define regPARITY_ERROR_STATUS_UNCORR_GRP1_BASE_IDX                                                     5
+#define regPARITY_ERROR_STATUS_UNCORR_GRP2                                                              0xe8800c
+#define regPARITY_ERROR_STATUS_UNCORR_GRP2_BASE_IDX                                                     5
+#define regPARITY_ERROR_STATUS_UNCORR_GRP3                                                              0xe8800d
+#define regPARITY_ERROR_STATUS_UNCORR_GRP3_BASE_IDX                                                     5
+#define regPARITY_ERROR_STATUS_UNCORR_GRP4                                                              0xe8800e
+#define regPARITY_ERROR_STATUS_UNCORR_GRP4_BASE_IDX                                                     5
+#define regPARITY_ERROR_STATUS_UNCORR_GRP5                                                              0xe8800f
+#define regPARITY_ERROR_STATUS_UNCORR_GRP5_BASE_IDX                                                     5
+#define regPARITY_ERROR_STATUS_UNCORR_GRP6                                                              0xe88010
+#define regPARITY_ERROR_STATUS_UNCORR_GRP6_BASE_IDX                                                     5
+#define regPARITY_ERROR_STATUS_UNCORR_GRP7                                                              0xe88011
+#define regPARITY_ERROR_STATUS_UNCORR_GRP7_BASE_IDX                                                     5
+#define regPARITY_ERROR_STATUS_CORR_GRP0                                                                0xe88012
+#define regPARITY_ERROR_STATUS_CORR_GRP0_BASE_IDX                                                       5
+#define regPARITY_ERROR_STATUS_CORR_GRP1                                                                0xe88013
+#define regPARITY_ERROR_STATUS_CORR_GRP1_BASE_IDX                                                       5
+#define regPARITY_ERROR_STATUS_CORR_GRP2                                                                0xe88014
+#define regPARITY_ERROR_STATUS_CORR_GRP2_BASE_IDX                                                       5
+#define regPARITY_ERROR_STATUS_CORR_GRP3                                                                0xe88015
+#define regPARITY_ERROR_STATUS_CORR_GRP3_BASE_IDX                                                       5
+#define regPARITY_ERROR_STATUS_CORR_GRP4                                                                0xe88016
+#define regPARITY_ERROR_STATUS_CORR_GRP4_BASE_IDX                                                       5
+#define regPARITY_ERROR_STATUS_CORR_GRP5                                                                0xe88017
+#define regPARITY_ERROR_STATUS_CORR_GRP5_BASE_IDX                                                       5
+#define regPARITY_ERROR_STATUS_CORR_GRP6                                                                0xe88018
+#define regPARITY_ERROR_STATUS_CORR_GRP6_BASE_IDX                                                       5
+#define regPARITY_ERROR_STATUS_CORR_GRP7                                                                0xe88019
+#define regPARITY_ERROR_STATUS_CORR_GRP7_BASE_IDX                                                       5
+#define regPARITY_COUNTER_CORR_GRP0                                                                     0xe8801a
+#define regPARITY_COUNTER_CORR_GRP0_BASE_IDX                                                            5
+#define regPARITY_COUNTER_CORR_GRP1                                                                     0xe8801b
+#define regPARITY_COUNTER_CORR_GRP1_BASE_IDX                                                            5
+#define regPARITY_COUNTER_CORR_GRP2                                                                     0xe8801c
+#define regPARITY_COUNTER_CORR_GRP2_BASE_IDX                                                            5
+#define regPARITY_COUNTER_CORR_GRP3                                                                     0xe8801d
+#define regPARITY_COUNTER_CORR_GRP3_BASE_IDX                                                            5
+#define regPARITY_COUNTER_CORR_GRP4                                                                     0xe8801e
+#define regPARITY_COUNTER_CORR_GRP4_BASE_IDX                                                            5
+#define regPARITY_COUNTER_CORR_GRP5                                                                     0xe8801f
+#define regPARITY_COUNTER_CORR_GRP5_BASE_IDX                                                            5
+#define regPARITY_COUNTER_CORR_GRP6                                                                     0xe88020
+#define regPARITY_COUNTER_CORR_GRP6_BASE_IDX                                                            5
+#define regPARITY_COUNTER_CORR_GRP7                                                                     0xe88021
+#define regPARITY_COUNTER_CORR_GRP7_BASE_IDX                                                            5
+#define regPARITY_ERROR_STATUS_UCP_GRP0                                                                 0xe88022
+#define regPARITY_ERROR_STATUS_UCP_GRP0_BASE_IDX                                                        5
+#define regPARITY_ERROR_STATUS_UCP_GRP1                                                                 0xe88023
+#define regPARITY_ERROR_STATUS_UCP_GRP1_BASE_IDX                                                        5
+#define regPARITY_ERROR_STATUS_UCP_GRP2                                                                 0xe88024
+#define regPARITY_ERROR_STATUS_UCP_GRP2_BASE_IDX                                                        5
+#define regPARITY_ERROR_STATUS_UCP_GRP3                                                                 0xe88025
+#define regPARITY_ERROR_STATUS_UCP_GRP3_BASE_IDX                                                        5
+#define regPARITY_ERROR_STATUS_UCP_GRP4                                                                 0xe88026
+#define regPARITY_ERROR_STATUS_UCP_GRP4_BASE_IDX                                                        5
+#define regPARITY_ERROR_STATUS_UCP_GRP5                                                                 0xe88027
+#define regPARITY_ERROR_STATUS_UCP_GRP5_BASE_IDX                                                        5
+#define regPARITY_ERROR_STATUS_UCP_GRP6                                                                 0xe88028
+#define regPARITY_ERROR_STATUS_UCP_GRP6_BASE_IDX                                                        5
+#define regPARITY_ERROR_STATUS_UCP_GRP7                                                                 0xe88029
+#define regPARITY_ERROR_STATUS_UCP_GRP7_BASE_IDX                                                        5
+#define regPARITY_COUNTER_UCP_GRP0                                                                      0xe8802a
+#define regPARITY_COUNTER_UCP_GRP0_BASE_IDX                                                             5
+#define regPARITY_COUNTER_UCP_GRP1                                                                      0xe8802b
+#define regPARITY_COUNTER_UCP_GRP1_BASE_IDX                                                             5
+#define regPARITY_COUNTER_UCP_GRP2                                                                      0xe8802c
+#define regPARITY_COUNTER_UCP_GRP2_BASE_IDX                                                             5
+#define regPARITY_COUNTER_UCP_GRP3                                                                      0xe8802d
+#define regPARITY_COUNTER_UCP_GRP3_BASE_IDX                                                             5
+#define regPARITY_COUNTER_UCP_GRP4                                                                      0xe8802e
+#define regPARITY_COUNTER_UCP_GRP4_BASE_IDX                                                             5
+#define regPARITY_COUNTER_UCP_GRP5                                                                      0xe8802f
+#define regPARITY_COUNTER_UCP_GRP5_BASE_IDX                                                             5
+#define regPARITY_COUNTER_UCP_GRP6                                                                      0xe88030
+#define regPARITY_COUNTER_UCP_GRP6_BASE_IDX                                                             5
+#define regPARITY_COUNTER_UCP_GRP7                                                                      0xe88031
+#define regPARITY_COUNTER_UCP_GRP7_BASE_IDX                                                             5
+#define regMISC_SEVERITY_CONTROL                                                                        0xe88032
+#define regMISC_SEVERITY_CONTROL_BASE_IDX                                                               5
+#define regMISC_RAS_CONTROL                                                                             0xe88033
+#define regMISC_RAS_CONTROL_BASE_IDX                                                                    5
+#define regRAS_SCRATCH_0                                                                                0xe88034
+#define regRAS_SCRATCH_0_BASE_IDX                                                                       5
+#define regRAS_SCRATCH_1                                                                                0xe88035
+#define regRAS_SCRATCH_1_BASE_IDX                                                                       5
+#define regErrEvent_ACTION_CONTROL                                                                      0xe88036
+#define regErrEvent_ACTION_CONTROL_BASE_IDX                                                             5
+#define regParitySerr_ACTION_CONTROL                                                                    0xe88037
+#define regParitySerr_ACTION_CONTROL_BASE_IDX                                                           5
+#define regParityFatal_ACTION_CONTROL                                                                   0xe88038
+#define regParityFatal_ACTION_CONTROL_BASE_IDX                                                          5
+#define regParityNonFatal_ACTION_CONTROL                                                                0xe88039
+#define regParityNonFatal_ACTION_CONTROL_BASE_IDX                                                       5
+#define regParityCorr_ACTION_CONTROL                                                                    0xe8803a
+#define regParityCorr_ACTION_CONTROL_BASE_IDX                                                           5
+#define regPCIE0PortASerr_ACTION_CONTROL                                                                0xe8803b
+#define regPCIE0PortASerr_ACTION_CONTROL_BASE_IDX                                                       5
+#define regPCIE0PortAIntFatal_ACTION_CONTROL                                                            0xe8803c
+#define regPCIE0PortAIntFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortAIntNonFatal_ACTION_CONTROL                                                         0xe8803d
+#define regPCIE0PortAIntNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortAIntCorr_ACTION_CONTROL                                                             0xe8803e
+#define regPCIE0PortAIntCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortAExtFatal_ACTION_CONTROL                                                            0xe8803f
+#define regPCIE0PortAExtFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortAExtNonFatal_ACTION_CONTROL                                                         0xe88040
+#define regPCIE0PortAExtNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortAExtCorr_ACTION_CONTROL                                                             0xe88041
+#define regPCIE0PortAExtCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortAParityErr_ACTION_CONTROL                                                           0xe88042
+#define regPCIE0PortAParityErr_ACTION_CONTROL_BASE_IDX                                                  5
+#define regPCIE0PortBSerr_ACTION_CONTROL                                                                0xe88043
+#define regPCIE0PortBSerr_ACTION_CONTROL_BASE_IDX                                                       5
+#define regPCIE0PortBIntFatal_ACTION_CONTROL                                                            0xe88044
+#define regPCIE0PortBIntFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortBIntNonFatal_ACTION_CONTROL                                                         0xe88045
+#define regPCIE0PortBIntNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortBIntCorr_ACTION_CONTROL                                                             0xe88046
+#define regPCIE0PortBIntCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortBExtFatal_ACTION_CONTROL                                                            0xe88047
+#define regPCIE0PortBExtFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortBExtNonFatal_ACTION_CONTROL                                                         0xe88048
+#define regPCIE0PortBExtNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortBExtCorr_ACTION_CONTROL                                                             0xe88049
+#define regPCIE0PortBExtCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortBParityErr_ACTION_CONTROL                                                           0xe8804a
+#define regPCIE0PortBParityErr_ACTION_CONTROL_BASE_IDX                                                  5
+#define regPCIE0PortCSerr_ACTION_CONTROL                                                                0xe8804b
+#define regPCIE0PortCSerr_ACTION_CONTROL_BASE_IDX                                                       5
+#define regPCIE0PortCIntFatal_ACTION_CONTROL                                                            0xe8804c
+#define regPCIE0PortCIntFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortCIntNonFatal_ACTION_CONTROL                                                         0xe8804d
+#define regPCIE0PortCIntNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortCIntCorr_ACTION_CONTROL                                                             0xe8804e
+#define regPCIE0PortCIntCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortCExtFatal_ACTION_CONTROL                                                            0xe8804f
+#define regPCIE0PortCExtFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortCExtNonFatal_ACTION_CONTROL                                                         0xe88050
+#define regPCIE0PortCExtNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortCExtCorr_ACTION_CONTROL                                                             0xe88051
+#define regPCIE0PortCExtCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortCParityErr_ACTION_CONTROL                                                           0xe88052
+#define regPCIE0PortCParityErr_ACTION_CONTROL_BASE_IDX                                                  5
+#define regPCIE0PortDSerr_ACTION_CONTROL                                                                0xe88053
+#define regPCIE0PortDSerr_ACTION_CONTROL_BASE_IDX                                                       5
+#define regPCIE0PortDIntFatal_ACTION_CONTROL                                                            0xe88054
+#define regPCIE0PortDIntFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortDIntNonFatal_ACTION_CONTROL                                                         0xe88055
+#define regPCIE0PortDIntNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortDIntCorr_ACTION_CONTROL                                                             0xe88056
+#define regPCIE0PortDIntCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortDExtFatal_ACTION_CONTROL                                                            0xe88057
+#define regPCIE0PortDExtFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortDExtNonFatal_ACTION_CONTROL                                                         0xe88058
+#define regPCIE0PortDExtNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortDExtCorr_ACTION_CONTROL                                                             0xe88059
+#define regPCIE0PortDExtCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortDParityErr_ACTION_CONTROL                                                           0xe8805a
+#define regPCIE0PortDParityErr_ACTION_CONTROL_BASE_IDX                                                  5
+#define regPCIE0PortESerr_ACTION_CONTROL                                                                0xe8805b
+#define regPCIE0PortESerr_ACTION_CONTROL_BASE_IDX                                                       5
+#define regPCIE0PortEIntFatal_ACTION_CONTROL                                                            0xe8805c
+#define regPCIE0PortEIntFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortEIntNonFatal_ACTION_CONTROL                                                         0xe8805d
+#define regPCIE0PortEIntNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortEIntCorr_ACTION_CONTROL                                                             0xe8805e
+#define regPCIE0PortEIntCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortEExtFatal_ACTION_CONTROL                                                            0xe8805f
+#define regPCIE0PortEExtFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortEExtNonFatal_ACTION_CONTROL                                                         0xe88060
+#define regPCIE0PortEExtNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortEExtCorr_ACTION_CONTROL                                                             0xe88061
+#define regPCIE0PortEExtCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortEParityErr_ACTION_CONTROL                                                           0xe88062
+#define regPCIE0PortEParityErr_ACTION_CONTROL_BASE_IDX                                                  5
+#define regPCIE0PortFSerr_ACTION_CONTROL                                                                0xe88063
+#define regPCIE0PortFSerr_ACTION_CONTROL_BASE_IDX                                                       5
+#define regPCIE0PortFIntFatal_ACTION_CONTROL                                                            0xe88064
+#define regPCIE0PortFIntFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortFIntNonFatal_ACTION_CONTROL                                                         0xe88065
+#define regPCIE0PortFIntNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortFIntCorr_ACTION_CONTROL                                                             0xe88066
+#define regPCIE0PortFIntCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortFExtFatal_ACTION_CONTROL                                                            0xe88067
+#define regPCIE0PortFExtFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortFExtNonFatal_ACTION_CONTROL                                                         0xe88068
+#define regPCIE0PortFExtNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortFExtCorr_ACTION_CONTROL                                                             0xe88069
+#define regPCIE0PortFExtCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortFParityErr_ACTION_CONTROL                                                           0xe8806a
+#define regPCIE0PortFParityErr_ACTION_CONTROL_BASE_IDX                                                  5
+#define regPCIE0PortGSerr_ACTION_CONTROL                                                                0xe8806b
+#define regPCIE0PortGSerr_ACTION_CONTROL_BASE_IDX                                                       5
+#define regPCIE0PortGIntFatal_ACTION_CONTROL                                                            0xe8806c
+#define regPCIE0PortGIntFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortGIntNonFatal_ACTION_CONTROL                                                         0xe8806d
+#define regPCIE0PortGIntNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortGIntCorr_ACTION_CONTROL                                                             0xe8806e
+#define regPCIE0PortGIntCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortGExtFatal_ACTION_CONTROL                                                            0xe8806f
+#define regPCIE0PortGExtFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regPCIE0PortGExtNonFatal_ACTION_CONTROL                                                         0xe88070
+#define regPCIE0PortGExtNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regPCIE0PortGExtCorr_ACTION_CONTROL                                                             0xe88071
+#define regPCIE0PortGExtCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regPCIE0PortGParityErr_ACTION_CONTROL                                                           0xe88072
+#define regPCIE0PortGParityErr_ACTION_CONTROL_BASE_IDX                                                  5
+#define regNBIF1PortASerr_ACTION_CONTROL                                                                0xe88073
+#define regNBIF1PortASerr_ACTION_CONTROL_BASE_IDX                                                       5
+#define regNBIF1PortAIntFatal_ACTION_CONTROL                                                            0xe88074
+#define regNBIF1PortAIntFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regNBIF1PortAIntNonFatal_ACTION_CONTROL                                                         0xe88075
+#define regNBIF1PortAIntNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regNBIF1PortAIntCorr_ACTION_CONTROL                                                             0xe88076
+#define regNBIF1PortAIntCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regNBIF1PortAExtFatal_ACTION_CONTROL                                                            0xe88077
+#define regNBIF1PortAExtFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regNBIF1PortAExtNonFatal_ACTION_CONTROL                                                         0xe88078
+#define regNBIF1PortAExtNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regNBIF1PortAExtCorr_ACTION_CONTROL                                                             0xe88079
+#define regNBIF1PortAExtCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regNBIF1PortAParityErr_ACTION_CONTROL                                                           0xe8807a
+#define regNBIF1PortAParityErr_ACTION_CONTROL_BASE_IDX                                                  5
+#define regNBIF1PortBSerr_ACTION_CONTROL                                                                0xe8807b
+#define regNBIF1PortBSerr_ACTION_CONTROL_BASE_IDX                                                       5
+#define regNBIF1PortBIntFatal_ACTION_CONTROL                                                            0xe8807c
+#define regNBIF1PortBIntFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regNBIF1PortBIntNonFatal_ACTION_CONTROL                                                         0xe8807d
+#define regNBIF1PortBIntNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regNBIF1PortBIntCorr_ACTION_CONTROL                                                             0xe8807e
+#define regNBIF1PortBIntCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regNBIF1PortBExtFatal_ACTION_CONTROL                                                            0xe8807f
+#define regNBIF1PortBExtFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regNBIF1PortBExtNonFatal_ACTION_CONTROL                                                         0xe88080
+#define regNBIF1PortBExtNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regNBIF1PortBExtCorr_ACTION_CONTROL                                                             0xe88081
+#define regNBIF1PortBExtCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regNBIF1PortBParityErr_ACTION_CONTROL                                                           0xe88082
+#define regNBIF1PortBParityErr_ACTION_CONTROL_BASE_IDX                                                  5
+#define regNBIF1PortCSerr_ACTION_CONTROL                                                                0xe88083
+#define regNBIF1PortCSerr_ACTION_CONTROL_BASE_IDX                                                       5
+#define regNBIF1PortCIntFatal_ACTION_CONTROL                                                            0xe88084
+#define regNBIF1PortCIntFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regNBIF1PortCIntNonFatal_ACTION_CONTROL                                                         0xe88085
+#define regNBIF1PortCIntNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regNBIF1PortCIntCorr_ACTION_CONTROL                                                             0xe88086
+#define regNBIF1PortCIntCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regNBIF1PortCExtFatal_ACTION_CONTROL                                                            0xe88087
+#define regNBIF1PortCExtFatal_ACTION_CONTROL_BASE_IDX                                                   5
+#define regNBIF1PortCExtNonFatal_ACTION_CONTROL                                                         0xe88088
+#define regNBIF1PortCExtNonFatal_ACTION_CONTROL_BASE_IDX                                                5
+#define regNBIF1PortCExtCorr_ACTION_CONTROL                                                             0xe88089
+#define regNBIF1PortCExtCorr_ACTION_CONTROL_BASE_IDX                                                    5
+#define regNBIF1PortCParityErr_ACTION_CONTROL                                                           0xe8808a
+#define regNBIF1PortCParityErr_ACTION_CONTROL_BASE_IDX                                                  5
+#define regSYNCFLOOD_STATUS                                                                             0xe88200
+#define regSYNCFLOOD_STATUS_BASE_IDX                                                                    5
+#define regNMI_STATUS                                                                                   0xe88201
+#define regNMI_STATUS_BASE_IDX                                                                          5
+#define regPOISON_ACTION_CONTROL                                                                        0xe88205
+#define regPOISON_ACTION_CONTROL_BASE_IDX                                                               5
+#define regEGRESS_POISON_STATUS_LO                                                                      0xe88208
+#define regEGRESS_POISON_STATUS_LO_BASE_IDX                                                             5
+#define regEGRESS_POISON_STATUS_HI                                                                      0xe88209
+#define regEGRESS_POISON_STATUS_HI_BASE_IDX                                                             5
+#define regEGRESS_POISON_MASK_LO                                                                        0xe8820a
+#define regEGRESS_POISON_MASK_LO_BASE_IDX                                                               5
+#define regEGRESS_POISON_MASK_HI                                                                        0xe8820b
+#define regEGRESS_POISON_MASK_HI_BASE_IDX                                                               5
+#define regEGRESS_POISON_SEVERITY_DOWN                                                                  0xe8820c
+#define regEGRESS_POISON_SEVERITY_DOWN_BASE_IDX                                                         5
+#define regEGRESS_POISON_SEVERITY_UPPER                                                                 0xe8820d
+#define regEGRESS_POISON_SEVERITY_UPPER_BASE_IDX                                                        5
+#define regAPML_STATUS                                                                                  0xe88370
+#define regAPML_STATUS_BASE_IDX                                                                         5
+#define regAPML_CONTROL                                                                                 0xe88371
+#define regAPML_CONTROL_BASE_IDX                                                                        5
+#define regAPML_TRIGGER                                                                                 0xe88372
+#define regAPML_TRIGGER_BASE_IDX                                                                        5
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+// base address: 0xd0000000
+#define regBIF_BX_PF2_MM_INDEX                                                                          0x2ffc0000
+#define regBIF_BX_PF2_MM_INDEX_BASE_IDX                                                                 5
+#define regBIF_BX_PF2_MM_DATA                                                                           0x2ffc0001
+#define regBIF_BX_PF2_MM_DATA_BASE_IDX                                                                  5
+#define regBIF_BX_PF2_MM_INDEX_HI                                                                       0x2ffc0006
+#define regBIF_BX_PF2_MM_INDEX_HI_BASE_IDX                                                              5
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+// base address: 0xd0000000
+#define regBIF_BX2_PCIE_INDEX                                                                           0x2ffc000c
+#define regBIF_BX2_PCIE_INDEX_BASE_IDX                                                                  5
+#define regBIF_BX2_PCIE_DATA                                                                            0x2ffc000d
+#define regBIF_BX2_PCIE_DATA_BASE_IDX                                                                   5
+#define regBIF_BX2_PCIE_INDEX2                                                                          0x2ffc000e
+#define regBIF_BX2_PCIE_INDEX2_BASE_IDX                                                                 5
+#define regBIF_BX2_PCIE_DATA2                                                                           0x2ffc000f
+#define regBIF_BX2_PCIE_DATA2_BASE_IDX                                                                  5
+#define regBIF_BX2_SBIOS_SCRATCH_0                                                                      0x2ffc0048
+#define regBIF_BX2_SBIOS_SCRATCH_0_BASE_IDX                                                             5
+#define regBIF_BX2_SBIOS_SCRATCH_1                                                                      0x2ffc0049
+#define regBIF_BX2_SBIOS_SCRATCH_1_BASE_IDX                                                             5
+#define regBIF_BX2_SBIOS_SCRATCH_2                                                                      0x2ffc004a
+#define regBIF_BX2_SBIOS_SCRATCH_2_BASE_IDX                                                             5
+#define regBIF_BX2_SBIOS_SCRATCH_3                                                                      0x2ffc004b
+#define regBIF_BX2_SBIOS_SCRATCH_3_BASE_IDX                                                             5
+#define regBIF_BX2_BIOS_SCRATCH_0                                                                       0x2ffc004c
+#define regBIF_BX2_BIOS_SCRATCH_0_BASE_IDX                                                              5
+#define regBIF_BX2_BIOS_SCRATCH_1                                                                       0x2ffc004d
+#define regBIF_BX2_BIOS_SCRATCH_1_BASE_IDX                                                              5
+#define regBIF_BX2_BIOS_SCRATCH_2                                                                       0x2ffc004e
+#define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX                                                              5
+#define regBIF_BX2_BIOS_SCRATCH_3                                                                       0x2ffc004f
+#define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX                                                              5
+#define regBIF_BX2_BIOS_SCRATCH_4                                                                       0x2ffc0050
+#define regBIF_BX2_BIOS_SCRATCH_4_BASE_IDX                                                              5
+#define regBIF_BX2_BIOS_SCRATCH_5                                                                       0x2ffc0051
+#define regBIF_BX2_BIOS_SCRATCH_5_BASE_IDX                                                              5
+#define regBIF_BX2_BIOS_SCRATCH_6                                                                       0x2ffc0052
+#define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX                                                              5
+#define regBIF_BX2_BIOS_SCRATCH_7                                                                       0x2ffc0053
+#define regBIF_BX2_BIOS_SCRATCH_7_BASE_IDX                                                              5
+#define regBIF_BX2_BIOS_SCRATCH_8                                                                       0x2ffc0054
+#define regBIF_BX2_BIOS_SCRATCH_8_BASE_IDX                                                              5
+#define regBIF_BX2_BIOS_SCRATCH_9                                                                       0x2ffc0055
+#define regBIF_BX2_BIOS_SCRATCH_9_BASE_IDX                                                              5
+#define regBIF_BX2_BIOS_SCRATCH_10                                                                      0x2ffc0056
+#define regBIF_BX2_BIOS_SCRATCH_10_BASE_IDX                                                             5
+#define regBIF_BX2_BIOS_SCRATCH_11                                                                      0x2ffc0057
+#define regBIF_BX2_BIOS_SCRATCH_11_BASE_IDX                                                             5
+#define regBIF_BX2_BIOS_SCRATCH_12                                                                      0x2ffc0058
+#define regBIF_BX2_BIOS_SCRATCH_12_BASE_IDX                                                             5
+#define regBIF_BX2_BIOS_SCRATCH_13                                                                      0x2ffc0059
+#define regBIF_BX2_BIOS_SCRATCH_13_BASE_IDX                                                             5
+#define regBIF_BX2_BIOS_SCRATCH_14                                                                      0x2ffc005a
+#define regBIF_BX2_BIOS_SCRATCH_14_BASE_IDX                                                             5
+#define regBIF_BX2_BIOS_SCRATCH_15                                                                      0x2ffc005b
+#define regBIF_BX2_BIOS_SCRATCH_15_BASE_IDX                                                             5
+#define regBIF_BX2_BIF_RLC_INTR_CNTL                                                                    0x2ffc0060
+#define regBIF_BX2_BIF_RLC_INTR_CNTL_BASE_IDX                                                           5
+#define regBIF_BX2_BIF_VCE_INTR_CNTL                                                                    0x2ffc0061
+#define regBIF_BX2_BIF_VCE_INTR_CNTL_BASE_IDX                                                           5
+#define regBIF_BX2_BIF_UVD_INTR_CNTL                                                                    0x2ffc0062
+#define regBIF_BX2_BIF_UVD_INTR_CNTL_BASE_IDX                                                           5
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR0                                                                0x2ffc0080
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR0_BASE_IDX                                                       5
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0                                                          0x2ffc0081
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX                                                 5
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR1                                                                0x2ffc0082
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR1_BASE_IDX                                                       5
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1                                                          0x2ffc0083
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX                                                 5
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR2                                                                0x2ffc0084
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR2_BASE_IDX                                                       5
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2                                                          0x2ffc0085
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX                                                 5
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR3                                                                0x2ffc0086
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR3_BASE_IDX                                                       5
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3                                                          0x2ffc0087
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX                                                 5
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR4                                                                0x2ffc0088
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR4_BASE_IDX                                                       5
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4                                                          0x2ffc0089
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX                                                 5
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR5                                                                0x2ffc008a
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR5_BASE_IDX                                                       5
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5                                                          0x2ffc008b
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX                                                 5
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR6                                                                0x2ffc008c
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR6_BASE_IDX                                                       5
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6                                                          0x2ffc008d
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX                                                 5
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR7                                                                0x2ffc008e
+#define regBIF_BX2_GFX_MMIOREG_CAM_ADDR7_BASE_IDX                                                       5
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7                                                          0x2ffc008f
+#define regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX                                                 5
+#define regBIF_BX2_GFX_MMIOREG_CAM_CNTL                                                                 0x2ffc0090
+#define regBIF_BX2_GFX_MMIOREG_CAM_CNTL_BASE_IDX                                                        5
+#define regBIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL                                                             0x2ffc0091
+#define regBIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX                                                    5
+#define regBIF_BX2_GFX_MMIOREG_CAM_ONE_CPL                                                              0x2ffc0092
+#define regBIF_BX2_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX                                                     5
+#define regBIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL                                                     0x2ffc0093
+#define regBIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
+// base address: 0xd0000000
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+// base address: 0xd0000000
+#define regRCC_STRAP3_RCC_BIF_STRAP0                                                                    0x2ffc0d20
+#define regRCC_STRAP3_RCC_BIF_STRAP0_BASE_IDX                                                           5
+#define regRCC_STRAP3_RCC_BIF_STRAP1                                                                    0x2ffc0d21
+#define regRCC_STRAP3_RCC_BIF_STRAP1_BASE_IDX                                                           5
+#define regRCC_STRAP3_RCC_BIF_STRAP2                                                                    0x2ffc0d22
+#define regRCC_STRAP3_RCC_BIF_STRAP2_BASE_IDX                                                           5
+#define regRCC_STRAP3_RCC_BIF_STRAP3                                                                    0x2ffc0d23
+#define regRCC_STRAP3_RCC_BIF_STRAP3_BASE_IDX                                                           5
+#define regRCC_STRAP3_RCC_BIF_STRAP4                                                                    0x2ffc0d24
+#define regRCC_STRAP3_RCC_BIF_STRAP4_BASE_IDX                                                           5
+#define regRCC_STRAP3_RCC_BIF_STRAP5                                                                    0x2ffc0d25
+#define regRCC_STRAP3_RCC_BIF_STRAP5_BASE_IDX                                                           5
+#define regRCC_STRAP3_RCC_BIF_STRAP6                                                                    0x2ffc0d26
+#define regRCC_STRAP3_RCC_BIF_STRAP6_BASE_IDX                                                           5
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP0                                                              0x2ffc0d27
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP1                                                              0x2ffc0d28
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP2                                                              0x2ffc0d29
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP3                                                              0x2ffc0d2a
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP4                                                              0x2ffc0d2b
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP5                                                              0x2ffc0d2c
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP6                                                              0x2ffc0d2d
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP6_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP7                                                              0x2ffc0d2e
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP7_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP8                                                              0x2ffc0d2f
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP9                                                              0x2ffc0d30
+#define regRCC_STRAP3_RCC_DEV0_PORT_STRAP9_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP0                                                              0x2ffc0d31
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP1                                                              0x2ffc0d32
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP13                                                             0x2ffc0d33
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP14                                                             0x2ffc0d34
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP14_BASE_IDX                                                    5
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP2                                                              0x2ffc0d35
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP3                                                              0x2ffc0d36
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP4                                                              0x2ffc0d37
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP5                                                              0x2ffc0d38
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP8                                                              0x2ffc0d39
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP9                                                              0x2ffc0d3a
+#define regRCC_STRAP3_RCC_DEV0_EPF0_STRAP9_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP0                                                              0x2ffc0d3b
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP10                                                             0x2ffc0d3c
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP10_BASE_IDX                                                    5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP11                                                             0x2ffc0d3d
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP11_BASE_IDX                                                    5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP12                                                             0x2ffc0d3e
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP12_BASE_IDX                                                    5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP13                                                             0x2ffc0d3f
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP14                                                             0x2ffc0d40
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP14_BASE_IDX                                                    5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP2                                                              0x2ffc0d41
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP3                                                              0x2ffc0d42
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP4                                                              0x2ffc0d43
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP5                                                              0x2ffc0d44
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP6                                                              0x2ffc0d45
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP6_BASE_IDX                                                     5
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP7                                                              0x2ffc0d46
+#define regRCC_STRAP3_RCC_DEV0_EPF1_STRAP7_BASE_IDX                                                     5
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+// base address: 0xd0000000
+#define regRCC_EP_DEV0_3_EP_PCIE_SCRATCH                                                                0x2ffc0d47
+#define regRCC_EP_DEV0_3_EP_PCIE_SCRATCH_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_3_EP_PCIE_CNTL                                                                   0x2ffc0d49
+#define regRCC_EP_DEV0_3_EP_PCIE_CNTL_BASE_IDX                                                          5
+#define regRCC_EP_DEV0_3_EP_PCIE_INT_CNTL                                                               0x2ffc0d4a
+#define regRCC_EP_DEV0_3_EP_PCIE_INT_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_3_EP_PCIE_INT_STATUS                                                             0x2ffc0d4b
+#define regRCC_EP_DEV0_3_EP_PCIE_INT_STATUS_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_3_EP_PCIE_RX_CNTL2                                                               0x2ffc0d4c
+#define regRCC_EP_DEV0_3_EP_PCIE_RX_CNTL2_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_3_EP_PCIE_BUS_CNTL                                                               0x2ffc0d4d
+#define regRCC_EP_DEV0_3_EP_PCIE_BUS_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_3_EP_PCIE_CFG_CNTL                                                               0x2ffc0d4e
+#define regRCC_EP_DEV0_3_EP_PCIE_CFG_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL                                                            0x2ffc0d50
+#define regRCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0                                               0x2ffc0d51
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1                                               0x2ffc0d51
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2                                               0x2ffc0d51
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3                                               0x2ffc0d51
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4                                               0x2ffc0d52
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5                                               0x2ffc0d52
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6                                               0x2ffc0d52
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7                                               0x2ffc0d52
+#define regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      5
+#define regRCC_EP_DEV0_3_EP_PCIE_STRAP_MISC                                                             0x2ffc0d53
+#define regRCC_EP_DEV0_3_EP_PCIE_STRAP_MISC_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_3_EP_PCIE_STRAP_MISC2                                                            0x2ffc0d54
+#define regRCC_EP_DEV0_3_EP_PCIE_STRAP_MISC2_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP                                                             0x2ffc0d56
+#define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR                                               0x2ffc0d57
+#define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL                                                            0x2ffc0d57
+#define regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                               0x2ffc0d57
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      5
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                               0x2ffc0d58
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      5
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                               0x2ffc0d58
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      5
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                               0x2ffc0d58
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      5
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                               0x2ffc0d58
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      5
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                               0x2ffc0d59
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      5
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                               0x2ffc0d59
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      5
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                               0x2ffc0d59
+#define regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      5
+#define regRCC_EP_DEV0_3_EP_PCIE_PME_CONTROL                                                            0x2ffc0d59
+#define regRCC_EP_DEV0_3_EP_PCIE_PME_CONTROL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_3_EP_PCIEP_RESERVED                                                              0x2ffc0d5a
+#define regRCC_EP_DEV0_3_EP_PCIEP_RESERVED_BASE_IDX                                                     5
+#define regRCC_EP_DEV0_3_EP_PCIE_TX_CNTL                                                                0x2ffc0d5c
+#define regRCC_EP_DEV0_3_EP_PCIE_TX_CNTL_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID                                                        0x2ffc0d5d
+#define regRCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID_BASE_IDX                                               5
+#define regRCC_EP_DEV0_3_EP_PCIE_ERR_CNTL                                                               0x2ffc0d5e
+#define regRCC_EP_DEV0_3_EP_PCIE_ERR_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_3_EP_PCIE_RX_CNTL                                                                0x2ffc0d5f
+#define regRCC_EP_DEV0_3_EP_PCIE_RX_CNTL_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL                                                          0x2ffc0d60
+#define regRCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+// base address: 0xd0000000
+#define regRCC_DWN_DEV0_3_DN_PCIE_RESERVED                                                              0x2ffc0d62
+#define regRCC_DWN_DEV0_3_DN_PCIE_RESERVED_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_3_DN_PCIE_SCRATCH                                                               0x2ffc0d63
+#define regRCC_DWN_DEV0_3_DN_PCIE_SCRATCH_BASE_IDX                                                      5
+#define regRCC_DWN_DEV0_3_DN_PCIE_CNTL                                                                  0x2ffc0d65
+#define regRCC_DWN_DEV0_3_DN_PCIE_CNTL_BASE_IDX                                                         5
+#define regRCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL                                                           0x2ffc0d66
+#define regRCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL_BASE_IDX                                                  5
+#define regRCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2                                                              0x2ffc0d67
+#define regRCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL                                                              0x2ffc0d68
+#define regRCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL                                                              0x2ffc0d69
+#define regRCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_F0                                                              0x2ffc0d6a
+#define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_F0_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC                                                            0x2ffc0d6b
+#define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC_BASE_IDX                                                   5
+#define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC2                                                           0x2ffc0d6c
+#define regRCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC2_BASE_IDX                                                  5
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+// base address: 0xd0000000
+#define regRCC_DWNP_DEV0_3_PCIE_ERR_CNTL                                                                0x2ffc0d6f
+#define regRCC_DWNP_DEV0_3_PCIE_ERR_CNTL_BASE_IDX                                                       5
+#define regRCC_DWNP_DEV0_3_PCIE_RX_CNTL                                                                 0x2ffc0d70
+#define regRCC_DWNP_DEV0_3_PCIE_RX_CNTL_BASE_IDX                                                        5
+#define regRCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL                                                           0x2ffc0d71
+#define regRCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL_BASE_IDX                                                  5
+#define regRCC_DWNP_DEV0_3_PCIE_LC_CNTL2                                                                0x2ffc0d72
+#define regRCC_DWNP_DEV0_3_PCIE_LC_CNTL2_BASE_IDX                                                       5
+#define regRCC_DWNP_DEV0_3_PCIEP_STRAP_MISC                                                             0x2ffc0d73
+#define regRCC_DWNP_DEV0_3_PCIEP_STRAP_MISC_BASE_IDX                                                    5
+#define regRCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP                                                         0x2ffc0d74
+#define regRCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP_BASE_IDX                                                5
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
+// base address: 0xd0003480
+#define regRCC_DEV0_EPF0_1_RCC_ERR_LOG                                                                  0x2ffc0da5
+#define regRCC_DEV0_EPF0_1_RCC_ERR_LOG_BASE_IDX                                                         5
+#define regRCC_DEV0_EPF0_1_RCC_ERR_LOG_1                                                                0x2ffc0da5
+#define regRCC_DEV0_EPF0_1_RCC_ERR_LOG_1_BASE_IDX                                                       5
+#define regRCC_DEV0_EPF0_1_RCC_ERR_LOG_2                                                                0x2ffc0da5
+#define regRCC_DEV0_EPF0_1_RCC_ERR_LOG_2_BASE_IDX                                                       5
+#define regRCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN                                                         0x2ffc0de0
+#define regRCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_BASE_IDX                                                5
+#define regRCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_1                                                       0x2ffc0de0
+#define regRCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_1_BASE_IDX                                              5
+#define regRCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_2                                                       0x2ffc0de0
+#define regRCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_2_BASE_IDX                                              5
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE                                                           0x2ffc0de3
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_BASE_IDX                                                  5
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_1                                                         0x2ffc0de3
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_1_BASE_IDX                                                5
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_2                                                         0x2ffc0de3
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_2_BASE_IDX                                                5
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED                                                          0x2ffc0de4
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_BASE_IDX                                                 5
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_1                                                        0x2ffc0de4
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_1_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_2                                                        0x2ffc0de4
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_2_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER                                                      0x2ffc0de5
+#define regRCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1                                                    0x2ffc0de5
+#define regRCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1_BASE_IDX                                           5
+#define regRCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2                                                    0x2ffc0de5
+#define regRCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2_BASE_IDX                                           5
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+// base address: 0xd0000000
+#define regRCC_DEV0_2_RCC_ERR_INT_CNTL                                                                  0x2ffc0da6
+#define regRCC_DEV0_2_RCC_ERR_INT_CNTL_BASE_IDX                                                         5
+#define regRCC_DEV0_2_RCC_BACO_CNTL_MISC                                                                0x2ffc0da7
+#define regRCC_DEV0_2_RCC_BACO_CNTL_MISC_BASE_IDX                                                       5
+#define regRCC_DEV0_2_RCC_RESET_EN                                                                      0x2ffc0da8
+#define regRCC_DEV0_2_RCC_RESET_EN_BASE_IDX                                                             5
+#define regRCC_DEV0_3_RCC_VDM_SUPPORT                                                                   0x2ffc0da9
+#define regRCC_DEV0_3_RCC_VDM_SUPPORT_BASE_IDX                                                          5
+#define regRCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0                                                            0x2ffc0daa
+#define regRCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0_BASE_IDX                                                   5
+#define regRCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1                                                            0x2ffc0dab
+#define regRCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                   5
+#define regRCC_DEV0_2_RCC_GPUIOV_REGION                                                                 0x2ffc0dac
+#define regRCC_DEV0_2_RCC_GPUIOV_REGION_BASE_IDX                                                        5
+#define regRCC_DEV0_2_RCC_GPU_HOSTVM_EN                                                                 0x2ffc0dad
+#define regRCC_DEV0_2_RCC_GPU_HOSTVM_EN_BASE_IDX                                                        5
+#define regRCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL                                                         0x2ffc0dae
+#define regRCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX                                                5
+#define regRCC_DEV0_2_RCC_CONSOLE_IOV_FIRST_VF_OFFSET                                                   0x2ffc0daf
+#define regRCC_DEV0_2_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX                                          5
+#define regRCC_DEV0_2_RCC_CONSOLE_IOV_VF_STRIDE                                                         0x2ffc0daf
+#define regRCC_DEV0_2_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX                                                5
+#define regRCC_DEV0_2_RCC_PEER_REG_RANGE0                                                               0x2ffc0dde
+#define regRCC_DEV0_2_RCC_PEER_REG_RANGE0_BASE_IDX                                                      5
+#define regRCC_DEV0_2_RCC_PEER_REG_RANGE1                                                               0x2ffc0ddf
+#define regRCC_DEV0_2_RCC_PEER_REG_RANGE1_BASE_IDX                                                      5
+#define regRCC_DEV0_3_RCC_BUS_CNTL                                                                      0x2ffc0de1
+#define regRCC_DEV0_3_RCC_BUS_CNTL_BASE_IDX                                                             5
+#define regRCC_DEV0_2_RCC_CONFIG_CNTL                                                                   0x2ffc0de2
+#define regRCC_DEV0_2_RCC_CONFIG_CNTL_BASE_IDX                                                          5
+#define regRCC_DEV0_2_RCC_CONFIG_F0_BASE                                                                0x2ffc0de6
+#define regRCC_DEV0_2_RCC_CONFIG_F0_BASE_BASE_IDX                                                       5
+#define regRCC_DEV0_2_RCC_CONFIG_APER_SIZE                                                              0x2ffc0de7
+#define regRCC_DEV0_2_RCC_CONFIG_APER_SIZE_BASE_IDX                                                     5
+#define regRCC_DEV0_2_RCC_CONFIG_REG_APER_SIZE                                                          0x2ffc0de8
+#define regRCC_DEV0_2_RCC_CONFIG_REG_APER_SIZE_BASE_IDX                                                 5
+#define regRCC_DEV0_2_RCC_XDMA_LO                                                                       0x2ffc0de9
+#define regRCC_DEV0_2_RCC_XDMA_LO_BASE_IDX                                                              5
+#define regRCC_DEV0_2_RCC_XDMA_HI                                                                       0x2ffc0dea
+#define regRCC_DEV0_2_RCC_XDMA_HI_BASE_IDX                                                              5
+#define regRCC_DEV0_3_RCC_FEATURES_CONTROL_MISC                                                         0x2ffc0deb
+#define regRCC_DEV0_3_RCC_FEATURES_CONTROL_MISC_BASE_IDX                                                5
+#define regRCC_DEV0_2_RCC_BUSNUM_CNTL1                                                                  0x2ffc0dec
+#define regRCC_DEV0_2_RCC_BUSNUM_CNTL1_BASE_IDX                                                         5
+#define regRCC_DEV0_2_RCC_BUSNUM_LIST0                                                                  0x2ffc0ded
+#define regRCC_DEV0_2_RCC_BUSNUM_LIST0_BASE_IDX                                                         5
+#define regRCC_DEV0_2_RCC_BUSNUM_LIST1                                                                  0x2ffc0dee
+#define regRCC_DEV0_2_RCC_BUSNUM_LIST1_BASE_IDX                                                         5
+#define regRCC_DEV0_2_RCC_BUSNUM_CNTL2                                                                  0x2ffc0def
+#define regRCC_DEV0_2_RCC_BUSNUM_CNTL2_BASE_IDX                                                         5
+#define regRCC_DEV0_2_RCC_CAPTURE_HOST_BUSNUM                                                           0x2ffc0df0
+#define regRCC_DEV0_2_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX                                                  5
+#define regRCC_DEV0_2_RCC_HOST_BUSNUM                                                                   0x2ffc0df1
+#define regRCC_DEV0_2_RCC_HOST_BUSNUM_BASE_IDX                                                          5
+#define regRCC_DEV0_2_RCC_PEER0_FB_OFFSET_HI                                                            0x2ffc0df2
+#define regRCC_DEV0_2_RCC_PEER0_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO                                                            0x2ffc0df3
+#define regRCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_2_RCC_PEER1_FB_OFFSET_HI                                                            0x2ffc0df4
+#define regRCC_DEV0_2_RCC_PEER1_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO                                                            0x2ffc0df5
+#define regRCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_2_RCC_PEER2_FB_OFFSET_HI                                                            0x2ffc0df6
+#define regRCC_DEV0_2_RCC_PEER2_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO                                                            0x2ffc0df7
+#define regRCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_2_RCC_PEER3_FB_OFFSET_HI                                                            0x2ffc0df8
+#define regRCC_DEV0_2_RCC_PEER3_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO                                                            0x2ffc0df9
+#define regRCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_2_RCC_DEVFUNCNUM_LIST0                                                              0x2ffc0dfa
+#define regRCC_DEV0_2_RCC_DEVFUNCNUM_LIST0_BASE_IDX                                                     5
+#define regRCC_DEV0_2_RCC_DEVFUNCNUM_LIST1                                                              0x2ffc0dfb
+#define regRCC_DEV0_2_RCC_DEVFUNCNUM_LIST1_BASE_IDX                                                     5
+#define regRCC_DEV0_3_RCC_DEV0_LINK_CNTL                                                                0x2ffc0dfd
+#define regRCC_DEV0_3_RCC_DEV0_LINK_CNTL_BASE_IDX                                                       5
+#define regRCC_DEV0_3_RCC_CMN_LINK_CNTL                                                                 0x2ffc0dfe
+#define regRCC_DEV0_3_RCC_CMN_LINK_CNTL_BASE_IDX                                                        5
+#define regRCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE                                                        0x2ffc0dff
+#define regRCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE_BASE_IDX                                               5
+#define regRCC_DEV0_3_RCC_LTR_LSWITCH_CNTL                                                              0x2ffc0e00
+#define regRCC_DEV0_3_RCC_LTR_LSWITCH_CNTL_BASE_IDX                                                     5
+#define regRCC_DEV0_3_RCC_MH_ARB_CNTL                                                                   0x2ffc0e01
+#define regRCC_DEV0_3_RCC_MH_ARB_CNTL_BASE_IDX                                                          5
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+// base address: 0xd0000000
+#define regBIF_BX2_CC_BIF_BX_STRAP0                                                                     0x2ffc0e02
+#define regBIF_BX2_CC_BIF_BX_STRAP0_BASE_IDX                                                            5
+#define regBIF_BX2_CC_BIF_BX_PINSTRAP0                                                                  0x2ffc0e04
+#define regBIF_BX2_CC_BIF_BX_PINSTRAP0_BASE_IDX                                                         5
+#define regBIF_BX2_BIF_MM_INDACCESS_CNTL                                                                0x2ffc0e06
+#define regBIF_BX2_BIF_MM_INDACCESS_CNTL_BASE_IDX                                                       5
+#define regBIF_BX2_BUS_CNTL                                                                             0x2ffc0e07
+#define regBIF_BX2_BUS_CNTL_BASE_IDX                                                                    5
+#define regBIF_BX2_BIF_SCRATCH0                                                                         0x2ffc0e08
+#define regBIF_BX2_BIF_SCRATCH0_BASE_IDX                                                                5
+#define regBIF_BX2_BIF_SCRATCH1                                                                         0x2ffc0e09
+#define regBIF_BX2_BIF_SCRATCH1_BASE_IDX                                                                5
+#define regBIF_BX2_BX_RESET_EN                                                                          0x2ffc0e0d
+#define regBIF_BX2_BX_RESET_EN_BASE_IDX                                                                 5
+#define regBIF_BX2_MM_CFGREGS_CNTL                                                                      0x2ffc0e0e
+#define regBIF_BX2_MM_CFGREGS_CNTL_BASE_IDX                                                             5
+#define regBIF_BX2_BX_RESET_CNTL                                                                        0x2ffc0e10
+#define regBIF_BX2_BX_RESET_CNTL_BASE_IDX                                                               5
+#define regBIF_BX2_INTERRUPT_CNTL                                                                       0x2ffc0e11
+#define regBIF_BX2_INTERRUPT_CNTL_BASE_IDX                                                              5
+#define regBIF_BX2_INTERRUPT_CNTL2                                                                      0x2ffc0e12
+#define regBIF_BX2_INTERRUPT_CNTL2_BASE_IDX                                                             5
+#define regBIF_BX2_CLKREQB_PAD_CNTL                                                                     0x2ffc0e18
+#define regBIF_BX2_CLKREQB_PAD_CNTL_BASE_IDX                                                            5
+#define regBIF_BX2_BIF_FEATURES_CONTROL_MISC                                                            0x2ffc0e1b
+#define regBIF_BX2_BIF_FEATURES_CONTROL_MISC_BASE_IDX                                                   5
+#define regBIF_BX2_BIF_DOORBELL_CNTL                                                                    0x2ffc0e1c
+#define regBIF_BX2_BIF_DOORBELL_CNTL_BASE_IDX                                                           5
+#define regBIF_BX2_BIF_DOORBELL_INT_CNTL                                                                0x2ffc0e1d
+#define regBIF_BX2_BIF_DOORBELL_INT_CNTL_BASE_IDX                                                       5
+#define regBIF_BX2_BIF_FB_EN                                                                            0x2ffc0e1f
+#define regBIF_BX2_BIF_FB_EN_BASE_IDX                                                                   5
+#define regBIF_BX2_BIF_INTR_CNTL                                                                        0x2ffc0e20
+#define regBIF_BX2_BIF_INTR_CNTL_BASE_IDX                                                               5
+#define regBIF_BX2_BIF_MST_TRANS_PENDING_VF                                                             0x2ffc0e29
+#define regBIF_BX2_BIF_MST_TRANS_PENDING_VF_BASE_IDX                                                    5
+#define regBIF_BX2_BIF_SLV_TRANS_PENDING_VF                                                             0x2ffc0e2a
+#define regBIF_BX2_BIF_SLV_TRANS_PENDING_VF_BASE_IDX                                                    5
+#define regBIF_BX2_BACO_CNTL                                                                            0x2ffc0e2b
+#define regBIF_BX2_BACO_CNTL_BASE_IDX                                                                   5
+#define regBIF_BX2_BIF_BACO_EXIT_TIME0                                                                  0x2ffc0e2c
+#define regBIF_BX2_BIF_BACO_EXIT_TIME0_BASE_IDX                                                         5
+#define regBIF_BX2_BIF_BACO_EXIT_TIMER1                                                                 0x2ffc0e2d
+#define regBIF_BX2_BIF_BACO_EXIT_TIMER1_BASE_IDX                                                        5
+#define regBIF_BX2_BIF_BACO_EXIT_TIMER2                                                                 0x2ffc0e2e
+#define regBIF_BX2_BIF_BACO_EXIT_TIMER2_BASE_IDX                                                        5
+#define regBIF_BX2_BIF_BACO_EXIT_TIMER3                                                                 0x2ffc0e2f
+#define regBIF_BX2_BIF_BACO_EXIT_TIMER3_BASE_IDX                                                        5
+#define regBIF_BX2_BIF_BACO_EXIT_TIMER4                                                                 0x2ffc0e30
+#define regBIF_BX2_BIF_BACO_EXIT_TIMER4_BASE_IDX                                                        5
+#define regBIF_BX2_MEM_TYPE_CNTL                                                                        0x2ffc0e31
+#define regBIF_BX2_MEM_TYPE_CNTL_BASE_IDX                                                               5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_CNTL                                                               0x2ffc0e33
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX                                                      5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_0                                                                  0x2ffc0e34
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_0_BASE_IDX                                                         5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_1                                                                  0x2ffc0e35
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_1_BASE_IDX                                                         5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_2                                                                  0x2ffc0e36
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_2_BASE_IDX                                                         5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_3                                                                  0x2ffc0e37
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_3_BASE_IDX                                                         5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_4                                                                  0x2ffc0e38
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_4_BASE_IDX                                                         5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_5                                                                  0x2ffc0e39
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_5_BASE_IDX                                                         5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_6                                                                  0x2ffc0e3a
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_6_BASE_IDX                                                         5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_7                                                                  0x2ffc0e3b
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_7_BASE_IDX                                                         5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_8                                                                  0x2ffc0e3c
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_8_BASE_IDX                                                         5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_9                                                                  0x2ffc0e3d
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_9_BASE_IDX                                                         5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_10                                                                 0x2ffc0e3e
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_10_BASE_IDX                                                        5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_11                                                                 0x2ffc0e3f
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_11_BASE_IDX                                                        5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_12                                                                 0x2ffc0e40
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_12_BASE_IDX                                                        5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_13                                                                 0x2ffc0e41
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_13_BASE_IDX                                                        5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_14                                                                 0x2ffc0e42
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_14_BASE_IDX                                                        5
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_15                                                                 0x2ffc0e43
+#define regBIF_BX2_NBIF_GFX_ADDR_LUT_15_BASE_IDX                                                        5
+#define regBIF_BX2_VF_REGWR_EN                                                                          0x2ffc0e44
+#define regBIF_BX2_VF_REGWR_EN_BASE_IDX                                                                 5
+#define regBIF_BX2_VF_DOORBELL_EN                                                                       0x2ffc0e45
+#define regBIF_BX2_VF_DOORBELL_EN_BASE_IDX                                                              5
+#define regBIF_BX2_VF_FB_EN                                                                             0x2ffc0e46
+#define regBIF_BX2_VF_FB_EN_BASE_IDX                                                                    5
+#define regBIF_BX2_VF_REGWR_STATUS                                                                      0x2ffc0e47
+#define regBIF_BX2_VF_REGWR_STATUS_BASE_IDX                                                             5
+#define regBIF_BX2_VF_DOORBELL_STATUS                                                                   0x2ffc0e48
+#define regBIF_BX2_VF_DOORBELL_STATUS_BASE_IDX                                                          5
+#define regBIF_BX2_VF_FB_STATUS                                                                         0x2ffc0e49
+#define regBIF_BX2_VF_FB_STATUS_BASE_IDX                                                                5
+#define regBIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL                                                             0x2ffc0e4d
+#define regBIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX                                                    5
+#define regBIF_BX2_REMAP_HDP_REG_FLUSH_CNTL                                                             0x2ffc0e4e
+#define regBIF_BX2_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX                                                    5
+#define regBIF_BX2_BIF_RB_CNTL                                                                          0x2ffc0e4f
+#define regBIF_BX2_BIF_RB_CNTL_BASE_IDX                                                                 5
+#define regBIF_BX2_BIF_RB_BASE                                                                          0x2ffc0e50
+#define regBIF_BX2_BIF_RB_BASE_BASE_IDX                                                                 5
+#define regBIF_BX2_BIF_RB_RPTR                                                                          0x2ffc0e51
+#define regBIF_BX2_BIF_RB_RPTR_BASE_IDX                                                                 5
+#define regBIF_BX2_BIF_RB_WPTR                                                                          0x2ffc0e52
+#define regBIF_BX2_BIF_RB_WPTR_BASE_IDX                                                                 5
+#define regBIF_BX2_BIF_RB_WPTR_ADDR_HI                                                                  0x2ffc0e53
+#define regBIF_BX2_BIF_RB_WPTR_ADDR_HI_BASE_IDX                                                         5
+#define regBIF_BX2_BIF_RB_WPTR_ADDR_LO                                                                  0x2ffc0e54
+#define regBIF_BX2_BIF_RB_WPTR_ADDR_LO_BASE_IDX                                                         5
+#define regBIF_BX2_MAILBOX_INDEX                                                                        0x2ffc0e55
+#define regBIF_BX2_MAILBOX_INDEX_BASE_IDX                                                               5
+#define regBIF_BX2_BIF_VCN0_GPUIOV_CFG_SIZE                                                             0x2ffc0e63
+#define regBIF_BX2_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX                                                    5
+#define regBIF_BX2_BIF_VCN1_GPUIOV_CFG_SIZE                                                             0x2ffc0e64
+#define regBIF_BX2_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX                                                    5
+#define regBIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE                                                         0x2ffc0e65
+#define regBIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX                                                5
+#define regBIF_BX2_BIF_PERSTB_PAD_CNTL                                                                  0x2ffc0e68
+#define regBIF_BX2_BIF_PERSTB_PAD_CNTL_BASE_IDX                                                         5
+#define regBIF_BX2_BIF_PX_EN_PAD_CNTL                                                                   0x2ffc0e69
+#define regBIF_BX2_BIF_PX_EN_PAD_CNTL_BASE_IDX                                                          5
+#define regBIF_BX2_BIF_REFPADKIN_PAD_CNTL                                                               0x2ffc0e6a
+#define regBIF_BX2_BIF_REFPADKIN_PAD_CNTL_BASE_IDX                                                      5
+#define regBIF_BX2_BIF_CLKREQB_PAD_CNTL                                                                 0x2ffc0e6b
+#define regBIF_BX2_BIF_CLKREQB_PAD_CNTL_BASE_IDX                                                        5
+#define regBIF_BX2_BIF_PWRBRK_PAD_CNTL                                                                  0x2ffc0e6c
+#define regBIF_BX2_BIF_PWRBRK_PAD_CNTL_BASE_IDX                                                         5
+#define regBIF_BX2_BIF_WAKEB_PAD_CNTL                                                                   0x2ffc0e6d
+#define regBIF_BX2_BIF_WAKEB_PAD_CNTL_BASE_IDX                                                          5
+#define regBIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL                                                            0x2ffc0e6e
+#define regBIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX                                                   5
+#define regBIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL                                                           0x2ffc0e70
+#define regBIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL_BASE_IDX                                                  5
+#define regBIF_BX2_BIF_S5_MEM_POWER_CTRL0                                                               0x2ffc0e71
+#define regBIF_BX2_BIF_S5_MEM_POWER_CTRL0_BASE_IDX                                                      5
+#define regBIF_BX2_BIF_S5_MEM_POWER_CTRL1                                                               0x2ffc0e72
+#define regBIF_BX2_BIF_S5_MEM_POWER_CTRL1_BASE_IDX                                                      5
+#define regBIF_BX2_BIF_S5_DUMMY_REGS                                                                    0x2ffc0e73
+#define regBIF_BX2_BIF_S5_DUMMY_REGS_BASE_IDX                                                           5
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+// base address: 0xd0000000
+#define regBIF_BX_PF2_BIF_BME_STATUS                                                                    0x2ffc0e0b
+#define regBIF_BX_PF2_BIF_BME_STATUS_BASE_IDX                                                           5
+#define regBIF_BX_PF2_BIF_ATOMIC_ERR_LOG                                                                0x2ffc0e0c
+#define regBIF_BX_PF2_BIF_ATOMIC_ERR_LOG_BASE_IDX                                                       5
+#define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                              0x2ffc0e13
+#define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                                     5
+#define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                               0x2ffc0e14
+#define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                                      5
+#define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL                                                   0x2ffc0e15
+#define regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                          5
+#define regBIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL                                                      0x2ffc0e16
+#define regBIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                             5
+#define regBIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL                                                      0x2ffc0e17
+#define regBIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                             5
+#define regBIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                                 0x2ffc0e19
+#define regBIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                                        5
+#define regBIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                            0x2ffc0e1a
+#define regBIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                                   5
+#define regBIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ                                                            0x2ffc0e24
+#define regBIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ_BASE_IDX                                                   5
+#define regBIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ                                                       0x2ffc0e25
+#define regBIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ_BASE_IDX                                              5
+#define regBIF_BX_PF2_GPU_HDP_FLUSH_REQ                                                                 0x2ffc0e26
+#define regBIF_BX_PF2_GPU_HDP_FLUSH_REQ_BASE_IDX                                                        5
+#define regBIF_BX_PF2_GPU_HDP_FLUSH_DONE                                                                0x2ffc0e27
+#define regBIF_BX_PF2_GPU_HDP_FLUSH_DONE_BASE_IDX                                                       5
+#define regBIF_BX_PF2_BIF_TRANS_PENDING                                                                 0x2ffc0e28
+#define regBIF_BX_PF2_BIF_TRANS_PENDING_BASE_IDX                                                        5
+#define regBIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS                                                          0x2ffc0e32
+#define regBIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                                 5
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0                                                            0x2ffc0e56
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                                   5
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1                                                            0x2ffc0e57
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                                   5
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2                                                            0x2ffc0e58
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                                   5
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3                                                            0x2ffc0e59
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                                   5
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0                                                            0x2ffc0e5a
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                                   5
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1                                                            0x2ffc0e5b
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                                   5
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2                                                            0x2ffc0e5c
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                                   5
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3                                                            0x2ffc0e5d
+#define regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                                   5
+#define regBIF_BX_PF2_MAILBOX_CONTROL                                                                   0x2ffc0e5e
+#define regBIF_BX_PF2_MAILBOX_CONTROL_BASE_IDX                                                          5
+#define regBIF_BX_PF2_MAILBOX_INT_CNTL                                                                  0x2ffc0e5f
+#define regBIF_BX_PF2_MAILBOX_INT_CNTL_BASE_IDX                                                         5
+#define regBIF_BX_PF2_BIF_VMHV_MAILBOX                                                                  0x2ffc0e60
+#define regBIF_BX_PF2_BIF_VMHV_MAILBOX_BASE_IDX                                                         5
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+// base address: 0xd0000000
+#define regGDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL                                                          0x2ffc0eda
+#define regGDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL_BASE_IDX                                                 5
+#define regGDC1_NGDC_SDP_PORT_CTRL                                                                      0x2ffc0ee2
+#define regGDC1_NGDC_SDP_PORT_CTRL_BASE_IDX                                                             5
+#define regGDC1_SHUB_REGS_IF_CTL                                                                        0x2ffc0ee3
+#define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX                                                               5
+#define regGDC1_NGDC_MP4SDP_CTRL                                                                        0x2ffc0ee4
+#define regGDC1_NGDC_MP4SDP_CTRL_BASE_IDX                                                               5
+#define regGDC1_NGDC_MGCG_CTRL                                                                          0x2ffc0eea
+#define regGDC1_NGDC_MGCG_CTRL_BASE_IDX                                                                 5
+#define regGDC1_NGDC_RESERVED_0                                                                         0x2ffc0eeb
+#define regGDC1_NGDC_RESERVED_0_BASE_IDX                                                                5
+#define regGDC1_NGDC_RESERVED_1                                                                         0x2ffc0eec
+#define regGDC1_NGDC_RESERVED_1_BASE_IDX                                                                5
+#define regGDC1_NGDC_SDP_PORT_CTRL_SOCCLK                                                               0x2ffc0eed
+#define regGDC1_NGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX                                                      5
+#define regGDC1_NGDC_SDP_PORT_CTRL1_SOCCLK                                                              0x2ffc0eee
+#define regGDC1_NGDC_SDP_PORT_CTRL1_SOCCLK_BASE_IDX                                                     5
+#define regGDC1_NBIF_GFX_DOORBELL_STATUS                                                                0x2ffc0eef
+#define regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX                                                       5
+#define regGDC1_BIF_SDMA0_DOORBELL_RANGE                                                                0x2ffc0ef0
+#define regGDC1_BIF_SDMA0_DOORBELL_RANGE_BASE_IDX                                                       5
+#define regGDC1_BIF_SDMA1_DOORBELL_RANGE                                                                0x2ffc0ef1
+#define regGDC1_BIF_SDMA1_DOORBELL_RANGE_BASE_IDX                                                       5
+#define regGDC1_BIF_IH_DOORBELL_RANGE                                                                   0x2ffc0ef2
+#define regGDC1_BIF_IH_DOORBELL_RANGE_BASE_IDX                                                          5
+#define regGDC1_BIF_VCN0_DOORBELL_RANGE                                                                 0x2ffc0ef3
+#define regGDC1_BIF_VCN0_DOORBELL_RANGE_BASE_IDX                                                        5
+#define regGDC1_BIF_RLC_DOORBELL_RANGE                                                                  0x2ffc0ef5
+#define regGDC1_BIF_RLC_DOORBELL_RANGE_BASE_IDX                                                         5
+#define regGDC1_BIF_SDMA2_DOORBELL_RANGE                                                                0x2ffc0ef6
+#define regGDC1_BIF_SDMA2_DOORBELL_RANGE_BASE_IDX                                                       5
+#define regGDC1_BIF_SDMA3_DOORBELL_RANGE                                                                0x2ffc0ef7
+#define regGDC1_BIF_SDMA3_DOORBELL_RANGE_BASE_IDX                                                       5
+#define regGDC1_BIF_VCN1_DOORBELL_RANGE                                                                 0x2ffc0ef8
+#define regGDC1_BIF_VCN1_DOORBELL_RANGE_BASE_IDX                                                        5
+#define regGDC1_BIF_SDMA4_DOORBELL_RANGE                                                                0x2ffc0ef9
+#define regGDC1_BIF_SDMA4_DOORBELL_RANGE_BASE_IDX                                                       5
+#define regGDC1_BIF_SDMA5_DOORBELL_RANGE                                                                0x2ffc0efa
+#define regGDC1_BIF_SDMA5_DOORBELL_RANGE_BASE_IDX                                                       5
+#define regGDC1_ATDMA_MISC_CNTL                                                                         0x2ffc0efd
+#define regGDC1_ATDMA_MISC_CNTL_BASE_IDX                                                                5
+#define regGDC1_BIF_DOORBELL_FENCE_CNTL                                                                 0x2ffc0efe
+#define regGDC1_BIF_DOORBELL_FENCE_CNTL_BASE_IDX                                                        5
+#define regGDC1_S2A_MISC_CNTL                                                                           0x2ffc0eff
+#define regGDC1_S2A_MISC_CNTL_BASE_IDX                                                                  5
+#define regGDC1_NGDC_EARLY_WAKEUP_CTRL                                                                  0x2ffc0f01
+#define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX                                                         5
+#define regGDC1_NGDC_PG_MISC_CTRL                                                                       0x2ffc0f18
+#define regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX                                                              5
+#define regGDC1_NGDC_PGMST_CTRL                                                                         0x2ffc0f19
+#define regGDC1_NGDC_PGMST_CTRL_BASE_IDX                                                                5
+#define regGDC1_NGDC_PGSLV_CTRL                                                                         0x2ffc0f1a
+#define regGDC1_NGDC_PGSLV_CTRL_BASE_IDX                                                                5
+#define regGDC1_SHUBCLK_DPM_CTRL                                                                        0x2ffc0f1b
+#define regGDC1_SHUBCLK_DPM_CTRL_BASE_IDX                                                               5
+#define regGDC1_SHUBCLK_DPM_WR_WEIGHT                                                                   0x2ffc0f1c
+#define regGDC1_SHUBCLK_DPM_WR_WEIGHT_BASE_IDX                                                          5
+#define regGDC1_SHUBCLK_DPM_RD_WEIGHT                                                                   0x2ffc0f1d
+#define regGDC1_SHUBCLK_DPM_RD_WEIGHT_BASE_IDX                                                          5
+#define regGDC1_SHUBCLK_DPM_WR_CNT                                                                      0x2ffc0f1e
+#define regGDC1_SHUBCLK_DPM_WR_CNT_BASE_IDX                                                             5
+#define regGDC1_SHUBCLK_DPM_RD_CNT                                                                      0x2ffc0f1f
+#define regGDC1_SHUBCLK_DPM_RD_CNT_BASE_IDX                                                             5
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
+// base address: 0xd0000000
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO                                                        0x2ffd0800
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_1                                                      0x2ffd0800
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_2                                                      0x2ffd0800
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI                                                        0x2ffd0801
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_1                                                      0x2ffd0801
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_2                                                      0x2ffd0801
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA                                                       0x2ffd0802
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                              5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_1                                                     0x2ffd0802
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_1_BASE_IDX                                            5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_2                                                     0x2ffd0802
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_2_BASE_IDX                                            5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL                                                        0x2ffd0803
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_1                                                      0x2ffd0803
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_2                                                      0x2ffd0803
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO                                                        0x2ffd0804
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_1                                                      0x2ffd0804
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_2                                                      0x2ffd0804
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI                                                        0x2ffd0805
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_1                                                      0x2ffd0805
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_2                                                      0x2ffd0805
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA                                                       0x2ffd0806
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                              5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_1                                                     0x2ffd0806
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_1_BASE_IDX                                            5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_2                                                     0x2ffd0806
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_2_BASE_IDX                                            5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL                                                        0x2ffd0807
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_1                                                      0x2ffd0807
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_2                                                      0x2ffd0807
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO                                                        0x2ffd0808
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_1                                                      0x2ffd0808
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_2                                                      0x2ffd0808
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI                                                        0x2ffd0809
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_1                                                      0x2ffd0809
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_2                                                      0x2ffd0809
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA                                                       0x2ffd080a
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                              5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_1                                                     0x2ffd080a
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_1_BASE_IDX                                            5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_2                                                     0x2ffd080a
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_2_BASE_IDX                                            5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL                                                        0x2ffd080b
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_1                                                      0x2ffd080b
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_2                                                      0x2ffd080b
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO                                                        0x2ffd080c
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_1                                                      0x2ffd080c
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_2                                                      0x2ffd080c
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI                                                        0x2ffd080d
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_1                                                      0x2ffd080d
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_2                                                      0x2ffd080d
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA                                                       0x2ffd080e
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                              5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_1                                                     0x2ffd080e
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_1_BASE_IDX                                            5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_2                                                     0x2ffd080e
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_2_BASE_IDX                                            5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL                                                        0x2ffd080f
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_BASE_IDX                                               5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_1                                                      0x2ffd080f
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_1_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_2                                                      0x2ffd080f
+#define regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_2_BASE_IDX                                             5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_PBA                                                                  0x2ffd0c00
+#define regRCC_DEV0_EPF0_1_GFXMSIX_PBA_BASE_IDX                                                         5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_PBA_1                                                                0x2ffd0c00
+#define regRCC_DEV0_EPF0_1_GFXMSIX_PBA_1_BASE_IDX                                                       5
+#define regRCC_DEV0_EPF0_1_GFXMSIX_PBA_2                                                                0x2ffd0c00
+#define regRCC_DEV0_EPF0_1_GFXMSIX_PBA_2_BASE_IDX                                                       5
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+// base address: 0xfffe00009000
+#define regBIFPLR0_1_VENDOR_ID                                                                          0x3fff7bfc2400
+#define regBIFPLR0_1_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR0_1_DEVICE_ID                                                                          0x3fff7bfc2400
+#define regBIFPLR0_1_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR0_1_COMMAND                                                                            0x3fff7bfc2401
+#define regBIFPLR0_1_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR0_1_STATUS                                                                             0x3fff7bfc2401
+#define regBIFPLR0_1_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR0_1_REVISION_ID                                                                        0x3fff7bfc2402
+#define regBIFPLR0_1_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR0_1_PROG_INTERFACE                                                                     0x3fff7bfc2402
+#define regBIFPLR0_1_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR0_1_SUB_CLASS                                                                          0x3fff7bfc2402
+#define regBIFPLR0_1_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR0_1_BASE_CLASS                                                                         0x3fff7bfc2402
+#define regBIFPLR0_1_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR0_1_CACHE_LINE                                                                         0x3fff7bfc2403
+#define regBIFPLR0_1_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR0_1_LATENCY                                                                            0x3fff7bfc2403
+#define regBIFPLR0_1_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR0_1_HEADER                                                                             0x3fff7bfc2403
+#define regBIFPLR0_1_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR0_1_BIST                                                                               0x3fff7bfc2403
+#define regBIFPLR0_1_BIST_BASE_IDX                                                                      5
+#define regBIFPLR0_1_SUB_BUS_NUMBER_LATENCY                                                             0x3fff7bfc2406
+#define regBIFPLR0_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR0_1_IO_BASE_LIMIT                                                                      0x3fff7bfc2407
+#define regBIFPLR0_1_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR0_1_SECONDARY_STATUS                                                                   0x3fff7bfc2407
+#define regBIFPLR0_1_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR0_1_MEM_BASE_LIMIT                                                                     0x3fff7bfc2408
+#define regBIFPLR0_1_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR0_1_PREF_BASE_LIMIT                                                                    0x3fff7bfc2409
+#define regBIFPLR0_1_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR0_1_PREF_BASE_UPPER                                                                    0x3fff7bfc240a
+#define regBIFPLR0_1_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR0_1_PREF_LIMIT_UPPER                                                                   0x3fff7bfc240b
+#define regBIFPLR0_1_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR0_1_IO_BASE_LIMIT_HI                                                                   0x3fff7bfc240c
+#define regBIFPLR0_1_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR0_1_CAP_PTR                                                                            0x3fff7bfc240d
+#define regBIFPLR0_1_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR0_1_ROM_BASE_ADDR                                                                      0x3fff7bfc240e
+#define regBIFPLR0_1_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR0_1_INTERRUPT_LINE                                                                     0x3fff7bfc240f
+#define regBIFPLR0_1_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR0_1_INTERRUPT_PIN                                                                      0x3fff7bfc240f
+#define regBIFPLR0_1_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR0_1_IRQ_BRIDGE_CNTL                                                                    0x3fff7bfc240f
+#define regBIFPLR0_1_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR0_1_EXT_BRIDGE_CNTL                                                                    0x3fff7bfc2410
+#define regBIFPLR0_1_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR0_1_VENDOR_CAP_LIST                                                                    0x3fff7bfc2412
+#define regBIFPLR0_1_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR0_1_ADAPTER_ID_W                                                                       0x3fff7bfc2413
+#define regBIFPLR0_1_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR0_1_PMI_CAP_LIST                                                                       0x3fff7bfc2414
+#define regBIFPLR0_1_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR0_1_PMI_CAP                                                                            0x3fff7bfc2414
+#define regBIFPLR0_1_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR0_1_PMI_STATUS_CNTL                                                                    0x3fff7bfc2415
+#define regBIFPLR0_1_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR0_1_PCIE_CAP_LIST                                                                      0x3fff7bfc2416
+#define regBIFPLR0_1_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR0_1_PCIE_CAP                                                                           0x3fff7bfc2416
+#define regBIFPLR0_1_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR0_1_DEVICE_CAP                                                                         0x3fff7bfc2417
+#define regBIFPLR0_1_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR0_1_DEVICE_CNTL                                                                        0x3fff7bfc2418
+#define regBIFPLR0_1_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR0_1_DEVICE_STATUS                                                                      0x3fff7bfc2418
+#define regBIFPLR0_1_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR0_1_LINK_CAP                                                                           0x3fff7bfc2419
+#define regBIFPLR0_1_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR0_1_LINK_CNTL                                                                          0x3fff7bfc241a
+#define regBIFPLR0_1_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR0_1_LINK_STATUS                                                                        0x3fff7bfc241a
+#define regBIFPLR0_1_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR0_1_SLOT_CAP                                                                           0x3fff7bfc241b
+#define regBIFPLR0_1_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR0_1_SLOT_CNTL                                                                          0x3fff7bfc241c
+#define regBIFPLR0_1_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR0_1_SLOT_STATUS                                                                        0x3fff7bfc241c
+#define regBIFPLR0_1_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR0_1_ROOT_CNTL                                                                          0x3fff7bfc241d
+#define regBIFPLR0_1_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR0_1_ROOT_CAP                                                                           0x3fff7bfc241d
+#define regBIFPLR0_1_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR0_1_ROOT_STATUS                                                                        0x3fff7bfc241e
+#define regBIFPLR0_1_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR0_1_DEVICE_CAP2                                                                        0x3fff7bfc241f
+#define regBIFPLR0_1_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR0_1_DEVICE_CNTL2                                                                       0x3fff7bfc2420
+#define regBIFPLR0_1_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR0_1_DEVICE_STATUS2                                                                     0x3fff7bfc2420
+#define regBIFPLR0_1_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR0_1_LINK_CAP2                                                                          0x3fff7bfc2421
+#define regBIFPLR0_1_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR0_1_LINK_CNTL2                                                                         0x3fff7bfc2422
+#define regBIFPLR0_1_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR0_1_LINK_STATUS2                                                                       0x3fff7bfc2422
+#define regBIFPLR0_1_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR0_1_SLOT_CAP2                                                                          0x3fff7bfc2423
+#define regBIFPLR0_1_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR0_1_SLOT_CNTL2                                                                         0x3fff7bfc2424
+#define regBIFPLR0_1_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR0_1_SLOT_STATUS2                                                                       0x3fff7bfc2424
+#define regBIFPLR0_1_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR0_1_MSI_CAP_LIST                                                                       0x3fff7bfc2428
+#define regBIFPLR0_1_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR0_1_MSI_MSG_CNTL                                                                       0x3fff7bfc2428
+#define regBIFPLR0_1_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR0_1_MSI_MSG_ADDR_LO                                                                    0x3fff7bfc2429
+#define regBIFPLR0_1_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR0_1_MSI_MSG_ADDR_HI                                                                    0x3fff7bfc242a
+#define regBIFPLR0_1_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR0_1_MSI_MSG_DATA                                                                       0x3fff7bfc242a
+#define regBIFPLR0_1_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR0_1_MSI_MSG_DATA_64                                                                    0x3fff7bfc242b
+#define regBIFPLR0_1_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR0_1_SSID_CAP_LIST                                                                      0x3fff7bfc2430
+#define regBIFPLR0_1_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR0_1_SSID_CAP                                                                           0x3fff7bfc2431
+#define regBIFPLR0_1_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR0_1_MSI_MAP_CAP_LIST                                                                   0x3fff7bfc2432
+#define regBIFPLR0_1_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR0_1_MSI_MAP_CAP                                                                        0x3fff7bfc2432
+#define regBIFPLR0_1_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x3fff7bfc2440
+#define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR                                                           0x3fff7bfc2441
+#define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC1                                                              0x3fff7bfc2442
+#define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC2                                                              0x3fff7bfc2443
+#define regBIFPLR0_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR0_1_PCIE_VC_ENH_CAP_LIST                                                               0x3fff7bfc2444
+#define regBIFPLR0_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_PORT_VC_CAP_REG1                                                              0x3fff7bfc2445
+#define regBIFPLR0_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR0_1_PCIE_PORT_VC_CAP_REG2                                                              0x3fff7bfc2446
+#define regBIFPLR0_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR0_1_PCIE_PORT_VC_CNTL                                                                  0x3fff7bfc2447
+#define regBIFPLR0_1_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR0_1_PCIE_PORT_VC_STATUS                                                                0x3fff7bfc2447
+#define regBIFPLR0_1_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR0_1_PCIE_VC0_RESOURCE_CAP                                                              0x3fff7bfc2448
+#define regBIFPLR0_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR0_1_PCIE_VC0_RESOURCE_CNTL                                                             0x3fff7bfc2449
+#define regBIFPLR0_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR0_1_PCIE_VC0_RESOURCE_STATUS                                                           0x3fff7bfc244a
+#define regBIFPLR0_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR0_1_PCIE_VC1_RESOURCE_CAP                                                              0x3fff7bfc244b
+#define regBIFPLR0_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR0_1_PCIE_VC1_RESOURCE_CNTL                                                             0x3fff7bfc244c
+#define regBIFPLR0_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR0_1_PCIE_VC1_RESOURCE_STATUS                                                           0x3fff7bfc244d
+#define regBIFPLR0_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x3fff7bfc2450
+#define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1                                                            0x3fff7bfc2451
+#define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2                                                            0x3fff7bfc2452
+#define regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x3fff7bfc2454
+#define regBIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_UNCORR_ERR_STATUS                                                             0x3fff7bfc2455
+#define regBIFPLR0_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR0_1_PCIE_UNCORR_ERR_MASK                                                               0x3fff7bfc2456
+#define regBIFPLR0_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY                                                           0x3fff7bfc2457
+#define regBIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR0_1_PCIE_CORR_ERR_STATUS                                                               0x3fff7bfc2458
+#define regBIFPLR0_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_CORR_ERR_MASK                                                                 0x3fff7bfc2459
+#define regBIFPLR0_1_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL                                                              0x3fff7bfc245a
+#define regBIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR0_1_PCIE_HDR_LOG0                                                                      0x3fff7bfc245b
+#define regBIFPLR0_1_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR0_1_PCIE_HDR_LOG1                                                                      0x3fff7bfc245c
+#define regBIFPLR0_1_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR0_1_PCIE_HDR_LOG2                                                                      0x3fff7bfc245d
+#define regBIFPLR0_1_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR0_1_PCIE_HDR_LOG3                                                                      0x3fff7bfc245e
+#define regBIFPLR0_1_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR0_1_PCIE_ROOT_ERR_CMD                                                                  0x3fff7bfc245f
+#define regBIFPLR0_1_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR0_1_PCIE_ROOT_ERR_STATUS                                                               0x3fff7bfc2460
+#define regBIFPLR0_1_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_ERR_SRC_ID                                                                    0x3fff7bfc2461
+#define regBIFPLR0_1_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG0                                                               0x3fff7bfc2462
+#define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG1                                                               0x3fff7bfc2463
+#define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG2                                                               0x3fff7bfc2464
+#define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG3                                                               0x3fff7bfc2465
+#define regBIFPLR0_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x3fff7bfc249c
+#define regBIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR0_1_PCIE_LINK_CNTL3                                                                    0x3fff7bfc249d
+#define regBIFPLR0_1_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR0_1_PCIE_LANE_ERROR_STATUS                                                             0x3fff7bfc249e
+#define regBIFPLR0_1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x3fff7bfc249f
+#define regBIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x3fff7bfc249f
+#define regBIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x3fff7bfc24a0
+#define regBIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x3fff7bfc24a0
+#define regBIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x3fff7bfc24a1
+#define regBIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x3fff7bfc24a1
+#define regBIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x3fff7bfc24a2
+#define regBIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x3fff7bfc24a2
+#define regBIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x3fff7bfc24a3
+#define regBIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x3fff7bfc24a3
+#define regBIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x3fff7bfc24a4
+#define regBIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x3fff7bfc24a4
+#define regBIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x3fff7bfc24a5
+#define regBIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x3fff7bfc24a5
+#define regBIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x3fff7bfc24a6
+#define regBIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x3fff7bfc24a6
+#define regBIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR0_1_PCIE_ACS_ENH_CAP_LIST                                                              0x3fff7bfc24a8
+#define regBIFPLR0_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR0_1_PCIE_ACS_CAP                                                                       0x3fff7bfc24a9
+#define regBIFPLR0_1_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR0_1_PCIE_ACS_CNTL                                                                      0x3fff7bfc24a9
+#define regBIFPLR0_1_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR0_1_PCIE_MC_ENH_CAP_LIST                                                               0x3fff7bfc24bc
+#define regBIFPLR0_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_MC_CAP                                                                        0x3fff7bfc24bd
+#define regBIFPLR0_1_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR0_1_PCIE_MC_CNTL                                                                       0x3fff7bfc24bd
+#define regBIFPLR0_1_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR0_1_PCIE_MC_ADDR0                                                                      0x3fff7bfc24be
+#define regBIFPLR0_1_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR0_1_PCIE_MC_ADDR1                                                                      0x3fff7bfc24bf
+#define regBIFPLR0_1_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR0_1_PCIE_MC_RCV0                                                                       0x3fff7bfc24c0
+#define regBIFPLR0_1_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR0_1_PCIE_MC_RCV1                                                                       0x3fff7bfc24c1
+#define regBIFPLR0_1_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR0_1_PCIE_MC_BLOCK_ALL0                                                                 0x3fff7bfc24c2
+#define regBIFPLR0_1_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR0_1_PCIE_MC_BLOCK_ALL1                                                                 0x3fff7bfc24c3
+#define regBIFPLR0_1_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x3fff7bfc24c4
+#define regBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x3fff7bfc24c5
+#define regBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR0_1_PCIE_MC_OVERLAY_BAR0                                                               0x3fff7bfc24c6
+#define regBIFPLR0_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_MC_OVERLAY_BAR1                                                               0x3fff7bfc24c7
+#define regBIFPLR0_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST                                                            0x3fff7bfc24dc
+#define regBIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR0_1_PCIE_L1_PM_SUB_CAP                                                                 0x3fff7bfc24dd
+#define regBIFPLR0_1_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR0_1_PCIE_L1_PM_SUB_CNTL                                                                0x3fff7bfc24de
+#define regBIFPLR0_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR0_1_PCIE_L1_PM_SUB_CNTL2                                                               0x3fff7bfc24df
+#define regBIFPLR0_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_DPC_ENH_CAP_LIST                                                              0x3fff7bfc24e0
+#define regBIFPLR0_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR0_1_PCIE_DPC_CAP_LIST                                                                  0x3fff7bfc24e1
+#define regBIFPLR0_1_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR0_1_PCIE_DPC_CNTL                                                                      0x3fff7bfc24e1
+#define regBIFPLR0_1_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR0_1_PCIE_DPC_STATUS                                                                    0x3fff7bfc24e2
+#define regBIFPLR0_1_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID                                                           0x3fff7bfc24e2
+#define regBIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR0_1_PCIE_RP_PIO_STATUS                                                                 0x3fff7bfc24e3
+#define regBIFPLR0_1_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR0_1_PCIE_RP_PIO_MASK                                                                   0x3fff7bfc24e4
+#define regBIFPLR0_1_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR0_1_PCIE_RP_PIO_SEVERITY                                                               0x3fff7bfc24e5
+#define regBIFPLR0_1_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_RP_PIO_SYSERROR                                                               0x3fff7bfc24e6
+#define regBIFPLR0_1_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_RP_PIO_EXCEPTION                                                              0x3fff7bfc24e7
+#define regBIFPLR0_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG0                                                               0x3fff7bfc24e8
+#define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG1                                                               0x3fff7bfc24e9
+#define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG2                                                               0x3fff7bfc24ea
+#define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG3                                                               0x3fff7bfc24eb
+#define regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0                                                            0x3fff7bfc24ed
+#define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1                                                            0x3fff7bfc24ee
+#define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2                                                            0x3fff7bfc24ef
+#define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3                                                            0x3fff7bfc24f0
+#define regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR0_1_PCIE_ESM_CAP_LIST                                                                  0x3fff7bfc24f1
+#define regBIFPLR0_1_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR0_1_PCIE_ESM_HEADER_1                                                                  0x3fff7bfc24f2
+#define regBIFPLR0_1_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR0_1_PCIE_ESM_HEADER_2                                                                  0x3fff7bfc24f3
+#define regBIFPLR0_1_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR0_1_PCIE_ESM_STATUS                                                                    0x3fff7bfc24f3
+#define regBIFPLR0_1_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR0_1_PCIE_ESM_CTRL                                                                      0x3fff7bfc24f4
+#define regBIFPLR0_1_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR0_1_PCIE_ESM_CAP_1                                                                     0x3fff7bfc24f5
+#define regBIFPLR0_1_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR0_1_PCIE_ESM_CAP_2                                                                     0x3fff7bfc24f6
+#define regBIFPLR0_1_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR0_1_PCIE_ESM_CAP_3                                                                     0x3fff7bfc24f7
+#define regBIFPLR0_1_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR0_1_PCIE_ESM_CAP_4                                                                     0x3fff7bfc24f8
+#define regBIFPLR0_1_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR0_1_PCIE_ESM_CAP_5                                                                     0x3fff7bfc24f9
+#define regBIFPLR0_1_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR0_1_PCIE_ESM_CAP_6                                                                     0x3fff7bfc24fa
+#define regBIFPLR0_1_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR0_1_PCIE_ESM_CAP_7                                                                     0x3fff7bfc24fb
+#define regBIFPLR0_1_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR0_1_PCIE_DLF_ENH_CAP_LIST                                                              0x3fff7bfc2500
+#define regBIFPLR0_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR0_1_DATA_LINK_FEATURE_CAP                                                              0x3fff7bfc2501
+#define regBIFPLR0_1_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR0_1_DATA_LINK_FEATURE_STATUS                                                           0x3fff7bfc2502
+#define regBIFPLR0_1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x3fff7bfc2504
+#define regBIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR0_1_LINK_CAP_16GT                                                                      0x3fff7bfc2505
+#define regBIFPLR0_1_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR0_1_LINK_CNTL_16GT                                                                     0x3fff7bfc2506
+#define regBIFPLR0_1_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR0_1_LINK_STATUS_16GT                                                                   0x3fff7bfc2507
+#define regBIFPLR0_1_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x3fff7bfc2508
+#define regBIFPLR0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR0_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc2509
+#define regBIFPLR0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR0_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc250a
+#define regBIFPLR0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc250c
+#define regBIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc250c
+#define regBIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc250c
+#define regBIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc250c
+#define regBIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc250d
+#define regBIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc250d
+#define regBIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc250d
+#define regBIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc250d
+#define regBIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc250e
+#define regBIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc250e
+#define regBIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc250e
+#define regBIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc250e
+#define regBIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc250f
+#define regBIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc250f
+#define regBIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc250f
+#define regBIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc250f
+#define regBIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST                                                        0x3fff7bfc2510
+#define regBIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR0_1_MARGINING_PORT_CAP                                                                 0x3fff7bfc2511
+#define regBIFPLR0_1_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR0_1_MARGINING_PORT_STATUS                                                              0x3fff7bfc2511
+#define regBIFPLR0_1_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR0_1_LANE_0_MARGINING_LANE_CNTL                                                         0x3fff7bfc2512
+#define regBIFPLR0_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_1_LANE_0_MARGINING_LANE_STATUS                                                       0x3fff7bfc2512
+#define regBIFPLR0_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_1_LANE_1_MARGINING_LANE_CNTL                                                         0x3fff7bfc2513
+#define regBIFPLR0_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_1_LANE_1_MARGINING_LANE_STATUS                                                       0x3fff7bfc2513
+#define regBIFPLR0_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_1_LANE_2_MARGINING_LANE_CNTL                                                         0x3fff7bfc2514
+#define regBIFPLR0_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_1_LANE_2_MARGINING_LANE_STATUS                                                       0x3fff7bfc2514
+#define regBIFPLR0_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_1_LANE_3_MARGINING_LANE_CNTL                                                         0x3fff7bfc2515
+#define regBIFPLR0_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_1_LANE_3_MARGINING_LANE_STATUS                                                       0x3fff7bfc2515
+#define regBIFPLR0_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_1_LANE_4_MARGINING_LANE_CNTL                                                         0x3fff7bfc2516
+#define regBIFPLR0_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_1_LANE_4_MARGINING_LANE_STATUS                                                       0x3fff7bfc2516
+#define regBIFPLR0_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_1_LANE_5_MARGINING_LANE_CNTL                                                         0x3fff7bfc2517
+#define regBIFPLR0_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_1_LANE_5_MARGINING_LANE_STATUS                                                       0x3fff7bfc2517
+#define regBIFPLR0_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_1_LANE_6_MARGINING_LANE_CNTL                                                         0x3fff7bfc2518
+#define regBIFPLR0_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_1_LANE_6_MARGINING_LANE_STATUS                                                       0x3fff7bfc2518
+#define regBIFPLR0_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_1_LANE_7_MARGINING_LANE_CNTL                                                         0x3fff7bfc2519
+#define regBIFPLR0_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_1_LANE_7_MARGINING_LANE_STATUS                                                       0x3fff7bfc2519
+#define regBIFPLR0_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_1_LANE_8_MARGINING_LANE_CNTL                                                         0x3fff7bfc251a
+#define regBIFPLR0_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_1_LANE_8_MARGINING_LANE_STATUS                                                       0x3fff7bfc251a
+#define regBIFPLR0_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_1_LANE_9_MARGINING_LANE_CNTL                                                         0x3fff7bfc251b
+#define regBIFPLR0_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR0_1_LANE_9_MARGINING_LANE_STATUS                                                       0x3fff7bfc251b
+#define regBIFPLR0_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR0_1_LANE_10_MARGINING_LANE_CNTL                                                        0x3fff7bfc251c
+#define regBIFPLR0_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_1_LANE_10_MARGINING_LANE_STATUS                                                      0x3fff7bfc251c
+#define regBIFPLR0_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_11_MARGINING_LANE_CNTL                                                        0x3fff7bfc251d
+#define regBIFPLR0_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_1_LANE_11_MARGINING_LANE_STATUS                                                      0x3fff7bfc251d
+#define regBIFPLR0_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_12_MARGINING_LANE_CNTL                                                        0x3fff7bfc251e
+#define regBIFPLR0_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_1_LANE_12_MARGINING_LANE_STATUS                                                      0x3fff7bfc251e
+#define regBIFPLR0_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_13_MARGINING_LANE_CNTL                                                        0x3fff7bfc251f
+#define regBIFPLR0_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_1_LANE_13_MARGINING_LANE_STATUS                                                      0x3fff7bfc251f
+#define regBIFPLR0_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_14_MARGINING_LANE_CNTL                                                        0x3fff7bfc2520
+#define regBIFPLR0_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_1_LANE_14_MARGINING_LANE_STATUS                                                      0x3fff7bfc2520
+#define regBIFPLR0_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_1_LANE_15_MARGINING_LANE_CNTL                                                        0x3fff7bfc2521
+#define regBIFPLR0_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR0_1_LANE_15_MARGINING_LANE_STATUS                                                      0x3fff7bfc2521
+#define regBIFPLR0_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR0_1_PCIE_CCIX_CAP_LIST                                                                 0x3fff7bfc2522
+#define regBIFPLR0_1_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR0_1_PCIE_CCIX_HEADER_1                                                                 0x3fff7bfc2523
+#define regBIFPLR0_1_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR0_1_PCIE_CCIX_HEADER_2                                                                 0x3fff7bfc2524
+#define regBIFPLR0_1_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR0_1_PCIE_CCIX_CAP                                                                      0x3fff7bfc2524
+#define regBIFPLR0_1_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP                                                             0x3fff7bfc2525
+#define regBIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR0_1_PCIE_CCIX_ESM_OPTL_CAP                                                             0x3fff7bfc2526
+#define regBIFPLR0_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR0_1_PCIE_CCIX_ESM_STATUS                                                               0x3fff7bfc2527
+#define regBIFPLR0_1_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR0_1_PCIE_CCIX_ESM_CNTL                                                                 0x3fff7bfc2528
+#define regBIFPLR0_1_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2529
+#define regBIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2529
+#define regBIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2529
+#define regBIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2529
+#define regBIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc252a
+#define regBIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc252a
+#define regBIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc252a
+#define regBIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc252a
+#define regBIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc252b
+#define regBIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc252b
+#define regBIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc252b
+#define regBIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc252b
+#define regBIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc252c
+#define regBIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc252c
+#define regBIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc252c
+#define regBIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc252c
+#define regBIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc252d
+#define regBIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc252d
+#define regBIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc252d
+#define regBIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc252d
+#define regBIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc252e
+#define regBIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc252e
+#define regBIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc252e
+#define regBIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc252e
+#define regBIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc252f
+#define regBIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc252f
+#define regBIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc252f
+#define regBIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc252f
+#define regBIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2530
+#define regBIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2530
+#define regBIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2530
+#define regBIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2530
+#define regBIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR0_1_PCIE_CCIX_TRANS_CAP                                                                0x3fff7bfc2531
+#define regBIFPLR0_1_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR0_1_PCIE_CCIX_TRANS_CNTL                                                               0x3fff7bfc2532
+#define regBIFPLR0_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+// base address: 0xfffe0000a000
+#define regBIFPLR1_1_VENDOR_ID                                                                          0x3fff7bfc2800
+#define regBIFPLR1_1_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR1_1_DEVICE_ID                                                                          0x3fff7bfc2800
+#define regBIFPLR1_1_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR1_1_COMMAND                                                                            0x3fff7bfc2801
+#define regBIFPLR1_1_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR1_1_STATUS                                                                             0x3fff7bfc2801
+#define regBIFPLR1_1_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR1_1_REVISION_ID                                                                        0x3fff7bfc2802
+#define regBIFPLR1_1_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR1_1_PROG_INTERFACE                                                                     0x3fff7bfc2802
+#define regBIFPLR1_1_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR1_1_SUB_CLASS                                                                          0x3fff7bfc2802
+#define regBIFPLR1_1_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR1_1_BASE_CLASS                                                                         0x3fff7bfc2802
+#define regBIFPLR1_1_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR1_1_CACHE_LINE                                                                         0x3fff7bfc2803
+#define regBIFPLR1_1_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR1_1_LATENCY                                                                            0x3fff7bfc2803
+#define regBIFPLR1_1_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR1_1_HEADER                                                                             0x3fff7bfc2803
+#define regBIFPLR1_1_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR1_1_BIST                                                                               0x3fff7bfc2803
+#define regBIFPLR1_1_BIST_BASE_IDX                                                                      5
+#define regBIFPLR1_1_SUB_BUS_NUMBER_LATENCY                                                             0x3fff7bfc2806
+#define regBIFPLR1_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR1_1_IO_BASE_LIMIT                                                                      0x3fff7bfc2807
+#define regBIFPLR1_1_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR1_1_SECONDARY_STATUS                                                                   0x3fff7bfc2807
+#define regBIFPLR1_1_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR1_1_MEM_BASE_LIMIT                                                                     0x3fff7bfc2808
+#define regBIFPLR1_1_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR1_1_PREF_BASE_LIMIT                                                                    0x3fff7bfc2809
+#define regBIFPLR1_1_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR1_1_PREF_BASE_UPPER                                                                    0x3fff7bfc280a
+#define regBIFPLR1_1_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR1_1_PREF_LIMIT_UPPER                                                                   0x3fff7bfc280b
+#define regBIFPLR1_1_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR1_1_IO_BASE_LIMIT_HI                                                                   0x3fff7bfc280c
+#define regBIFPLR1_1_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR1_1_CAP_PTR                                                                            0x3fff7bfc280d
+#define regBIFPLR1_1_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR1_1_ROM_BASE_ADDR                                                                      0x3fff7bfc280e
+#define regBIFPLR1_1_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR1_1_INTERRUPT_LINE                                                                     0x3fff7bfc280f
+#define regBIFPLR1_1_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR1_1_INTERRUPT_PIN                                                                      0x3fff7bfc280f
+#define regBIFPLR1_1_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR1_1_IRQ_BRIDGE_CNTL                                                                    0x3fff7bfc280f
+#define regBIFPLR1_1_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR1_1_EXT_BRIDGE_CNTL                                                                    0x3fff7bfc2810
+#define regBIFPLR1_1_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR1_1_VENDOR_CAP_LIST                                                                    0x3fff7bfc2812
+#define regBIFPLR1_1_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR1_1_ADAPTER_ID_W                                                                       0x3fff7bfc2813
+#define regBIFPLR1_1_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR1_1_PMI_CAP_LIST                                                                       0x3fff7bfc2814
+#define regBIFPLR1_1_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR1_1_PMI_CAP                                                                            0x3fff7bfc2814
+#define regBIFPLR1_1_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR1_1_PMI_STATUS_CNTL                                                                    0x3fff7bfc2815
+#define regBIFPLR1_1_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR1_1_PCIE_CAP_LIST                                                                      0x3fff7bfc2816
+#define regBIFPLR1_1_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR1_1_PCIE_CAP                                                                           0x3fff7bfc2816
+#define regBIFPLR1_1_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR1_1_DEVICE_CAP                                                                         0x3fff7bfc2817
+#define regBIFPLR1_1_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR1_1_DEVICE_CNTL                                                                        0x3fff7bfc2818
+#define regBIFPLR1_1_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR1_1_DEVICE_STATUS                                                                      0x3fff7bfc2818
+#define regBIFPLR1_1_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR1_1_LINK_CAP                                                                           0x3fff7bfc2819
+#define regBIFPLR1_1_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR1_1_LINK_CNTL                                                                          0x3fff7bfc281a
+#define regBIFPLR1_1_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR1_1_LINK_STATUS                                                                        0x3fff7bfc281a
+#define regBIFPLR1_1_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR1_1_SLOT_CAP                                                                           0x3fff7bfc281b
+#define regBIFPLR1_1_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR1_1_SLOT_CNTL                                                                          0x3fff7bfc281c
+#define regBIFPLR1_1_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR1_1_SLOT_STATUS                                                                        0x3fff7bfc281c
+#define regBIFPLR1_1_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR1_1_ROOT_CNTL                                                                          0x3fff7bfc281d
+#define regBIFPLR1_1_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR1_1_ROOT_CAP                                                                           0x3fff7bfc281d
+#define regBIFPLR1_1_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR1_1_ROOT_STATUS                                                                        0x3fff7bfc281e
+#define regBIFPLR1_1_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR1_1_DEVICE_CAP2                                                                        0x3fff7bfc281f
+#define regBIFPLR1_1_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR1_1_DEVICE_CNTL2                                                                       0x3fff7bfc2820
+#define regBIFPLR1_1_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR1_1_DEVICE_STATUS2                                                                     0x3fff7bfc2820
+#define regBIFPLR1_1_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR1_1_LINK_CAP2                                                                          0x3fff7bfc2821
+#define regBIFPLR1_1_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR1_1_LINK_CNTL2                                                                         0x3fff7bfc2822
+#define regBIFPLR1_1_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR1_1_LINK_STATUS2                                                                       0x3fff7bfc2822
+#define regBIFPLR1_1_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR1_1_SLOT_CAP2                                                                          0x3fff7bfc2823
+#define regBIFPLR1_1_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR1_1_SLOT_CNTL2                                                                         0x3fff7bfc2824
+#define regBIFPLR1_1_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR1_1_SLOT_STATUS2                                                                       0x3fff7bfc2824
+#define regBIFPLR1_1_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR1_1_MSI_CAP_LIST                                                                       0x3fff7bfc2828
+#define regBIFPLR1_1_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR1_1_MSI_MSG_CNTL                                                                       0x3fff7bfc2828
+#define regBIFPLR1_1_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR1_1_MSI_MSG_ADDR_LO                                                                    0x3fff7bfc2829
+#define regBIFPLR1_1_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR1_1_MSI_MSG_ADDR_HI                                                                    0x3fff7bfc282a
+#define regBIFPLR1_1_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR1_1_MSI_MSG_DATA                                                                       0x3fff7bfc282a
+#define regBIFPLR1_1_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR1_1_MSI_MSG_DATA_64                                                                    0x3fff7bfc282b
+#define regBIFPLR1_1_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR1_1_SSID_CAP_LIST                                                                      0x3fff7bfc2830
+#define regBIFPLR1_1_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR1_1_SSID_CAP                                                                           0x3fff7bfc2831
+#define regBIFPLR1_1_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR1_1_MSI_MAP_CAP_LIST                                                                   0x3fff7bfc2832
+#define regBIFPLR1_1_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR1_1_MSI_MAP_CAP                                                                        0x3fff7bfc2832
+#define regBIFPLR1_1_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x3fff7bfc2840
+#define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR                                                           0x3fff7bfc2841
+#define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC1                                                              0x3fff7bfc2842
+#define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC2                                                              0x3fff7bfc2843
+#define regBIFPLR1_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR1_1_PCIE_VC_ENH_CAP_LIST                                                               0x3fff7bfc2844
+#define regBIFPLR1_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_PORT_VC_CAP_REG1                                                              0x3fff7bfc2845
+#define regBIFPLR1_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR1_1_PCIE_PORT_VC_CAP_REG2                                                              0x3fff7bfc2846
+#define regBIFPLR1_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR1_1_PCIE_PORT_VC_CNTL                                                                  0x3fff7bfc2847
+#define regBIFPLR1_1_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR1_1_PCIE_PORT_VC_STATUS                                                                0x3fff7bfc2847
+#define regBIFPLR1_1_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR1_1_PCIE_VC0_RESOURCE_CAP                                                              0x3fff7bfc2848
+#define regBIFPLR1_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR1_1_PCIE_VC0_RESOURCE_CNTL                                                             0x3fff7bfc2849
+#define regBIFPLR1_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR1_1_PCIE_VC0_RESOURCE_STATUS                                                           0x3fff7bfc284a
+#define regBIFPLR1_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR1_1_PCIE_VC1_RESOURCE_CAP                                                              0x3fff7bfc284b
+#define regBIFPLR1_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR1_1_PCIE_VC1_RESOURCE_CNTL                                                             0x3fff7bfc284c
+#define regBIFPLR1_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR1_1_PCIE_VC1_RESOURCE_STATUS                                                           0x3fff7bfc284d
+#define regBIFPLR1_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x3fff7bfc2850
+#define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1                                                            0x3fff7bfc2851
+#define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2                                                            0x3fff7bfc2852
+#define regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x3fff7bfc2854
+#define regBIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_UNCORR_ERR_STATUS                                                             0x3fff7bfc2855
+#define regBIFPLR1_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR1_1_PCIE_UNCORR_ERR_MASK                                                               0x3fff7bfc2856
+#define regBIFPLR1_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY                                                           0x3fff7bfc2857
+#define regBIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR1_1_PCIE_CORR_ERR_STATUS                                                               0x3fff7bfc2858
+#define regBIFPLR1_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_CORR_ERR_MASK                                                                 0x3fff7bfc2859
+#define regBIFPLR1_1_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL                                                              0x3fff7bfc285a
+#define regBIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR1_1_PCIE_HDR_LOG0                                                                      0x3fff7bfc285b
+#define regBIFPLR1_1_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR1_1_PCIE_HDR_LOG1                                                                      0x3fff7bfc285c
+#define regBIFPLR1_1_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR1_1_PCIE_HDR_LOG2                                                                      0x3fff7bfc285d
+#define regBIFPLR1_1_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR1_1_PCIE_HDR_LOG3                                                                      0x3fff7bfc285e
+#define regBIFPLR1_1_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR1_1_PCIE_ROOT_ERR_CMD                                                                  0x3fff7bfc285f
+#define regBIFPLR1_1_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR1_1_PCIE_ROOT_ERR_STATUS                                                               0x3fff7bfc2860
+#define regBIFPLR1_1_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_ERR_SRC_ID                                                                    0x3fff7bfc2861
+#define regBIFPLR1_1_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG0                                                               0x3fff7bfc2862
+#define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG1                                                               0x3fff7bfc2863
+#define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG2                                                               0x3fff7bfc2864
+#define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG3                                                               0x3fff7bfc2865
+#define regBIFPLR1_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x3fff7bfc289c
+#define regBIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR1_1_PCIE_LINK_CNTL3                                                                    0x3fff7bfc289d
+#define regBIFPLR1_1_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR1_1_PCIE_LANE_ERROR_STATUS                                                             0x3fff7bfc289e
+#define regBIFPLR1_1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x3fff7bfc289f
+#define regBIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x3fff7bfc289f
+#define regBIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x3fff7bfc28a0
+#define regBIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x3fff7bfc28a0
+#define regBIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x3fff7bfc28a1
+#define regBIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x3fff7bfc28a1
+#define regBIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x3fff7bfc28a2
+#define regBIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x3fff7bfc28a2
+#define regBIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x3fff7bfc28a3
+#define regBIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x3fff7bfc28a3
+#define regBIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x3fff7bfc28a4
+#define regBIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x3fff7bfc28a4
+#define regBIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x3fff7bfc28a5
+#define regBIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x3fff7bfc28a5
+#define regBIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x3fff7bfc28a6
+#define regBIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x3fff7bfc28a6
+#define regBIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR1_1_PCIE_ACS_ENH_CAP_LIST                                                              0x3fff7bfc28a8
+#define regBIFPLR1_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR1_1_PCIE_ACS_CAP                                                                       0x3fff7bfc28a9
+#define regBIFPLR1_1_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR1_1_PCIE_ACS_CNTL                                                                      0x3fff7bfc28a9
+#define regBIFPLR1_1_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR1_1_PCIE_MC_ENH_CAP_LIST                                                               0x3fff7bfc28bc
+#define regBIFPLR1_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_MC_CAP                                                                        0x3fff7bfc28bd
+#define regBIFPLR1_1_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR1_1_PCIE_MC_CNTL                                                                       0x3fff7bfc28bd
+#define regBIFPLR1_1_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR1_1_PCIE_MC_ADDR0                                                                      0x3fff7bfc28be
+#define regBIFPLR1_1_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR1_1_PCIE_MC_ADDR1                                                                      0x3fff7bfc28bf
+#define regBIFPLR1_1_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR1_1_PCIE_MC_RCV0                                                                       0x3fff7bfc28c0
+#define regBIFPLR1_1_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR1_1_PCIE_MC_RCV1                                                                       0x3fff7bfc28c1
+#define regBIFPLR1_1_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR1_1_PCIE_MC_BLOCK_ALL0                                                                 0x3fff7bfc28c2
+#define regBIFPLR1_1_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR1_1_PCIE_MC_BLOCK_ALL1                                                                 0x3fff7bfc28c3
+#define regBIFPLR1_1_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x3fff7bfc28c4
+#define regBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x3fff7bfc28c5
+#define regBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR1_1_PCIE_MC_OVERLAY_BAR0                                                               0x3fff7bfc28c6
+#define regBIFPLR1_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_MC_OVERLAY_BAR1                                                               0x3fff7bfc28c7
+#define regBIFPLR1_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST                                                            0x3fff7bfc28dc
+#define regBIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR1_1_PCIE_L1_PM_SUB_CAP                                                                 0x3fff7bfc28dd
+#define regBIFPLR1_1_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR1_1_PCIE_L1_PM_SUB_CNTL                                                                0x3fff7bfc28de
+#define regBIFPLR1_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR1_1_PCIE_L1_PM_SUB_CNTL2                                                               0x3fff7bfc28df
+#define regBIFPLR1_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_DPC_ENH_CAP_LIST                                                              0x3fff7bfc28e0
+#define regBIFPLR1_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR1_1_PCIE_DPC_CAP_LIST                                                                  0x3fff7bfc28e1
+#define regBIFPLR1_1_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR1_1_PCIE_DPC_CNTL                                                                      0x3fff7bfc28e1
+#define regBIFPLR1_1_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR1_1_PCIE_DPC_STATUS                                                                    0x3fff7bfc28e2
+#define regBIFPLR1_1_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID                                                           0x3fff7bfc28e2
+#define regBIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR1_1_PCIE_RP_PIO_STATUS                                                                 0x3fff7bfc28e3
+#define regBIFPLR1_1_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR1_1_PCIE_RP_PIO_MASK                                                                   0x3fff7bfc28e4
+#define regBIFPLR1_1_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR1_1_PCIE_RP_PIO_SEVERITY                                                               0x3fff7bfc28e5
+#define regBIFPLR1_1_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_RP_PIO_SYSERROR                                                               0x3fff7bfc28e6
+#define regBIFPLR1_1_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_RP_PIO_EXCEPTION                                                              0x3fff7bfc28e7
+#define regBIFPLR1_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG0                                                               0x3fff7bfc28e8
+#define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG1                                                               0x3fff7bfc28e9
+#define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG2                                                               0x3fff7bfc28ea
+#define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG3                                                               0x3fff7bfc28eb
+#define regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0                                                            0x3fff7bfc28ed
+#define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1                                                            0x3fff7bfc28ee
+#define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2                                                            0x3fff7bfc28ef
+#define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3                                                            0x3fff7bfc28f0
+#define regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR1_1_PCIE_ESM_CAP_LIST                                                                  0x3fff7bfc28f1
+#define regBIFPLR1_1_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR1_1_PCIE_ESM_HEADER_1                                                                  0x3fff7bfc28f2
+#define regBIFPLR1_1_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR1_1_PCIE_ESM_HEADER_2                                                                  0x3fff7bfc28f3
+#define regBIFPLR1_1_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR1_1_PCIE_ESM_STATUS                                                                    0x3fff7bfc28f3
+#define regBIFPLR1_1_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR1_1_PCIE_ESM_CTRL                                                                      0x3fff7bfc28f4
+#define regBIFPLR1_1_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR1_1_PCIE_ESM_CAP_1                                                                     0x3fff7bfc28f5
+#define regBIFPLR1_1_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR1_1_PCIE_ESM_CAP_2                                                                     0x3fff7bfc28f6
+#define regBIFPLR1_1_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR1_1_PCIE_ESM_CAP_3                                                                     0x3fff7bfc28f7
+#define regBIFPLR1_1_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR1_1_PCIE_ESM_CAP_4                                                                     0x3fff7bfc28f8
+#define regBIFPLR1_1_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR1_1_PCIE_ESM_CAP_5                                                                     0x3fff7bfc28f9
+#define regBIFPLR1_1_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR1_1_PCIE_ESM_CAP_6                                                                     0x3fff7bfc28fa
+#define regBIFPLR1_1_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR1_1_PCIE_ESM_CAP_7                                                                     0x3fff7bfc28fb
+#define regBIFPLR1_1_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR1_1_PCIE_DLF_ENH_CAP_LIST                                                              0x3fff7bfc2900
+#define regBIFPLR1_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR1_1_DATA_LINK_FEATURE_CAP                                                              0x3fff7bfc2901
+#define regBIFPLR1_1_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR1_1_DATA_LINK_FEATURE_STATUS                                                           0x3fff7bfc2902
+#define regBIFPLR1_1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x3fff7bfc2904
+#define regBIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR1_1_LINK_CAP_16GT                                                                      0x3fff7bfc2905
+#define regBIFPLR1_1_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR1_1_LINK_CNTL_16GT                                                                     0x3fff7bfc2906
+#define regBIFPLR1_1_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR1_1_LINK_STATUS_16GT                                                                   0x3fff7bfc2907
+#define regBIFPLR1_1_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x3fff7bfc2908
+#define regBIFPLR1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR1_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc2909
+#define regBIFPLR1_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR1_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc290a
+#define regBIFPLR1_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc290c
+#define regBIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc290c
+#define regBIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc290c
+#define regBIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc290c
+#define regBIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc290d
+#define regBIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc290d
+#define regBIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc290d
+#define regBIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc290d
+#define regBIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc290e
+#define regBIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc290e
+#define regBIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc290e
+#define regBIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc290e
+#define regBIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc290f
+#define regBIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc290f
+#define regBIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc290f
+#define regBIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc290f
+#define regBIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST                                                        0x3fff7bfc2910
+#define regBIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR1_1_MARGINING_PORT_CAP                                                                 0x3fff7bfc2911
+#define regBIFPLR1_1_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR1_1_MARGINING_PORT_STATUS                                                              0x3fff7bfc2911
+#define regBIFPLR1_1_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR1_1_LANE_0_MARGINING_LANE_CNTL                                                         0x3fff7bfc2912
+#define regBIFPLR1_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_1_LANE_0_MARGINING_LANE_STATUS                                                       0x3fff7bfc2912
+#define regBIFPLR1_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_1_LANE_1_MARGINING_LANE_CNTL                                                         0x3fff7bfc2913
+#define regBIFPLR1_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_1_LANE_1_MARGINING_LANE_STATUS                                                       0x3fff7bfc2913
+#define regBIFPLR1_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_1_LANE_2_MARGINING_LANE_CNTL                                                         0x3fff7bfc2914
+#define regBIFPLR1_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_1_LANE_2_MARGINING_LANE_STATUS                                                       0x3fff7bfc2914
+#define regBIFPLR1_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_1_LANE_3_MARGINING_LANE_CNTL                                                         0x3fff7bfc2915
+#define regBIFPLR1_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_1_LANE_3_MARGINING_LANE_STATUS                                                       0x3fff7bfc2915
+#define regBIFPLR1_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_1_LANE_4_MARGINING_LANE_CNTL                                                         0x3fff7bfc2916
+#define regBIFPLR1_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_1_LANE_4_MARGINING_LANE_STATUS                                                       0x3fff7bfc2916
+#define regBIFPLR1_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_1_LANE_5_MARGINING_LANE_CNTL                                                         0x3fff7bfc2917
+#define regBIFPLR1_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_1_LANE_5_MARGINING_LANE_STATUS                                                       0x3fff7bfc2917
+#define regBIFPLR1_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_1_LANE_6_MARGINING_LANE_CNTL                                                         0x3fff7bfc2918
+#define regBIFPLR1_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_1_LANE_6_MARGINING_LANE_STATUS                                                       0x3fff7bfc2918
+#define regBIFPLR1_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_1_LANE_7_MARGINING_LANE_CNTL                                                         0x3fff7bfc2919
+#define regBIFPLR1_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_1_LANE_7_MARGINING_LANE_STATUS                                                       0x3fff7bfc2919
+#define regBIFPLR1_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_1_LANE_8_MARGINING_LANE_CNTL                                                         0x3fff7bfc291a
+#define regBIFPLR1_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_1_LANE_8_MARGINING_LANE_STATUS                                                       0x3fff7bfc291a
+#define regBIFPLR1_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_1_LANE_9_MARGINING_LANE_CNTL                                                         0x3fff7bfc291b
+#define regBIFPLR1_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR1_1_LANE_9_MARGINING_LANE_STATUS                                                       0x3fff7bfc291b
+#define regBIFPLR1_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR1_1_LANE_10_MARGINING_LANE_CNTL                                                        0x3fff7bfc291c
+#define regBIFPLR1_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_1_LANE_10_MARGINING_LANE_STATUS                                                      0x3fff7bfc291c
+#define regBIFPLR1_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_11_MARGINING_LANE_CNTL                                                        0x3fff7bfc291d
+#define regBIFPLR1_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_1_LANE_11_MARGINING_LANE_STATUS                                                      0x3fff7bfc291d
+#define regBIFPLR1_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_12_MARGINING_LANE_CNTL                                                        0x3fff7bfc291e
+#define regBIFPLR1_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_1_LANE_12_MARGINING_LANE_STATUS                                                      0x3fff7bfc291e
+#define regBIFPLR1_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_13_MARGINING_LANE_CNTL                                                        0x3fff7bfc291f
+#define regBIFPLR1_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_1_LANE_13_MARGINING_LANE_STATUS                                                      0x3fff7bfc291f
+#define regBIFPLR1_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_14_MARGINING_LANE_CNTL                                                        0x3fff7bfc2920
+#define regBIFPLR1_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_1_LANE_14_MARGINING_LANE_STATUS                                                      0x3fff7bfc2920
+#define regBIFPLR1_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_1_LANE_15_MARGINING_LANE_CNTL                                                        0x3fff7bfc2921
+#define regBIFPLR1_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR1_1_LANE_15_MARGINING_LANE_STATUS                                                      0x3fff7bfc2921
+#define regBIFPLR1_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR1_1_PCIE_CCIX_CAP_LIST                                                                 0x3fff7bfc2922
+#define regBIFPLR1_1_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR1_1_PCIE_CCIX_HEADER_1                                                                 0x3fff7bfc2923
+#define regBIFPLR1_1_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR1_1_PCIE_CCIX_HEADER_2                                                                 0x3fff7bfc2924
+#define regBIFPLR1_1_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR1_1_PCIE_CCIX_CAP                                                                      0x3fff7bfc2924
+#define regBIFPLR1_1_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP                                                             0x3fff7bfc2925
+#define regBIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR1_1_PCIE_CCIX_ESM_OPTL_CAP                                                             0x3fff7bfc2926
+#define regBIFPLR1_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR1_1_PCIE_CCIX_ESM_STATUS                                                               0x3fff7bfc2927
+#define regBIFPLR1_1_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR1_1_PCIE_CCIX_ESM_CNTL                                                                 0x3fff7bfc2928
+#define regBIFPLR1_1_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2929
+#define regBIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2929
+#define regBIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2929
+#define regBIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2929
+#define regBIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc292a
+#define regBIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc292a
+#define regBIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc292a
+#define regBIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc292a
+#define regBIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc292b
+#define regBIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc292b
+#define regBIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc292b
+#define regBIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc292b
+#define regBIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc292c
+#define regBIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc292c
+#define regBIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc292c
+#define regBIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc292c
+#define regBIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc292d
+#define regBIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc292d
+#define regBIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc292d
+#define regBIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc292d
+#define regBIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc292e
+#define regBIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc292e
+#define regBIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc292e
+#define regBIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc292e
+#define regBIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc292f
+#define regBIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc292f
+#define regBIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc292f
+#define regBIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc292f
+#define regBIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2930
+#define regBIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2930
+#define regBIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2930
+#define regBIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2930
+#define regBIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR1_1_PCIE_CCIX_TRANS_CAP                                                                0x3fff7bfc2931
+#define regBIFPLR1_1_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR1_1_PCIE_CCIX_TRANS_CNTL                                                               0x3fff7bfc2932
+#define regBIFPLR1_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+// base address: 0xfffe0000b000
+#define regBIFPLR2_1_VENDOR_ID                                                                          0x3fff7bfc2c00
+#define regBIFPLR2_1_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR2_1_DEVICE_ID                                                                          0x3fff7bfc2c00
+#define regBIFPLR2_1_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR2_1_COMMAND                                                                            0x3fff7bfc2c01
+#define regBIFPLR2_1_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR2_1_STATUS                                                                             0x3fff7bfc2c01
+#define regBIFPLR2_1_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR2_1_REVISION_ID                                                                        0x3fff7bfc2c02
+#define regBIFPLR2_1_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR2_1_PROG_INTERFACE                                                                     0x3fff7bfc2c02
+#define regBIFPLR2_1_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR2_1_SUB_CLASS                                                                          0x3fff7bfc2c02
+#define regBIFPLR2_1_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR2_1_BASE_CLASS                                                                         0x3fff7bfc2c02
+#define regBIFPLR2_1_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR2_1_CACHE_LINE                                                                         0x3fff7bfc2c03
+#define regBIFPLR2_1_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR2_1_LATENCY                                                                            0x3fff7bfc2c03
+#define regBIFPLR2_1_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR2_1_HEADER                                                                             0x3fff7bfc2c03
+#define regBIFPLR2_1_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR2_1_BIST                                                                               0x3fff7bfc2c03
+#define regBIFPLR2_1_BIST_BASE_IDX                                                                      5
+#define regBIFPLR2_1_SUB_BUS_NUMBER_LATENCY                                                             0x3fff7bfc2c06
+#define regBIFPLR2_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR2_1_IO_BASE_LIMIT                                                                      0x3fff7bfc2c07
+#define regBIFPLR2_1_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR2_1_SECONDARY_STATUS                                                                   0x3fff7bfc2c07
+#define regBIFPLR2_1_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR2_1_MEM_BASE_LIMIT                                                                     0x3fff7bfc2c08
+#define regBIFPLR2_1_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR2_1_PREF_BASE_LIMIT                                                                    0x3fff7bfc2c09
+#define regBIFPLR2_1_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR2_1_PREF_BASE_UPPER                                                                    0x3fff7bfc2c0a
+#define regBIFPLR2_1_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR2_1_PREF_LIMIT_UPPER                                                                   0x3fff7bfc2c0b
+#define regBIFPLR2_1_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR2_1_IO_BASE_LIMIT_HI                                                                   0x3fff7bfc2c0c
+#define regBIFPLR2_1_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR2_1_CAP_PTR                                                                            0x3fff7bfc2c0d
+#define regBIFPLR2_1_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR2_1_ROM_BASE_ADDR                                                                      0x3fff7bfc2c0e
+#define regBIFPLR2_1_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR2_1_INTERRUPT_LINE                                                                     0x3fff7bfc2c0f
+#define regBIFPLR2_1_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR2_1_INTERRUPT_PIN                                                                      0x3fff7bfc2c0f
+#define regBIFPLR2_1_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR2_1_IRQ_BRIDGE_CNTL                                                                    0x3fff7bfc2c0f
+#define regBIFPLR2_1_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR2_1_EXT_BRIDGE_CNTL                                                                    0x3fff7bfc2c10
+#define regBIFPLR2_1_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR2_1_VENDOR_CAP_LIST                                                                    0x3fff7bfc2c12
+#define regBIFPLR2_1_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR2_1_ADAPTER_ID_W                                                                       0x3fff7bfc2c13
+#define regBIFPLR2_1_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR2_1_PMI_CAP_LIST                                                                       0x3fff7bfc2c14
+#define regBIFPLR2_1_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR2_1_PMI_CAP                                                                            0x3fff7bfc2c14
+#define regBIFPLR2_1_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR2_1_PMI_STATUS_CNTL                                                                    0x3fff7bfc2c15
+#define regBIFPLR2_1_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR2_1_PCIE_CAP_LIST                                                                      0x3fff7bfc2c16
+#define regBIFPLR2_1_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR2_1_PCIE_CAP                                                                           0x3fff7bfc2c16
+#define regBIFPLR2_1_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR2_1_DEVICE_CAP                                                                         0x3fff7bfc2c17
+#define regBIFPLR2_1_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR2_1_DEVICE_CNTL                                                                        0x3fff7bfc2c18
+#define regBIFPLR2_1_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR2_1_DEVICE_STATUS                                                                      0x3fff7bfc2c18
+#define regBIFPLR2_1_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR2_1_LINK_CAP                                                                           0x3fff7bfc2c19
+#define regBIFPLR2_1_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR2_1_LINK_CNTL                                                                          0x3fff7bfc2c1a
+#define regBIFPLR2_1_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR2_1_LINK_STATUS                                                                        0x3fff7bfc2c1a
+#define regBIFPLR2_1_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR2_1_SLOT_CAP                                                                           0x3fff7bfc2c1b
+#define regBIFPLR2_1_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR2_1_SLOT_CNTL                                                                          0x3fff7bfc2c1c
+#define regBIFPLR2_1_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR2_1_SLOT_STATUS                                                                        0x3fff7bfc2c1c
+#define regBIFPLR2_1_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR2_1_ROOT_CNTL                                                                          0x3fff7bfc2c1d
+#define regBIFPLR2_1_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR2_1_ROOT_CAP                                                                           0x3fff7bfc2c1d
+#define regBIFPLR2_1_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR2_1_ROOT_STATUS                                                                        0x3fff7bfc2c1e
+#define regBIFPLR2_1_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR2_1_DEVICE_CAP2                                                                        0x3fff7bfc2c1f
+#define regBIFPLR2_1_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR2_1_DEVICE_CNTL2                                                                       0x3fff7bfc2c20
+#define regBIFPLR2_1_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR2_1_DEVICE_STATUS2                                                                     0x3fff7bfc2c20
+#define regBIFPLR2_1_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR2_1_LINK_CAP2                                                                          0x3fff7bfc2c21
+#define regBIFPLR2_1_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR2_1_LINK_CNTL2                                                                         0x3fff7bfc2c22
+#define regBIFPLR2_1_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR2_1_LINK_STATUS2                                                                       0x3fff7bfc2c22
+#define regBIFPLR2_1_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR2_1_SLOT_CAP2                                                                          0x3fff7bfc2c23
+#define regBIFPLR2_1_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR2_1_SLOT_CNTL2                                                                         0x3fff7bfc2c24
+#define regBIFPLR2_1_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR2_1_SLOT_STATUS2                                                                       0x3fff7bfc2c24
+#define regBIFPLR2_1_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR2_1_MSI_CAP_LIST                                                                       0x3fff7bfc2c28
+#define regBIFPLR2_1_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR2_1_MSI_MSG_CNTL                                                                       0x3fff7bfc2c28
+#define regBIFPLR2_1_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR2_1_MSI_MSG_ADDR_LO                                                                    0x3fff7bfc2c29
+#define regBIFPLR2_1_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR2_1_MSI_MSG_ADDR_HI                                                                    0x3fff7bfc2c2a
+#define regBIFPLR2_1_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR2_1_MSI_MSG_DATA                                                                       0x3fff7bfc2c2a
+#define regBIFPLR2_1_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR2_1_MSI_MSG_DATA_64                                                                    0x3fff7bfc2c2b
+#define regBIFPLR2_1_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR2_1_SSID_CAP_LIST                                                                      0x3fff7bfc2c30
+#define regBIFPLR2_1_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR2_1_SSID_CAP                                                                           0x3fff7bfc2c31
+#define regBIFPLR2_1_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR2_1_MSI_MAP_CAP_LIST                                                                   0x3fff7bfc2c32
+#define regBIFPLR2_1_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR2_1_MSI_MAP_CAP                                                                        0x3fff7bfc2c32
+#define regBIFPLR2_1_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x3fff7bfc2c40
+#define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR                                                           0x3fff7bfc2c41
+#define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC1                                                              0x3fff7bfc2c42
+#define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC2                                                              0x3fff7bfc2c43
+#define regBIFPLR2_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR2_1_PCIE_VC_ENH_CAP_LIST                                                               0x3fff7bfc2c44
+#define regBIFPLR2_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_PORT_VC_CAP_REG1                                                              0x3fff7bfc2c45
+#define regBIFPLR2_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR2_1_PCIE_PORT_VC_CAP_REG2                                                              0x3fff7bfc2c46
+#define regBIFPLR2_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR2_1_PCIE_PORT_VC_CNTL                                                                  0x3fff7bfc2c47
+#define regBIFPLR2_1_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR2_1_PCIE_PORT_VC_STATUS                                                                0x3fff7bfc2c47
+#define regBIFPLR2_1_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR2_1_PCIE_VC0_RESOURCE_CAP                                                              0x3fff7bfc2c48
+#define regBIFPLR2_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR2_1_PCIE_VC0_RESOURCE_CNTL                                                             0x3fff7bfc2c49
+#define regBIFPLR2_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR2_1_PCIE_VC0_RESOURCE_STATUS                                                           0x3fff7bfc2c4a
+#define regBIFPLR2_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR2_1_PCIE_VC1_RESOURCE_CAP                                                              0x3fff7bfc2c4b
+#define regBIFPLR2_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR2_1_PCIE_VC1_RESOURCE_CNTL                                                             0x3fff7bfc2c4c
+#define regBIFPLR2_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR2_1_PCIE_VC1_RESOURCE_STATUS                                                           0x3fff7bfc2c4d
+#define regBIFPLR2_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x3fff7bfc2c50
+#define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1                                                            0x3fff7bfc2c51
+#define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2                                                            0x3fff7bfc2c52
+#define regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x3fff7bfc2c54
+#define regBIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_UNCORR_ERR_STATUS                                                             0x3fff7bfc2c55
+#define regBIFPLR2_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR2_1_PCIE_UNCORR_ERR_MASK                                                               0x3fff7bfc2c56
+#define regBIFPLR2_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY                                                           0x3fff7bfc2c57
+#define regBIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR2_1_PCIE_CORR_ERR_STATUS                                                               0x3fff7bfc2c58
+#define regBIFPLR2_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_CORR_ERR_MASK                                                                 0x3fff7bfc2c59
+#define regBIFPLR2_1_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL                                                              0x3fff7bfc2c5a
+#define regBIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR2_1_PCIE_HDR_LOG0                                                                      0x3fff7bfc2c5b
+#define regBIFPLR2_1_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR2_1_PCIE_HDR_LOG1                                                                      0x3fff7bfc2c5c
+#define regBIFPLR2_1_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR2_1_PCIE_HDR_LOG2                                                                      0x3fff7bfc2c5d
+#define regBIFPLR2_1_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR2_1_PCIE_HDR_LOG3                                                                      0x3fff7bfc2c5e
+#define regBIFPLR2_1_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR2_1_PCIE_ROOT_ERR_CMD                                                                  0x3fff7bfc2c5f
+#define regBIFPLR2_1_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR2_1_PCIE_ROOT_ERR_STATUS                                                               0x3fff7bfc2c60
+#define regBIFPLR2_1_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_ERR_SRC_ID                                                                    0x3fff7bfc2c61
+#define regBIFPLR2_1_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG0                                                               0x3fff7bfc2c62
+#define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG1                                                               0x3fff7bfc2c63
+#define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG2                                                               0x3fff7bfc2c64
+#define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG3                                                               0x3fff7bfc2c65
+#define regBIFPLR2_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x3fff7bfc2c9c
+#define regBIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR2_1_PCIE_LINK_CNTL3                                                                    0x3fff7bfc2c9d
+#define regBIFPLR2_1_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR2_1_PCIE_LANE_ERROR_STATUS                                                             0x3fff7bfc2c9e
+#define regBIFPLR2_1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x3fff7bfc2c9f
+#define regBIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x3fff7bfc2c9f
+#define regBIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x3fff7bfc2ca0
+#define regBIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x3fff7bfc2ca0
+#define regBIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x3fff7bfc2ca1
+#define regBIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x3fff7bfc2ca1
+#define regBIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x3fff7bfc2ca2
+#define regBIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x3fff7bfc2ca2
+#define regBIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x3fff7bfc2ca3
+#define regBIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x3fff7bfc2ca3
+#define regBIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x3fff7bfc2ca4
+#define regBIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x3fff7bfc2ca4
+#define regBIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x3fff7bfc2ca5
+#define regBIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x3fff7bfc2ca5
+#define regBIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x3fff7bfc2ca6
+#define regBIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x3fff7bfc2ca6
+#define regBIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR2_1_PCIE_ACS_ENH_CAP_LIST                                                              0x3fff7bfc2ca8
+#define regBIFPLR2_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR2_1_PCIE_ACS_CAP                                                                       0x3fff7bfc2ca9
+#define regBIFPLR2_1_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR2_1_PCIE_ACS_CNTL                                                                      0x3fff7bfc2ca9
+#define regBIFPLR2_1_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR2_1_PCIE_MC_ENH_CAP_LIST                                                               0x3fff7bfc2cbc
+#define regBIFPLR2_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_MC_CAP                                                                        0x3fff7bfc2cbd
+#define regBIFPLR2_1_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR2_1_PCIE_MC_CNTL                                                                       0x3fff7bfc2cbd
+#define regBIFPLR2_1_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR2_1_PCIE_MC_ADDR0                                                                      0x3fff7bfc2cbe
+#define regBIFPLR2_1_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR2_1_PCIE_MC_ADDR1                                                                      0x3fff7bfc2cbf
+#define regBIFPLR2_1_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR2_1_PCIE_MC_RCV0                                                                       0x3fff7bfc2cc0
+#define regBIFPLR2_1_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR2_1_PCIE_MC_RCV1                                                                       0x3fff7bfc2cc1
+#define regBIFPLR2_1_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR2_1_PCIE_MC_BLOCK_ALL0                                                                 0x3fff7bfc2cc2
+#define regBIFPLR2_1_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR2_1_PCIE_MC_BLOCK_ALL1                                                                 0x3fff7bfc2cc3
+#define regBIFPLR2_1_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x3fff7bfc2cc4
+#define regBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x3fff7bfc2cc5
+#define regBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR2_1_PCIE_MC_OVERLAY_BAR0                                                               0x3fff7bfc2cc6
+#define regBIFPLR2_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_MC_OVERLAY_BAR1                                                               0x3fff7bfc2cc7
+#define regBIFPLR2_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST                                                            0x3fff7bfc2cdc
+#define regBIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR2_1_PCIE_L1_PM_SUB_CAP                                                                 0x3fff7bfc2cdd
+#define regBIFPLR2_1_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR2_1_PCIE_L1_PM_SUB_CNTL                                                                0x3fff7bfc2cde
+#define regBIFPLR2_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR2_1_PCIE_L1_PM_SUB_CNTL2                                                               0x3fff7bfc2cdf
+#define regBIFPLR2_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_DPC_ENH_CAP_LIST                                                              0x3fff7bfc2ce0
+#define regBIFPLR2_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR2_1_PCIE_DPC_CAP_LIST                                                                  0x3fff7bfc2ce1
+#define regBIFPLR2_1_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR2_1_PCIE_DPC_CNTL                                                                      0x3fff7bfc2ce1
+#define regBIFPLR2_1_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR2_1_PCIE_DPC_STATUS                                                                    0x3fff7bfc2ce2
+#define regBIFPLR2_1_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID                                                           0x3fff7bfc2ce2
+#define regBIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR2_1_PCIE_RP_PIO_STATUS                                                                 0x3fff7bfc2ce3
+#define regBIFPLR2_1_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR2_1_PCIE_RP_PIO_MASK                                                                   0x3fff7bfc2ce4
+#define regBIFPLR2_1_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR2_1_PCIE_RP_PIO_SEVERITY                                                               0x3fff7bfc2ce5
+#define regBIFPLR2_1_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_RP_PIO_SYSERROR                                                               0x3fff7bfc2ce6
+#define regBIFPLR2_1_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_RP_PIO_EXCEPTION                                                              0x3fff7bfc2ce7
+#define regBIFPLR2_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG0                                                               0x3fff7bfc2ce8
+#define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG1                                                               0x3fff7bfc2ce9
+#define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG2                                                               0x3fff7bfc2cea
+#define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG3                                                               0x3fff7bfc2ceb
+#define regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0                                                            0x3fff7bfc2ced
+#define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1                                                            0x3fff7bfc2cee
+#define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2                                                            0x3fff7bfc2cef
+#define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3                                                            0x3fff7bfc2cf0
+#define regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR2_1_PCIE_ESM_CAP_LIST                                                                  0x3fff7bfc2cf1
+#define regBIFPLR2_1_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR2_1_PCIE_ESM_HEADER_1                                                                  0x3fff7bfc2cf2
+#define regBIFPLR2_1_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR2_1_PCIE_ESM_HEADER_2                                                                  0x3fff7bfc2cf3
+#define regBIFPLR2_1_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR2_1_PCIE_ESM_STATUS                                                                    0x3fff7bfc2cf3
+#define regBIFPLR2_1_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR2_1_PCIE_ESM_CTRL                                                                      0x3fff7bfc2cf4
+#define regBIFPLR2_1_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR2_1_PCIE_ESM_CAP_1                                                                     0x3fff7bfc2cf5
+#define regBIFPLR2_1_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR2_1_PCIE_ESM_CAP_2                                                                     0x3fff7bfc2cf6
+#define regBIFPLR2_1_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR2_1_PCIE_ESM_CAP_3                                                                     0x3fff7bfc2cf7
+#define regBIFPLR2_1_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR2_1_PCIE_ESM_CAP_4                                                                     0x3fff7bfc2cf8
+#define regBIFPLR2_1_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR2_1_PCIE_ESM_CAP_5                                                                     0x3fff7bfc2cf9
+#define regBIFPLR2_1_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR2_1_PCIE_ESM_CAP_6                                                                     0x3fff7bfc2cfa
+#define regBIFPLR2_1_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR2_1_PCIE_ESM_CAP_7                                                                     0x3fff7bfc2cfb
+#define regBIFPLR2_1_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR2_1_PCIE_DLF_ENH_CAP_LIST                                                              0x3fff7bfc2d00
+#define regBIFPLR2_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR2_1_DATA_LINK_FEATURE_CAP                                                              0x3fff7bfc2d01
+#define regBIFPLR2_1_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR2_1_DATA_LINK_FEATURE_STATUS                                                           0x3fff7bfc2d02
+#define regBIFPLR2_1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x3fff7bfc2d04
+#define regBIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR2_1_LINK_CAP_16GT                                                                      0x3fff7bfc2d05
+#define regBIFPLR2_1_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR2_1_LINK_CNTL_16GT                                                                     0x3fff7bfc2d06
+#define regBIFPLR2_1_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR2_1_LINK_STATUS_16GT                                                                   0x3fff7bfc2d07
+#define regBIFPLR2_1_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR2_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x3fff7bfc2d08
+#define regBIFPLR2_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR2_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc2d09
+#define regBIFPLR2_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR2_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc2d0a
+#define regBIFPLR2_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc2d0c
+#define regBIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc2d0c
+#define regBIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc2d0c
+#define regBIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc2d0c
+#define regBIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc2d0d
+#define regBIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc2d0d
+#define regBIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc2d0d
+#define regBIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc2d0d
+#define regBIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc2d0e
+#define regBIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc2d0e
+#define regBIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc2d0e
+#define regBIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc2d0e
+#define regBIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc2d0f
+#define regBIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc2d0f
+#define regBIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc2d0f
+#define regBIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc2d0f
+#define regBIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST                                                        0x3fff7bfc2d10
+#define regBIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR2_1_MARGINING_PORT_CAP                                                                 0x3fff7bfc2d11
+#define regBIFPLR2_1_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR2_1_MARGINING_PORT_STATUS                                                              0x3fff7bfc2d11
+#define regBIFPLR2_1_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR2_1_LANE_0_MARGINING_LANE_CNTL                                                         0x3fff7bfc2d12
+#define regBIFPLR2_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_1_LANE_0_MARGINING_LANE_STATUS                                                       0x3fff7bfc2d12
+#define regBIFPLR2_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_1_LANE_1_MARGINING_LANE_CNTL                                                         0x3fff7bfc2d13
+#define regBIFPLR2_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_1_LANE_1_MARGINING_LANE_STATUS                                                       0x3fff7bfc2d13
+#define regBIFPLR2_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_1_LANE_2_MARGINING_LANE_CNTL                                                         0x3fff7bfc2d14
+#define regBIFPLR2_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_1_LANE_2_MARGINING_LANE_STATUS                                                       0x3fff7bfc2d14
+#define regBIFPLR2_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_1_LANE_3_MARGINING_LANE_CNTL                                                         0x3fff7bfc2d15
+#define regBIFPLR2_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_1_LANE_3_MARGINING_LANE_STATUS                                                       0x3fff7bfc2d15
+#define regBIFPLR2_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_1_LANE_4_MARGINING_LANE_CNTL                                                         0x3fff7bfc2d16
+#define regBIFPLR2_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_1_LANE_4_MARGINING_LANE_STATUS                                                       0x3fff7bfc2d16
+#define regBIFPLR2_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_1_LANE_5_MARGINING_LANE_CNTL                                                         0x3fff7bfc2d17
+#define regBIFPLR2_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_1_LANE_5_MARGINING_LANE_STATUS                                                       0x3fff7bfc2d17
+#define regBIFPLR2_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_1_LANE_6_MARGINING_LANE_CNTL                                                         0x3fff7bfc2d18
+#define regBIFPLR2_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_1_LANE_6_MARGINING_LANE_STATUS                                                       0x3fff7bfc2d18
+#define regBIFPLR2_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_1_LANE_7_MARGINING_LANE_CNTL                                                         0x3fff7bfc2d19
+#define regBIFPLR2_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_1_LANE_7_MARGINING_LANE_STATUS                                                       0x3fff7bfc2d19
+#define regBIFPLR2_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_1_LANE_8_MARGINING_LANE_CNTL                                                         0x3fff7bfc2d1a
+#define regBIFPLR2_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_1_LANE_8_MARGINING_LANE_STATUS                                                       0x3fff7bfc2d1a
+#define regBIFPLR2_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_1_LANE_9_MARGINING_LANE_CNTL                                                         0x3fff7bfc2d1b
+#define regBIFPLR2_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR2_1_LANE_9_MARGINING_LANE_STATUS                                                       0x3fff7bfc2d1b
+#define regBIFPLR2_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR2_1_LANE_10_MARGINING_LANE_CNTL                                                        0x3fff7bfc2d1c
+#define regBIFPLR2_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_1_LANE_10_MARGINING_LANE_STATUS                                                      0x3fff7bfc2d1c
+#define regBIFPLR2_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_11_MARGINING_LANE_CNTL                                                        0x3fff7bfc2d1d
+#define regBIFPLR2_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_1_LANE_11_MARGINING_LANE_STATUS                                                      0x3fff7bfc2d1d
+#define regBIFPLR2_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_12_MARGINING_LANE_CNTL                                                        0x3fff7bfc2d1e
+#define regBIFPLR2_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_1_LANE_12_MARGINING_LANE_STATUS                                                      0x3fff7bfc2d1e
+#define regBIFPLR2_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_13_MARGINING_LANE_CNTL                                                        0x3fff7bfc2d1f
+#define regBIFPLR2_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_1_LANE_13_MARGINING_LANE_STATUS                                                      0x3fff7bfc2d1f
+#define regBIFPLR2_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_14_MARGINING_LANE_CNTL                                                        0x3fff7bfc2d20
+#define regBIFPLR2_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_1_LANE_14_MARGINING_LANE_STATUS                                                      0x3fff7bfc2d20
+#define regBIFPLR2_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_1_LANE_15_MARGINING_LANE_CNTL                                                        0x3fff7bfc2d21
+#define regBIFPLR2_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR2_1_LANE_15_MARGINING_LANE_STATUS                                                      0x3fff7bfc2d21
+#define regBIFPLR2_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR2_1_PCIE_CCIX_CAP_LIST                                                                 0x3fff7bfc2d22
+#define regBIFPLR2_1_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR2_1_PCIE_CCIX_HEADER_1                                                                 0x3fff7bfc2d23
+#define regBIFPLR2_1_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR2_1_PCIE_CCIX_HEADER_2                                                                 0x3fff7bfc2d24
+#define regBIFPLR2_1_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR2_1_PCIE_CCIX_CAP                                                                      0x3fff7bfc2d24
+#define regBIFPLR2_1_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP                                                             0x3fff7bfc2d25
+#define regBIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR2_1_PCIE_CCIX_ESM_OPTL_CAP                                                             0x3fff7bfc2d26
+#define regBIFPLR2_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR2_1_PCIE_CCIX_ESM_STATUS                                                               0x3fff7bfc2d27
+#define regBIFPLR2_1_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR2_1_PCIE_CCIX_ESM_CNTL                                                                 0x3fff7bfc2d28
+#define regBIFPLR2_1_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2d29
+#define regBIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2d29
+#define regBIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2d29
+#define regBIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2d29
+#define regBIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2d2a
+#define regBIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2d2a
+#define regBIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2d2a
+#define regBIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2d2a
+#define regBIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2d2b
+#define regBIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc2d2b
+#define regBIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc2d2b
+#define regBIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc2d2b
+#define regBIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc2d2c
+#define regBIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc2d2c
+#define regBIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc2d2c
+#define regBIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc2d2c
+#define regBIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc2d2d
+#define regBIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc2d2d
+#define regBIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc2d2d
+#define regBIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc2d2d
+#define regBIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc2d2e
+#define regBIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc2d2e
+#define regBIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc2d2e
+#define regBIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc2d2e
+#define regBIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc2d2f
+#define regBIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc2d2f
+#define regBIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2d2f
+#define regBIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2d2f
+#define regBIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2d30
+#define regBIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2d30
+#define regBIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2d30
+#define regBIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc2d30
+#define regBIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR2_1_PCIE_CCIX_TRANS_CAP                                                                0x3fff7bfc2d31
+#define regBIFPLR2_1_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR2_1_PCIE_CCIX_TRANS_CNTL                                                               0x3fff7bfc2d32
+#define regBIFPLR2_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+// base address: 0xfffe0000c000
+#define regBIFPLR3_1_VENDOR_ID                                                                          0x3fff7bfc3000
+#define regBIFPLR3_1_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR3_1_DEVICE_ID                                                                          0x3fff7bfc3000
+#define regBIFPLR3_1_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR3_1_COMMAND                                                                            0x3fff7bfc3001
+#define regBIFPLR3_1_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR3_1_STATUS                                                                             0x3fff7bfc3001
+#define regBIFPLR3_1_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR3_1_REVISION_ID                                                                        0x3fff7bfc3002
+#define regBIFPLR3_1_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR3_1_PROG_INTERFACE                                                                     0x3fff7bfc3002
+#define regBIFPLR3_1_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR3_1_SUB_CLASS                                                                          0x3fff7bfc3002
+#define regBIFPLR3_1_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR3_1_BASE_CLASS                                                                         0x3fff7bfc3002
+#define regBIFPLR3_1_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR3_1_CACHE_LINE                                                                         0x3fff7bfc3003
+#define regBIFPLR3_1_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR3_1_LATENCY                                                                            0x3fff7bfc3003
+#define regBIFPLR3_1_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR3_1_HEADER                                                                             0x3fff7bfc3003
+#define regBIFPLR3_1_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR3_1_BIST                                                                               0x3fff7bfc3003
+#define regBIFPLR3_1_BIST_BASE_IDX                                                                      5
+#define regBIFPLR3_1_SUB_BUS_NUMBER_LATENCY                                                             0x3fff7bfc3006
+#define regBIFPLR3_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR3_1_IO_BASE_LIMIT                                                                      0x3fff7bfc3007
+#define regBIFPLR3_1_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR3_1_SECONDARY_STATUS                                                                   0x3fff7bfc3007
+#define regBIFPLR3_1_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR3_1_MEM_BASE_LIMIT                                                                     0x3fff7bfc3008
+#define regBIFPLR3_1_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR3_1_PREF_BASE_LIMIT                                                                    0x3fff7bfc3009
+#define regBIFPLR3_1_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR3_1_PREF_BASE_UPPER                                                                    0x3fff7bfc300a
+#define regBIFPLR3_1_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR3_1_PREF_LIMIT_UPPER                                                                   0x3fff7bfc300b
+#define regBIFPLR3_1_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR3_1_IO_BASE_LIMIT_HI                                                                   0x3fff7bfc300c
+#define regBIFPLR3_1_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR3_1_CAP_PTR                                                                            0x3fff7bfc300d
+#define regBIFPLR3_1_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR3_1_ROM_BASE_ADDR                                                                      0x3fff7bfc300e
+#define regBIFPLR3_1_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR3_1_INTERRUPT_LINE                                                                     0x3fff7bfc300f
+#define regBIFPLR3_1_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR3_1_INTERRUPT_PIN                                                                      0x3fff7bfc300f
+#define regBIFPLR3_1_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR3_1_IRQ_BRIDGE_CNTL                                                                    0x3fff7bfc300f
+#define regBIFPLR3_1_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR3_1_EXT_BRIDGE_CNTL                                                                    0x3fff7bfc3010
+#define regBIFPLR3_1_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR3_1_VENDOR_CAP_LIST                                                                    0x3fff7bfc3012
+#define regBIFPLR3_1_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR3_1_ADAPTER_ID_W                                                                       0x3fff7bfc3013
+#define regBIFPLR3_1_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR3_1_PMI_CAP_LIST                                                                       0x3fff7bfc3014
+#define regBIFPLR3_1_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR3_1_PMI_CAP                                                                            0x3fff7bfc3014
+#define regBIFPLR3_1_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR3_1_PMI_STATUS_CNTL                                                                    0x3fff7bfc3015
+#define regBIFPLR3_1_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR3_1_PCIE_CAP_LIST                                                                      0x3fff7bfc3016
+#define regBIFPLR3_1_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR3_1_PCIE_CAP                                                                           0x3fff7bfc3016
+#define regBIFPLR3_1_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR3_1_DEVICE_CAP                                                                         0x3fff7bfc3017
+#define regBIFPLR3_1_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR3_1_DEVICE_CNTL                                                                        0x3fff7bfc3018
+#define regBIFPLR3_1_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR3_1_DEVICE_STATUS                                                                      0x3fff7bfc3018
+#define regBIFPLR3_1_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR3_1_LINK_CAP                                                                           0x3fff7bfc3019
+#define regBIFPLR3_1_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR3_1_LINK_CNTL                                                                          0x3fff7bfc301a
+#define regBIFPLR3_1_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR3_1_LINK_STATUS                                                                        0x3fff7bfc301a
+#define regBIFPLR3_1_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR3_1_SLOT_CAP                                                                           0x3fff7bfc301b
+#define regBIFPLR3_1_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR3_1_SLOT_CNTL                                                                          0x3fff7bfc301c
+#define regBIFPLR3_1_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR3_1_SLOT_STATUS                                                                        0x3fff7bfc301c
+#define regBIFPLR3_1_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR3_1_ROOT_CNTL                                                                          0x3fff7bfc301d
+#define regBIFPLR3_1_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR3_1_ROOT_CAP                                                                           0x3fff7bfc301d
+#define regBIFPLR3_1_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR3_1_ROOT_STATUS                                                                        0x3fff7bfc301e
+#define regBIFPLR3_1_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR3_1_DEVICE_CAP2                                                                        0x3fff7bfc301f
+#define regBIFPLR3_1_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR3_1_DEVICE_CNTL2                                                                       0x3fff7bfc3020
+#define regBIFPLR3_1_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR3_1_DEVICE_STATUS2                                                                     0x3fff7bfc3020
+#define regBIFPLR3_1_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR3_1_LINK_CAP2                                                                          0x3fff7bfc3021
+#define regBIFPLR3_1_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR3_1_LINK_CNTL2                                                                         0x3fff7bfc3022
+#define regBIFPLR3_1_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR3_1_LINK_STATUS2                                                                       0x3fff7bfc3022
+#define regBIFPLR3_1_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR3_1_SLOT_CAP2                                                                          0x3fff7bfc3023
+#define regBIFPLR3_1_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR3_1_SLOT_CNTL2                                                                         0x3fff7bfc3024
+#define regBIFPLR3_1_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR3_1_SLOT_STATUS2                                                                       0x3fff7bfc3024
+#define regBIFPLR3_1_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR3_1_MSI_CAP_LIST                                                                       0x3fff7bfc3028
+#define regBIFPLR3_1_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR3_1_MSI_MSG_CNTL                                                                       0x3fff7bfc3028
+#define regBIFPLR3_1_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR3_1_MSI_MSG_ADDR_LO                                                                    0x3fff7bfc3029
+#define regBIFPLR3_1_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR3_1_MSI_MSG_ADDR_HI                                                                    0x3fff7bfc302a
+#define regBIFPLR3_1_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR3_1_MSI_MSG_DATA                                                                       0x3fff7bfc302a
+#define regBIFPLR3_1_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR3_1_MSI_MSG_DATA_64                                                                    0x3fff7bfc302b
+#define regBIFPLR3_1_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR3_1_SSID_CAP_LIST                                                                      0x3fff7bfc3030
+#define regBIFPLR3_1_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR3_1_SSID_CAP                                                                           0x3fff7bfc3031
+#define regBIFPLR3_1_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR3_1_MSI_MAP_CAP_LIST                                                                   0x3fff7bfc3032
+#define regBIFPLR3_1_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR3_1_MSI_MAP_CAP                                                                        0x3fff7bfc3032
+#define regBIFPLR3_1_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x3fff7bfc3040
+#define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR                                                           0x3fff7bfc3041
+#define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC1                                                              0x3fff7bfc3042
+#define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC2                                                              0x3fff7bfc3043
+#define regBIFPLR3_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR3_1_PCIE_VC_ENH_CAP_LIST                                                               0x3fff7bfc3044
+#define regBIFPLR3_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_PORT_VC_CAP_REG1                                                              0x3fff7bfc3045
+#define regBIFPLR3_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR3_1_PCIE_PORT_VC_CAP_REG2                                                              0x3fff7bfc3046
+#define regBIFPLR3_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR3_1_PCIE_PORT_VC_CNTL                                                                  0x3fff7bfc3047
+#define regBIFPLR3_1_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR3_1_PCIE_PORT_VC_STATUS                                                                0x3fff7bfc3047
+#define regBIFPLR3_1_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR3_1_PCIE_VC0_RESOURCE_CAP                                                              0x3fff7bfc3048
+#define regBIFPLR3_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR3_1_PCIE_VC0_RESOURCE_CNTL                                                             0x3fff7bfc3049
+#define regBIFPLR3_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR3_1_PCIE_VC0_RESOURCE_STATUS                                                           0x3fff7bfc304a
+#define regBIFPLR3_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR3_1_PCIE_VC1_RESOURCE_CAP                                                              0x3fff7bfc304b
+#define regBIFPLR3_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR3_1_PCIE_VC1_RESOURCE_CNTL                                                             0x3fff7bfc304c
+#define regBIFPLR3_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR3_1_PCIE_VC1_RESOURCE_STATUS                                                           0x3fff7bfc304d
+#define regBIFPLR3_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x3fff7bfc3050
+#define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1                                                            0x3fff7bfc3051
+#define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2                                                            0x3fff7bfc3052
+#define regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x3fff7bfc3054
+#define regBIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_UNCORR_ERR_STATUS                                                             0x3fff7bfc3055
+#define regBIFPLR3_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR3_1_PCIE_UNCORR_ERR_MASK                                                               0x3fff7bfc3056
+#define regBIFPLR3_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY                                                           0x3fff7bfc3057
+#define regBIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR3_1_PCIE_CORR_ERR_STATUS                                                               0x3fff7bfc3058
+#define regBIFPLR3_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_CORR_ERR_MASK                                                                 0x3fff7bfc3059
+#define regBIFPLR3_1_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL                                                              0x3fff7bfc305a
+#define regBIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR3_1_PCIE_HDR_LOG0                                                                      0x3fff7bfc305b
+#define regBIFPLR3_1_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR3_1_PCIE_HDR_LOG1                                                                      0x3fff7bfc305c
+#define regBIFPLR3_1_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR3_1_PCIE_HDR_LOG2                                                                      0x3fff7bfc305d
+#define regBIFPLR3_1_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR3_1_PCIE_HDR_LOG3                                                                      0x3fff7bfc305e
+#define regBIFPLR3_1_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR3_1_PCIE_ROOT_ERR_CMD                                                                  0x3fff7bfc305f
+#define regBIFPLR3_1_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR3_1_PCIE_ROOT_ERR_STATUS                                                               0x3fff7bfc3060
+#define regBIFPLR3_1_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_ERR_SRC_ID                                                                    0x3fff7bfc3061
+#define regBIFPLR3_1_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG0                                                               0x3fff7bfc3062
+#define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG1                                                               0x3fff7bfc3063
+#define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG2                                                               0x3fff7bfc3064
+#define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG3                                                               0x3fff7bfc3065
+#define regBIFPLR3_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x3fff7bfc309c
+#define regBIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR3_1_PCIE_LINK_CNTL3                                                                    0x3fff7bfc309d
+#define regBIFPLR3_1_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR3_1_PCIE_LANE_ERROR_STATUS                                                             0x3fff7bfc309e
+#define regBIFPLR3_1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x3fff7bfc309f
+#define regBIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x3fff7bfc309f
+#define regBIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x3fff7bfc30a0
+#define regBIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x3fff7bfc30a0
+#define regBIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x3fff7bfc30a1
+#define regBIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x3fff7bfc30a1
+#define regBIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x3fff7bfc30a2
+#define regBIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x3fff7bfc30a2
+#define regBIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x3fff7bfc30a3
+#define regBIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x3fff7bfc30a3
+#define regBIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x3fff7bfc30a4
+#define regBIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x3fff7bfc30a4
+#define regBIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x3fff7bfc30a5
+#define regBIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x3fff7bfc30a5
+#define regBIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x3fff7bfc30a6
+#define regBIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x3fff7bfc30a6
+#define regBIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR3_1_PCIE_ACS_ENH_CAP_LIST                                                              0x3fff7bfc30a8
+#define regBIFPLR3_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR3_1_PCIE_ACS_CAP                                                                       0x3fff7bfc30a9
+#define regBIFPLR3_1_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR3_1_PCIE_ACS_CNTL                                                                      0x3fff7bfc30a9
+#define regBIFPLR3_1_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR3_1_PCIE_MC_ENH_CAP_LIST                                                               0x3fff7bfc30bc
+#define regBIFPLR3_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_MC_CAP                                                                        0x3fff7bfc30bd
+#define regBIFPLR3_1_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR3_1_PCIE_MC_CNTL                                                                       0x3fff7bfc30bd
+#define regBIFPLR3_1_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR3_1_PCIE_MC_ADDR0                                                                      0x3fff7bfc30be
+#define regBIFPLR3_1_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR3_1_PCIE_MC_ADDR1                                                                      0x3fff7bfc30bf
+#define regBIFPLR3_1_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR3_1_PCIE_MC_RCV0                                                                       0x3fff7bfc30c0
+#define regBIFPLR3_1_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR3_1_PCIE_MC_RCV1                                                                       0x3fff7bfc30c1
+#define regBIFPLR3_1_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR3_1_PCIE_MC_BLOCK_ALL0                                                                 0x3fff7bfc30c2
+#define regBIFPLR3_1_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR3_1_PCIE_MC_BLOCK_ALL1                                                                 0x3fff7bfc30c3
+#define regBIFPLR3_1_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x3fff7bfc30c4
+#define regBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x3fff7bfc30c5
+#define regBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR3_1_PCIE_MC_OVERLAY_BAR0                                                               0x3fff7bfc30c6
+#define regBIFPLR3_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_MC_OVERLAY_BAR1                                                               0x3fff7bfc30c7
+#define regBIFPLR3_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST                                                            0x3fff7bfc30dc
+#define regBIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR3_1_PCIE_L1_PM_SUB_CAP                                                                 0x3fff7bfc30dd
+#define regBIFPLR3_1_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR3_1_PCIE_L1_PM_SUB_CNTL                                                                0x3fff7bfc30de
+#define regBIFPLR3_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR3_1_PCIE_L1_PM_SUB_CNTL2                                                               0x3fff7bfc30df
+#define regBIFPLR3_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_DPC_ENH_CAP_LIST                                                              0x3fff7bfc30e0
+#define regBIFPLR3_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR3_1_PCIE_DPC_CAP_LIST                                                                  0x3fff7bfc30e1
+#define regBIFPLR3_1_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR3_1_PCIE_DPC_CNTL                                                                      0x3fff7bfc30e1
+#define regBIFPLR3_1_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR3_1_PCIE_DPC_STATUS                                                                    0x3fff7bfc30e2
+#define regBIFPLR3_1_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID                                                           0x3fff7bfc30e2
+#define regBIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR3_1_PCIE_RP_PIO_STATUS                                                                 0x3fff7bfc30e3
+#define regBIFPLR3_1_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR3_1_PCIE_RP_PIO_MASK                                                                   0x3fff7bfc30e4
+#define regBIFPLR3_1_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR3_1_PCIE_RP_PIO_SEVERITY                                                               0x3fff7bfc30e5
+#define regBIFPLR3_1_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_RP_PIO_SYSERROR                                                               0x3fff7bfc30e6
+#define regBIFPLR3_1_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_RP_PIO_EXCEPTION                                                              0x3fff7bfc30e7
+#define regBIFPLR3_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG0                                                               0x3fff7bfc30e8
+#define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG1                                                               0x3fff7bfc30e9
+#define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG2                                                               0x3fff7bfc30ea
+#define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG3                                                               0x3fff7bfc30eb
+#define regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0                                                            0x3fff7bfc30ed
+#define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1                                                            0x3fff7bfc30ee
+#define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2                                                            0x3fff7bfc30ef
+#define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3                                                            0x3fff7bfc30f0
+#define regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR3_1_PCIE_ESM_CAP_LIST                                                                  0x3fff7bfc30f1
+#define regBIFPLR3_1_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR3_1_PCIE_ESM_HEADER_1                                                                  0x3fff7bfc30f2
+#define regBIFPLR3_1_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR3_1_PCIE_ESM_HEADER_2                                                                  0x3fff7bfc30f3
+#define regBIFPLR3_1_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR3_1_PCIE_ESM_STATUS                                                                    0x3fff7bfc30f3
+#define regBIFPLR3_1_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR3_1_PCIE_ESM_CTRL                                                                      0x3fff7bfc30f4
+#define regBIFPLR3_1_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR3_1_PCIE_ESM_CAP_1                                                                     0x3fff7bfc30f5
+#define regBIFPLR3_1_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR3_1_PCIE_ESM_CAP_2                                                                     0x3fff7bfc30f6
+#define regBIFPLR3_1_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR3_1_PCIE_ESM_CAP_3                                                                     0x3fff7bfc30f7
+#define regBIFPLR3_1_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR3_1_PCIE_ESM_CAP_4                                                                     0x3fff7bfc30f8
+#define regBIFPLR3_1_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR3_1_PCIE_ESM_CAP_5                                                                     0x3fff7bfc30f9
+#define regBIFPLR3_1_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR3_1_PCIE_ESM_CAP_6                                                                     0x3fff7bfc30fa
+#define regBIFPLR3_1_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR3_1_PCIE_ESM_CAP_7                                                                     0x3fff7bfc30fb
+#define regBIFPLR3_1_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR3_1_PCIE_DLF_ENH_CAP_LIST                                                              0x3fff7bfc3100
+#define regBIFPLR3_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR3_1_DATA_LINK_FEATURE_CAP                                                              0x3fff7bfc3101
+#define regBIFPLR3_1_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR3_1_DATA_LINK_FEATURE_STATUS                                                           0x3fff7bfc3102
+#define regBIFPLR3_1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x3fff7bfc3104
+#define regBIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR3_1_LINK_CAP_16GT                                                                      0x3fff7bfc3105
+#define regBIFPLR3_1_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR3_1_LINK_CNTL_16GT                                                                     0x3fff7bfc3106
+#define regBIFPLR3_1_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR3_1_LINK_STATUS_16GT                                                                   0x3fff7bfc3107
+#define regBIFPLR3_1_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR3_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x3fff7bfc3108
+#define regBIFPLR3_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR3_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc3109
+#define regBIFPLR3_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR3_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc310a
+#define regBIFPLR3_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc310c
+#define regBIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc310c
+#define regBIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc310c
+#define regBIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc310c
+#define regBIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc310d
+#define regBIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc310d
+#define regBIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc310d
+#define regBIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc310d
+#define regBIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc310e
+#define regBIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc310e
+#define regBIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc310e
+#define regBIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc310e
+#define regBIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc310f
+#define regBIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc310f
+#define regBIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc310f
+#define regBIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc310f
+#define regBIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST                                                        0x3fff7bfc3110
+#define regBIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR3_1_MARGINING_PORT_CAP                                                                 0x3fff7bfc3111
+#define regBIFPLR3_1_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR3_1_MARGINING_PORT_STATUS                                                              0x3fff7bfc3111
+#define regBIFPLR3_1_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR3_1_LANE_0_MARGINING_LANE_CNTL                                                         0x3fff7bfc3112
+#define regBIFPLR3_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_1_LANE_0_MARGINING_LANE_STATUS                                                       0x3fff7bfc3112
+#define regBIFPLR3_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_1_LANE_1_MARGINING_LANE_CNTL                                                         0x3fff7bfc3113
+#define regBIFPLR3_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_1_LANE_1_MARGINING_LANE_STATUS                                                       0x3fff7bfc3113
+#define regBIFPLR3_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_1_LANE_2_MARGINING_LANE_CNTL                                                         0x3fff7bfc3114
+#define regBIFPLR3_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_1_LANE_2_MARGINING_LANE_STATUS                                                       0x3fff7bfc3114
+#define regBIFPLR3_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_1_LANE_3_MARGINING_LANE_CNTL                                                         0x3fff7bfc3115
+#define regBIFPLR3_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_1_LANE_3_MARGINING_LANE_STATUS                                                       0x3fff7bfc3115
+#define regBIFPLR3_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_1_LANE_4_MARGINING_LANE_CNTL                                                         0x3fff7bfc3116
+#define regBIFPLR3_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_1_LANE_4_MARGINING_LANE_STATUS                                                       0x3fff7bfc3116
+#define regBIFPLR3_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_1_LANE_5_MARGINING_LANE_CNTL                                                         0x3fff7bfc3117
+#define regBIFPLR3_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_1_LANE_5_MARGINING_LANE_STATUS                                                       0x3fff7bfc3117
+#define regBIFPLR3_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_1_LANE_6_MARGINING_LANE_CNTL                                                         0x3fff7bfc3118
+#define regBIFPLR3_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_1_LANE_6_MARGINING_LANE_STATUS                                                       0x3fff7bfc3118
+#define regBIFPLR3_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_1_LANE_7_MARGINING_LANE_CNTL                                                         0x3fff7bfc3119
+#define regBIFPLR3_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_1_LANE_7_MARGINING_LANE_STATUS                                                       0x3fff7bfc3119
+#define regBIFPLR3_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_1_LANE_8_MARGINING_LANE_CNTL                                                         0x3fff7bfc311a
+#define regBIFPLR3_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_1_LANE_8_MARGINING_LANE_STATUS                                                       0x3fff7bfc311a
+#define regBIFPLR3_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_1_LANE_9_MARGINING_LANE_CNTL                                                         0x3fff7bfc311b
+#define regBIFPLR3_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR3_1_LANE_9_MARGINING_LANE_STATUS                                                       0x3fff7bfc311b
+#define regBIFPLR3_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR3_1_LANE_10_MARGINING_LANE_CNTL                                                        0x3fff7bfc311c
+#define regBIFPLR3_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_1_LANE_10_MARGINING_LANE_STATUS                                                      0x3fff7bfc311c
+#define regBIFPLR3_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_11_MARGINING_LANE_CNTL                                                        0x3fff7bfc311d
+#define regBIFPLR3_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_1_LANE_11_MARGINING_LANE_STATUS                                                      0x3fff7bfc311d
+#define regBIFPLR3_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_12_MARGINING_LANE_CNTL                                                        0x3fff7bfc311e
+#define regBIFPLR3_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_1_LANE_12_MARGINING_LANE_STATUS                                                      0x3fff7bfc311e
+#define regBIFPLR3_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_13_MARGINING_LANE_CNTL                                                        0x3fff7bfc311f
+#define regBIFPLR3_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_1_LANE_13_MARGINING_LANE_STATUS                                                      0x3fff7bfc311f
+#define regBIFPLR3_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_14_MARGINING_LANE_CNTL                                                        0x3fff7bfc3120
+#define regBIFPLR3_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_1_LANE_14_MARGINING_LANE_STATUS                                                      0x3fff7bfc3120
+#define regBIFPLR3_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_1_LANE_15_MARGINING_LANE_CNTL                                                        0x3fff7bfc3121
+#define regBIFPLR3_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR3_1_LANE_15_MARGINING_LANE_STATUS                                                      0x3fff7bfc3121
+#define regBIFPLR3_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR3_1_PCIE_CCIX_CAP_LIST                                                                 0x3fff7bfc3122
+#define regBIFPLR3_1_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR3_1_PCIE_CCIX_HEADER_1                                                                 0x3fff7bfc3123
+#define regBIFPLR3_1_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR3_1_PCIE_CCIX_HEADER_2                                                                 0x3fff7bfc3124
+#define regBIFPLR3_1_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR3_1_PCIE_CCIX_CAP                                                                      0x3fff7bfc3124
+#define regBIFPLR3_1_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP                                                             0x3fff7bfc3125
+#define regBIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR3_1_PCIE_CCIX_ESM_OPTL_CAP                                                             0x3fff7bfc3126
+#define regBIFPLR3_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR3_1_PCIE_CCIX_ESM_STATUS                                                               0x3fff7bfc3127
+#define regBIFPLR3_1_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR3_1_PCIE_CCIX_ESM_CNTL                                                                 0x3fff7bfc3128
+#define regBIFPLR3_1_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3129
+#define regBIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3129
+#define regBIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3129
+#define regBIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3129
+#define regBIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc312a
+#define regBIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc312a
+#define regBIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc312a
+#define regBIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc312a
+#define regBIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc312b
+#define regBIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc312b
+#define regBIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc312b
+#define regBIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc312b
+#define regBIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc312c
+#define regBIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc312c
+#define regBIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc312c
+#define regBIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc312c
+#define regBIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc312d
+#define regBIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc312d
+#define regBIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc312d
+#define regBIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc312d
+#define regBIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc312e
+#define regBIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc312e
+#define regBIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc312e
+#define regBIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc312e
+#define regBIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc312f
+#define regBIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc312f
+#define regBIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc312f
+#define regBIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc312f
+#define regBIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3130
+#define regBIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3130
+#define regBIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3130
+#define regBIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3130
+#define regBIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR3_1_PCIE_CCIX_TRANS_CAP                                                                0x3fff7bfc3131
+#define regBIFPLR3_1_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR3_1_PCIE_CCIX_TRANS_CNTL                                                               0x3fff7bfc3132
+#define regBIFPLR3_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+// base address: 0xfffe0000d000
+#define regBIFPLR4_1_VENDOR_ID                                                                          0x3fff7bfc3400
+#define regBIFPLR4_1_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR4_1_DEVICE_ID                                                                          0x3fff7bfc3400
+#define regBIFPLR4_1_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR4_1_COMMAND                                                                            0x3fff7bfc3401
+#define regBIFPLR4_1_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR4_1_STATUS                                                                             0x3fff7bfc3401
+#define regBIFPLR4_1_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR4_1_REVISION_ID                                                                        0x3fff7bfc3402
+#define regBIFPLR4_1_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR4_1_PROG_INTERFACE                                                                     0x3fff7bfc3402
+#define regBIFPLR4_1_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR4_1_SUB_CLASS                                                                          0x3fff7bfc3402
+#define regBIFPLR4_1_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR4_1_BASE_CLASS                                                                         0x3fff7bfc3402
+#define regBIFPLR4_1_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR4_1_CACHE_LINE                                                                         0x3fff7bfc3403
+#define regBIFPLR4_1_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR4_1_LATENCY                                                                            0x3fff7bfc3403
+#define regBIFPLR4_1_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR4_1_HEADER                                                                             0x3fff7bfc3403
+#define regBIFPLR4_1_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR4_1_BIST                                                                               0x3fff7bfc3403
+#define regBIFPLR4_1_BIST_BASE_IDX                                                                      5
+#define regBIFPLR4_1_SUB_BUS_NUMBER_LATENCY                                                             0x3fff7bfc3406
+#define regBIFPLR4_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR4_1_IO_BASE_LIMIT                                                                      0x3fff7bfc3407
+#define regBIFPLR4_1_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR4_1_SECONDARY_STATUS                                                                   0x3fff7bfc3407
+#define regBIFPLR4_1_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR4_1_MEM_BASE_LIMIT                                                                     0x3fff7bfc3408
+#define regBIFPLR4_1_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR4_1_PREF_BASE_LIMIT                                                                    0x3fff7bfc3409
+#define regBIFPLR4_1_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR4_1_PREF_BASE_UPPER                                                                    0x3fff7bfc340a
+#define regBIFPLR4_1_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR4_1_PREF_LIMIT_UPPER                                                                   0x3fff7bfc340b
+#define regBIFPLR4_1_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR4_1_IO_BASE_LIMIT_HI                                                                   0x3fff7bfc340c
+#define regBIFPLR4_1_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR4_1_CAP_PTR                                                                            0x3fff7bfc340d
+#define regBIFPLR4_1_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR4_1_ROM_BASE_ADDR                                                                      0x3fff7bfc340e
+#define regBIFPLR4_1_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR4_1_INTERRUPT_LINE                                                                     0x3fff7bfc340f
+#define regBIFPLR4_1_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR4_1_INTERRUPT_PIN                                                                      0x3fff7bfc340f
+#define regBIFPLR4_1_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR4_1_IRQ_BRIDGE_CNTL                                                                    0x3fff7bfc340f
+#define regBIFPLR4_1_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR4_1_EXT_BRIDGE_CNTL                                                                    0x3fff7bfc3410
+#define regBIFPLR4_1_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR4_1_VENDOR_CAP_LIST                                                                    0x3fff7bfc3412
+#define regBIFPLR4_1_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR4_1_ADAPTER_ID_W                                                                       0x3fff7bfc3413
+#define regBIFPLR4_1_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR4_1_PMI_CAP_LIST                                                                       0x3fff7bfc3414
+#define regBIFPLR4_1_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR4_1_PMI_CAP                                                                            0x3fff7bfc3414
+#define regBIFPLR4_1_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR4_1_PMI_STATUS_CNTL                                                                    0x3fff7bfc3415
+#define regBIFPLR4_1_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR4_1_PCIE_CAP_LIST                                                                      0x3fff7bfc3416
+#define regBIFPLR4_1_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR4_1_PCIE_CAP                                                                           0x3fff7bfc3416
+#define regBIFPLR4_1_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR4_1_DEVICE_CAP                                                                         0x3fff7bfc3417
+#define regBIFPLR4_1_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR4_1_DEVICE_CNTL                                                                        0x3fff7bfc3418
+#define regBIFPLR4_1_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR4_1_DEVICE_STATUS                                                                      0x3fff7bfc3418
+#define regBIFPLR4_1_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR4_1_LINK_CAP                                                                           0x3fff7bfc3419
+#define regBIFPLR4_1_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR4_1_LINK_CNTL                                                                          0x3fff7bfc341a
+#define regBIFPLR4_1_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR4_1_LINK_STATUS                                                                        0x3fff7bfc341a
+#define regBIFPLR4_1_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR4_1_SLOT_CAP                                                                           0x3fff7bfc341b
+#define regBIFPLR4_1_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR4_1_SLOT_CNTL                                                                          0x3fff7bfc341c
+#define regBIFPLR4_1_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR4_1_SLOT_STATUS                                                                        0x3fff7bfc341c
+#define regBIFPLR4_1_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR4_1_ROOT_CNTL                                                                          0x3fff7bfc341d
+#define regBIFPLR4_1_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR4_1_ROOT_CAP                                                                           0x3fff7bfc341d
+#define regBIFPLR4_1_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR4_1_ROOT_STATUS                                                                        0x3fff7bfc341e
+#define regBIFPLR4_1_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR4_1_DEVICE_CAP2                                                                        0x3fff7bfc341f
+#define regBIFPLR4_1_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR4_1_DEVICE_CNTL2                                                                       0x3fff7bfc3420
+#define regBIFPLR4_1_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR4_1_DEVICE_STATUS2                                                                     0x3fff7bfc3420
+#define regBIFPLR4_1_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR4_1_LINK_CAP2                                                                          0x3fff7bfc3421
+#define regBIFPLR4_1_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR4_1_LINK_CNTL2                                                                         0x3fff7bfc3422
+#define regBIFPLR4_1_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR4_1_LINK_STATUS2                                                                       0x3fff7bfc3422
+#define regBIFPLR4_1_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR4_1_SLOT_CAP2                                                                          0x3fff7bfc3423
+#define regBIFPLR4_1_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR4_1_SLOT_CNTL2                                                                         0x3fff7bfc3424
+#define regBIFPLR4_1_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR4_1_SLOT_STATUS2                                                                       0x3fff7bfc3424
+#define regBIFPLR4_1_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR4_1_MSI_CAP_LIST                                                                       0x3fff7bfc3428
+#define regBIFPLR4_1_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR4_1_MSI_MSG_CNTL                                                                       0x3fff7bfc3428
+#define regBIFPLR4_1_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR4_1_MSI_MSG_ADDR_LO                                                                    0x3fff7bfc3429
+#define regBIFPLR4_1_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR4_1_MSI_MSG_ADDR_HI                                                                    0x3fff7bfc342a
+#define regBIFPLR4_1_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR4_1_MSI_MSG_DATA                                                                       0x3fff7bfc342a
+#define regBIFPLR4_1_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR4_1_MSI_MSG_DATA_64                                                                    0x3fff7bfc342b
+#define regBIFPLR4_1_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR4_1_SSID_CAP_LIST                                                                      0x3fff7bfc3430
+#define regBIFPLR4_1_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR4_1_SSID_CAP                                                                           0x3fff7bfc3431
+#define regBIFPLR4_1_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR4_1_MSI_MAP_CAP_LIST                                                                   0x3fff7bfc3432
+#define regBIFPLR4_1_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR4_1_MSI_MAP_CAP                                                                        0x3fff7bfc3432
+#define regBIFPLR4_1_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x3fff7bfc3440
+#define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR                                                           0x3fff7bfc3441
+#define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC1                                                              0x3fff7bfc3442
+#define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC2                                                              0x3fff7bfc3443
+#define regBIFPLR4_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR4_1_PCIE_VC_ENH_CAP_LIST                                                               0x3fff7bfc3444
+#define regBIFPLR4_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_PORT_VC_CAP_REG1                                                              0x3fff7bfc3445
+#define regBIFPLR4_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR4_1_PCIE_PORT_VC_CAP_REG2                                                              0x3fff7bfc3446
+#define regBIFPLR4_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR4_1_PCIE_PORT_VC_CNTL                                                                  0x3fff7bfc3447
+#define regBIFPLR4_1_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR4_1_PCIE_PORT_VC_STATUS                                                                0x3fff7bfc3447
+#define regBIFPLR4_1_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR4_1_PCIE_VC0_RESOURCE_CAP                                                              0x3fff7bfc3448
+#define regBIFPLR4_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR4_1_PCIE_VC0_RESOURCE_CNTL                                                             0x3fff7bfc3449
+#define regBIFPLR4_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR4_1_PCIE_VC0_RESOURCE_STATUS                                                           0x3fff7bfc344a
+#define regBIFPLR4_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR4_1_PCIE_VC1_RESOURCE_CAP                                                              0x3fff7bfc344b
+#define regBIFPLR4_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR4_1_PCIE_VC1_RESOURCE_CNTL                                                             0x3fff7bfc344c
+#define regBIFPLR4_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR4_1_PCIE_VC1_RESOURCE_STATUS                                                           0x3fff7bfc344d
+#define regBIFPLR4_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x3fff7bfc3450
+#define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1                                                            0x3fff7bfc3451
+#define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2                                                            0x3fff7bfc3452
+#define regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x3fff7bfc3454
+#define regBIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_UNCORR_ERR_STATUS                                                             0x3fff7bfc3455
+#define regBIFPLR4_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR4_1_PCIE_UNCORR_ERR_MASK                                                               0x3fff7bfc3456
+#define regBIFPLR4_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY                                                           0x3fff7bfc3457
+#define regBIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR4_1_PCIE_CORR_ERR_STATUS                                                               0x3fff7bfc3458
+#define regBIFPLR4_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_CORR_ERR_MASK                                                                 0x3fff7bfc3459
+#define regBIFPLR4_1_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL                                                              0x3fff7bfc345a
+#define regBIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR4_1_PCIE_HDR_LOG0                                                                      0x3fff7bfc345b
+#define regBIFPLR4_1_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR4_1_PCIE_HDR_LOG1                                                                      0x3fff7bfc345c
+#define regBIFPLR4_1_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR4_1_PCIE_HDR_LOG2                                                                      0x3fff7bfc345d
+#define regBIFPLR4_1_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR4_1_PCIE_HDR_LOG3                                                                      0x3fff7bfc345e
+#define regBIFPLR4_1_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR4_1_PCIE_ROOT_ERR_CMD                                                                  0x3fff7bfc345f
+#define regBIFPLR4_1_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR4_1_PCIE_ROOT_ERR_STATUS                                                               0x3fff7bfc3460
+#define regBIFPLR4_1_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_ERR_SRC_ID                                                                    0x3fff7bfc3461
+#define regBIFPLR4_1_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG0                                                               0x3fff7bfc3462
+#define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG1                                                               0x3fff7bfc3463
+#define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG2                                                               0x3fff7bfc3464
+#define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG3                                                               0x3fff7bfc3465
+#define regBIFPLR4_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x3fff7bfc349c
+#define regBIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR4_1_PCIE_LINK_CNTL3                                                                    0x3fff7bfc349d
+#define regBIFPLR4_1_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR4_1_PCIE_LANE_ERROR_STATUS                                                             0x3fff7bfc349e
+#define regBIFPLR4_1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x3fff7bfc349f
+#define regBIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x3fff7bfc349f
+#define regBIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x3fff7bfc34a0
+#define regBIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x3fff7bfc34a0
+#define regBIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x3fff7bfc34a1
+#define regBIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x3fff7bfc34a1
+#define regBIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x3fff7bfc34a2
+#define regBIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x3fff7bfc34a2
+#define regBIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x3fff7bfc34a3
+#define regBIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x3fff7bfc34a3
+#define regBIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x3fff7bfc34a4
+#define regBIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x3fff7bfc34a4
+#define regBIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x3fff7bfc34a5
+#define regBIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x3fff7bfc34a5
+#define regBIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x3fff7bfc34a6
+#define regBIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x3fff7bfc34a6
+#define regBIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR4_1_PCIE_ACS_ENH_CAP_LIST                                                              0x3fff7bfc34a8
+#define regBIFPLR4_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR4_1_PCIE_ACS_CAP                                                                       0x3fff7bfc34a9
+#define regBIFPLR4_1_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR4_1_PCIE_ACS_CNTL                                                                      0x3fff7bfc34a9
+#define regBIFPLR4_1_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR4_1_PCIE_MC_ENH_CAP_LIST                                                               0x3fff7bfc34bc
+#define regBIFPLR4_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_MC_CAP                                                                        0x3fff7bfc34bd
+#define regBIFPLR4_1_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR4_1_PCIE_MC_CNTL                                                                       0x3fff7bfc34bd
+#define regBIFPLR4_1_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR4_1_PCIE_MC_ADDR0                                                                      0x3fff7bfc34be
+#define regBIFPLR4_1_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR4_1_PCIE_MC_ADDR1                                                                      0x3fff7bfc34bf
+#define regBIFPLR4_1_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR4_1_PCIE_MC_RCV0                                                                       0x3fff7bfc34c0
+#define regBIFPLR4_1_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR4_1_PCIE_MC_RCV1                                                                       0x3fff7bfc34c1
+#define regBIFPLR4_1_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR4_1_PCIE_MC_BLOCK_ALL0                                                                 0x3fff7bfc34c2
+#define regBIFPLR4_1_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR4_1_PCIE_MC_BLOCK_ALL1                                                                 0x3fff7bfc34c3
+#define regBIFPLR4_1_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x3fff7bfc34c4
+#define regBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x3fff7bfc34c5
+#define regBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR4_1_PCIE_MC_OVERLAY_BAR0                                                               0x3fff7bfc34c6
+#define regBIFPLR4_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_MC_OVERLAY_BAR1                                                               0x3fff7bfc34c7
+#define regBIFPLR4_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST                                                            0x3fff7bfc34dc
+#define regBIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR4_1_PCIE_L1_PM_SUB_CAP                                                                 0x3fff7bfc34dd
+#define regBIFPLR4_1_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR4_1_PCIE_L1_PM_SUB_CNTL                                                                0x3fff7bfc34de
+#define regBIFPLR4_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR4_1_PCIE_L1_PM_SUB_CNTL2                                                               0x3fff7bfc34df
+#define regBIFPLR4_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_DPC_ENH_CAP_LIST                                                              0x3fff7bfc34e0
+#define regBIFPLR4_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR4_1_PCIE_DPC_CAP_LIST                                                                  0x3fff7bfc34e1
+#define regBIFPLR4_1_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR4_1_PCIE_DPC_CNTL                                                                      0x3fff7bfc34e1
+#define regBIFPLR4_1_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR4_1_PCIE_DPC_STATUS                                                                    0x3fff7bfc34e2
+#define regBIFPLR4_1_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID                                                           0x3fff7bfc34e2
+#define regBIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR4_1_PCIE_RP_PIO_STATUS                                                                 0x3fff7bfc34e3
+#define regBIFPLR4_1_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR4_1_PCIE_RP_PIO_MASK                                                                   0x3fff7bfc34e4
+#define regBIFPLR4_1_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR4_1_PCIE_RP_PIO_SEVERITY                                                               0x3fff7bfc34e5
+#define regBIFPLR4_1_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_RP_PIO_SYSERROR                                                               0x3fff7bfc34e6
+#define regBIFPLR4_1_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_RP_PIO_EXCEPTION                                                              0x3fff7bfc34e7
+#define regBIFPLR4_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG0                                                               0x3fff7bfc34e8
+#define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG1                                                               0x3fff7bfc34e9
+#define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG2                                                               0x3fff7bfc34ea
+#define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG3                                                               0x3fff7bfc34eb
+#define regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0                                                            0x3fff7bfc34ed
+#define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1                                                            0x3fff7bfc34ee
+#define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2                                                            0x3fff7bfc34ef
+#define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3                                                            0x3fff7bfc34f0
+#define regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR4_1_PCIE_ESM_CAP_LIST                                                                  0x3fff7bfc34f1
+#define regBIFPLR4_1_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR4_1_PCIE_ESM_HEADER_1                                                                  0x3fff7bfc34f2
+#define regBIFPLR4_1_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR4_1_PCIE_ESM_HEADER_2                                                                  0x3fff7bfc34f3
+#define regBIFPLR4_1_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR4_1_PCIE_ESM_STATUS                                                                    0x3fff7bfc34f3
+#define regBIFPLR4_1_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR4_1_PCIE_ESM_CTRL                                                                      0x3fff7bfc34f4
+#define regBIFPLR4_1_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR4_1_PCIE_ESM_CAP_1                                                                     0x3fff7bfc34f5
+#define regBIFPLR4_1_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR4_1_PCIE_ESM_CAP_2                                                                     0x3fff7bfc34f6
+#define regBIFPLR4_1_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR4_1_PCIE_ESM_CAP_3                                                                     0x3fff7bfc34f7
+#define regBIFPLR4_1_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR4_1_PCIE_ESM_CAP_4                                                                     0x3fff7bfc34f8
+#define regBIFPLR4_1_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR4_1_PCIE_ESM_CAP_5                                                                     0x3fff7bfc34f9
+#define regBIFPLR4_1_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR4_1_PCIE_ESM_CAP_6                                                                     0x3fff7bfc34fa
+#define regBIFPLR4_1_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR4_1_PCIE_ESM_CAP_7                                                                     0x3fff7bfc34fb
+#define regBIFPLR4_1_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR4_1_PCIE_DLF_ENH_CAP_LIST                                                              0x3fff7bfc3500
+#define regBIFPLR4_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR4_1_DATA_LINK_FEATURE_CAP                                                              0x3fff7bfc3501
+#define regBIFPLR4_1_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR4_1_DATA_LINK_FEATURE_STATUS                                                           0x3fff7bfc3502
+#define regBIFPLR4_1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x3fff7bfc3504
+#define regBIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR4_1_LINK_CAP_16GT                                                                      0x3fff7bfc3505
+#define regBIFPLR4_1_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR4_1_LINK_CNTL_16GT                                                                     0x3fff7bfc3506
+#define regBIFPLR4_1_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR4_1_LINK_STATUS_16GT                                                                   0x3fff7bfc3507
+#define regBIFPLR4_1_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR4_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x3fff7bfc3508
+#define regBIFPLR4_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR4_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc3509
+#define regBIFPLR4_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR4_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc350a
+#define regBIFPLR4_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc350c
+#define regBIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc350c
+#define regBIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc350c
+#define regBIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc350c
+#define regBIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc350d
+#define regBIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc350d
+#define regBIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc350d
+#define regBIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc350d
+#define regBIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc350e
+#define regBIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc350e
+#define regBIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc350e
+#define regBIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc350e
+#define regBIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc350f
+#define regBIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc350f
+#define regBIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc350f
+#define regBIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc350f
+#define regBIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST                                                        0x3fff7bfc3510
+#define regBIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR4_1_MARGINING_PORT_CAP                                                                 0x3fff7bfc3511
+#define regBIFPLR4_1_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR4_1_MARGINING_PORT_STATUS                                                              0x3fff7bfc3511
+#define regBIFPLR4_1_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR4_1_LANE_0_MARGINING_LANE_CNTL                                                         0x3fff7bfc3512
+#define regBIFPLR4_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_1_LANE_0_MARGINING_LANE_STATUS                                                       0x3fff7bfc3512
+#define regBIFPLR4_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_1_LANE_1_MARGINING_LANE_CNTL                                                         0x3fff7bfc3513
+#define regBIFPLR4_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_1_LANE_1_MARGINING_LANE_STATUS                                                       0x3fff7bfc3513
+#define regBIFPLR4_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_1_LANE_2_MARGINING_LANE_CNTL                                                         0x3fff7bfc3514
+#define regBIFPLR4_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_1_LANE_2_MARGINING_LANE_STATUS                                                       0x3fff7bfc3514
+#define regBIFPLR4_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_1_LANE_3_MARGINING_LANE_CNTL                                                         0x3fff7bfc3515
+#define regBIFPLR4_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_1_LANE_3_MARGINING_LANE_STATUS                                                       0x3fff7bfc3515
+#define regBIFPLR4_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_1_LANE_4_MARGINING_LANE_CNTL                                                         0x3fff7bfc3516
+#define regBIFPLR4_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_1_LANE_4_MARGINING_LANE_STATUS                                                       0x3fff7bfc3516
+#define regBIFPLR4_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_1_LANE_5_MARGINING_LANE_CNTL                                                         0x3fff7bfc3517
+#define regBIFPLR4_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_1_LANE_5_MARGINING_LANE_STATUS                                                       0x3fff7bfc3517
+#define regBIFPLR4_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_1_LANE_6_MARGINING_LANE_CNTL                                                         0x3fff7bfc3518
+#define regBIFPLR4_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_1_LANE_6_MARGINING_LANE_STATUS                                                       0x3fff7bfc3518
+#define regBIFPLR4_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_1_LANE_7_MARGINING_LANE_CNTL                                                         0x3fff7bfc3519
+#define regBIFPLR4_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_1_LANE_7_MARGINING_LANE_STATUS                                                       0x3fff7bfc3519
+#define regBIFPLR4_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_1_LANE_8_MARGINING_LANE_CNTL                                                         0x3fff7bfc351a
+#define regBIFPLR4_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_1_LANE_8_MARGINING_LANE_STATUS                                                       0x3fff7bfc351a
+#define regBIFPLR4_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_1_LANE_9_MARGINING_LANE_CNTL                                                         0x3fff7bfc351b
+#define regBIFPLR4_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR4_1_LANE_9_MARGINING_LANE_STATUS                                                       0x3fff7bfc351b
+#define regBIFPLR4_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR4_1_LANE_10_MARGINING_LANE_CNTL                                                        0x3fff7bfc351c
+#define regBIFPLR4_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_1_LANE_10_MARGINING_LANE_STATUS                                                      0x3fff7bfc351c
+#define regBIFPLR4_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_11_MARGINING_LANE_CNTL                                                        0x3fff7bfc351d
+#define regBIFPLR4_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_1_LANE_11_MARGINING_LANE_STATUS                                                      0x3fff7bfc351d
+#define regBIFPLR4_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_12_MARGINING_LANE_CNTL                                                        0x3fff7bfc351e
+#define regBIFPLR4_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_1_LANE_12_MARGINING_LANE_STATUS                                                      0x3fff7bfc351e
+#define regBIFPLR4_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_13_MARGINING_LANE_CNTL                                                        0x3fff7bfc351f
+#define regBIFPLR4_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_1_LANE_13_MARGINING_LANE_STATUS                                                      0x3fff7bfc351f
+#define regBIFPLR4_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_14_MARGINING_LANE_CNTL                                                        0x3fff7bfc3520
+#define regBIFPLR4_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_1_LANE_14_MARGINING_LANE_STATUS                                                      0x3fff7bfc3520
+#define regBIFPLR4_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_1_LANE_15_MARGINING_LANE_CNTL                                                        0x3fff7bfc3521
+#define regBIFPLR4_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR4_1_LANE_15_MARGINING_LANE_STATUS                                                      0x3fff7bfc3521
+#define regBIFPLR4_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR4_1_PCIE_CCIX_CAP_LIST                                                                 0x3fff7bfc3522
+#define regBIFPLR4_1_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR4_1_PCIE_CCIX_HEADER_1                                                                 0x3fff7bfc3523
+#define regBIFPLR4_1_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR4_1_PCIE_CCIX_HEADER_2                                                                 0x3fff7bfc3524
+#define regBIFPLR4_1_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR4_1_PCIE_CCIX_CAP                                                                      0x3fff7bfc3524
+#define regBIFPLR4_1_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP                                                             0x3fff7bfc3525
+#define regBIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR4_1_PCIE_CCIX_ESM_OPTL_CAP                                                             0x3fff7bfc3526
+#define regBIFPLR4_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR4_1_PCIE_CCIX_ESM_STATUS                                                               0x3fff7bfc3527
+#define regBIFPLR4_1_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR4_1_PCIE_CCIX_ESM_CNTL                                                                 0x3fff7bfc3528
+#define regBIFPLR4_1_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3529
+#define regBIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3529
+#define regBIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3529
+#define regBIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3529
+#define regBIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc352a
+#define regBIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc352a
+#define regBIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc352a
+#define regBIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc352a
+#define regBIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc352b
+#define regBIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc352b
+#define regBIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc352b
+#define regBIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc352b
+#define regBIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc352c
+#define regBIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc352c
+#define regBIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc352c
+#define regBIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc352c
+#define regBIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc352d
+#define regBIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc352d
+#define regBIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc352d
+#define regBIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc352d
+#define regBIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc352e
+#define regBIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc352e
+#define regBIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc352e
+#define regBIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc352e
+#define regBIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc352f
+#define regBIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc352f
+#define regBIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc352f
+#define regBIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc352f
+#define regBIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3530
+#define regBIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3530
+#define regBIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3530
+#define regBIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3530
+#define regBIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR4_1_PCIE_CCIX_TRANS_CAP                                                                0x3fff7bfc3531
+#define regBIFPLR4_1_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR4_1_PCIE_CCIX_TRANS_CNTL                                                               0x3fff7bfc3532
+#define regBIFPLR4_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+// base address: 0xfffe0000e000
+#define regBIFPLR5_1_VENDOR_ID                                                                          0x3fff7bfc3800
+#define regBIFPLR5_1_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR5_1_DEVICE_ID                                                                          0x3fff7bfc3800
+#define regBIFPLR5_1_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR5_1_COMMAND                                                                            0x3fff7bfc3801
+#define regBIFPLR5_1_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR5_1_STATUS                                                                             0x3fff7bfc3801
+#define regBIFPLR5_1_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR5_1_REVISION_ID                                                                        0x3fff7bfc3802
+#define regBIFPLR5_1_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR5_1_PROG_INTERFACE                                                                     0x3fff7bfc3802
+#define regBIFPLR5_1_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR5_1_SUB_CLASS                                                                          0x3fff7bfc3802
+#define regBIFPLR5_1_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR5_1_BASE_CLASS                                                                         0x3fff7bfc3802
+#define regBIFPLR5_1_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR5_1_CACHE_LINE                                                                         0x3fff7bfc3803
+#define regBIFPLR5_1_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR5_1_LATENCY                                                                            0x3fff7bfc3803
+#define regBIFPLR5_1_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR5_1_HEADER                                                                             0x3fff7bfc3803
+#define regBIFPLR5_1_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR5_1_BIST                                                                               0x3fff7bfc3803
+#define regBIFPLR5_1_BIST_BASE_IDX                                                                      5
+#define regBIFPLR5_1_SUB_BUS_NUMBER_LATENCY                                                             0x3fff7bfc3806
+#define regBIFPLR5_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR5_1_IO_BASE_LIMIT                                                                      0x3fff7bfc3807
+#define regBIFPLR5_1_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR5_1_SECONDARY_STATUS                                                                   0x3fff7bfc3807
+#define regBIFPLR5_1_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR5_1_MEM_BASE_LIMIT                                                                     0x3fff7bfc3808
+#define regBIFPLR5_1_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR5_1_PREF_BASE_LIMIT                                                                    0x3fff7bfc3809
+#define regBIFPLR5_1_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR5_1_PREF_BASE_UPPER                                                                    0x3fff7bfc380a
+#define regBIFPLR5_1_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR5_1_PREF_LIMIT_UPPER                                                                   0x3fff7bfc380b
+#define regBIFPLR5_1_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR5_1_IO_BASE_LIMIT_HI                                                                   0x3fff7bfc380c
+#define regBIFPLR5_1_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR5_1_CAP_PTR                                                                            0x3fff7bfc380d
+#define regBIFPLR5_1_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR5_1_ROM_BASE_ADDR                                                                      0x3fff7bfc380e
+#define regBIFPLR5_1_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR5_1_INTERRUPT_LINE                                                                     0x3fff7bfc380f
+#define regBIFPLR5_1_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR5_1_INTERRUPT_PIN                                                                      0x3fff7bfc380f
+#define regBIFPLR5_1_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR5_1_IRQ_BRIDGE_CNTL                                                                    0x3fff7bfc380f
+#define regBIFPLR5_1_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR5_1_EXT_BRIDGE_CNTL                                                                    0x3fff7bfc3810
+#define regBIFPLR5_1_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR5_1_VENDOR_CAP_LIST                                                                    0x3fff7bfc3812
+#define regBIFPLR5_1_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR5_1_ADAPTER_ID_W                                                                       0x3fff7bfc3813
+#define regBIFPLR5_1_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR5_1_PMI_CAP_LIST                                                                       0x3fff7bfc3814
+#define regBIFPLR5_1_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR5_1_PMI_CAP                                                                            0x3fff7bfc3814
+#define regBIFPLR5_1_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR5_1_PMI_STATUS_CNTL                                                                    0x3fff7bfc3815
+#define regBIFPLR5_1_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR5_1_PCIE_CAP_LIST                                                                      0x3fff7bfc3816
+#define regBIFPLR5_1_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR5_1_PCIE_CAP                                                                           0x3fff7bfc3816
+#define regBIFPLR5_1_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR5_1_DEVICE_CAP                                                                         0x3fff7bfc3817
+#define regBIFPLR5_1_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR5_1_DEVICE_CNTL                                                                        0x3fff7bfc3818
+#define regBIFPLR5_1_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR5_1_DEVICE_STATUS                                                                      0x3fff7bfc3818
+#define regBIFPLR5_1_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR5_1_LINK_CAP                                                                           0x3fff7bfc3819
+#define regBIFPLR5_1_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR5_1_LINK_CNTL                                                                          0x3fff7bfc381a
+#define regBIFPLR5_1_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR5_1_LINK_STATUS                                                                        0x3fff7bfc381a
+#define regBIFPLR5_1_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR5_1_SLOT_CAP                                                                           0x3fff7bfc381b
+#define regBIFPLR5_1_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR5_1_SLOT_CNTL                                                                          0x3fff7bfc381c
+#define regBIFPLR5_1_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR5_1_SLOT_STATUS                                                                        0x3fff7bfc381c
+#define regBIFPLR5_1_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR5_1_ROOT_CNTL                                                                          0x3fff7bfc381d
+#define regBIFPLR5_1_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR5_1_ROOT_CAP                                                                           0x3fff7bfc381d
+#define regBIFPLR5_1_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR5_1_ROOT_STATUS                                                                        0x3fff7bfc381e
+#define regBIFPLR5_1_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR5_1_DEVICE_CAP2                                                                        0x3fff7bfc381f
+#define regBIFPLR5_1_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR5_1_DEVICE_CNTL2                                                                       0x3fff7bfc3820
+#define regBIFPLR5_1_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR5_1_DEVICE_STATUS2                                                                     0x3fff7bfc3820
+#define regBIFPLR5_1_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR5_1_LINK_CAP2                                                                          0x3fff7bfc3821
+#define regBIFPLR5_1_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR5_1_LINK_CNTL2                                                                         0x3fff7bfc3822
+#define regBIFPLR5_1_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR5_1_LINK_STATUS2                                                                       0x3fff7bfc3822
+#define regBIFPLR5_1_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR5_1_SLOT_CAP2                                                                          0x3fff7bfc3823
+#define regBIFPLR5_1_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR5_1_SLOT_CNTL2                                                                         0x3fff7bfc3824
+#define regBIFPLR5_1_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR5_1_SLOT_STATUS2                                                                       0x3fff7bfc3824
+#define regBIFPLR5_1_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR5_1_MSI_CAP_LIST                                                                       0x3fff7bfc3828
+#define regBIFPLR5_1_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR5_1_MSI_MSG_CNTL                                                                       0x3fff7bfc3828
+#define regBIFPLR5_1_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR5_1_MSI_MSG_ADDR_LO                                                                    0x3fff7bfc3829
+#define regBIFPLR5_1_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR5_1_MSI_MSG_ADDR_HI                                                                    0x3fff7bfc382a
+#define regBIFPLR5_1_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR5_1_MSI_MSG_DATA                                                                       0x3fff7bfc382a
+#define regBIFPLR5_1_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR5_1_MSI_MSG_DATA_64                                                                    0x3fff7bfc382b
+#define regBIFPLR5_1_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR5_1_SSID_CAP_LIST                                                                      0x3fff7bfc3830
+#define regBIFPLR5_1_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR5_1_SSID_CAP                                                                           0x3fff7bfc3831
+#define regBIFPLR5_1_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR5_1_MSI_MAP_CAP_LIST                                                                   0x3fff7bfc3832
+#define regBIFPLR5_1_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR5_1_MSI_MAP_CAP                                                                        0x3fff7bfc3832
+#define regBIFPLR5_1_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x3fff7bfc3840
+#define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR                                                           0x3fff7bfc3841
+#define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC1                                                              0x3fff7bfc3842
+#define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC2                                                              0x3fff7bfc3843
+#define regBIFPLR5_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR5_1_PCIE_VC_ENH_CAP_LIST                                                               0x3fff7bfc3844
+#define regBIFPLR5_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_PORT_VC_CAP_REG1                                                              0x3fff7bfc3845
+#define regBIFPLR5_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR5_1_PCIE_PORT_VC_CAP_REG2                                                              0x3fff7bfc3846
+#define regBIFPLR5_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR5_1_PCIE_PORT_VC_CNTL                                                                  0x3fff7bfc3847
+#define regBIFPLR5_1_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR5_1_PCIE_PORT_VC_STATUS                                                                0x3fff7bfc3847
+#define regBIFPLR5_1_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR5_1_PCIE_VC0_RESOURCE_CAP                                                              0x3fff7bfc3848
+#define regBIFPLR5_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR5_1_PCIE_VC0_RESOURCE_CNTL                                                             0x3fff7bfc3849
+#define regBIFPLR5_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR5_1_PCIE_VC0_RESOURCE_STATUS                                                           0x3fff7bfc384a
+#define regBIFPLR5_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR5_1_PCIE_VC1_RESOURCE_CAP                                                              0x3fff7bfc384b
+#define regBIFPLR5_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR5_1_PCIE_VC1_RESOURCE_CNTL                                                             0x3fff7bfc384c
+#define regBIFPLR5_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR5_1_PCIE_VC1_RESOURCE_STATUS                                                           0x3fff7bfc384d
+#define regBIFPLR5_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x3fff7bfc3850
+#define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1                                                            0x3fff7bfc3851
+#define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2                                                            0x3fff7bfc3852
+#define regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x3fff7bfc3854
+#define regBIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_UNCORR_ERR_STATUS                                                             0x3fff7bfc3855
+#define regBIFPLR5_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR5_1_PCIE_UNCORR_ERR_MASK                                                               0x3fff7bfc3856
+#define regBIFPLR5_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY                                                           0x3fff7bfc3857
+#define regBIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR5_1_PCIE_CORR_ERR_STATUS                                                               0x3fff7bfc3858
+#define regBIFPLR5_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_CORR_ERR_MASK                                                                 0x3fff7bfc3859
+#define regBIFPLR5_1_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL                                                              0x3fff7bfc385a
+#define regBIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR5_1_PCIE_HDR_LOG0                                                                      0x3fff7bfc385b
+#define regBIFPLR5_1_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR5_1_PCIE_HDR_LOG1                                                                      0x3fff7bfc385c
+#define regBIFPLR5_1_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR5_1_PCIE_HDR_LOG2                                                                      0x3fff7bfc385d
+#define regBIFPLR5_1_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR5_1_PCIE_HDR_LOG3                                                                      0x3fff7bfc385e
+#define regBIFPLR5_1_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR5_1_PCIE_ROOT_ERR_CMD                                                                  0x3fff7bfc385f
+#define regBIFPLR5_1_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR5_1_PCIE_ROOT_ERR_STATUS                                                               0x3fff7bfc3860
+#define regBIFPLR5_1_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_ERR_SRC_ID                                                                    0x3fff7bfc3861
+#define regBIFPLR5_1_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG0                                                               0x3fff7bfc3862
+#define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG1                                                               0x3fff7bfc3863
+#define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG2                                                               0x3fff7bfc3864
+#define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG3                                                               0x3fff7bfc3865
+#define regBIFPLR5_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x3fff7bfc389c
+#define regBIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR5_1_PCIE_LINK_CNTL3                                                                    0x3fff7bfc389d
+#define regBIFPLR5_1_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR5_1_PCIE_LANE_ERROR_STATUS                                                             0x3fff7bfc389e
+#define regBIFPLR5_1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x3fff7bfc389f
+#define regBIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x3fff7bfc389f
+#define regBIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x3fff7bfc38a0
+#define regBIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x3fff7bfc38a0
+#define regBIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x3fff7bfc38a1
+#define regBIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x3fff7bfc38a1
+#define regBIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x3fff7bfc38a2
+#define regBIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x3fff7bfc38a2
+#define regBIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x3fff7bfc38a3
+#define regBIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x3fff7bfc38a3
+#define regBIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x3fff7bfc38a4
+#define regBIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x3fff7bfc38a4
+#define regBIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x3fff7bfc38a5
+#define regBIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x3fff7bfc38a5
+#define regBIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x3fff7bfc38a6
+#define regBIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x3fff7bfc38a6
+#define regBIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR5_1_PCIE_ACS_ENH_CAP_LIST                                                              0x3fff7bfc38a8
+#define regBIFPLR5_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR5_1_PCIE_ACS_CAP                                                                       0x3fff7bfc38a9
+#define regBIFPLR5_1_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR5_1_PCIE_ACS_CNTL                                                                      0x3fff7bfc38a9
+#define regBIFPLR5_1_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR5_1_PCIE_MC_ENH_CAP_LIST                                                               0x3fff7bfc38bc
+#define regBIFPLR5_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_MC_CAP                                                                        0x3fff7bfc38bd
+#define regBIFPLR5_1_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR5_1_PCIE_MC_CNTL                                                                       0x3fff7bfc38bd
+#define regBIFPLR5_1_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR5_1_PCIE_MC_ADDR0                                                                      0x3fff7bfc38be
+#define regBIFPLR5_1_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR5_1_PCIE_MC_ADDR1                                                                      0x3fff7bfc38bf
+#define regBIFPLR5_1_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR5_1_PCIE_MC_RCV0                                                                       0x3fff7bfc38c0
+#define regBIFPLR5_1_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR5_1_PCIE_MC_RCV1                                                                       0x3fff7bfc38c1
+#define regBIFPLR5_1_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR5_1_PCIE_MC_BLOCK_ALL0                                                                 0x3fff7bfc38c2
+#define regBIFPLR5_1_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR5_1_PCIE_MC_BLOCK_ALL1                                                                 0x3fff7bfc38c3
+#define regBIFPLR5_1_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x3fff7bfc38c4
+#define regBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x3fff7bfc38c5
+#define regBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR5_1_PCIE_MC_OVERLAY_BAR0                                                               0x3fff7bfc38c6
+#define regBIFPLR5_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_MC_OVERLAY_BAR1                                                               0x3fff7bfc38c7
+#define regBIFPLR5_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST                                                            0x3fff7bfc38dc
+#define regBIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR5_1_PCIE_L1_PM_SUB_CAP                                                                 0x3fff7bfc38dd
+#define regBIFPLR5_1_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR5_1_PCIE_L1_PM_SUB_CNTL                                                                0x3fff7bfc38de
+#define regBIFPLR5_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR5_1_PCIE_L1_PM_SUB_CNTL2                                                               0x3fff7bfc38df
+#define regBIFPLR5_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_DPC_ENH_CAP_LIST                                                              0x3fff7bfc38e0
+#define regBIFPLR5_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR5_1_PCIE_DPC_CAP_LIST                                                                  0x3fff7bfc38e1
+#define regBIFPLR5_1_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR5_1_PCIE_DPC_CNTL                                                                      0x3fff7bfc38e1
+#define regBIFPLR5_1_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR5_1_PCIE_DPC_STATUS                                                                    0x3fff7bfc38e2
+#define regBIFPLR5_1_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID                                                           0x3fff7bfc38e2
+#define regBIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR5_1_PCIE_RP_PIO_STATUS                                                                 0x3fff7bfc38e3
+#define regBIFPLR5_1_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR5_1_PCIE_RP_PIO_MASK                                                                   0x3fff7bfc38e4
+#define regBIFPLR5_1_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR5_1_PCIE_RP_PIO_SEVERITY                                                               0x3fff7bfc38e5
+#define regBIFPLR5_1_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_RP_PIO_SYSERROR                                                               0x3fff7bfc38e6
+#define regBIFPLR5_1_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_RP_PIO_EXCEPTION                                                              0x3fff7bfc38e7
+#define regBIFPLR5_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG0                                                               0x3fff7bfc38e8
+#define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG1                                                               0x3fff7bfc38e9
+#define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG2                                                               0x3fff7bfc38ea
+#define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG3                                                               0x3fff7bfc38eb
+#define regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0                                                            0x3fff7bfc38ed
+#define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1                                                            0x3fff7bfc38ee
+#define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2                                                            0x3fff7bfc38ef
+#define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3                                                            0x3fff7bfc38f0
+#define regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR5_1_PCIE_ESM_CAP_LIST                                                                  0x3fff7bfc38f1
+#define regBIFPLR5_1_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR5_1_PCIE_ESM_HEADER_1                                                                  0x3fff7bfc38f2
+#define regBIFPLR5_1_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR5_1_PCIE_ESM_HEADER_2                                                                  0x3fff7bfc38f3
+#define regBIFPLR5_1_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR5_1_PCIE_ESM_STATUS                                                                    0x3fff7bfc38f3
+#define regBIFPLR5_1_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR5_1_PCIE_ESM_CTRL                                                                      0x3fff7bfc38f4
+#define regBIFPLR5_1_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR5_1_PCIE_ESM_CAP_1                                                                     0x3fff7bfc38f5
+#define regBIFPLR5_1_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR5_1_PCIE_ESM_CAP_2                                                                     0x3fff7bfc38f6
+#define regBIFPLR5_1_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR5_1_PCIE_ESM_CAP_3                                                                     0x3fff7bfc38f7
+#define regBIFPLR5_1_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR5_1_PCIE_ESM_CAP_4                                                                     0x3fff7bfc38f8
+#define regBIFPLR5_1_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR5_1_PCIE_ESM_CAP_5                                                                     0x3fff7bfc38f9
+#define regBIFPLR5_1_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR5_1_PCIE_ESM_CAP_6                                                                     0x3fff7bfc38fa
+#define regBIFPLR5_1_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR5_1_PCIE_ESM_CAP_7                                                                     0x3fff7bfc38fb
+#define regBIFPLR5_1_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR5_1_PCIE_DLF_ENH_CAP_LIST                                                              0x3fff7bfc3900
+#define regBIFPLR5_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR5_1_DATA_LINK_FEATURE_CAP                                                              0x3fff7bfc3901
+#define regBIFPLR5_1_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR5_1_DATA_LINK_FEATURE_STATUS                                                           0x3fff7bfc3902
+#define regBIFPLR5_1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x3fff7bfc3904
+#define regBIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR5_1_LINK_CAP_16GT                                                                      0x3fff7bfc3905
+#define regBIFPLR5_1_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR5_1_LINK_CNTL_16GT                                                                     0x3fff7bfc3906
+#define regBIFPLR5_1_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR5_1_LINK_STATUS_16GT                                                                   0x3fff7bfc3907
+#define regBIFPLR5_1_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR5_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x3fff7bfc3908
+#define regBIFPLR5_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR5_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc3909
+#define regBIFPLR5_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR5_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc390a
+#define regBIFPLR5_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc390c
+#define regBIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc390c
+#define regBIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc390c
+#define regBIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc390c
+#define regBIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc390d
+#define regBIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc390d
+#define regBIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc390d
+#define regBIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc390d
+#define regBIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc390e
+#define regBIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc390e
+#define regBIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc390e
+#define regBIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc390e
+#define regBIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc390f
+#define regBIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc390f
+#define regBIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc390f
+#define regBIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc390f
+#define regBIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST                                                        0x3fff7bfc3910
+#define regBIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR5_1_MARGINING_PORT_CAP                                                                 0x3fff7bfc3911
+#define regBIFPLR5_1_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR5_1_MARGINING_PORT_STATUS                                                              0x3fff7bfc3911
+#define regBIFPLR5_1_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR5_1_LANE_0_MARGINING_LANE_CNTL                                                         0x3fff7bfc3912
+#define regBIFPLR5_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_1_LANE_0_MARGINING_LANE_STATUS                                                       0x3fff7bfc3912
+#define regBIFPLR5_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_1_LANE_1_MARGINING_LANE_CNTL                                                         0x3fff7bfc3913
+#define regBIFPLR5_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_1_LANE_1_MARGINING_LANE_STATUS                                                       0x3fff7bfc3913
+#define regBIFPLR5_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_1_LANE_2_MARGINING_LANE_CNTL                                                         0x3fff7bfc3914
+#define regBIFPLR5_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_1_LANE_2_MARGINING_LANE_STATUS                                                       0x3fff7bfc3914
+#define regBIFPLR5_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_1_LANE_3_MARGINING_LANE_CNTL                                                         0x3fff7bfc3915
+#define regBIFPLR5_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_1_LANE_3_MARGINING_LANE_STATUS                                                       0x3fff7bfc3915
+#define regBIFPLR5_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_1_LANE_4_MARGINING_LANE_CNTL                                                         0x3fff7bfc3916
+#define regBIFPLR5_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_1_LANE_4_MARGINING_LANE_STATUS                                                       0x3fff7bfc3916
+#define regBIFPLR5_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_1_LANE_5_MARGINING_LANE_CNTL                                                         0x3fff7bfc3917
+#define regBIFPLR5_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_1_LANE_5_MARGINING_LANE_STATUS                                                       0x3fff7bfc3917
+#define regBIFPLR5_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_1_LANE_6_MARGINING_LANE_CNTL                                                         0x3fff7bfc3918
+#define regBIFPLR5_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_1_LANE_6_MARGINING_LANE_STATUS                                                       0x3fff7bfc3918
+#define regBIFPLR5_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_1_LANE_7_MARGINING_LANE_CNTL                                                         0x3fff7bfc3919
+#define regBIFPLR5_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_1_LANE_7_MARGINING_LANE_STATUS                                                       0x3fff7bfc3919
+#define regBIFPLR5_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_1_LANE_8_MARGINING_LANE_CNTL                                                         0x3fff7bfc391a
+#define regBIFPLR5_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_1_LANE_8_MARGINING_LANE_STATUS                                                       0x3fff7bfc391a
+#define regBIFPLR5_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_1_LANE_9_MARGINING_LANE_CNTL                                                         0x3fff7bfc391b
+#define regBIFPLR5_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR5_1_LANE_9_MARGINING_LANE_STATUS                                                       0x3fff7bfc391b
+#define regBIFPLR5_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR5_1_LANE_10_MARGINING_LANE_CNTL                                                        0x3fff7bfc391c
+#define regBIFPLR5_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_1_LANE_10_MARGINING_LANE_STATUS                                                      0x3fff7bfc391c
+#define regBIFPLR5_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_11_MARGINING_LANE_CNTL                                                        0x3fff7bfc391d
+#define regBIFPLR5_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_1_LANE_11_MARGINING_LANE_STATUS                                                      0x3fff7bfc391d
+#define regBIFPLR5_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_12_MARGINING_LANE_CNTL                                                        0x3fff7bfc391e
+#define regBIFPLR5_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_1_LANE_12_MARGINING_LANE_STATUS                                                      0x3fff7bfc391e
+#define regBIFPLR5_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_13_MARGINING_LANE_CNTL                                                        0x3fff7bfc391f
+#define regBIFPLR5_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_1_LANE_13_MARGINING_LANE_STATUS                                                      0x3fff7bfc391f
+#define regBIFPLR5_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_14_MARGINING_LANE_CNTL                                                        0x3fff7bfc3920
+#define regBIFPLR5_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_1_LANE_14_MARGINING_LANE_STATUS                                                      0x3fff7bfc3920
+#define regBIFPLR5_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_1_LANE_15_MARGINING_LANE_CNTL                                                        0x3fff7bfc3921
+#define regBIFPLR5_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR5_1_LANE_15_MARGINING_LANE_STATUS                                                      0x3fff7bfc3921
+#define regBIFPLR5_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR5_1_PCIE_CCIX_CAP_LIST                                                                 0x3fff7bfc3922
+#define regBIFPLR5_1_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR5_1_PCIE_CCIX_HEADER_1                                                                 0x3fff7bfc3923
+#define regBIFPLR5_1_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR5_1_PCIE_CCIX_HEADER_2                                                                 0x3fff7bfc3924
+#define regBIFPLR5_1_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR5_1_PCIE_CCIX_CAP                                                                      0x3fff7bfc3924
+#define regBIFPLR5_1_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP                                                             0x3fff7bfc3925
+#define regBIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR5_1_PCIE_CCIX_ESM_OPTL_CAP                                                             0x3fff7bfc3926
+#define regBIFPLR5_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR5_1_PCIE_CCIX_ESM_STATUS                                                               0x3fff7bfc3927
+#define regBIFPLR5_1_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR5_1_PCIE_CCIX_ESM_CNTL                                                                 0x3fff7bfc3928
+#define regBIFPLR5_1_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3929
+#define regBIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3929
+#define regBIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3929
+#define regBIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3929
+#define regBIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc392a
+#define regBIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc392a
+#define regBIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc392a
+#define regBIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc392a
+#define regBIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc392b
+#define regBIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc392b
+#define regBIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc392b
+#define regBIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc392b
+#define regBIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc392c
+#define regBIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc392c
+#define regBIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc392c
+#define regBIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc392c
+#define regBIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc392d
+#define regBIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc392d
+#define regBIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc392d
+#define regBIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc392d
+#define regBIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc392e
+#define regBIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc392e
+#define regBIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc392e
+#define regBIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc392e
+#define regBIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc392f
+#define regBIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc392f
+#define regBIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc392f
+#define regBIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc392f
+#define regBIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3930
+#define regBIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3930
+#define regBIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3930
+#define regBIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3930
+#define regBIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR5_1_PCIE_CCIX_TRANS_CAP                                                                0x3fff7bfc3931
+#define regBIFPLR5_1_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR5_1_PCIE_CCIX_TRANS_CNTL                                                               0x3fff7bfc3932
+#define regBIFPLR5_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+// base address: 0xfffe0000f000
+#define regBIFPLR6_1_VENDOR_ID                                                                          0x3fff7bfc3c00
+#define regBIFPLR6_1_VENDOR_ID_BASE_IDX                                                                 5
+#define regBIFPLR6_1_DEVICE_ID                                                                          0x3fff7bfc3c00
+#define regBIFPLR6_1_DEVICE_ID_BASE_IDX                                                                 5
+#define regBIFPLR6_1_COMMAND                                                                            0x3fff7bfc3c01
+#define regBIFPLR6_1_COMMAND_BASE_IDX                                                                   5
+#define regBIFPLR6_1_STATUS                                                                             0x3fff7bfc3c01
+#define regBIFPLR6_1_STATUS_BASE_IDX                                                                    5
+#define regBIFPLR6_1_REVISION_ID                                                                        0x3fff7bfc3c02
+#define regBIFPLR6_1_REVISION_ID_BASE_IDX                                                               5
+#define regBIFPLR6_1_PROG_INTERFACE                                                                     0x3fff7bfc3c02
+#define regBIFPLR6_1_PROG_INTERFACE_BASE_IDX                                                            5
+#define regBIFPLR6_1_SUB_CLASS                                                                          0x3fff7bfc3c02
+#define regBIFPLR6_1_SUB_CLASS_BASE_IDX                                                                 5
+#define regBIFPLR6_1_BASE_CLASS                                                                         0x3fff7bfc3c02
+#define regBIFPLR6_1_BASE_CLASS_BASE_IDX                                                                5
+#define regBIFPLR6_1_CACHE_LINE                                                                         0x3fff7bfc3c03
+#define regBIFPLR6_1_CACHE_LINE_BASE_IDX                                                                5
+#define regBIFPLR6_1_LATENCY                                                                            0x3fff7bfc3c03
+#define regBIFPLR6_1_LATENCY_BASE_IDX                                                                   5
+#define regBIFPLR6_1_HEADER                                                                             0x3fff7bfc3c03
+#define regBIFPLR6_1_HEADER_BASE_IDX                                                                    5
+#define regBIFPLR6_1_BIST                                                                               0x3fff7bfc3c03
+#define regBIFPLR6_1_BIST_BASE_IDX                                                                      5
+#define regBIFPLR6_1_SUB_BUS_NUMBER_LATENCY                                                             0x3fff7bfc3c06
+#define regBIFPLR6_1_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                    5
+#define regBIFPLR6_1_IO_BASE_LIMIT                                                                      0x3fff7bfc3c07
+#define regBIFPLR6_1_IO_BASE_LIMIT_BASE_IDX                                                             5
+#define regBIFPLR6_1_SECONDARY_STATUS                                                                   0x3fff7bfc3c07
+#define regBIFPLR6_1_SECONDARY_STATUS_BASE_IDX                                                          5
+#define regBIFPLR6_1_MEM_BASE_LIMIT                                                                     0x3fff7bfc3c08
+#define regBIFPLR6_1_MEM_BASE_LIMIT_BASE_IDX                                                            5
+#define regBIFPLR6_1_PREF_BASE_LIMIT                                                                    0x3fff7bfc3c09
+#define regBIFPLR6_1_PREF_BASE_LIMIT_BASE_IDX                                                           5
+#define regBIFPLR6_1_PREF_BASE_UPPER                                                                    0x3fff7bfc3c0a
+#define regBIFPLR6_1_PREF_BASE_UPPER_BASE_IDX                                                           5
+#define regBIFPLR6_1_PREF_LIMIT_UPPER                                                                   0x3fff7bfc3c0b
+#define regBIFPLR6_1_PREF_LIMIT_UPPER_BASE_IDX                                                          5
+#define regBIFPLR6_1_IO_BASE_LIMIT_HI                                                                   0x3fff7bfc3c0c
+#define regBIFPLR6_1_IO_BASE_LIMIT_HI_BASE_IDX                                                          5
+#define regBIFPLR6_1_CAP_PTR                                                                            0x3fff7bfc3c0d
+#define regBIFPLR6_1_CAP_PTR_BASE_IDX                                                                   5
+#define regBIFPLR6_1_ROM_BASE_ADDR                                                                      0x3fff7bfc3c0e
+#define regBIFPLR6_1_ROM_BASE_ADDR_BASE_IDX                                                             5
+#define regBIFPLR6_1_INTERRUPT_LINE                                                                     0x3fff7bfc3c0f
+#define regBIFPLR6_1_INTERRUPT_LINE_BASE_IDX                                                            5
+#define regBIFPLR6_1_INTERRUPT_PIN                                                                      0x3fff7bfc3c0f
+#define regBIFPLR6_1_INTERRUPT_PIN_BASE_IDX                                                             5
+#define regBIFPLR6_1_IRQ_BRIDGE_CNTL                                                                    0x3fff7bfc3c0f
+#define regBIFPLR6_1_IRQ_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR6_1_EXT_BRIDGE_CNTL                                                                    0x3fff7bfc3c10
+#define regBIFPLR6_1_EXT_BRIDGE_CNTL_BASE_IDX                                                           5
+#define regBIFPLR6_1_VENDOR_CAP_LIST                                                                    0x3fff7bfc3c12
+#define regBIFPLR6_1_VENDOR_CAP_LIST_BASE_IDX                                                           5
+#define regBIFPLR6_1_ADAPTER_ID_W                                                                       0x3fff7bfc3c13
+#define regBIFPLR6_1_ADAPTER_ID_W_BASE_IDX                                                              5
+#define regBIFPLR6_1_PMI_CAP_LIST                                                                       0x3fff7bfc3c14
+#define regBIFPLR6_1_PMI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR6_1_PMI_CAP                                                                            0x3fff7bfc3c14
+#define regBIFPLR6_1_PMI_CAP_BASE_IDX                                                                   5
+#define regBIFPLR6_1_PMI_STATUS_CNTL                                                                    0x3fff7bfc3c15
+#define regBIFPLR6_1_PMI_STATUS_CNTL_BASE_IDX                                                           5
+#define regBIFPLR6_1_PCIE_CAP_LIST                                                                      0x3fff7bfc3c16
+#define regBIFPLR6_1_PCIE_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR6_1_PCIE_CAP                                                                           0x3fff7bfc3c16
+#define regBIFPLR6_1_PCIE_CAP_BASE_IDX                                                                  5
+#define regBIFPLR6_1_DEVICE_CAP                                                                         0x3fff7bfc3c17
+#define regBIFPLR6_1_DEVICE_CAP_BASE_IDX                                                                5
+#define regBIFPLR6_1_DEVICE_CNTL                                                                        0x3fff7bfc3c18
+#define regBIFPLR6_1_DEVICE_CNTL_BASE_IDX                                                               5
+#define regBIFPLR6_1_DEVICE_STATUS                                                                      0x3fff7bfc3c18
+#define regBIFPLR6_1_DEVICE_STATUS_BASE_IDX                                                             5
+#define regBIFPLR6_1_LINK_CAP                                                                           0x3fff7bfc3c19
+#define regBIFPLR6_1_LINK_CAP_BASE_IDX                                                                  5
+#define regBIFPLR6_1_LINK_CNTL                                                                          0x3fff7bfc3c1a
+#define regBIFPLR6_1_LINK_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR6_1_LINK_STATUS                                                                        0x3fff7bfc3c1a
+#define regBIFPLR6_1_LINK_STATUS_BASE_IDX                                                               5
+#define regBIFPLR6_1_SLOT_CAP                                                                           0x3fff7bfc3c1b
+#define regBIFPLR6_1_SLOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR6_1_SLOT_CNTL                                                                          0x3fff7bfc3c1c
+#define regBIFPLR6_1_SLOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR6_1_SLOT_STATUS                                                                        0x3fff7bfc3c1c
+#define regBIFPLR6_1_SLOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR6_1_ROOT_CNTL                                                                          0x3fff7bfc3c1d
+#define regBIFPLR6_1_ROOT_CNTL_BASE_IDX                                                                 5
+#define regBIFPLR6_1_ROOT_CAP                                                                           0x3fff7bfc3c1d
+#define regBIFPLR6_1_ROOT_CAP_BASE_IDX                                                                  5
+#define regBIFPLR6_1_ROOT_STATUS                                                                        0x3fff7bfc3c1e
+#define regBIFPLR6_1_ROOT_STATUS_BASE_IDX                                                               5
+#define regBIFPLR6_1_DEVICE_CAP2                                                                        0x3fff7bfc3c1f
+#define regBIFPLR6_1_DEVICE_CAP2_BASE_IDX                                                               5
+#define regBIFPLR6_1_DEVICE_CNTL2                                                                       0x3fff7bfc3c20
+#define regBIFPLR6_1_DEVICE_CNTL2_BASE_IDX                                                              5
+#define regBIFPLR6_1_DEVICE_STATUS2                                                                     0x3fff7bfc3c20
+#define regBIFPLR6_1_DEVICE_STATUS2_BASE_IDX                                                            5
+#define regBIFPLR6_1_LINK_CAP2                                                                          0x3fff7bfc3c21
+#define regBIFPLR6_1_LINK_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR6_1_LINK_CNTL2                                                                         0x3fff7bfc3c22
+#define regBIFPLR6_1_LINK_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR6_1_LINK_STATUS2                                                                       0x3fff7bfc3c22
+#define regBIFPLR6_1_LINK_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR6_1_SLOT_CAP2                                                                          0x3fff7bfc3c23
+#define regBIFPLR6_1_SLOT_CAP2_BASE_IDX                                                                 5
+#define regBIFPLR6_1_SLOT_CNTL2                                                                         0x3fff7bfc3c24
+#define regBIFPLR6_1_SLOT_CNTL2_BASE_IDX                                                                5
+#define regBIFPLR6_1_SLOT_STATUS2                                                                       0x3fff7bfc3c24
+#define regBIFPLR6_1_SLOT_STATUS2_BASE_IDX                                                              5
+#define regBIFPLR6_1_MSI_CAP_LIST                                                                       0x3fff7bfc3c28
+#define regBIFPLR6_1_MSI_CAP_LIST_BASE_IDX                                                              5
+#define regBIFPLR6_1_MSI_MSG_CNTL                                                                       0x3fff7bfc3c28
+#define regBIFPLR6_1_MSI_MSG_CNTL_BASE_IDX                                                              5
+#define regBIFPLR6_1_MSI_MSG_ADDR_LO                                                                    0x3fff7bfc3c29
+#define regBIFPLR6_1_MSI_MSG_ADDR_LO_BASE_IDX                                                           5
+#define regBIFPLR6_1_MSI_MSG_ADDR_HI                                                                    0x3fff7bfc3c2a
+#define regBIFPLR6_1_MSI_MSG_ADDR_HI_BASE_IDX                                                           5
+#define regBIFPLR6_1_MSI_MSG_DATA                                                                       0x3fff7bfc3c2a
+#define regBIFPLR6_1_MSI_MSG_DATA_BASE_IDX                                                              5
+#define regBIFPLR6_1_MSI_MSG_DATA_64                                                                    0x3fff7bfc3c2b
+#define regBIFPLR6_1_MSI_MSG_DATA_64_BASE_IDX                                                           5
+#define regBIFPLR6_1_SSID_CAP_LIST                                                                      0x3fff7bfc3c30
+#define regBIFPLR6_1_SSID_CAP_LIST_BASE_IDX                                                             5
+#define regBIFPLR6_1_SSID_CAP                                                                           0x3fff7bfc3c31
+#define regBIFPLR6_1_SSID_CAP_BASE_IDX                                                                  5
+#define regBIFPLR6_1_MSI_MAP_CAP_LIST                                                                   0x3fff7bfc3c32
+#define regBIFPLR6_1_MSI_MAP_CAP_LIST_BASE_IDX                                                          5
+#define regBIFPLR6_1_MSI_MAP_CAP                                                                        0x3fff7bfc3c32
+#define regBIFPLR6_1_MSI_MAP_CAP_BASE_IDX                                                               5
+#define regBIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                                  0x3fff7bfc3c40
+#define regBIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR                                                           0x3fff7bfc3c41
+#define regBIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                                  5
+#define regBIFPLR6_1_PCIE_VENDOR_SPECIFIC1                                                              0x3fff7bfc3c42
+#define regBIFPLR6_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                                     5
+#define regBIFPLR6_1_PCIE_VENDOR_SPECIFIC2                                                              0x3fff7bfc3c43
+#define regBIFPLR6_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                                     5
+#define regBIFPLR6_1_PCIE_VC_ENH_CAP_LIST                                                               0x3fff7bfc3c44
+#define regBIFPLR6_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_PORT_VC_CAP_REG1                                                              0x3fff7bfc3c45
+#define regBIFPLR6_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                                     5
+#define regBIFPLR6_1_PCIE_PORT_VC_CAP_REG2                                                              0x3fff7bfc3c46
+#define regBIFPLR6_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                                     5
+#define regBIFPLR6_1_PCIE_PORT_VC_CNTL                                                                  0x3fff7bfc3c47
+#define regBIFPLR6_1_PCIE_PORT_VC_CNTL_BASE_IDX                                                         5
+#define regBIFPLR6_1_PCIE_PORT_VC_STATUS                                                                0x3fff7bfc3c47
+#define regBIFPLR6_1_PCIE_PORT_VC_STATUS_BASE_IDX                                                       5
+#define regBIFPLR6_1_PCIE_VC0_RESOURCE_CAP                                                              0x3fff7bfc3c48
+#define regBIFPLR6_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR6_1_PCIE_VC0_RESOURCE_CNTL                                                             0x3fff7bfc3c49
+#define regBIFPLR6_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR6_1_PCIE_VC0_RESOURCE_STATUS                                                           0x3fff7bfc3c4a
+#define regBIFPLR6_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR6_1_PCIE_VC1_RESOURCE_CAP                                                              0x3fff7bfc3c4b
+#define regBIFPLR6_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                                     5
+#define regBIFPLR6_1_PCIE_VC1_RESOURCE_CNTL                                                             0x3fff7bfc3c4c
+#define regBIFPLR6_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                                    5
+#define regBIFPLR6_1_PCIE_VC1_RESOURCE_STATUS                                                           0x3fff7bfc3c4d
+#define regBIFPLR6_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                                   0x3fff7bfc3c50
+#define regBIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                          5
+#define regBIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1                                                            0x3fff7bfc3c51
+#define regBIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                                   5
+#define regBIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2                                                            0x3fff7bfc3c52
+#define regBIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                                   5
+#define regBIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                      0x3fff7bfc3c54
+#define regBIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_UNCORR_ERR_STATUS                                                             0x3fff7bfc3c55
+#define regBIFPLR6_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR6_1_PCIE_UNCORR_ERR_MASK                                                               0x3fff7bfc3c56
+#define regBIFPLR6_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY                                                           0x3fff7bfc3c57
+#define regBIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                                  5
+#define regBIFPLR6_1_PCIE_CORR_ERR_STATUS                                                               0x3fff7bfc3c58
+#define regBIFPLR6_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_CORR_ERR_MASK                                                                 0x3fff7bfc3c59
+#define regBIFPLR6_1_PCIE_CORR_ERR_MASK_BASE_IDX                                                        5
+#define regBIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL                                                              0x3fff7bfc3c5a
+#define regBIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                                     5
+#define regBIFPLR6_1_PCIE_HDR_LOG0                                                                      0x3fff7bfc3c5b
+#define regBIFPLR6_1_PCIE_HDR_LOG0_BASE_IDX                                                             5
+#define regBIFPLR6_1_PCIE_HDR_LOG1                                                                      0x3fff7bfc3c5c
+#define regBIFPLR6_1_PCIE_HDR_LOG1_BASE_IDX                                                             5
+#define regBIFPLR6_1_PCIE_HDR_LOG2                                                                      0x3fff7bfc3c5d
+#define regBIFPLR6_1_PCIE_HDR_LOG2_BASE_IDX                                                             5
+#define regBIFPLR6_1_PCIE_HDR_LOG3                                                                      0x3fff7bfc3c5e
+#define regBIFPLR6_1_PCIE_HDR_LOG3_BASE_IDX                                                             5
+#define regBIFPLR6_1_PCIE_ROOT_ERR_CMD                                                                  0x3fff7bfc3c5f
+#define regBIFPLR6_1_PCIE_ROOT_ERR_CMD_BASE_IDX                                                         5
+#define regBIFPLR6_1_PCIE_ROOT_ERR_STATUS                                                               0x3fff7bfc3c60
+#define regBIFPLR6_1_PCIE_ROOT_ERR_STATUS_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_ERR_SRC_ID                                                                    0x3fff7bfc3c61
+#define regBIFPLR6_1_PCIE_ERR_SRC_ID_BASE_IDX                                                           5
+#define regBIFPLR6_1_PCIE_TLP_PREFIX_LOG0                                                               0x3fff7bfc3c62
+#define regBIFPLR6_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_TLP_PREFIX_LOG1                                                               0x3fff7bfc3c63
+#define regBIFPLR6_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_TLP_PREFIX_LOG2                                                               0x3fff7bfc3c64
+#define regBIFPLR6_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_TLP_PREFIX_LOG3                                                               0x3fff7bfc3c65
+#define regBIFPLR6_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST                                                        0x3fff7bfc3c9c
+#define regBIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR6_1_PCIE_LINK_CNTL3                                                                    0x3fff7bfc3c9d
+#define regBIFPLR6_1_PCIE_LINK_CNTL3_BASE_IDX                                                           5
+#define regBIFPLR6_1_PCIE_LANE_ERROR_STATUS                                                             0x3fff7bfc3c9e
+#define regBIFPLR6_1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                                    5
+#define regBIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL                                                      0x3fff7bfc3c9f
+#define regBIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL                                                      0x3fff7bfc3c9f
+#define regBIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL                                                      0x3fff7bfc3ca0
+#define regBIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL                                                      0x3fff7bfc3ca0
+#define regBIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL                                                      0x3fff7bfc3ca1
+#define regBIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL                                                      0x3fff7bfc3ca1
+#define regBIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL                                                      0x3fff7bfc3ca2
+#define regBIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL                                                      0x3fff7bfc3ca2
+#define regBIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL                                                      0x3fff7bfc3ca3
+#define regBIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL                                                      0x3fff7bfc3ca3
+#define regBIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL                                                     0x3fff7bfc3ca4
+#define regBIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL                                                     0x3fff7bfc3ca4
+#define regBIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL                                                     0x3fff7bfc3ca5
+#define regBIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL                                                     0x3fff7bfc3ca5
+#define regBIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL                                                     0x3fff7bfc3ca6
+#define regBIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL                                                     0x3fff7bfc3ca6
+#define regBIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                            5
+#define regBIFPLR6_1_PCIE_ACS_ENH_CAP_LIST                                                              0x3fff7bfc3ca8
+#define regBIFPLR6_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR6_1_PCIE_ACS_CAP                                                                       0x3fff7bfc3ca9
+#define regBIFPLR6_1_PCIE_ACS_CAP_BASE_IDX                                                              5
+#define regBIFPLR6_1_PCIE_ACS_CNTL                                                                      0x3fff7bfc3ca9
+#define regBIFPLR6_1_PCIE_ACS_CNTL_BASE_IDX                                                             5
+#define regBIFPLR6_1_PCIE_MC_ENH_CAP_LIST                                                               0x3fff7bfc3cbc
+#define regBIFPLR6_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_MC_CAP                                                                        0x3fff7bfc3cbd
+#define regBIFPLR6_1_PCIE_MC_CAP_BASE_IDX                                                               5
+#define regBIFPLR6_1_PCIE_MC_CNTL                                                                       0x3fff7bfc3cbd
+#define regBIFPLR6_1_PCIE_MC_CNTL_BASE_IDX                                                              5
+#define regBIFPLR6_1_PCIE_MC_ADDR0                                                                      0x3fff7bfc3cbe
+#define regBIFPLR6_1_PCIE_MC_ADDR0_BASE_IDX                                                             5
+#define regBIFPLR6_1_PCIE_MC_ADDR1                                                                      0x3fff7bfc3cbf
+#define regBIFPLR6_1_PCIE_MC_ADDR1_BASE_IDX                                                             5
+#define regBIFPLR6_1_PCIE_MC_RCV0                                                                       0x3fff7bfc3cc0
+#define regBIFPLR6_1_PCIE_MC_RCV0_BASE_IDX                                                              5
+#define regBIFPLR6_1_PCIE_MC_RCV1                                                                       0x3fff7bfc3cc1
+#define regBIFPLR6_1_PCIE_MC_RCV1_BASE_IDX                                                              5
+#define regBIFPLR6_1_PCIE_MC_BLOCK_ALL0                                                                 0x3fff7bfc3cc2
+#define regBIFPLR6_1_PCIE_MC_BLOCK_ALL0_BASE_IDX                                                        5
+#define regBIFPLR6_1_PCIE_MC_BLOCK_ALL1                                                                 0x3fff7bfc3cc3
+#define regBIFPLR6_1_PCIE_MC_BLOCK_ALL1_BASE_IDX                                                        5
+#define regBIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                                       0x3fff7bfc3cc4
+#define regBIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                              5
+#define regBIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                                       0x3fff7bfc3cc5
+#define regBIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                              5
+#define regBIFPLR6_1_PCIE_MC_OVERLAY_BAR0                                                               0x3fff7bfc3cc6
+#define regBIFPLR6_1_PCIE_MC_OVERLAY_BAR0_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_MC_OVERLAY_BAR1                                                               0x3fff7bfc3cc7
+#define regBIFPLR6_1_PCIE_MC_OVERLAY_BAR1_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST                                                            0x3fff7bfc3cdc
+#define regBIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST_BASE_IDX                                                   5
+#define regBIFPLR6_1_PCIE_L1_PM_SUB_CAP                                                                 0x3fff7bfc3cdd
+#define regBIFPLR6_1_PCIE_L1_PM_SUB_CAP_BASE_IDX                                                        5
+#define regBIFPLR6_1_PCIE_L1_PM_SUB_CNTL                                                                0x3fff7bfc3cde
+#define regBIFPLR6_1_PCIE_L1_PM_SUB_CNTL_BASE_IDX                                                       5
+#define regBIFPLR6_1_PCIE_L1_PM_SUB_CNTL2                                                               0x3fff7bfc3cdf
+#define regBIFPLR6_1_PCIE_L1_PM_SUB_CNTL2_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_DPC_ENH_CAP_LIST                                                              0x3fff7bfc3ce0
+#define regBIFPLR6_1_PCIE_DPC_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR6_1_PCIE_DPC_CAP_LIST                                                                  0x3fff7bfc3ce1
+#define regBIFPLR6_1_PCIE_DPC_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR6_1_PCIE_DPC_CNTL                                                                      0x3fff7bfc3ce1
+#define regBIFPLR6_1_PCIE_DPC_CNTL_BASE_IDX                                                             5
+#define regBIFPLR6_1_PCIE_DPC_STATUS                                                                    0x3fff7bfc3ce2
+#define regBIFPLR6_1_PCIE_DPC_STATUS_BASE_IDX                                                           5
+#define regBIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID                                                           0x3fff7bfc3ce2
+#define regBIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID_BASE_IDX                                                  5
+#define regBIFPLR6_1_PCIE_RP_PIO_STATUS                                                                 0x3fff7bfc3ce3
+#define regBIFPLR6_1_PCIE_RP_PIO_STATUS_BASE_IDX                                                        5
+#define regBIFPLR6_1_PCIE_RP_PIO_MASK                                                                   0x3fff7bfc3ce4
+#define regBIFPLR6_1_PCIE_RP_PIO_MASK_BASE_IDX                                                          5
+#define regBIFPLR6_1_PCIE_RP_PIO_SEVERITY                                                               0x3fff7bfc3ce5
+#define regBIFPLR6_1_PCIE_RP_PIO_SEVERITY_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_RP_PIO_SYSERROR                                                               0x3fff7bfc3ce6
+#define regBIFPLR6_1_PCIE_RP_PIO_SYSERROR_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_RP_PIO_EXCEPTION                                                              0x3fff7bfc3ce7
+#define regBIFPLR6_1_PCIE_RP_PIO_EXCEPTION_BASE_IDX                                                     5
+#define regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG0                                                               0x3fff7bfc3ce8
+#define regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG0_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG1                                                               0x3fff7bfc3ce9
+#define regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG1_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG2                                                               0x3fff7bfc3cea
+#define regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG2_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG3                                                               0x3fff7bfc3ceb
+#define regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG3_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0                                                            0x3fff7bfc3ced
+#define regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0_BASE_IDX                                                   5
+#define regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1                                                            0x3fff7bfc3cee
+#define regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1_BASE_IDX                                                   5
+#define regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2                                                            0x3fff7bfc3cef
+#define regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2_BASE_IDX                                                   5
+#define regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3                                                            0x3fff7bfc3cf0
+#define regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3_BASE_IDX                                                   5
+#define regBIFPLR6_1_PCIE_ESM_CAP_LIST                                                                  0x3fff7bfc3cf1
+#define regBIFPLR6_1_PCIE_ESM_CAP_LIST_BASE_IDX                                                         5
+#define regBIFPLR6_1_PCIE_ESM_HEADER_1                                                                  0x3fff7bfc3cf2
+#define regBIFPLR6_1_PCIE_ESM_HEADER_1_BASE_IDX                                                         5
+#define regBIFPLR6_1_PCIE_ESM_HEADER_2                                                                  0x3fff7bfc3cf3
+#define regBIFPLR6_1_PCIE_ESM_HEADER_2_BASE_IDX                                                         5
+#define regBIFPLR6_1_PCIE_ESM_STATUS                                                                    0x3fff7bfc3cf3
+#define regBIFPLR6_1_PCIE_ESM_STATUS_BASE_IDX                                                           5
+#define regBIFPLR6_1_PCIE_ESM_CTRL                                                                      0x3fff7bfc3cf4
+#define regBIFPLR6_1_PCIE_ESM_CTRL_BASE_IDX                                                             5
+#define regBIFPLR6_1_PCIE_ESM_CAP_1                                                                     0x3fff7bfc3cf5
+#define regBIFPLR6_1_PCIE_ESM_CAP_1_BASE_IDX                                                            5
+#define regBIFPLR6_1_PCIE_ESM_CAP_2                                                                     0x3fff7bfc3cf6
+#define regBIFPLR6_1_PCIE_ESM_CAP_2_BASE_IDX                                                            5
+#define regBIFPLR6_1_PCIE_ESM_CAP_3                                                                     0x3fff7bfc3cf7
+#define regBIFPLR6_1_PCIE_ESM_CAP_3_BASE_IDX                                                            5
+#define regBIFPLR6_1_PCIE_ESM_CAP_4                                                                     0x3fff7bfc3cf8
+#define regBIFPLR6_1_PCIE_ESM_CAP_4_BASE_IDX                                                            5
+#define regBIFPLR6_1_PCIE_ESM_CAP_5                                                                     0x3fff7bfc3cf9
+#define regBIFPLR6_1_PCIE_ESM_CAP_5_BASE_IDX                                                            5
+#define regBIFPLR6_1_PCIE_ESM_CAP_6                                                                     0x3fff7bfc3cfa
+#define regBIFPLR6_1_PCIE_ESM_CAP_6_BASE_IDX                                                            5
+#define regBIFPLR6_1_PCIE_ESM_CAP_7                                                                     0x3fff7bfc3cfb
+#define regBIFPLR6_1_PCIE_ESM_CAP_7_BASE_IDX                                                            5
+#define regBIFPLR6_1_PCIE_DLF_ENH_CAP_LIST                                                              0x3fff7bfc3d00
+#define regBIFPLR6_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                                     5
+#define regBIFPLR6_1_DATA_LINK_FEATURE_CAP                                                              0x3fff7bfc3d01
+#define regBIFPLR6_1_DATA_LINK_FEATURE_CAP_BASE_IDX                                                     5
+#define regBIFPLR6_1_DATA_LINK_FEATURE_STATUS                                                           0x3fff7bfc3d02
+#define regBIFPLR6_1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                                  5
+#define regBIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST                                                         0x3fff7bfc3d04
+#define regBIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIFPLR6_1_LINK_CAP_16GT                                                                      0x3fff7bfc3d05
+#define regBIFPLR6_1_LINK_CAP_16GT_BASE_IDX                                                             5
+#define regBIFPLR6_1_LINK_CNTL_16GT                                                                     0x3fff7bfc3d06
+#define regBIFPLR6_1_LINK_CNTL_16GT_BASE_IDX                                                            5
+#define regBIFPLR6_1_LINK_STATUS_16GT                                                                   0x3fff7bfc3d07
+#define regBIFPLR6_1_LINK_STATUS_16GT_BASE_IDX                                                          5
+#define regBIFPLR6_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                                  0x3fff7bfc3d08
+#define regBIFPLR6_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                         5
+#define regBIFPLR6_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc3d09
+#define regBIFPLR6_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR6_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                                   0x3fff7bfc3d0a
+#define regBIFPLR6_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                          5
+#define regBIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc3d0c
+#define regBIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc3d0c
+#define regBIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc3d0c
+#define regBIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc3d0c
+#define regBIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc3d0d
+#define regBIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc3d0d
+#define regBIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc3d0d
+#define regBIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc3d0d
+#define regBIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc3d0e
+#define regBIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT                                                      0x3fff7bfc3d0e
+#define regBIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc3d0e
+#define regBIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc3d0e
+#define regBIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc3d0f
+#define regBIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc3d0f
+#define regBIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc3d0f
+#define regBIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT                                                     0x3fff7bfc3d0f
+#define regBIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                            5
+#define regBIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST                                                        0x3fff7bfc3d10
+#define regBIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIFPLR6_1_MARGINING_PORT_CAP                                                                 0x3fff7bfc3d11
+#define regBIFPLR6_1_MARGINING_PORT_CAP_BASE_IDX                                                        5
+#define regBIFPLR6_1_MARGINING_PORT_STATUS                                                              0x3fff7bfc3d11
+#define regBIFPLR6_1_MARGINING_PORT_STATUS_BASE_IDX                                                     5
+#define regBIFPLR6_1_LANE_0_MARGINING_LANE_CNTL                                                         0x3fff7bfc3d12
+#define regBIFPLR6_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_1_LANE_0_MARGINING_LANE_STATUS                                                       0x3fff7bfc3d12
+#define regBIFPLR6_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_1_LANE_1_MARGINING_LANE_CNTL                                                         0x3fff7bfc3d13
+#define regBIFPLR6_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_1_LANE_1_MARGINING_LANE_STATUS                                                       0x3fff7bfc3d13
+#define regBIFPLR6_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_1_LANE_2_MARGINING_LANE_CNTL                                                         0x3fff7bfc3d14
+#define regBIFPLR6_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_1_LANE_2_MARGINING_LANE_STATUS                                                       0x3fff7bfc3d14
+#define regBIFPLR6_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_1_LANE_3_MARGINING_LANE_CNTL                                                         0x3fff7bfc3d15
+#define regBIFPLR6_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_1_LANE_3_MARGINING_LANE_STATUS                                                       0x3fff7bfc3d15
+#define regBIFPLR6_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_1_LANE_4_MARGINING_LANE_CNTL                                                         0x3fff7bfc3d16
+#define regBIFPLR6_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_1_LANE_4_MARGINING_LANE_STATUS                                                       0x3fff7bfc3d16
+#define regBIFPLR6_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_1_LANE_5_MARGINING_LANE_CNTL                                                         0x3fff7bfc3d17
+#define regBIFPLR6_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_1_LANE_5_MARGINING_LANE_STATUS                                                       0x3fff7bfc3d17
+#define regBIFPLR6_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_1_LANE_6_MARGINING_LANE_CNTL                                                         0x3fff7bfc3d18
+#define regBIFPLR6_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_1_LANE_6_MARGINING_LANE_STATUS                                                       0x3fff7bfc3d18
+#define regBIFPLR6_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_1_LANE_7_MARGINING_LANE_CNTL                                                         0x3fff7bfc3d19
+#define regBIFPLR6_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_1_LANE_7_MARGINING_LANE_STATUS                                                       0x3fff7bfc3d19
+#define regBIFPLR6_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_1_LANE_8_MARGINING_LANE_CNTL                                                         0x3fff7bfc3d1a
+#define regBIFPLR6_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_1_LANE_8_MARGINING_LANE_STATUS                                                       0x3fff7bfc3d1a
+#define regBIFPLR6_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_1_LANE_9_MARGINING_LANE_CNTL                                                         0x3fff7bfc3d1b
+#define regBIFPLR6_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                                5
+#define regBIFPLR6_1_LANE_9_MARGINING_LANE_STATUS                                                       0x3fff7bfc3d1b
+#define regBIFPLR6_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                              5
+#define regBIFPLR6_1_LANE_10_MARGINING_LANE_CNTL                                                        0x3fff7bfc3d1c
+#define regBIFPLR6_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_1_LANE_10_MARGINING_LANE_STATUS                                                      0x3fff7bfc3d1c
+#define regBIFPLR6_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_11_MARGINING_LANE_CNTL                                                        0x3fff7bfc3d1d
+#define regBIFPLR6_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_1_LANE_11_MARGINING_LANE_STATUS                                                      0x3fff7bfc3d1d
+#define regBIFPLR6_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_12_MARGINING_LANE_CNTL                                                        0x3fff7bfc3d1e
+#define regBIFPLR6_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_1_LANE_12_MARGINING_LANE_STATUS                                                      0x3fff7bfc3d1e
+#define regBIFPLR6_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_13_MARGINING_LANE_CNTL                                                        0x3fff7bfc3d1f
+#define regBIFPLR6_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_1_LANE_13_MARGINING_LANE_STATUS                                                      0x3fff7bfc3d1f
+#define regBIFPLR6_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_14_MARGINING_LANE_CNTL                                                        0x3fff7bfc3d20
+#define regBIFPLR6_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_1_LANE_14_MARGINING_LANE_STATUS                                                      0x3fff7bfc3d20
+#define regBIFPLR6_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_1_LANE_15_MARGINING_LANE_CNTL                                                        0x3fff7bfc3d21
+#define regBIFPLR6_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                               5
+#define regBIFPLR6_1_LANE_15_MARGINING_LANE_STATUS                                                      0x3fff7bfc3d21
+#define regBIFPLR6_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                             5
+#define regBIFPLR6_1_PCIE_CCIX_CAP_LIST                                                                 0x3fff7bfc3d22
+#define regBIFPLR6_1_PCIE_CCIX_CAP_LIST_BASE_IDX                                                        5
+#define regBIFPLR6_1_PCIE_CCIX_HEADER_1                                                                 0x3fff7bfc3d23
+#define regBIFPLR6_1_PCIE_CCIX_HEADER_1_BASE_IDX                                                        5
+#define regBIFPLR6_1_PCIE_CCIX_HEADER_2                                                                 0x3fff7bfc3d24
+#define regBIFPLR6_1_PCIE_CCIX_HEADER_2_BASE_IDX                                                        5
+#define regBIFPLR6_1_PCIE_CCIX_CAP                                                                      0x3fff7bfc3d24
+#define regBIFPLR6_1_PCIE_CCIX_CAP_BASE_IDX                                                             5
+#define regBIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP                                                             0x3fff7bfc3d25
+#define regBIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP_BASE_IDX                                                    5
+#define regBIFPLR6_1_PCIE_CCIX_ESM_OPTL_CAP                                                             0x3fff7bfc3d26
+#define regBIFPLR6_1_PCIE_CCIX_ESM_OPTL_CAP_BASE_IDX                                                    5
+#define regBIFPLR6_1_PCIE_CCIX_ESM_STATUS                                                               0x3fff7bfc3d27
+#define regBIFPLR6_1_PCIE_CCIX_ESM_STATUS_BASE_IDX                                                      5
+#define regBIFPLR6_1_PCIE_CCIX_ESM_CNTL                                                                 0x3fff7bfc3d28
+#define regBIFPLR6_1_PCIE_CCIX_ESM_CNTL_BASE_IDX                                                        5
+#define regBIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3d29
+#define regBIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3d29
+#define regBIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3d29
+#define regBIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3d29
+#define regBIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3d2a
+#define regBIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3d2a
+#define regBIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3d2a
+#define regBIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3d2a
+#define regBIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3d2b
+#define regBIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT                                                  0x3fff7bfc3d2b
+#define regBIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc3d2b
+#define regBIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc3d2b
+#define regBIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc3d2c
+#define regBIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc3d2c
+#define regBIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc3d2c
+#define regBIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT                                                 0x3fff7bfc3d2c
+#define regBIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT_BASE_IDX                                        5
+#define regBIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc3d2d
+#define regBIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc3d2d
+#define regBIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc3d2d
+#define regBIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc3d2d
+#define regBIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc3d2e
+#define regBIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc3d2e
+#define regBIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc3d2e
+#define regBIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc3d2e
+#define regBIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc3d2f
+#define regBIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT                                                  0x3fff7bfc3d2f
+#define regBIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT_BASE_IDX                                         5
+#define regBIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3d2f
+#define regBIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3d2f
+#define regBIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3d30
+#define regBIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3d30
+#define regBIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3d30
+#define regBIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT                                                 0x3fff7bfc3d30
+#define regBIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT_BASE_IDX                                        5
+#define regBIFPLR6_1_PCIE_CCIX_TRANS_CAP                                                                0x3fff7bfc3d31
+#define regBIFPLR6_1_PCIE_CCIX_TRANS_CAP_BASE_IDX                                                       5
+#define regBIFPLR6_1_PCIE_CCIX_TRANS_CNTL                                                               0x3fff7bfc3d32
+#define regBIFPLR6_1_PCIE_CCIX_TRANS_CNTL_BASE_IDX                                                      5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+// base address: 0xfffe00041000
+#define regBIF_CFG_DEV0_RC1_VENDOR_ID                                                                   0x3fff7bfd0400
+#define regBIF_CFG_DEV0_RC1_VENDOR_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC1_DEVICE_ID                                                                   0x3fff7bfd0400
+#define regBIF_CFG_DEV0_RC1_DEVICE_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC1_COMMAND                                                                     0x3fff7bfd0401
+#define regBIF_CFG_DEV0_RC1_COMMAND_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC1_STATUS                                                                      0x3fff7bfd0401
+#define regBIF_CFG_DEV0_RC1_STATUS_BASE_IDX                                                             5
+#define regBIF_CFG_DEV0_RC1_REVISION_ID                                                                 0x3fff7bfd0402
+#define regBIF_CFG_DEV0_RC1_REVISION_ID_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC1_PROG_INTERFACE                                                              0x3fff7bfd0402
+#define regBIF_CFG_DEV0_RC1_PROG_INTERFACE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC1_SUB_CLASS                                                                   0x3fff7bfd0402
+#define regBIF_CFG_DEV0_RC1_SUB_CLASS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC1_BASE_CLASS                                                                  0x3fff7bfd0402
+#define regBIF_CFG_DEV0_RC1_BASE_CLASS_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC1_CACHE_LINE                                                                  0x3fff7bfd0403
+#define regBIF_CFG_DEV0_RC1_CACHE_LINE_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC1_LATENCY                                                                     0x3fff7bfd0403
+#define regBIF_CFG_DEV0_RC1_LATENCY_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC1_HEADER                                                                      0x3fff7bfd0403
+#define regBIF_CFG_DEV0_RC1_HEADER_BASE_IDX                                                             5
+#define regBIF_CFG_DEV0_RC1_BIST                                                                        0x3fff7bfd0403
+#define regBIF_CFG_DEV0_RC1_BIST_BASE_IDX                                                               5
+#define regBIF_CFG_DEV0_RC1_BASE_ADDR_1                                                                 0x3fff7bfd0404
+#define regBIF_CFG_DEV0_RC1_BASE_ADDR_1_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC1_BASE_ADDR_2                                                                 0x3fff7bfd0405
+#define regBIF_CFG_DEV0_RC1_BASE_ADDR_2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY                                                      0x3fff7bfd0406
+#define regBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC1_IO_BASE_LIMIT                                                               0x3fff7bfd0407
+#define regBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_SECONDARY_STATUS                                                            0x3fff7bfd0407
+#define regBIF_CFG_DEV0_RC1_SECONDARY_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT                                                              0x3fff7bfd0408
+#define regBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT                                                             0x3fff7bfd0409
+#define regBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC1_PREF_BASE_UPPER                                                             0x3fff7bfd040a
+#define regBIF_CFG_DEV0_RC1_PREF_BASE_UPPER_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER                                                            0x3fff7bfd040b
+#define regBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI                                                            0x3fff7bfd040c
+#define regBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC1_CAP_PTR                                                                     0x3fff7bfd040d
+#define regBIF_CFG_DEV0_RC1_CAP_PTR_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC1_ROM_BASE_ADDR                                                               0x3fff7bfd040e
+#define regBIF_CFG_DEV0_RC1_ROM_BASE_ADDR_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_INTERRUPT_LINE                                                              0x3fff7bfd040f
+#define regBIF_CFG_DEV0_RC1_INTERRUPT_LINE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC1_INTERRUPT_PIN                                                               0x3fff7bfd040f
+#define regBIF_CFG_DEV0_RC1_INTERRUPT_PIN_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL                                                             0x3fff7bfd040f
+#define regBIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL                                                             0x3fff7bfd0410
+#define regBIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC1_PMI_CAP_LIST                                                                0x3fff7bfd0414
+#define regBIF_CFG_DEV0_RC1_PMI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC1_PMI_CAP                                                                     0x3fff7bfd0414
+#define regBIF_CFG_DEV0_RC1_PMI_CAP_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL                                                             0x3fff7bfd0415
+#define regBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC1_PCIE_CAP_LIST                                                               0x3fff7bfd0416
+#define regBIF_CFG_DEV0_RC1_PCIE_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_CAP                                                                    0x3fff7bfd0416
+#define regBIF_CFG_DEV0_RC1_PCIE_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC1_DEVICE_CAP                                                                  0x3fff7bfd0417
+#define regBIF_CFG_DEV0_RC1_DEVICE_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC1_DEVICE_CNTL                                                                 0x3fff7bfd0418
+#define regBIF_CFG_DEV0_RC1_DEVICE_CNTL_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC1_DEVICE_STATUS                                                               0x3fff7bfd0418
+#define regBIF_CFG_DEV0_RC1_DEVICE_STATUS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_LINK_CAP                                                                    0x3fff7bfd0419
+#define regBIF_CFG_DEV0_RC1_LINK_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC1_LINK_CNTL                                                                   0x3fff7bfd041a
+#define regBIF_CFG_DEV0_RC1_LINK_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC1_LINK_STATUS                                                                 0x3fff7bfd041a
+#define regBIF_CFG_DEV0_RC1_LINK_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC1_SLOT_CAP                                                                    0x3fff7bfd041b
+#define regBIF_CFG_DEV0_RC1_SLOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC1_SLOT_CNTL                                                                   0x3fff7bfd041c
+#define regBIF_CFG_DEV0_RC1_SLOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC1_SLOT_STATUS                                                                 0x3fff7bfd041c
+#define regBIF_CFG_DEV0_RC1_SLOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC1_ROOT_CNTL                                                                   0x3fff7bfd041d
+#define regBIF_CFG_DEV0_RC1_ROOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC1_ROOT_CAP                                                                    0x3fff7bfd041d
+#define regBIF_CFG_DEV0_RC1_ROOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC1_ROOT_STATUS                                                                 0x3fff7bfd041e
+#define regBIF_CFG_DEV0_RC1_ROOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC1_DEVICE_CAP2                                                                 0x3fff7bfd041f
+#define regBIF_CFG_DEV0_RC1_DEVICE_CAP2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC1_DEVICE_CNTL2                                                                0x3fff7bfd0420
+#define regBIF_CFG_DEV0_RC1_DEVICE_CNTL2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC1_DEVICE_STATUS2                                                              0x3fff7bfd0420
+#define regBIF_CFG_DEV0_RC1_DEVICE_STATUS2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC1_LINK_CAP2                                                                   0x3fff7bfd0421
+#define regBIF_CFG_DEV0_RC1_LINK_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC1_LINK_CNTL2                                                                  0x3fff7bfd0422
+#define regBIF_CFG_DEV0_RC1_LINK_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC1_LINK_STATUS2                                                                0x3fff7bfd0422
+#define regBIF_CFG_DEV0_RC1_LINK_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC1_SLOT_CAP2                                                                   0x3fff7bfd0423
+#define regBIF_CFG_DEV0_RC1_SLOT_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC1_SLOT_CNTL2                                                                  0x3fff7bfd0424
+#define regBIF_CFG_DEV0_RC1_SLOT_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC1_SLOT_STATUS2                                                                0x3fff7bfd0424
+#define regBIF_CFG_DEV0_RC1_SLOT_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC1_MSI_CAP_LIST                                                                0x3fff7bfd0428
+#define regBIF_CFG_DEV0_RC1_MSI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC1_MSI_MSG_CNTL                                                                0x3fff7bfd0428
+#define regBIF_CFG_DEV0_RC1_MSI_MSG_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO                                                             0x3fff7bfd0429
+#define regBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI                                                             0x3fff7bfd042a
+#define regBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC1_MSI_MSG_DATA                                                                0x3fff7bfd042a
+#define regBIF_CFG_DEV0_RC1_MSI_MSG_DATA_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA                                                            0x3fff7bfd042a
+#define regBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64                                                             0x3fff7bfd042b
+#define regBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64                                                         0x3fff7bfd042b
+#define regBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_RC1_SSID_CAP_LIST                                                               0x3fff7bfd0430
+#define regBIF_CFG_DEV0_RC1_SSID_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_SSID_CAP                                                                    0x3fff7bfd0431
+#define regBIF_CFG_DEV0_RC1_SSID_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST                                                            0x3fff7bfd0432
+#define regBIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC1_MSI_MAP_CAP                                                                 0x3fff7bfd0432
+#define regBIF_CFG_DEV0_RC1_MSI_MAP_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                           0x3fff7bfd0440
+#define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR                                                    0x3fff7bfd0441
+#define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1                                                       0x3fff7bfd0442
+#define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2                                                       0x3fff7bfd0443
+#define regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST                                                        0x3fff7bfd0444
+#define regBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1                                                       0x3fff7bfd0445
+#define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2                                                       0x3fff7bfd0446
+#define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL                                                           0x3fff7bfd0447
+#define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS                                                         0x3fff7bfd0447
+#define regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP                                                       0x3fff7bfd0448
+#define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL                                                      0x3fff7bfd0449
+#define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS                                                    0x3fff7bfd044a
+#define regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP                                                       0x3fff7bfd044b
+#define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL                                                      0x3fff7bfd044c
+#define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS                                                    0x3fff7bfd044d
+#define regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                            0x3fff7bfd0450
+#define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1                                                     0x3fff7bfd0451
+#define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2                                                     0x3fff7bfd0452
+#define regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                               0x3fff7bfd0454
+#define regBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS                                                      0x3fff7bfd0455
+#define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK                                                        0x3fff7bfd0456
+#define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY                                                    0x3fff7bfd0457
+#define regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS                                                        0x3fff7bfd0458
+#define regBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK                                                          0x3fff7bfd0459
+#define regBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL                                                       0x3fff7bfd045a
+#define regBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0                                                               0x3fff7bfd045b
+#define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1                                                               0x3fff7bfd045c
+#define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2                                                               0x3fff7bfd045d
+#define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3                                                               0x3fff7bfd045e
+#define regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD                                                           0x3fff7bfd045f
+#define regBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS                                                        0x3fff7bfd0460
+#define regBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID                                                             0x3fff7bfd0461
+#define regBIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0                                                        0x3fff7bfd0462
+#define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1                                                        0x3fff7bfd0463
+#define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2                                                        0x3fff7bfd0464
+#define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3                                                        0x3fff7bfd0465
+#define regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST                                                 0x3fff7bfd049c
+#define regBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3                                                             0x3fff7bfd049d
+#define regBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS                                                      0x3fff7bfd049e
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL                                               0x3fff7bfd049f
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL                                               0x3fff7bfd049f
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL                                               0x3fff7bfd04a0
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL                                               0x3fff7bfd04a0
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL                                               0x3fff7bfd04a1
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL                                               0x3fff7bfd04a1
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL                                               0x3fff7bfd04a2
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL                                               0x3fff7bfd04a2
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL                                               0x3fff7bfd04a3
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL                                               0x3fff7bfd04a3
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL                                              0x3fff7bfd04a4
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL                                              0x3fff7bfd04a4
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL                                              0x3fff7bfd04a5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL                                              0x3fff7bfd04a5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL                                              0x3fff7bfd04a6
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL                                              0x3fff7bfd04a6
+#define regBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST                                                       0x3fff7bfd04a8
+#define regBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC1_PCIE_ACS_CAP                                                                0x3fff7bfd04a9
+#define regBIF_CFG_DEV0_RC1_PCIE_ACS_CAP_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL                                                               0x3fff7bfd04a9
+#define regBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST                                                       0x3fff7bfd0500
+#define regBIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP                                                       0x3fff7bfd0501
+#define regBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS                                                    0x3fff7bfd0502
+#define regBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST                                                  0x3fff7bfd0504
+#define regBIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC1_LINK_CAP_16GT                                                               0x3fff7bfd0505
+#define regBIF_CFG_DEV0_RC1_LINK_CAP_16GT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC1_LINK_CNTL_16GT                                                              0x3fff7bfd0506
+#define regBIF_CFG_DEV0_RC1_LINK_CNTL_16GT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC1_LINK_STATUS_16GT                                                            0x3fff7bfd0507
+#define regBIF_CFG_DEV0_RC1_LINK_STATUS_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                           0x3fff7bfd0508
+#define regBIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT                                            0x3fff7bfd0509
+#define regBIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT                                            0x3fff7bfd050a
+#define regBIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd050c
+#define regBIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd050c
+#define regBIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd050c
+#define regBIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd050c
+#define regBIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd050d
+#define regBIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd050d
+#define regBIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd050d
+#define regBIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd050d
+#define regBIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd050e
+#define regBIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd050e
+#define regBIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd050e
+#define regBIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd050e
+#define regBIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd050f
+#define regBIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd050f
+#define regBIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd050f
+#define regBIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd050f
+#define regBIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST                                                 0x3fff7bfd0510
+#define regBIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC1_MARGINING_PORT_CAP                                                          0x3fff7bfd0511
+#define regBIF_CFG_DEV0_RC1_MARGINING_PORT_CAP_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS                                                       0x3fff7bfd0511
+#define regBIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL                                                  0x3fff7bfd0512
+#define regBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS                                                0x3fff7bfd0512
+#define regBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL                                                  0x3fff7bfd0513
+#define regBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS                                                0x3fff7bfd0513
+#define regBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL                                                  0x3fff7bfd0514
+#define regBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS                                                0x3fff7bfd0514
+#define regBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL                                                  0x3fff7bfd0515
+#define regBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS                                                0x3fff7bfd0515
+#define regBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL                                                  0x3fff7bfd0516
+#define regBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS                                                0x3fff7bfd0516
+#define regBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL                                                  0x3fff7bfd0517
+#define regBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS                                                0x3fff7bfd0517
+#define regBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL                                                  0x3fff7bfd0518
+#define regBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS                                                0x3fff7bfd0518
+#define regBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL                                                  0x3fff7bfd0519
+#define regBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS                                                0x3fff7bfd0519
+#define regBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL                                                  0x3fff7bfd051a
+#define regBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS                                                0x3fff7bfd051a
+#define regBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL                                                  0x3fff7bfd051b
+#define regBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS                                                0x3fff7bfd051b
+#define regBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL                                                 0x3fff7bfd051c
+#define regBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS                                               0x3fff7bfd051c
+#define regBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL                                                 0x3fff7bfd051d
+#define regBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS                                               0x3fff7bfd051d
+#define regBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL                                                 0x3fff7bfd051e
+#define regBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS                                               0x3fff7bfd051e
+#define regBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL                                                 0x3fff7bfd051f
+#define regBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS                                               0x3fff7bfd051f
+#define regBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL                                                 0x3fff7bfd0520
+#define regBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS                                               0x3fff7bfd0520
+#define regBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL                                                 0x3fff7bfd0521
+#define regBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS                                               0x3fff7bfd0521
+#define regBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                      5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+// base address: 0xfffe00042000
+#define regBIF_CFG_DEV1_RC1_VENDOR_ID                                                                   0x3fff7bfd0800
+#define regBIF_CFG_DEV1_RC1_VENDOR_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC1_DEVICE_ID                                                                   0x3fff7bfd0800
+#define regBIF_CFG_DEV1_RC1_DEVICE_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC1_COMMAND                                                                     0x3fff7bfd0801
+#define regBIF_CFG_DEV1_RC1_COMMAND_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_RC1_STATUS                                                                      0x3fff7bfd0801
+#define regBIF_CFG_DEV1_RC1_STATUS_BASE_IDX                                                             5
+#define regBIF_CFG_DEV1_RC1_REVISION_ID                                                                 0x3fff7bfd0802
+#define regBIF_CFG_DEV1_RC1_REVISION_ID_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC1_PROG_INTERFACE                                                              0x3fff7bfd0802
+#define regBIF_CFG_DEV1_RC1_PROG_INTERFACE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_RC1_SUB_CLASS                                                                   0x3fff7bfd0802
+#define regBIF_CFG_DEV1_RC1_SUB_CLASS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC1_BASE_CLASS                                                                  0x3fff7bfd0802
+#define regBIF_CFG_DEV1_RC1_BASE_CLASS_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_RC1_CACHE_LINE                                                                  0x3fff7bfd0803
+#define regBIF_CFG_DEV1_RC1_CACHE_LINE_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_RC1_LATENCY                                                                     0x3fff7bfd0803
+#define regBIF_CFG_DEV1_RC1_LATENCY_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_RC1_HEADER                                                                      0x3fff7bfd0803
+#define regBIF_CFG_DEV1_RC1_HEADER_BASE_IDX                                                             5
+#define regBIF_CFG_DEV1_RC1_BIST                                                                        0x3fff7bfd0803
+#define regBIF_CFG_DEV1_RC1_BIST_BASE_IDX                                                               5
+#define regBIF_CFG_DEV1_RC1_BASE_ADDR_1                                                                 0x3fff7bfd0804
+#define regBIF_CFG_DEV1_RC1_BASE_ADDR_1_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC1_BASE_ADDR_2                                                                 0x3fff7bfd0805
+#define regBIF_CFG_DEV1_RC1_BASE_ADDR_2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY                                                      0x3fff7bfd0806
+#define regBIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_RC1_IO_BASE_LIMIT                                                               0x3fff7bfd0807
+#define regBIF_CFG_DEV1_RC1_IO_BASE_LIMIT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_SECONDARY_STATUS                                                            0x3fff7bfd0807
+#define regBIF_CFG_DEV1_RC1_SECONDARY_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC1_MEM_BASE_LIMIT                                                              0x3fff7bfd0808
+#define regBIF_CFG_DEV1_RC1_MEM_BASE_LIMIT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_RC1_PREF_BASE_LIMIT                                                             0x3fff7bfd0809
+#define regBIF_CFG_DEV1_RC1_PREF_BASE_LIMIT_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC1_PREF_BASE_UPPER                                                             0x3fff7bfd080a
+#define regBIF_CFG_DEV1_RC1_PREF_BASE_UPPER_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER                                                            0x3fff7bfd080b
+#define regBIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI                                                            0x3fff7bfd080c
+#define regBIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC1_CAP_PTR                                                                     0x3fff7bfd080d
+#define regBIF_CFG_DEV1_RC1_CAP_PTR_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_RC1_ROM_BASE_ADDR                                                               0x3fff7bfd080e
+#define regBIF_CFG_DEV1_RC1_ROM_BASE_ADDR_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_INTERRUPT_LINE                                                              0x3fff7bfd080f
+#define regBIF_CFG_DEV1_RC1_INTERRUPT_LINE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_RC1_INTERRUPT_PIN                                                               0x3fff7bfd080f
+#define regBIF_CFG_DEV1_RC1_INTERRUPT_PIN_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL                                                             0x3fff7bfd080f
+#define regBIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL                                                             0x3fff7bfd0810
+#define regBIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC1_PMI_CAP_LIST                                                                0x3fff7bfd0814
+#define regBIF_CFG_DEV1_RC1_PMI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC1_PMI_CAP                                                                     0x3fff7bfd0814
+#define regBIF_CFG_DEV1_RC1_PMI_CAP_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_RC1_PMI_STATUS_CNTL                                                             0x3fff7bfd0815
+#define regBIF_CFG_DEV1_RC1_PMI_STATUS_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC1_PCIE_CAP_LIST                                                               0x3fff7bfd0816
+#define regBIF_CFG_DEV1_RC1_PCIE_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_CAP                                                                    0x3fff7bfd0816
+#define regBIF_CFG_DEV1_RC1_PCIE_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_RC1_DEVICE_CAP                                                                  0x3fff7bfd0817
+#define regBIF_CFG_DEV1_RC1_DEVICE_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_RC1_DEVICE_CNTL                                                                 0x3fff7bfd0818
+#define regBIF_CFG_DEV1_RC1_DEVICE_CNTL_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC1_DEVICE_STATUS                                                               0x3fff7bfd0818
+#define regBIF_CFG_DEV1_RC1_DEVICE_STATUS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_LINK_CAP                                                                    0x3fff7bfd0819
+#define regBIF_CFG_DEV1_RC1_LINK_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_RC1_LINK_CNTL                                                                   0x3fff7bfd081a
+#define regBIF_CFG_DEV1_RC1_LINK_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC1_LINK_STATUS                                                                 0x3fff7bfd081a
+#define regBIF_CFG_DEV1_RC1_LINK_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC1_SLOT_CAP                                                                    0x3fff7bfd081b
+#define regBIF_CFG_DEV1_RC1_SLOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_RC1_SLOT_CNTL                                                                   0x3fff7bfd081c
+#define regBIF_CFG_DEV1_RC1_SLOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC1_SLOT_STATUS                                                                 0x3fff7bfd081c
+#define regBIF_CFG_DEV1_RC1_SLOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC1_ROOT_CNTL                                                                   0x3fff7bfd081d
+#define regBIF_CFG_DEV1_RC1_ROOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC1_ROOT_CAP                                                                    0x3fff7bfd081d
+#define regBIF_CFG_DEV1_RC1_ROOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_RC1_ROOT_STATUS                                                                 0x3fff7bfd081e
+#define regBIF_CFG_DEV1_RC1_ROOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC1_DEVICE_CAP2                                                                 0x3fff7bfd081f
+#define regBIF_CFG_DEV1_RC1_DEVICE_CAP2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC1_DEVICE_CNTL2                                                                0x3fff7bfd0820
+#define regBIF_CFG_DEV1_RC1_DEVICE_CNTL2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC1_DEVICE_STATUS2                                                              0x3fff7bfd0820
+#define regBIF_CFG_DEV1_RC1_DEVICE_STATUS2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_RC1_LINK_CAP2                                                                   0x3fff7bfd0821
+#define regBIF_CFG_DEV1_RC1_LINK_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC1_LINK_CNTL2                                                                  0x3fff7bfd0822
+#define regBIF_CFG_DEV1_RC1_LINK_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_RC1_LINK_STATUS2                                                                0x3fff7bfd0822
+#define regBIF_CFG_DEV1_RC1_LINK_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC1_SLOT_CAP2                                                                   0x3fff7bfd0823
+#define regBIF_CFG_DEV1_RC1_SLOT_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_RC1_SLOT_CNTL2                                                                  0x3fff7bfd0824
+#define regBIF_CFG_DEV1_RC1_SLOT_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_RC1_SLOT_STATUS2                                                                0x3fff7bfd0824
+#define regBIF_CFG_DEV1_RC1_SLOT_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC1_MSI_CAP_LIST                                                                0x3fff7bfd0828
+#define regBIF_CFG_DEV1_RC1_MSI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC1_MSI_MSG_CNTL                                                                0x3fff7bfd0828
+#define regBIF_CFG_DEV1_RC1_MSI_MSG_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO                                                             0x3fff7bfd0829
+#define regBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI                                                             0x3fff7bfd082a
+#define regBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC1_MSI_MSG_DATA                                                                0x3fff7bfd082a
+#define regBIF_CFG_DEV1_RC1_MSI_MSG_DATA_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA                                                            0x3fff7bfd082a
+#define regBIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC1_MSI_MSG_DATA_64                                                             0x3fff7bfd082b
+#define regBIF_CFG_DEV1_RC1_MSI_MSG_DATA_64_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_64                                                         0x3fff7bfd082b
+#define regBIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV1_RC1_SSID_CAP_LIST                                                               0x3fff7bfd0830
+#define regBIF_CFG_DEV1_RC1_SSID_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_SSID_CAP                                                                    0x3fff7bfd0831
+#define regBIF_CFG_DEV1_RC1_SSID_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST                                                            0x3fff7bfd0832
+#define regBIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC1_MSI_MAP_CAP                                                                 0x3fff7bfd0832
+#define regBIF_CFG_DEV1_RC1_MSI_MAP_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                           0x3fff7bfd0840
+#define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR                                                    0x3fff7bfd0841
+#define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1                                                       0x3fff7bfd0842
+#define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2                                                       0x3fff7bfd0843
+#define regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST                                                        0x3fff7bfd0844
+#define regBIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1                                                       0x3fff7bfd0845
+#define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2                                                       0x3fff7bfd0846
+#define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL                                                           0x3fff7bfd0847
+#define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS                                                         0x3fff7bfd0847
+#define regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS_BASE_IDX                                                5
+#define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP                                                       0x3fff7bfd0848
+#define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL                                                      0x3fff7bfd0849
+#define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS                                                    0x3fff7bfd084a
+#define regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP                                                       0x3fff7bfd084b
+#define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL                                                      0x3fff7bfd084c
+#define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS                                                    0x3fff7bfd084d
+#define regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                            0x3fff7bfd0850
+#define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1                                                     0x3fff7bfd0851
+#define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2                                                     0x3fff7bfd0852
+#define regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                               0x3fff7bfd0854
+#define regBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS                                                      0x3fff7bfd0855
+#define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK                                                        0x3fff7bfd0856
+#define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY                                                    0x3fff7bfd0857
+#define regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS                                                        0x3fff7bfd0858
+#define regBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK                                                          0x3fff7bfd0859
+#define regBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL                                                       0x3fff7bfd085a
+#define regBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG0                                                               0x3fff7bfd085b
+#define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG0_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG1                                                               0x3fff7bfd085c
+#define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG1_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG2                                                               0x3fff7bfd085d
+#define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG3                                                               0x3fff7bfd085e
+#define regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG3_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD                                                           0x3fff7bfd085f
+#define regBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS                                                        0x3fff7bfd0860
+#define regBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID                                                             0x3fff7bfd0861
+#define regBIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0                                                        0x3fff7bfd0862
+#define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1                                                        0x3fff7bfd0863
+#define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2                                                        0x3fff7bfd0864
+#define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3                                                        0x3fff7bfd0865
+#define regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST                                                 0x3fff7bfd089c
+#define regBIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3                                                             0x3fff7bfd089d
+#define regBIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS                                                      0x3fff7bfd089e
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL                                               0x3fff7bfd089f
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL                                               0x3fff7bfd089f
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL                                               0x3fff7bfd08a0
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL                                               0x3fff7bfd08a0
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL                                               0x3fff7bfd08a1
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL                                               0x3fff7bfd08a1
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL                                               0x3fff7bfd08a2
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL                                               0x3fff7bfd08a2
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL                                               0x3fff7bfd08a3
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL                                               0x3fff7bfd08a3
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL                                              0x3fff7bfd08a4
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL                                              0x3fff7bfd08a4
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL                                              0x3fff7bfd08a5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL                                              0x3fff7bfd08a5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL                                              0x3fff7bfd08a6
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL                                              0x3fff7bfd08a6
+#define regBIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST                                                       0x3fff7bfd08a8
+#define regBIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC1_PCIE_ACS_CAP                                                                0x3fff7bfd08a9
+#define regBIF_CFG_DEV1_RC1_PCIE_ACS_CAP_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_RC1_PCIE_ACS_CNTL                                                               0x3fff7bfd08a9
+#define regBIF_CFG_DEV1_RC1_PCIE_ACS_CNTL_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST                                                       0x3fff7bfd0900
+#define regBIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP                                                       0x3fff7bfd0901
+#define regBIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS                                                    0x3fff7bfd0902
+#define regBIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST                                                  0x3fff7bfd0904
+#define regBIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC1_LINK_CAP_16GT                                                               0x3fff7bfd0905
+#define regBIF_CFG_DEV1_RC1_LINK_CAP_16GT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_RC1_LINK_CNTL_16GT                                                              0x3fff7bfd0906
+#define regBIF_CFG_DEV1_RC1_LINK_CNTL_16GT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_RC1_LINK_STATUS_16GT                                                            0x3fff7bfd0907
+#define regBIF_CFG_DEV1_RC1_LINK_STATUS_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                           0x3fff7bfd0908
+#define regBIF_CFG_DEV1_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT                                            0x3fff7bfd0909
+#define regBIF_CFG_DEV1_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT                                            0x3fff7bfd090a
+#define regBIF_CFG_DEV1_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd090c
+#define regBIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd090c
+#define regBIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd090c
+#define regBIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd090c
+#define regBIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd090d
+#define regBIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd090d
+#define regBIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd090d
+#define regBIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd090d
+#define regBIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd090e
+#define regBIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd090e
+#define regBIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd090e
+#define regBIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd090e
+#define regBIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd090f
+#define regBIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd090f
+#define regBIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd090f
+#define regBIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd090f
+#define regBIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST                                                 0x3fff7bfd0910
+#define regBIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC1_MARGINING_PORT_CAP                                                          0x3fff7bfd0911
+#define regBIF_CFG_DEV1_RC1_MARGINING_PORT_CAP_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS                                                       0x3fff7bfd0911
+#define regBIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL                                                  0x3fff7bfd0912
+#define regBIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS                                                0x3fff7bfd0912
+#define regBIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL                                                  0x3fff7bfd0913
+#define regBIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS                                                0x3fff7bfd0913
+#define regBIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL                                                  0x3fff7bfd0914
+#define regBIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS                                                0x3fff7bfd0914
+#define regBIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL                                                  0x3fff7bfd0915
+#define regBIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS                                                0x3fff7bfd0915
+#define regBIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL                                                  0x3fff7bfd0916
+#define regBIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS                                                0x3fff7bfd0916
+#define regBIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL                                                  0x3fff7bfd0917
+#define regBIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS                                                0x3fff7bfd0917
+#define regBIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL                                                  0x3fff7bfd0918
+#define regBIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS                                                0x3fff7bfd0918
+#define regBIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL                                                  0x3fff7bfd0919
+#define regBIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS                                                0x3fff7bfd0919
+#define regBIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL                                                  0x3fff7bfd091a
+#define regBIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS                                                0x3fff7bfd091a
+#define regBIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL                                                  0x3fff7bfd091b
+#define regBIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS                                                0x3fff7bfd091b
+#define regBIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL                                                 0x3fff7bfd091c
+#define regBIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS                                               0x3fff7bfd091c
+#define regBIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL                                                 0x3fff7bfd091d
+#define regBIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS                                               0x3fff7bfd091d
+#define regBIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL                                                 0x3fff7bfd091e
+#define regBIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS                                               0x3fff7bfd091e
+#define regBIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL                                                 0x3fff7bfd091f
+#define regBIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS                                               0x3fff7bfd091f
+#define regBIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL                                                 0x3fff7bfd0920
+#define regBIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS                                               0x3fff7bfd0920
+#define regBIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL                                                 0x3fff7bfd0921
+#define regBIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS                                               0x3fff7bfd0921
+#define regBIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                      5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp
+// base address: 0xfffe00043000
+#define regBIF_CFG_DEV2_RC1_VENDOR_ID                                                                   0x3fff7bfd0c00
+#define regBIF_CFG_DEV2_RC1_VENDOR_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC1_DEVICE_ID                                                                   0x3fff7bfd0c00
+#define regBIF_CFG_DEV2_RC1_DEVICE_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC1_COMMAND                                                                     0x3fff7bfd0c01
+#define regBIF_CFG_DEV2_RC1_COMMAND_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_RC1_STATUS                                                                      0x3fff7bfd0c01
+#define regBIF_CFG_DEV2_RC1_STATUS_BASE_IDX                                                             5
+#define regBIF_CFG_DEV2_RC1_REVISION_ID                                                                 0x3fff7bfd0c02
+#define regBIF_CFG_DEV2_RC1_REVISION_ID_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC1_PROG_INTERFACE                                                              0x3fff7bfd0c02
+#define regBIF_CFG_DEV2_RC1_PROG_INTERFACE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_RC1_SUB_CLASS                                                                   0x3fff7bfd0c02
+#define regBIF_CFG_DEV2_RC1_SUB_CLASS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC1_BASE_CLASS                                                                  0x3fff7bfd0c02
+#define regBIF_CFG_DEV2_RC1_BASE_CLASS_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_RC1_CACHE_LINE                                                                  0x3fff7bfd0c03
+#define regBIF_CFG_DEV2_RC1_CACHE_LINE_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_RC1_LATENCY                                                                     0x3fff7bfd0c03
+#define regBIF_CFG_DEV2_RC1_LATENCY_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_RC1_HEADER                                                                      0x3fff7bfd0c03
+#define regBIF_CFG_DEV2_RC1_HEADER_BASE_IDX                                                             5
+#define regBIF_CFG_DEV2_RC1_BIST                                                                        0x3fff7bfd0c03
+#define regBIF_CFG_DEV2_RC1_BIST_BASE_IDX                                                               5
+#define regBIF_CFG_DEV2_RC1_BASE_ADDR_1                                                                 0x3fff7bfd0c04
+#define regBIF_CFG_DEV2_RC1_BASE_ADDR_1_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC1_BASE_ADDR_2                                                                 0x3fff7bfd0c05
+#define regBIF_CFG_DEV2_RC1_BASE_ADDR_2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY                                                      0x3fff7bfd0c06
+#define regBIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_RC1_IO_BASE_LIMIT                                                               0x3fff7bfd0c07
+#define regBIF_CFG_DEV2_RC1_IO_BASE_LIMIT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_SECONDARY_STATUS                                                            0x3fff7bfd0c07
+#define regBIF_CFG_DEV2_RC1_SECONDARY_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC1_MEM_BASE_LIMIT                                                              0x3fff7bfd0c08
+#define regBIF_CFG_DEV2_RC1_MEM_BASE_LIMIT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_RC1_PREF_BASE_LIMIT                                                             0x3fff7bfd0c09
+#define regBIF_CFG_DEV2_RC1_PREF_BASE_LIMIT_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC1_PREF_BASE_UPPER                                                             0x3fff7bfd0c0a
+#define regBIF_CFG_DEV2_RC1_PREF_BASE_UPPER_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC1_PREF_LIMIT_UPPER                                                            0x3fff7bfd0c0b
+#define regBIF_CFG_DEV2_RC1_PREF_LIMIT_UPPER_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI                                                            0x3fff7bfd0c0c
+#define regBIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC1_CAP_PTR                                                                     0x3fff7bfd0c0d
+#define regBIF_CFG_DEV2_RC1_CAP_PTR_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_RC1_ROM_BASE_ADDR                                                               0x3fff7bfd0c0e
+#define regBIF_CFG_DEV2_RC1_ROM_BASE_ADDR_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_INTERRUPT_LINE                                                              0x3fff7bfd0c0f
+#define regBIF_CFG_DEV2_RC1_INTERRUPT_LINE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_RC1_INTERRUPT_PIN                                                               0x3fff7bfd0c0f
+#define regBIF_CFG_DEV2_RC1_INTERRUPT_PIN_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL                                                             0x3fff7bfd0c0f
+#define regBIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC1_EXT_BRIDGE_CNTL                                                             0x3fff7bfd0c10
+#define regBIF_CFG_DEV2_RC1_EXT_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC1_PMI_CAP_LIST                                                                0x3fff7bfd0c14
+#define regBIF_CFG_DEV2_RC1_PMI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC1_PMI_CAP                                                                     0x3fff7bfd0c14
+#define regBIF_CFG_DEV2_RC1_PMI_CAP_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_RC1_PMI_STATUS_CNTL                                                             0x3fff7bfd0c15
+#define regBIF_CFG_DEV2_RC1_PMI_STATUS_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC1_PCIE_CAP_LIST                                                               0x3fff7bfd0c16
+#define regBIF_CFG_DEV2_RC1_PCIE_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_CAP                                                                    0x3fff7bfd0c16
+#define regBIF_CFG_DEV2_RC1_PCIE_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_RC1_DEVICE_CAP                                                                  0x3fff7bfd0c17
+#define regBIF_CFG_DEV2_RC1_DEVICE_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_RC1_DEVICE_CNTL                                                                 0x3fff7bfd0c18
+#define regBIF_CFG_DEV2_RC1_DEVICE_CNTL_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC1_DEVICE_STATUS                                                               0x3fff7bfd0c18
+#define regBIF_CFG_DEV2_RC1_DEVICE_STATUS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_LINK_CAP                                                                    0x3fff7bfd0c19
+#define regBIF_CFG_DEV2_RC1_LINK_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_RC1_LINK_CNTL                                                                   0x3fff7bfd0c1a
+#define regBIF_CFG_DEV2_RC1_LINK_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC1_LINK_STATUS                                                                 0x3fff7bfd0c1a
+#define regBIF_CFG_DEV2_RC1_LINK_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC1_SLOT_CAP                                                                    0x3fff7bfd0c1b
+#define regBIF_CFG_DEV2_RC1_SLOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_RC1_SLOT_CNTL                                                                   0x3fff7bfd0c1c
+#define regBIF_CFG_DEV2_RC1_SLOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC1_SLOT_STATUS                                                                 0x3fff7bfd0c1c
+#define regBIF_CFG_DEV2_RC1_SLOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC1_ROOT_CNTL                                                                   0x3fff7bfd0c1d
+#define regBIF_CFG_DEV2_RC1_ROOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC1_ROOT_CAP                                                                    0x3fff7bfd0c1d
+#define regBIF_CFG_DEV2_RC1_ROOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_RC1_ROOT_STATUS                                                                 0x3fff7bfd0c1e
+#define regBIF_CFG_DEV2_RC1_ROOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC1_DEVICE_CAP2                                                                 0x3fff7bfd0c1f
+#define regBIF_CFG_DEV2_RC1_DEVICE_CAP2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC1_DEVICE_CNTL2                                                                0x3fff7bfd0c20
+#define regBIF_CFG_DEV2_RC1_DEVICE_CNTL2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC1_DEVICE_STATUS2                                                              0x3fff7bfd0c20
+#define regBIF_CFG_DEV2_RC1_DEVICE_STATUS2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_RC1_LINK_CAP2                                                                   0x3fff7bfd0c21
+#define regBIF_CFG_DEV2_RC1_LINK_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC1_LINK_CNTL2                                                                  0x3fff7bfd0c22
+#define regBIF_CFG_DEV2_RC1_LINK_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_RC1_LINK_STATUS2                                                                0x3fff7bfd0c22
+#define regBIF_CFG_DEV2_RC1_LINK_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC1_SLOT_CAP2                                                                   0x3fff7bfd0c23
+#define regBIF_CFG_DEV2_RC1_SLOT_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_RC1_SLOT_CNTL2                                                                  0x3fff7bfd0c24
+#define regBIF_CFG_DEV2_RC1_SLOT_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_RC1_SLOT_STATUS2                                                                0x3fff7bfd0c24
+#define regBIF_CFG_DEV2_RC1_SLOT_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC1_MSI_CAP_LIST                                                                0x3fff7bfd0c28
+#define regBIF_CFG_DEV2_RC1_MSI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC1_MSI_MSG_CNTL                                                                0x3fff7bfd0c28
+#define regBIF_CFG_DEV2_RC1_MSI_MSG_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC1_MSI_MSG_ADDR_LO                                                             0x3fff7bfd0c29
+#define regBIF_CFG_DEV2_RC1_MSI_MSG_ADDR_LO_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC1_MSI_MSG_ADDR_HI                                                             0x3fff7bfd0c2a
+#define regBIF_CFG_DEV2_RC1_MSI_MSG_ADDR_HI_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC1_MSI_MSG_DATA                                                                0x3fff7bfd0c2a
+#define regBIF_CFG_DEV2_RC1_MSI_MSG_DATA_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA                                                            0x3fff7bfd0c2a
+#define regBIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC1_MSI_MSG_DATA_64                                                             0x3fff7bfd0c2b
+#define regBIF_CFG_DEV2_RC1_MSI_MSG_DATA_64_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_64                                                         0x3fff7bfd0c2b
+#define regBIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_RC1_SSID_CAP_LIST                                                               0x3fff7bfd0c30
+#define regBIF_CFG_DEV2_RC1_SSID_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_SSID_CAP                                                                    0x3fff7bfd0c31
+#define regBIF_CFG_DEV2_RC1_SSID_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST                                                            0x3fff7bfd0c32
+#define regBIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC1_MSI_MAP_CAP                                                                 0x3fff7bfd0c32
+#define regBIF_CFG_DEV2_RC1_MSI_MAP_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                           0x3fff7bfd0c40
+#define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR                                                    0x3fff7bfd0c41
+#define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC1                                                       0x3fff7bfd0c42
+#define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC2                                                       0x3fff7bfd0c43
+#define regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST                                                        0x3fff7bfd0c44
+#define regBIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1                                                       0x3fff7bfd0c45
+#define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2                                                       0x3fff7bfd0c46
+#define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL                                                           0x3fff7bfd0c47
+#define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_STATUS                                                         0x3fff7bfd0c47
+#define regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_STATUS_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP                                                       0x3fff7bfd0c48
+#define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL                                                      0x3fff7bfd0c49
+#define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS                                                    0x3fff7bfd0c4a
+#define regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP                                                       0x3fff7bfd0c4b
+#define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL                                                      0x3fff7bfd0c4c
+#define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS                                                    0x3fff7bfd0c4d
+#define regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                            0x3fff7bfd0c50
+#define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW1                                                     0x3fff7bfd0c51
+#define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW2                                                     0x3fff7bfd0c52
+#define regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                               0x3fff7bfd0c54
+#define regBIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS                                                      0x3fff7bfd0c55
+#define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK                                                        0x3fff7bfd0c56
+#define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY                                                    0x3fff7bfd0c57
+#define regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS                                                        0x3fff7bfd0c58
+#define regBIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK                                                          0x3fff7bfd0c59
+#define regBIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL                                                       0x3fff7bfd0c5a
+#define regBIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG0                                                               0x3fff7bfd0c5b
+#define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG0_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG1                                                               0x3fff7bfd0c5c
+#define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG1_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG2                                                               0x3fff7bfd0c5d
+#define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG3                                                               0x3fff7bfd0c5e
+#define regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG3_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD                                                           0x3fff7bfd0c5f
+#define regBIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS                                                        0x3fff7bfd0c60
+#define regBIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID                                                             0x3fff7bfd0c61
+#define regBIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG0                                                        0x3fff7bfd0c62
+#define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG1                                                        0x3fff7bfd0c63
+#define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG2                                                        0x3fff7bfd0c64
+#define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG3                                                        0x3fff7bfd0c65
+#define regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST                                                 0x3fff7bfd0c9c
+#define regBIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3                                                             0x3fff7bfd0c9d
+#define regBIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_ERROR_STATUS                                                      0x3fff7bfd0c9e
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL                                               0x3fff7bfd0c9f
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL                                               0x3fff7bfd0c9f
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL                                               0x3fff7bfd0ca0
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL                                               0x3fff7bfd0ca0
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL                                               0x3fff7bfd0ca1
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL                                               0x3fff7bfd0ca1
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL                                               0x3fff7bfd0ca2
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL                                               0x3fff7bfd0ca2
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL                                               0x3fff7bfd0ca3
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL                                               0x3fff7bfd0ca3
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL                                              0x3fff7bfd0ca4
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL                                              0x3fff7bfd0ca4
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL                                              0x3fff7bfd0ca5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL                                              0x3fff7bfd0ca5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL                                              0x3fff7bfd0ca6
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL                                              0x3fff7bfd0ca6
+#define regBIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST                                                       0x3fff7bfd0ca8
+#define regBIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC1_PCIE_ACS_CAP                                                                0x3fff7bfd0ca9
+#define regBIF_CFG_DEV2_RC1_PCIE_ACS_CAP_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_RC1_PCIE_ACS_CNTL                                                               0x3fff7bfd0ca9
+#define regBIF_CFG_DEV2_RC1_PCIE_ACS_CNTL_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST                                                       0x3fff7bfd0d00
+#define regBIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP                                                       0x3fff7bfd0d01
+#define regBIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS                                                    0x3fff7bfd0d02
+#define regBIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST                                                  0x3fff7bfd0d04
+#define regBIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC1_LINK_CAP_16GT                                                               0x3fff7bfd0d05
+#define regBIF_CFG_DEV2_RC1_LINK_CAP_16GT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_RC1_LINK_CNTL_16GT                                                              0x3fff7bfd0d06
+#define regBIF_CFG_DEV2_RC1_LINK_CNTL_16GT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_RC1_LINK_STATUS_16GT                                                            0x3fff7bfd0d07
+#define regBIF_CFG_DEV2_RC1_LINK_STATUS_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                           0x3fff7bfd0d08
+#define regBIF_CFG_DEV2_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT                                            0x3fff7bfd0d09
+#define regBIF_CFG_DEV2_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT                                            0x3fff7bfd0d0a
+#define regBIF_CFG_DEV2_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd0d0c
+#define regBIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd0d0c
+#define regBIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd0d0c
+#define regBIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd0d0c
+#define regBIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd0d0d
+#define regBIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd0d0d
+#define regBIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd0d0d
+#define regBIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd0d0d
+#define regBIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd0d0e
+#define regBIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT                                               0x3fff7bfd0d0e
+#define regBIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd0d0e
+#define regBIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd0d0e
+#define regBIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd0d0f
+#define regBIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd0d0f
+#define regBIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd0d0f
+#define regBIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT                                              0x3fff7bfd0d0f
+#define regBIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST                                                 0x3fff7bfd0d10
+#define regBIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC1_MARGINING_PORT_CAP                                                          0x3fff7bfd0d11
+#define regBIF_CFG_DEV2_RC1_MARGINING_PORT_CAP_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS                                                       0x3fff7bfd0d11
+#define regBIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL                                                  0x3fff7bfd0d12
+#define regBIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS                                                0x3fff7bfd0d12
+#define regBIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL                                                  0x3fff7bfd0d13
+#define regBIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS                                                0x3fff7bfd0d13
+#define regBIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL                                                  0x3fff7bfd0d14
+#define regBIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS                                                0x3fff7bfd0d14
+#define regBIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL                                                  0x3fff7bfd0d15
+#define regBIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS                                                0x3fff7bfd0d15
+#define regBIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL                                                  0x3fff7bfd0d16
+#define regBIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS                                                0x3fff7bfd0d16
+#define regBIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL                                                  0x3fff7bfd0d17
+#define regBIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS                                                0x3fff7bfd0d17
+#define regBIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL                                                  0x3fff7bfd0d18
+#define regBIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS                                                0x3fff7bfd0d18
+#define regBIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL                                                  0x3fff7bfd0d19
+#define regBIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS                                                0x3fff7bfd0d19
+#define regBIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL                                                  0x3fff7bfd0d1a
+#define regBIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS                                                0x3fff7bfd0d1a
+#define regBIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL                                                  0x3fff7bfd0d1b
+#define regBIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS                                                0x3fff7bfd0d1b
+#define regBIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL                                                 0x3fff7bfd0d1c
+#define regBIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS                                               0x3fff7bfd0d1c
+#define regBIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL                                                 0x3fff7bfd0d1d
+#define regBIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS                                               0x3fff7bfd0d1d
+#define regBIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL                                                 0x3fff7bfd0d1e
+#define regBIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS                                               0x3fff7bfd0d1e
+#define regBIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL                                                 0x3fff7bfd0d1f
+#define regBIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS                                               0x3fff7bfd0d1f
+#define regBIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL                                                 0x3fff7bfd0d20
+#define regBIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS                                               0x3fff7bfd0d20
+#define regBIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL                                                 0x3fff7bfd0d21
+#define regBIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS                                               0x3fff7bfd0d21
+#define regBIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                      5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0xfffe12100000
+#define regBIF_CFG_DEV0_EPF0_1_VENDOR_ID                                                                0x3fff80800000
+#define regBIF_CFG_DEV0_EPF0_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_ID                                                                0x3fff80800000
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_1_COMMAND                                                                  0x3fff80800001
+#define regBIF_CFG_DEV0_EPF0_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_1_STATUS                                                                   0x3fff80800001
+#define regBIF_CFG_DEV0_EPF0_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_1_REVISION_ID                                                              0x3fff80800002
+#define regBIF_CFG_DEV0_EPF0_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE                                                           0x3fff80800002
+#define regBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_SUB_CLASS                                                                0x3fff80800002
+#define regBIF_CFG_DEV0_EPF0_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_1_BASE_CLASS                                                               0x3fff80800002
+#define regBIF_CFG_DEV0_EPF0_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_1_CACHE_LINE                                                               0x3fff80800003
+#define regBIF_CFG_DEV0_EPF0_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LATENCY                                                                  0x3fff80800003
+#define regBIF_CFG_DEV0_EPF0_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_1_HEADER                                                                   0x3fff80800003
+#define regBIF_CFG_DEV0_EPF0_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_1_BIST                                                                     0x3fff80800003
+#define regBIF_CFG_DEV0_EPF0_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1                                                              0x3fff80800004
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2                                                              0x3fff80800005
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3                                                              0x3fff80800006
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4                                                              0x3fff80800007
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5                                                              0x3fff80800008
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6                                                              0x3fff80800009
+#define regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR                                                          0x3fff8080000a
+#define regBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_1_ADAPTER_ID                                                               0x3fff8080000b
+#define regBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR                                                            0x3fff8080000c
+#define regBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_CAP_PTR                                                                  0x3fff8080000d
+#define regBIF_CFG_DEV0_EPF0_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE                                                           0x3fff8080000f
+#define regBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN                                                            0x3fff8080000f
+#define regBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_MIN_GRANT                                                                0x3fff8080000f
+#define regBIF_CFG_DEV0_EPF0_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_1_MAX_LATENCY                                                              0x3fff8080000f
+#define regBIF_CFG_DEV0_EPF0_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST                                                          0x3fff80800012
+#define regBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W                                                             0x3fff80800013
+#define regBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST                                                             0x3fff80800014
+#define regBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PMI_CAP                                                                  0x3fff80800014
+#define regBIF_CFG_DEV0_EPF0_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL                                                          0x3fff80800015
+#define regBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST                                                            0x3fff80800019
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_CAP                                                                 0x3fff80800019
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_CAP                                                               0x3fff8080001a
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL                                                              0x3fff8080001b
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS                                                            0x3fff8080001b
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CAP                                                                 0x3fff8080001c
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL                                                                0x3fff8080001d
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS                                                              0x3fff8080001d
+#define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2                                                              0x3fff80800022
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2                                                             0x3fff80800023
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2                                                           0x3fff80800023
+#define regBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CAP2                                                                0x3fff80800024
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL2                                                               0x3fff80800025
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS2                                                             0x3fff80800025
+#define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST                                                             0x3fff80800028
+#define regBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL                                                             0x3fff80800028
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO                                                          0x3fff80800029
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI                                                          0x3fff8080002a
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA                                                             0x3fff8080002a
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA                                                         0x3fff8080002a
+#define regBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MASK                                                                 0x3fff8080002b
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64                                                          0x3fff8080002b
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64                                                      0x3fff8080002b
+#define regBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MASK_64                                                              0x3fff8080002c
+#define regBIF_CFG_DEV0_EPF0_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_PENDING                                                              0x3fff8080002c
+#define regBIF_CFG_DEV0_EPF0_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64                                                           0x3fff8080002d
+#define regBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST                                                            0x3fff80800030
+#define regBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL                                                            0x3fff80800030
+#define regBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_MSIX_TABLE                                                               0x3fff80800031
+#define regBIF_CFG_DEV0_EPF0_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_1_MSIX_PBA                                                                 0x3fff80800032
+#define regBIF_CFG_DEV0_EPF0_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80800040
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80800041
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80800042
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80800043
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST                                                     0x3fff80800044
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1                                                    0x3fff80800045
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2                                                    0x3fff80800046
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL                                                        0x3fff80800047
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS                                                      0x3fff80800047
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP                                                    0x3fff80800048
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL                                                   0x3fff80800049
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS                                                 0x3fff8080004a
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP                                                    0x3fff8080004b
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL                                                   0x3fff8080004c
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS                                                 0x3fff8080004d
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                         0x3fff80800050
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1                                                  0x3fff80800051
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2                                                  0x3fff80800052
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80800054
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80800055
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80800056
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80800057
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80800058
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK                                                       0x3fff80800059
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff8080005a
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0                                                            0x3fff8080005b
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1                                                            0x3fff8080005c
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2                                                            0x3fff8080005d
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3                                                            0x3fff8080005e
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80800062
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80800063
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80800064
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80800065
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80800080
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP                                                            0x3fff80800081
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL                                                           0x3fff80800082
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP                                                            0x3fff80800083
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL                                                           0x3fff80800084
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP                                                            0x3fff80800085
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL                                                           0x3fff80800086
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP                                                            0x3fff80800087
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL                                                           0x3fff80800088
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP                                                            0x3fff80800089
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL                                                           0x3fff8080008a
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP                                                            0x3fff8080008b
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL                                                           0x3fff8080008c
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80800090
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80800091
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80800092
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80800093
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80800094
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP                                                             0x3fff80800095
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80800096
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS                                                          0x3fff80800097
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL                                                            0x3fff80800097
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80800098
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80800098
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80800098
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80800098
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80800099
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80800099
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80800099
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80800099
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST                                              0x3fff8080009c
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3                                                          0x3fff8080009d
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS                                                   0x3fff8080009e
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL                                            0x3fff8080009f
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL                                            0x3fff8080009f
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL                                            0x3fff808000a0
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL                                            0x3fff808000a0
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL                                            0x3fff808000a1
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL                                            0x3fff808000a1
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL                                            0x3fff808000a2
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL                                            0x3fff808000a2
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL                                            0x3fff808000a3
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL                                            0x3fff808000a3
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL                                           0x3fff808000a4
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL                                           0x3fff808000a4
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL                                           0x3fff808000a5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL                                           0x3fff808000a5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL                                           0x3fff808000a6
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL                                           0x3fff808000a6
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff808000a8
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP                                                             0x3fff808000a9
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL                                                            0x3fff808000a9
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST                                                    0x3fff808000ac
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP                                                             0x3fff808000ad
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL                                                            0x3fff808000ad
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST                                               0x3fff808000b0
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL                                                       0x3fff808000b1
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS                                                     0x3fff808000b1
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY                                          0x3fff808000b2
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC                                             0x3fff808000b3
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff808000b4
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP                                                           0x3fff808000b5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL                                                          0x3fff808000b5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST                                                     0x3fff808000bc
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP                                                              0x3fff808000bd
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL                                                             0x3fff808000bd
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0                                                            0x3fff808000be
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1                                                            0x3fff808000bf
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0                                                             0x3fff808000c0
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1                                                             0x3fff808000c1
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0                                                       0x3fff808000c2
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1                                                       0x3fff808000c3
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                             0x3fff808000c4
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                             0x3fff808000c5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST                                                    0x3fff808000c8
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP                                                             0x3fff808000c9
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff808000ca
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP                                                             0x3fff808000cb
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL                                                            0x3fff808000cb
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST                                                  0x3fff808000cc
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP                                                           0x3fff808000cd
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL                                                       0x3fff808000ce
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS                                                        0x3fff808000ce
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS                                                   0x3fff808000cf
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS                                                     0x3fff808000cf
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS                                                       0x3fff808000d0
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK                                                 0x3fff808000d0
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET                                               0x3fff808000d1
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE                                                     0x3fff808000d1
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID                                                  0x3fff808000d2
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                           0x3fff808000d3
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                              0x3fff808000d4
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0                                                0x3fff808000d5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1                                                0x3fff808000d6
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2                                                0x3fff808000d7
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3                                                0x3fff808000d8
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4                                                0x3fff808000d9
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5                                                0x3fff808000da
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                               0x3fff808000db
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff808000dc
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP                                                        0x3fff808000dd
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL                                                       0x3fff808000de
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST                                                    0x3fff80800100
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP                                                    0x3fff80800101
+#define regBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS                                                 0x3fff80800102
+#define regBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST                                               0x3fff80800104
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT                                                            0x3fff80800105
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT                                                           0x3fff80800106
+#define regBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT                                                         0x3fff80800107
+#define regBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0x3fff80800108
+#define regBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0x3fff80800109
+#define regBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0x3fff8080010a
+#define regBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT                                            0x3fff8080010c
+#define regBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT                                            0x3fff8080010c
+#define regBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT                                            0x3fff8080010c
+#define regBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT                                            0x3fff8080010c
+#define regBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT                                            0x3fff8080010d
+#define regBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT                                            0x3fff8080010d
+#define regBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT                                            0x3fff8080010d
+#define regBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT                                            0x3fff8080010d
+#define regBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT                                            0x3fff8080010e
+#define regBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT                                            0x3fff8080010e
+#define regBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT                                           0x3fff8080010e
+#define regBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT                                           0x3fff8080010e
+#define regBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT                                           0x3fff8080010f
+#define regBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT                                           0x3fff8080010f
+#define regBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT                                           0x3fff8080010f
+#define regBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT                                           0x3fff8080010f
+#define regBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST                                              0x3fff80800110
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP                                                       0x3fff80800111
+#define regBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS                                                    0x3fff80800111
+#define regBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL                                               0x3fff80800112
+#define regBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS                                             0x3fff80800112
+#define regBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL                                               0x3fff80800113
+#define regBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS                                             0x3fff80800113
+#define regBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL                                               0x3fff80800114
+#define regBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS                                             0x3fff80800114
+#define regBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL                                               0x3fff80800115
+#define regBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS                                             0x3fff80800115
+#define regBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL                                               0x3fff80800116
+#define regBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS                                             0x3fff80800116
+#define regBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL                                               0x3fff80800117
+#define regBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS                                             0x3fff80800117
+#define regBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL                                               0x3fff80800118
+#define regBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS                                             0x3fff80800118
+#define regBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL                                               0x3fff80800119
+#define regBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS                                             0x3fff80800119
+#define regBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL                                               0x3fff8080011a
+#define regBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS                                             0x3fff8080011a
+#define regBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL                                               0x3fff8080011b
+#define regBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS                                             0x3fff8080011b
+#define regBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL                                              0x3fff8080011c
+#define regBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS                                            0x3fff8080011c
+#define regBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL                                              0x3fff8080011d
+#define regBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS                                            0x3fff8080011d
+#define regBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL                                              0x3fff8080011e
+#define regBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS                                            0x3fff8080011e
+#define regBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL                                              0x3fff8080011f
+#define regBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS                                            0x3fff8080011f
+#define regBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL                                              0x3fff80800120
+#define regBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS                                            0x3fff80800120
+#define regBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL                                              0x3fff80800121
+#define regBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS                                            0x3fff80800121
+#define regBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                          0x3fff80800130
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP                                                  0x3fff80800131
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL                                                 0x3fff80800132
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP                                                  0x3fff80800133
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL                                                 0x3fff80800134
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP                                                  0x3fff80800135
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL                                                 0x3fff80800136
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP                                                  0x3fff80800137
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL                                                 0x3fff80800138
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP                                                  0x3fff80800139
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL                                                 0x3fff8080013a
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP                                                  0x3fff8080013b
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL                                                 0x3fff8080013c
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                 0x3fff80800140
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                          0x3fff80800141
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                             0x3fff80800142
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_BASE_IDX                    5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                              0x3fff80800143
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                              0x3fff80800144
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                            0x3fff80800145
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                            0x3fff80800146
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                            0x3fff80800147
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                            0x3fff80800148
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                                  0x3fff80800149
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                 0x3fff8080014a
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                                  0x3fff8080014b
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                   0x3fff8080014c
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                     0x3fff8080014d
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX            5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                   0x3fff8080014e
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                   0x3fff8080014f
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                   0x3fff80800150
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                   0x3fff80800151
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                   0x3fff80800152
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                   0x3fff80800153
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                   0x3fff80800154
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                   0x3fff80800155
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                   0x3fff80800156
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                   0x3fff80800157
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                                  0x3fff80800158
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                                  0x3fff80800159
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                                  0x3fff8080015a
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                                  0x3fff8080015b
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                                  0x3fff8080015c
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                                  0x3fff8080015d
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB                                  0x3fff8080015e
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB                                  0x3fff8080015f
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB                                  0x3fff80800160
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB                                  0x3fff80800161
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB                                  0x3fff80800162
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB                                  0x3fff80800163
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB                                  0x3fff80800164
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB                                  0x3fff80800165
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB                                  0x3fff80800166
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB                                  0x3fff80800167
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB                                  0x3fff80800168
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB                                  0x3fff80800169
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB                                  0x3fff8080016a
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB                                  0x3fff8080016b
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB                                  0x3fff8080016c
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0                               0x3fff80800170
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1                               0x3fff80800171
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2                               0x3fff80800172
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3                               0x3fff80800173
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4                               0x3fff80800174
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5                               0x3fff80800175
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6                               0x3fff80800176
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7                               0x3fff80800177
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8                               0x3fff80800178
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0                               0x3fff8080017c
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1                               0x3fff8080017d
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2                               0x3fff8080017e
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3                               0x3fff8080017f
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4                               0x3fff80800180
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5                               0x3fff80800181
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6                               0x3fff80800182
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7                               0x3fff80800183
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8                               0x3fff80800184
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0                               0x3fff80800188
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1                               0x3fff80800189
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2                               0x3fff8080018a
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3                               0x3fff8080018b
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4                               0x3fff8080018c
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5                               0x3fff8080018d
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6                               0x3fff8080018e
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7                               0x3fff8080018f
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8                               0x3fff80800190
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0                              0x3fff80800194
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1                              0x3fff80800195
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2                              0x3fff80800196
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3                              0x3fff80800197
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4                              0x3fff80800198
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5                              0x3fff80800199
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6                              0x3fff8080019a
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7                              0x3fff8080019b
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8                              0x3fff8080019c
+#define regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_BASE_IDX                     5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+// base address: 0xfffe12101000
+#define regBIF_CFG_DEV0_EPF1_1_VENDOR_ID                                                                0x3fff80800400
+#define regBIF_CFG_DEV0_EPF1_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_ID                                                                0x3fff80800400
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_1_COMMAND                                                                  0x3fff80800401
+#define regBIF_CFG_DEV0_EPF1_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_1_STATUS                                                                   0x3fff80800401
+#define regBIF_CFG_DEV0_EPF1_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF1_1_REVISION_ID                                                              0x3fff80800402
+#define regBIF_CFG_DEV0_EPF1_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE                                                           0x3fff80800402
+#define regBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_SUB_CLASS                                                                0x3fff80800402
+#define regBIF_CFG_DEV0_EPF1_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_1_BASE_CLASS                                                               0x3fff80800402
+#define regBIF_CFG_DEV0_EPF1_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_1_CACHE_LINE                                                               0x3fff80800403
+#define regBIF_CFG_DEV0_EPF1_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LATENCY                                                                  0x3fff80800403
+#define regBIF_CFG_DEV0_EPF1_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_1_HEADER                                                                   0x3fff80800403
+#define regBIF_CFG_DEV0_EPF1_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF1_1_BIST                                                                     0x3fff80800403
+#define regBIF_CFG_DEV0_EPF1_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1                                                              0x3fff80800404
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2                                                              0x3fff80800405
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3                                                              0x3fff80800406
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4                                                              0x3fff80800407
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5                                                              0x3fff80800408
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6                                                              0x3fff80800409
+#define regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR                                                          0x3fff8080040a
+#define regBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_1_ADAPTER_ID                                                               0x3fff8080040b
+#define regBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR                                                            0x3fff8080040c
+#define regBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_CAP_PTR                                                                  0x3fff8080040d
+#define regBIF_CFG_DEV0_EPF1_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE                                                           0x3fff8080040f
+#define regBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN                                                            0x3fff8080040f
+#define regBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_MIN_GRANT                                                                0x3fff8080040f
+#define regBIF_CFG_DEV0_EPF1_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_1_MAX_LATENCY                                                              0x3fff8080040f
+#define regBIF_CFG_DEV0_EPF1_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST                                                          0x3fff80800412
+#define regBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W                                                             0x3fff80800413
+#define regBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST                                                             0x3fff80800414
+#define regBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PMI_CAP                                                                  0x3fff80800414
+#define regBIF_CFG_DEV0_EPF1_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL                                                          0x3fff80800415
+#define regBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST                                                            0x3fff80800419
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_CAP                                                                 0x3fff80800419
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_CAP                                                               0x3fff8080041a
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL                                                              0x3fff8080041b
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS                                                            0x3fff8080041b
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CAP                                                                 0x3fff8080041c
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL                                                                0x3fff8080041d
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS                                                              0x3fff8080041d
+#define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2                                                              0x3fff80800422
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2                                                             0x3fff80800423
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2                                                           0x3fff80800423
+#define regBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CAP2                                                                0x3fff80800424
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL2                                                               0x3fff80800425
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS2                                                             0x3fff80800425
+#define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST                                                             0x3fff80800428
+#define regBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL                                                             0x3fff80800428
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO                                                          0x3fff80800429
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI                                                          0x3fff8080042a
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA                                                             0x3fff8080042a
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA                                                         0x3fff8080042a
+#define regBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MASK                                                                 0x3fff8080042b
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64                                                          0x3fff8080042b
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64                                                      0x3fff8080042b
+#define regBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MASK_64                                                              0x3fff8080042c
+#define regBIF_CFG_DEV0_EPF1_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_PENDING                                                              0x3fff8080042c
+#define regBIF_CFG_DEV0_EPF1_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64                                                           0x3fff8080042d
+#define regBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST                                                            0x3fff80800430
+#define regBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL                                                            0x3fff80800430
+#define regBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_MSIX_TABLE                                                               0x3fff80800431
+#define regBIF_CFG_DEV0_EPF1_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_1_MSIX_PBA                                                                 0x3fff80800432
+#define regBIF_CFG_DEV0_EPF1_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80800440
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80800441
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80800442
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80800443
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST                                                     0x3fff80800444
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1                                                    0x3fff80800445
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2                                                    0x3fff80800446
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL                                                        0x3fff80800447
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS                                                      0x3fff80800447
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP                                                    0x3fff80800448
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL                                                   0x3fff80800449
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS                                                 0x3fff8080044a
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP                                                    0x3fff8080044b
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL                                                   0x3fff8080044c
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS                                                 0x3fff8080044d
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                         0x3fff80800450
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1                                                  0x3fff80800451
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2                                                  0x3fff80800452
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80800454
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80800455
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80800456
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80800457
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80800458
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK                                                       0x3fff80800459
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff8080045a
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0                                                            0x3fff8080045b
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1                                                            0x3fff8080045c
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2                                                            0x3fff8080045d
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3                                                            0x3fff8080045e
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80800462
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80800463
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80800464
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80800465
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80800480
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP                                                            0x3fff80800481
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL                                                           0x3fff80800482
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP                                                            0x3fff80800483
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL                                                           0x3fff80800484
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP                                                            0x3fff80800485
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL                                                           0x3fff80800486
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP                                                            0x3fff80800487
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL                                                           0x3fff80800488
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP                                                            0x3fff80800489
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL                                                           0x3fff8080048a
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP                                                            0x3fff8080048b
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL                                                           0x3fff8080048c
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80800490
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80800491
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80800492
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80800493
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80800494
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP                                                             0x3fff80800495
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80800496
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS                                                          0x3fff80800497
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL                                                            0x3fff80800497
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80800498
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80800498
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80800498
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80800498
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80800499
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80800499
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80800499
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80800499
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST                                              0x3fff8080049c
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3                                                          0x3fff8080049d
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS                                                   0x3fff8080049e
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL                                            0x3fff8080049f
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL                                            0x3fff8080049f
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL                                            0x3fff808004a0
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL                                            0x3fff808004a0
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL                                            0x3fff808004a1
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL                                            0x3fff808004a1
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL                                            0x3fff808004a2
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL                                            0x3fff808004a2
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL                                            0x3fff808004a3
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL                                            0x3fff808004a3
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL                                           0x3fff808004a4
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL                                           0x3fff808004a4
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL                                           0x3fff808004a5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL                                           0x3fff808004a5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL                                           0x3fff808004a6
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL                                           0x3fff808004a6
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff808004a8
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP                                                             0x3fff808004a9
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL                                                            0x3fff808004a9
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST                                                    0x3fff808004ac
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP                                                             0x3fff808004ad
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL                                                            0x3fff808004ad
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST                                               0x3fff808004b0
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL                                                       0x3fff808004b1
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS                                                     0x3fff808004b1
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY                                          0x3fff808004b2
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC                                             0x3fff808004b3
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff808004b4
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP                                                           0x3fff808004b5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL                                                          0x3fff808004b5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST                                                     0x3fff808004bc
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP                                                              0x3fff808004bd
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL                                                             0x3fff808004bd
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0                                                            0x3fff808004be
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1                                                            0x3fff808004bf
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0                                                             0x3fff808004c0
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1                                                             0x3fff808004c1
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0                                                       0x3fff808004c2
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1                                                       0x3fff808004c3
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0                                             0x3fff808004c4
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1                                             0x3fff808004c5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST                                                    0x3fff808004c8
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP                                                             0x3fff808004c9
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff808004ca
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP                                                             0x3fff808004cb
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL                                                            0x3fff808004cb
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST                                                  0x3fff808004cc
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP                                                           0x3fff808004cd
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL                                                       0x3fff808004ce
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS                                                        0x3fff808004ce
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS                                                   0x3fff808004cf
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS                                                     0x3fff808004cf
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS                                                       0x3fff808004d0
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK                                                 0x3fff808004d0
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET                                               0x3fff808004d1
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE                                                     0x3fff808004d1
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID                                                  0x3fff808004d2
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                           0x3fff808004d3
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                              0x3fff808004d4
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0                                                0x3fff808004d5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1                                                0x3fff808004d6
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2                                                0x3fff808004d7
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3                                                0x3fff808004d8
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4                                                0x3fff808004d9
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5                                                0x3fff808004da
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                               0x3fff808004db
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff808004dc
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP                                                        0x3fff808004dd
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL                                                       0x3fff808004de
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST                                                    0x3fff80800500
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP                                                    0x3fff80800501
+#define regBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS                                                 0x3fff80800502
+#define regBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST                                               0x3fff80800504
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT                                                            0x3fff80800505
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT                                                           0x3fff80800506
+#define regBIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT                                                         0x3fff80800507
+#define regBIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0x3fff80800508
+#define regBIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0x3fff80800509
+#define regBIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0x3fff8080050a
+#define regBIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT                                            0x3fff8080050c
+#define regBIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT                                            0x3fff8080050c
+#define regBIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT                                            0x3fff8080050c
+#define regBIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT                                            0x3fff8080050c
+#define regBIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT                                            0x3fff8080050d
+#define regBIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT                                            0x3fff8080050d
+#define regBIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT                                            0x3fff8080050d
+#define regBIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT                                            0x3fff8080050d
+#define regBIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT                                            0x3fff8080050e
+#define regBIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT                                            0x3fff8080050e
+#define regBIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT                                           0x3fff8080050e
+#define regBIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT                                           0x3fff8080050e
+#define regBIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT                                           0x3fff8080050f
+#define regBIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT                                           0x3fff8080050f
+#define regBIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT                                           0x3fff8080050f
+#define regBIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT                                           0x3fff8080050f
+#define regBIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST                                              0x3fff80800510
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP                                                       0x3fff80800511
+#define regBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS                                                    0x3fff80800511
+#define regBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL                                               0x3fff80800512
+#define regBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS                                             0x3fff80800512
+#define regBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL                                               0x3fff80800513
+#define regBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS                                             0x3fff80800513
+#define regBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL                                               0x3fff80800514
+#define regBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS                                             0x3fff80800514
+#define regBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL                                               0x3fff80800515
+#define regBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS                                             0x3fff80800515
+#define regBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL                                               0x3fff80800516
+#define regBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS                                             0x3fff80800516
+#define regBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL                                               0x3fff80800517
+#define regBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS                                             0x3fff80800517
+#define regBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL                                               0x3fff80800518
+#define regBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS                                             0x3fff80800518
+#define regBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL                                               0x3fff80800519
+#define regBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS                                             0x3fff80800519
+#define regBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL                                               0x3fff8080051a
+#define regBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS                                             0x3fff8080051a
+#define regBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL                                               0x3fff8080051b
+#define regBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS                                             0x3fff8080051b
+#define regBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL                                              0x3fff8080051c
+#define regBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS                                            0x3fff8080051c
+#define regBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL                                              0x3fff8080051d
+#define regBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS                                            0x3fff8080051d
+#define regBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL                                              0x3fff8080051e
+#define regBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS                                            0x3fff8080051e
+#define regBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL                                              0x3fff8080051f
+#define regBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS                                            0x3fff8080051f
+#define regBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL                                              0x3fff80800520
+#define regBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS                                            0x3fff80800520
+#define regBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL                                              0x3fff80800521
+#define regBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS                                            0x3fff80800521
+#define regBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                          0x3fff80800530
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP                                                  0x3fff80800531
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL                                                 0x3fff80800532
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP                                                  0x3fff80800533
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL                                                 0x3fff80800534
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP                                                  0x3fff80800535
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL                                                 0x3fff80800536
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP                                                  0x3fff80800537
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL                                                 0x3fff80800538
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP                                                  0x3fff80800539
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL                                                 0x3fff8080053a
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP                                                  0x3fff8080053b
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL                                                 0x3fff8080053c
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                 0x3fff80800540
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                          0x3fff80800541
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                             0x3fff80800542
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_BASE_IDX                    5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                              0x3fff80800543
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                              0x3fff80800544
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                            0x3fff80800545
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                            0x3fff80800546
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                            0x3fff80800547
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                            0x3fff80800548
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT                                  0x3fff80800549
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                 0x3fff8080054a
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS                                  0x3fff8080054b
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                   0x3fff8080054c
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                     0x3fff8080054d
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX            5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB                                   0x3fff8080054e
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB                                   0x3fff8080054f
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB                                   0x3fff80800550
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB                                   0x3fff80800551
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB                                   0x3fff80800552
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB                                   0x3fff80800553
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB                                   0x3fff80800554
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB                                   0x3fff80800555
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB                                   0x3fff80800556
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB                                   0x3fff80800557
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB                                  0x3fff80800558
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB                                  0x3fff80800559
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB                                  0x3fff8080055a
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB                                  0x3fff8080055b
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB                                  0x3fff8080055c
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB                                  0x3fff8080055d
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB                                  0x3fff8080055e
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB                                  0x3fff8080055f
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB                                  0x3fff80800560
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB                                  0x3fff80800561
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB                                  0x3fff80800562
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB                                  0x3fff80800563
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB                                  0x3fff80800564
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB                                  0x3fff80800565
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB                                  0x3fff80800566
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB                                  0x3fff80800567
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB                                  0x3fff80800568
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB                                  0x3fff80800569
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB                                  0x3fff8080056a
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB                                  0x3fff8080056b
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB                                  0x3fff8080056c
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX                         5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0                               0x3fff80800570
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1                               0x3fff80800571
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2                               0x3fff80800572
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3                               0x3fff80800573
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4                               0x3fff80800574
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5                               0x3fff80800575
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6                               0x3fff80800576
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7                               0x3fff80800577
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8                               0x3fff80800578
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0                               0x3fff8080057c
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1                               0x3fff8080057d
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2                               0x3fff8080057e
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3                               0x3fff8080057f
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4                               0x3fff80800580
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5                               0x3fff80800581
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6                               0x3fff80800582
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7                               0x3fff80800583
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8                               0x3fff80800584
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0                               0x3fff80800588
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1                               0x3fff80800589
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2                               0x3fff8080058a
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3                               0x3fff8080058b
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4                               0x3fff8080058c
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5                               0x3fff8080058d
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6                               0x3fff8080058e
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7                               0x3fff8080058f
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8                               0x3fff80800590
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0                              0x3fff80800594
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1                              0x3fff80800595
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2                              0x3fff80800596
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3                              0x3fff80800597
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4                              0x3fff80800598
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5                              0x3fff80800599
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6                              0x3fff8080059a
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7                              0x3fff8080059b
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8                              0x3fff8080059c
+#define regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_BASE_IDX                     5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+// base address: 0xfffe12102000
+#define regBIF_CFG_DEV0_EPF2_1_VENDOR_ID                                                                0x3fff80800800
+#define regBIF_CFG_DEV0_EPF2_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_ID                                                                0x3fff80800800
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_1_COMMAND                                                                  0x3fff80800801
+#define regBIF_CFG_DEV0_EPF2_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF2_1_STATUS                                                                   0x3fff80800801
+#define regBIF_CFG_DEV0_EPF2_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF2_1_REVISION_ID                                                              0x3fff80800802
+#define regBIF_CFG_DEV0_EPF2_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE                                                           0x3fff80800802
+#define regBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_1_SUB_CLASS                                                                0x3fff80800802
+#define regBIF_CFG_DEV0_EPF2_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_1_BASE_CLASS                                                               0x3fff80800802
+#define regBIF_CFG_DEV0_EPF2_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_1_CACHE_LINE                                                               0x3fff80800803
+#define regBIF_CFG_DEV0_EPF2_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_1_LATENCY                                                                  0x3fff80800803
+#define regBIF_CFG_DEV0_EPF2_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF2_1_HEADER                                                                   0x3fff80800803
+#define regBIF_CFG_DEV0_EPF2_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF2_1_BIST                                                                     0x3fff80800803
+#define regBIF_CFG_DEV0_EPF2_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1                                                              0x3fff80800804
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2                                                              0x3fff80800805
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3                                                              0x3fff80800806
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4                                                              0x3fff80800807
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5                                                              0x3fff80800808
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6                                                              0x3fff80800809
+#define regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR                                                          0x3fff8080080a
+#define regBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_1_ADAPTER_ID                                                               0x3fff8080080b
+#define regBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR                                                            0x3fff8080080c
+#define regBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_CAP_PTR                                                                  0x3fff8080080d
+#define regBIF_CFG_DEV0_EPF2_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE                                                           0x3fff8080080f
+#define regBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN                                                            0x3fff8080080f
+#define regBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_MIN_GRANT                                                                0x3fff8080080f
+#define regBIF_CFG_DEV0_EPF2_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_1_MAX_LATENCY                                                              0x3fff8080080f
+#define regBIF_CFG_DEV0_EPF2_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST                                                          0x3fff80800812
+#define regBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W                                                             0x3fff80800813
+#define regBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST                                                             0x3fff80800814
+#define regBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_1_PMI_CAP                                                                  0x3fff80800814
+#define regBIF_CFG_DEV0_EPF2_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL                                                          0x3fff80800815
+#define regBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_1_SBRN                                                                     0x3fff80800818
+#define regBIF_CFG_DEV0_EPF2_1_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF2_1_FLADJ                                                                    0x3fff80800818
+#define regBIF_CFG_DEV0_EPF2_1_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD                                                             0x3fff80800818
+#define regBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST                                                            0x3fff80800819
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_CAP                                                                 0x3fff80800819
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_CAP                                                               0x3fff8080081a
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL                                                              0x3fff8080081b
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS                                                            0x3fff8080081b
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_LINK_CAP                                                                 0x3fff8080081c
+#define regBIF_CFG_DEV0_EPF2_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF2_1_LINK_CNTL                                                                0x3fff8080081d
+#define regBIF_CFG_DEV0_EPF2_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_1_LINK_STATUS                                                              0x3fff8080081d
+#define regBIF_CFG_DEV0_EPF2_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2                                                              0x3fff80800822
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2                                                             0x3fff80800823
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2                                                           0x3fff80800823
+#define regBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_1_LINK_CAP2                                                                0x3fff80800824
+#define regBIF_CFG_DEV0_EPF2_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF2_1_LINK_CNTL2                                                               0x3fff80800825
+#define regBIF_CFG_DEV0_EPF2_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_1_LINK_STATUS2                                                             0x3fff80800825
+#define regBIF_CFG_DEV0_EPF2_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST                                                             0x3fff80800828
+#define regBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL                                                             0x3fff80800828
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO                                                          0x3fff80800829
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI                                                          0x3fff8080082a
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA                                                             0x3fff8080082a
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA                                                         0x3fff8080082a
+#define regBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MASK                                                                 0x3fff8080082b
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64                                                          0x3fff8080082b
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64                                                      0x3fff8080082b
+#define regBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MASK_64                                                              0x3fff8080082c
+#define regBIF_CFG_DEV0_EPF2_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_PENDING                                                              0x3fff8080082c
+#define regBIF_CFG_DEV0_EPF2_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64                                                           0x3fff8080082d
+#define regBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST                                                            0x3fff80800830
+#define regBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL                                                            0x3fff80800830
+#define regBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_MSIX_TABLE                                                               0x3fff80800831
+#define regBIF_CFG_DEV0_EPF2_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF2_1_MSIX_PBA                                                                 0x3fff80800832
+#define regBIF_CFG_DEV0_EPF2_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80800840
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80800841
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80800842
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80800843
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80800854
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80800855
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80800856
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80800857
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80800858
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK                                                       0x3fff80800859
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff8080085a
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0                                                            0x3fff8080085b
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1                                                            0x3fff8080085c
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2                                                            0x3fff8080085d
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3                                                            0x3fff8080085e
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80800862
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80800863
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80800864
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80800865
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80800880
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP                                                            0x3fff80800881
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL                                                           0x3fff80800882
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP                                                            0x3fff80800883
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL                                                           0x3fff80800884
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP                                                            0x3fff80800885
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL                                                           0x3fff80800886
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP                                                            0x3fff80800887
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL                                                           0x3fff80800888
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP                                                            0x3fff80800889
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL                                                           0x3fff8080088a
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP                                                            0x3fff8080088b
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL                                                           0x3fff8080088c
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80800890
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80800891
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80800892
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80800893
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80800894
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP                                                             0x3fff80800895
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80800896
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS                                                          0x3fff80800897
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL                                                            0x3fff80800897
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80800898
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80800898
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80800898
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80800898
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80800899
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80800899
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80800899
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80800899
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff808008a8
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP                                                             0x3fff808008a9
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL                                                            0x3fff808008a9
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff808008b4
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP                                                           0x3fff808008b5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL                                                          0x3fff808008b5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff808008ca
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP                                                             0x3fff808008cb
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL                                                            0x3fff808008cb
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff808008dc
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP                                                        0x3fff808008dd
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL                                                       0x3fff808008de
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0                                                      0x3fff808008df
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1                                                      0x3fff808008df
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2                                                      0x3fff808008e0
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3                                                      0x3fff808008e0
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4                                                      0x3fff808008e1
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5                                                      0x3fff808008e1
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6                                                      0x3fff808008e2
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7                                                      0x3fff808008e2
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8                                                      0x3fff808008e3
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9                                                      0x3fff808008e3
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10                                                     0x3fff808008e4
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11                                                     0x3fff808008e4
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12                                                     0x3fff808008e5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13                                                     0x3fff808008e5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14                                                     0x3fff808008e6
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15                                                     0x3fff808008e6
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16                                                     0x3fff808008e7
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17                                                     0x3fff808008e7
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18                                                     0x3fff808008e8
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19                                                     0x3fff808008e8
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20                                                     0x3fff808008e9
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21                                                     0x3fff808008e9
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22                                                     0x3fff808008ea
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23                                                     0x3fff808008ea
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24                                                     0x3fff808008eb
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25                                                     0x3fff808008eb
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26                                                     0x3fff808008ec
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27                                                     0x3fff808008ec
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28                                                     0x3fff808008ed
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29                                                     0x3fff808008ed
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30                                                     0x3fff808008ee
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31                                                     0x3fff808008ee
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32                                                     0x3fff808008ef
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33                                                     0x3fff808008ef
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34                                                     0x3fff808008f0
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35                                                     0x3fff808008f0
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36                                                     0x3fff808008f1
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37                                                     0x3fff808008f1
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38                                                     0x3fff808008f2
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39                                                     0x3fff808008f2
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40                                                     0x3fff808008f3
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41                                                     0x3fff808008f3
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42                                                     0x3fff808008f4
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43                                                     0x3fff808008f4
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44                                                     0x3fff808008f5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45                                                     0x3fff808008f5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46                                                     0x3fff808008f6
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47                                                     0x3fff808008f6
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48                                                     0x3fff808008f7
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49                                                     0x3fff808008f7
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50                                                     0x3fff808008f8
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51                                                     0x3fff808008f8
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52                                                     0x3fff808008f9
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53                                                     0x3fff808008f9
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54                                                     0x3fff808008fa
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55                                                     0x3fff808008fa
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56                                                     0x3fff808008fb
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57                                                     0x3fff808008fb
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58                                                     0x3fff808008fc
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59                                                     0x3fff808008fc
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60                                                     0x3fff808008fd
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61                                                     0x3fff808008fd
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62                                                     0x3fff808008fe
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63                                                     0x3fff808008fe
+#define regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+// base address: 0xfffe12103000
+#define regBIF_CFG_DEV0_EPF3_1_VENDOR_ID                                                                0x3fff80800c00
+#define regBIF_CFG_DEV0_EPF3_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_ID                                                                0x3fff80800c00
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_1_COMMAND                                                                  0x3fff80800c01
+#define regBIF_CFG_DEV0_EPF3_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF3_1_STATUS                                                                   0x3fff80800c01
+#define regBIF_CFG_DEV0_EPF3_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF3_1_REVISION_ID                                                              0x3fff80800c02
+#define regBIF_CFG_DEV0_EPF3_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE                                                           0x3fff80800c02
+#define regBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_1_SUB_CLASS                                                                0x3fff80800c02
+#define regBIF_CFG_DEV0_EPF3_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_1_BASE_CLASS                                                               0x3fff80800c02
+#define regBIF_CFG_DEV0_EPF3_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_1_CACHE_LINE                                                               0x3fff80800c03
+#define regBIF_CFG_DEV0_EPF3_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_1_LATENCY                                                                  0x3fff80800c03
+#define regBIF_CFG_DEV0_EPF3_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF3_1_HEADER                                                                   0x3fff80800c03
+#define regBIF_CFG_DEV0_EPF3_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF3_1_BIST                                                                     0x3fff80800c03
+#define regBIF_CFG_DEV0_EPF3_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1                                                              0x3fff80800c04
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2                                                              0x3fff80800c05
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3                                                              0x3fff80800c06
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4                                                              0x3fff80800c07
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5                                                              0x3fff80800c08
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6                                                              0x3fff80800c09
+#define regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR                                                          0x3fff80800c0a
+#define regBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_1_ADAPTER_ID                                                               0x3fff80800c0b
+#define regBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR                                                            0x3fff80800c0c
+#define regBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_CAP_PTR                                                                  0x3fff80800c0d
+#define regBIF_CFG_DEV0_EPF3_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE                                                           0x3fff80800c0f
+#define regBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN                                                            0x3fff80800c0f
+#define regBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_MIN_GRANT                                                                0x3fff80800c0f
+#define regBIF_CFG_DEV0_EPF3_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_1_MAX_LATENCY                                                              0x3fff80800c0f
+#define regBIF_CFG_DEV0_EPF3_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST                                                          0x3fff80800c12
+#define regBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W                                                             0x3fff80800c13
+#define regBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST                                                             0x3fff80800c14
+#define regBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_1_PMI_CAP                                                                  0x3fff80800c14
+#define regBIF_CFG_DEV0_EPF3_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL                                                          0x3fff80800c15
+#define regBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_1_SBRN                                                                     0x3fff80800c18
+#define regBIF_CFG_DEV0_EPF3_1_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF3_1_FLADJ                                                                    0x3fff80800c18
+#define regBIF_CFG_DEV0_EPF3_1_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD                                                             0x3fff80800c18
+#define regBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST                                                            0x3fff80800c19
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_CAP                                                                 0x3fff80800c19
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_CAP                                                               0x3fff80800c1a
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL                                                              0x3fff80800c1b
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS                                                            0x3fff80800c1b
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_LINK_CAP                                                                 0x3fff80800c1c
+#define regBIF_CFG_DEV0_EPF3_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF3_1_LINK_CNTL                                                                0x3fff80800c1d
+#define regBIF_CFG_DEV0_EPF3_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_1_LINK_STATUS                                                              0x3fff80800c1d
+#define regBIF_CFG_DEV0_EPF3_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2                                                              0x3fff80800c22
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2                                                             0x3fff80800c23
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2                                                           0x3fff80800c23
+#define regBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_1_LINK_CAP2                                                                0x3fff80800c24
+#define regBIF_CFG_DEV0_EPF3_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF3_1_LINK_CNTL2                                                               0x3fff80800c25
+#define regBIF_CFG_DEV0_EPF3_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_1_LINK_STATUS2                                                             0x3fff80800c25
+#define regBIF_CFG_DEV0_EPF3_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST                                                             0x3fff80800c28
+#define regBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL                                                             0x3fff80800c28
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO                                                          0x3fff80800c29
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI                                                          0x3fff80800c2a
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA                                                             0x3fff80800c2a
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA                                                         0x3fff80800c2a
+#define regBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MASK                                                                 0x3fff80800c2b
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64                                                          0x3fff80800c2b
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64                                                      0x3fff80800c2b
+#define regBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MASK_64                                                              0x3fff80800c2c
+#define regBIF_CFG_DEV0_EPF3_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_PENDING                                                              0x3fff80800c2c
+#define regBIF_CFG_DEV0_EPF3_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64                                                           0x3fff80800c2d
+#define regBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST                                                            0x3fff80800c30
+#define regBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL                                                            0x3fff80800c30
+#define regBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_MSIX_TABLE                                                               0x3fff80800c31
+#define regBIF_CFG_DEV0_EPF3_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF3_1_MSIX_PBA                                                                 0x3fff80800c32
+#define regBIF_CFG_DEV0_EPF3_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80800c40
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80800c41
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80800c42
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80800c43
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80800c54
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80800c55
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80800c56
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80800c57
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80800c58
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK                                                       0x3fff80800c59
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff80800c5a
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0                                                            0x3fff80800c5b
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1                                                            0x3fff80800c5c
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2                                                            0x3fff80800c5d
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3                                                            0x3fff80800c5e
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80800c62
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80800c63
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80800c64
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80800c65
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80800c80
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP                                                            0x3fff80800c81
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL                                                           0x3fff80800c82
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP                                                            0x3fff80800c83
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL                                                           0x3fff80800c84
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP                                                            0x3fff80800c85
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL                                                           0x3fff80800c86
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP                                                            0x3fff80800c87
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL                                                           0x3fff80800c88
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP                                                            0x3fff80800c89
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL                                                           0x3fff80800c8a
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP                                                            0x3fff80800c8b
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL                                                           0x3fff80800c8c
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80800c90
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80800c91
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80800c92
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80800c93
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80800c94
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP                                                             0x3fff80800c95
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80800c96
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS                                                          0x3fff80800c97
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL                                                            0x3fff80800c97
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80800c98
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80800c98
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80800c98
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80800c98
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80800c99
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80800c99
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80800c99
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80800c99
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff80800ca8
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP                                                             0x3fff80800ca9
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL                                                            0x3fff80800ca9
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff80800cb4
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP                                                           0x3fff80800cb5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL                                                          0x3fff80800cb5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff80800cca
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP                                                             0x3fff80800ccb
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL                                                            0x3fff80800ccb
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff80800cdc
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP                                                        0x3fff80800cdd
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL                                                       0x3fff80800cde
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0                                                      0x3fff80800cdf
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1                                                      0x3fff80800cdf
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2                                                      0x3fff80800ce0
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3                                                      0x3fff80800ce0
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4                                                      0x3fff80800ce1
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5                                                      0x3fff80800ce1
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6                                                      0x3fff80800ce2
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7                                                      0x3fff80800ce2
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8                                                      0x3fff80800ce3
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9                                                      0x3fff80800ce3
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10                                                     0x3fff80800ce4
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11                                                     0x3fff80800ce4
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12                                                     0x3fff80800ce5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13                                                     0x3fff80800ce5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14                                                     0x3fff80800ce6
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15                                                     0x3fff80800ce6
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16                                                     0x3fff80800ce7
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17                                                     0x3fff80800ce7
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18                                                     0x3fff80800ce8
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19                                                     0x3fff80800ce8
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20                                                     0x3fff80800ce9
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21                                                     0x3fff80800ce9
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22                                                     0x3fff80800cea
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23                                                     0x3fff80800cea
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24                                                     0x3fff80800ceb
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25                                                     0x3fff80800ceb
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26                                                     0x3fff80800cec
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27                                                     0x3fff80800cec
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28                                                     0x3fff80800ced
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29                                                     0x3fff80800ced
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30                                                     0x3fff80800cee
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31                                                     0x3fff80800cee
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32                                                     0x3fff80800cef
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33                                                     0x3fff80800cef
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34                                                     0x3fff80800cf0
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35                                                     0x3fff80800cf0
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36                                                     0x3fff80800cf1
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37                                                     0x3fff80800cf1
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38                                                     0x3fff80800cf2
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39                                                     0x3fff80800cf2
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40                                                     0x3fff80800cf3
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41                                                     0x3fff80800cf3
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42                                                     0x3fff80800cf4
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43                                                     0x3fff80800cf4
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44                                                     0x3fff80800cf5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45                                                     0x3fff80800cf5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46                                                     0x3fff80800cf6
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47                                                     0x3fff80800cf6
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48                                                     0x3fff80800cf7
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49                                                     0x3fff80800cf7
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50                                                     0x3fff80800cf8
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51                                                     0x3fff80800cf8
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52                                                     0x3fff80800cf9
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53                                                     0x3fff80800cf9
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54                                                     0x3fff80800cfa
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55                                                     0x3fff80800cfa
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56                                                     0x3fff80800cfb
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57                                                     0x3fff80800cfb
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58                                                     0x3fff80800cfc
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59                                                     0x3fff80800cfc
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60                                                     0x3fff80800cfd
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61                                                     0x3fff80800cfd
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62                                                     0x3fff80800cfe
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63                                                     0x3fff80800cfe
+#define regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+// base address: 0xfffe12104000
+#define regBIF_CFG_DEV0_EPF4_1_VENDOR_ID                                                                0x3fff80801000
+#define regBIF_CFG_DEV0_EPF4_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_ID                                                                0x3fff80801000
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_1_COMMAND                                                                  0x3fff80801001
+#define regBIF_CFG_DEV0_EPF4_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF4_1_STATUS                                                                   0x3fff80801001
+#define regBIF_CFG_DEV0_EPF4_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF4_1_REVISION_ID                                                              0x3fff80801002
+#define regBIF_CFG_DEV0_EPF4_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_PROG_INTERFACE                                                           0x3fff80801002
+#define regBIF_CFG_DEV0_EPF4_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_1_SUB_CLASS                                                                0x3fff80801002
+#define regBIF_CFG_DEV0_EPF4_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_1_BASE_CLASS                                                               0x3fff80801002
+#define regBIF_CFG_DEV0_EPF4_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_1_CACHE_LINE                                                               0x3fff80801003
+#define regBIF_CFG_DEV0_EPF4_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_1_LATENCY                                                                  0x3fff80801003
+#define regBIF_CFG_DEV0_EPF4_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF4_1_HEADER                                                                   0x3fff80801003
+#define regBIF_CFG_DEV0_EPF4_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF4_1_BIST                                                                     0x3fff80801003
+#define regBIF_CFG_DEV0_EPF4_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_1                                                              0x3fff80801004
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_2                                                              0x3fff80801005
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_3                                                              0x3fff80801006
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_4                                                              0x3fff80801007
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_5                                                              0x3fff80801008
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_6                                                              0x3fff80801009
+#define regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_CARDBUS_CIS_PTR                                                          0x3fff8080100a
+#define regBIF_CFG_DEV0_EPF4_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_1_ADAPTER_ID                                                               0x3fff8080100b
+#define regBIF_CFG_DEV0_EPF4_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR                                                            0x3fff8080100c
+#define regBIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_CAP_PTR                                                                  0x3fff8080100d
+#define regBIF_CFG_DEV0_EPF4_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE                                                           0x3fff8080100f
+#define regBIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN                                                            0x3fff8080100f
+#define regBIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_MIN_GRANT                                                                0x3fff8080100f
+#define regBIF_CFG_DEV0_EPF4_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_1_MAX_LATENCY                                                              0x3fff8080100f
+#define regBIF_CFG_DEV0_EPF4_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST                                                          0x3fff80801012
+#define regBIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W                                                             0x3fff80801013
+#define regBIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST                                                             0x3fff80801014
+#define regBIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_1_PMI_CAP                                                                  0x3fff80801014
+#define regBIF_CFG_DEV0_EPF4_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL                                                          0x3fff80801015
+#define regBIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_1_SBRN                                                                     0x3fff80801018
+#define regBIF_CFG_DEV0_EPF4_1_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF4_1_FLADJ                                                                    0x3fff80801018
+#define regBIF_CFG_DEV0_EPF4_1_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF4_1_DBESL_DBESLD                                                             0x3fff80801018
+#define regBIF_CFG_DEV0_EPF4_1_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST                                                            0x3fff80801019
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_CAP                                                                 0x3fff80801019
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_CAP                                                               0x3fff8080101a
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL                                                              0x3fff8080101b
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS                                                            0x3fff8080101b
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_LINK_CAP                                                                 0x3fff8080101c
+#define regBIF_CFG_DEV0_EPF4_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF4_1_LINK_CNTL                                                                0x3fff8080101d
+#define regBIF_CFG_DEV0_EPF4_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_1_LINK_STATUS                                                              0x3fff8080101d
+#define regBIF_CFG_DEV0_EPF4_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_CAP2                                                              0x3fff80801022
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2                                                             0x3fff80801023
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2                                                           0x3fff80801023
+#define regBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_1_LINK_CAP2                                                                0x3fff80801024
+#define regBIF_CFG_DEV0_EPF4_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF4_1_LINK_CNTL2                                                               0x3fff80801025
+#define regBIF_CFG_DEV0_EPF4_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_1_LINK_STATUS2                                                             0x3fff80801025
+#define regBIF_CFG_DEV0_EPF4_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST                                                             0x3fff80801028
+#define regBIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL                                                             0x3fff80801028
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO                                                          0x3fff80801029
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI                                                          0x3fff8080102a
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA                                                             0x3fff8080102a
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA                                                         0x3fff8080102a
+#define regBIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MASK                                                                 0x3fff8080102b
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64                                                          0x3fff8080102b
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_64                                                      0x3fff8080102b
+#define regBIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MASK_64                                                              0x3fff8080102c
+#define regBIF_CFG_DEV0_EPF4_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_PENDING                                                              0x3fff8080102c
+#define regBIF_CFG_DEV0_EPF4_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF4_1_MSI_PENDING_64                                                           0x3fff8080102d
+#define regBIF_CFG_DEV0_EPF4_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST                                                            0x3fff80801030
+#define regBIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL                                                            0x3fff80801030
+#define regBIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_MSIX_TABLE                                                               0x3fff80801031
+#define regBIF_CFG_DEV0_EPF4_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF4_1_MSIX_PBA                                                                 0x3fff80801032
+#define regBIF_CFG_DEV0_EPF4_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80801040
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80801041
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80801042
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80801043
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80801054
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80801055
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80801056
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80801057
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80801058
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK                                                       0x3fff80801059
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff8080105a
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0                                                            0x3fff8080105b
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1                                                            0x3fff8080105c
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2                                                            0x3fff8080105d
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3                                                            0x3fff8080105e
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80801062
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80801063
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80801064
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80801065
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80801080
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP                                                            0x3fff80801081
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL                                                           0x3fff80801082
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP                                                            0x3fff80801083
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL                                                           0x3fff80801084
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP                                                            0x3fff80801085
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL                                                           0x3fff80801086
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP                                                            0x3fff80801087
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL                                                           0x3fff80801088
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP                                                            0x3fff80801089
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL                                                           0x3fff8080108a
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP                                                            0x3fff8080108b
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL                                                           0x3fff8080108c
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80801090
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80801091
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80801092
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80801093
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80801094
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP                                                             0x3fff80801095
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80801096
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS                                                          0x3fff80801097
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL                                                            0x3fff80801097
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80801098
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80801098
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80801098
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80801098
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80801099
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80801099
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80801099
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80801099
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff808010a8
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP                                                             0x3fff808010a9
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL                                                            0x3fff808010a9
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff808010b4
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP                                                           0x3fff808010b5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL                                                          0x3fff808010b5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff808010ca
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP                                                             0x3fff808010cb
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL                                                            0x3fff808010cb
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff808010dc
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP                                                        0x3fff808010dd
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL                                                       0x3fff808010de
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0                                                      0x3fff808010df
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1                                                      0x3fff808010df
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2                                                      0x3fff808010e0
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3                                                      0x3fff808010e0
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4                                                      0x3fff808010e1
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5                                                      0x3fff808010e1
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6                                                      0x3fff808010e2
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7                                                      0x3fff808010e2
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8                                                      0x3fff808010e3
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9                                                      0x3fff808010e3
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10                                                     0x3fff808010e4
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11                                                     0x3fff808010e4
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12                                                     0x3fff808010e5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13                                                     0x3fff808010e5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14                                                     0x3fff808010e6
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15                                                     0x3fff808010e6
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16                                                     0x3fff808010e7
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17                                                     0x3fff808010e7
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18                                                     0x3fff808010e8
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19                                                     0x3fff808010e8
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20                                                     0x3fff808010e9
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21                                                     0x3fff808010e9
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22                                                     0x3fff808010ea
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23                                                     0x3fff808010ea
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24                                                     0x3fff808010eb
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25                                                     0x3fff808010eb
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26                                                     0x3fff808010ec
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27                                                     0x3fff808010ec
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28                                                     0x3fff808010ed
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29                                                     0x3fff808010ed
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30                                                     0x3fff808010ee
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31                                                     0x3fff808010ee
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32                                                     0x3fff808010ef
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33                                                     0x3fff808010ef
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34                                                     0x3fff808010f0
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35                                                     0x3fff808010f0
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36                                                     0x3fff808010f1
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37                                                     0x3fff808010f1
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38                                                     0x3fff808010f2
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39                                                     0x3fff808010f2
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40                                                     0x3fff808010f3
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41                                                     0x3fff808010f3
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42                                                     0x3fff808010f4
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43                                                     0x3fff808010f4
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44                                                     0x3fff808010f5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45                                                     0x3fff808010f5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46                                                     0x3fff808010f6
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47                                                     0x3fff808010f6
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48                                                     0x3fff808010f7
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49                                                     0x3fff808010f7
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50                                                     0x3fff808010f8
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51                                                     0x3fff808010f8
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52                                                     0x3fff808010f9
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53                                                     0x3fff808010f9
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54                                                     0x3fff808010fa
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55                                                     0x3fff808010fa
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56                                                     0x3fff808010fb
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57                                                     0x3fff808010fb
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58                                                     0x3fff808010fc
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59                                                     0x3fff808010fc
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60                                                     0x3fff808010fd
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61                                                     0x3fff808010fd
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62                                                     0x3fff808010fe
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63                                                     0x3fff808010fe
+#define regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+// base address: 0xfffe12105000
+#define regBIF_CFG_DEV0_EPF5_1_VENDOR_ID                                                                0x3fff80801400
+#define regBIF_CFG_DEV0_EPF5_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_ID                                                                0x3fff80801400
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_1_COMMAND                                                                  0x3fff80801401
+#define regBIF_CFG_DEV0_EPF5_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF5_1_STATUS                                                                   0x3fff80801401
+#define regBIF_CFG_DEV0_EPF5_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF5_1_REVISION_ID                                                              0x3fff80801402
+#define regBIF_CFG_DEV0_EPF5_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_PROG_INTERFACE                                                           0x3fff80801402
+#define regBIF_CFG_DEV0_EPF5_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_1_SUB_CLASS                                                                0x3fff80801402
+#define regBIF_CFG_DEV0_EPF5_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_1_BASE_CLASS                                                               0x3fff80801402
+#define regBIF_CFG_DEV0_EPF5_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_1_CACHE_LINE                                                               0x3fff80801403
+#define regBIF_CFG_DEV0_EPF5_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_1_LATENCY                                                                  0x3fff80801403
+#define regBIF_CFG_DEV0_EPF5_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF5_1_HEADER                                                                   0x3fff80801403
+#define regBIF_CFG_DEV0_EPF5_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF5_1_BIST                                                                     0x3fff80801403
+#define regBIF_CFG_DEV0_EPF5_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_1                                                              0x3fff80801404
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_2                                                              0x3fff80801405
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_3                                                              0x3fff80801406
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_4                                                              0x3fff80801407
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_5                                                              0x3fff80801408
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_6                                                              0x3fff80801409
+#define regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_CARDBUS_CIS_PTR                                                          0x3fff8080140a
+#define regBIF_CFG_DEV0_EPF5_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_1_ADAPTER_ID                                                               0x3fff8080140b
+#define regBIF_CFG_DEV0_EPF5_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR                                                            0x3fff8080140c
+#define regBIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_CAP_PTR                                                                  0x3fff8080140d
+#define regBIF_CFG_DEV0_EPF5_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE                                                           0x3fff8080140f
+#define regBIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN                                                            0x3fff8080140f
+#define regBIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_MIN_GRANT                                                                0x3fff8080140f
+#define regBIF_CFG_DEV0_EPF5_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_1_MAX_LATENCY                                                              0x3fff8080140f
+#define regBIF_CFG_DEV0_EPF5_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST                                                          0x3fff80801412
+#define regBIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W                                                             0x3fff80801413
+#define regBIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST                                                             0x3fff80801414
+#define regBIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_1_PMI_CAP                                                                  0x3fff80801414
+#define regBIF_CFG_DEV0_EPF5_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL                                                          0x3fff80801415
+#define regBIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_1_SBRN                                                                     0x3fff80801418
+#define regBIF_CFG_DEV0_EPF5_1_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF5_1_FLADJ                                                                    0x3fff80801418
+#define regBIF_CFG_DEV0_EPF5_1_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF5_1_DBESL_DBESLD                                                             0x3fff80801418
+#define regBIF_CFG_DEV0_EPF5_1_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST                                                            0x3fff80801419
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_CAP                                                                 0x3fff80801419
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_CAP                                                               0x3fff8080141a
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL                                                              0x3fff8080141b
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS                                                            0x3fff8080141b
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_LINK_CAP                                                                 0x3fff8080141c
+#define regBIF_CFG_DEV0_EPF5_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF5_1_LINK_CNTL                                                                0x3fff8080141d
+#define regBIF_CFG_DEV0_EPF5_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_1_LINK_STATUS                                                              0x3fff8080141d
+#define regBIF_CFG_DEV0_EPF5_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_CAP2                                                              0x3fff80801422
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2                                                             0x3fff80801423
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2                                                           0x3fff80801423
+#define regBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_1_LINK_CAP2                                                                0x3fff80801424
+#define regBIF_CFG_DEV0_EPF5_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF5_1_LINK_CNTL2                                                               0x3fff80801425
+#define regBIF_CFG_DEV0_EPF5_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_1_LINK_STATUS2                                                             0x3fff80801425
+#define regBIF_CFG_DEV0_EPF5_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST                                                             0x3fff80801428
+#define regBIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL                                                             0x3fff80801428
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO                                                          0x3fff80801429
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI                                                          0x3fff8080142a
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA                                                             0x3fff8080142a
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA                                                         0x3fff8080142a
+#define regBIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MASK                                                                 0x3fff8080142b
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64                                                          0x3fff8080142b
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_64                                                      0x3fff8080142b
+#define regBIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MASK_64                                                              0x3fff8080142c
+#define regBIF_CFG_DEV0_EPF5_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_PENDING                                                              0x3fff8080142c
+#define regBIF_CFG_DEV0_EPF5_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF5_1_MSI_PENDING_64                                                           0x3fff8080142d
+#define regBIF_CFG_DEV0_EPF5_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST                                                            0x3fff80801430
+#define regBIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL                                                            0x3fff80801430
+#define regBIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_MSIX_TABLE                                                               0x3fff80801431
+#define regBIF_CFG_DEV0_EPF5_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF5_1_MSIX_PBA                                                                 0x3fff80801432
+#define regBIF_CFG_DEV0_EPF5_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80801440
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80801441
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80801442
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80801443
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80801454
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80801455
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80801456
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80801457
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80801458
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK                                                       0x3fff80801459
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff8080145a
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0                                                            0x3fff8080145b
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1                                                            0x3fff8080145c
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2                                                            0x3fff8080145d
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3                                                            0x3fff8080145e
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80801462
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80801463
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80801464
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80801465
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80801480
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP                                                            0x3fff80801481
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL                                                           0x3fff80801482
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP                                                            0x3fff80801483
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL                                                           0x3fff80801484
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP                                                            0x3fff80801485
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL                                                           0x3fff80801486
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP                                                            0x3fff80801487
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL                                                           0x3fff80801488
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP                                                            0x3fff80801489
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL                                                           0x3fff8080148a
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP                                                            0x3fff8080148b
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL                                                           0x3fff8080148c
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80801490
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80801491
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80801492
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80801493
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80801494
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP                                                             0x3fff80801495
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80801496
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS                                                          0x3fff80801497
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL                                                            0x3fff80801497
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80801498
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80801498
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80801498
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80801498
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80801499
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80801499
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80801499
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80801499
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff808014a8
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP                                                             0x3fff808014a9
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL                                                            0x3fff808014a9
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff808014b4
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP                                                           0x3fff808014b5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL                                                          0x3fff808014b5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff808014ca
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP                                                             0x3fff808014cb
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL                                                            0x3fff808014cb
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff808014dc
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP                                                        0x3fff808014dd
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL                                                       0x3fff808014de
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0                                                      0x3fff808014df
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1                                                      0x3fff808014df
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2                                                      0x3fff808014e0
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3                                                      0x3fff808014e0
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4                                                      0x3fff808014e1
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5                                                      0x3fff808014e1
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6                                                      0x3fff808014e2
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7                                                      0x3fff808014e2
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8                                                      0x3fff808014e3
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9                                                      0x3fff808014e3
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10                                                     0x3fff808014e4
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11                                                     0x3fff808014e4
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12                                                     0x3fff808014e5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13                                                     0x3fff808014e5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14                                                     0x3fff808014e6
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15                                                     0x3fff808014e6
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16                                                     0x3fff808014e7
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17                                                     0x3fff808014e7
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18                                                     0x3fff808014e8
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19                                                     0x3fff808014e8
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20                                                     0x3fff808014e9
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21                                                     0x3fff808014e9
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22                                                     0x3fff808014ea
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23                                                     0x3fff808014ea
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24                                                     0x3fff808014eb
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25                                                     0x3fff808014eb
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26                                                     0x3fff808014ec
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27                                                     0x3fff808014ec
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28                                                     0x3fff808014ed
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29                                                     0x3fff808014ed
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30                                                     0x3fff808014ee
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31                                                     0x3fff808014ee
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32                                                     0x3fff808014ef
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33                                                     0x3fff808014ef
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34                                                     0x3fff808014f0
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35                                                     0x3fff808014f0
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36                                                     0x3fff808014f1
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37                                                     0x3fff808014f1
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38                                                     0x3fff808014f2
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39                                                     0x3fff808014f2
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40                                                     0x3fff808014f3
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41                                                     0x3fff808014f3
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42                                                     0x3fff808014f4
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43                                                     0x3fff808014f4
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44                                                     0x3fff808014f5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45                                                     0x3fff808014f5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46                                                     0x3fff808014f6
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47                                                     0x3fff808014f6
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48                                                     0x3fff808014f7
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49                                                     0x3fff808014f7
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50                                                     0x3fff808014f8
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51                                                     0x3fff808014f8
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52                                                     0x3fff808014f9
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53                                                     0x3fff808014f9
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54                                                     0x3fff808014fa
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55                                                     0x3fff808014fa
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56                                                     0x3fff808014fb
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57                                                     0x3fff808014fb
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58                                                     0x3fff808014fc
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59                                                     0x3fff808014fc
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60                                                     0x3fff808014fd
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61                                                     0x3fff808014fd
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62                                                     0x3fff808014fe
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63                                                     0x3fff808014fe
+#define regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+// base address: 0xfffe12106000
+#define regBIF_CFG_DEV0_EPF6_1_VENDOR_ID                                                                0x3fff80801800
+#define regBIF_CFG_DEV0_EPF6_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_ID                                                                0x3fff80801800
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_1_COMMAND                                                                  0x3fff80801801
+#define regBIF_CFG_DEV0_EPF6_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF6_1_STATUS                                                                   0x3fff80801801
+#define regBIF_CFG_DEV0_EPF6_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF6_1_REVISION_ID                                                              0x3fff80801802
+#define regBIF_CFG_DEV0_EPF6_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_PROG_INTERFACE                                                           0x3fff80801802
+#define regBIF_CFG_DEV0_EPF6_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_1_SUB_CLASS                                                                0x3fff80801802
+#define regBIF_CFG_DEV0_EPF6_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_1_BASE_CLASS                                                               0x3fff80801802
+#define regBIF_CFG_DEV0_EPF6_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_1_CACHE_LINE                                                               0x3fff80801803
+#define regBIF_CFG_DEV0_EPF6_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_1_LATENCY                                                                  0x3fff80801803
+#define regBIF_CFG_DEV0_EPF6_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF6_1_HEADER                                                                   0x3fff80801803
+#define regBIF_CFG_DEV0_EPF6_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF6_1_BIST                                                                     0x3fff80801803
+#define regBIF_CFG_DEV0_EPF6_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_1                                                              0x3fff80801804
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_2                                                              0x3fff80801805
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_3                                                              0x3fff80801806
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_4                                                              0x3fff80801807
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_5                                                              0x3fff80801808
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_6                                                              0x3fff80801809
+#define regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_CARDBUS_CIS_PTR                                                          0x3fff8080180a
+#define regBIF_CFG_DEV0_EPF6_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_1_ADAPTER_ID                                                               0x3fff8080180b
+#define regBIF_CFG_DEV0_EPF6_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR                                                            0x3fff8080180c
+#define regBIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_CAP_PTR                                                                  0x3fff8080180d
+#define regBIF_CFG_DEV0_EPF6_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE                                                           0x3fff8080180f
+#define regBIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN                                                            0x3fff8080180f
+#define regBIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_MIN_GRANT                                                                0x3fff8080180f
+#define regBIF_CFG_DEV0_EPF6_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_1_MAX_LATENCY                                                              0x3fff8080180f
+#define regBIF_CFG_DEV0_EPF6_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST                                                          0x3fff80801812
+#define regBIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W                                                             0x3fff80801813
+#define regBIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST                                                             0x3fff80801814
+#define regBIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_1_PMI_CAP                                                                  0x3fff80801814
+#define regBIF_CFG_DEV0_EPF6_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL                                                          0x3fff80801815
+#define regBIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_1_SBRN                                                                     0x3fff80801818
+#define regBIF_CFG_DEV0_EPF6_1_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF6_1_FLADJ                                                                    0x3fff80801818
+#define regBIF_CFG_DEV0_EPF6_1_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF6_1_DBESL_DBESLD                                                             0x3fff80801818
+#define regBIF_CFG_DEV0_EPF6_1_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST                                                            0x3fff80801819
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_CAP                                                                 0x3fff80801819
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_CAP                                                               0x3fff8080181a
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL                                                              0x3fff8080181b
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS                                                            0x3fff8080181b
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_LINK_CAP                                                                 0x3fff8080181c
+#define regBIF_CFG_DEV0_EPF6_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF6_1_LINK_CNTL                                                                0x3fff8080181d
+#define regBIF_CFG_DEV0_EPF6_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_1_LINK_STATUS                                                              0x3fff8080181d
+#define regBIF_CFG_DEV0_EPF6_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_CAP2                                                              0x3fff80801822
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2                                                             0x3fff80801823
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2                                                           0x3fff80801823
+#define regBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_1_LINK_CAP2                                                                0x3fff80801824
+#define regBIF_CFG_DEV0_EPF6_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF6_1_LINK_CNTL2                                                               0x3fff80801825
+#define regBIF_CFG_DEV0_EPF6_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_1_LINK_STATUS2                                                             0x3fff80801825
+#define regBIF_CFG_DEV0_EPF6_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST                                                             0x3fff80801828
+#define regBIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL                                                             0x3fff80801828
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO                                                          0x3fff80801829
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI                                                          0x3fff8080182a
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA                                                             0x3fff8080182a
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA                                                         0x3fff8080182a
+#define regBIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MASK                                                                 0x3fff8080182b
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64                                                          0x3fff8080182b
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_64                                                      0x3fff8080182b
+#define regBIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MASK_64                                                              0x3fff8080182c
+#define regBIF_CFG_DEV0_EPF6_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_PENDING                                                              0x3fff8080182c
+#define regBIF_CFG_DEV0_EPF6_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF6_1_MSI_PENDING_64                                                           0x3fff8080182d
+#define regBIF_CFG_DEV0_EPF6_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST                                                            0x3fff80801830
+#define regBIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL                                                            0x3fff80801830
+#define regBIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_MSIX_TABLE                                                               0x3fff80801831
+#define regBIF_CFG_DEV0_EPF6_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF6_1_MSIX_PBA                                                                 0x3fff80801832
+#define regBIF_CFG_DEV0_EPF6_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80801840
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80801841
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80801842
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80801843
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80801854
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80801855
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80801856
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80801857
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80801858
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK                                                       0x3fff80801859
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff8080185a
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0                                                            0x3fff8080185b
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1                                                            0x3fff8080185c
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2                                                            0x3fff8080185d
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3                                                            0x3fff8080185e
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80801862
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80801863
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80801864
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80801865
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80801880
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP                                                            0x3fff80801881
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL                                                           0x3fff80801882
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP                                                            0x3fff80801883
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL                                                           0x3fff80801884
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP                                                            0x3fff80801885
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL                                                           0x3fff80801886
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP                                                            0x3fff80801887
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL                                                           0x3fff80801888
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP                                                            0x3fff80801889
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL                                                           0x3fff8080188a
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP                                                            0x3fff8080188b
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL                                                           0x3fff8080188c
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80801890
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80801891
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80801892
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80801893
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80801894
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP                                                             0x3fff80801895
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80801896
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS                                                          0x3fff80801897
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL                                                            0x3fff80801897
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80801898
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80801898
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80801898
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80801898
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80801899
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80801899
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80801899
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80801899
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff808018a8
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP                                                             0x3fff808018a9
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL                                                            0x3fff808018a9
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff808018b4
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP                                                           0x3fff808018b5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL                                                          0x3fff808018b5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff808018ca
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP                                                             0x3fff808018cb
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL                                                            0x3fff808018cb
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff808018dc
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP                                                        0x3fff808018dd
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL                                                       0x3fff808018de
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0                                                      0x3fff808018df
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1                                                      0x3fff808018df
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2                                                      0x3fff808018e0
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3                                                      0x3fff808018e0
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4                                                      0x3fff808018e1
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5                                                      0x3fff808018e1
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6                                                      0x3fff808018e2
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7                                                      0x3fff808018e2
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8                                                      0x3fff808018e3
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9                                                      0x3fff808018e3
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10                                                     0x3fff808018e4
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11                                                     0x3fff808018e4
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12                                                     0x3fff808018e5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13                                                     0x3fff808018e5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14                                                     0x3fff808018e6
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15                                                     0x3fff808018e6
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16                                                     0x3fff808018e7
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17                                                     0x3fff808018e7
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18                                                     0x3fff808018e8
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19                                                     0x3fff808018e8
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20                                                     0x3fff808018e9
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21                                                     0x3fff808018e9
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22                                                     0x3fff808018ea
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23                                                     0x3fff808018ea
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24                                                     0x3fff808018eb
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25                                                     0x3fff808018eb
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26                                                     0x3fff808018ec
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27                                                     0x3fff808018ec
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28                                                     0x3fff808018ed
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29                                                     0x3fff808018ed
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30                                                     0x3fff808018ee
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31                                                     0x3fff808018ee
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32                                                     0x3fff808018ef
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33                                                     0x3fff808018ef
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34                                                     0x3fff808018f0
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35                                                     0x3fff808018f0
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36                                                     0x3fff808018f1
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37                                                     0x3fff808018f1
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38                                                     0x3fff808018f2
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39                                                     0x3fff808018f2
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40                                                     0x3fff808018f3
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41                                                     0x3fff808018f3
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42                                                     0x3fff808018f4
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43                                                     0x3fff808018f4
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44                                                     0x3fff808018f5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45                                                     0x3fff808018f5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46                                                     0x3fff808018f6
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47                                                     0x3fff808018f6
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48                                                     0x3fff808018f7
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49                                                     0x3fff808018f7
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50                                                     0x3fff808018f8
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51                                                     0x3fff808018f8
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52                                                     0x3fff808018f9
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53                                                     0x3fff808018f9
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54                                                     0x3fff808018fa
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55                                                     0x3fff808018fa
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56                                                     0x3fff808018fb
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57                                                     0x3fff808018fb
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58                                                     0x3fff808018fc
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59                                                     0x3fff808018fc
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60                                                     0x3fff808018fd
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61                                                     0x3fff808018fd
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62                                                     0x3fff808018fe
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63                                                     0x3fff808018fe
+#define regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp
+// base address: 0xfffe12107000
+#define regBIF_CFG_DEV0_EPF7_1_VENDOR_ID                                                                0x3fff80801c00
+#define regBIF_CFG_DEV0_EPF7_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_ID                                                                0x3fff80801c00
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_1_COMMAND                                                                  0x3fff80801c01
+#define regBIF_CFG_DEV0_EPF7_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF7_1_STATUS                                                                   0x3fff80801c01
+#define regBIF_CFG_DEV0_EPF7_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF7_1_REVISION_ID                                                              0x3fff80801c02
+#define regBIF_CFG_DEV0_EPF7_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_PROG_INTERFACE                                                           0x3fff80801c02
+#define regBIF_CFG_DEV0_EPF7_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_1_SUB_CLASS                                                                0x3fff80801c02
+#define regBIF_CFG_DEV0_EPF7_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_1_BASE_CLASS                                                               0x3fff80801c02
+#define regBIF_CFG_DEV0_EPF7_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_1_CACHE_LINE                                                               0x3fff80801c03
+#define regBIF_CFG_DEV0_EPF7_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_1_LATENCY                                                                  0x3fff80801c03
+#define regBIF_CFG_DEV0_EPF7_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF7_1_HEADER                                                                   0x3fff80801c03
+#define regBIF_CFG_DEV0_EPF7_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF7_1_BIST                                                                     0x3fff80801c03
+#define regBIF_CFG_DEV0_EPF7_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_1                                                              0x3fff80801c04
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_2                                                              0x3fff80801c05
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_3                                                              0x3fff80801c06
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_4                                                              0x3fff80801c07
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_5                                                              0x3fff80801c08
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_6                                                              0x3fff80801c09
+#define regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_CARDBUS_CIS_PTR                                                          0x3fff80801c0a
+#define regBIF_CFG_DEV0_EPF7_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_1_ADAPTER_ID                                                               0x3fff80801c0b
+#define regBIF_CFG_DEV0_EPF7_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR                                                            0x3fff80801c0c
+#define regBIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_CAP_PTR                                                                  0x3fff80801c0d
+#define regBIF_CFG_DEV0_EPF7_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE                                                           0x3fff80801c0f
+#define regBIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN                                                            0x3fff80801c0f
+#define regBIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_MIN_GRANT                                                                0x3fff80801c0f
+#define regBIF_CFG_DEV0_EPF7_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_1_MAX_LATENCY                                                              0x3fff80801c0f
+#define regBIF_CFG_DEV0_EPF7_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST                                                          0x3fff80801c12
+#define regBIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W                                                             0x3fff80801c13
+#define regBIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST                                                             0x3fff80801c14
+#define regBIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_1_PMI_CAP                                                                  0x3fff80801c14
+#define regBIF_CFG_DEV0_EPF7_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL                                                          0x3fff80801c15
+#define regBIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_1_SBRN                                                                     0x3fff80801c18
+#define regBIF_CFG_DEV0_EPF7_1_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF7_1_FLADJ                                                                    0x3fff80801c18
+#define regBIF_CFG_DEV0_EPF7_1_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF7_1_DBESL_DBESLD                                                             0x3fff80801c18
+#define regBIF_CFG_DEV0_EPF7_1_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST                                                            0x3fff80801c19
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_CAP                                                                 0x3fff80801c19
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_CAP                                                               0x3fff80801c1a
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL                                                              0x3fff80801c1b
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS                                                            0x3fff80801c1b
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_LINK_CAP                                                                 0x3fff80801c1c
+#define regBIF_CFG_DEV0_EPF7_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF7_1_LINK_CNTL                                                                0x3fff80801c1d
+#define regBIF_CFG_DEV0_EPF7_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_1_LINK_STATUS                                                              0x3fff80801c1d
+#define regBIF_CFG_DEV0_EPF7_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_CAP2                                                              0x3fff80801c22
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2                                                             0x3fff80801c23
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2                                                           0x3fff80801c23
+#define regBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_1_LINK_CAP2                                                                0x3fff80801c24
+#define regBIF_CFG_DEV0_EPF7_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF7_1_LINK_CNTL2                                                               0x3fff80801c25
+#define regBIF_CFG_DEV0_EPF7_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_1_LINK_STATUS2                                                             0x3fff80801c25
+#define regBIF_CFG_DEV0_EPF7_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST                                                             0x3fff80801c28
+#define regBIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL                                                             0x3fff80801c28
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO                                                          0x3fff80801c29
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI                                                          0x3fff80801c2a
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA                                                             0x3fff80801c2a
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA                                                         0x3fff80801c2a
+#define regBIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MASK                                                                 0x3fff80801c2b
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64                                                          0x3fff80801c2b
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_64                                                      0x3fff80801c2b
+#define regBIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MASK_64                                                              0x3fff80801c2c
+#define regBIF_CFG_DEV0_EPF7_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_PENDING                                                              0x3fff80801c2c
+#define regBIF_CFG_DEV0_EPF7_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF7_1_MSI_PENDING_64                                                           0x3fff80801c2d
+#define regBIF_CFG_DEV0_EPF7_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST                                                            0x3fff80801c30
+#define regBIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL                                                            0x3fff80801c30
+#define regBIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_MSIX_TABLE                                                               0x3fff80801c31
+#define regBIF_CFG_DEV0_EPF7_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF7_1_MSIX_PBA                                                                 0x3fff80801c32
+#define regBIF_CFG_DEV0_EPF7_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80801c40
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80801c41
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80801c42
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80801c43
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80801c54
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80801c55
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80801c56
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80801c57
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80801c58
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK                                                       0x3fff80801c59
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff80801c5a
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0                                                            0x3fff80801c5b
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1                                                            0x3fff80801c5c
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2                                                            0x3fff80801c5d
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3                                                            0x3fff80801c5e
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80801c62
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80801c63
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80801c64
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80801c65
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80801c80
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP                                                            0x3fff80801c81
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL                                                           0x3fff80801c82
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP                                                            0x3fff80801c83
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL                                                           0x3fff80801c84
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP                                                            0x3fff80801c85
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL                                                           0x3fff80801c86
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP                                                            0x3fff80801c87
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL                                                           0x3fff80801c88
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP                                                            0x3fff80801c89
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL                                                           0x3fff80801c8a
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP                                                            0x3fff80801c8b
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL                                                           0x3fff80801c8c
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80801c90
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80801c91
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80801c92
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80801c93
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80801c94
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP                                                             0x3fff80801c95
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80801c96
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS                                                          0x3fff80801c97
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL                                                            0x3fff80801c97
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80801c98
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80801c98
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80801c98
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80801c98
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80801c99
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80801c99
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80801c99
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80801c99
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff80801ca8
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP                                                             0x3fff80801ca9
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL                                                            0x3fff80801ca9
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff80801cb4
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP                                                           0x3fff80801cb5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL                                                          0x3fff80801cb5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff80801cca
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP                                                             0x3fff80801ccb
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL                                                            0x3fff80801ccb
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff80801cdc
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP                                                        0x3fff80801cdd
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL                                                       0x3fff80801cde
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0                                                      0x3fff80801cdf
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1                                                      0x3fff80801cdf
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2                                                      0x3fff80801ce0
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3                                                      0x3fff80801ce0
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4                                                      0x3fff80801ce1
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5                                                      0x3fff80801ce1
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6                                                      0x3fff80801ce2
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7                                                      0x3fff80801ce2
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8                                                      0x3fff80801ce3
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9                                                      0x3fff80801ce3
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10                                                     0x3fff80801ce4
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11                                                     0x3fff80801ce4
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12                                                     0x3fff80801ce5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13                                                     0x3fff80801ce5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14                                                     0x3fff80801ce6
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15                                                     0x3fff80801ce6
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16                                                     0x3fff80801ce7
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17                                                     0x3fff80801ce7
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18                                                     0x3fff80801ce8
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19                                                     0x3fff80801ce8
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20                                                     0x3fff80801ce9
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21                                                     0x3fff80801ce9
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22                                                     0x3fff80801cea
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23                                                     0x3fff80801cea
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24                                                     0x3fff80801ceb
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25                                                     0x3fff80801ceb
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26                                                     0x3fff80801cec
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27                                                     0x3fff80801cec
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28                                                     0x3fff80801ced
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29                                                     0x3fff80801ced
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30                                                     0x3fff80801cee
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31                                                     0x3fff80801cee
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32                                                     0x3fff80801cef
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33                                                     0x3fff80801cef
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34                                                     0x3fff80801cf0
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35                                                     0x3fff80801cf0
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36                                                     0x3fff80801cf1
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37                                                     0x3fff80801cf1
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38                                                     0x3fff80801cf2
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39                                                     0x3fff80801cf2
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40                                                     0x3fff80801cf3
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41                                                     0x3fff80801cf3
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42                                                     0x3fff80801cf4
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43                                                     0x3fff80801cf4
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44                                                     0x3fff80801cf5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45                                                     0x3fff80801cf5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46                                                     0x3fff80801cf6
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47                                                     0x3fff80801cf6
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48                                                     0x3fff80801cf7
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49                                                     0x3fff80801cf7
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50                                                     0x3fff80801cf8
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51                                                     0x3fff80801cf8
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52                                                     0x3fff80801cf9
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53                                                     0x3fff80801cf9
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54                                                     0x3fff80801cfa
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55                                                     0x3fff80801cfa
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56                                                     0x3fff80801cfb
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57                                                     0x3fff80801cfb
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58                                                     0x3fff80801cfc
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59                                                     0x3fff80801cfc
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60                                                     0x3fff80801cfd
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61                                                     0x3fff80801cfd
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62                                                     0x3fff80801cfe
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63                                                     0x3fff80801cfe
+#define regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp
+// base address: 0xfffe12300000
+#define regBIF_CFG_DEV1_EPF0_1_VENDOR_ID                                                                0x3fff80880000
+#define regBIF_CFG_DEV1_EPF0_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_ID                                                                0x3fff80880000
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_1_COMMAND                                                                  0x3fff80880001
+#define regBIF_CFG_DEV1_EPF0_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF0_1_STATUS                                                                   0x3fff80880001
+#define regBIF_CFG_DEV1_EPF0_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_EPF0_1_REVISION_ID                                                              0x3fff80880002
+#define regBIF_CFG_DEV1_EPF0_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_PROG_INTERFACE                                                           0x3fff80880002
+#define regBIF_CFG_DEV1_EPF0_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_SUB_CLASS                                                                0x3fff80880002
+#define regBIF_CFG_DEV1_EPF0_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_1_BASE_CLASS                                                               0x3fff80880002
+#define regBIF_CFG_DEV1_EPF0_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_1_CACHE_LINE                                                               0x3fff80880003
+#define regBIF_CFG_DEV1_EPF0_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LATENCY                                                                  0x3fff80880003
+#define regBIF_CFG_DEV1_EPF0_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF0_1_HEADER                                                                   0x3fff80880003
+#define regBIF_CFG_DEV1_EPF0_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_EPF0_1_BIST                                                                     0x3fff80880003
+#define regBIF_CFG_DEV1_EPF0_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_1                                                              0x3fff80880004
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_2                                                              0x3fff80880005
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_3                                                              0x3fff80880006
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_4                                                              0x3fff80880007
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_5                                                              0x3fff80880008
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_6                                                              0x3fff80880009
+#define regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_CARDBUS_CIS_PTR                                                          0x3fff8088000a
+#define regBIF_CFG_DEV1_EPF0_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_1_ADAPTER_ID                                                               0x3fff8088000b
+#define regBIF_CFG_DEV1_EPF0_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR                                                            0x3fff8088000c
+#define regBIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_CAP_PTR                                                                  0x3fff8088000d
+#define regBIF_CFG_DEV1_EPF0_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE                                                           0x3fff8088000f
+#define regBIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN                                                            0x3fff8088000f
+#define regBIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_MIN_GRANT                                                                0x3fff8088000f
+#define regBIF_CFG_DEV1_EPF0_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_1_MAX_LATENCY                                                              0x3fff8088000f
+#define regBIF_CFG_DEV1_EPF0_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST                                                          0x3fff80880012
+#define regBIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W                                                             0x3fff80880013
+#define regBIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST                                                             0x3fff80880014
+#define regBIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_PMI_CAP                                                                  0x3fff80880014
+#define regBIF_CFG_DEV1_EPF0_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL                                                          0x3fff80880015
+#define regBIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_1_SBRN                                                                     0x3fff80880018
+#define regBIF_CFG_DEV1_EPF0_1_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_EPF0_1_FLADJ                                                                    0x3fff80880018
+#define regBIF_CFG_DEV1_EPF0_1_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_EPF0_1_DBESL_DBESLD                                                             0x3fff80880018
+#define regBIF_CFG_DEV1_EPF0_1_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST                                                            0x3fff80880019
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_CAP                                                                 0x3fff80880019
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_CAP                                                               0x3fff8088001a
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL                                                              0x3fff8088001b
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS                                                            0x3fff8088001b
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CAP                                                                 0x3fff8088001c
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL                                                                0x3fff8088001d
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS                                                              0x3fff8088001d
+#define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_CAP2                                                              0x3fff80880022
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2                                                             0x3fff80880023
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2                                                           0x3fff80880023
+#define regBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CAP2                                                                0x3fff80880024
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL2                                                               0x3fff80880025
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS2                                                             0x3fff80880025
+#define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST                                                             0x3fff80880028
+#define regBIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL                                                             0x3fff80880028
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO                                                          0x3fff80880029
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI                                                          0x3fff8088002a
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA                                                             0x3fff8088002a
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA                                                         0x3fff8088002a
+#define regBIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MASK                                                                 0x3fff8088002b
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64                                                          0x3fff8088002b
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_64                                                      0x3fff8088002b
+#define regBIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MASK_64                                                              0x3fff8088002c
+#define regBIF_CFG_DEV1_EPF0_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_PENDING                                                              0x3fff8088002c
+#define regBIF_CFG_DEV1_EPF0_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF0_1_MSI_PENDING_64                                                           0x3fff8088002d
+#define regBIF_CFG_DEV1_EPF0_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST                                                            0x3fff80880030
+#define regBIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL                                                            0x3fff80880030
+#define regBIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_MSIX_TABLE                                                               0x3fff80880031
+#define regBIF_CFG_DEV1_EPF0_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF0_1_MSIX_PBA                                                                 0x3fff80880032
+#define regBIF_CFG_DEV1_EPF0_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80880040
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80880041
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80880042
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80880043
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST                                                     0x3fff80880044
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1                                                    0x3fff80880045
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2                                                    0x3fff80880046
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL                                                        0x3fff80880047
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS                                                      0x3fff80880047
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP                                                    0x3fff80880048
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL                                                   0x3fff80880049
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS                                                 0x3fff8088004a
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP                                                    0x3fff8088004b
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL                                                   0x3fff8088004c
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS                                                 0x3fff8088004d
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80880054
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80880055
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80880056
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80880057
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80880058
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK                                                       0x3fff80880059
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff8088005a
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0                                                            0x3fff8088005b
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1                                                            0x3fff8088005c
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2                                                            0x3fff8088005d
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3                                                            0x3fff8088005e
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80880062
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80880063
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80880064
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80880065
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80880080
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP                                                            0x3fff80880081
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL                                                           0x3fff80880082
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP                                                            0x3fff80880083
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL                                                           0x3fff80880084
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP                                                            0x3fff80880085
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL                                                           0x3fff80880086
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP                                                            0x3fff80880087
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL                                                           0x3fff80880088
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP                                                            0x3fff80880089
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL                                                           0x3fff8088008a
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP                                                            0x3fff8088008b
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL                                                           0x3fff8088008c
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80880090
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80880091
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80880092
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80880093
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80880094
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP                                                             0x3fff80880095
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80880096
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS                                                          0x3fff80880097
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL                                                            0x3fff80880097
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80880098
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80880098
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80880098
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80880098
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80880099
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80880099
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80880099
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80880099
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST                                              0x3fff8088009c
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3                                                          0x3fff8088009d
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS                                                   0x3fff8088009e
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL                                            0x3fff8088009f
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL                                            0x3fff8088009f
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL                                            0x3fff808800a0
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL                                            0x3fff808800a0
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL                                            0x3fff808800a1
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL                                            0x3fff808800a1
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL                                            0x3fff808800a2
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL                                            0x3fff808800a2
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL                                            0x3fff808800a3
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL                                            0x3fff808800a3
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL                                           0x3fff808800a4
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL                                           0x3fff808800a4
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL                                           0x3fff808800a5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL                                           0x3fff808800a5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL                                           0x3fff808800a6
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL                                           0x3fff808800a6
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff808800a8
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP                                                             0x3fff808800a9
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL                                                            0x3fff808800a9
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff808800b4
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP                                                           0x3fff808800b5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL                                                          0x3fff808800b5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST                                                    0x3fff808800c8
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP                                                             0x3fff808800c9
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff808800ca
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP                                                             0x3fff808800cb
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL                                                            0x3fff808800cb
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff808800dc
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP                                                        0x3fff808800dd
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL                                                       0x3fff808800de
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0                                                      0x3fff808800df
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1                                                      0x3fff808800df
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2                                                      0x3fff808800e0
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3                                                      0x3fff808800e0
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4                                                      0x3fff808800e1
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5                                                      0x3fff808800e1
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6                                                      0x3fff808800e2
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7                                                      0x3fff808800e2
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8                                                      0x3fff808800e3
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9                                                      0x3fff808800e3
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10                                                     0x3fff808800e4
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11                                                     0x3fff808800e4
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12                                                     0x3fff808800e5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13                                                     0x3fff808800e5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14                                                     0x3fff808800e6
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15                                                     0x3fff808800e6
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16                                                     0x3fff808800e7
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17                                                     0x3fff808800e7
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18                                                     0x3fff808800e8
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19                                                     0x3fff808800e8
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20                                                     0x3fff808800e9
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21                                                     0x3fff808800e9
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22                                                     0x3fff808800ea
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23                                                     0x3fff808800ea
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24                                                     0x3fff808800eb
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25                                                     0x3fff808800eb
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26                                                     0x3fff808800ec
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27                                                     0x3fff808800ec
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28                                                     0x3fff808800ed
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29                                                     0x3fff808800ed
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30                                                     0x3fff808800ee
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31                                                     0x3fff808800ee
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32                                                     0x3fff808800ef
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33                                                     0x3fff808800ef
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34                                                     0x3fff808800f0
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35                                                     0x3fff808800f0
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36                                                     0x3fff808800f1
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37                                                     0x3fff808800f1
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38                                                     0x3fff808800f2
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39                                                     0x3fff808800f2
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40                                                     0x3fff808800f3
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41                                                     0x3fff808800f3
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42                                                     0x3fff808800f4
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43                                                     0x3fff808800f4
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44                                                     0x3fff808800f5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45                                                     0x3fff808800f5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46                                                     0x3fff808800f6
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47                                                     0x3fff808800f6
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48                                                     0x3fff808800f7
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49                                                     0x3fff808800f7
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50                                                     0x3fff808800f8
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51                                                     0x3fff808800f8
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52                                                     0x3fff808800f9
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53                                                     0x3fff808800f9
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54                                                     0x3fff808800fa
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55                                                     0x3fff808800fa
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56                                                     0x3fff808800fb
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57                                                     0x3fff808800fb
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58                                                     0x3fff808800fc
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59                                                     0x3fff808800fc
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60                                                     0x3fff808800fd
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61                                                     0x3fff808800fd
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62                                                     0x3fff808800fe
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63                                                     0x3fff808800fe
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST                                                    0x3fff80880100
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP                                                    0x3fff80880101
+#define regBIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS                                                 0x3fff80880102
+#define regBIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST                                               0x3fff80880104
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CAP_16GT                                                            0x3fff80880105
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CAP_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL_16GT                                                           0x3fff80880106
+#define regBIF_CFG_DEV1_EPF0_1_LINK_CNTL_16GT_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT                                                         0x3fff80880107
+#define regBIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT_BASE_IDX                                                5
+#define regBIF_CFG_DEV1_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0x3fff80880108
+#define regBIF_CFG_DEV1_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                               5
+#define regBIF_CFG_DEV1_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0x3fff80880109
+#define regBIF_CFG_DEV1_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV1_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0x3fff8088010a
+#define regBIF_CFG_DEV1_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT                                            0x3fff8088010c
+#define regBIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT                                            0x3fff8088010c
+#define regBIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT                                            0x3fff8088010c
+#define regBIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT                                            0x3fff8088010c
+#define regBIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT                                            0x3fff8088010d
+#define regBIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT                                            0x3fff8088010d
+#define regBIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT                                            0x3fff8088010d
+#define regBIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT                                            0x3fff8088010d
+#define regBIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT                                            0x3fff8088010e
+#define regBIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT                                            0x3fff8088010e
+#define regBIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT                                           0x3fff8088010e
+#define regBIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT                                           0x3fff8088010e
+#define regBIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT                                           0x3fff8088010f
+#define regBIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT                                           0x3fff8088010f
+#define regBIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT                                           0x3fff8088010f
+#define regBIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT                                           0x3fff8088010f
+#define regBIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST                                              0x3fff80880110
+#define regBIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_1_MARGINING_PORT_CAP                                                       0x3fff80880111
+#define regBIF_CFG_DEV1_EPF0_1_MARGINING_PORT_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS                                                    0x3fff80880111
+#define regBIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL                                               0x3fff80880112
+#define regBIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS                                             0x3fff80880112
+#define regBIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL                                               0x3fff80880113
+#define regBIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS                                             0x3fff80880113
+#define regBIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL                                               0x3fff80880114
+#define regBIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS                                             0x3fff80880114
+#define regBIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL                                               0x3fff80880115
+#define regBIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS                                             0x3fff80880115
+#define regBIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL                                               0x3fff80880116
+#define regBIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS                                             0x3fff80880116
+#define regBIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL                                               0x3fff80880117
+#define regBIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS                                             0x3fff80880117
+#define regBIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL                                               0x3fff80880118
+#define regBIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS                                             0x3fff80880118
+#define regBIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL                                               0x3fff80880119
+#define regBIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS                                             0x3fff80880119
+#define regBIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL                                               0x3fff8088011a
+#define regBIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS                                             0x3fff8088011a
+#define regBIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL                                               0x3fff8088011b
+#define regBIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS                                             0x3fff8088011b
+#define regBIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL                                              0x3fff8088011c
+#define regBIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS                                            0x3fff8088011c
+#define regBIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL                                              0x3fff8088011d
+#define regBIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS                                            0x3fff8088011d
+#define regBIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL                                              0x3fff8088011e
+#define regBIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS                                            0x3fff8088011e
+#define regBIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL                                              0x3fff8088011f
+#define regBIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS                                            0x3fff8088011f
+#define regBIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL                                              0x3fff80880120
+#define regBIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS                                            0x3fff80880120
+#define regBIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL                                              0x3fff80880121
+#define regBIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS                                            0x3fff80880121
+#define regBIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                   5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp
+// base address: 0xfffe12301000
+#define regBIF_CFG_DEV1_EPF1_1_VENDOR_ID                                                                0x3fff80880400
+#define regBIF_CFG_DEV1_EPF1_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_ID                                                                0x3fff80880400
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_1_COMMAND                                                                  0x3fff80880401
+#define regBIF_CFG_DEV1_EPF1_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF1_1_STATUS                                                                   0x3fff80880401
+#define regBIF_CFG_DEV1_EPF1_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_EPF1_1_REVISION_ID                                                              0x3fff80880402
+#define regBIF_CFG_DEV1_EPF1_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_PROG_INTERFACE                                                           0x3fff80880402
+#define regBIF_CFG_DEV1_EPF1_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_1_SUB_CLASS                                                                0x3fff80880402
+#define regBIF_CFG_DEV1_EPF1_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_1_BASE_CLASS                                                               0x3fff80880402
+#define regBIF_CFG_DEV1_EPF1_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_1_CACHE_LINE                                                               0x3fff80880403
+#define regBIF_CFG_DEV1_EPF1_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_1_LATENCY                                                                  0x3fff80880403
+#define regBIF_CFG_DEV1_EPF1_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF1_1_HEADER                                                                   0x3fff80880403
+#define regBIF_CFG_DEV1_EPF1_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV1_EPF1_1_BIST                                                                     0x3fff80880403
+#define regBIF_CFG_DEV1_EPF1_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_1                                                              0x3fff80880404
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_2                                                              0x3fff80880405
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_3                                                              0x3fff80880406
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_4                                                              0x3fff80880407
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_5                                                              0x3fff80880408
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_6                                                              0x3fff80880409
+#define regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_CARDBUS_CIS_PTR                                                          0x3fff8088040a
+#define regBIF_CFG_DEV1_EPF1_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_1_ADAPTER_ID                                                               0x3fff8088040b
+#define regBIF_CFG_DEV1_EPF1_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR                                                            0x3fff8088040c
+#define regBIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_CAP_PTR                                                                  0x3fff8088040d
+#define regBIF_CFG_DEV1_EPF1_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE                                                           0x3fff8088040f
+#define regBIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN                                                            0x3fff8088040f
+#define regBIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_MIN_GRANT                                                                0x3fff8088040f
+#define regBIF_CFG_DEV1_EPF1_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_1_MAX_LATENCY                                                              0x3fff8088040f
+#define regBIF_CFG_DEV1_EPF1_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST                                                          0x3fff80880412
+#define regBIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W                                                             0x3fff80880413
+#define regBIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST                                                             0x3fff80880414
+#define regBIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_1_PMI_CAP                                                                  0x3fff80880414
+#define regBIF_CFG_DEV1_EPF1_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL                                                          0x3fff80880415
+#define regBIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_1_SBRN                                                                     0x3fff80880418
+#define regBIF_CFG_DEV1_EPF1_1_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV1_EPF1_1_FLADJ                                                                    0x3fff80880418
+#define regBIF_CFG_DEV1_EPF1_1_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV1_EPF1_1_DBESL_DBESLD                                                             0x3fff80880418
+#define regBIF_CFG_DEV1_EPF1_1_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST                                                            0x3fff80880419
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_CAP                                                                 0x3fff80880419
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_CAP                                                               0x3fff8088041a
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL                                                              0x3fff8088041b
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS                                                            0x3fff8088041b
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_LINK_CAP                                                                 0x3fff8088041c
+#define regBIF_CFG_DEV1_EPF1_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF1_1_LINK_CNTL                                                                0x3fff8088041d
+#define regBIF_CFG_DEV1_EPF1_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_1_LINK_STATUS                                                              0x3fff8088041d
+#define regBIF_CFG_DEV1_EPF1_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_CAP2                                                              0x3fff80880422
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2                                                             0x3fff80880423
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2                                                           0x3fff80880423
+#define regBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_1_LINK_CAP2                                                                0x3fff80880424
+#define regBIF_CFG_DEV1_EPF1_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV1_EPF1_1_LINK_CNTL2                                                               0x3fff80880425
+#define regBIF_CFG_DEV1_EPF1_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_1_LINK_STATUS2                                                             0x3fff80880425
+#define regBIF_CFG_DEV1_EPF1_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST                                                             0x3fff80880428
+#define regBIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL                                                             0x3fff80880428
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO                                                          0x3fff80880429
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI                                                          0x3fff8088042a
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA                                                             0x3fff8088042a
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA                                                         0x3fff8088042a
+#define regBIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MASK                                                                 0x3fff8088042b
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64                                                          0x3fff8088042b
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_64                                                      0x3fff8088042b
+#define regBIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MASK_64                                                              0x3fff8088042c
+#define regBIF_CFG_DEV1_EPF1_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_PENDING                                                              0x3fff8088042c
+#define regBIF_CFG_DEV1_EPF1_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV1_EPF1_1_MSI_PENDING_64                                                           0x3fff8088042d
+#define regBIF_CFG_DEV1_EPF1_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST                                                            0x3fff80880430
+#define regBIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL                                                            0x3fff80880430
+#define regBIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_MSIX_TABLE                                                               0x3fff80880431
+#define regBIF_CFG_DEV1_EPF1_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV1_EPF1_1_MSIX_PBA                                                                 0x3fff80880432
+#define regBIF_CFG_DEV1_EPF1_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80880440
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80880441
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80880442
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80880443
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80880454
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80880455
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80880456
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80880457
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80880458
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK                                                       0x3fff80880459
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff8088045a
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0                                                            0x3fff8088045b
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1                                                            0x3fff8088045c
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2                                                            0x3fff8088045d
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3                                                            0x3fff8088045e
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80880462
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80880463
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80880464
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80880465
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80880480
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP                                                            0x3fff80880481
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL                                                           0x3fff80880482
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP                                                            0x3fff80880483
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL                                                           0x3fff80880484
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP                                                            0x3fff80880485
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL                                                           0x3fff80880486
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP                                                            0x3fff80880487
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL                                                           0x3fff80880488
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP                                                            0x3fff80880489
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL                                                           0x3fff8088048a
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP                                                            0x3fff8088048b
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL                                                           0x3fff8088048c
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80880490
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80880491
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80880492
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80880493
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80880494
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP                                                             0x3fff80880495
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80880496
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS                                                          0x3fff80880497
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL                                                            0x3fff80880497
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80880498
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80880498
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80880498
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80880498
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80880499
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80880499
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80880499
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80880499
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff808804a8
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP                                                             0x3fff808804a9
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL                                                            0x3fff808804a9
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff808804b4
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP                                                           0x3fff808804b5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL                                                          0x3fff808804b5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff808804ca
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP                                                             0x3fff808804cb
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL                                                            0x3fff808804cb
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff808804dc
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP                                                        0x3fff808804dd
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL                                                       0x3fff808804de
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0                                                      0x3fff808804df
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1                                                      0x3fff808804df
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2                                                      0x3fff808804e0
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3                                                      0x3fff808804e0
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4                                                      0x3fff808804e1
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5                                                      0x3fff808804e1
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6                                                      0x3fff808804e2
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7                                                      0x3fff808804e2
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8                                                      0x3fff808804e3
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9                                                      0x3fff808804e3
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10                                                     0x3fff808804e4
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11                                                     0x3fff808804e4
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12                                                     0x3fff808804e5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13                                                     0x3fff808804e5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14                                                     0x3fff808804e6
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15                                                     0x3fff808804e6
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16                                                     0x3fff808804e7
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17                                                     0x3fff808804e7
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18                                                     0x3fff808804e8
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19                                                     0x3fff808804e8
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20                                                     0x3fff808804e9
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21                                                     0x3fff808804e9
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22                                                     0x3fff808804ea
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23                                                     0x3fff808804ea
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24                                                     0x3fff808804eb
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25                                                     0x3fff808804eb
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26                                                     0x3fff808804ec
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27                                                     0x3fff808804ec
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28                                                     0x3fff808804ed
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29                                                     0x3fff808804ed
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30                                                     0x3fff808804ee
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31                                                     0x3fff808804ee
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32                                                     0x3fff808804ef
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33                                                     0x3fff808804ef
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34                                                     0x3fff808804f0
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35                                                     0x3fff808804f0
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36                                                     0x3fff808804f1
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37                                                     0x3fff808804f1
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38                                                     0x3fff808804f2
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39                                                     0x3fff808804f2
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40                                                     0x3fff808804f3
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41                                                     0x3fff808804f3
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42                                                     0x3fff808804f4
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43                                                     0x3fff808804f4
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44                                                     0x3fff808804f5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45                                                     0x3fff808804f5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46                                                     0x3fff808804f6
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47                                                     0x3fff808804f6
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48                                                     0x3fff808804f7
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49                                                     0x3fff808804f7
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50                                                     0x3fff808804f8
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51                                                     0x3fff808804f8
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52                                                     0x3fff808804f9
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53                                                     0x3fff808804f9
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54                                                     0x3fff808804fa
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55                                                     0x3fff808804fa
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56                                                     0x3fff808804fb
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57                                                     0x3fff808804fb
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58                                                     0x3fff808804fc
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59                                                     0x3fff808804fc
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60                                                     0x3fff808804fd
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61                                                     0x3fff808804fd
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62                                                     0x3fff808804fe
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63                                                     0x3fff808804fe
+#define regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp
+// base address: 0xfffe12500000
+#define regBIF_CFG_DEV2_EPF0_1_VENDOR_ID                                                                0x3fff80900000
+#define regBIF_CFG_DEV2_EPF0_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_ID                                                                0x3fff80900000
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_1_COMMAND                                                                  0x3fff80900001
+#define regBIF_CFG_DEV2_EPF0_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF0_1_STATUS                                                                   0x3fff80900001
+#define regBIF_CFG_DEV2_EPF0_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF0_1_REVISION_ID                                                              0x3fff80900002
+#define regBIF_CFG_DEV2_EPF0_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_PROG_INTERFACE                                                           0x3fff80900002
+#define regBIF_CFG_DEV2_EPF0_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_SUB_CLASS                                                                0x3fff80900002
+#define regBIF_CFG_DEV2_EPF0_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_1_BASE_CLASS                                                               0x3fff80900002
+#define regBIF_CFG_DEV2_EPF0_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_1_CACHE_LINE                                                               0x3fff80900003
+#define regBIF_CFG_DEV2_EPF0_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LATENCY                                                                  0x3fff80900003
+#define regBIF_CFG_DEV2_EPF0_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF0_1_HEADER                                                                   0x3fff80900003
+#define regBIF_CFG_DEV2_EPF0_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF0_1_BIST                                                                     0x3fff80900003
+#define regBIF_CFG_DEV2_EPF0_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_1                                                              0x3fff80900004
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_2                                                              0x3fff80900005
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_3                                                              0x3fff80900006
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_4                                                              0x3fff80900007
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_5                                                              0x3fff80900008
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_6                                                              0x3fff80900009
+#define regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_CARDBUS_CIS_PTR                                                          0x3fff8090000a
+#define regBIF_CFG_DEV2_EPF0_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_1_ADAPTER_ID                                                               0x3fff8090000b
+#define regBIF_CFG_DEV2_EPF0_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_1_ROM_BASE_ADDR                                                            0x3fff8090000c
+#define regBIF_CFG_DEV2_EPF0_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_CAP_PTR                                                                  0x3fff8090000d
+#define regBIF_CFG_DEV2_EPF0_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF0_1_INTERRUPT_LINE                                                           0x3fff8090000f
+#define regBIF_CFG_DEV2_EPF0_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_INTERRUPT_PIN                                                            0x3fff8090000f
+#define regBIF_CFG_DEV2_EPF0_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_MIN_GRANT                                                                0x3fff8090000f
+#define regBIF_CFG_DEV2_EPF0_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_1_MAX_LATENCY                                                              0x3fff8090000f
+#define regBIF_CFG_DEV2_EPF0_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST                                                          0x3fff80900012
+#define regBIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W                                                             0x3fff80900013
+#define regBIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST                                                             0x3fff80900014
+#define regBIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_PMI_CAP                                                                  0x3fff80900014
+#define regBIF_CFG_DEV2_EPF0_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL                                                          0x3fff80900015
+#define regBIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_1_SBRN                                                                     0x3fff80900018
+#define regBIF_CFG_DEV2_EPF0_1_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF0_1_FLADJ                                                                    0x3fff80900018
+#define regBIF_CFG_DEV2_EPF0_1_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_EPF0_1_DBESL_DBESLD                                                             0x3fff80900018
+#define regBIF_CFG_DEV2_EPF0_1_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST                                                            0x3fff80900019
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_CAP                                                                 0x3fff80900019
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_CAP                                                               0x3fff8090001a
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_CNTL                                                              0x3fff8090001b
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_STATUS                                                            0x3fff8090001b
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CAP                                                                 0x3fff8090001c
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL                                                                0x3fff8090001d
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS                                                              0x3fff8090001d
+#define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_CAP2                                                              0x3fff80900022
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2                                                             0x3fff80900023
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_STATUS2                                                           0x3fff80900023
+#define regBIF_CFG_DEV2_EPF0_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CAP2                                                                0x3fff80900024
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL2                                                               0x3fff80900025
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS2                                                             0x3fff80900025
+#define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST                                                             0x3fff80900028
+#define regBIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL                                                             0x3fff80900028
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_LO                                                          0x3fff80900029
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_HI                                                          0x3fff8090002a
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA                                                             0x3fff8090002a
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA                                                         0x3fff8090002a
+#define regBIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MASK                                                                 0x3fff8090002b
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_64                                                          0x3fff8090002b
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_64                                                      0x3fff8090002b
+#define regBIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MASK_64                                                              0x3fff8090002c
+#define regBIF_CFG_DEV2_EPF0_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_PENDING                                                              0x3fff8090002c
+#define regBIF_CFG_DEV2_EPF0_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF0_1_MSI_PENDING_64                                                           0x3fff8090002d
+#define regBIF_CFG_DEV2_EPF0_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST                                                            0x3fff80900030
+#define regBIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL                                                            0x3fff80900030
+#define regBIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_MSIX_TABLE                                                               0x3fff80900031
+#define regBIF_CFG_DEV2_EPF0_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF0_1_MSIX_PBA                                                                 0x3fff80900032
+#define regBIF_CFG_DEV2_EPF0_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80900040
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80900041
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80900042
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80900043
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST                                                     0x3fff80900044
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1                                                    0x3fff80900045
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2                                                    0x3fff80900046
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL                                                        0x3fff80900047
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_STATUS                                                      0x3fff80900047
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP                                                    0x3fff80900048
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL                                                   0x3fff80900049
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS                                                 0x3fff8090004a
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP                                                    0x3fff8090004b
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL                                                   0x3fff8090004c
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS                                                 0x3fff8090004d
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80900054
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80900055
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80900056
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80900057
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80900058
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK                                                       0x3fff80900059
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff8090005a
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG0                                                            0x3fff8090005b
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG1                                                            0x3fff8090005c
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG2                                                            0x3fff8090005d
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG3                                                            0x3fff8090005e
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80900062
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80900063
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80900064
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80900065
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80900080
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CAP                                                            0x3fff80900081
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL                                                           0x3fff80900082
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CAP                                                            0x3fff80900083
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL                                                           0x3fff80900084
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CAP                                                            0x3fff80900085
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL                                                           0x3fff80900086
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CAP                                                            0x3fff80900087
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL                                                           0x3fff80900088
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CAP                                                            0x3fff80900089
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL                                                           0x3fff8090008a
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CAP                                                            0x3fff8090008b
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL                                                           0x3fff8090008c
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80900090
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80900091
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80900092
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80900093
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80900094
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP                                                             0x3fff80900095
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80900096
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS                                                          0x3fff80900097
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_CNTL                                                            0x3fff80900097
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80900098
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80900098
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80900098
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80900098
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80900099
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80900099
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80900099
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80900099
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST                                              0x3fff8090009c
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3                                                          0x3fff8090009d
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_ERROR_STATUS                                                   0x3fff8090009e
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_ERROR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL                                            0x3fff8090009f
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL                                            0x3fff8090009f
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL                                            0x3fff809000a0
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL                                            0x3fff809000a0
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL                                            0x3fff809000a1
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL                                            0x3fff809000a1
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL                                            0x3fff809000a2
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL                                            0x3fff809000a2
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL                                            0x3fff809000a3
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL                                            0x3fff809000a3
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL                                           0x3fff809000a4
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL                                           0x3fff809000a4
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL                                           0x3fff809000a5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL                                           0x3fff809000a5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL                                           0x3fff809000a6
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL                                           0x3fff809000a6
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff809000a8
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP                                                             0x3fff809000a9
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL                                                            0x3fff809000a9
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff809000b4
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP                                                           0x3fff809000b5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL                                                          0x3fff809000b5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST                                                    0x3fff809000c8
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP                                                             0x3fff809000c9
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff809000ca
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP                                                             0x3fff809000cb
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL                                                            0x3fff809000cb
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff809000dc
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP                                                        0x3fff809000dd
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL                                                       0x3fff809000de
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0                                                      0x3fff809000df
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1                                                      0x3fff809000df
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2                                                      0x3fff809000e0
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3                                                      0x3fff809000e0
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4                                                      0x3fff809000e1
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5                                                      0x3fff809000e1
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6                                                      0x3fff809000e2
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7                                                      0x3fff809000e2
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8                                                      0x3fff809000e3
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9                                                      0x3fff809000e3
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10                                                     0x3fff809000e4
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11                                                     0x3fff809000e4
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12                                                     0x3fff809000e5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13                                                     0x3fff809000e5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14                                                     0x3fff809000e6
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15                                                     0x3fff809000e6
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16                                                     0x3fff809000e7
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17                                                     0x3fff809000e7
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18                                                     0x3fff809000e8
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19                                                     0x3fff809000e8
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20                                                     0x3fff809000e9
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21                                                     0x3fff809000e9
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22                                                     0x3fff809000ea
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23                                                     0x3fff809000ea
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24                                                     0x3fff809000eb
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25                                                     0x3fff809000eb
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26                                                     0x3fff809000ec
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27                                                     0x3fff809000ec
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28                                                     0x3fff809000ed
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29                                                     0x3fff809000ed
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30                                                     0x3fff809000ee
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31                                                     0x3fff809000ee
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32                                                     0x3fff809000ef
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33                                                     0x3fff809000ef
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34                                                     0x3fff809000f0
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35                                                     0x3fff809000f0
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36                                                     0x3fff809000f1
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37                                                     0x3fff809000f1
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38                                                     0x3fff809000f2
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39                                                     0x3fff809000f2
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40                                                     0x3fff809000f3
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41                                                     0x3fff809000f3
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42                                                     0x3fff809000f4
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43                                                     0x3fff809000f4
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44                                                     0x3fff809000f5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45                                                     0x3fff809000f5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46                                                     0x3fff809000f6
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47                                                     0x3fff809000f6
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48                                                     0x3fff809000f7
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49                                                     0x3fff809000f7
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50                                                     0x3fff809000f8
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51                                                     0x3fff809000f8
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52                                                     0x3fff809000f9
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53                                                     0x3fff809000f9
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54                                                     0x3fff809000fa
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55                                                     0x3fff809000fa
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56                                                     0x3fff809000fb
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57                                                     0x3fff809000fb
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58                                                     0x3fff809000fc
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59                                                     0x3fff809000fc
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60                                                     0x3fff809000fd
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61                                                     0x3fff809000fd
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62                                                     0x3fff809000fe
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63                                                     0x3fff809000fe
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST                                                    0x3fff80900100
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP                                                    0x3fff80900101
+#define regBIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS                                                 0x3fff80900102
+#define regBIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST                                               0x3fff80900104
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CAP_16GT                                                            0x3fff80900105
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CAP_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL_16GT                                                           0x3fff80900106
+#define regBIF_CFG_DEV2_EPF0_1_LINK_CNTL_16GT_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT                                                         0x3fff80900107
+#define regBIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0x3fff80900108
+#define regBIF_CFG_DEV2_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                               5
+#define regBIF_CFG_DEV2_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0x3fff80900109
+#define regBIF_CFG_DEV2_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV2_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0x3fff8090010a
+#define regBIF_CFG_DEV2_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT                                            0x3fff8090010c
+#define regBIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT                                            0x3fff8090010c
+#define regBIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT                                            0x3fff8090010c
+#define regBIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT                                            0x3fff8090010c
+#define regBIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT                                            0x3fff8090010d
+#define regBIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT                                            0x3fff8090010d
+#define regBIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT                                            0x3fff8090010d
+#define regBIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT                                            0x3fff8090010d
+#define regBIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT                                            0x3fff8090010e
+#define regBIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT                                            0x3fff8090010e
+#define regBIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT                                           0x3fff8090010e
+#define regBIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT                                           0x3fff8090010e
+#define regBIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT                                           0x3fff8090010f
+#define regBIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT                                           0x3fff8090010f
+#define regBIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT                                           0x3fff8090010f
+#define regBIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT                                           0x3fff8090010f
+#define regBIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST                                              0x3fff80900110
+#define regBIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_1_MARGINING_PORT_CAP                                                       0x3fff80900111
+#define regBIF_CFG_DEV2_EPF0_1_MARGINING_PORT_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS                                                    0x3fff80900111
+#define regBIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL                                               0x3fff80900112
+#define regBIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS                                             0x3fff80900112
+#define regBIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL                                               0x3fff80900113
+#define regBIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS                                             0x3fff80900113
+#define regBIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL                                               0x3fff80900114
+#define regBIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS                                             0x3fff80900114
+#define regBIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL                                               0x3fff80900115
+#define regBIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS                                             0x3fff80900115
+#define regBIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL                                               0x3fff80900116
+#define regBIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS                                             0x3fff80900116
+#define regBIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL                                               0x3fff80900117
+#define regBIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS                                             0x3fff80900117
+#define regBIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL                                               0x3fff80900118
+#define regBIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS                                             0x3fff80900118
+#define regBIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL                                               0x3fff80900119
+#define regBIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS                                             0x3fff80900119
+#define regBIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL                                               0x3fff8090011a
+#define regBIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS                                             0x3fff8090011a
+#define regBIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL                                               0x3fff8090011b
+#define regBIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS                                             0x3fff8090011b
+#define regBIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL                                              0x3fff8090011c
+#define regBIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS                                            0x3fff8090011c
+#define regBIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL                                              0x3fff8090011d
+#define regBIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS                                            0x3fff8090011d
+#define regBIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL                                              0x3fff8090011e
+#define regBIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS                                            0x3fff8090011e
+#define regBIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL                                              0x3fff8090011f
+#define regBIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS                                            0x3fff8090011f
+#define regBIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL                                              0x3fff80900120
+#define regBIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS                                            0x3fff80900120
+#define regBIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL                                              0x3fff80900121
+#define regBIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS                                            0x3fff80900121
+#define regBIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                   5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf1_bifcfgdecp
+// base address: 0xfffe12501000
+#define regBIF_CFG_DEV2_EPF1_1_VENDOR_ID                                                                0x3fff80900400
+#define regBIF_CFG_DEV2_EPF1_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_ID                                                                0x3fff80900400
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_1_COMMAND                                                                  0x3fff80900401
+#define regBIF_CFG_DEV2_EPF1_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF1_1_STATUS                                                                   0x3fff80900401
+#define regBIF_CFG_DEV2_EPF1_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF1_1_REVISION_ID                                                              0x3fff80900402
+#define regBIF_CFG_DEV2_EPF1_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_PROG_INTERFACE                                                           0x3fff80900402
+#define regBIF_CFG_DEV2_EPF1_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_1_SUB_CLASS                                                                0x3fff80900402
+#define regBIF_CFG_DEV2_EPF1_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_1_BASE_CLASS                                                               0x3fff80900402
+#define regBIF_CFG_DEV2_EPF1_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_1_CACHE_LINE                                                               0x3fff80900403
+#define regBIF_CFG_DEV2_EPF1_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_1_LATENCY                                                                  0x3fff80900403
+#define regBIF_CFG_DEV2_EPF1_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF1_1_HEADER                                                                   0x3fff80900403
+#define regBIF_CFG_DEV2_EPF1_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF1_1_BIST                                                                     0x3fff80900403
+#define regBIF_CFG_DEV2_EPF1_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_1                                                              0x3fff80900404
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_2                                                              0x3fff80900405
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_3                                                              0x3fff80900406
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_4                                                              0x3fff80900407
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_5                                                              0x3fff80900408
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_6                                                              0x3fff80900409
+#define regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_CARDBUS_CIS_PTR                                                          0x3fff8090040a
+#define regBIF_CFG_DEV2_EPF1_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_1_ADAPTER_ID                                                               0x3fff8090040b
+#define regBIF_CFG_DEV2_EPF1_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_1_ROM_BASE_ADDR                                                            0x3fff8090040c
+#define regBIF_CFG_DEV2_EPF1_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_CAP_PTR                                                                  0x3fff8090040d
+#define regBIF_CFG_DEV2_EPF1_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF1_1_INTERRUPT_LINE                                                           0x3fff8090040f
+#define regBIF_CFG_DEV2_EPF1_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_1_INTERRUPT_PIN                                                            0x3fff8090040f
+#define regBIF_CFG_DEV2_EPF1_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_MIN_GRANT                                                                0x3fff8090040f
+#define regBIF_CFG_DEV2_EPF1_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_1_MAX_LATENCY                                                              0x3fff8090040f
+#define regBIF_CFG_DEV2_EPF1_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST                                                          0x3fff80900412
+#define regBIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W                                                             0x3fff80900413
+#define regBIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST                                                             0x3fff80900414
+#define regBIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_1_PMI_CAP                                                                  0x3fff80900414
+#define regBIF_CFG_DEV2_EPF1_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL                                                          0x3fff80900415
+#define regBIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_1_SBRN                                                                     0x3fff80900418
+#define regBIF_CFG_DEV2_EPF1_1_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF1_1_FLADJ                                                                    0x3fff80900418
+#define regBIF_CFG_DEV2_EPF1_1_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_EPF1_1_DBESL_DBESLD                                                             0x3fff80900418
+#define regBIF_CFG_DEV2_EPF1_1_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST                                                            0x3fff80900419
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_CAP                                                                 0x3fff80900419
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_CAP                                                               0x3fff8090041a
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_CNTL                                                              0x3fff8090041b
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_STATUS                                                            0x3fff8090041b
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_LINK_CAP                                                                 0x3fff8090041c
+#define regBIF_CFG_DEV2_EPF1_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF1_1_LINK_CNTL                                                                0x3fff8090041d
+#define regBIF_CFG_DEV2_EPF1_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_1_LINK_STATUS                                                              0x3fff8090041d
+#define regBIF_CFG_DEV2_EPF1_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_CAP2                                                              0x3fff80900422
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2                                                             0x3fff80900423
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_STATUS2                                                           0x3fff80900423
+#define regBIF_CFG_DEV2_EPF1_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_1_LINK_CAP2                                                                0x3fff80900424
+#define regBIF_CFG_DEV2_EPF1_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF1_1_LINK_CNTL2                                                               0x3fff80900425
+#define regBIF_CFG_DEV2_EPF1_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_1_LINK_STATUS2                                                             0x3fff80900425
+#define regBIF_CFG_DEV2_EPF1_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST                                                             0x3fff80900428
+#define regBIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL                                                             0x3fff80900428
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_LO                                                          0x3fff80900429
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_HI                                                          0x3fff8090042a
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA                                                             0x3fff8090042a
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA                                                         0x3fff8090042a
+#define regBIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MASK                                                                 0x3fff8090042b
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_64                                                          0x3fff8090042b
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_64                                                      0x3fff8090042b
+#define regBIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MASK_64                                                              0x3fff8090042c
+#define regBIF_CFG_DEV2_EPF1_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_PENDING                                                              0x3fff8090042c
+#define regBIF_CFG_DEV2_EPF1_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF1_1_MSI_PENDING_64                                                           0x3fff8090042d
+#define regBIF_CFG_DEV2_EPF1_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST                                                            0x3fff80900430
+#define regBIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL                                                            0x3fff80900430
+#define regBIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_MSIX_TABLE                                                               0x3fff80900431
+#define regBIF_CFG_DEV2_EPF1_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF1_1_MSIX_PBA                                                                 0x3fff80900432
+#define regBIF_CFG_DEV2_EPF1_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80900440
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80900441
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80900442
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80900443
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80900454
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80900455
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80900456
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80900457
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80900458
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK                                                       0x3fff80900459
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff8090045a
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG0                                                            0x3fff8090045b
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG1                                                            0x3fff8090045c
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG2                                                            0x3fff8090045d
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG3                                                            0x3fff8090045e
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80900462
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80900463
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80900464
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80900465
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80900480
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CAP                                                            0x3fff80900481
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL                                                           0x3fff80900482
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CAP                                                            0x3fff80900483
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL                                                           0x3fff80900484
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CAP                                                            0x3fff80900485
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL                                                           0x3fff80900486
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CAP                                                            0x3fff80900487
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL                                                           0x3fff80900488
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CAP                                                            0x3fff80900489
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL                                                           0x3fff8090048a
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CAP                                                            0x3fff8090048b
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL                                                           0x3fff8090048c
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80900490
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80900491
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80900492
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80900493
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80900494
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP                                                             0x3fff80900495
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80900496
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS                                                          0x3fff80900497
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_CNTL                                                            0x3fff80900497
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80900498
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80900498
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80900498
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80900498
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80900499
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80900499
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80900499
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80900499
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff809004a8
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP                                                             0x3fff809004a9
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL                                                            0x3fff809004a9
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff809004b4
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP                                                           0x3fff809004b5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL                                                          0x3fff809004b5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff809004ca
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP                                                             0x3fff809004cb
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL                                                            0x3fff809004cb
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff809004dc
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP                                                        0x3fff809004dd
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL                                                       0x3fff809004de
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0                                                      0x3fff809004df
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1                                                      0x3fff809004df
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2                                                      0x3fff809004e0
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3                                                      0x3fff809004e0
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4                                                      0x3fff809004e1
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5                                                      0x3fff809004e1
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6                                                      0x3fff809004e2
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7                                                      0x3fff809004e2
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8                                                      0x3fff809004e3
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9                                                      0x3fff809004e3
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10                                                     0x3fff809004e4
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11                                                     0x3fff809004e4
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12                                                     0x3fff809004e5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13                                                     0x3fff809004e5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14                                                     0x3fff809004e6
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15                                                     0x3fff809004e6
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16                                                     0x3fff809004e7
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17                                                     0x3fff809004e7
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18                                                     0x3fff809004e8
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19                                                     0x3fff809004e8
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20                                                     0x3fff809004e9
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21                                                     0x3fff809004e9
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22                                                     0x3fff809004ea
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23                                                     0x3fff809004ea
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24                                                     0x3fff809004eb
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25                                                     0x3fff809004eb
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26                                                     0x3fff809004ec
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27                                                     0x3fff809004ec
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28                                                     0x3fff809004ed
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29                                                     0x3fff809004ed
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30                                                     0x3fff809004ee
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31                                                     0x3fff809004ee
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32                                                     0x3fff809004ef
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33                                                     0x3fff809004ef
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34                                                     0x3fff809004f0
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35                                                     0x3fff809004f0
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36                                                     0x3fff809004f1
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37                                                     0x3fff809004f1
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38                                                     0x3fff809004f2
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39                                                     0x3fff809004f2
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40                                                     0x3fff809004f3
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41                                                     0x3fff809004f3
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42                                                     0x3fff809004f4
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43                                                     0x3fff809004f4
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44                                                     0x3fff809004f5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45                                                     0x3fff809004f5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46                                                     0x3fff809004f6
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47                                                     0x3fff809004f6
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48                                                     0x3fff809004f7
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49                                                     0x3fff809004f7
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50                                                     0x3fff809004f8
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51                                                     0x3fff809004f8
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52                                                     0x3fff809004f9
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53                                                     0x3fff809004f9
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54                                                     0x3fff809004fa
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55                                                     0x3fff809004fa
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56                                                     0x3fff809004fb
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57                                                     0x3fff809004fb
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58                                                     0x3fff809004fc
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59                                                     0x3fff809004fc
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60                                                     0x3fff809004fd
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61                                                     0x3fff809004fd
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62                                                     0x3fff809004fe
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63                                                     0x3fff809004fe
+#define regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf2_bifcfgdecp
+// base address: 0xfffe12502000
+#define regBIF_CFG_DEV2_EPF2_1_VENDOR_ID                                                                0x3fff80900800
+#define regBIF_CFG_DEV2_EPF2_1_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_ID                                                                0x3fff80900800
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_1_COMMAND                                                                  0x3fff80900801
+#define regBIF_CFG_DEV2_EPF2_1_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF2_1_STATUS                                                                   0x3fff80900801
+#define regBIF_CFG_DEV2_EPF2_1_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF2_1_REVISION_ID                                                              0x3fff80900802
+#define regBIF_CFG_DEV2_EPF2_1_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_PROG_INTERFACE                                                           0x3fff80900802
+#define regBIF_CFG_DEV2_EPF2_1_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_1_SUB_CLASS                                                                0x3fff80900802
+#define regBIF_CFG_DEV2_EPF2_1_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_1_BASE_CLASS                                                               0x3fff80900802
+#define regBIF_CFG_DEV2_EPF2_1_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_1_CACHE_LINE                                                               0x3fff80900803
+#define regBIF_CFG_DEV2_EPF2_1_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_1_LATENCY                                                                  0x3fff80900803
+#define regBIF_CFG_DEV2_EPF2_1_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF2_1_HEADER                                                                   0x3fff80900803
+#define regBIF_CFG_DEV2_EPF2_1_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV2_EPF2_1_BIST                                                                     0x3fff80900803
+#define regBIF_CFG_DEV2_EPF2_1_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_1                                                              0x3fff80900804
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_2                                                              0x3fff80900805
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_3                                                              0x3fff80900806
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_4                                                              0x3fff80900807
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_5                                                              0x3fff80900808
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_6                                                              0x3fff80900809
+#define regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_CARDBUS_CIS_PTR                                                          0x3fff8090080a
+#define regBIF_CFG_DEV2_EPF2_1_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_1_ADAPTER_ID                                                               0x3fff8090080b
+#define regBIF_CFG_DEV2_EPF2_1_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_1_ROM_BASE_ADDR                                                            0x3fff8090080c
+#define regBIF_CFG_DEV2_EPF2_1_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_CAP_PTR                                                                  0x3fff8090080d
+#define regBIF_CFG_DEV2_EPF2_1_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF2_1_INTERRUPT_LINE                                                           0x3fff8090080f
+#define regBIF_CFG_DEV2_EPF2_1_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_1_INTERRUPT_PIN                                                            0x3fff8090080f
+#define regBIF_CFG_DEV2_EPF2_1_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_MIN_GRANT                                                                0x3fff8090080f
+#define regBIF_CFG_DEV2_EPF2_1_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_1_MAX_LATENCY                                                              0x3fff8090080f
+#define regBIF_CFG_DEV2_EPF2_1_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST                                                          0x3fff80900812
+#define regBIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W                                                             0x3fff80900813
+#define regBIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST                                                             0x3fff80900814
+#define regBIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_1_PMI_CAP                                                                  0x3fff80900814
+#define regBIF_CFG_DEV2_EPF2_1_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL                                                          0x3fff80900815
+#define regBIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_1_SBRN                                                                     0x3fff80900818
+#define regBIF_CFG_DEV2_EPF2_1_SBRN_BASE_IDX                                                            5
+#define regBIF_CFG_DEV2_EPF2_1_FLADJ                                                                    0x3fff80900818
+#define regBIF_CFG_DEV2_EPF2_1_FLADJ_BASE_IDX                                                           5
+#define regBIF_CFG_DEV2_EPF2_1_DBESL_DBESLD                                                             0x3fff80900818
+#define regBIF_CFG_DEV2_EPF2_1_DBESL_DBESLD_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST                                                            0x3fff80900819
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_CAP                                                                 0x3fff80900819
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_CAP                                                               0x3fff8090081a
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_CNTL                                                              0x3fff8090081b
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_STATUS                                                            0x3fff8090081b
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_LINK_CAP                                                                 0x3fff8090081c
+#define regBIF_CFG_DEV2_EPF2_1_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF2_1_LINK_CNTL                                                                0x3fff8090081d
+#define regBIF_CFG_DEV2_EPF2_1_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_1_LINK_STATUS                                                              0x3fff8090081d
+#define regBIF_CFG_DEV2_EPF2_1_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_CAP2                                                              0x3fff80900822
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2                                                             0x3fff80900823
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_STATUS2                                                           0x3fff80900823
+#define regBIF_CFG_DEV2_EPF2_1_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_1_LINK_CAP2                                                                0x3fff80900824
+#define regBIF_CFG_DEV2_EPF2_1_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV2_EPF2_1_LINK_CNTL2                                                               0x3fff80900825
+#define regBIF_CFG_DEV2_EPF2_1_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_1_LINK_STATUS2                                                             0x3fff80900825
+#define regBIF_CFG_DEV2_EPF2_1_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST                                                             0x3fff80900828
+#define regBIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL                                                             0x3fff80900828
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_LO                                                          0x3fff80900829
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_HI                                                          0x3fff8090082a
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA                                                             0x3fff8090082a
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA                                                         0x3fff8090082a
+#define regBIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MASK                                                                 0x3fff8090082b
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_64                                                          0x3fff8090082b
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_64                                                      0x3fff8090082b
+#define regBIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MASK_64                                                              0x3fff8090082c
+#define regBIF_CFG_DEV2_EPF2_1_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_PENDING                                                              0x3fff8090082c
+#define regBIF_CFG_DEV2_EPF2_1_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV2_EPF2_1_MSI_PENDING_64                                                           0x3fff8090082d
+#define regBIF_CFG_DEV2_EPF2_1_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST                                                            0x3fff80900830
+#define regBIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL                                                            0x3fff80900830
+#define regBIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_MSIX_TABLE                                                               0x3fff80900831
+#define regBIF_CFG_DEV2_EPF2_1_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV2_EPF2_1_MSIX_PBA                                                                 0x3fff80900832
+#define regBIF_CFG_DEV2_EPF2_1_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x3fff80900840
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR                                                 0x3fff80900841
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC1                                                    0x3fff80900842
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC2                                                    0x3fff80900843
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x3fff80900854
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS                                                   0x3fff80900855
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK                                                     0x3fff80900856
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY                                                 0x3fff80900857
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS                                                     0x3fff80900858
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK                                                       0x3fff80900859
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL                                                    0x3fff8090085a
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG0                                                            0x3fff8090085b
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG1                                                            0x3fff8090085c
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG2                                                            0x3fff8090085d
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG3                                                            0x3fff8090085e
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG0                                                     0x3fff80900862
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG1                                                     0x3fff80900863
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG2                                                     0x3fff80900864
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG3                                                     0x3fff80900865
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST                                                    0x3fff80900880
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CAP                                                            0x3fff80900881
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL                                                           0x3fff80900882
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CAP                                                            0x3fff80900883
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL                                                           0x3fff80900884
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CAP                                                            0x3fff80900885
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL                                                           0x3fff80900886
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CAP                                                            0x3fff80900887
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL                                                           0x3fff80900888
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CAP                                                            0x3fff80900889
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL                                                           0x3fff8090088a
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CAP                                                            0x3fff8090088b
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL                                                           0x3fff8090088c
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x3fff80900890
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT                                              0x3fff80900891
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA                                                     0x3fff80900892
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_CAP                                                      0x3fff80900893
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST                                                    0x3fff80900894
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP                                                             0x3fff80900895
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_LATENCY_INDICATOR                                               0x3fff80900896
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS                                                          0x3fff80900897
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_CNTL                                                            0x3fff80900897
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x3fff80900898
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x3fff80900898
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x3fff80900898
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x3fff80900898
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x3fff80900899
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x3fff80900899
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x3fff80900899
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x3fff80900899
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST                                                    0x3fff809008a8
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP                                                             0x3fff809008a9
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL                                                            0x3fff809008a9
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST                                                  0x3fff809008b4
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP                                                           0x3fff809008b5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL                                                          0x3fff809008b5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST                                                    0x3fff809008ca
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP                                                             0x3fff809008cb
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL                                                            0x3fff809008cb
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST                                               0x3fff809008dc
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP                                                        0x3fff809008dd
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL                                                       0x3fff809008de
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0                                                      0x3fff809008df
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1                                                      0x3fff809008df
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2                                                      0x3fff809008e0
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3                                                      0x3fff809008e0
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4                                                      0x3fff809008e1
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5                                                      0x3fff809008e1
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6                                                      0x3fff809008e2
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7                                                      0x3fff809008e2
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8                                                      0x3fff809008e3
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9                                                      0x3fff809008e3
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9_BASE_IDX                                             5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10                                                     0x3fff809008e4
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11                                                     0x3fff809008e4
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12                                                     0x3fff809008e5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13                                                     0x3fff809008e5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14                                                     0x3fff809008e6
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15                                                     0x3fff809008e6
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16                                                     0x3fff809008e7
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17                                                     0x3fff809008e7
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18                                                     0x3fff809008e8
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19                                                     0x3fff809008e8
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20                                                     0x3fff809008e9
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21                                                     0x3fff809008e9
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22                                                     0x3fff809008ea
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23                                                     0x3fff809008ea
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24                                                     0x3fff809008eb
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25                                                     0x3fff809008eb
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26                                                     0x3fff809008ec
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27                                                     0x3fff809008ec
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28                                                     0x3fff809008ed
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29                                                     0x3fff809008ed
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30                                                     0x3fff809008ee
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31                                                     0x3fff809008ee
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32                                                     0x3fff809008ef
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33                                                     0x3fff809008ef
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34                                                     0x3fff809008f0
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35                                                     0x3fff809008f0
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36                                                     0x3fff809008f1
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37                                                     0x3fff809008f1
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38                                                     0x3fff809008f2
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39                                                     0x3fff809008f2
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40                                                     0x3fff809008f3
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41                                                     0x3fff809008f3
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42                                                     0x3fff809008f4
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43                                                     0x3fff809008f4
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44                                                     0x3fff809008f5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45                                                     0x3fff809008f5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46                                                     0x3fff809008f6
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47                                                     0x3fff809008f6
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48                                                     0x3fff809008f7
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49                                                     0x3fff809008f7
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50                                                     0x3fff809008f8
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51                                                     0x3fff809008f8
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52                                                     0x3fff809008f9
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53                                                     0x3fff809008f9
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54                                                     0x3fff809008fa
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55                                                     0x3fff809008fa
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56                                                     0x3fff809008fb
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57                                                     0x3fff809008fb
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58                                                     0x3fff809008fc
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59                                                     0x3fff809008fc
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60                                                     0x3fff809008fd
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61                                                     0x3fff809008fd
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62                                                     0x3fff809008fe
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62_BASE_IDX                                            5
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63                                                     0x3fff809008fe
+#define regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63_BASE_IDX                                            5
+
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h
new file mode 100644
index 000000000000..e27fdc0c643c
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h
@@ -0,0 +1,152495 @@
+
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbio_7_2_0_SH_MASK_HEADER
+#define _nbio_7_2_0_SH_MASK_HEADER
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+//BIF_CFG_DEV0_RC_VENDOR_ID
+#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID_MASK                                                             0xFFFFL
+//BIF_CFG_DEV0_RC_DEVICE_ID
+#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID_MASK                                                             0xFFFFL
+//BIF_CFG_DEV0_RC_COMMAND
+#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN__SHIFT                                                              0x1
+#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN__SHIFT                                                         0x2
+#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                      0x3
+#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN__SHIFT                                                          0x5
+#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                 0x6
+#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN__SHIFT                                                               0x8
+#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN__SHIFT                                                           0x9
+#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT                                                               0xa
+#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN_MASK                                                                 0x0001L
+#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN_MASK                                                                0x0002L
+#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN_MASK                                                           0x0004L
+#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN_MASK                                                        0x0008L
+#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN_MASK                                                            0x0020L
+#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                   0x0040L
+#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING_MASK                                                             0x0080L
+#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN_MASK                                                                 0x0100L
+#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN_MASK                                                             0x0200L
+#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS_MASK                                                                 0x0400L
+//BIF_CFG_DEV0_RC_STATUS
+#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS__SHIFT                                                             0x3
+#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST__SHIFT                                                               0x4
+#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP__SHIFT                                                             0x5
+#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                               0x8
+#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                    0xb
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                  0xd
+#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                  0xe
+#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS_MASK                                                               0x0008L
+#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST_MASK                                                                 0x0010L
+#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP_MASK                                                               0x0020L
+#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING_MASK                                                            0x0600L
+#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT_MASK                                                      0x0800L
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT_MASK                                                    0x1000L
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT_MASK                                                    0x2000L
+#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                    0x4000L
+#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED_MASK                                                    0x8000L
+//BIF_CFG_DEV0_RC_REVISION_ID
+#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID_MASK                                                        0x0FL
+#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID_MASK                                                        0xF0L
+//BIF_CFG_DEV0_RC_PROG_INTERFACE
+#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE_MASK                                                   0xFFL
+//BIF_CFG_DEV0_RC_SUB_CLASS
+#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS_MASK                                                             0xFFL
+//BIF_CFG_DEV0_RC_BASE_CLASS
+#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV0_RC_CACHE_LINE
+#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                      0xFFL
+//BIF_CFG_DEV0_RC_LATENCY
+#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER_MASK                                                           0xFFL
+//BIF_CFG_DEV0_RC_HEADER
+#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE__SHIFT                                                            0x7
+#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE_MASK                                                              0x7FL
+#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE_MASK                                                              0x80L
+//BIF_CFG_DEV0_RC_BIST
+#define BIF_CFG_DEV0_RC_BIST__BIST_COMP__SHIFT                                                                0x0
+#define BIF_CFG_DEV0_RC_BIST__BIST_STRT__SHIFT                                                                0x6
+#define BIF_CFG_DEV0_RC_BIST__BIST_CAP__SHIFT                                                                 0x7
+#define BIF_CFG_DEV0_RC_BIST__BIST_COMP_MASK                                                                  0x0FL
+#define BIF_CFG_DEV0_RC_BIST__BIST_STRT_MASK                                                                  0x40L
+#define BIF_CFG_DEV0_RC_BIST__BIST_CAP_MASK                                                                   0x80L
+//BIF_CFG_DEV0_RC_BASE_ADDR_1
+#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_BASE_ADDR_2
+#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                            0x10
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                0x18
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                              0x000000FFL
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                            0x0000FF00L
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                              0x00FF0000L
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                  0xFF000000L
+//BIF_CFG_DEV0_RC_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                        0xc
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                      0x000FL
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_MASK                                                           0x00F0L
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                     0x0F00L
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_MASK                                                          0xF000L
+//BIF_CFG_DEV0_RC_SECONDARY_STATUS
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                            0x7
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                     0x8
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                0x9
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                          0xb
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                        0xc
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                        0xd
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                        0xe
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                        0xf
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP_MASK                                                     0x0020L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                              0x0080L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                       0x0100L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                  0x0600L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                            0x0800L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                          0x1000L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                          0x2000L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                          0x4000L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                          0x8000L
+//BIF_CFG_DEV0_RC_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV0_RC_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                           0x4
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                              0x0000000FL
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                             0x0000FFF0L
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_RC_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                               0x10
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                 0xFFFF0000L
+//BIF_CFG_DEV0_RC_CAP_PTR
+#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR_MASK                                                                 0xFFL
+//BIF_CFG_DEV0_RC_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_INTERRUPT_LINE
+#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                   0xFFL
+//BIF_CFG_DEV0_RC_INTERRUPT_PIN
+#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                     0xFFL
+//BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                       0x1
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                        0x2
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                        0x3
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                             0x5
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                           0x6
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                       0x9
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                          0xa
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                     0xb
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                              0x0001L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                         0x0002L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                          0x0004L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                          0x0008L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                         0x0010L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                               0x0020L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                             0x0040L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                           0x0100L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                         0x0200L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                            0x0400L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                       0x0800L
+//BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                   0x01L
+//BIF_CFG_DEV0_RC_PMI_CAP_LIST
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
+//BIF_CFG_DEV0_RC_PMI_CAP
+#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK__SHIFT                                                             0x3
+#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                   0x4
+#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT__SHIFT                                                           0x6
+#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT__SHIFT                                                            0x9
+#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT                                                            0xa
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT__SHIFT                                                           0xb
+#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION_MASK                                                                 0x0007L
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK_MASK                                                               0x0008L
+#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                     0x0010L
+#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                       0x0020L
+#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT_MASK                                                             0x01C0L
+#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT_MASK                                                              0x0200L
+#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT_MASK                                                              0x0400L
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT_MASK                                                             0xF800L
+//BIF_CFG_DEV0_RC_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                   0x9
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                    0xd
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                 0x16
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                    0x17
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE_MASK                                                     0x00000003L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                   0x00000008L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN_MASK                                                          0x00000100L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                     0x00001E00L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                      0x00006000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS_MASK                                                      0x00008000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                   0x00400000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                      0x00800000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV0_RC_PCIE_CAP
+#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION_MASK                                                                0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE_MASK                                                            0x00F0L
+#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                       0x0100L
+#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                        0x3E00L
+//BIF_CFG_DEV0_RC_DEVICE_CAP
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                             0x6
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                              0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                           0xf
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                        0x1c
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                  0x00000007L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC_MASK                                                         0x00000018L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG_MASK                                                         0x00000020L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                               0x000001C0L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                0x00000E00L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                             0x00008000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE_MASK                                                          0x10000000L
+//BIF_CFG_DEV0_RC_DEVICE_CNTL
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                   0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                   0xa
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                             0xc
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                               0xf
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                    0x0002L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                      0x0010L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                    0x00E0L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                     0x0100L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                     0x0200L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                     0x0400L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                         0x0800L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                               0x7000L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                 0x8000L
+//BIF_CFG_DEV0_RC_DEVICE_STATUS
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                               0x5
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                   0x6
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR_MASK                                                          0x0001L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                     0x0002L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR_MASK                                                           0x0010L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                 0x0020L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                     0x0040L
+//BIF_CFG_DEV0_RC_LINK_CAP
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                      0xf
+#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                               0x12
+#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                          0x13
+#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                             0x15
+#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                          0x16
+#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER__SHIFT                                                          0x18
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED_MASK                                                             0x0000000FL
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH_MASK                                                             0x000003F0L
+#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT_MASK                                                             0x00000C00L
+#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                       0x00007000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY_MASK                                                        0x00038000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                 0x00040000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                            0x00080000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                            0x00100000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                               0x00200000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                            0x00400000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER_MASK                                                            0xFF000000L
+//BIF_CFG_DEV0_RC_LINK_CNTL
+#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS__SHIFT                                                            0x4
+#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK__SHIFT                                                        0x5
+#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                    0x6
+#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                         0x9
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                           0xa
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                           0xb
+#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                               0xe
+#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL_MASK                                                            0x0003L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS_MASK                                                              0x0010L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK_MASK                                                          0x0020L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                      0x0040L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                             0x0100L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                           0x0200L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                             0x0400L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                             0x0800L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                 0xC000L
+//BIF_CFG_DEV0_RC_LINK_STATUS
+#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                             0x4
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                    0xc
+#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE__SHIFT                                                         0xd
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                         0xe
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                         0xf
+#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                               0x03F0L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                      0x1000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE_MASK                                                           0x2000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                           0x4000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                           0x8000L
+//BIF_CFG_DEV0_RC_SLOT_CAP
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                               0x1
+#define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                               0x3
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                0x4
+#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                      0x6
+#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                 0x7
+#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                        0x11
+#define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                       0x12
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                    0x13
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                    0x00000001L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                 0x00000002L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                     0x00000004L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                 0x00000008L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                  0x00000010L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                       0x00000020L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                        0x00000040L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                   0x00007F80L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                   0x00018000L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                      0xFFF80000L
+//BIF_CFG_DEV0_RC_SLOT_CNTL
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                               0x1
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                               0x2
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                          0x3
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                 0x6
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                 0xa
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                          0xb
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                         0xd
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                0x0001L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                 0x0004L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                            0x0008L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                       0x0020L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                   0x00C0L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                    0x0300L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                   0x0400L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                            0x0800L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                           0x2000L
+//BIF_CFG_DEV0_RC_SLOT_STATUS
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                0x1
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                0x2
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                           0x3
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                 0x0001L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                  0x0002L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                  0x0004L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                             0x0008L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                        0x0080L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                    0x0100L
+//BIF_CFG_DEV0_RC_ROOT_CNTL
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                             0x1
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                0x2
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                   0x0001L
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                               0x0002L
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                  0x0004L
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                            0x0010L
+//BIF_CFG_DEV0_RC_ROOT_CAP
+#define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                0x0001L
+//BIF_CFG_DEV0_RC_ROOT_STATUS
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS__SHIFT                                                        0x10
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING__SHIFT                                                       0x11
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS_MASK                                                          0x00010000L
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING_MASK                                                         0x00020000L
+//BIF_CFG_DEV0_RC_DEVICE_CAP2
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                       0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                          0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                        0x6
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                        0x7
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                        0x8
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                            0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                         0xa
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                0xc
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                     0xe
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                   0x10
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                   0x11
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                    0x12
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                      0x14
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                      0x15
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                          0x16
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                    0x18
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                     0x1a
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                         0x0000000FL
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                            0x00000020L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                          0x00000040L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                          0x00000100L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                              0x00000200L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                           0x00000400L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                       0x00000800L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                  0x00003000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                       0x0000C000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                     0x00020000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                      0x000C0000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                        0x00200000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                            0x00C00000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                      0x03000000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                       0x04000000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_RC_DEVICE_CNTL2
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                              0x6
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                         0x7
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                               0x8
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                            0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                     0xb
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                     0xc
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN__SHIFT                                                          0xd
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                      0xf
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                  0x0020L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                0x0040L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                           0x0080L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                              0x0200L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN_MASK                                                             0x0400L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                       0x0800L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                       0x1000L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN_MASK                                                            0x6000L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                        0x8000L
+//BIF_CFG_DEV0_RC_DEVICE_STATUS2
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_RC_LINK_CAP2
+#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                0x1
+#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                            0x10
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                           0x17
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                           0x18
+#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                       0x1f
+#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                  0x000000FEL
+#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                   0x00000100L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                              0x007F0000L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                             0x00800000L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                             0x01000000L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED_MASK                                                         0x80000000L
+//BIF_CFG_DEV0_RC_LINK_CNTL2
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                        0x5
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                              0x6
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                               0xa
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                              0xc
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                    0x000FL
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                          0x0020L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                0x0040L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN_MASK                                                          0x0380L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                0xF000L
+//BIF_CFG_DEV0_RC_LINK_STATUS2
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                  0x2
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                  0x3
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                  0x4
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                    0x5
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                0x6
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                0x7
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                             0x8
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                    0xc
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                             0xf
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                               0x0001L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                          0x0002L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                    0x0004L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                    0x0008L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                    0x0010L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                      0x0020L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                  0x0080L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                               0x0300L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                      0x7000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                               0x8000L
+//BIF_CFG_DEV0_RC_SLOT_CAP2
+#define BIF_CFG_DEV0_RC_SLOT_CAP2__RESERVED__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_RC_SLOT_CAP2__RESERVED_MASK                                                              0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SLOT_CNTL2
+#define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED_MASK                                                             0xFFFFL
+//BIF_CFG_DEV0_RC_SLOT_STATUS2
+#define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_CAP_LIST
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
+//BIF_CFG_DEV0_RC_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                    0x1
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                        0x8
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                             0x9
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                              0xa
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN_MASK                                                             0x0001L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                      0x000EL
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                       0x0070L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT_MASK                                                          0x0080L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                          0x0100L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                               0x0200L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                                0x0400L
+//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                               0x2
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_MSI_MSG_DATA
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                             0xFFFFL
+//BIF_CFG_DEV0_RC_SSID_CAP_LIST
+#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV0_RC_SSID_CAP
+#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                         0x10
+#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID_MASK                                                           0xFFFF0000L
+//BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_RC_MSI_MAP_CAP
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__EN__SHIFT                                                                0x0
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__FIXD__SHIFT                                                              0x1
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                          0xb
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__EN_MASK                                                                  0x0001L
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__FIXD_MASK                                                                0x0002L
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__CAP_TYPE_MASK                                                            0xF800L
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                             0x10
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                               0x4
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                               0xa
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                 0x00000070L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                   0x00000300L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                 0x00000C00L
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                     0x18
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                0x000000FFL
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                               0x1
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                             0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                 0x000EL
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                         0x0001L
+//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x007F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
+//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
+//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x003F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
+//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
+//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                      0x5
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                         0xc
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                          0xd
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                       0x10
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                        0x11
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                         0x12
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                        0x13
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                  0x14
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                   0x15
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                  0x16
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                  0x17
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                         0x18
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                          0x19
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                     0x1a
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                           0x01000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                            0x02000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                       0x04000000L
+//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                             0x4
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                          0x5
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                             0xc
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                              0xd
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                         0xe
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                       0xf
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                            0x11
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                             0x12
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                            0x13
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                      0x14
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                       0x15
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                      0x16
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                      0x17
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                             0x18
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                              0x19
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                         0x1a
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                               0x00000010L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                            0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                               0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                           0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                             0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                              0x00020000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                               0x00040000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                              0x00080000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                         0x00200000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                        0x00800000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                               0x01000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                0x02000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                           0x04000000L
+//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                     0x4
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                  0x5
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                     0xc
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                      0xd
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                 0xe
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                               0xf
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                   0x10
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                    0x11
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                     0x12
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                    0x13
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                              0x14
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                               0x15
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                              0x16
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                              0x17
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                     0x18
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                      0x19
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x1a
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                0x00100000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                0x00400000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                0x00800000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                       0x01000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                        0x02000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                   0x04000000L
+//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                           0x6
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                          0x7
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                               0x8
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                              0xc
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                             0xd
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                      0xe
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                      0xf
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                               0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                        0x00008000L
+//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                               0x6
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                              0x7
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                   0x8
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                  0xc
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                 0xd
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                          0xe
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                          0xf
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                 0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                 0x00000040L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                0x00000080L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                    0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                   0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                            0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                            0x00008000L
+//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                          0x7
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                      0x9
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                  0xb
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                          0xc
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                             0x0000001FL
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                        0x00000200L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                         0x00000400L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                    0x00000800L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                            0x00001000L
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                            0x2
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                           0x00000002L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                              0x00000004L
+//BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                       0x1
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                  0x2
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                             0x3
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                0x4
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                  0x5
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                     0x6
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                      0x1b
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                    0x00000004L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                               0x00000008L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                  0x00000010L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                       0x00000040L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                        0xF8000000L
+//BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                     0x10
+#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                  0x1
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                    0x00000002L
+//BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                   0x0000FFFFL
+//BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                             0x1
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                             0x2
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                          0x3
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                              0x4
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                               0x5
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                            0x6
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                               0x0002L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                               0x0004L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                            0x0008L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                0x0010L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                 0x0020L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                              0x0040L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                         0xFF00L
+//BIF_CFG_DEV0_RC_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                         0x2
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                      0x3
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                           0x5
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                              0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                           0x0002L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                           0x0004L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                        0x0008L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                            0x0010L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                             0x0020L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                          0x0040L
+//BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                     0x1f
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                       0x007FFFFFL
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                       0x80000000L
+//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                           0x1f
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                             0x80000000L
+//BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIF_CFG_DEV0_RC_LINK_CAP_16GT
+#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                             0x1
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                             0x2
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                             0x3
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                               0x4
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                     0x00000001L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                               0x00000002L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                               0x00000004L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                               0x00000008L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                 0x00000010L
+//BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
+#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
+//BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
+#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
+//BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
+#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
+//BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_RC_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                    0x0
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                      0x0001L
+//BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                0x1
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                           0x0001L
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                  0x0002L
+//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+//BIF_CFG_DEV1_RC_VENDOR_ID
+#define BIF_CFG_DEV1_RC_VENDOR_ID__VENDOR_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC_VENDOR_ID__VENDOR_ID_MASK                                                             0xFFFFL
+//BIF_CFG_DEV1_RC_DEVICE_ID
+#define BIF_CFG_DEV1_RC_DEVICE_ID__DEVICE_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC_DEVICE_ID__DEVICE_ID_MASK                                                             0xFFFFL
+//BIF_CFG_DEV1_RC_COMMAND
+#define BIF_CFG_DEV1_RC_COMMAND__IOEN_DN__SHIFT                                                               0x0
+#define BIF_CFG_DEV1_RC_COMMAND__MEMEN_DN__SHIFT                                                              0x1
+#define BIF_CFG_DEV1_RC_COMMAND__BUS_MASTER_EN__SHIFT                                                         0x2
+#define BIF_CFG_DEV1_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                      0x3
+#define BIF_CFG_DEV1_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV1_RC_COMMAND__PAL_SNOOP_EN__SHIFT                                                          0x5
+#define BIF_CFG_DEV1_RC_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                 0x6
+#define BIF_CFG_DEV1_RC_COMMAND__AD_STEPPING__SHIFT                                                           0x7
+#define BIF_CFG_DEV1_RC_COMMAND__SERR_EN__SHIFT                                                               0x8
+#define BIF_CFG_DEV1_RC_COMMAND__FAST_B2B_EN__SHIFT                                                           0x9
+#define BIF_CFG_DEV1_RC_COMMAND__INT_DIS__SHIFT                                                               0xa
+#define BIF_CFG_DEV1_RC_COMMAND__IOEN_DN_MASK                                                                 0x0001L
+#define BIF_CFG_DEV1_RC_COMMAND__MEMEN_DN_MASK                                                                0x0002L
+#define BIF_CFG_DEV1_RC_COMMAND__BUS_MASTER_EN_MASK                                                           0x0004L
+#define BIF_CFG_DEV1_RC_COMMAND__SPECIAL_CYCLE_EN_MASK                                                        0x0008L
+#define BIF_CFG_DEV1_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                 0x0010L
+#define BIF_CFG_DEV1_RC_COMMAND__PAL_SNOOP_EN_MASK                                                            0x0020L
+#define BIF_CFG_DEV1_RC_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                   0x0040L
+#define BIF_CFG_DEV1_RC_COMMAND__AD_STEPPING_MASK                                                             0x0080L
+#define BIF_CFG_DEV1_RC_COMMAND__SERR_EN_MASK                                                                 0x0100L
+#define BIF_CFG_DEV1_RC_COMMAND__FAST_B2B_EN_MASK                                                             0x0200L
+#define BIF_CFG_DEV1_RC_COMMAND__INT_DIS_MASK                                                                 0x0400L
+//BIF_CFG_DEV1_RC_STATUS
+#define BIF_CFG_DEV1_RC_STATUS__IMMEDIATE_READINESS__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_RC_STATUS__INT_STATUS__SHIFT                                                             0x3
+#define BIF_CFG_DEV1_RC_STATUS__CAP_LIST__SHIFT                                                               0x4
+#define BIF_CFG_DEV1_RC_STATUS__PCI_66_CAP__SHIFT                                                             0x5
+#define BIF_CFG_DEV1_RC_STATUS__FAST_BACK_CAPABLE__SHIFT                                                      0x7
+#define BIF_CFG_DEV1_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                               0x8
+#define BIF_CFG_DEV1_RC_STATUS__DEVSEL_TIMING__SHIFT                                                          0x9
+#define BIF_CFG_DEV1_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                    0xb
+#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                  0xc
+#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                  0xd
+#define BIF_CFG_DEV1_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                  0xe
+#define BIF_CFG_DEV1_RC_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                  0xf
+#define BIF_CFG_DEV1_RC_STATUS__IMMEDIATE_READINESS_MASK                                                      0x0001L
+#define BIF_CFG_DEV1_RC_STATUS__INT_STATUS_MASK                                                               0x0008L
+#define BIF_CFG_DEV1_RC_STATUS__CAP_LIST_MASK                                                                 0x0010L
+#define BIF_CFG_DEV1_RC_STATUS__PCI_66_CAP_MASK                                                               0x0020L
+#define BIF_CFG_DEV1_RC_STATUS__FAST_BACK_CAPABLE_MASK                                                        0x0080L
+#define BIF_CFG_DEV1_RC_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                 0x0100L
+#define BIF_CFG_DEV1_RC_STATUS__DEVSEL_TIMING_MASK                                                            0x0600L
+#define BIF_CFG_DEV1_RC_STATUS__SIGNAL_TARGET_ABORT_MASK                                                      0x0800L
+#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_TARGET_ABORT_MASK                                                    0x1000L
+#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_MASTER_ABORT_MASK                                                    0x2000L
+#define BIF_CFG_DEV1_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                    0x4000L
+#define BIF_CFG_DEV1_RC_STATUS__PARITY_ERROR_DETECTED_MASK                                                    0x8000L
+//BIF_CFG_DEV1_RC_REVISION_ID
+#define BIF_CFG_DEV1_RC_REVISION_ID__MINOR_REV_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_RC_REVISION_ID__MAJOR_REV_ID__SHIFT                                                      0x4
+#define BIF_CFG_DEV1_RC_REVISION_ID__MINOR_REV_ID_MASK                                                        0x0FL
+#define BIF_CFG_DEV1_RC_REVISION_ID__MAJOR_REV_ID_MASK                                                        0xF0L
+//BIF_CFG_DEV1_RC_PROG_INTERFACE
+#define BIF_CFG_DEV1_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC_PROG_INTERFACE__PROG_INTERFACE_MASK                                                   0xFFL
+//BIF_CFG_DEV1_RC_SUB_CLASS
+#define BIF_CFG_DEV1_RC_SUB_CLASS__SUB_CLASS__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC_SUB_CLASS__SUB_CLASS_MASK                                                             0xFFL
+//BIF_CFG_DEV1_RC_BASE_CLASS
+#define BIF_CFG_DEV1_RC_BASE_CLASS__BASE_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC_BASE_CLASS__BASE_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV1_RC_CACHE_LINE
+#define BIF_CFG_DEV1_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                      0xFFL
+//BIF_CFG_DEV1_RC_LATENCY
+#define BIF_CFG_DEV1_RC_LATENCY__LATENCY_TIMER__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC_LATENCY__LATENCY_TIMER_MASK                                                           0xFFL
+//BIF_CFG_DEV1_RC_HEADER
+#define BIF_CFG_DEV1_RC_HEADER__HEADER_TYPE__SHIFT                                                            0x0
+#define BIF_CFG_DEV1_RC_HEADER__DEVICE_TYPE__SHIFT                                                            0x7
+#define BIF_CFG_DEV1_RC_HEADER__HEADER_TYPE_MASK                                                              0x7FL
+#define BIF_CFG_DEV1_RC_HEADER__DEVICE_TYPE_MASK                                                              0x80L
+//BIF_CFG_DEV1_RC_BIST
+#define BIF_CFG_DEV1_RC_BIST__BIST_COMP__SHIFT                                                                0x0
+#define BIF_CFG_DEV1_RC_BIST__BIST_STRT__SHIFT                                                                0x6
+#define BIF_CFG_DEV1_RC_BIST__BIST_CAP__SHIFT                                                                 0x7
+#define BIF_CFG_DEV1_RC_BIST__BIST_COMP_MASK                                                                  0x0FL
+#define BIF_CFG_DEV1_RC_BIST__BIST_STRT_MASK                                                                  0x40L
+#define BIF_CFG_DEV1_RC_BIST__BIST_CAP_MASK                                                                   0x80L
+//BIF_CFG_DEV1_RC_BASE_ADDR_1
+#define BIF_CFG_DEV1_RC_BASE_ADDR_1__BASE_ADDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC_BASE_ADDR_1__BASE_ADDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_BASE_ADDR_2
+#define BIF_CFG_DEV1_RC_BASE_ADDR_2__BASE_ADDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC_BASE_ADDR_2__BASE_ADDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                          0x8
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                            0x10
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                0x18
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                              0x000000FFL
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                            0x0000FF00L
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                              0x00FF0000L
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                  0xFF000000L
+//BIF_CFG_DEV1_RC_IO_BASE_LIMIT
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE__SHIFT                                                         0x4
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                        0xc
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                      0x000FL
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_MASK                                                           0x00F0L
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                     0x0F00L
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_MASK                                                          0xF000L
+//BIF_CFG_DEV1_RC_SECONDARY_STATUS
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                   0x5
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                            0x7
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                     0x8
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                0x9
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                          0xb
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                        0xc
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                        0xd
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                        0xe
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                        0xf
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PCI_66_CAP_MASK                                                     0x0020L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                              0x0080L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                       0x0100L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                  0x0600L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                            0x0800L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                          0x1000L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                          0x2000L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                          0x4000L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                          0x8000L
+//BIF_CFG_DEV1_RC_MEM_BASE_LIMIT
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV1_RC_PREF_BASE_LIMIT
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                           0x4
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                           0x10
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                          0x14
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                              0x0000000FL
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                             0x0000FFF0L
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                             0x000F0000L
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                            0xFFF00000L
+//BIF_CFG_DEV1_RC_PREF_BASE_UPPER
+#define BIF_CFG_DEV1_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                               0x10
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                 0xFFFF0000L
+//BIF_CFG_DEV1_RC_CAP_PTR
+#define BIF_CFG_DEV1_RC_CAP_PTR__CAP_PTR__SHIFT                                                               0x0
+#define BIF_CFG_DEV1_RC_CAP_PTR__CAP_PTR_MASK                                                                 0xFFL
+//BIF_CFG_DEV1_RC_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_RC_ROM_BASE_ADDR__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_INTERRUPT_LINE
+#define BIF_CFG_DEV1_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                   0xFFL
+//BIF_CFG_DEV1_RC_INTERRUPT_PIN
+#define BIF_CFG_DEV1_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                     0xFFL
+//BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                       0x1
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                        0x2
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                        0x3
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                       0x4
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                             0x5
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                           0x6
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                   0x7
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                         0x8
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                       0x9
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                          0xa
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                     0xb
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                              0x0001L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                         0x0002L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                          0x0004L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                          0x0008L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                         0x0010L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                               0x0020L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                             0x0040L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                     0x0080L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                           0x0100L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                         0x0200L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                            0x0400L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                       0x0800L
+//BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                   0x01L
+//BIF_CFG_DEV1_RC_PMI_CAP_LIST
+#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
+#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
+#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
+//BIF_CFG_DEV1_RC_PMI_CAP
+#define BIF_CFG_DEV1_RC_PMI_CAP__VERSION__SHIFT                                                               0x0
+#define BIF_CFG_DEV1_RC_PMI_CAP__PME_CLOCK__SHIFT                                                             0x3
+#define BIF_CFG_DEV1_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                   0x4
+#define BIF_CFG_DEV1_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                     0x5
+#define BIF_CFG_DEV1_RC_PMI_CAP__AUX_CURRENT__SHIFT                                                           0x6
+#define BIF_CFG_DEV1_RC_PMI_CAP__D1_SUPPORT__SHIFT                                                            0x9
+#define BIF_CFG_DEV1_RC_PMI_CAP__D2_SUPPORT__SHIFT                                                            0xa
+#define BIF_CFG_DEV1_RC_PMI_CAP__PME_SUPPORT__SHIFT                                                           0xb
+#define BIF_CFG_DEV1_RC_PMI_CAP__VERSION_MASK                                                                 0x0007L
+#define BIF_CFG_DEV1_RC_PMI_CAP__PME_CLOCK_MASK                                                               0x0008L
+#define BIF_CFG_DEV1_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                     0x0010L
+#define BIF_CFG_DEV1_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                       0x0020L
+#define BIF_CFG_DEV1_RC_PMI_CAP__AUX_CURRENT_MASK                                                             0x01C0L
+#define BIF_CFG_DEV1_RC_PMI_CAP__D1_SUPPORT_MASK                                                              0x0200L
+#define BIF_CFG_DEV1_RC_PMI_CAP__D2_SUPPORT_MASK                                                              0x0400L
+#define BIF_CFG_DEV1_RC_PMI_CAP__PME_SUPPORT_MASK                                                             0xF800L
+//BIF_CFG_DEV1_RC_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                 0x3
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_EN__SHIFT                                                        0x8
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                   0x9
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                    0xd
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                    0xf
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                 0x16
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                    0x17
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                      0x18
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__POWER_STATE_MASK                                                     0x00000003L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                   0x00000008L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_EN_MASK                                                          0x00000100L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                     0x00001E00L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                      0x00006000L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_STATUS_MASK                                                      0x00008000L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                   0x00400000L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                      0x00800000L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PMI_DATA_MASK                                                        0xFF000000L
+//BIF_CFG_DEV1_RC_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV1_RC_PCIE_CAP
+#define BIF_CFG_DEV1_RC_PCIE_CAP__VERSION__SHIFT                                                              0x0
+#define BIF_CFG_DEV1_RC_PCIE_CAP__DEVICE_TYPE__SHIFT                                                          0x4
+#define BIF_CFG_DEV1_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                     0x8
+#define BIF_CFG_DEV1_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                      0x9
+#define BIF_CFG_DEV1_RC_PCIE_CAP__VERSION_MASK                                                                0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_CAP__DEVICE_TYPE_MASK                                                            0x00F0L
+#define BIF_CFG_DEV1_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                       0x0100L
+#define BIF_CFG_DEV1_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                        0x3E00L
+//BIF_CFG_DEV1_RC_DEVICE_CAP
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                       0x3
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                       0x5
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                             0x6
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                              0x9
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                           0xf
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                        0x1c
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                  0x00000007L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__PHANTOM_FUNC_MASK                                                         0x00000018L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__EXTENDED_TAG_MASK                                                         0x00000020L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                               0x000001C0L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                0x00000E00L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                             0x00008000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__FLR_CAPABLE_MASK                                                          0x10000000L
+//BIF_CFG_DEV1_RC_DEVICE_CNTL
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                  0x1
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                    0x4
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                  0x5
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                   0x9
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                   0xa
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                       0xb
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                             0xc
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                               0xf
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__CORR_ERR_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                    0x0002L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__USR_REPORT_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                      0x0010L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                    0x00E0L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                     0x0100L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                     0x0200L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                     0x0400L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                         0x0800L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                               0x7000L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                 0x8000L
+//BIF_CFG_DEV1_RC_DEVICE_STATUS
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__CORR_ERR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                   0x1
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__FATAL_ERR__SHIFT                                                       0x2
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__USR_DETECTED__SHIFT                                                    0x3
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__AUX_PWR__SHIFT                                                         0x4
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                               0x5
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                   0x6
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__CORR_ERR_MASK                                                          0x0001L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                     0x0002L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__FATAL_ERR_MASK                                                         0x0004L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__USR_DETECTED_MASK                                                      0x0008L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__AUX_PWR_MASK                                                           0x0010L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                 0x0020L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                     0x0040L
+//BIF_CFG_DEV1_RC_LINK_CAP
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_SPEED__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_WIDTH__SHIFT                                                           0x4
+#define BIF_CFG_DEV1_RC_LINK_CAP__PM_SUPPORT__SHIFT                                                           0xa
+#define BIF_CFG_DEV1_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                     0xc
+#define BIF_CFG_DEV1_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                      0xf
+#define BIF_CFG_DEV1_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                               0x12
+#define BIF_CFG_DEV1_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                          0x13
+#define BIF_CFG_DEV1_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                          0x14
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                             0x15
+#define BIF_CFG_DEV1_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                          0x16
+#define BIF_CFG_DEV1_RC_LINK_CAP__PORT_NUMBER__SHIFT                                                          0x18
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_SPEED_MASK                                                             0x0000000FL
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_WIDTH_MASK                                                             0x000003F0L
+#define BIF_CFG_DEV1_RC_LINK_CAP__PM_SUPPORT_MASK                                                             0x00000C00L
+#define BIF_CFG_DEV1_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                       0x00007000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__L1_EXIT_LATENCY_MASK                                                        0x00038000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                 0x00040000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                            0x00080000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                            0x00100000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                               0x00200000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                            0x00400000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__PORT_NUMBER_MASK                                                            0xFF000000L
+//BIF_CFG_DEV1_RC_LINK_CNTL
+#define BIF_CFG_DEV1_RC_LINK_CNTL__PM_CONTROL__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                   0x3
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_DIS__SHIFT                                                            0x4
+#define BIF_CFG_DEV1_RC_LINK_CNTL__RETRAIN_LINK__SHIFT                                                        0x5
+#define BIF_CFG_DEV1_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                    0x6
+#define BIF_CFG_DEV1_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                       0x7
+#define BIF_CFG_DEV1_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                           0x8
+#define BIF_CFG_DEV1_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                         0x9
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                           0xa
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                           0xb
+#define BIF_CFG_DEV1_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                               0xe
+#define BIF_CFG_DEV1_RC_LINK_CNTL__PM_CONTROL_MASK                                                            0x0003L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                     0x0008L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_DIS_MASK                                                              0x0010L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__RETRAIN_LINK_MASK                                                          0x0020L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                      0x0040L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__EXTENDED_SYNC_MASK                                                         0x0080L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                             0x0100L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                           0x0200L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                             0x0400L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                             0x0800L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                 0xC000L
+//BIF_CFG_DEV1_RC_LINK_STATUS
+#define BIF_CFG_DEV1_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                             0x4
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_TRAINING__SHIFT                                                     0xb
+#define BIF_CFG_DEV1_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                    0xc
+#define BIF_CFG_DEV1_RC_LINK_STATUS__DL_ACTIVE__SHIFT                                                         0xd
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                         0xe
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                         0xf
+#define BIF_CFG_DEV1_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV1_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                               0x03F0L
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_TRAINING_MASK                                                       0x0800L
+#define BIF_CFG_DEV1_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                      0x1000L
+#define BIF_CFG_DEV1_RC_LINK_STATUS__DL_ACTIVE_MASK                                                           0x2000L
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                           0x4000L
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                           0x8000L
+//BIF_CFG_DEV1_RC_SLOT_CAP
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                               0x1
+#define BIF_CFG_DEV1_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                   0x2
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                               0x3
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                0x4
+#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                     0x5
+#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                      0x6
+#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                 0x7
+#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                 0xf
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                        0x11
+#define BIF_CFG_DEV1_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                       0x12
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                    0x13
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                    0x00000001L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                 0x00000002L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                     0x00000004L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                 0x00000008L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                  0x00000010L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                       0x00000020L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                        0x00000040L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                   0x00007F80L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                   0x00018000L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                          0x00020000L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                         0x00040000L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                      0xFFF80000L
+//BIF_CFG_DEV1_RC_SLOT_CNTL
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                               0x1
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                               0x2
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                          0x3
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                     0x5
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                 0x6
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                  0x8
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                 0xa
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                          0xb
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                 0xc
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                         0xd
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                0x0001L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                 0x0002L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                 0x0004L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                            0x0008L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                       0x0020L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                   0x00C0L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                    0x0300L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                   0x0400L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                            0x0800L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                   0x1000L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                           0x2000L
+//BIF_CFG_DEV1_RC_SLOT_STATUS
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                0x1
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                0x2
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                           0x3
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                 0x4
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                  0x5
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                             0x6
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                  0x8
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                 0x0001L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                  0x0002L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                  0x0004L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                             0x0008L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                   0x0010L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                    0x0020L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                               0x0040L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                        0x0080L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                    0x0100L
+//BIF_CFG_DEV1_RC_ROOT_CNTL
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                             0x1
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                0x2
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                   0x0001L
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                               0x0002L
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                  0x0004L
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                            0x0010L
+//BIF_CFG_DEV1_RC_ROOT_CAP
+#define BIF_CFG_DEV1_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                0x0001L
+//BIF_CFG_DEV1_RC_ROOT_STATUS
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_STATUS__SHIFT                                                        0x10
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_PENDING__SHIFT                                                       0x11
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_STATUS_MASK                                                          0x00010000L
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_PENDING_MASK                                                         0x00020000L
+//BIF_CFG_DEV1_RC_DEVICE_CAP2
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                       0x0
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                         0x4
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                          0x5
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                        0x6
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                        0x7
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                        0x8
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                            0x9
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                         0xa
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                     0xb
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                0xc
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                     0xe
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                   0x10
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                   0x11
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                    0x12
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                      0x14
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                      0x15
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                          0x16
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                    0x18
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                     0x1a
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                         0x0000000FL
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                           0x00000010L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                            0x00000020L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                          0x00000040L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                          0x00000080L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                          0x00000100L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                              0x00000200L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                           0x00000400L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                       0x00000800L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                  0x00003000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                       0x0000C000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                     0x00010000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                     0x00020000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                      0x000C0000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                        0x00100000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                        0x00200000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                            0x00C00000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                      0x03000000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                       0x04000000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV1_RC_DEVICE_CNTL2
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                  0x4
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                0x5
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                              0x6
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                         0x7
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                               0x8
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                            0x9
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__LTR_EN__SHIFT                                                           0xa
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                     0xb
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                     0xc
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__OBFF_EN__SHIFT                                                          0xd
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                      0xf
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                  0x000FL
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                    0x0010L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                  0x0020L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                0x0040L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                           0x0080L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                 0x0100L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                              0x0200L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__LTR_EN_MASK                                                             0x0400L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                       0x0800L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                       0x1000L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__OBFF_EN_MASK                                                            0x6000L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                        0x8000L
+//BIF_CFG_DEV1_RC_DEVICE_STATUS2
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS2__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS2__RESERVED_MASK                                                         0xFFFFL
+//BIF_CFG_DEV1_RC_LINK_CAP2
+#define BIF_CFG_DEV1_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                0x1
+#define BIF_CFG_DEV1_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                            0x10
+#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                           0x17
+#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                           0x18
+#define BIF_CFG_DEV1_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                       0x1f
+#define BIF_CFG_DEV1_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                  0x000000FEL
+#define BIF_CFG_DEV1_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                   0x00000100L
+#define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                              0x007F0000L
+#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                             0x00800000L
+#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                             0x01000000L
+#define BIF_CFG_DEV1_RC_LINK_CAP2__DRS_SUPPORTED_MASK                                                         0x80000000L
+//BIF_CFG_DEV1_RC_LINK_CNTL2
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                   0x4
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                        0x5
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                              0x6
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                        0x7
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                               0xa
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                     0xb
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                              0xc
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                    0x000FL
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                     0x0010L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                          0x0020L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                0x0040L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__XMIT_MARGIN_MASK                                                          0x0380L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                 0x0400L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                       0x0800L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                0xF000L
+//BIF_CFG_DEV1_RC_LINK_STATUS2
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                        0x1
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                  0x2
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                  0x3
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                  0x4
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                    0x5
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                0x6
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                0x7
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                             0x8
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                    0xc
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                             0xf
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                               0x0001L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                          0x0002L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                    0x0004L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                    0x0008L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                    0x0010L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                      0x0020L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                  0x0040L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                  0x0080L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                               0x0300L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                      0x7000L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                               0x8000L
+//BIF_CFG_DEV1_RC_SLOT_CAP2
+#define BIF_CFG_DEV1_RC_SLOT_CAP2__RESERVED__SHIFT                                                            0x0
+#define BIF_CFG_DEV1_RC_SLOT_CAP2__RESERVED_MASK                                                              0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_SLOT_CNTL2
+#define BIF_CFG_DEV1_RC_SLOT_CNTL2__RESERVED__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC_SLOT_CNTL2__RESERVED_MASK                                                             0xFFFFL
+//BIF_CFG_DEV1_RC_SLOT_STATUS2
+#define BIF_CFG_DEV1_RC_SLOT_STATUS2__RESERVED__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC_SLOT_STATUS2__RESERVED_MASK                                                           0xFFFFL
+//BIF_CFG_DEV1_RC_MSI_CAP_LIST
+#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
+#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
+#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
+//BIF_CFG_DEV1_RC_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EN__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                    0x1
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                     0x4
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                        0x7
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                        0x8
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                             0x9
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                              0xa
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EN_MASK                                                             0x0001L
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                      0x000EL
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                       0x0070L
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_64BIT_MASK                                                          0x0080L
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                          0x0100L
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                               0x0200L
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                                0x0400L
+//BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                               0x2
+#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_MSI_MSG_DATA
+#define BIF_CFG_DEV1_RC_MSI_MSG_DATA__MSI_DATA__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC_MSI_MSG_DATA__MSI_DATA_MASK                                                           0xFFFFL
+//BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                   0xFFFFL
+//BIF_CFG_DEV1_RC_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                     0xFFFFL
+//BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                             0xFFFFL
+//BIF_CFG_DEV1_RC_SSID_CAP_LIST
+#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV1_RC_SSID_CAP
+#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                         0x10
+#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_ID_MASK                                                           0xFFFF0000L
+//BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV1_RC_MSI_MAP_CAP
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__EN__SHIFT                                                                0x0
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__FIXD__SHIFT                                                              0x1
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                          0xb
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__EN_MASK                                                                  0x0001L
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__FIXD_MASK                                                                0x0002L
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__CAP_TYPE_MASK                                                            0xF800L
+//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                             0x10
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                          0x14
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                            0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                               0x4
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                 0x8
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                               0xa
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                              0x00000007L
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                 0x00000070L
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                   0x00000300L
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                 0x00000C00L
+//BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                     0x18
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                0x000000FFL
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                       0xFF000000L
+//BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                               0x1
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                             0x0001L
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                 0x000EL
+//BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                         0x0001L
+//BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x007F0000L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
+//BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
+//BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
+//BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x003F0000L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
+//BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
+//BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
+//BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                      0x0
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                      0x0
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                         0x4
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                      0x5
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                         0xc
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                          0xd
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                       0x10
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                        0x11
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                         0x12
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                        0x13
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                  0x14
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                   0x15
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                  0x16
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                  0x17
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                         0x18
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                          0x19
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                     0x1a
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                           0x00000010L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                        0x00000020L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                           0x00001000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                            0x00002000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                       0x00004000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                     0x00008000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                         0x00010000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                          0x00020000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                           0x00040000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                          0x00080000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                    0x00100000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                     0x00200000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                    0x00400000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                    0x00800000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                           0x01000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                            0x02000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                       0x04000000L
+//BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                             0x4
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                          0x5
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                             0xc
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                              0xd
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                         0xe
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                       0xf
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                           0x10
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                            0x11
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                             0x12
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                            0x13
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                      0x14
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                       0x15
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                      0x16
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                      0x17
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                             0x18
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                              0x19
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                         0x1a
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                               0x00000010L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                            0x00000020L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                               0x00001000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                0x00002000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                           0x00004000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                         0x00008000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                             0x00010000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                              0x00020000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                               0x00040000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                              0x00080000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                        0x00100000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                         0x00200000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                        0x00400000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                        0x00800000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                               0x01000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                0x02000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                           0x04000000L
+//BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                     0x4
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                  0x5
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                     0xc
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                      0xd
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                 0xe
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                               0xf
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                   0x10
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                    0x11
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                     0x12
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                    0x13
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                              0x14
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                               0x15
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                              0x16
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                              0x17
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                     0x18
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                      0x19
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x1a
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                       0x00000010L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                    0x00000020L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                       0x00001000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                        0x00002000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                   0x00004000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                 0x00008000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                     0x00010000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                      0x00020000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                       0x00040000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                      0x00080000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                0x00100000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                 0x00200000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                0x00400000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                0x00800000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                       0x01000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                        0x02000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                   0x04000000L
+//BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                           0x6
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                          0x7
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                               0x8
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                              0xc
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                             0xd
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                      0xe
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                      0xf
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                             0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                             0x00000040L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                            0x00000080L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                 0x00000100L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                0x00001000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                               0x00002000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                        0x00004000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                        0x00008000L
+//BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                               0x6
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                              0x7
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                   0x8
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                  0xc
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                 0xd
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                          0xe
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                          0xf
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                 0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                 0x00000040L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                0x00000080L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                     0x00000100L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                    0x00001000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                   0x00002000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                            0x00004000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                            0x00008000L
+//BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                          0x7
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                           0x8
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                      0x9
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                  0xb
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                          0xc
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                             0x0000001FL
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                            0x00000080L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                             0x00000100L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                        0x00000200L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                         0x00000400L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                    0x00000800L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                            0x00001000L
+//BIF_CFG_DEV1_RC_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG0__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG1__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG2__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG3__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                         0x1
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                            0x2
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                               0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                           0x00000002L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                              0x00000004L
+//BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                       0x1
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                  0x2
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                             0x3
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                0x4
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                  0x5
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                     0x6
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                      0x1b
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                              0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                         0x00000002L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                    0x00000004L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                               0x00000008L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                  0x00000010L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                    0x00000020L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                       0x00000040L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                        0xF8000000L
+//BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                     0x10
+#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                  0x1
+#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                            0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                    0x00000002L
+//BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                   0x0000FFFFL
+//BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                             0x1
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                             0x2
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                          0x3
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                              0x4
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                               0x5
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                            0x6
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                       0x8
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                  0x0001L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                               0x0002L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                               0x0004L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                            0x0008L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                0x0010L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                 0x0020L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                              0x0040L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                         0xFF00L
+//BIF_CFG_DEV1_RC_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                         0x1
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                         0x2
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                      0x3
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                           0x5
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                              0x0001L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                           0x0002L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                           0x0004L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                        0x0008L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                            0x0010L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                             0x0020L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                          0x0040L
+//BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                     0x1f
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                       0x007FFFFFL
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                       0x80000000L
+//BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                           0x1f
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                             0x80000000L
+//BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIF_CFG_DEV1_RC_LINK_CAP_16GT
+#define BIF_CFG_DEV1_RC_LINK_CAP_16GT__RESERVED__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC_LINK_CAP_16GT__RESERVED_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_LINK_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LINK_CNTL_16GT__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_RC_LINK_CNTL_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_LINK_STATUS_16GT
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                   0x0
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                             0x1
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                             0x2
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                             0x3
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                               0x4
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                     0x00000001L
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                               0x00000002L
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                               0x00000004L
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                               0x00000008L
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                 0x00000010L
+//BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
+#define BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
+//BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
+#define BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
+//BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
+#define BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
+//BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV1_RC_MARGINING_PORT_CAP
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                    0x0
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                      0x0001L
+//BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                         0x0
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                0x1
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                           0x0001L
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                  0x0002L
+//BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+
+
+// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec
+
+
+// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF0_COMMAND
+#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
+#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
+#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                               0x6
+#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT                                                         0x7
+#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT                                                             0x8
+#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT                                                             0xa
+#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
+#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
+#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK                                                           0x0080L
+#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK                                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
+#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK                                                               0x0400L
+//BIF_CFG_DEV0_EPF0_STATUS
+#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT                                                             0x4
+#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK                                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
+//BIF_CFG_DEV0_EPF0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
+//BIF_CFG_DEV0_EPF0_LATENCY
+#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_HEADER
+#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK                                                            0x7FL
+#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK                                                            0x80L
+//BIF_CFG_DEV0_EPF0_BIST
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT                                                              0x6
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT                                                               0x7
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK                                                                0x0FL
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK                                                                0x40L
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK                                                                 0x80L
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
+//BIF_CFG_DEV0_EPF0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
+//BIF_CFG_DEV0_EPF0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
+//BIF_CFG_DEV0_EPF0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF0_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK                                                               0x0007L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
+//BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK                                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
+//BIF_CFG_DEV0_EPF0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
+//BIF_CFG_DEV0_EPF0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
+//BIF_CFG_DEV0_EPF0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
+//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
+//BIF_CFG_DEV0_EPF0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                             0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                               0x00000070L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                               0x00000C00L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                              0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                               0x000EL
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                       0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x003F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
+//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                        0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                          0x00008000L
+//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                  0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                          0x00001000L
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                  0x00000002L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                               0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK                                                             0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                                 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                  0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                          0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                                0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                            0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                            0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                  0x0100L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                              0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                          0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                      0x003FL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                   0x3F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                      0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                     0x003FL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                        0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                    0x0000003FL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                  0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                          0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                          0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                        0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                       0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                          0x000003FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                          0x00001C00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                         0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                         0x1C000000L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                            0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                     0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                              0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                              0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                       0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                                0xFFE00000L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                                0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                  0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                  0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                             0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                    0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                      0x0020L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                   0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                      0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                          0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                              0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                  0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                              0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                          0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                    0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                            0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT     0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK       0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                               0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                             0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                            0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                  0x00000600L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                      0x07FF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                                0x00000300L
+//BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                   0x1f
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                     0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                     0x80000000L
+//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                   0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                             0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                             0x00000008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                               0x00000010L
+//BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
+#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
+#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                    0x0001L
+//BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                0x0002L
+//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                            0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                           0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                               0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                              0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                             0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                                 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                      0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                         0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                            0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                           0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT       0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT        0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT       0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT       0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT      0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT       0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT    0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK          0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK   0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK         0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK    0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK          0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK   0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK         0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK    0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK         0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK        0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK   0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK          0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK   0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK         0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK    0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK      0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK    0x02000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT   0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT    0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT   0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT   0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT    0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT   0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK      0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK     0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK      0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK     0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK     0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK    0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK      0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK     0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                     0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT                 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                  0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                        0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                    0x00000F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                    0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                     0x01000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT                 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT                 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT                 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                   0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT                 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT                 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                   0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT                 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                   0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT                 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                   0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT                 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                   0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT                 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                   0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT                 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                  0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT                0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                  0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT                0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                  0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                  0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT                0x1b
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                  0x1c
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT                0x1d
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                  0x1e
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT                0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                   0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                   0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                   0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                     0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                   0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                     0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                   0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                   0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                     0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                   0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                     0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                     0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                   0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                     0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                   0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                    0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                  0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                    0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                    0x04000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                  0x08000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                    0x10000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                  0x20000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                    0x40000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                  0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT                0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT                  0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT                0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT                  0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT                0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT                0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT                0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT                  0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT                0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT                  0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT                0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT                  0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT                0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT                  0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT                0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT                  0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT                0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT                  0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT                0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT                  0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT                0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT                  0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT                  0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT                0x1b
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT                  0x1c
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT                0x1d
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                    0x1e
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                  0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK                    0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK                  0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK                    0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK                  0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK                    0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK                  0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK                    0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK                  0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK                    0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK                  0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK                    0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK                  0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK                    0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK                  0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK                    0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK                  0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK                    0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK                  0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK                    0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK                  0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK                    0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK                  0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK                    0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK                    0x04000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK                  0x08000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK                    0x10000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK                  0x20000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                      0x40000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                    0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT                                 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT                      0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK                          0x0000007FL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK                                   0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK                        0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                  0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                   0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                    0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT                       0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT                      0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK                        0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK                         0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK                        0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK                             0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK                             0x00000070L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK  0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK                               0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF1_COMMAND
+#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
+#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
+#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                               0x6
+#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT                                                         0x7
+#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT                                                             0x8
+#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT                                                             0xa
+#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
+#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
+#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK                                                           0x0080L
+#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK                                                               0x0100L
+#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
+#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK                                                               0x0400L
+//BIF_CFG_DEV0_EPF1_STATUS
+#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT                                                             0x4
+#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK                                                               0x0010L
+#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF1_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
+//BIF_CFG_DEV0_EPF1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
+//BIF_CFG_DEV0_EPF1_LATENCY
+#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF1_HEADER
+#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK                                                            0x7FL
+#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK                                                            0x80L
+//BIF_CFG_DEV0_EPF1_BIST
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT                                                              0x6
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT                                                               0x7
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK                                                                0x0FL
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK                                                                0x40L
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK                                                                 0x80L
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
+//BIF_CFG_DEV0_EPF1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
+//BIF_CFG_DEV0_EPF1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
+//BIF_CFG_DEV0_EPF1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF1_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK                                                               0x0007L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
+//BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK                                                              0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
+//BIF_CFG_DEV0_EPF1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
+//BIF_CFG_DEV0_EPF1_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
+//BIF_CFG_DEV0_EPF1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
+//BIF_CFG_DEV0_EPF1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
+//BIF_CFG_DEV0_EPF1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
+//BIF_CFG_DEV0_EPF1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
+//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
+//BIF_CFG_DEV0_EPF1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                             0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                               0x00000070L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                               0x00000C00L
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                              0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                               0x000EL
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                       0x0001L
+//BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
+//BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x003F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
+//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                        0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                          0x00008000L
+//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                  0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                          0x00001000L
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                  0x00000002L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
+//BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                               0x001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU_MASK                                                             0x001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                                 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                  0x0002L
+//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                          0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                                0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                            0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                            0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                  0x0100L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                              0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                          0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                      0x003FL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                   0x3F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                      0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                     0x003FL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                        0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                    0x0000003FL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                  0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                          0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                          0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                        0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                       0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                          0x000003FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                          0x00001C00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                         0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                         0x1C000000L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                            0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                     0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                              0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                              0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                       0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                                0xFFE00000L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                                0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                  0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                  0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                             0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                    0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                      0x0020L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                   0x0001L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                      0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                          0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                              0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                  0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                              0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                          0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                    0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                            0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT     0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK       0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                               0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                             0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                            0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                  0x00000600L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                      0x07FF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                                0x00000300L
+//BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                   0x1f
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                     0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                     0x80000000L
+//BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                   0x00000001L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                             0x00000002L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                             0x00000008L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                               0x00000010L
+//BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
+#define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
+#define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                    0x0001L
+//BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                0x0002L
+//BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                            0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                           0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                               0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                              0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                             0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                                 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                      0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                         0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                            0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                           0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT       0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT       0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT       0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT      0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT       0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT    0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK          0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK   0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK         0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK    0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK          0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK   0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK         0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK    0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK         0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK        0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK   0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK          0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK   0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK         0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK    0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK      0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK    0x02000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT   0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT    0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT   0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT   0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT    0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT   0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK      0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK     0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK      0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK     0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK     0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK    0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK      0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK     0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                     0x0001L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT                 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                  0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                        0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                    0x00000F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                   0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                    0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                     0x01000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT                 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT                 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT                 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                   0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT                 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT                 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                   0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT                 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                   0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT                 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                   0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT                 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                   0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT                 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                   0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT                 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                  0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT                0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                  0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT                0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                  0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                  0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT                0x1b
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                  0x1c
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT                0x1d
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                  0x1e
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT                0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                     0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                   0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                   0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                     0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                   0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                     0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                   0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                     0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                   0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                     0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                   0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                     0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                   0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                     0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                   0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                     0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                   0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                     0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                   0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                    0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                  0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                    0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                  0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                    0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                    0x04000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                  0x08000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                    0x10000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                  0x20000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                    0x40000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                  0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT                0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT                  0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT                0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT                  0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT                0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT                0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT                  0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT                0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT                  0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT                0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT                  0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT                0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT                  0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT                0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT                  0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT                0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT                  0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT                0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT                  0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT                0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT                  0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT                  0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT                0x1b
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT                  0x1c
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT                0x1d
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                    0x1e
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                  0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK                    0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK                  0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK                    0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK                  0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK                    0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK                  0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK                    0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK                  0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK                    0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK                  0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK                    0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK                  0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK                    0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK                  0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK                    0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK                  0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK                    0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK                  0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK                    0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK                  0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK                    0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK                  0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK                    0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK                  0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK                    0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK                    0x04000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK                  0x08000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK                    0x10000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK                  0x20000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                      0x40000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                    0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT                                 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT                      0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK                          0x0000007FL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK                                   0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK                        0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                  0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                   0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                    0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT                       0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT                      0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK                        0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK                         0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK                        0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK                             0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK                             0x00000070L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK  0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK                               0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF2_COMMAND
+#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
+#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
+#define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                               0x6
+#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING__SHIFT                                                         0x7
+#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN__SHIFT                                                             0x8
+#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS__SHIFT                                                             0xa
+#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
+#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
+#define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING_MASK                                                           0x0080L
+#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN_MASK                                                               0x0100L
+#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
+#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS_MASK                                                               0x0400L
+//BIF_CFG_DEV0_EPF2_STATUS
+#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST__SHIFT                                                             0x4
+#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST_MASK                                                               0x0010L
+#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF2_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
+//BIF_CFG_DEV0_EPF2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
+//BIF_CFG_DEV0_EPF2_LATENCY
+#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF2_HEADER
+#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE_MASK                                                            0x7FL
+#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE_MASK                                                            0x80L
+//BIF_CFG_DEV0_EPF2_BIST
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT__SHIFT                                                              0x6
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP__SHIFT                                                               0x7
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP_MASK                                                                0x0FL
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT_MASK                                                                0x40L
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP_MASK                                                                 0x80L
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
+//BIF_CFG_DEV0_EPF2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
+//BIF_CFG_DEV0_EPF2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
+//BIF_CFG_DEV0_EPF2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF2_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION_MASK                                                               0x0007L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
+//BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF2_SBRN
+#define BIF_CFG_DEV0_EPF2_SBRN__SBRN__SHIFT                                                                   0x0
+#define BIF_CFG_DEV0_EPF2_SBRN__SBRN_MASK                                                                     0xFFL
+//BIF_CFG_DEV0_EPF2_FLADJ
+#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF2_FLADJ__NFC__SHIFT                                                                   0x6
+#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ_MASK                                                                   0x3FL
+#define BIF_CFG_DEV0_EPF2_FLADJ__NFC_MASK                                                                     0x40L
+//BIF_CFG_DEV0_EPF2_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
+//BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION_MASK                                                              0x000FL
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
+//BIF_CFG_DEV0_EPF2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
+//BIF_CFG_DEV0_EPF2_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
+//BIF_CFG_DEV0_EPF2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
+//BIF_CFG_DEV0_EPF2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
+//BIF_CFG_DEV0_EPF2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
+//BIF_CFG_DEV0_EPF2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
+//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
+//BIF_CFG_DEV0_EPF2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
+//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                        0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                          0x00008000L
+//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                0xb
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                  0x00000800L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                          0x00001000L
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                               0x00000001L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                             0x00000002L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                            0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                  0x00000600L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                      0x07FF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                                0x00000300L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF3_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF3_COMMAND
+#define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
+#define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
+#define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                               0x6
+#define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING__SHIFT                                                         0x7
+#define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN__SHIFT                                                             0x8
+#define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS__SHIFT                                                             0xa
+#define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
+#define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
+#define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING_MASK                                                           0x0080L
+#define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN_MASK                                                               0x0100L
+#define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
+#define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS_MASK                                                               0x0400L
+//BIF_CFG_DEV0_EPF3_STATUS
+#define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST__SHIFT                                                             0x4
+#define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST_MASK                                                               0x0010L
+#define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF3_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
+//BIF_CFG_DEV0_EPF3_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF3_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF3_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF3_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
+//BIF_CFG_DEV0_EPF3_LATENCY
+#define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF3_HEADER
+#define BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE_MASK                                                            0x7FL
+#define BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE_MASK                                                            0x80L
+//BIF_CFG_DEV0_EPF3_BIST
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT__SHIFT                                                              0x6
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP__SHIFT                                                               0x7
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP_MASK                                                                0x0FL
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT_MASK                                                                0x40L
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP_MASK                                                                 0x80L
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
+//BIF_CFG_DEV0_EPF3_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF3_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
+//BIF_CFG_DEV0_EPF3_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF3_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
+//BIF_CFG_DEV0_EPF3_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF3_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION_MASK                                                               0x0007L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
+//BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF3_SBRN
+#define BIF_CFG_DEV0_EPF3_SBRN__SBRN__SHIFT                                                                   0x0
+#define BIF_CFG_DEV0_EPF3_SBRN__SBRN_MASK                                                                     0xFFL
+//BIF_CFG_DEV0_EPF3_FLADJ
+#define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF3_FLADJ__NFC__SHIFT                                                                   0x6
+#define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ_MASK                                                                   0x3FL
+#define BIF_CFG_DEV0_EPF3_FLADJ__NFC_MASK                                                                     0x40L
+//BIF_CFG_DEV0_EPF3_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
+//BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION_MASK                                                              0x000FL
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
+//BIF_CFG_DEV0_EPF3_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
+//BIF_CFG_DEV0_EPF3_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
+//BIF_CFG_DEV0_EPF3_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
+//BIF_CFG_DEV0_EPF3_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF3_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF3_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
+//BIF_CFG_DEV0_EPF3_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
+//BIF_CFG_DEV0_EPF3_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
+//BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
+//BIF_CFG_DEV0_EPF3_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
+//BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                        0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                          0x00008000L
+//BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                0xb
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                  0x00000800L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                          0x00001000L
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                               0x00000001L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                             0x00000002L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                            0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                  0x00000600L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                      0x07FF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                                0x00000300L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF4_VENDOR_ID
+#define BIF_CFG_DEV0_EPF4_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF4_DEVICE_ID
+#define BIF_CFG_DEV0_EPF4_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF4_COMMAND
+#define BIF_CFG_DEV0_EPF4_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
+#define BIF_CFG_DEV0_EPF4_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_EPF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF4_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
+#define BIF_CFG_DEV0_EPF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                               0x6
+#define BIF_CFG_DEV0_EPF4_COMMAND__AD_STEPPING__SHIFT                                                         0x7
+#define BIF_CFG_DEV0_EPF4_COMMAND__SERR_EN__SHIFT                                                             0x8
+#define BIF_CFG_DEV0_EPF4_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_EPF4_COMMAND__INT_DIS__SHIFT                                                             0xa
+#define BIF_CFG_DEV0_EPF4_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
+#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
+#define BIF_CFG_DEV0_EPF4_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_EPF4_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF4_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
+#define BIF_CFG_DEV0_EPF4_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_EPF4_COMMAND__AD_STEPPING_MASK                                                           0x0080L
+#define BIF_CFG_DEV0_EPF4_COMMAND__SERR_EN_MASK                                                               0x0100L
+#define BIF_CFG_DEV0_EPF4_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
+#define BIF_CFG_DEV0_EPF4_COMMAND__INT_DIS_MASK                                                               0x0400L
+//BIF_CFG_DEV0_EPF4_STATUS
+#define BIF_CFG_DEV0_EPF4_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_STATUS__INT_STATUS__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF4_STATUS__CAP_LIST__SHIFT                                                             0x4
+#define BIF_CFG_DEV0_EPF4_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIF_CFG_DEV0_EPF4_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF4_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF4_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF4_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF4_STATUS__INT_STATUS_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF4_STATUS__CAP_LIST_MASK                                                               0x0010L
+#define BIF_CFG_DEV0_EPF4_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIF_CFG_DEV0_EPF4_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF4_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIF_CFG_DEV0_EPF4_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIF_CFG_DEV0_EPF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF4_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF4_REVISION_ID
+#define BIF_CFG_DEV0_EPF4_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF4_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF4_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
+#define BIF_CFG_DEV0_EPF4_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
+//BIF_CFG_DEV0_EPF4_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF4_SUB_CLASS
+#define BIF_CFG_DEV0_EPF4_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF4_BASE_CLASS
+#define BIF_CFG_DEV0_EPF4_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF4_CACHE_LINE
+#define BIF_CFG_DEV0_EPF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
+//BIF_CFG_DEV0_EPF4_LATENCY
+#define BIF_CFG_DEV0_EPF4_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF4_HEADER
+#define BIF_CFG_DEV0_EPF4_HEADER__HEADER_TYPE__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF4_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_EPF4_HEADER__HEADER_TYPE_MASK                                                            0x7FL
+#define BIF_CFG_DEV0_EPF4_HEADER__DEVICE_TYPE_MASK                                                            0x80L
+//BIF_CFG_DEV0_EPF4_BIST
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_COMP__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_STRT__SHIFT                                                              0x6
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_CAP__SHIFT                                                               0x7
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_COMP_MASK                                                                0x0FL
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_STRT_MASK                                                                0x40L
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_CAP_MASK                                                                 0x80L
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_CAP_PTR
+#define BIF_CFG_DEV0_EPF4_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF4_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
+//BIF_CFG_DEV0_EPF4_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF4_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
+//BIF_CFG_DEV0_EPF4_MIN_GRANT
+#define BIF_CFG_DEV0_EPF4_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF4_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF4_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF4_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
+//BIF_CFG_DEV0_EPF4_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF4_PMI_CAP
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__VERSION_MASK                                                               0x0007L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
+//BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF4_SBRN
+#define BIF_CFG_DEV0_EPF4_SBRN__SBRN__SHIFT                                                                   0x0
+#define BIF_CFG_DEV0_EPF4_SBRN__SBRN_MASK                                                                     0xFFL
+//BIF_CFG_DEV0_EPF4_FLADJ
+#define BIF_CFG_DEV0_EPF4_FLADJ__FLADJ__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF4_FLADJ__NFC__SHIFT                                                                   0x6
+#define BIF_CFG_DEV0_EPF4_FLADJ__FLADJ_MASK                                                                   0x3FL
+#define BIF_CFG_DEV0_EPF4_FLADJ__NFC_MASK                                                                     0x40L
+//BIF_CFG_DEV0_EPF4_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
+//BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__VERSION__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__VERSION_MASK                                                              0x000FL
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
+//BIF_CFG_DEV0_EPF4_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
+//BIF_CFG_DEV0_EPF4_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF4_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
+//BIF_CFG_DEV0_EPF4_LINK_CAP
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
+//BIF_CFG_DEV0_EPF4_LINK_CNTL
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
+//BIF_CFG_DEV0_EPF4_LINK_STATUS
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF4_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF4_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
+//BIF_CFG_DEV0_EPF4_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF4_LINK_CAP2
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF4_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
+//BIF_CFG_DEV0_EPF4_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
+//BIF_CFG_DEV0_EPF4_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
+//BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_MASK
+#define BIF_CFG_DEV0_EPF4_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF4_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_PENDING
+#define BIF_CFG_DEV0_EPF4_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
+//BIF_CFG_DEV0_EPF4_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_MSIX_PBA
+#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
+#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
+//BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
+//BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
+//BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                        0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                          0x00008000L
+//BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                0xb
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                  0x00000800L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                          0x00001000L
+//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
+//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
+//BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
+//BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
+//BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                               0x00000001L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                             0x00000002L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                            0x00000100L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                  0x00000600L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                      0x07FF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                                0x00000300L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF5_VENDOR_ID
+#define BIF_CFG_DEV0_EPF5_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF5_DEVICE_ID
+#define BIF_CFG_DEV0_EPF5_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF5_COMMAND
+#define BIF_CFG_DEV0_EPF5_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
+#define BIF_CFG_DEV0_EPF5_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_EPF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF5_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
+#define BIF_CFG_DEV0_EPF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                               0x6
+#define BIF_CFG_DEV0_EPF5_COMMAND__AD_STEPPING__SHIFT                                                         0x7
+#define BIF_CFG_DEV0_EPF5_COMMAND__SERR_EN__SHIFT                                                             0x8
+#define BIF_CFG_DEV0_EPF5_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_EPF5_COMMAND__INT_DIS__SHIFT                                                             0xa
+#define BIF_CFG_DEV0_EPF5_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
+#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
+#define BIF_CFG_DEV0_EPF5_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_EPF5_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF5_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
+#define BIF_CFG_DEV0_EPF5_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_EPF5_COMMAND__AD_STEPPING_MASK                                                           0x0080L
+#define BIF_CFG_DEV0_EPF5_COMMAND__SERR_EN_MASK                                                               0x0100L
+#define BIF_CFG_DEV0_EPF5_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
+#define BIF_CFG_DEV0_EPF5_COMMAND__INT_DIS_MASK                                                               0x0400L
+//BIF_CFG_DEV0_EPF5_STATUS
+#define BIF_CFG_DEV0_EPF5_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_STATUS__INT_STATUS__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF5_STATUS__CAP_LIST__SHIFT                                                             0x4
+#define BIF_CFG_DEV0_EPF5_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIF_CFG_DEV0_EPF5_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF5_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF5_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF5_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF5_STATUS__INT_STATUS_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF5_STATUS__CAP_LIST_MASK                                                               0x0010L
+#define BIF_CFG_DEV0_EPF5_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIF_CFG_DEV0_EPF5_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF5_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIF_CFG_DEV0_EPF5_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIF_CFG_DEV0_EPF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF5_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF5_REVISION_ID
+#define BIF_CFG_DEV0_EPF5_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF5_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF5_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
+#define BIF_CFG_DEV0_EPF5_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
+//BIF_CFG_DEV0_EPF5_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF5_SUB_CLASS
+#define BIF_CFG_DEV0_EPF5_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF5_BASE_CLASS
+#define BIF_CFG_DEV0_EPF5_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF5_CACHE_LINE
+#define BIF_CFG_DEV0_EPF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
+//BIF_CFG_DEV0_EPF5_LATENCY
+#define BIF_CFG_DEV0_EPF5_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF5_HEADER
+#define BIF_CFG_DEV0_EPF5_HEADER__HEADER_TYPE__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF5_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_EPF5_HEADER__HEADER_TYPE_MASK                                                            0x7FL
+#define BIF_CFG_DEV0_EPF5_HEADER__DEVICE_TYPE_MASK                                                            0x80L
+//BIF_CFG_DEV0_EPF5_BIST
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_COMP__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_STRT__SHIFT                                                              0x6
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_CAP__SHIFT                                                               0x7
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_COMP_MASK                                                                0x0FL
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_STRT_MASK                                                                0x40L
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_CAP_MASK                                                                 0x80L
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_CAP_PTR
+#define BIF_CFG_DEV0_EPF5_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF5_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
+//BIF_CFG_DEV0_EPF5_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF5_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
+//BIF_CFG_DEV0_EPF5_MIN_GRANT
+#define BIF_CFG_DEV0_EPF5_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF5_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF5_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF5_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
+//BIF_CFG_DEV0_EPF5_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF5_PMI_CAP
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__VERSION_MASK                                                               0x0007L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
+//BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF5_SBRN
+#define BIF_CFG_DEV0_EPF5_SBRN__SBRN__SHIFT                                                                   0x0
+#define BIF_CFG_DEV0_EPF5_SBRN__SBRN_MASK                                                                     0xFFL
+//BIF_CFG_DEV0_EPF5_FLADJ
+#define BIF_CFG_DEV0_EPF5_FLADJ__FLADJ__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF5_FLADJ__NFC__SHIFT                                                                   0x6
+#define BIF_CFG_DEV0_EPF5_FLADJ__FLADJ_MASK                                                                   0x3FL
+#define BIF_CFG_DEV0_EPF5_FLADJ__NFC_MASK                                                                     0x40L
+//BIF_CFG_DEV0_EPF5_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
+//BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__VERSION__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__VERSION_MASK                                                              0x000FL
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
+//BIF_CFG_DEV0_EPF5_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
+//BIF_CFG_DEV0_EPF5_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF5_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
+//BIF_CFG_DEV0_EPF5_LINK_CAP
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
+//BIF_CFG_DEV0_EPF5_LINK_CNTL
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
+//BIF_CFG_DEV0_EPF5_LINK_STATUS
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF5_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF5_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
+//BIF_CFG_DEV0_EPF5_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF5_LINK_CAP2
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF5_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
+//BIF_CFG_DEV0_EPF5_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
+//BIF_CFG_DEV0_EPF5_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
+//BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_MASK
+#define BIF_CFG_DEV0_EPF5_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF5_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_PENDING
+#define BIF_CFG_DEV0_EPF5_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
+//BIF_CFG_DEV0_EPF5_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_MSIX_PBA
+#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
+#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
+//BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
+//BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
+//BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                        0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                          0x00008000L
+//BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                0xb
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                  0x00000800L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                          0x00001000L
+//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
+//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
+//BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
+//BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
+//BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                               0x00000001L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                             0x00000002L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                            0x00000100L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                  0x00000600L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                      0x07FF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                                0x00000300L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF6_VENDOR_ID
+#define BIF_CFG_DEV0_EPF6_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF6_DEVICE_ID
+#define BIF_CFG_DEV0_EPF6_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF6_COMMAND
+#define BIF_CFG_DEV0_EPF6_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
+#define BIF_CFG_DEV0_EPF6_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_EPF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF6_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
+#define BIF_CFG_DEV0_EPF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                               0x6
+#define BIF_CFG_DEV0_EPF6_COMMAND__AD_STEPPING__SHIFT                                                         0x7
+#define BIF_CFG_DEV0_EPF6_COMMAND__SERR_EN__SHIFT                                                             0x8
+#define BIF_CFG_DEV0_EPF6_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_EPF6_COMMAND__INT_DIS__SHIFT                                                             0xa
+#define BIF_CFG_DEV0_EPF6_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
+#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
+#define BIF_CFG_DEV0_EPF6_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_EPF6_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF6_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
+#define BIF_CFG_DEV0_EPF6_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_EPF6_COMMAND__AD_STEPPING_MASK                                                           0x0080L
+#define BIF_CFG_DEV0_EPF6_COMMAND__SERR_EN_MASK                                                               0x0100L
+#define BIF_CFG_DEV0_EPF6_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
+#define BIF_CFG_DEV0_EPF6_COMMAND__INT_DIS_MASK                                                               0x0400L
+//BIF_CFG_DEV0_EPF6_STATUS
+#define BIF_CFG_DEV0_EPF6_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_STATUS__INT_STATUS__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF6_STATUS__CAP_LIST__SHIFT                                                             0x4
+#define BIF_CFG_DEV0_EPF6_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIF_CFG_DEV0_EPF6_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF6_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF6_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF6_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF6_STATUS__INT_STATUS_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF6_STATUS__CAP_LIST_MASK                                                               0x0010L
+#define BIF_CFG_DEV0_EPF6_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIF_CFG_DEV0_EPF6_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF6_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIF_CFG_DEV0_EPF6_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIF_CFG_DEV0_EPF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF6_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF6_REVISION_ID
+#define BIF_CFG_DEV0_EPF6_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF6_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF6_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
+#define BIF_CFG_DEV0_EPF6_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
+//BIF_CFG_DEV0_EPF6_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF6_SUB_CLASS
+#define BIF_CFG_DEV0_EPF6_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF6_BASE_CLASS
+#define BIF_CFG_DEV0_EPF6_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF6_CACHE_LINE
+#define BIF_CFG_DEV0_EPF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
+//BIF_CFG_DEV0_EPF6_LATENCY
+#define BIF_CFG_DEV0_EPF6_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF6_HEADER
+#define BIF_CFG_DEV0_EPF6_HEADER__HEADER_TYPE__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF6_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_EPF6_HEADER__HEADER_TYPE_MASK                                                            0x7FL
+#define BIF_CFG_DEV0_EPF6_HEADER__DEVICE_TYPE_MASK                                                            0x80L
+//BIF_CFG_DEV0_EPF6_BIST
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_COMP__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_STRT__SHIFT                                                              0x6
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_CAP__SHIFT                                                               0x7
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_COMP_MASK                                                                0x0FL
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_STRT_MASK                                                                0x40L
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_CAP_MASK                                                                 0x80L
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_CAP_PTR
+#define BIF_CFG_DEV0_EPF6_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF6_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
+//BIF_CFG_DEV0_EPF6_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF6_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
+//BIF_CFG_DEV0_EPF6_MIN_GRANT
+#define BIF_CFG_DEV0_EPF6_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF6_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF6_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF6_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
+//BIF_CFG_DEV0_EPF6_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF6_PMI_CAP
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__VERSION_MASK                                                               0x0007L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
+//BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF6_SBRN
+#define BIF_CFG_DEV0_EPF6_SBRN__SBRN__SHIFT                                                                   0x0
+#define BIF_CFG_DEV0_EPF6_SBRN__SBRN_MASK                                                                     0xFFL
+//BIF_CFG_DEV0_EPF6_FLADJ
+#define BIF_CFG_DEV0_EPF6_FLADJ__FLADJ__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF6_FLADJ__NFC__SHIFT                                                                   0x6
+#define BIF_CFG_DEV0_EPF6_FLADJ__FLADJ_MASK                                                                   0x3FL
+#define BIF_CFG_DEV0_EPF6_FLADJ__NFC_MASK                                                                     0x40L
+//BIF_CFG_DEV0_EPF6_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESL__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESLD__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESL_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESLD_MASK                                                           0xF0L
+//BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__VERSION__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__VERSION_MASK                                                              0x000FL
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
+//BIF_CFG_DEV0_EPF6_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
+//BIF_CFG_DEV0_EPF6_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF6_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
+//BIF_CFG_DEV0_EPF6_LINK_CAP
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
+//BIF_CFG_DEV0_EPF6_LINK_CNTL
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
+//BIF_CFG_DEV0_EPF6_LINK_STATUS
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF6_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF6_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
+//BIF_CFG_DEV0_EPF6_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF6_LINK_CAP2
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF6_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
+//BIF_CFG_DEV0_EPF6_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
+//BIF_CFG_DEV0_EPF6_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
+//BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_MASK
+#define BIF_CFG_DEV0_EPF6_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF6_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_PENDING
+#define BIF_CFG_DEV0_EPF6_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
+//BIF_CFG_DEV0_EPF6_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_MSIX_PBA
+#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
+#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
+//BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
+//BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
+//BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                        0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                          0x00008000L
+//BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                0xb
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                  0x00000800L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                          0x00001000L
+//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
+//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
+//BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
+//BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
+//BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                               0x00000001L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                             0x00000002L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                            0x00000100L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                  0x00000600L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                      0x07FF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                                0x00000300L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                        0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                       0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                       0xFF00L
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+//BIFPLR0_VENDOR_ID
+#define BIFPLR0_VENDOR_ID__VENDOR_ID__SHIFT                                                                   0x0
+#define BIFPLR0_VENDOR_ID__VENDOR_ID_MASK                                                                     0xFFFFL
+//BIFPLR0_DEVICE_ID
+#define BIFPLR0_DEVICE_ID__DEVICE_ID__SHIFT                                                                   0x0
+#define BIFPLR0_DEVICE_ID__DEVICE_ID_MASK                                                                     0xFFFFL
+//BIFPLR0_COMMAND
+#define BIFPLR0_COMMAND__IO_ACCESS_EN__SHIFT                                                                  0x0
+#define BIFPLR0_COMMAND__MEM_ACCESS_EN__SHIFT                                                                 0x1
+#define BIFPLR0_COMMAND__BUS_MASTER_EN__SHIFT                                                                 0x2
+#define BIFPLR0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                              0x3
+#define BIFPLR0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                       0x4
+#define BIFPLR0_COMMAND__PAL_SNOOP_EN__SHIFT                                                                  0x5
+#define BIFPLR0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                         0x6
+#define BIFPLR0_COMMAND__AD_STEPPING__SHIFT                                                                   0x7
+#define BIFPLR0_COMMAND__SERR_EN__SHIFT                                                                       0x8
+#define BIFPLR0_COMMAND__FAST_B2B_EN__SHIFT                                                                   0x9
+#define BIFPLR0_COMMAND__INT_DIS__SHIFT                                                                       0xa
+#define BIFPLR0_COMMAND__IO_ACCESS_EN_MASK                                                                    0x0001L
+#define BIFPLR0_COMMAND__MEM_ACCESS_EN_MASK                                                                   0x0002L
+#define BIFPLR0_COMMAND__BUS_MASTER_EN_MASK                                                                   0x0004L
+#define BIFPLR0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                                0x0008L
+#define BIFPLR0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                         0x0010L
+#define BIFPLR0_COMMAND__PAL_SNOOP_EN_MASK                                                                    0x0020L
+#define BIFPLR0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                           0x0040L
+#define BIFPLR0_COMMAND__AD_STEPPING_MASK                                                                     0x0080L
+#define BIFPLR0_COMMAND__SERR_EN_MASK                                                                         0x0100L
+#define BIFPLR0_COMMAND__FAST_B2B_EN_MASK                                                                     0x0200L
+#define BIFPLR0_COMMAND__INT_DIS_MASK                                                                         0x0400L
+//BIFPLR0_STATUS
+#define BIFPLR0_STATUS__IMMEDIATE_READINESS__SHIFT                                                            0x0
+#define BIFPLR0_STATUS__INT_STATUS__SHIFT                                                                     0x3
+#define BIFPLR0_STATUS__CAP_LIST__SHIFT                                                                       0x4
+#define BIFPLR0_STATUS__PCI_66_CAP__SHIFT                                                                     0x5
+#define BIFPLR0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                              0x7
+#define BIFPLR0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                       0x8
+#define BIFPLR0_STATUS__DEVSEL_TIMING__SHIFT                                                                  0x9
+#define BIFPLR0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                            0xb
+#define BIFPLR0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                          0xc
+#define BIFPLR0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                          0xd
+#define BIFPLR0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                          0xe
+#define BIFPLR0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                          0xf
+#define BIFPLR0_STATUS__IMMEDIATE_READINESS_MASK                                                              0x0001L
+#define BIFPLR0_STATUS__INT_STATUS_MASK                                                                       0x0008L
+#define BIFPLR0_STATUS__CAP_LIST_MASK                                                                         0x0010L
+#define BIFPLR0_STATUS__PCI_66_CAP_MASK                                                                       0x0020L
+#define BIFPLR0_STATUS__FAST_BACK_CAPABLE_MASK                                                                0x0080L
+#define BIFPLR0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                         0x0100L
+#define BIFPLR0_STATUS__DEVSEL_TIMING_MASK                                                                    0x0600L
+#define BIFPLR0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                              0x0800L
+#define BIFPLR0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                            0x1000L
+#define BIFPLR0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                            0x2000L
+#define BIFPLR0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                            0x4000L
+#define BIFPLR0_STATUS__PARITY_ERROR_DETECTED_MASK                                                            0x8000L
+//BIFPLR0_REVISION_ID
+#define BIFPLR0_REVISION_ID__MINOR_REV_ID__SHIFT                                                              0x0
+#define BIFPLR0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                              0x4
+#define BIFPLR0_REVISION_ID__MINOR_REV_ID_MASK                                                                0x0FL
+#define BIFPLR0_REVISION_ID__MAJOR_REV_ID_MASK                                                                0xF0L
+//BIFPLR0_PROG_INTERFACE
+#define BIFPLR0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                         0x0
+#define BIFPLR0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                           0xFFL
+//BIFPLR0_SUB_CLASS
+#define BIFPLR0_SUB_CLASS__SUB_CLASS__SHIFT                                                                   0x0
+#define BIFPLR0_SUB_CLASS__SUB_CLASS_MASK                                                                     0xFFL
+//BIFPLR0_BASE_CLASS
+#define BIFPLR0_BASE_CLASS__BASE_CLASS__SHIFT                                                                 0x0
+#define BIFPLR0_BASE_CLASS__BASE_CLASS_MASK                                                                   0xFFL
+//BIFPLR0_CACHE_LINE
+#define BIFPLR0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                            0x0
+#define BIFPLR0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                              0xFFL
+//BIFPLR0_LATENCY
+#define BIFPLR0_LATENCY__LATENCY_TIMER__SHIFT                                                                 0x0
+#define BIFPLR0_LATENCY__LATENCY_TIMER_MASK                                                                   0xFFL
+//BIFPLR0_HEADER
+#define BIFPLR0_HEADER__HEADER_TYPE__SHIFT                                                                    0x0
+#define BIFPLR0_HEADER__DEVICE_TYPE__SHIFT                                                                    0x7
+#define BIFPLR0_HEADER__HEADER_TYPE_MASK                                                                      0x7FL
+#define BIFPLR0_HEADER__DEVICE_TYPE_MASK                                                                      0x80L
+//BIFPLR0_BIST
+#define BIFPLR0_BIST__BIST_COMP__SHIFT                                                                        0x0
+#define BIFPLR0_BIST__BIST_STRT__SHIFT                                                                        0x6
+#define BIFPLR0_BIST__BIST_CAP__SHIFT                                                                         0x7
+#define BIFPLR0_BIST__BIST_COMP_MASK                                                                          0x0FL
+#define BIFPLR0_BIST__BIST_STRT_MASK                                                                          0x40L
+#define BIFPLR0_BIST__BIST_CAP_MASK                                                                           0x80L
+//BIFPLR0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                    0x0
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                  0x8
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                    0x10
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                        0x18
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                      0x000000FFL
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                    0x0000FF00L
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                      0x00FF0000L
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                          0xFF000000L
+//BIFPLR0_IO_BASE_LIMIT
+#define BIFPLR0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                            0x0
+#define BIFPLR0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                                 0x4
+#define BIFPLR0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                           0x8
+#define BIFPLR0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                                0xc
+#define BIFPLR0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                              0x000FL
+#define BIFPLR0_IO_BASE_LIMIT__IO_BASE_MASK                                                                   0x00F0L
+#define BIFPLR0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                             0x0F00L
+#define BIFPLR0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                  0xF000L
+//BIFPLR0_SECONDARY_STATUS
+#define BIFPLR0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIFPLR0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIFPLR0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIFPLR0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIFPLR0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIFPLR0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIFPLR0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIFPLR0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIFPLR0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIFPLR0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIFPLR0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIFPLR0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIFPLR0_MEM_BASE_LIMIT
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                         0x4
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                         0x10
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                        0x14
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                            0x0000000FL
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                           0x0000FFF0L
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                           0x000F0000L
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                          0xFFF00000L
+//BIFPLR0_PREF_BASE_LIMIT
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                    0x0
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                   0x4
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                   0x10
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                  0x14
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                      0x0000000FL
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                     0x0000FFF0L
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                     0x000F0000L
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                    0xFFF00000L
+//BIFPLR0_PREF_BASE_UPPER
+#define BIFPLR0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                       0x0
+#define BIFPLR0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                         0xFFFFFFFFL
+//BIFPLR0_PREF_LIMIT_UPPER
+#define BIFPLR0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                     0x0
+#define BIFPLR0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_IO_BASE_LIMIT_HI
+#define BIFPLR0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                        0x0
+#define BIFPLR0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                       0x10
+#define BIFPLR0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                          0x0000FFFFL
+#define BIFPLR0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                         0xFFFF0000L
+//BIFPLR0_CAP_PTR
+#define BIFPLR0_CAP_PTR__CAP_PTR__SHIFT                                                                       0x0
+#define BIFPLR0_CAP_PTR__CAP_PTR_MASK                                                                         0xFFL
+//BIFPLR0_ROM_BASE_ADDR
+#define BIFPLR0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                               0x0
+#define BIFPLR0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR0_INTERRUPT_LINE
+#define BIFPLR0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                         0x0
+#define BIFPLR0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                           0xFFL
+//BIFPLR0_INTERRUPT_PIN
+#define BIFPLR0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                           0x0
+#define BIFPLR0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                             0xFFL
+//BIFPLR0_IRQ_BRIDGE_CNTL
+#define BIFPLR0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                    0x0
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                               0x1
+#define BIFPLR0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                                0x2
+#define BIFPLR0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                                0x3
+#define BIFPLR0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                               0x4
+#define BIFPLR0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                     0x5
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                   0x6
+#define BIFPLR0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                           0x7
+#define BIFPLR0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                                 0x8
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                               0x9
+#define BIFPLR0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                  0xa
+#define BIFPLR0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                             0xb
+#define BIFPLR0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                      0x0001L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                                 0x0002L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                  0x0004L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                  0x0008L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                                 0x0010L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                       0x0020L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                     0x0040L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                             0x0080L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                   0x0100L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                                 0x0200L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                    0x0400L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                               0x0800L
+//BIFPLR0_EXT_BRIDGE_CNTL
+#define BIFPLR0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                         0x0
+#define BIFPLR0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                           0x01L
+//BIFPLR0_VENDOR_CAP_LIST
+#define BIFPLR0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                                0x10
+#define BIFPLR0_VENDOR_CAP_LIST__CAP_ID_MASK                                                                  0x000000FFL
+#define BIFPLR0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                                0x0000FF00L
+#define BIFPLR0_VENDOR_CAP_LIST__LENGTH_MASK                                                                  0x00FF0000L
+//BIFPLR0_ADAPTER_ID_W
+#define BIFPLR0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                      0x0
+#define BIFPLR0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                             0x10
+#define BIFPLR0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                               0xFFFF0000L
+//BIFPLR0_PMI_CAP_LIST
+#define BIFPLR0_PMI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR0_PMI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR0_PMI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR0_PMI_CAP
+#define BIFPLR0_PMI_CAP__VERSION__SHIFT                                                                       0x0
+#define BIFPLR0_PMI_CAP__PME_CLOCK__SHIFT                                                                     0x3
+#define BIFPLR0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                           0x4
+#define BIFPLR0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                             0x5
+#define BIFPLR0_PMI_CAP__AUX_CURRENT__SHIFT                                                                   0x6
+#define BIFPLR0_PMI_CAP__D1_SUPPORT__SHIFT                                                                    0x9
+#define BIFPLR0_PMI_CAP__D2_SUPPORT__SHIFT                                                                    0xa
+#define BIFPLR0_PMI_CAP__PME_SUPPORT__SHIFT                                                                   0xb
+#define BIFPLR0_PMI_CAP__VERSION_MASK                                                                         0x0007L
+#define BIFPLR0_PMI_CAP__PME_CLOCK_MASK                                                                       0x0008L
+#define BIFPLR0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                             0x0010L
+#define BIFPLR0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                               0x0020L
+#define BIFPLR0_PMI_CAP__AUX_CURRENT_MASK                                                                     0x01C0L
+#define BIFPLR0_PMI_CAP__D1_SUPPORT_MASK                                                                      0x0200L
+#define BIFPLR0_PMI_CAP__D2_SUPPORT_MASK                                                                      0x0400L
+#define BIFPLR0_PMI_CAP__PME_SUPPORT_MASK                                                                     0xF800L
+//BIFPLR0_PMI_STATUS_CNTL
+#define BIFPLR0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                           0x0
+#define BIFPLR0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                         0x3
+#define BIFPLR0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                                0x8
+#define BIFPLR0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                           0x9
+#define BIFPLR0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                            0xd
+#define BIFPLR0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                            0xf
+#define BIFPLR0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                         0x16
+#define BIFPLR0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                            0x17
+#define BIFPLR0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                              0x18
+#define BIFPLR0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                             0x00000003L
+#define BIFPLR0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                           0x00000008L
+#define BIFPLR0_PMI_STATUS_CNTL__PME_EN_MASK                                                                  0x00000100L
+#define BIFPLR0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                             0x00001E00L
+#define BIFPLR0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                              0x00006000L
+#define BIFPLR0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                              0x00008000L
+#define BIFPLR0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                           0x00400000L
+#define BIFPLR0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                              0x00800000L
+#define BIFPLR0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                                0xFF000000L
+//BIFPLR0_PCIE_CAP_LIST
+#define BIFPLR0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR0_PCIE_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR0_PCIE_CAP
+#define BIFPLR0_PCIE_CAP__VERSION__SHIFT                                                                      0x0
+#define BIFPLR0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                  0x4
+#define BIFPLR0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                             0x8
+#define BIFPLR0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                              0x9
+#define BIFPLR0_PCIE_CAP__VERSION_MASK                                                                        0x000FL
+#define BIFPLR0_PCIE_CAP__DEVICE_TYPE_MASK                                                                    0x00F0L
+#define BIFPLR0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                               0x0100L
+#define BIFPLR0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                                0x3E00L
+//BIFPLR0_DEVICE_CAP
+#define BIFPLR0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                        0x0
+#define BIFPLR0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                               0x3
+#define BIFPLR0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                               0x5
+#define BIFPLR0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                     0x6
+#define BIFPLR0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                      0x9
+#define BIFPLR0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                   0xf
+#define BIFPLR0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                  0x12
+#define BIFPLR0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                  0x1a
+#define BIFPLR0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                                0x1c
+#define BIFPLR0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                          0x00000007L
+#define BIFPLR0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                                 0x00000018L
+#define BIFPLR0_DEVICE_CAP__EXTENDED_TAG_MASK                                                                 0x00000020L
+#define BIFPLR0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                       0x000001C0L
+#define BIFPLR0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                        0x00000E00L
+#define BIFPLR0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                     0x00008000L
+#define BIFPLR0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                    0x03FC0000L
+#define BIFPLR0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                    0x0C000000L
+#define BIFPLR0_DEVICE_CAP__FLR_CAPABLE_MASK                                                                  0x10000000L
+//BIFPLR0_DEVICE_CNTL
+#define BIFPLR0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                               0x0
+#define BIFPLR0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                          0x1
+#define BIFPLR0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                              0x2
+#define BIFPLR0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                             0x3
+#define BIFPLR0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                            0x4
+#define BIFPLR0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                          0x5
+#define BIFPLR0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                           0x8
+#define BIFPLR0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                           0x9
+#define BIFPLR0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                           0xa
+#define BIFPLR0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                               0xb
+#define BIFPLR0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                     0xc
+#define BIFPLR0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                       0xf
+#define BIFPLR0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                                 0x0001L
+#define BIFPLR0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                            0x0002L
+#define BIFPLR0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                                0x0004L
+#define BIFPLR0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                               0x0008L
+#define BIFPLR0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                              0x0010L
+#define BIFPLR0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                            0x00E0L
+#define BIFPLR0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                             0x0100L
+#define BIFPLR0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                             0x0200L
+#define BIFPLR0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                             0x0400L
+#define BIFPLR0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                                 0x0800L
+#define BIFPLR0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                       0x7000L
+#define BIFPLR0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                         0x8000L
+//BIFPLR0_DEVICE_STATUS
+#define BIFPLR0_DEVICE_STATUS__CORR_ERR__SHIFT                                                                0x0
+#define BIFPLR0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                           0x1
+#define BIFPLR0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                               0x2
+#define BIFPLR0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                            0x3
+#define BIFPLR0_DEVICE_STATUS__AUX_PWR__SHIFT                                                                 0x4
+#define BIFPLR0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                       0x5
+#define BIFPLR0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                           0x6
+#define BIFPLR0_DEVICE_STATUS__CORR_ERR_MASK                                                                  0x0001L
+#define BIFPLR0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                             0x0002L
+#define BIFPLR0_DEVICE_STATUS__FATAL_ERR_MASK                                                                 0x0004L
+#define BIFPLR0_DEVICE_STATUS__USR_DETECTED_MASK                                                              0x0008L
+#define BIFPLR0_DEVICE_STATUS__AUX_PWR_MASK                                                                   0x0010L
+#define BIFPLR0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                         0x0020L
+#define BIFPLR0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                             0x0040L
+//BIFPLR0_LINK_CAP
+#define BIFPLR0_LINK_CAP__LINK_SPEED__SHIFT                                                                   0x0
+#define BIFPLR0_LINK_CAP__LINK_WIDTH__SHIFT                                                                   0x4
+#define BIFPLR0_LINK_CAP__PM_SUPPORT__SHIFT                                                                   0xa
+#define BIFPLR0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                             0xc
+#define BIFPLR0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                              0xf
+#define BIFPLR0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                       0x12
+#define BIFPLR0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                  0x13
+#define BIFPLR0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                  0x14
+#define BIFPLR0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                     0x15
+#define BIFPLR0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                  0x16
+#define BIFPLR0_LINK_CAP__PORT_NUMBER__SHIFT                                                                  0x18
+#define BIFPLR0_LINK_CAP__LINK_SPEED_MASK                                                                     0x0000000FL
+#define BIFPLR0_LINK_CAP__LINK_WIDTH_MASK                                                                     0x000003F0L
+#define BIFPLR0_LINK_CAP__PM_SUPPORT_MASK                                                                     0x00000C00L
+#define BIFPLR0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                               0x00007000L
+#define BIFPLR0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                                0x00038000L
+#define BIFPLR0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                         0x00040000L
+#define BIFPLR0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                    0x00080000L
+#define BIFPLR0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                    0x00100000L
+#define BIFPLR0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                       0x00200000L
+#define BIFPLR0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                    0x00400000L
+#define BIFPLR0_LINK_CAP__PORT_NUMBER_MASK                                                                    0xFF000000L
+//BIFPLR0_LINK_CNTL
+#define BIFPLR0_LINK_CNTL__PM_CONTROL__SHIFT                                                                  0x0
+#define BIFPLR0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                           0x3
+#define BIFPLR0_LINK_CNTL__LINK_DIS__SHIFT                                                                    0x4
+#define BIFPLR0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                                0x5
+#define BIFPLR0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                            0x6
+#define BIFPLR0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                               0x7
+#define BIFPLR0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                   0x8
+#define BIFPLR0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                                 0x9
+#define BIFPLR0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                   0xa
+#define BIFPLR0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                   0xb
+#define BIFPLR0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                       0xe
+#define BIFPLR0_LINK_CNTL__PM_CONTROL_MASK                                                                    0x0003L
+#define BIFPLR0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                             0x0008L
+#define BIFPLR0_LINK_CNTL__LINK_DIS_MASK                                                                      0x0010L
+#define BIFPLR0_LINK_CNTL__RETRAIN_LINK_MASK                                                                  0x0020L
+#define BIFPLR0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                              0x0040L
+#define BIFPLR0_LINK_CNTL__EXTENDED_SYNC_MASK                                                                 0x0080L
+#define BIFPLR0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                     0x0100L
+#define BIFPLR0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                   0x0200L
+#define BIFPLR0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                     0x0400L
+#define BIFPLR0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                     0x0800L
+#define BIFPLR0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                         0xC000L
+//BIFPLR0_LINK_STATUS
+#define BIFPLR0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                     0x4
+#define BIFPLR0_LINK_STATUS__LINK_TRAINING__SHIFT                                                             0xb
+#define BIFPLR0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                            0xc
+#define BIFPLR0_LINK_STATUS__DL_ACTIVE__SHIFT                                                                 0xd
+#define BIFPLR0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                                 0xe
+#define BIFPLR0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                                 0xf
+#define BIFPLR0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                       0x03F0L
+#define BIFPLR0_LINK_STATUS__LINK_TRAINING_MASK                                                               0x0800L
+#define BIFPLR0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                              0x1000L
+#define BIFPLR0_LINK_STATUS__DL_ACTIVE_MASK                                                                   0x2000L
+#define BIFPLR0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                   0x4000L
+#define BIFPLR0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                   0x8000L
+//BIFPLR0_SLOT_CAP
+#define BIFPLR0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                          0x0
+#define BIFPLR0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                       0x1
+#define BIFPLR0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                           0x2
+#define BIFPLR0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                       0x3
+#define BIFPLR0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                        0x4
+#define BIFPLR0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                             0x5
+#define BIFPLR0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                              0x6
+#define BIFPLR0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                         0x7
+#define BIFPLR0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                         0xf
+#define BIFPLR0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                                0x11
+#define BIFPLR0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                               0x12
+#define BIFPLR0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                            0x13
+#define BIFPLR0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                            0x00000001L
+#define BIFPLR0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                         0x00000002L
+#define BIFPLR0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                             0x00000004L
+#define BIFPLR0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                         0x00000008L
+#define BIFPLR0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                          0x00000010L
+#define BIFPLR0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                               0x00000020L
+#define BIFPLR0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                                0x00000040L
+#define BIFPLR0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                           0x00007F80L
+#define BIFPLR0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                           0x00018000L
+#define BIFPLR0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                  0x00020000L
+#define BIFPLR0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                                 0x00040000L
+#define BIFPLR0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                              0xFFF80000L
+//BIFPLR0_SLOT_CNTL
+#define BIFPLR0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                      0x0
+#define BIFPLR0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                       0x1
+#define BIFPLR0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                       0x2
+#define BIFPLR0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                  0x3
+#define BIFPLR0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                   0x4
+#define BIFPLR0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                             0x5
+#define BIFPLR0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                         0x6
+#define BIFPLR0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                          0x8
+#define BIFPLR0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                         0xa
+#define BIFPLR0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                  0xb
+#define BIFPLR0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                         0xc
+#define BIFPLR0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                                 0xd
+#define BIFPLR0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                        0x0001L
+#define BIFPLR0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                         0x0002L
+#define BIFPLR0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                         0x0004L
+#define BIFPLR0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                    0x0008L
+#define BIFPLR0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                     0x0010L
+#define BIFPLR0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                               0x0020L
+#define BIFPLR0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                           0x00C0L
+#define BIFPLR0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                            0x0300L
+#define BIFPLR0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                           0x0400L
+#define BIFPLR0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                    0x0800L
+#define BIFPLR0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                           0x1000L
+#define BIFPLR0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                   0x2000L
+//BIFPLR0_SLOT_STATUS
+#define BIFPLR0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                       0x0
+#define BIFPLR0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                        0x1
+#define BIFPLR0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                        0x2
+#define BIFPLR0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                   0x3
+#define BIFPLR0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                         0x4
+#define BIFPLR0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                          0x5
+#define BIFPLR0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                     0x6
+#define BIFPLR0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                              0x7
+#define BIFPLR0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                          0x8
+#define BIFPLR0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                         0x0001L
+#define BIFPLR0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                          0x0002L
+#define BIFPLR0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                          0x0004L
+#define BIFPLR0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                     0x0008L
+#define BIFPLR0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                           0x0010L
+#define BIFPLR0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                            0x0020L
+#define BIFPLR0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                       0x0040L
+#define BIFPLR0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                                0x0080L
+#define BIFPLR0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                            0x0100L
+//BIFPLR0_ROOT_CNTL
+#define BIFPLR0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                         0x0
+#define BIFPLR0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                     0x1
+#define BIFPLR0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                        0x2
+#define BIFPLR0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                             0x3
+#define BIFPLR0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                  0x4
+#define BIFPLR0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                           0x0001L
+#define BIFPLR0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                       0x0002L
+#define BIFPLR0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                          0x0004L
+#define BIFPLR0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                               0x0008L
+#define BIFPLR0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                    0x0010L
+//BIFPLR0_ROOT_CAP
+#define BIFPLR0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                      0x0
+#define BIFPLR0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                        0x0001L
+//BIFPLR0_ROOT_STATUS
+#define BIFPLR0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                          0x0
+#define BIFPLR0_ROOT_STATUS__PME_STATUS__SHIFT                                                                0x10
+#define BIFPLR0_ROOT_STATUS__PME_PENDING__SHIFT                                                               0x11
+#define BIFPLR0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR0_ROOT_STATUS__PME_STATUS_MASK                                                                  0x00010000L
+#define BIFPLR0_ROOT_STATUS__PME_PENDING_MASK                                                                 0x00020000L
+//BIFPLR0_DEVICE_CAP2
+#define BIFPLR0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                               0x0
+#define BIFPLR0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                                 0x4
+#define BIFPLR0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                  0x5
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                                0x6
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                                0x7
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                                0x8
+#define BIFPLR0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                    0x9
+#define BIFPLR0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                                 0xa
+#define BIFPLR0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                             0xb
+#define BIFPLR0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                        0xc
+#define BIFPLR0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                             0xe
+#define BIFPLR0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                           0x10
+#define BIFPLR0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                           0x11
+#define BIFPLR0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                            0x12
+#define BIFPLR0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                              0x14
+#define BIFPLR0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                              0x15
+#define BIFPLR0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                  0x16
+#define BIFPLR0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                            0x18
+#define BIFPLR0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                             0x1a
+#define BIFPLR0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                                 0x0000000FL
+#define BIFPLR0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                   0x00000010L
+#define BIFPLR0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                    0x00000020L
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                  0x00000040L
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                  0x00000080L
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                  0x00000100L
+#define BIFPLR0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                      0x00000200L
+#define BIFPLR0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                   0x00000400L
+#define BIFPLR0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                               0x00000800L
+#define BIFPLR0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                          0x00003000L
+#define BIFPLR0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                               0x0000C000L
+#define BIFPLR0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                             0x00010000L
+#define BIFPLR0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                             0x00020000L
+#define BIFPLR0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                              0x000C0000L
+#define BIFPLR0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                                0x00100000L
+#define BIFPLR0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                                0x00200000L
+#define BIFPLR0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                    0x00C00000L
+#define BIFPLR0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                              0x03000000L
+#define BIFPLR0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                               0x04000000L
+#define BIFPLR0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR0_DEVICE_CNTL2
+#define BIFPLR0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                        0x0
+#define BIFPLR0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                          0x4
+#define BIFPLR0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                        0x5
+#define BIFPLR0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                      0x6
+#define BIFPLR0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                                 0x7
+#define BIFPLR0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                       0x8
+#define BIFPLR0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                    0x9
+#define BIFPLR0_DEVICE_CNTL2__LTR_EN__SHIFT                                                                   0xa
+#define BIFPLR0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                             0xb
+#define BIFPLR0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                             0xc
+#define BIFPLR0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                  0xd
+#define BIFPLR0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                              0xf
+#define BIFPLR0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                          0x000FL
+#define BIFPLR0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                            0x0010L
+#define BIFPLR0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                          0x0020L
+#define BIFPLR0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                        0x0040L
+#define BIFPLR0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                   0x0080L
+#define BIFPLR0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                         0x0100L
+#define BIFPLR0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                      0x0200L
+#define BIFPLR0_DEVICE_CNTL2__LTR_EN_MASK                                                                     0x0400L
+#define BIFPLR0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                               0x0800L
+#define BIFPLR0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                               0x1000L
+#define BIFPLR0_DEVICE_CNTL2__OBFF_EN_MASK                                                                    0x6000L
+#define BIFPLR0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                                0x8000L
+//BIFPLR0_DEVICE_STATUS2
+#define BIFPLR0_DEVICE_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR0_DEVICE_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR0_LINK_CAP2
+#define BIFPLR0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                        0x1
+#define BIFPLR0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                         0x8
+#define BIFPLR0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                    0x10
+#define BIFPLR0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                   0x17
+#define BIFPLR0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                   0x18
+#define BIFPLR0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                               0x1f
+#define BIFPLR0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                          0x000000FEL
+#define BIFPLR0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                           0x00000100L
+#define BIFPLR0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                      0x007F0000L
+#define BIFPLR0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                     0x00800000L
+#define BIFPLR0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                     0x01000000L
+#define BIFPLR0_LINK_CAP2__DRS_SUPPORTED_MASK                                                                 0x80000000L
+//BIFPLR0_LINK_CNTL2
+#define BIFPLR0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                          0x0
+#define BIFPLR0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                           0x4
+#define BIFPLR0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                                0x5
+#define BIFPLR0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                      0x6
+#define BIFPLR0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                                0x7
+#define BIFPLR0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                       0xa
+#define BIFPLR0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                             0xb
+#define BIFPLR0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                      0xc
+#define BIFPLR0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                            0x000FL
+#define BIFPLR0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                             0x0010L
+#define BIFPLR0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                  0x0020L
+#define BIFPLR0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                        0x0040L
+#define BIFPLR0_LINK_CNTL2__XMIT_MARGIN_MASK                                                                  0x0380L
+#define BIFPLR0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                         0x0400L
+#define BIFPLR0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                               0x0800L
+#define BIFPLR0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                        0xF000L
+//BIFPLR0_LINK_STATUS2
+#define BIFPLR0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                     0x0
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                                0x1
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                          0x2
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                          0x3
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                          0x4
+#define BIFPLR0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                            0x5
+#define BIFPLR0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                        0x6
+#define BIFPLR0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                        0x7
+#define BIFPLR0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                     0x8
+#define BIFPLR0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                            0xc
+#define BIFPLR0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                     0xf
+#define BIFPLR0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                       0x0001L
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                  0x0002L
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                            0x0004L
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                            0x0008L
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                            0x0010L
+#define BIFPLR0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                              0x0020L
+#define BIFPLR0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                          0x0040L
+#define BIFPLR0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                          0x0080L
+#define BIFPLR0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                       0x0300L
+#define BIFPLR0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                              0x7000L
+#define BIFPLR0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                       0x8000L
+//BIFPLR0_SLOT_CAP2
+#define BIFPLR0_SLOT_CAP2__RESERVED__SHIFT                                                                    0x0
+#define BIFPLR0_SLOT_CAP2__RESERVED_MASK                                                                      0xFFFFFFFFL
+//BIFPLR0_SLOT_CNTL2
+#define BIFPLR0_SLOT_CNTL2__RESERVED__SHIFT                                                                   0x0
+#define BIFPLR0_SLOT_CNTL2__RESERVED_MASK                                                                     0xFFFFL
+//BIFPLR0_SLOT_STATUS2
+#define BIFPLR0_SLOT_STATUS2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR0_SLOT_STATUS2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR0_MSI_CAP_LIST
+#define BIFPLR0_MSI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR0_MSI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR0_MSI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR0_MSI_MSG_CNTL
+#define BIFPLR0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                   0x0
+#define BIFPLR0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                            0x1
+#define BIFPLR0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                             0x4
+#define BIFPLR0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                                0x7
+#define BIFPLR0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                                0x8
+#define BIFPLR0_MSI_MSG_CNTL__MSI_EN_MASK                                                                     0x0001L
+#define BIFPLR0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                              0x000EL
+#define BIFPLR0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                               0x0070L
+#define BIFPLR0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                  0x0080L
+#define BIFPLR0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                  0x0100L
+//BIFPLR0_MSI_MSG_ADDR_LO
+#define BIFPLR0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                       0x2
+#define BIFPLR0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                         0xFFFFFFFCL
+//BIFPLR0_MSI_MSG_ADDR_HI
+#define BIFPLR0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                       0x0
+#define BIFPLR0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                         0xFFFFFFFFL
+//BIFPLR0_MSI_MSG_DATA
+#define BIFPLR0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                                 0x0
+#define BIFPLR0_MSI_MSG_DATA__MSI_DATA_MASK                                                                   0xFFFFL
+//BIFPLR0_MSI_MSG_DATA_64
+#define BIFPLR0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                           0x0
+#define BIFPLR0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                             0xFFFFL
+//BIFPLR0_SSID_CAP_LIST
+#define BIFPLR0_SSID_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR0_SSID_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR0_SSID_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR0_SSID_CAP
+#define BIFPLR0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                          0x0
+#define BIFPLR0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                                 0x10
+#define BIFPLR0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR0_SSID_CAP__SUBSYSTEM_ID_MASK                                                                   0xFFFF0000L
+//BIFPLR0_MSI_MAP_CAP_LIST
+#define BIFPLR0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                               0x0
+#define BIFPLR0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                             0x8
+#define BIFPLR0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                                 0x00FFL
+#define BIFPLR0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                               0xFF00L
+//BIFPLR0_MSI_MAP_CAP
+#define BIFPLR0_MSI_MAP_CAP__EN__SHIFT                                                                        0x0
+#define BIFPLR0_MSI_MAP_CAP__FIXD__SHIFT                                                                      0x1
+#define BIFPLR0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                  0xb
+#define BIFPLR0_MSI_MAP_CAP__EN_MASK                                                                          0x0001L
+#define BIFPLR0_MSI_MAP_CAP__FIXD_MASK                                                                        0x0002L
+#define BIFPLR0_MSI_MAP_CAP__CAP_TYPE_MASK                                                                    0xF800L
+//BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                      0x0
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                     0x10
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                  0x14
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                       0x000F0000L
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                    0xFFF00000L
+//BIFPLR0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                       0x4
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                         0x8
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                       0xa
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                      0x00000007L
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                         0x00000070L
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                           0x00000300L
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                         0x00000C00L
+//BIFPLR0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                      0x0
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                             0x18
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                        0x000000FFL
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                               0xFF000000L
+//BIFPLR0_PCIE_PORT_VC_CNTL
+#define BIFPLR0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                   0x0
+#define BIFPLR0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                       0x1
+#define BIFPLR0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                     0x0001L
+#define BIFPLR0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                         0x000EL
+//BIFPLR0_PCIE_PORT_VC_STATUS
+#define BIFPLR0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                               0x0
+#define BIFPLR0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                                 0x0001L
+//BIFPLR0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIFPLR0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                              0x0
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                                0xFFFFFFFFL
+//BIFPLR0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                              0x0
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                                0xFFFFFFFFL
+//BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                                 0x4
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                              0x5
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                                 0xc
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                  0xd
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                             0xe
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                           0xf
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                               0x10
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                                0x11
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                                 0x12
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                                0x13
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                          0x14
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                           0x15
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                          0x16
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                          0x17
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                                 0x18
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                  0x19
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                             0x1a
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                   0x00000010L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                                0x00000020L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                   0x00001000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                    0x00002000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                               0x00004000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                             0x00008000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                                 0x00010000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                  0x00020000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                   0x00040000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                  0x00080000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                            0x00100000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                             0x00200000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                            0x00400000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                            0x00800000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                   0x01000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                    0x02000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                               0x04000000L
+//BIFPLR0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                     0x4
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                  0x5
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                     0xc
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                      0xd
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                                 0xe
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                               0xf
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                   0x10
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                    0x11
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                     0x12
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                    0x13
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                              0x14
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                               0x15
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                              0x16
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                              0x17
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                     0x18
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                      0x19
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                                 0x1a
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                       0x00000010L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                    0x00000020L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                       0x00001000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                        0x00002000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                   0x00004000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                                 0x00008000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                     0x00010000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                      0x00020000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                       0x00040000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                      0x00080000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                                0x00100000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                                 0x00200000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                                0x00400000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                                0x00800000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                       0x01000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                        0x02000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                   0x04000000L
+//BIFPLR0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                             0x4
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                          0x5
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                             0xc
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                              0xd
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                         0xe
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                       0xf
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                           0x10
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                            0x11
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                             0x12
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                            0x13
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                      0x14
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                       0x15
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                      0x16
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                      0x17
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                             0x18
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                              0x19
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                         0x1a
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                               0x00000010L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                            0x00000020L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                               0x00001000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                                0x00002000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                           0x00004000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                         0x00008000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                             0x00010000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                              0x00020000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                               0x00040000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                              0x00080000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                        0x00100000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                         0x00200000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                        0x00400000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                        0x00800000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                               0x01000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                                0x02000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                           0x04000000L
+//BIFPLR0_PCIE_CORR_ERR_STATUS
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                   0x0
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                   0x6
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                  0x7
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                       0x8
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                      0xc
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                     0xd
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                              0xe
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                              0xf
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                     0x00000001L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                     0x00000040L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                    0x00000080L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                         0x00000100L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                        0x00001000L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                       0x00002000L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                                0x00004000L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                                0x00008000L
+//BIFPLR0_PCIE_CORR_ERR_MASK
+#define BIFPLR0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                       0x0
+#define BIFPLR0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                       0x6
+#define BIFPLR0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                      0x7
+#define BIFPLR0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                           0x8
+#define BIFPLR0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                          0xc
+#define BIFPLR0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                         0xd
+#define BIFPLR0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                  0xe
+#define BIFPLR0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                  0xf
+#define BIFPLR0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                         0x00000001L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                         0x00000040L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                        0x00000080L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                             0x00000100L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                            0x00001000L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                           0x00002000L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                    0x00004000L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                    0x00008000L
+//BIFPLR0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                   0x0
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                  0x7
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                   0x8
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                              0x9
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                               0xa
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                          0xb
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                  0xc
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                     0x0000001FL
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                    0x00000080L
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                     0x00000100L
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                                0x00000200L
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                                 0x00000400L
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                            0x00000800L
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                    0x00001000L
+//BIFPLR0_PCIE_HDR_LOG0
+#define BIFPLR0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR0_PCIE_HDR_LOG1
+#define BIFPLR0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR0_PCIE_HDR_LOG2
+#define BIFPLR0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR0_PCIE_HDR_LOG3
+#define BIFPLR0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR0_PCIE_ROOT_ERR_CMD
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                     0x0
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                                 0x1
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                    0x2
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                       0x00000001L
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                   0x00000002L
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                      0x00000004L
+//BIFPLR0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                               0x1
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                          0x2
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                     0x3
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                        0x4
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                          0x5
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                             0x6
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                              0x1b
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                      0x00000001L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                                 0x00000002L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                            0x00000004L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                       0x00000008L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                          0x00000010L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                            0x00000020L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                               0x00000040L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                                0xF8000000L
+//BIFPLR0_PCIE_ERR_SRC_ID
+#define BIFPLR0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                       0x0
+#define BIFPLR0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                             0x10
+#define BIFPLR0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                               0xFFFF0000L
+//BIFPLR0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR0_PCIE_LINK_CNTL3
+#define BIFPLR0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                  0x0
+#define BIFPLR0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                          0x1
+#define BIFPLR0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                    0x00000001L
+#define BIFPLR0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                            0x00000002L
+//BIFPLR0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                         0x0
+#define BIFPLR0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                           0x0000FFFFL
+//BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR0_PCIE_ACS_CAP
+#define BIFPLR0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                        0x0
+#define BIFPLR0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                     0x1
+#define BIFPLR0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                     0x2
+#define BIFPLR0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                  0x3
+#define BIFPLR0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                      0x4
+#define BIFPLR0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                       0x5
+#define BIFPLR0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                    0x6
+#define BIFPLR0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                               0x8
+#define BIFPLR0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                          0x0001L
+#define BIFPLR0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                       0x0002L
+#define BIFPLR0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                       0x0004L
+#define BIFPLR0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                    0x0008L
+#define BIFPLR0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                        0x0010L
+#define BIFPLR0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                         0x0020L
+#define BIFPLR0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                      0x0040L
+#define BIFPLR0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                                 0xFF00L
+//BIFPLR0_PCIE_ACS_CNTL
+#define BIFPLR0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                                 0x1
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                                 0x2
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                              0x3
+#define BIFPLR0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                  0x4
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                   0x5
+#define BIFPLR0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                                0x6
+#define BIFPLR0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                      0x0001L
+#define BIFPLR0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                   0x0002L
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                   0x0004L
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                                0x0008L
+#define BIFPLR0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                    0x0010L
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                     0x0020L
+#define BIFPLR0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                  0x0040L
+//BIFPLR0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR0_PCIE_MC_CAP
+#define BIFPLR0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                              0x0
+#define BIFPLR0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                           0x8
+#define BIFPLR0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                        0xf
+#define BIFPLR0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                                0x003FL
+#define BIFPLR0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                             0x3F00L
+#define BIFPLR0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                          0x8000L
+//BIFPLR0_PCIE_MC_CNTL
+#define BIFPLR0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                             0x0
+#define BIFPLR0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                                0xf
+#define BIFPLR0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                               0x003FL
+#define BIFPLR0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                  0x8000L
+//BIFPLR0_PCIE_MC_ADDR0
+#define BIFPLR0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                            0x0
+#define BIFPLR0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                          0xc
+#define BIFPLR0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                              0x0000003FL
+#define BIFPLR0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                            0xFFFFF000L
+//BIFPLR0_PCIE_MC_ADDR1
+#define BIFPLR0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                          0x0
+#define BIFPLR0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                            0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_RCV0
+#define BIFPLR0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                             0x0
+#define BIFPLR0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                               0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_RCV1
+#define BIFPLR0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                             0x0
+#define BIFPLR0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                               0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                     0x0
+#define BIFPLR0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                     0x0
+#define BIFPLR0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                  0x0
+#define BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                    0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                  0x0
+#define BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                    0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                  0x0
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                                 0x6
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                    0x0000003FL
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                   0xFFFFFFC0L
+//BIFPLR0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                                 0x0
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                   0xFFFFFFFFL
+//BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                              0x0
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                              0x1
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                                0x2
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                                0x3
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                                0x4
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                               0x8
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                              0x10
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                              0x13
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                                0x00000001L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                                0x00000002L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                  0x00000004L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                  0x00000008L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                  0x00000010L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                                 0x0000FF00L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                                0x00030000L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                                0x00F80000L
+//BIFPLR0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                    0x1
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                      0x2
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                      0x3
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                          0x8
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                          0x1d
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                      0x00000001L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                      0x00000002L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                        0x00000004L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                        0x00000008L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                            0x0000FF00L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                            0xE0000000L
+//BIFPLR0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                                 0x0
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                                 0x3
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                   0x00000003L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                   0x000000F8L
+//BIFPLR0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR0_PCIE_DPC_CAP_LIST
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                               0x5
+#define BIFPLR0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                              0x6
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                   0x7
+#define BIFPLR0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                     0x8
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                               0xc
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                      0x001FL
+#define BIFPLR0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                                 0x0020L
+#define BIFPLR0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                                0x0040L
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                     0x0080L
+#define BIFPLR0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                       0x0F00L
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                                 0x1000L
+//BIFPLR0_PCIE_DPC_CNTL
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                      0x0
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                  0x2
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                    0x3
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                      0x4
+#define BIFPLR0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                     0x5
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                    0x6
+#define BIFPLR0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                                0x7
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                        0x0003L
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                    0x0004L
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                      0x0008L
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                        0x0010L
+#define BIFPLR0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                       0x0020L
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                      0x0040L
+#define BIFPLR0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                  0x0080L
+//BIFPLR0_PCIE_DPC_STATUS
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                    0x1
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                  0x3
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                           0x4
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                          0x5
+#define BIFPLR0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                            0x8
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                      0x0001L
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                      0x0006L
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                    0x0008L
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                             0x0010L
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                            0x0060L
+#define BIFPLR0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                              0x1F00L
+//BIFPLR0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                          0x0
+#define BIFPLR0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                            0xFFFFL
+//BIFPLR0_PCIE_RP_PIO_STATUS
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR0_PCIE_RP_PIO_MASK
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                           0x0
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                           0x1
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                              0x2
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                            0x8
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                            0x9
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                               0xa
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                           0x10
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                           0x11
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                              0x12
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                             0x00000001L
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                             0x00000002L
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                                0x00000004L
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                              0x00000100L
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                              0x00000200L
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                                 0x00000400L
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                             0x00010000L
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                             0x00020000L
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                                0x00040000L
+//BIFPLR0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                      0x0
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                      0x1
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                         0x2
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                       0x8
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                       0x9
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                          0xa
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                      0x10
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                      0x11
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                         0x12
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                        0x00000001L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                        0x00000002L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                           0x00000004L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                         0x00000100L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                         0x00000200L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                            0x00000400L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                        0x00010000L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                        0x00020000L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                           0x00040000L
+//BIFPLR0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR0_PCIE_ESM_CAP_LIST
+#define BIFPLR0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                             0x10
+#define BIFPLR0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                            0x14
+#define BIFPLR0_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                                0x0000FFFFL
+#define BIFPLR0_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                               0x000F0000L
+#define BIFPLR0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                              0xFFF00000L
+//BIFPLR0_PCIE_ESM_HEADER_1
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                       0x0
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                         0x10
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                         0x14
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                           0x000F0000L
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                           0xFFF00000L
+//BIFPLR0_PCIE_ESM_HEADER_2
+#define BIFPLR0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR0_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                                0xFFFFL
+//BIFPLR0_PCIE_ESM_STATUS
+#define BIFPLR0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                  0x9
+#define BIFPLR0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                      0x01FFL
+#define BIFPLR0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                    0x0E00L
+//BIFPLR0_PCIE_ESM_CTRL
+#define BIFPLR0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                             0xf
+#define BIFPLR0_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                               0x8000L
+//BIFPLR0_PCIE_ESM_CAP_1
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                               0x0
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                               0x1
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                               0x2
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                               0x3
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                               0x4
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                               0x5
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                               0x6
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                               0x7
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                               0x8
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                               0x9
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                               0xa
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                               0xb
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                               0xc
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                               0xd
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                               0xe
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                               0xf
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                               0x10
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                               0x11
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                               0x12
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                               0x13
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                              0x14
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                              0x15
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                              0x16
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                              0x17
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                              0x18
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                              0x19
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                              0x1a
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                              0x1b
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                              0x1c
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                              0x1d
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                                 0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                                 0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                                 0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                                 0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                                 0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                                 0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                                 0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                                 0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                                 0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                                 0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                                 0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                                 0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                                 0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                                 0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                                 0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                                 0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                                 0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                                 0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                                 0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                                 0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                                0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                                0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                                0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                                0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                                0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                                0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                                0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                                0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                                0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                                0x20000000L
+//BIFPLR0_PCIE_ESM_CAP_2
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                              0x0
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                              0x1
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                              0x2
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                              0x3
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                              0x4
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                              0x5
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                              0x6
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                              0x7
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                              0x8
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                              0x9
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                              0xa
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                              0xb
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                              0xc
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                              0xd
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                              0xe
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                              0xf
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                              0x10
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                              0x11
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                              0x12
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                              0x13
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                              0x14
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                              0x15
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                              0x16
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                              0x17
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                              0x18
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                              0x19
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                              0x1a
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                              0x1b
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                              0x1c
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                              0x1d
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                                0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                                0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                                0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                                0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                                0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                                0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                                0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                                0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                                0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                                0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                                0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                                0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                                0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                                0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                                0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                                0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                                0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                                0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                                0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                                0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                                0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                                0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                                0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                                0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                                0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                                0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                                0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                                0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                                0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                                0x20000000L
+//BIFPLR0_PCIE_ESM_CAP_3
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                              0x0
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                              0x1
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                              0x2
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                              0x3
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                              0x4
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                              0x5
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                              0x6
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                              0x7
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                              0x8
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                              0x9
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                              0xa
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                              0xb
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                              0xc
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                              0xd
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                              0xe
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                              0xf
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                              0x10
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                              0x11
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                              0x12
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                              0x13
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                                0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                                0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                                0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                                0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                                0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                                0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                                0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                                0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                                0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                                0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                                0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                                0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                                0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                                0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                                0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                                0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                                0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                                0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                                0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                                0x00080000L
+//BIFPLR0_PCIE_ESM_CAP_4
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                              0x0
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                              0x1
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                              0x2
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                              0x3
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                              0x4
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                              0x5
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                              0x6
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                              0x7
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                              0x8
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                              0x9
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                              0xa
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                              0xb
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                              0xc
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                              0xd
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                              0xe
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                              0xf
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                              0x10
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                              0x11
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                              0x12
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                              0x13
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                              0x14
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                              0x15
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                              0x16
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                              0x17
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                              0x18
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                              0x19
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                              0x1a
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                              0x1b
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                              0x1c
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                              0x1d
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                                0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                                0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                                0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                                0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                                0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                                0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                                0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                                0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                                0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                                0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                                0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                                0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                                0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                                0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                                0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                                0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                                0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                                0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                                0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                                0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                                0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                                0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                                0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                                0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                                0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                                0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                                0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                                0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                                0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                                0x20000000L
+//BIFPLR0_PCIE_ESM_CAP_5
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                              0x0
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                              0x1
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                              0x2
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                              0x3
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                              0x4
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                              0x5
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                              0x6
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                              0x7
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                              0x8
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                              0x9
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                              0xa
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                              0xb
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                              0xc
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                              0xd
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                              0xe
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                              0xf
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                              0x10
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                              0x11
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                              0x12
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                              0x13
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                              0x14
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                              0x15
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                              0x16
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                              0x17
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                              0x18
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                              0x19
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                              0x1a
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                              0x1b
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                              0x1c
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                              0x1d
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                                0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                                0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                                0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                                0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                                0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                                0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                                0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                                0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                                0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                                0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                                0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                                0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                                0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                                0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                                0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                                0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                                0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                                0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                                0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                                0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                                0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                                0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                                0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                                0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                                0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                                0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                                0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                                0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                                0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                                0x20000000L
+//BIFPLR0_PCIE_ESM_CAP_6
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                              0x0
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                              0x1
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                              0x2
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                              0x3
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                              0x4
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                              0x5
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                              0x6
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                              0x7
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                              0x8
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                              0x9
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                              0xa
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                              0xb
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                              0xc
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                              0xd
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                              0xe
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                              0xf
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                              0x10
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                              0x11
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                              0x12
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                              0x13
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                              0x14
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                              0x15
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                              0x16
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                              0x17
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                              0x18
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                              0x19
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                              0x1a
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                              0x1b
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                              0x1c
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                              0x1d
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                                0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                                0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                                0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                                0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                                0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                                0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                                0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                                0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                                0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                                0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                                0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                                0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                                0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                                0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                                0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                                0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                                0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                                0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                                0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                                0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                                0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                                0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                                0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                                0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                                0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                                0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                                0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                                0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                                0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                                0x20000000L
+//BIFPLR0_PCIE_ESM_CAP_7
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                              0x0
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                              0x1
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                              0x2
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                              0x3
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                              0x4
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                              0x5
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                              0x6
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                              0x7
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                              0x8
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                              0x9
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                              0xa
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                              0xb
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                              0xc
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                              0xd
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                              0xe
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                              0xf
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                              0x10
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                              0x11
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                              0x12
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                              0x13
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                              0x14
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                              0x15
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                              0x16
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                              0x17
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                              0x18
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                              0x19
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                              0x1a
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                              0x1b
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                              0x1c
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                              0x1d
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                              0x1e
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                                0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                                0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                                0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                                0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                                0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                                0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                                0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                                0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                                0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                                0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                                0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                                0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                                0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                                0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                                0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                                0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                                0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                                0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                                0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                                0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                                0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                                0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                                0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                                0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                                0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                                0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                                0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                                0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                                0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                                0x20000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                                0x40000000L
+//BIFPLR0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR0_DATA_LINK_FEATURE_CAP
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                         0x0
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                        0x1
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                             0x1f
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                           0x00000001L
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                          0x007FFFFEL
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                               0x80000000L
+//BIFPLR0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                         0x0
+#define BIFPLR0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                   0x1f
+#define BIFPLR0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                           0x007FFFFFL
+#define BIFPLR0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                     0x80000000L
+//BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                    0x10
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                   0x14
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                      0x000F0000L
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                     0xFFF00000L
+//BIFPLR0_LINK_CAP_16GT
+#define BIFPLR0_LINK_CAP_16GT__RESERVED__SHIFT                                                                0x0
+#define BIFPLR0_LINK_CAP_16GT__RESERVED_MASK                                                                  0xFFFFFFFFL
+//BIFPLR0_LINK_CNTL_16GT
+#define BIFPLR0_LINK_CNTL_16GT__RESERVED__SHIFT                                                               0x0
+#define BIFPLR0_LINK_CNTL_16GT__RESERVED_MASK                                                                 0xFFFFFFFFL
+//BIFPLR0_LINK_STATUS_16GT
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                           0x0
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                     0x1
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                     0x2
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                     0x3
+#define BIFPLR0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                       0x4
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                             0x00000001L
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                       0x00000002L
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                       0x00000004L
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                       0x00000008L
+#define BIFPLR0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                         0x00000010L
+//BIFPLR0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR0_MARGINING_PORT_CAP
+#define BIFPLR0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                            0x0
+#define BIFPLR0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                              0x0001L
+//BIFPLR0_MARGINING_PORT_STATUS
+#define BIFPLR0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                                 0x0
+#define BIFPLR0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                        0x1
+#define BIFPLR0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                   0x0001L
+#define BIFPLR0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                          0x0002L
+//BIFPLR0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_PCIE_CCIX_CAP_LIST
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                            0x10
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                           0x14
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                               0x0000FFFFL
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                              0x000F0000L
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                             0xFFF00000L
+//BIFPLR0_PCIE_CCIX_HEADER_1
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR0_PCIE_CCIX_HEADER_2
+#define BIFPLR0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR0_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                               0xFFFFL
+//BIFPLR0_PCIE_CCIX_CAP
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                      0x0
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                         0x1
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                        0x3
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                    0x4
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                          0x8
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                        0x0001L
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                           0x0006L
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                          0x0008L
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                      0x0070L
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                            0x0700L
+//BIFPLR0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                              0x0
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                                0x1
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                                0x2
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                               0x5
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                               0x9
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                               0xe
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                                0x00000001L
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                  0x00000002L
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                  0x00000004L
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                                 0x00000020L
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                                 0x00000200L
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                                 0x00004000L
+//BIFPLR0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                       0x0
+#define BIFPLR0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIFPLR0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                            0x0
+#define BIFPLR0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                         0x7
+#define BIFPLR0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                              0x0000007FL
+#define BIFPLR0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                           0x00000080L
+//BIFPLR0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                     0x0
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                            0x7
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                     0x8
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                         0xf
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                           0x10
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                           0x14
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                  0x18
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                    0x19
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                              0x1a
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                       0x0000007FL
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                              0x00000080L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                       0x00007F00L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                           0x00008000L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                             0x00070000L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                             0x00700000L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                    0x01000000L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                      0x02000000L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                                0x1C000000L
+//BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                                 0x0
+#define BIFPLR0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                   0x00000001L
+//BIFPLR0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                                 0x0
+#define BIFPLR0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                   0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+//BIFPLR1_VENDOR_ID
+#define BIFPLR1_VENDOR_ID__VENDOR_ID__SHIFT                                                                   0x0
+#define BIFPLR1_VENDOR_ID__VENDOR_ID_MASK                                                                     0xFFFFL
+//BIFPLR1_DEVICE_ID
+#define BIFPLR1_DEVICE_ID__DEVICE_ID__SHIFT                                                                   0x0
+#define BIFPLR1_DEVICE_ID__DEVICE_ID_MASK                                                                     0xFFFFL
+//BIFPLR1_COMMAND
+#define BIFPLR1_COMMAND__IO_ACCESS_EN__SHIFT                                                                  0x0
+#define BIFPLR1_COMMAND__MEM_ACCESS_EN__SHIFT                                                                 0x1
+#define BIFPLR1_COMMAND__BUS_MASTER_EN__SHIFT                                                                 0x2
+#define BIFPLR1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                              0x3
+#define BIFPLR1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                       0x4
+#define BIFPLR1_COMMAND__PAL_SNOOP_EN__SHIFT                                                                  0x5
+#define BIFPLR1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                         0x6
+#define BIFPLR1_COMMAND__AD_STEPPING__SHIFT                                                                   0x7
+#define BIFPLR1_COMMAND__SERR_EN__SHIFT                                                                       0x8
+#define BIFPLR1_COMMAND__FAST_B2B_EN__SHIFT                                                                   0x9
+#define BIFPLR1_COMMAND__INT_DIS__SHIFT                                                                       0xa
+#define BIFPLR1_COMMAND__IO_ACCESS_EN_MASK                                                                    0x0001L
+#define BIFPLR1_COMMAND__MEM_ACCESS_EN_MASK                                                                   0x0002L
+#define BIFPLR1_COMMAND__BUS_MASTER_EN_MASK                                                                   0x0004L
+#define BIFPLR1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                                0x0008L
+#define BIFPLR1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                         0x0010L
+#define BIFPLR1_COMMAND__PAL_SNOOP_EN_MASK                                                                    0x0020L
+#define BIFPLR1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                           0x0040L
+#define BIFPLR1_COMMAND__AD_STEPPING_MASK                                                                     0x0080L
+#define BIFPLR1_COMMAND__SERR_EN_MASK                                                                         0x0100L
+#define BIFPLR1_COMMAND__FAST_B2B_EN_MASK                                                                     0x0200L
+#define BIFPLR1_COMMAND__INT_DIS_MASK                                                                         0x0400L
+//BIFPLR1_STATUS
+#define BIFPLR1_STATUS__IMMEDIATE_READINESS__SHIFT                                                            0x0
+#define BIFPLR1_STATUS__INT_STATUS__SHIFT                                                                     0x3
+#define BIFPLR1_STATUS__CAP_LIST__SHIFT                                                                       0x4
+#define BIFPLR1_STATUS__PCI_66_CAP__SHIFT                                                                     0x5
+#define BIFPLR1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                              0x7
+#define BIFPLR1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                       0x8
+#define BIFPLR1_STATUS__DEVSEL_TIMING__SHIFT                                                                  0x9
+#define BIFPLR1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                            0xb
+#define BIFPLR1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                          0xc
+#define BIFPLR1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                          0xd
+#define BIFPLR1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                          0xe
+#define BIFPLR1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                          0xf
+#define BIFPLR1_STATUS__IMMEDIATE_READINESS_MASK                                                              0x0001L
+#define BIFPLR1_STATUS__INT_STATUS_MASK                                                                       0x0008L
+#define BIFPLR1_STATUS__CAP_LIST_MASK                                                                         0x0010L
+#define BIFPLR1_STATUS__PCI_66_CAP_MASK                                                                       0x0020L
+#define BIFPLR1_STATUS__FAST_BACK_CAPABLE_MASK                                                                0x0080L
+#define BIFPLR1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                         0x0100L
+#define BIFPLR1_STATUS__DEVSEL_TIMING_MASK                                                                    0x0600L
+#define BIFPLR1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                              0x0800L
+#define BIFPLR1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                            0x1000L
+#define BIFPLR1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                            0x2000L
+#define BIFPLR1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                            0x4000L
+#define BIFPLR1_STATUS__PARITY_ERROR_DETECTED_MASK                                                            0x8000L
+//BIFPLR1_REVISION_ID
+#define BIFPLR1_REVISION_ID__MINOR_REV_ID__SHIFT                                                              0x0
+#define BIFPLR1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                              0x4
+#define BIFPLR1_REVISION_ID__MINOR_REV_ID_MASK                                                                0x0FL
+#define BIFPLR1_REVISION_ID__MAJOR_REV_ID_MASK                                                                0xF0L
+//BIFPLR1_PROG_INTERFACE
+#define BIFPLR1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                         0x0
+#define BIFPLR1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                           0xFFL
+//BIFPLR1_SUB_CLASS
+#define BIFPLR1_SUB_CLASS__SUB_CLASS__SHIFT                                                                   0x0
+#define BIFPLR1_SUB_CLASS__SUB_CLASS_MASK                                                                     0xFFL
+//BIFPLR1_BASE_CLASS
+#define BIFPLR1_BASE_CLASS__BASE_CLASS__SHIFT                                                                 0x0
+#define BIFPLR1_BASE_CLASS__BASE_CLASS_MASK                                                                   0xFFL
+//BIFPLR1_CACHE_LINE
+#define BIFPLR1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                            0x0
+#define BIFPLR1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                              0xFFL
+//BIFPLR1_LATENCY
+#define BIFPLR1_LATENCY__LATENCY_TIMER__SHIFT                                                                 0x0
+#define BIFPLR1_LATENCY__LATENCY_TIMER_MASK                                                                   0xFFL
+//BIFPLR1_HEADER
+#define BIFPLR1_HEADER__HEADER_TYPE__SHIFT                                                                    0x0
+#define BIFPLR1_HEADER__DEVICE_TYPE__SHIFT                                                                    0x7
+#define BIFPLR1_HEADER__HEADER_TYPE_MASK                                                                      0x7FL
+#define BIFPLR1_HEADER__DEVICE_TYPE_MASK                                                                      0x80L
+//BIFPLR1_BIST
+#define BIFPLR1_BIST__BIST_COMP__SHIFT                                                                        0x0
+#define BIFPLR1_BIST__BIST_STRT__SHIFT                                                                        0x6
+#define BIFPLR1_BIST__BIST_CAP__SHIFT                                                                         0x7
+#define BIFPLR1_BIST__BIST_COMP_MASK                                                                          0x0FL
+#define BIFPLR1_BIST__BIST_STRT_MASK                                                                          0x40L
+#define BIFPLR1_BIST__BIST_CAP_MASK                                                                           0x80L
+//BIFPLR1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                    0x0
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                  0x8
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                    0x10
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                        0x18
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                      0x000000FFL
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                    0x0000FF00L
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                      0x00FF0000L
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                          0xFF000000L
+//BIFPLR1_IO_BASE_LIMIT
+#define BIFPLR1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                            0x0
+#define BIFPLR1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                                 0x4
+#define BIFPLR1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                           0x8
+#define BIFPLR1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                                0xc
+#define BIFPLR1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                              0x000FL
+#define BIFPLR1_IO_BASE_LIMIT__IO_BASE_MASK                                                                   0x00F0L
+#define BIFPLR1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                             0x0F00L
+#define BIFPLR1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                  0xF000L
+//BIFPLR1_SECONDARY_STATUS
+#define BIFPLR1_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIFPLR1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIFPLR1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIFPLR1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIFPLR1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIFPLR1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIFPLR1_SECONDARY_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIFPLR1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIFPLR1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIFPLR1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIFPLR1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIFPLR1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIFPLR1_MEM_BASE_LIMIT
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                         0x4
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                         0x10
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                        0x14
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                            0x0000000FL
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                           0x0000FFF0L
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                           0x000F0000L
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                          0xFFF00000L
+//BIFPLR1_PREF_BASE_LIMIT
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                    0x0
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                   0x4
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                   0x10
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                  0x14
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                      0x0000000FL
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                     0x0000FFF0L
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                     0x000F0000L
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                    0xFFF00000L
+//BIFPLR1_PREF_BASE_UPPER
+#define BIFPLR1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                       0x0
+#define BIFPLR1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                         0xFFFFFFFFL
+//BIFPLR1_PREF_LIMIT_UPPER
+#define BIFPLR1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                     0x0
+#define BIFPLR1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_IO_BASE_LIMIT_HI
+#define BIFPLR1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                        0x0
+#define BIFPLR1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                       0x10
+#define BIFPLR1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                          0x0000FFFFL
+#define BIFPLR1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                         0xFFFF0000L
+//BIFPLR1_CAP_PTR
+#define BIFPLR1_CAP_PTR__CAP_PTR__SHIFT                                                                       0x0
+#define BIFPLR1_CAP_PTR__CAP_PTR_MASK                                                                         0xFFL
+//BIFPLR1_ROM_BASE_ADDR
+#define BIFPLR1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                               0x0
+#define BIFPLR1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR1_INTERRUPT_LINE
+#define BIFPLR1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                         0x0
+#define BIFPLR1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                           0xFFL
+//BIFPLR1_INTERRUPT_PIN
+#define BIFPLR1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                           0x0
+#define BIFPLR1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                             0xFFL
+//BIFPLR1_IRQ_BRIDGE_CNTL
+#define BIFPLR1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                    0x0
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                               0x1
+#define BIFPLR1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                                0x2
+#define BIFPLR1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                                0x3
+#define BIFPLR1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                               0x4
+#define BIFPLR1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                     0x5
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                   0x6
+#define BIFPLR1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                           0x7
+#define BIFPLR1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                                 0x8
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                               0x9
+#define BIFPLR1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                  0xa
+#define BIFPLR1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                             0xb
+#define BIFPLR1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                      0x0001L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                                 0x0002L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                  0x0004L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                  0x0008L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                                 0x0010L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                       0x0020L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                     0x0040L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                             0x0080L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                   0x0100L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                                 0x0200L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                    0x0400L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                               0x0800L
+//BIFPLR1_EXT_BRIDGE_CNTL
+#define BIFPLR1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                         0x0
+#define BIFPLR1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                           0x01L
+//BIFPLR1_VENDOR_CAP_LIST
+#define BIFPLR1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                                0x10
+#define BIFPLR1_VENDOR_CAP_LIST__CAP_ID_MASK                                                                  0x000000FFL
+#define BIFPLR1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                                0x0000FF00L
+#define BIFPLR1_VENDOR_CAP_LIST__LENGTH_MASK                                                                  0x00FF0000L
+//BIFPLR1_ADAPTER_ID_W
+#define BIFPLR1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                      0x0
+#define BIFPLR1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                             0x10
+#define BIFPLR1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                               0xFFFF0000L
+//BIFPLR1_PMI_CAP_LIST
+#define BIFPLR1_PMI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR1_PMI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR1_PMI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR1_PMI_CAP
+#define BIFPLR1_PMI_CAP__VERSION__SHIFT                                                                       0x0
+#define BIFPLR1_PMI_CAP__PME_CLOCK__SHIFT                                                                     0x3
+#define BIFPLR1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                           0x4
+#define BIFPLR1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                             0x5
+#define BIFPLR1_PMI_CAP__AUX_CURRENT__SHIFT                                                                   0x6
+#define BIFPLR1_PMI_CAP__D1_SUPPORT__SHIFT                                                                    0x9
+#define BIFPLR1_PMI_CAP__D2_SUPPORT__SHIFT                                                                    0xa
+#define BIFPLR1_PMI_CAP__PME_SUPPORT__SHIFT                                                                   0xb
+#define BIFPLR1_PMI_CAP__VERSION_MASK                                                                         0x0007L
+#define BIFPLR1_PMI_CAP__PME_CLOCK_MASK                                                                       0x0008L
+#define BIFPLR1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                             0x0010L
+#define BIFPLR1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                               0x0020L
+#define BIFPLR1_PMI_CAP__AUX_CURRENT_MASK                                                                     0x01C0L
+#define BIFPLR1_PMI_CAP__D1_SUPPORT_MASK                                                                      0x0200L
+#define BIFPLR1_PMI_CAP__D2_SUPPORT_MASK                                                                      0x0400L
+#define BIFPLR1_PMI_CAP__PME_SUPPORT_MASK                                                                     0xF800L
+//BIFPLR1_PMI_STATUS_CNTL
+#define BIFPLR1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                           0x0
+#define BIFPLR1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                         0x3
+#define BIFPLR1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                                0x8
+#define BIFPLR1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                           0x9
+#define BIFPLR1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                            0xd
+#define BIFPLR1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                            0xf
+#define BIFPLR1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                         0x16
+#define BIFPLR1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                            0x17
+#define BIFPLR1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                              0x18
+#define BIFPLR1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                             0x00000003L
+#define BIFPLR1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                           0x00000008L
+#define BIFPLR1_PMI_STATUS_CNTL__PME_EN_MASK                                                                  0x00000100L
+#define BIFPLR1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                             0x00001E00L
+#define BIFPLR1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                              0x00006000L
+#define BIFPLR1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                              0x00008000L
+#define BIFPLR1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                           0x00400000L
+#define BIFPLR1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                              0x00800000L
+#define BIFPLR1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                                0xFF000000L
+//BIFPLR1_PCIE_CAP_LIST
+#define BIFPLR1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR1_PCIE_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR1_PCIE_CAP
+#define BIFPLR1_PCIE_CAP__VERSION__SHIFT                                                                      0x0
+#define BIFPLR1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                  0x4
+#define BIFPLR1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                             0x8
+#define BIFPLR1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                              0x9
+#define BIFPLR1_PCIE_CAP__VERSION_MASK                                                                        0x000FL
+#define BIFPLR1_PCIE_CAP__DEVICE_TYPE_MASK                                                                    0x00F0L
+#define BIFPLR1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                               0x0100L
+#define BIFPLR1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                                0x3E00L
+//BIFPLR1_DEVICE_CAP
+#define BIFPLR1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                        0x0
+#define BIFPLR1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                               0x3
+#define BIFPLR1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                               0x5
+#define BIFPLR1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                     0x6
+#define BIFPLR1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                      0x9
+#define BIFPLR1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                   0xf
+#define BIFPLR1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                  0x12
+#define BIFPLR1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                  0x1a
+#define BIFPLR1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                                0x1c
+#define BIFPLR1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                          0x00000007L
+#define BIFPLR1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                                 0x00000018L
+#define BIFPLR1_DEVICE_CAP__EXTENDED_TAG_MASK                                                                 0x00000020L
+#define BIFPLR1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                       0x000001C0L
+#define BIFPLR1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                        0x00000E00L
+#define BIFPLR1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                     0x00008000L
+#define BIFPLR1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                    0x03FC0000L
+#define BIFPLR1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                    0x0C000000L
+#define BIFPLR1_DEVICE_CAP__FLR_CAPABLE_MASK                                                                  0x10000000L
+//BIFPLR1_DEVICE_CNTL
+#define BIFPLR1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                               0x0
+#define BIFPLR1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                          0x1
+#define BIFPLR1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                              0x2
+#define BIFPLR1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                             0x3
+#define BIFPLR1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                            0x4
+#define BIFPLR1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                          0x5
+#define BIFPLR1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                           0x8
+#define BIFPLR1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                           0x9
+#define BIFPLR1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                           0xa
+#define BIFPLR1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                               0xb
+#define BIFPLR1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                     0xc
+#define BIFPLR1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                       0xf
+#define BIFPLR1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                                 0x0001L
+#define BIFPLR1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                            0x0002L
+#define BIFPLR1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                                0x0004L
+#define BIFPLR1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                               0x0008L
+#define BIFPLR1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                              0x0010L
+#define BIFPLR1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                            0x00E0L
+#define BIFPLR1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                             0x0100L
+#define BIFPLR1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                             0x0200L
+#define BIFPLR1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                             0x0400L
+#define BIFPLR1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                                 0x0800L
+#define BIFPLR1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                       0x7000L
+#define BIFPLR1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                         0x8000L
+//BIFPLR1_DEVICE_STATUS
+#define BIFPLR1_DEVICE_STATUS__CORR_ERR__SHIFT                                                                0x0
+#define BIFPLR1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                           0x1
+#define BIFPLR1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                               0x2
+#define BIFPLR1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                            0x3
+#define BIFPLR1_DEVICE_STATUS__AUX_PWR__SHIFT                                                                 0x4
+#define BIFPLR1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                       0x5
+#define BIFPLR1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                           0x6
+#define BIFPLR1_DEVICE_STATUS__CORR_ERR_MASK                                                                  0x0001L
+#define BIFPLR1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                             0x0002L
+#define BIFPLR1_DEVICE_STATUS__FATAL_ERR_MASK                                                                 0x0004L
+#define BIFPLR1_DEVICE_STATUS__USR_DETECTED_MASK                                                              0x0008L
+#define BIFPLR1_DEVICE_STATUS__AUX_PWR_MASK                                                                   0x0010L
+#define BIFPLR1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                         0x0020L
+#define BIFPLR1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                             0x0040L
+//BIFPLR1_LINK_CAP
+#define BIFPLR1_LINK_CAP__LINK_SPEED__SHIFT                                                                   0x0
+#define BIFPLR1_LINK_CAP__LINK_WIDTH__SHIFT                                                                   0x4
+#define BIFPLR1_LINK_CAP__PM_SUPPORT__SHIFT                                                                   0xa
+#define BIFPLR1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                             0xc
+#define BIFPLR1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                              0xf
+#define BIFPLR1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                       0x12
+#define BIFPLR1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                  0x13
+#define BIFPLR1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                  0x14
+#define BIFPLR1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                     0x15
+#define BIFPLR1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                  0x16
+#define BIFPLR1_LINK_CAP__PORT_NUMBER__SHIFT                                                                  0x18
+#define BIFPLR1_LINK_CAP__LINK_SPEED_MASK                                                                     0x0000000FL
+#define BIFPLR1_LINK_CAP__LINK_WIDTH_MASK                                                                     0x000003F0L
+#define BIFPLR1_LINK_CAP__PM_SUPPORT_MASK                                                                     0x00000C00L
+#define BIFPLR1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                               0x00007000L
+#define BIFPLR1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                                0x00038000L
+#define BIFPLR1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                         0x00040000L
+#define BIFPLR1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                    0x00080000L
+#define BIFPLR1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                    0x00100000L
+#define BIFPLR1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                       0x00200000L
+#define BIFPLR1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                    0x00400000L
+#define BIFPLR1_LINK_CAP__PORT_NUMBER_MASK                                                                    0xFF000000L
+//BIFPLR1_LINK_CNTL
+#define BIFPLR1_LINK_CNTL__PM_CONTROL__SHIFT                                                                  0x0
+#define BIFPLR1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                           0x3
+#define BIFPLR1_LINK_CNTL__LINK_DIS__SHIFT                                                                    0x4
+#define BIFPLR1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                                0x5
+#define BIFPLR1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                            0x6
+#define BIFPLR1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                               0x7
+#define BIFPLR1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                   0x8
+#define BIFPLR1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                                 0x9
+#define BIFPLR1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                   0xa
+#define BIFPLR1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                   0xb
+#define BIFPLR1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                       0xe
+#define BIFPLR1_LINK_CNTL__PM_CONTROL_MASK                                                                    0x0003L
+#define BIFPLR1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                             0x0008L
+#define BIFPLR1_LINK_CNTL__LINK_DIS_MASK                                                                      0x0010L
+#define BIFPLR1_LINK_CNTL__RETRAIN_LINK_MASK                                                                  0x0020L
+#define BIFPLR1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                              0x0040L
+#define BIFPLR1_LINK_CNTL__EXTENDED_SYNC_MASK                                                                 0x0080L
+#define BIFPLR1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                     0x0100L
+#define BIFPLR1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                   0x0200L
+#define BIFPLR1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                     0x0400L
+#define BIFPLR1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                     0x0800L
+#define BIFPLR1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                         0xC000L
+//BIFPLR1_LINK_STATUS
+#define BIFPLR1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                     0x4
+#define BIFPLR1_LINK_STATUS__LINK_TRAINING__SHIFT                                                             0xb
+#define BIFPLR1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                            0xc
+#define BIFPLR1_LINK_STATUS__DL_ACTIVE__SHIFT                                                                 0xd
+#define BIFPLR1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                                 0xe
+#define BIFPLR1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                                 0xf
+#define BIFPLR1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                       0x03F0L
+#define BIFPLR1_LINK_STATUS__LINK_TRAINING_MASK                                                               0x0800L
+#define BIFPLR1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                              0x1000L
+#define BIFPLR1_LINK_STATUS__DL_ACTIVE_MASK                                                                   0x2000L
+#define BIFPLR1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                   0x4000L
+#define BIFPLR1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                   0x8000L
+//BIFPLR1_SLOT_CAP
+#define BIFPLR1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                          0x0
+#define BIFPLR1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                       0x1
+#define BIFPLR1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                           0x2
+#define BIFPLR1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                       0x3
+#define BIFPLR1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                        0x4
+#define BIFPLR1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                             0x5
+#define BIFPLR1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                              0x6
+#define BIFPLR1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                         0x7
+#define BIFPLR1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                         0xf
+#define BIFPLR1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                                0x11
+#define BIFPLR1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                               0x12
+#define BIFPLR1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                            0x13
+#define BIFPLR1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                            0x00000001L
+#define BIFPLR1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                         0x00000002L
+#define BIFPLR1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                             0x00000004L
+#define BIFPLR1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                         0x00000008L
+#define BIFPLR1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                          0x00000010L
+#define BIFPLR1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                               0x00000020L
+#define BIFPLR1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                                0x00000040L
+#define BIFPLR1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                           0x00007F80L
+#define BIFPLR1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                           0x00018000L
+#define BIFPLR1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                  0x00020000L
+#define BIFPLR1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                                 0x00040000L
+#define BIFPLR1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                              0xFFF80000L
+//BIFPLR1_SLOT_CNTL
+#define BIFPLR1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                      0x0
+#define BIFPLR1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                       0x1
+#define BIFPLR1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                       0x2
+#define BIFPLR1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                  0x3
+#define BIFPLR1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                   0x4
+#define BIFPLR1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                             0x5
+#define BIFPLR1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                         0x6
+#define BIFPLR1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                          0x8
+#define BIFPLR1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                         0xa
+#define BIFPLR1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                  0xb
+#define BIFPLR1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                         0xc
+#define BIFPLR1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                                 0xd
+#define BIFPLR1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                        0x0001L
+#define BIFPLR1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                         0x0002L
+#define BIFPLR1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                         0x0004L
+#define BIFPLR1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                    0x0008L
+#define BIFPLR1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                     0x0010L
+#define BIFPLR1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                               0x0020L
+#define BIFPLR1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                           0x00C0L
+#define BIFPLR1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                            0x0300L
+#define BIFPLR1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                           0x0400L
+#define BIFPLR1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                    0x0800L
+#define BIFPLR1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                           0x1000L
+#define BIFPLR1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                   0x2000L
+//BIFPLR1_SLOT_STATUS
+#define BIFPLR1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                       0x0
+#define BIFPLR1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                        0x1
+#define BIFPLR1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                        0x2
+#define BIFPLR1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                   0x3
+#define BIFPLR1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                         0x4
+#define BIFPLR1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                          0x5
+#define BIFPLR1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                     0x6
+#define BIFPLR1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                              0x7
+#define BIFPLR1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                          0x8
+#define BIFPLR1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                         0x0001L
+#define BIFPLR1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                          0x0002L
+#define BIFPLR1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                          0x0004L
+#define BIFPLR1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                     0x0008L
+#define BIFPLR1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                           0x0010L
+#define BIFPLR1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                            0x0020L
+#define BIFPLR1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                       0x0040L
+#define BIFPLR1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                                0x0080L
+#define BIFPLR1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                            0x0100L
+//BIFPLR1_ROOT_CNTL
+#define BIFPLR1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                         0x0
+#define BIFPLR1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                     0x1
+#define BIFPLR1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                        0x2
+#define BIFPLR1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                             0x3
+#define BIFPLR1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                  0x4
+#define BIFPLR1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                           0x0001L
+#define BIFPLR1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                       0x0002L
+#define BIFPLR1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                          0x0004L
+#define BIFPLR1_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                               0x0008L
+#define BIFPLR1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                    0x0010L
+//BIFPLR1_ROOT_CAP
+#define BIFPLR1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                      0x0
+#define BIFPLR1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                        0x0001L
+//BIFPLR1_ROOT_STATUS
+#define BIFPLR1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                          0x0
+#define BIFPLR1_ROOT_STATUS__PME_STATUS__SHIFT                                                                0x10
+#define BIFPLR1_ROOT_STATUS__PME_PENDING__SHIFT                                                               0x11
+#define BIFPLR1_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR1_ROOT_STATUS__PME_STATUS_MASK                                                                  0x00010000L
+#define BIFPLR1_ROOT_STATUS__PME_PENDING_MASK                                                                 0x00020000L
+//BIFPLR1_DEVICE_CAP2
+#define BIFPLR1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                               0x0
+#define BIFPLR1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                                 0x4
+#define BIFPLR1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                  0x5
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                                0x6
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                                0x7
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                                0x8
+#define BIFPLR1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                    0x9
+#define BIFPLR1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                                 0xa
+#define BIFPLR1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                             0xb
+#define BIFPLR1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                        0xc
+#define BIFPLR1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                             0xe
+#define BIFPLR1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                           0x10
+#define BIFPLR1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                           0x11
+#define BIFPLR1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                            0x12
+#define BIFPLR1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                              0x14
+#define BIFPLR1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                              0x15
+#define BIFPLR1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                  0x16
+#define BIFPLR1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                            0x18
+#define BIFPLR1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                             0x1a
+#define BIFPLR1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                                 0x0000000FL
+#define BIFPLR1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                   0x00000010L
+#define BIFPLR1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                    0x00000020L
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                  0x00000040L
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                  0x00000080L
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                  0x00000100L
+#define BIFPLR1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                      0x00000200L
+#define BIFPLR1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                   0x00000400L
+#define BIFPLR1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                               0x00000800L
+#define BIFPLR1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                          0x00003000L
+#define BIFPLR1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                               0x0000C000L
+#define BIFPLR1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                             0x00010000L
+#define BIFPLR1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                             0x00020000L
+#define BIFPLR1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                              0x000C0000L
+#define BIFPLR1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                                0x00100000L
+#define BIFPLR1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                                0x00200000L
+#define BIFPLR1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                    0x00C00000L
+#define BIFPLR1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                              0x03000000L
+#define BIFPLR1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                               0x04000000L
+#define BIFPLR1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR1_DEVICE_CNTL2
+#define BIFPLR1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                        0x0
+#define BIFPLR1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                          0x4
+#define BIFPLR1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                        0x5
+#define BIFPLR1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                      0x6
+#define BIFPLR1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                                 0x7
+#define BIFPLR1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                       0x8
+#define BIFPLR1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                    0x9
+#define BIFPLR1_DEVICE_CNTL2__LTR_EN__SHIFT                                                                   0xa
+#define BIFPLR1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                             0xb
+#define BIFPLR1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                             0xc
+#define BIFPLR1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                  0xd
+#define BIFPLR1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                              0xf
+#define BIFPLR1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                          0x000FL
+#define BIFPLR1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                            0x0010L
+#define BIFPLR1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                          0x0020L
+#define BIFPLR1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                        0x0040L
+#define BIFPLR1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                   0x0080L
+#define BIFPLR1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                         0x0100L
+#define BIFPLR1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                      0x0200L
+#define BIFPLR1_DEVICE_CNTL2__LTR_EN_MASK                                                                     0x0400L
+#define BIFPLR1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                               0x0800L
+#define BIFPLR1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                               0x1000L
+#define BIFPLR1_DEVICE_CNTL2__OBFF_EN_MASK                                                                    0x6000L
+#define BIFPLR1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                                0x8000L
+//BIFPLR1_DEVICE_STATUS2
+#define BIFPLR1_DEVICE_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR1_DEVICE_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR1_LINK_CAP2
+#define BIFPLR1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                        0x1
+#define BIFPLR1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                         0x8
+#define BIFPLR1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                    0x10
+#define BIFPLR1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                   0x17
+#define BIFPLR1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                   0x18
+#define BIFPLR1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                               0x1f
+#define BIFPLR1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                          0x000000FEL
+#define BIFPLR1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                           0x00000100L
+#define BIFPLR1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                      0x007F0000L
+#define BIFPLR1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                     0x00800000L
+#define BIFPLR1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                     0x01000000L
+#define BIFPLR1_LINK_CAP2__DRS_SUPPORTED_MASK                                                                 0x80000000L
+//BIFPLR1_LINK_CNTL2
+#define BIFPLR1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                          0x0
+#define BIFPLR1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                           0x4
+#define BIFPLR1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                                0x5
+#define BIFPLR1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                      0x6
+#define BIFPLR1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                                0x7
+#define BIFPLR1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                       0xa
+#define BIFPLR1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                             0xb
+#define BIFPLR1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                      0xc
+#define BIFPLR1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                            0x000FL
+#define BIFPLR1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                             0x0010L
+#define BIFPLR1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                  0x0020L
+#define BIFPLR1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                        0x0040L
+#define BIFPLR1_LINK_CNTL2__XMIT_MARGIN_MASK                                                                  0x0380L
+#define BIFPLR1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                         0x0400L
+#define BIFPLR1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                               0x0800L
+#define BIFPLR1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                        0xF000L
+//BIFPLR1_LINK_STATUS2
+#define BIFPLR1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                     0x0
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                                0x1
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                          0x2
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                          0x3
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                          0x4
+#define BIFPLR1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                            0x5
+#define BIFPLR1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                        0x6
+#define BIFPLR1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                        0x7
+#define BIFPLR1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                     0x8
+#define BIFPLR1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                            0xc
+#define BIFPLR1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                     0xf
+#define BIFPLR1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                       0x0001L
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                  0x0002L
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                            0x0004L
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                            0x0008L
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                            0x0010L
+#define BIFPLR1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                              0x0020L
+#define BIFPLR1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                          0x0040L
+#define BIFPLR1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                          0x0080L
+#define BIFPLR1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                       0x0300L
+#define BIFPLR1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                              0x7000L
+#define BIFPLR1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                       0x8000L
+//BIFPLR1_SLOT_CAP2
+#define BIFPLR1_SLOT_CAP2__RESERVED__SHIFT                                                                    0x0
+#define BIFPLR1_SLOT_CAP2__RESERVED_MASK                                                                      0xFFFFFFFFL
+//BIFPLR1_SLOT_CNTL2
+#define BIFPLR1_SLOT_CNTL2__RESERVED__SHIFT                                                                   0x0
+#define BIFPLR1_SLOT_CNTL2__RESERVED_MASK                                                                     0xFFFFL
+//BIFPLR1_SLOT_STATUS2
+#define BIFPLR1_SLOT_STATUS2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR1_SLOT_STATUS2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR1_MSI_CAP_LIST
+#define BIFPLR1_MSI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR1_MSI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR1_MSI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR1_MSI_MSG_CNTL
+#define BIFPLR1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                   0x0
+#define BIFPLR1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                            0x1
+#define BIFPLR1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                             0x4
+#define BIFPLR1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                                0x7
+#define BIFPLR1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                                0x8
+#define BIFPLR1_MSI_MSG_CNTL__MSI_EN_MASK                                                                     0x0001L
+#define BIFPLR1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                              0x000EL
+#define BIFPLR1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                               0x0070L
+#define BIFPLR1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                  0x0080L
+#define BIFPLR1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                  0x0100L
+//BIFPLR1_MSI_MSG_ADDR_LO
+#define BIFPLR1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                       0x2
+#define BIFPLR1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                         0xFFFFFFFCL
+//BIFPLR1_MSI_MSG_ADDR_HI
+#define BIFPLR1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                       0x0
+#define BIFPLR1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                         0xFFFFFFFFL
+//BIFPLR1_MSI_MSG_DATA
+#define BIFPLR1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                                 0x0
+#define BIFPLR1_MSI_MSG_DATA__MSI_DATA_MASK                                                                   0xFFFFL
+//BIFPLR1_MSI_MSG_DATA_64
+#define BIFPLR1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                           0x0
+#define BIFPLR1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                             0xFFFFL
+//BIFPLR1_SSID_CAP_LIST
+#define BIFPLR1_SSID_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR1_SSID_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR1_SSID_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR1_SSID_CAP
+#define BIFPLR1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                          0x0
+#define BIFPLR1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                                 0x10
+#define BIFPLR1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR1_SSID_CAP__SUBSYSTEM_ID_MASK                                                                   0xFFFF0000L
+//BIFPLR1_MSI_MAP_CAP_LIST
+#define BIFPLR1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                               0x0
+#define BIFPLR1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                             0x8
+#define BIFPLR1_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                                 0x00FFL
+#define BIFPLR1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                               0xFF00L
+//BIFPLR1_MSI_MAP_CAP
+#define BIFPLR1_MSI_MAP_CAP__EN__SHIFT                                                                        0x0
+#define BIFPLR1_MSI_MAP_CAP__FIXD__SHIFT                                                                      0x1
+#define BIFPLR1_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                  0xb
+#define BIFPLR1_MSI_MAP_CAP__EN_MASK                                                                          0x0001L
+#define BIFPLR1_MSI_MAP_CAP__FIXD_MASK                                                                        0x0002L
+#define BIFPLR1_MSI_MAP_CAP__CAP_TYPE_MASK                                                                    0xF800L
+//BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                      0x0
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                     0x10
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                  0x14
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                       0x000F0000L
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                    0xFFF00000L
+//BIFPLR1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                       0x4
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                         0x8
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                       0xa
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                      0x00000007L
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                         0x00000070L
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                           0x00000300L
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                         0x00000C00L
+//BIFPLR1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                      0x0
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                             0x18
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                        0x000000FFL
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                               0xFF000000L
+//BIFPLR1_PCIE_PORT_VC_CNTL
+#define BIFPLR1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                   0x0
+#define BIFPLR1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                       0x1
+#define BIFPLR1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                     0x0001L
+#define BIFPLR1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                         0x000EL
+//BIFPLR1_PCIE_PORT_VC_STATUS
+#define BIFPLR1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                               0x0
+#define BIFPLR1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                                 0x0001L
+//BIFPLR1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIFPLR1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                              0x0
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                                0xFFFFFFFFL
+//BIFPLR1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                              0x0
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                                0xFFFFFFFFL
+//BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                                 0x4
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                              0x5
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                                 0xc
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                  0xd
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                             0xe
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                           0xf
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                               0x10
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                                0x11
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                                 0x12
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                                0x13
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                          0x14
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                           0x15
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                          0x16
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                          0x17
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                                 0x18
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                  0x19
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                             0x1a
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                   0x00000010L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                                0x00000020L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                   0x00001000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                    0x00002000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                               0x00004000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                             0x00008000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                                 0x00010000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                  0x00020000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                   0x00040000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                  0x00080000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                            0x00100000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                             0x00200000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                            0x00400000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                            0x00800000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                   0x01000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                    0x02000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                               0x04000000L
+//BIFPLR1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                     0x4
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                  0x5
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                     0xc
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                      0xd
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                                 0xe
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                               0xf
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                   0x10
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                    0x11
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                     0x12
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                    0x13
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                              0x14
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                               0x15
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                              0x16
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                              0x17
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                     0x18
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                      0x19
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                                 0x1a
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                       0x00000010L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                    0x00000020L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                       0x00001000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                        0x00002000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                   0x00004000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                                 0x00008000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                     0x00010000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                      0x00020000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                       0x00040000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                      0x00080000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                                0x00100000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                                 0x00200000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                                0x00400000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                                0x00800000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                       0x01000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                        0x02000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                   0x04000000L
+//BIFPLR1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                             0x4
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                          0x5
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                             0xc
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                              0xd
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                         0xe
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                       0xf
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                           0x10
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                            0x11
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                             0x12
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                            0x13
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                      0x14
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                       0x15
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                      0x16
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                      0x17
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                             0x18
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                              0x19
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                         0x1a
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                               0x00000010L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                            0x00000020L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                               0x00001000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                                0x00002000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                           0x00004000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                         0x00008000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                             0x00010000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                              0x00020000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                               0x00040000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                              0x00080000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                        0x00100000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                         0x00200000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                        0x00400000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                        0x00800000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                               0x01000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                                0x02000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                           0x04000000L
+//BIFPLR1_PCIE_CORR_ERR_STATUS
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                   0x0
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                   0x6
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                  0x7
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                       0x8
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                      0xc
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                     0xd
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                              0xe
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                              0xf
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                     0x00000001L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                     0x00000040L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                    0x00000080L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                         0x00000100L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                        0x00001000L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                       0x00002000L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                                0x00004000L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                                0x00008000L
+//BIFPLR1_PCIE_CORR_ERR_MASK
+#define BIFPLR1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                       0x0
+#define BIFPLR1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                       0x6
+#define BIFPLR1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                      0x7
+#define BIFPLR1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                           0x8
+#define BIFPLR1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                          0xc
+#define BIFPLR1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                         0xd
+#define BIFPLR1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                  0xe
+#define BIFPLR1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                  0xf
+#define BIFPLR1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                         0x00000001L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                         0x00000040L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                        0x00000080L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                             0x00000100L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                            0x00001000L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                           0x00002000L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                    0x00004000L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                    0x00008000L
+//BIFPLR1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                   0x0
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                  0x7
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                   0x8
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                              0x9
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                               0xa
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                          0xb
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                  0xc
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                     0x0000001FL
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                    0x00000080L
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                     0x00000100L
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                                0x00000200L
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                                 0x00000400L
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                            0x00000800L
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                    0x00001000L
+//BIFPLR1_PCIE_HDR_LOG0
+#define BIFPLR1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR1_PCIE_HDR_LOG1
+#define BIFPLR1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR1_PCIE_HDR_LOG2
+#define BIFPLR1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR1_PCIE_HDR_LOG3
+#define BIFPLR1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR1_PCIE_ROOT_ERR_CMD
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                     0x0
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                                 0x1
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                    0x2
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                       0x00000001L
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                   0x00000002L
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                      0x00000004L
+//BIFPLR1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                               0x1
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                          0x2
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                     0x3
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                        0x4
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                          0x5
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                             0x6
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                              0x1b
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                      0x00000001L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                                 0x00000002L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                            0x00000004L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                       0x00000008L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                          0x00000010L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                            0x00000020L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                               0x00000040L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                                0xF8000000L
+//BIFPLR1_PCIE_ERR_SRC_ID
+#define BIFPLR1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                       0x0
+#define BIFPLR1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                             0x10
+#define BIFPLR1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                               0xFFFF0000L
+//BIFPLR1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR1_PCIE_LINK_CNTL3
+#define BIFPLR1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                  0x0
+#define BIFPLR1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                          0x1
+#define BIFPLR1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                    0x00000001L
+#define BIFPLR1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                            0x00000002L
+//BIFPLR1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                         0x0
+#define BIFPLR1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                           0x0000FFFFL
+//BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR1_PCIE_ACS_CAP
+#define BIFPLR1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                        0x0
+#define BIFPLR1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                     0x1
+#define BIFPLR1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                     0x2
+#define BIFPLR1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                  0x3
+#define BIFPLR1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                      0x4
+#define BIFPLR1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                       0x5
+#define BIFPLR1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                    0x6
+#define BIFPLR1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                               0x8
+#define BIFPLR1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                          0x0001L
+#define BIFPLR1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                       0x0002L
+#define BIFPLR1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                       0x0004L
+#define BIFPLR1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                    0x0008L
+#define BIFPLR1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                        0x0010L
+#define BIFPLR1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                         0x0020L
+#define BIFPLR1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                      0x0040L
+#define BIFPLR1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                                 0xFF00L
+//BIFPLR1_PCIE_ACS_CNTL
+#define BIFPLR1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                                 0x1
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                                 0x2
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                              0x3
+#define BIFPLR1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                  0x4
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                   0x5
+#define BIFPLR1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                                0x6
+#define BIFPLR1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                      0x0001L
+#define BIFPLR1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                   0x0002L
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                   0x0004L
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                                0x0008L
+#define BIFPLR1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                    0x0010L
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                     0x0020L
+#define BIFPLR1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                  0x0040L
+//BIFPLR1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR1_PCIE_MC_CAP
+#define BIFPLR1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                              0x0
+#define BIFPLR1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                           0x8
+#define BIFPLR1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                        0xf
+#define BIFPLR1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                                0x003FL
+#define BIFPLR1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                             0x3F00L
+#define BIFPLR1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                          0x8000L
+//BIFPLR1_PCIE_MC_CNTL
+#define BIFPLR1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                             0x0
+#define BIFPLR1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                                0xf
+#define BIFPLR1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                               0x003FL
+#define BIFPLR1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                  0x8000L
+//BIFPLR1_PCIE_MC_ADDR0
+#define BIFPLR1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                            0x0
+#define BIFPLR1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                          0xc
+#define BIFPLR1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                              0x0000003FL
+#define BIFPLR1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                            0xFFFFF000L
+//BIFPLR1_PCIE_MC_ADDR1
+#define BIFPLR1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                          0x0
+#define BIFPLR1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                            0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_RCV0
+#define BIFPLR1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                             0x0
+#define BIFPLR1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                               0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_RCV1
+#define BIFPLR1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                             0x0
+#define BIFPLR1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                               0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                     0x0
+#define BIFPLR1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                     0x0
+#define BIFPLR1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                  0x0
+#define BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                    0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                  0x0
+#define BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                    0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                  0x0
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                                 0x6
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                    0x0000003FL
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                   0xFFFFFFC0L
+//BIFPLR1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                                 0x0
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                   0xFFFFFFFFL
+//BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                              0x0
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                              0x1
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                                0x2
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                                0x3
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                                0x4
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                               0x8
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                              0x10
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                              0x13
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                                0x00000001L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                                0x00000002L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                  0x00000004L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                  0x00000008L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                  0x00000010L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                                 0x0000FF00L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                                0x00030000L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                                0x00F80000L
+//BIFPLR1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                    0x1
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                      0x2
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                      0x3
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                          0x8
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                          0x1d
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                      0x00000001L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                      0x00000002L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                        0x00000004L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                        0x00000008L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                            0x0000FF00L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                            0xE0000000L
+//BIFPLR1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                                 0x0
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                                 0x3
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                   0x00000003L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                   0x000000F8L
+//BIFPLR1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR1_PCIE_DPC_CAP_LIST
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                               0x5
+#define BIFPLR1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                              0x6
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                   0x7
+#define BIFPLR1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                     0x8
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                               0xc
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                      0x001FL
+#define BIFPLR1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                                 0x0020L
+#define BIFPLR1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                                0x0040L
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                     0x0080L
+#define BIFPLR1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                       0x0F00L
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                                 0x1000L
+//BIFPLR1_PCIE_DPC_CNTL
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                      0x0
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                  0x2
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                    0x3
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                      0x4
+#define BIFPLR1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                     0x5
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                    0x6
+#define BIFPLR1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                                0x7
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                        0x0003L
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                    0x0004L
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                      0x0008L
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                        0x0010L
+#define BIFPLR1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                       0x0020L
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                      0x0040L
+#define BIFPLR1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                  0x0080L
+//BIFPLR1_PCIE_DPC_STATUS
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                    0x1
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                  0x3
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                           0x4
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                          0x5
+#define BIFPLR1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                            0x8
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                      0x0001L
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                      0x0006L
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                    0x0008L
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                             0x0010L
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                            0x0060L
+#define BIFPLR1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                              0x1F00L
+//BIFPLR1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                          0x0
+#define BIFPLR1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                            0xFFFFL
+//BIFPLR1_PCIE_RP_PIO_STATUS
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR1_PCIE_RP_PIO_MASK
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                           0x0
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                           0x1
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                              0x2
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                            0x8
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                            0x9
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                               0xa
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                           0x10
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                           0x11
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                              0x12
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                             0x00000001L
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                             0x00000002L
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                                0x00000004L
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                              0x00000100L
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                              0x00000200L
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                                 0x00000400L
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                             0x00010000L
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                             0x00020000L
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                                0x00040000L
+//BIFPLR1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                      0x0
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                      0x1
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                         0x2
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                       0x8
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                       0x9
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                          0xa
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                      0x10
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                      0x11
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                         0x12
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                        0x00000001L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                        0x00000002L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                           0x00000004L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                         0x00000100L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                         0x00000200L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                            0x00000400L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                        0x00010000L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                        0x00020000L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                           0x00040000L
+//BIFPLR1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR1_PCIE_ESM_CAP_LIST
+#define BIFPLR1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                             0x10
+#define BIFPLR1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                            0x14
+#define BIFPLR1_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                                0x0000FFFFL
+#define BIFPLR1_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                               0x000F0000L
+#define BIFPLR1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                              0xFFF00000L
+//BIFPLR1_PCIE_ESM_HEADER_1
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                       0x0
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                         0x10
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                         0x14
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                           0x000F0000L
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                           0xFFF00000L
+//BIFPLR1_PCIE_ESM_HEADER_2
+#define BIFPLR1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR1_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                                0xFFFFL
+//BIFPLR1_PCIE_ESM_STATUS
+#define BIFPLR1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                  0x9
+#define BIFPLR1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                      0x01FFL
+#define BIFPLR1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                    0x0E00L
+//BIFPLR1_PCIE_ESM_CTRL
+#define BIFPLR1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                             0xf
+#define BIFPLR1_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                               0x8000L
+//BIFPLR1_PCIE_ESM_CAP_1
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                               0x0
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                               0x1
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                               0x2
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                               0x3
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                               0x4
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                               0x5
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                               0x6
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                               0x7
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                               0x8
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                               0x9
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                               0xa
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                               0xb
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                               0xc
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                               0xd
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                               0xe
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                               0xf
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                               0x10
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                               0x11
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                               0x12
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                               0x13
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                              0x14
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                              0x15
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                              0x16
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                              0x17
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                              0x18
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                              0x19
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                              0x1a
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                              0x1b
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                              0x1c
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                              0x1d
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                                 0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                                 0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                                 0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                                 0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                                 0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                                 0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                                 0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                                 0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                                 0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                                 0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                                 0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                                 0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                                 0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                                 0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                                 0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                                 0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                                 0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                                 0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                                 0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                                 0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                                0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                                0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                                0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                                0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                                0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                                0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                                0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                                0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                                0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                                0x20000000L
+//BIFPLR1_PCIE_ESM_CAP_2
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                              0x0
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                              0x1
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                              0x2
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                              0x3
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                              0x4
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                              0x5
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                              0x6
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                              0x7
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                              0x8
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                              0x9
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                              0xa
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                              0xb
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                              0xc
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                              0xd
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                              0xe
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                              0xf
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                              0x10
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                              0x11
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                              0x12
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                              0x13
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                              0x14
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                              0x15
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                              0x16
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                              0x17
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                              0x18
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                              0x19
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                              0x1a
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                              0x1b
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                              0x1c
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                              0x1d
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                                0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                                0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                                0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                                0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                                0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                                0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                                0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                                0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                                0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                                0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                                0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                                0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                                0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                                0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                                0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                                0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                                0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                                0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                                0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                                0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                                0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                                0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                                0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                                0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                                0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                                0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                                0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                                0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                                0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                                0x20000000L
+//BIFPLR1_PCIE_ESM_CAP_3
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                              0x0
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                              0x1
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                              0x2
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                              0x3
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                              0x4
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                              0x5
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                              0x6
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                              0x7
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                              0x8
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                              0x9
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                              0xa
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                              0xb
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                              0xc
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                              0xd
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                              0xe
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                              0xf
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                              0x10
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                              0x11
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                              0x12
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                              0x13
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                                0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                                0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                                0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                                0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                                0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                                0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                                0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                                0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                                0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                                0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                                0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                                0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                                0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                                0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                                0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                                0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                                0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                                0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                                0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                                0x00080000L
+//BIFPLR1_PCIE_ESM_CAP_4
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                              0x0
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                              0x1
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                              0x2
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                              0x3
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                              0x4
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                              0x5
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                              0x6
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                              0x7
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                              0x8
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                              0x9
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                              0xa
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                              0xb
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                              0xc
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                              0xd
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                              0xe
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                              0xf
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                              0x10
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                              0x11
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                              0x12
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                              0x13
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                              0x14
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                              0x15
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                              0x16
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                              0x17
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                              0x18
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                              0x19
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                              0x1a
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                              0x1b
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                              0x1c
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                              0x1d
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                                0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                                0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                                0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                                0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                                0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                                0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                                0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                                0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                                0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                                0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                                0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                                0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                                0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                                0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                                0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                                0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                                0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                                0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                                0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                                0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                                0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                                0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                                0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                                0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                                0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                                0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                                0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                                0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                                0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                                0x20000000L
+//BIFPLR1_PCIE_ESM_CAP_5
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                              0x0
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                              0x1
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                              0x2
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                              0x3
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                              0x4
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                              0x5
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                              0x6
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                              0x7
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                              0x8
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                              0x9
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                              0xa
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                              0xb
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                              0xc
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                              0xd
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                              0xe
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                              0xf
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                              0x10
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                              0x11
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                              0x12
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                              0x13
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                              0x14
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                              0x15
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                              0x16
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                              0x17
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                              0x18
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                              0x19
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                              0x1a
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                              0x1b
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                              0x1c
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                              0x1d
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                                0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                                0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                                0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                                0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                                0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                                0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                                0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                                0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                                0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                                0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                                0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                                0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                                0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                                0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                                0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                                0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                                0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                                0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                                0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                                0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                                0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                                0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                                0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                                0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                                0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                                0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                                0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                                0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                                0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                                0x20000000L
+//BIFPLR1_PCIE_ESM_CAP_6
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                              0x0
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                              0x1
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                              0x2
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                              0x3
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                              0x4
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                              0x5
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                              0x6
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                              0x7
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                              0x8
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                              0x9
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                              0xa
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                              0xb
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                              0xc
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                              0xd
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                              0xe
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                              0xf
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                              0x10
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                              0x11
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                              0x12
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                              0x13
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                              0x14
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                              0x15
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                              0x16
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                              0x17
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                              0x18
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                              0x19
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                              0x1a
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                              0x1b
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                              0x1c
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                              0x1d
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                                0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                                0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                                0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                                0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                                0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                                0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                                0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                                0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                                0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                                0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                                0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                                0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                                0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                                0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                                0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                                0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                                0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                                0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                                0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                                0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                                0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                                0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                                0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                                0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                                0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                                0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                                0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                                0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                                0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                                0x20000000L
+//BIFPLR1_PCIE_ESM_CAP_7
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                              0x0
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                              0x1
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                              0x2
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                              0x3
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                              0x4
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                              0x5
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                              0x6
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                              0x7
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                              0x8
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                              0x9
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                              0xa
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                              0xb
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                              0xc
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                              0xd
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                              0xe
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                              0xf
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                              0x10
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                              0x11
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                              0x12
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                              0x13
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                              0x14
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                              0x15
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                              0x16
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                              0x17
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                              0x18
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                              0x19
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                              0x1a
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                              0x1b
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                              0x1c
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                              0x1d
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                              0x1e
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                                0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                                0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                                0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                                0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                                0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                                0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                                0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                                0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                                0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                                0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                                0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                                0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                                0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                                0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                                0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                                0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                                0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                                0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                                0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                                0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                                0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                                0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                                0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                                0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                                0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                                0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                                0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                                0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                                0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                                0x20000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                                0x40000000L
+//BIFPLR1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR1_DATA_LINK_FEATURE_CAP
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                         0x0
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                        0x1
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                             0x1f
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                           0x00000001L
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                          0x007FFFFEL
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                               0x80000000L
+//BIFPLR1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                         0x0
+#define BIFPLR1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                   0x1f
+#define BIFPLR1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                           0x007FFFFFL
+#define BIFPLR1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                     0x80000000L
+//BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                    0x10
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                   0x14
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                      0x000F0000L
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                     0xFFF00000L
+//BIFPLR1_LINK_CAP_16GT
+#define BIFPLR1_LINK_CAP_16GT__RESERVED__SHIFT                                                                0x0
+#define BIFPLR1_LINK_CAP_16GT__RESERVED_MASK                                                                  0xFFFFFFFFL
+//BIFPLR1_LINK_CNTL_16GT
+#define BIFPLR1_LINK_CNTL_16GT__RESERVED__SHIFT                                                               0x0
+#define BIFPLR1_LINK_CNTL_16GT__RESERVED_MASK                                                                 0xFFFFFFFFL
+//BIFPLR1_LINK_STATUS_16GT
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                           0x0
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                     0x1
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                     0x2
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                     0x3
+#define BIFPLR1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                       0x4
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                             0x00000001L
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                       0x00000002L
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                       0x00000004L
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                       0x00000008L
+#define BIFPLR1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                         0x00000010L
+//BIFPLR1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR1_MARGINING_PORT_CAP
+#define BIFPLR1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                            0x0
+#define BIFPLR1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                              0x0001L
+//BIFPLR1_MARGINING_PORT_STATUS
+#define BIFPLR1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                                 0x0
+#define BIFPLR1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                        0x1
+#define BIFPLR1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                   0x0001L
+#define BIFPLR1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                          0x0002L
+//BIFPLR1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_PCIE_CCIX_CAP_LIST
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                            0x10
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                           0x14
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                               0x0000FFFFL
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                              0x000F0000L
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                             0xFFF00000L
+//BIFPLR1_PCIE_CCIX_HEADER_1
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR1_PCIE_CCIX_HEADER_2
+#define BIFPLR1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR1_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                               0xFFFFL
+//BIFPLR1_PCIE_CCIX_CAP
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                      0x0
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                         0x1
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                        0x3
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                    0x4
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                          0x8
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                        0x0001L
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                           0x0006L
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                          0x0008L
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                      0x0070L
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                            0x0700L
+//BIFPLR1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                              0x0
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                                0x1
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                                0x2
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                               0x5
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                               0x9
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                               0xe
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                                0x00000001L
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                  0x00000002L
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                  0x00000004L
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                                 0x00000020L
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                                 0x00000200L
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                                 0x00004000L
+//BIFPLR1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                       0x0
+#define BIFPLR1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIFPLR1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                            0x0
+#define BIFPLR1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                         0x7
+#define BIFPLR1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                              0x0000007FL
+#define BIFPLR1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                           0x00000080L
+//BIFPLR1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                     0x0
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                            0x7
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                     0x8
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                         0xf
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                           0x10
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                           0x14
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                  0x18
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                    0x19
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                              0x1a
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                       0x0000007FL
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                              0x00000080L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                       0x00007F00L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                           0x00008000L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                             0x00070000L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                             0x00700000L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                    0x01000000L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                      0x02000000L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                                0x1C000000L
+//BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                                 0x0
+#define BIFPLR1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                   0x00000001L
+//BIFPLR1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                                 0x0
+#define BIFPLR1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                   0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+//BIFPLR2_VENDOR_ID
+#define BIFPLR2_VENDOR_ID__VENDOR_ID__SHIFT                                                                   0x0
+#define BIFPLR2_VENDOR_ID__VENDOR_ID_MASK                                                                     0xFFFFL
+//BIFPLR2_DEVICE_ID
+#define BIFPLR2_DEVICE_ID__DEVICE_ID__SHIFT                                                                   0x0
+#define BIFPLR2_DEVICE_ID__DEVICE_ID_MASK                                                                     0xFFFFL
+//BIFPLR2_COMMAND
+#define BIFPLR2_COMMAND__IO_ACCESS_EN__SHIFT                                                                  0x0
+#define BIFPLR2_COMMAND__MEM_ACCESS_EN__SHIFT                                                                 0x1
+#define BIFPLR2_COMMAND__BUS_MASTER_EN__SHIFT                                                                 0x2
+#define BIFPLR2_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                              0x3
+#define BIFPLR2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                       0x4
+#define BIFPLR2_COMMAND__PAL_SNOOP_EN__SHIFT                                                                  0x5
+#define BIFPLR2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                         0x6
+#define BIFPLR2_COMMAND__AD_STEPPING__SHIFT                                                                   0x7
+#define BIFPLR2_COMMAND__SERR_EN__SHIFT                                                                       0x8
+#define BIFPLR2_COMMAND__FAST_B2B_EN__SHIFT                                                                   0x9
+#define BIFPLR2_COMMAND__INT_DIS__SHIFT                                                                       0xa
+#define BIFPLR2_COMMAND__IO_ACCESS_EN_MASK                                                                    0x0001L
+#define BIFPLR2_COMMAND__MEM_ACCESS_EN_MASK                                                                   0x0002L
+#define BIFPLR2_COMMAND__BUS_MASTER_EN_MASK                                                                   0x0004L
+#define BIFPLR2_COMMAND__SPECIAL_CYCLE_EN_MASK                                                                0x0008L
+#define BIFPLR2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                         0x0010L
+#define BIFPLR2_COMMAND__PAL_SNOOP_EN_MASK                                                                    0x0020L
+#define BIFPLR2_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                           0x0040L
+#define BIFPLR2_COMMAND__AD_STEPPING_MASK                                                                     0x0080L
+#define BIFPLR2_COMMAND__SERR_EN_MASK                                                                         0x0100L
+#define BIFPLR2_COMMAND__FAST_B2B_EN_MASK                                                                     0x0200L
+#define BIFPLR2_COMMAND__INT_DIS_MASK                                                                         0x0400L
+//BIFPLR2_STATUS
+#define BIFPLR2_STATUS__IMMEDIATE_READINESS__SHIFT                                                            0x0
+#define BIFPLR2_STATUS__INT_STATUS__SHIFT                                                                     0x3
+#define BIFPLR2_STATUS__CAP_LIST__SHIFT                                                                       0x4
+#define BIFPLR2_STATUS__PCI_66_CAP__SHIFT                                                                     0x5
+#define BIFPLR2_STATUS__FAST_BACK_CAPABLE__SHIFT                                                              0x7
+#define BIFPLR2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                       0x8
+#define BIFPLR2_STATUS__DEVSEL_TIMING__SHIFT                                                                  0x9
+#define BIFPLR2_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                            0xb
+#define BIFPLR2_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                          0xc
+#define BIFPLR2_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                          0xd
+#define BIFPLR2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                          0xe
+#define BIFPLR2_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                          0xf
+#define BIFPLR2_STATUS__IMMEDIATE_READINESS_MASK                                                              0x0001L
+#define BIFPLR2_STATUS__INT_STATUS_MASK                                                                       0x0008L
+#define BIFPLR2_STATUS__CAP_LIST_MASK                                                                         0x0010L
+#define BIFPLR2_STATUS__PCI_66_CAP_MASK                                                                       0x0020L
+#define BIFPLR2_STATUS__FAST_BACK_CAPABLE_MASK                                                                0x0080L
+#define BIFPLR2_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                         0x0100L
+#define BIFPLR2_STATUS__DEVSEL_TIMING_MASK                                                                    0x0600L
+#define BIFPLR2_STATUS__SIGNAL_TARGET_ABORT_MASK                                                              0x0800L
+#define BIFPLR2_STATUS__RECEIVED_TARGET_ABORT_MASK                                                            0x1000L
+#define BIFPLR2_STATUS__RECEIVED_MASTER_ABORT_MASK                                                            0x2000L
+#define BIFPLR2_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                            0x4000L
+#define BIFPLR2_STATUS__PARITY_ERROR_DETECTED_MASK                                                            0x8000L
+//BIFPLR2_REVISION_ID
+#define BIFPLR2_REVISION_ID__MINOR_REV_ID__SHIFT                                                              0x0
+#define BIFPLR2_REVISION_ID__MAJOR_REV_ID__SHIFT                                                              0x4
+#define BIFPLR2_REVISION_ID__MINOR_REV_ID_MASK                                                                0x0FL
+#define BIFPLR2_REVISION_ID__MAJOR_REV_ID_MASK                                                                0xF0L
+//BIFPLR2_PROG_INTERFACE
+#define BIFPLR2_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                         0x0
+#define BIFPLR2_PROG_INTERFACE__PROG_INTERFACE_MASK                                                           0xFFL
+//BIFPLR2_SUB_CLASS
+#define BIFPLR2_SUB_CLASS__SUB_CLASS__SHIFT                                                                   0x0
+#define BIFPLR2_SUB_CLASS__SUB_CLASS_MASK                                                                     0xFFL
+//BIFPLR2_BASE_CLASS
+#define BIFPLR2_BASE_CLASS__BASE_CLASS__SHIFT                                                                 0x0
+#define BIFPLR2_BASE_CLASS__BASE_CLASS_MASK                                                                   0xFFL
+//BIFPLR2_CACHE_LINE
+#define BIFPLR2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                            0x0
+#define BIFPLR2_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                              0xFFL
+//BIFPLR2_LATENCY
+#define BIFPLR2_LATENCY__LATENCY_TIMER__SHIFT                                                                 0x0
+#define BIFPLR2_LATENCY__LATENCY_TIMER_MASK                                                                   0xFFL
+//BIFPLR2_HEADER
+#define BIFPLR2_HEADER__HEADER_TYPE__SHIFT                                                                    0x0
+#define BIFPLR2_HEADER__DEVICE_TYPE__SHIFT                                                                    0x7
+#define BIFPLR2_HEADER__HEADER_TYPE_MASK                                                                      0x7FL
+#define BIFPLR2_HEADER__DEVICE_TYPE_MASK                                                                      0x80L
+//BIFPLR2_BIST
+#define BIFPLR2_BIST__BIST_COMP__SHIFT                                                                        0x0
+#define BIFPLR2_BIST__BIST_STRT__SHIFT                                                                        0x6
+#define BIFPLR2_BIST__BIST_CAP__SHIFT                                                                         0x7
+#define BIFPLR2_BIST__BIST_COMP_MASK                                                                          0x0FL
+#define BIFPLR2_BIST__BIST_STRT_MASK                                                                          0x40L
+#define BIFPLR2_BIST__BIST_CAP_MASK                                                                           0x80L
+//BIFPLR2_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                    0x0
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                  0x8
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                    0x10
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                        0x18
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                      0x000000FFL
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                    0x0000FF00L
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                      0x00FF0000L
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                          0xFF000000L
+//BIFPLR2_IO_BASE_LIMIT
+#define BIFPLR2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                            0x0
+#define BIFPLR2_IO_BASE_LIMIT__IO_BASE__SHIFT                                                                 0x4
+#define BIFPLR2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                           0x8
+#define BIFPLR2_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                                0xc
+#define BIFPLR2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                              0x000FL
+#define BIFPLR2_IO_BASE_LIMIT__IO_BASE_MASK                                                                   0x00F0L
+#define BIFPLR2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                             0x0F00L
+#define BIFPLR2_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                  0xF000L
+//BIFPLR2_SECONDARY_STATUS
+#define BIFPLR2_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIFPLR2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIFPLR2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIFPLR2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIFPLR2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIFPLR2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIFPLR2_SECONDARY_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIFPLR2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIFPLR2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIFPLR2_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIFPLR2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIFPLR2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIFPLR2_MEM_BASE_LIMIT
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                         0x4
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                         0x10
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                        0x14
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                            0x0000000FL
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                           0x0000FFF0L
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                           0x000F0000L
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                          0xFFF00000L
+//BIFPLR2_PREF_BASE_LIMIT
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                    0x0
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                   0x4
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                   0x10
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                  0x14
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                      0x0000000FL
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                     0x0000FFF0L
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                     0x000F0000L
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                    0xFFF00000L
+//BIFPLR2_PREF_BASE_UPPER
+#define BIFPLR2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                       0x0
+#define BIFPLR2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                         0xFFFFFFFFL
+//BIFPLR2_PREF_LIMIT_UPPER
+#define BIFPLR2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                     0x0
+#define BIFPLR2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_IO_BASE_LIMIT_HI
+#define BIFPLR2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                        0x0
+#define BIFPLR2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                       0x10
+#define BIFPLR2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                          0x0000FFFFL
+#define BIFPLR2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                         0xFFFF0000L
+//BIFPLR2_CAP_PTR
+#define BIFPLR2_CAP_PTR__CAP_PTR__SHIFT                                                                       0x0
+#define BIFPLR2_CAP_PTR__CAP_PTR_MASK                                                                         0xFFL
+//BIFPLR2_ROM_BASE_ADDR
+#define BIFPLR2_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                               0x0
+#define BIFPLR2_ROM_BASE_ADDR__BASE_ADDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR2_INTERRUPT_LINE
+#define BIFPLR2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                         0x0
+#define BIFPLR2_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                           0xFFL
+//BIFPLR2_INTERRUPT_PIN
+#define BIFPLR2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                           0x0
+#define BIFPLR2_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                             0xFFL
+//BIFPLR2_IRQ_BRIDGE_CNTL
+#define BIFPLR2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                    0x0
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                               0x1
+#define BIFPLR2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                                0x2
+#define BIFPLR2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                                0x3
+#define BIFPLR2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                               0x4
+#define BIFPLR2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                     0x5
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                   0x6
+#define BIFPLR2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                           0x7
+#define BIFPLR2_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                                 0x8
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                               0x9
+#define BIFPLR2_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                  0xa
+#define BIFPLR2_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                             0xb
+#define BIFPLR2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                      0x0001L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                                 0x0002L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                  0x0004L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                  0x0008L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                                 0x0010L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                       0x0020L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                     0x0040L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                             0x0080L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                   0x0100L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                                 0x0200L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                    0x0400L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                               0x0800L
+//BIFPLR2_EXT_BRIDGE_CNTL
+#define BIFPLR2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                         0x0
+#define BIFPLR2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                           0x01L
+//BIFPLR2_VENDOR_CAP_LIST
+#define BIFPLR2_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR2_VENDOR_CAP_LIST__LENGTH__SHIFT                                                                0x10
+#define BIFPLR2_VENDOR_CAP_LIST__CAP_ID_MASK                                                                  0x000000FFL
+#define BIFPLR2_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                                0x0000FF00L
+#define BIFPLR2_VENDOR_CAP_LIST__LENGTH_MASK                                                                  0x00FF0000L
+//BIFPLR2_ADAPTER_ID_W
+#define BIFPLR2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                      0x0
+#define BIFPLR2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                             0x10
+#define BIFPLR2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                               0xFFFF0000L
+//BIFPLR2_PMI_CAP_LIST
+#define BIFPLR2_PMI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR2_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR2_PMI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR2_PMI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR2_PMI_CAP
+#define BIFPLR2_PMI_CAP__VERSION__SHIFT                                                                       0x0
+#define BIFPLR2_PMI_CAP__PME_CLOCK__SHIFT                                                                     0x3
+#define BIFPLR2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                           0x4
+#define BIFPLR2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                             0x5
+#define BIFPLR2_PMI_CAP__AUX_CURRENT__SHIFT                                                                   0x6
+#define BIFPLR2_PMI_CAP__D1_SUPPORT__SHIFT                                                                    0x9
+#define BIFPLR2_PMI_CAP__D2_SUPPORT__SHIFT                                                                    0xa
+#define BIFPLR2_PMI_CAP__PME_SUPPORT__SHIFT                                                                   0xb
+#define BIFPLR2_PMI_CAP__VERSION_MASK                                                                         0x0007L
+#define BIFPLR2_PMI_CAP__PME_CLOCK_MASK                                                                       0x0008L
+#define BIFPLR2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                             0x0010L
+#define BIFPLR2_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                               0x0020L
+#define BIFPLR2_PMI_CAP__AUX_CURRENT_MASK                                                                     0x01C0L
+#define BIFPLR2_PMI_CAP__D1_SUPPORT_MASK                                                                      0x0200L
+#define BIFPLR2_PMI_CAP__D2_SUPPORT_MASK                                                                      0x0400L
+#define BIFPLR2_PMI_CAP__PME_SUPPORT_MASK                                                                     0xF800L
+//BIFPLR2_PMI_STATUS_CNTL
+#define BIFPLR2_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                           0x0
+#define BIFPLR2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                         0x3
+#define BIFPLR2_PMI_STATUS_CNTL__PME_EN__SHIFT                                                                0x8
+#define BIFPLR2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                           0x9
+#define BIFPLR2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                            0xd
+#define BIFPLR2_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                            0xf
+#define BIFPLR2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                         0x16
+#define BIFPLR2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                            0x17
+#define BIFPLR2_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                              0x18
+#define BIFPLR2_PMI_STATUS_CNTL__POWER_STATE_MASK                                                             0x00000003L
+#define BIFPLR2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                           0x00000008L
+#define BIFPLR2_PMI_STATUS_CNTL__PME_EN_MASK                                                                  0x00000100L
+#define BIFPLR2_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                             0x00001E00L
+#define BIFPLR2_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                              0x00006000L
+#define BIFPLR2_PMI_STATUS_CNTL__PME_STATUS_MASK                                                              0x00008000L
+#define BIFPLR2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                           0x00400000L
+#define BIFPLR2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                              0x00800000L
+#define BIFPLR2_PMI_STATUS_CNTL__PMI_DATA_MASK                                                                0xFF000000L
+//BIFPLR2_PCIE_CAP_LIST
+#define BIFPLR2_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR2_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR2_PCIE_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR2_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR2_PCIE_CAP
+#define BIFPLR2_PCIE_CAP__VERSION__SHIFT                                                                      0x0
+#define BIFPLR2_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                  0x4
+#define BIFPLR2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                             0x8
+#define BIFPLR2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                              0x9
+#define BIFPLR2_PCIE_CAP__VERSION_MASK                                                                        0x000FL
+#define BIFPLR2_PCIE_CAP__DEVICE_TYPE_MASK                                                                    0x00F0L
+#define BIFPLR2_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                               0x0100L
+#define BIFPLR2_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                                0x3E00L
+//BIFPLR2_DEVICE_CAP
+#define BIFPLR2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                        0x0
+#define BIFPLR2_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                               0x3
+#define BIFPLR2_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                               0x5
+#define BIFPLR2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                     0x6
+#define BIFPLR2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                      0x9
+#define BIFPLR2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                   0xf
+#define BIFPLR2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                  0x12
+#define BIFPLR2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                  0x1a
+#define BIFPLR2_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                                0x1c
+#define BIFPLR2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                          0x00000007L
+#define BIFPLR2_DEVICE_CAP__PHANTOM_FUNC_MASK                                                                 0x00000018L
+#define BIFPLR2_DEVICE_CAP__EXTENDED_TAG_MASK                                                                 0x00000020L
+#define BIFPLR2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                       0x000001C0L
+#define BIFPLR2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                        0x00000E00L
+#define BIFPLR2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                     0x00008000L
+#define BIFPLR2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                    0x03FC0000L
+#define BIFPLR2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                    0x0C000000L
+#define BIFPLR2_DEVICE_CAP__FLR_CAPABLE_MASK                                                                  0x10000000L
+//BIFPLR2_DEVICE_CNTL
+#define BIFPLR2_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                               0x0
+#define BIFPLR2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                          0x1
+#define BIFPLR2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                              0x2
+#define BIFPLR2_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                             0x3
+#define BIFPLR2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                            0x4
+#define BIFPLR2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                          0x5
+#define BIFPLR2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                           0x8
+#define BIFPLR2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                           0x9
+#define BIFPLR2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                           0xa
+#define BIFPLR2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                               0xb
+#define BIFPLR2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                     0xc
+#define BIFPLR2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                       0xf
+#define BIFPLR2_DEVICE_CNTL__CORR_ERR_EN_MASK                                                                 0x0001L
+#define BIFPLR2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                            0x0002L
+#define BIFPLR2_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                                0x0004L
+#define BIFPLR2_DEVICE_CNTL__USR_REPORT_EN_MASK                                                               0x0008L
+#define BIFPLR2_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                              0x0010L
+#define BIFPLR2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                            0x00E0L
+#define BIFPLR2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                             0x0100L
+#define BIFPLR2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                             0x0200L
+#define BIFPLR2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                             0x0400L
+#define BIFPLR2_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                                 0x0800L
+#define BIFPLR2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                       0x7000L
+#define BIFPLR2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                         0x8000L
+//BIFPLR2_DEVICE_STATUS
+#define BIFPLR2_DEVICE_STATUS__CORR_ERR__SHIFT                                                                0x0
+#define BIFPLR2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                           0x1
+#define BIFPLR2_DEVICE_STATUS__FATAL_ERR__SHIFT                                                               0x2
+#define BIFPLR2_DEVICE_STATUS__USR_DETECTED__SHIFT                                                            0x3
+#define BIFPLR2_DEVICE_STATUS__AUX_PWR__SHIFT                                                                 0x4
+#define BIFPLR2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                       0x5
+#define BIFPLR2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                           0x6
+#define BIFPLR2_DEVICE_STATUS__CORR_ERR_MASK                                                                  0x0001L
+#define BIFPLR2_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                             0x0002L
+#define BIFPLR2_DEVICE_STATUS__FATAL_ERR_MASK                                                                 0x0004L
+#define BIFPLR2_DEVICE_STATUS__USR_DETECTED_MASK                                                              0x0008L
+#define BIFPLR2_DEVICE_STATUS__AUX_PWR_MASK                                                                   0x0010L
+#define BIFPLR2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                         0x0020L
+#define BIFPLR2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                             0x0040L
+//BIFPLR2_LINK_CAP
+#define BIFPLR2_LINK_CAP__LINK_SPEED__SHIFT                                                                   0x0
+#define BIFPLR2_LINK_CAP__LINK_WIDTH__SHIFT                                                                   0x4
+#define BIFPLR2_LINK_CAP__PM_SUPPORT__SHIFT                                                                   0xa
+#define BIFPLR2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                             0xc
+#define BIFPLR2_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                              0xf
+#define BIFPLR2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                       0x12
+#define BIFPLR2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                  0x13
+#define BIFPLR2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                  0x14
+#define BIFPLR2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                     0x15
+#define BIFPLR2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                  0x16
+#define BIFPLR2_LINK_CAP__PORT_NUMBER__SHIFT                                                                  0x18
+#define BIFPLR2_LINK_CAP__LINK_SPEED_MASK                                                                     0x0000000FL
+#define BIFPLR2_LINK_CAP__LINK_WIDTH_MASK                                                                     0x000003F0L
+#define BIFPLR2_LINK_CAP__PM_SUPPORT_MASK                                                                     0x00000C00L
+#define BIFPLR2_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                               0x00007000L
+#define BIFPLR2_LINK_CAP__L1_EXIT_LATENCY_MASK                                                                0x00038000L
+#define BIFPLR2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                         0x00040000L
+#define BIFPLR2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                    0x00080000L
+#define BIFPLR2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                    0x00100000L
+#define BIFPLR2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                       0x00200000L
+#define BIFPLR2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                    0x00400000L
+#define BIFPLR2_LINK_CAP__PORT_NUMBER_MASK                                                                    0xFF000000L
+//BIFPLR2_LINK_CNTL
+#define BIFPLR2_LINK_CNTL__PM_CONTROL__SHIFT                                                                  0x0
+#define BIFPLR2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                           0x3
+#define BIFPLR2_LINK_CNTL__LINK_DIS__SHIFT                                                                    0x4
+#define BIFPLR2_LINK_CNTL__RETRAIN_LINK__SHIFT                                                                0x5
+#define BIFPLR2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                            0x6
+#define BIFPLR2_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                               0x7
+#define BIFPLR2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                   0x8
+#define BIFPLR2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                                 0x9
+#define BIFPLR2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                   0xa
+#define BIFPLR2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                   0xb
+#define BIFPLR2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                       0xe
+#define BIFPLR2_LINK_CNTL__PM_CONTROL_MASK                                                                    0x0003L
+#define BIFPLR2_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                             0x0008L
+#define BIFPLR2_LINK_CNTL__LINK_DIS_MASK                                                                      0x0010L
+#define BIFPLR2_LINK_CNTL__RETRAIN_LINK_MASK                                                                  0x0020L
+#define BIFPLR2_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                              0x0040L
+#define BIFPLR2_LINK_CNTL__EXTENDED_SYNC_MASK                                                                 0x0080L
+#define BIFPLR2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                     0x0100L
+#define BIFPLR2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                   0x0200L
+#define BIFPLR2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                     0x0400L
+#define BIFPLR2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                     0x0800L
+#define BIFPLR2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                         0xC000L
+//BIFPLR2_LINK_STATUS
+#define BIFPLR2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                     0x4
+#define BIFPLR2_LINK_STATUS__LINK_TRAINING__SHIFT                                                             0xb
+#define BIFPLR2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                            0xc
+#define BIFPLR2_LINK_STATUS__DL_ACTIVE__SHIFT                                                                 0xd
+#define BIFPLR2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                                 0xe
+#define BIFPLR2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                                 0xf
+#define BIFPLR2_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                       0x03F0L
+#define BIFPLR2_LINK_STATUS__LINK_TRAINING_MASK                                                               0x0800L
+#define BIFPLR2_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                              0x1000L
+#define BIFPLR2_LINK_STATUS__DL_ACTIVE_MASK                                                                   0x2000L
+#define BIFPLR2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                   0x4000L
+#define BIFPLR2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                   0x8000L
+//BIFPLR2_SLOT_CAP
+#define BIFPLR2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                          0x0
+#define BIFPLR2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                       0x1
+#define BIFPLR2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                           0x2
+#define BIFPLR2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                       0x3
+#define BIFPLR2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                        0x4
+#define BIFPLR2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                             0x5
+#define BIFPLR2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                              0x6
+#define BIFPLR2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                         0x7
+#define BIFPLR2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                         0xf
+#define BIFPLR2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                                0x11
+#define BIFPLR2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                               0x12
+#define BIFPLR2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                            0x13
+#define BIFPLR2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                            0x00000001L
+#define BIFPLR2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                         0x00000002L
+#define BIFPLR2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                             0x00000004L
+#define BIFPLR2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                         0x00000008L
+#define BIFPLR2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                          0x00000010L
+#define BIFPLR2_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                               0x00000020L
+#define BIFPLR2_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                                0x00000040L
+#define BIFPLR2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                           0x00007F80L
+#define BIFPLR2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                           0x00018000L
+#define BIFPLR2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                  0x00020000L
+#define BIFPLR2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                                 0x00040000L
+#define BIFPLR2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                              0xFFF80000L
+//BIFPLR2_SLOT_CNTL
+#define BIFPLR2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                      0x0
+#define BIFPLR2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                       0x1
+#define BIFPLR2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                       0x2
+#define BIFPLR2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                  0x3
+#define BIFPLR2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                   0x4
+#define BIFPLR2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                             0x5
+#define BIFPLR2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                         0x6
+#define BIFPLR2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                          0x8
+#define BIFPLR2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                         0xa
+#define BIFPLR2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                  0xb
+#define BIFPLR2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                         0xc
+#define BIFPLR2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                                 0xd
+#define BIFPLR2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                        0x0001L
+#define BIFPLR2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                         0x0002L
+#define BIFPLR2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                         0x0004L
+#define BIFPLR2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                    0x0008L
+#define BIFPLR2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                     0x0010L
+#define BIFPLR2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                               0x0020L
+#define BIFPLR2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                           0x00C0L
+#define BIFPLR2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                            0x0300L
+#define BIFPLR2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                           0x0400L
+#define BIFPLR2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                    0x0800L
+#define BIFPLR2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                           0x1000L
+#define BIFPLR2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                   0x2000L
+//BIFPLR2_SLOT_STATUS
+#define BIFPLR2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                       0x0
+#define BIFPLR2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                        0x1
+#define BIFPLR2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                        0x2
+#define BIFPLR2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                   0x3
+#define BIFPLR2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                         0x4
+#define BIFPLR2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                          0x5
+#define BIFPLR2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                     0x6
+#define BIFPLR2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                              0x7
+#define BIFPLR2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                          0x8
+#define BIFPLR2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                         0x0001L
+#define BIFPLR2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                          0x0002L
+#define BIFPLR2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                          0x0004L
+#define BIFPLR2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                     0x0008L
+#define BIFPLR2_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                           0x0010L
+#define BIFPLR2_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                            0x0020L
+#define BIFPLR2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                       0x0040L
+#define BIFPLR2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                                0x0080L
+#define BIFPLR2_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                            0x0100L
+//BIFPLR2_ROOT_CNTL
+#define BIFPLR2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                         0x0
+#define BIFPLR2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                     0x1
+#define BIFPLR2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                        0x2
+#define BIFPLR2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                             0x3
+#define BIFPLR2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                  0x4
+#define BIFPLR2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                           0x0001L
+#define BIFPLR2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                       0x0002L
+#define BIFPLR2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                          0x0004L
+#define BIFPLR2_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                               0x0008L
+#define BIFPLR2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                    0x0010L
+//BIFPLR2_ROOT_CAP
+#define BIFPLR2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                      0x0
+#define BIFPLR2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                        0x0001L
+//BIFPLR2_ROOT_STATUS
+#define BIFPLR2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                          0x0
+#define BIFPLR2_ROOT_STATUS__PME_STATUS__SHIFT                                                                0x10
+#define BIFPLR2_ROOT_STATUS__PME_PENDING__SHIFT                                                               0x11
+#define BIFPLR2_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR2_ROOT_STATUS__PME_STATUS_MASK                                                                  0x00010000L
+#define BIFPLR2_ROOT_STATUS__PME_PENDING_MASK                                                                 0x00020000L
+//BIFPLR2_DEVICE_CAP2
+#define BIFPLR2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                               0x0
+#define BIFPLR2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                                 0x4
+#define BIFPLR2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                  0x5
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                                0x6
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                                0x7
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                                0x8
+#define BIFPLR2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                    0x9
+#define BIFPLR2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                                 0xa
+#define BIFPLR2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                             0xb
+#define BIFPLR2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                        0xc
+#define BIFPLR2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                             0xe
+#define BIFPLR2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                           0x10
+#define BIFPLR2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                           0x11
+#define BIFPLR2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                            0x12
+#define BIFPLR2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                              0x14
+#define BIFPLR2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                              0x15
+#define BIFPLR2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                  0x16
+#define BIFPLR2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                            0x18
+#define BIFPLR2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                             0x1a
+#define BIFPLR2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                                 0x0000000FL
+#define BIFPLR2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                   0x00000010L
+#define BIFPLR2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                    0x00000020L
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                  0x00000040L
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                  0x00000080L
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                  0x00000100L
+#define BIFPLR2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                      0x00000200L
+#define BIFPLR2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                   0x00000400L
+#define BIFPLR2_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                               0x00000800L
+#define BIFPLR2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                          0x00003000L
+#define BIFPLR2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                               0x0000C000L
+#define BIFPLR2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                             0x00010000L
+#define BIFPLR2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                             0x00020000L
+#define BIFPLR2_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                              0x000C0000L
+#define BIFPLR2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                                0x00100000L
+#define BIFPLR2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                                0x00200000L
+#define BIFPLR2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                    0x00C00000L
+#define BIFPLR2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                              0x03000000L
+#define BIFPLR2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                               0x04000000L
+#define BIFPLR2_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR2_DEVICE_CNTL2
+#define BIFPLR2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                        0x0
+#define BIFPLR2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                          0x4
+#define BIFPLR2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                        0x5
+#define BIFPLR2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                      0x6
+#define BIFPLR2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                                 0x7
+#define BIFPLR2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                       0x8
+#define BIFPLR2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                    0x9
+#define BIFPLR2_DEVICE_CNTL2__LTR_EN__SHIFT                                                                   0xa
+#define BIFPLR2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                             0xb
+#define BIFPLR2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                             0xc
+#define BIFPLR2_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                  0xd
+#define BIFPLR2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                              0xf
+#define BIFPLR2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                          0x000FL
+#define BIFPLR2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                            0x0010L
+#define BIFPLR2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                          0x0020L
+#define BIFPLR2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                        0x0040L
+#define BIFPLR2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                   0x0080L
+#define BIFPLR2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                         0x0100L
+#define BIFPLR2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                      0x0200L
+#define BIFPLR2_DEVICE_CNTL2__LTR_EN_MASK                                                                     0x0400L
+#define BIFPLR2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                               0x0800L
+#define BIFPLR2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                               0x1000L
+#define BIFPLR2_DEVICE_CNTL2__OBFF_EN_MASK                                                                    0x6000L
+#define BIFPLR2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                                0x8000L
+//BIFPLR2_DEVICE_STATUS2
+#define BIFPLR2_DEVICE_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR2_DEVICE_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR2_LINK_CAP2
+#define BIFPLR2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                        0x1
+#define BIFPLR2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                         0x8
+#define BIFPLR2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                    0x10
+#define BIFPLR2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                   0x17
+#define BIFPLR2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                   0x18
+#define BIFPLR2_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                               0x1f
+#define BIFPLR2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                          0x000000FEL
+#define BIFPLR2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                           0x00000100L
+#define BIFPLR2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                      0x007F0000L
+#define BIFPLR2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                     0x00800000L
+#define BIFPLR2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                     0x01000000L
+#define BIFPLR2_LINK_CAP2__DRS_SUPPORTED_MASK                                                                 0x80000000L
+//BIFPLR2_LINK_CNTL2
+#define BIFPLR2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                          0x0
+#define BIFPLR2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                           0x4
+#define BIFPLR2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                                0x5
+#define BIFPLR2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                      0x6
+#define BIFPLR2_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                                0x7
+#define BIFPLR2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                       0xa
+#define BIFPLR2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                             0xb
+#define BIFPLR2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                      0xc
+#define BIFPLR2_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                            0x000FL
+#define BIFPLR2_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                             0x0010L
+#define BIFPLR2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                  0x0020L
+#define BIFPLR2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                        0x0040L
+#define BIFPLR2_LINK_CNTL2__XMIT_MARGIN_MASK                                                                  0x0380L
+#define BIFPLR2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                         0x0400L
+#define BIFPLR2_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                               0x0800L
+#define BIFPLR2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                        0xF000L
+//BIFPLR2_LINK_STATUS2
+#define BIFPLR2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                     0x0
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                                0x1
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                          0x2
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                          0x3
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                          0x4
+#define BIFPLR2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                            0x5
+#define BIFPLR2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                        0x6
+#define BIFPLR2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                        0x7
+#define BIFPLR2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                     0x8
+#define BIFPLR2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                            0xc
+#define BIFPLR2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                     0xf
+#define BIFPLR2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                       0x0001L
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                  0x0002L
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                            0x0004L
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                            0x0008L
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                            0x0010L
+#define BIFPLR2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                              0x0020L
+#define BIFPLR2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                          0x0040L
+#define BIFPLR2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                          0x0080L
+#define BIFPLR2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                       0x0300L
+#define BIFPLR2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                              0x7000L
+#define BIFPLR2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                       0x8000L
+//BIFPLR2_SLOT_CAP2
+#define BIFPLR2_SLOT_CAP2__RESERVED__SHIFT                                                                    0x0
+#define BIFPLR2_SLOT_CAP2__RESERVED_MASK                                                                      0xFFFFFFFFL
+//BIFPLR2_SLOT_CNTL2
+#define BIFPLR2_SLOT_CNTL2__RESERVED__SHIFT                                                                   0x0
+#define BIFPLR2_SLOT_CNTL2__RESERVED_MASK                                                                     0xFFFFL
+//BIFPLR2_SLOT_STATUS2
+#define BIFPLR2_SLOT_STATUS2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR2_SLOT_STATUS2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR2_MSI_CAP_LIST
+#define BIFPLR2_MSI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR2_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR2_MSI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR2_MSI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR2_MSI_MSG_CNTL
+#define BIFPLR2_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                   0x0
+#define BIFPLR2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                            0x1
+#define BIFPLR2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                             0x4
+#define BIFPLR2_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                                0x7
+#define BIFPLR2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                                0x8
+#define BIFPLR2_MSI_MSG_CNTL__MSI_EN_MASK                                                                     0x0001L
+#define BIFPLR2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                              0x000EL
+#define BIFPLR2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                               0x0070L
+#define BIFPLR2_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                  0x0080L
+#define BIFPLR2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                  0x0100L
+//BIFPLR2_MSI_MSG_ADDR_LO
+#define BIFPLR2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                       0x2
+#define BIFPLR2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                         0xFFFFFFFCL
+//BIFPLR2_MSI_MSG_ADDR_HI
+#define BIFPLR2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                       0x0
+#define BIFPLR2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                         0xFFFFFFFFL
+//BIFPLR2_MSI_MSG_DATA
+#define BIFPLR2_MSI_MSG_DATA__MSI_DATA__SHIFT                                                                 0x0
+#define BIFPLR2_MSI_MSG_DATA__MSI_DATA_MASK                                                                   0xFFFFL
+//BIFPLR2_MSI_MSG_DATA_64
+#define BIFPLR2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                           0x0
+#define BIFPLR2_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                             0xFFFFL
+//BIFPLR2_SSID_CAP_LIST
+#define BIFPLR2_SSID_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR2_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR2_SSID_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR2_SSID_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR2_SSID_CAP
+#define BIFPLR2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                          0x0
+#define BIFPLR2_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                                 0x10
+#define BIFPLR2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR2_SSID_CAP__SUBSYSTEM_ID_MASK                                                                   0xFFFF0000L
+//BIFPLR2_MSI_MAP_CAP_LIST
+#define BIFPLR2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                               0x0
+#define BIFPLR2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                             0x8
+#define BIFPLR2_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                                 0x00FFL
+#define BIFPLR2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                               0xFF00L
+//BIFPLR2_MSI_MAP_CAP
+#define BIFPLR2_MSI_MAP_CAP__EN__SHIFT                                                                        0x0
+#define BIFPLR2_MSI_MAP_CAP__FIXD__SHIFT                                                                      0x1
+#define BIFPLR2_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                  0xb
+#define BIFPLR2_MSI_MAP_CAP__EN_MASK                                                                          0x0001L
+#define BIFPLR2_MSI_MAP_CAP__FIXD_MASK                                                                        0x0002L
+#define BIFPLR2_MSI_MAP_CAP__CAP_TYPE_MASK                                                                    0xF800L
+//BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                      0x0
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                     0x10
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                  0x14
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                       0x000F0000L
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                    0xFFF00000L
+//BIFPLR2_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR2_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR2_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR2_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                       0x4
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                         0x8
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                       0xa
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                      0x00000007L
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                         0x00000070L
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                           0x00000300L
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                         0x00000C00L
+//BIFPLR2_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                      0x0
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                             0x18
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                        0x000000FFL
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                               0xFF000000L
+//BIFPLR2_PCIE_PORT_VC_CNTL
+#define BIFPLR2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                   0x0
+#define BIFPLR2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                       0x1
+#define BIFPLR2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                     0x0001L
+#define BIFPLR2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                         0x000EL
+//BIFPLR2_PCIE_PORT_VC_STATUS
+#define BIFPLR2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                               0x0
+#define BIFPLR2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                                 0x0001L
+//BIFPLR2_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR2_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR2_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR2_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR2_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR2_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIFPLR2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                              0x0
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                                0xFFFFFFFFL
+//BIFPLR2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                              0x0
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                                0xFFFFFFFFL
+//BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR2_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                                 0x4
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                              0x5
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                                 0xc
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                  0xd
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                             0xe
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                           0xf
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                               0x10
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                                0x11
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                                 0x12
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                                0x13
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                          0x14
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                           0x15
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                          0x16
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                          0x17
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                                 0x18
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                  0x19
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                             0x1a
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                   0x00000010L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                                0x00000020L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                   0x00001000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                    0x00002000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                               0x00004000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                             0x00008000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                                 0x00010000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                  0x00020000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                   0x00040000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                  0x00080000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                            0x00100000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                             0x00200000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                            0x00400000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                            0x00800000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                   0x01000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                    0x02000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                               0x04000000L
+//BIFPLR2_PCIE_UNCORR_ERR_MASK
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                     0x4
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                  0x5
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                     0xc
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                      0xd
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                                 0xe
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                               0xf
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                   0x10
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                    0x11
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                     0x12
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                    0x13
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                              0x14
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                               0x15
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                              0x16
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                              0x17
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                     0x18
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                      0x19
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                                 0x1a
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                       0x00000010L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                    0x00000020L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                       0x00001000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                        0x00002000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                   0x00004000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                                 0x00008000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                     0x00010000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                      0x00020000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                       0x00040000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                      0x00080000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                                0x00100000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                                 0x00200000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                                0x00400000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                                0x00800000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                       0x01000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                        0x02000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                   0x04000000L
+//BIFPLR2_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                             0x4
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                          0x5
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                             0xc
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                              0xd
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                         0xe
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                       0xf
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                           0x10
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                            0x11
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                             0x12
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                            0x13
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                      0x14
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                       0x15
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                      0x16
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                      0x17
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                             0x18
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                              0x19
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                         0x1a
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                               0x00000010L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                            0x00000020L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                               0x00001000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                                0x00002000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                           0x00004000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                         0x00008000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                             0x00010000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                              0x00020000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                               0x00040000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                              0x00080000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                        0x00100000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                         0x00200000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                        0x00400000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                        0x00800000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                               0x01000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                                0x02000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                           0x04000000L
+//BIFPLR2_PCIE_CORR_ERR_STATUS
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                   0x0
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                   0x6
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                  0x7
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                       0x8
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                      0xc
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                     0xd
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                              0xe
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                              0xf
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                     0x00000001L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                     0x00000040L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                    0x00000080L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                         0x00000100L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                        0x00001000L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                       0x00002000L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                                0x00004000L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                                0x00008000L
+//BIFPLR2_PCIE_CORR_ERR_MASK
+#define BIFPLR2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                       0x0
+#define BIFPLR2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                       0x6
+#define BIFPLR2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                      0x7
+#define BIFPLR2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                           0x8
+#define BIFPLR2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                          0xc
+#define BIFPLR2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                         0xd
+#define BIFPLR2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                  0xe
+#define BIFPLR2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                  0xf
+#define BIFPLR2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                         0x00000001L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                         0x00000040L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                        0x00000080L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                             0x00000100L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                            0x00001000L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                           0x00002000L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                    0x00004000L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                    0x00008000L
+//BIFPLR2_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                   0x0
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                  0x7
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                   0x8
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                              0x9
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                               0xa
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                          0xb
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                  0xc
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                     0x0000001FL
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                    0x00000080L
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                     0x00000100L
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                                0x00000200L
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                                 0x00000400L
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                            0x00000800L
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                    0x00001000L
+//BIFPLR2_PCIE_HDR_LOG0
+#define BIFPLR2_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR2_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR2_PCIE_HDR_LOG1
+#define BIFPLR2_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR2_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR2_PCIE_HDR_LOG2
+#define BIFPLR2_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR2_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR2_PCIE_HDR_LOG3
+#define BIFPLR2_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR2_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR2_PCIE_ROOT_ERR_CMD
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                     0x0
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                                 0x1
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                    0x2
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                       0x00000001L
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                   0x00000002L
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                      0x00000004L
+//BIFPLR2_PCIE_ROOT_ERR_STATUS
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                               0x1
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                          0x2
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                     0x3
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                        0x4
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                          0x5
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                             0x6
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                              0x1b
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                      0x00000001L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                                 0x00000002L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                            0x00000004L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                       0x00000008L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                          0x00000010L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                            0x00000020L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                               0x00000040L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                                0xF8000000L
+//BIFPLR2_PCIE_ERR_SRC_ID
+#define BIFPLR2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                       0x0
+#define BIFPLR2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                             0x10
+#define BIFPLR2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                               0xFFFF0000L
+//BIFPLR2_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR2_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR2_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR2_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR2_PCIE_LINK_CNTL3
+#define BIFPLR2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                  0x0
+#define BIFPLR2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                          0x1
+#define BIFPLR2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                    0x00000001L
+#define BIFPLR2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                            0x00000002L
+//BIFPLR2_PCIE_LANE_ERROR_STATUS
+#define BIFPLR2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                         0x0
+#define BIFPLR2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                           0x0000FFFFL
+//BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR2_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR2_PCIE_ACS_CAP
+#define BIFPLR2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                        0x0
+#define BIFPLR2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                     0x1
+#define BIFPLR2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                     0x2
+#define BIFPLR2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                  0x3
+#define BIFPLR2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                      0x4
+#define BIFPLR2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                       0x5
+#define BIFPLR2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                    0x6
+#define BIFPLR2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                               0x8
+#define BIFPLR2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                          0x0001L
+#define BIFPLR2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                       0x0002L
+#define BIFPLR2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                       0x0004L
+#define BIFPLR2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                    0x0008L
+#define BIFPLR2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                        0x0010L
+#define BIFPLR2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                         0x0020L
+#define BIFPLR2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                      0x0040L
+#define BIFPLR2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                                 0xFF00L
+//BIFPLR2_PCIE_ACS_CNTL
+#define BIFPLR2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                                 0x1
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                                 0x2
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                              0x3
+#define BIFPLR2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                  0x4
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                   0x5
+#define BIFPLR2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                                0x6
+#define BIFPLR2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                      0x0001L
+#define BIFPLR2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                   0x0002L
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                   0x0004L
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                                0x0008L
+#define BIFPLR2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                    0x0010L
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                     0x0020L
+#define BIFPLR2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                  0x0040L
+//BIFPLR2_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR2_PCIE_MC_CAP
+#define BIFPLR2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                              0x0
+#define BIFPLR2_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                           0x8
+#define BIFPLR2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                        0xf
+#define BIFPLR2_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                                0x003FL
+#define BIFPLR2_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                             0x3F00L
+#define BIFPLR2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                          0x8000L
+//BIFPLR2_PCIE_MC_CNTL
+#define BIFPLR2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                             0x0
+#define BIFPLR2_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                                0xf
+#define BIFPLR2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                               0x003FL
+#define BIFPLR2_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                  0x8000L
+//BIFPLR2_PCIE_MC_ADDR0
+#define BIFPLR2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                            0x0
+#define BIFPLR2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                          0xc
+#define BIFPLR2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                              0x0000003FL
+#define BIFPLR2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                            0xFFFFF000L
+//BIFPLR2_PCIE_MC_ADDR1
+#define BIFPLR2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                          0x0
+#define BIFPLR2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                            0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_RCV0
+#define BIFPLR2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                             0x0
+#define BIFPLR2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                               0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_RCV1
+#define BIFPLR2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                             0x0
+#define BIFPLR2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                               0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_BLOCK_ALL0
+#define BIFPLR2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                     0x0
+#define BIFPLR2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_BLOCK_ALL1
+#define BIFPLR2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                     0x0
+#define BIFPLR2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                  0x0
+#define BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                    0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                  0x0
+#define BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                    0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                  0x0
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                                 0x6
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                    0x0000003FL
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                   0xFFFFFFC0L
+//BIFPLR2_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                                 0x0
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                   0xFFFFFFFFL
+//BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR2_PCIE_L1_PM_SUB_CAP
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                              0x0
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                              0x1
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                                0x2
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                                0x3
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                                0x4
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                               0x8
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                              0x10
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                              0x13
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                                0x00000001L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                                0x00000002L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                  0x00000004L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                  0x00000008L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                  0x00000010L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                                 0x0000FF00L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                                0x00030000L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                                0x00F80000L
+//BIFPLR2_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                    0x1
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                      0x2
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                      0x3
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                          0x8
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                          0x1d
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                      0x00000001L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                      0x00000002L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                        0x00000004L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                        0x00000008L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                            0x0000FF00L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                            0xE0000000L
+//BIFPLR2_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                                 0x0
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                                 0x3
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                   0x00000003L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                   0x000000F8L
+//BIFPLR2_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR2_PCIE_DPC_CAP_LIST
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                               0x5
+#define BIFPLR2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                              0x6
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                   0x7
+#define BIFPLR2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                     0x8
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                               0xc
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                      0x001FL
+#define BIFPLR2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                                 0x0020L
+#define BIFPLR2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                                0x0040L
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                     0x0080L
+#define BIFPLR2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                       0x0F00L
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                                 0x1000L
+//BIFPLR2_PCIE_DPC_CNTL
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                      0x0
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                  0x2
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                    0x3
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                      0x4
+#define BIFPLR2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                     0x5
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                    0x6
+#define BIFPLR2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                                0x7
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                        0x0003L
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                    0x0004L
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                      0x0008L
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                        0x0010L
+#define BIFPLR2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                       0x0020L
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                      0x0040L
+#define BIFPLR2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                  0x0080L
+//BIFPLR2_PCIE_DPC_STATUS
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                    0x1
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                  0x3
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                           0x4
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                          0x5
+#define BIFPLR2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                            0x8
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                      0x0001L
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                      0x0006L
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                    0x0008L
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                             0x0010L
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                            0x0060L
+#define BIFPLR2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                              0x1F00L
+//BIFPLR2_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                          0x0
+#define BIFPLR2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                            0xFFFFL
+//BIFPLR2_PCIE_RP_PIO_STATUS
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR2_PCIE_RP_PIO_MASK
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                           0x0
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                           0x1
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                              0x2
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                            0x8
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                            0x9
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                               0xa
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                           0x10
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                           0x11
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                              0x12
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                             0x00000001L
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                             0x00000002L
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                                0x00000004L
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                              0x00000100L
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                              0x00000200L
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                                 0x00000400L
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                             0x00010000L
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                             0x00020000L
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                                0x00040000L
+//BIFPLR2_PCIE_RP_PIO_SEVERITY
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR2_PCIE_RP_PIO_SYSERROR
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR2_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                      0x0
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                      0x1
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                         0x2
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                       0x8
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                       0x9
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                          0xa
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                      0x10
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                      0x11
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                         0x12
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                        0x00000001L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                        0x00000002L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                           0x00000004L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                         0x00000100L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                         0x00000200L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                            0x00000400L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                        0x00010000L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                        0x00020000L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                           0x00040000L
+//BIFPLR2_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR2_PCIE_ESM_CAP_LIST
+#define BIFPLR2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                             0x10
+#define BIFPLR2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                            0x14
+#define BIFPLR2_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                                0x0000FFFFL
+#define BIFPLR2_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                               0x000F0000L
+#define BIFPLR2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                              0xFFF00000L
+//BIFPLR2_PCIE_ESM_HEADER_1
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                       0x0
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                         0x10
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                         0x14
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                           0x000F0000L
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                           0xFFF00000L
+//BIFPLR2_PCIE_ESM_HEADER_2
+#define BIFPLR2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR2_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                                0xFFFFL
+//BIFPLR2_PCIE_ESM_STATUS
+#define BIFPLR2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                  0x9
+#define BIFPLR2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                      0x01FFL
+#define BIFPLR2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                    0x0E00L
+//BIFPLR2_PCIE_ESM_CTRL
+#define BIFPLR2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                             0xf
+#define BIFPLR2_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                               0x8000L
+//BIFPLR2_PCIE_ESM_CAP_1
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                               0x0
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                               0x1
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                               0x2
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                               0x3
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                               0x4
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                               0x5
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                               0x6
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                               0x7
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                               0x8
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                               0x9
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                               0xa
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                               0xb
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                               0xc
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                               0xd
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                               0xe
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                               0xf
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                               0x10
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                               0x11
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                               0x12
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                               0x13
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                              0x14
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                              0x15
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                              0x16
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                              0x17
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                              0x18
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                              0x19
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                              0x1a
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                              0x1b
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                              0x1c
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                              0x1d
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                                 0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                                 0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                                 0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                                 0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                                 0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                                 0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                                 0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                                 0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                                 0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                                 0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                                 0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                                 0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                                 0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                                 0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                                 0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                                 0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                                 0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                                 0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                                 0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                                 0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                                0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                                0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                                0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                                0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                                0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                                0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                                0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                                0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                                0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                                0x20000000L
+//BIFPLR2_PCIE_ESM_CAP_2
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                              0x0
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                              0x1
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                              0x2
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                              0x3
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                              0x4
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                              0x5
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                              0x6
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                              0x7
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                              0x8
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                              0x9
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                              0xa
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                              0xb
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                              0xc
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                              0xd
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                              0xe
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                              0xf
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                              0x10
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                              0x11
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                              0x12
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                              0x13
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                              0x14
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                              0x15
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                              0x16
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                              0x17
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                              0x18
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                              0x19
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                              0x1a
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                              0x1b
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                              0x1c
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                              0x1d
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                                0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                                0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                                0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                                0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                                0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                                0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                                0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                                0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                                0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                                0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                                0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                                0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                                0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                                0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                                0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                                0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                                0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                                0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                                0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                                0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                                0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                                0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                                0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                                0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                                0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                                0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                                0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                                0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                                0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                                0x20000000L
+//BIFPLR2_PCIE_ESM_CAP_3
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                              0x0
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                              0x1
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                              0x2
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                              0x3
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                              0x4
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                              0x5
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                              0x6
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                              0x7
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                              0x8
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                              0x9
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                              0xa
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                              0xb
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                              0xc
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                              0xd
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                              0xe
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                              0xf
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                              0x10
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                              0x11
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                              0x12
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                              0x13
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                                0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                                0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                                0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                                0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                                0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                                0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                                0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                                0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                                0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                                0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                                0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                                0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                                0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                                0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                                0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                                0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                                0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                                0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                                0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                                0x00080000L
+//BIFPLR2_PCIE_ESM_CAP_4
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                              0x0
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                              0x1
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                              0x2
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                              0x3
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                              0x4
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                              0x5
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                              0x6
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                              0x7
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                              0x8
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                              0x9
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                              0xa
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                              0xb
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                              0xc
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                              0xd
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                              0xe
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                              0xf
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                              0x10
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                              0x11
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                              0x12
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                              0x13
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                              0x14
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                              0x15
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                              0x16
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                              0x17
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                              0x18
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                              0x19
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                              0x1a
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                              0x1b
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                              0x1c
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                              0x1d
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                                0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                                0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                                0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                                0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                                0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                                0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                                0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                                0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                                0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                                0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                                0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                                0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                                0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                                0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                                0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                                0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                                0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                                0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                                0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                                0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                                0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                                0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                                0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                                0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                                0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                                0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                                0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                                0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                                0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                                0x20000000L
+//BIFPLR2_PCIE_ESM_CAP_5
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                              0x0
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                              0x1
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                              0x2
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                              0x3
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                              0x4
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                              0x5
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                              0x6
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                              0x7
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                              0x8
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                              0x9
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                              0xa
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                              0xb
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                              0xc
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                              0xd
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                              0xe
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                              0xf
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                              0x10
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                              0x11
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                              0x12
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                              0x13
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                              0x14
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                              0x15
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                              0x16
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                              0x17
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                              0x18
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                              0x19
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                              0x1a
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                              0x1b
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                              0x1c
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                              0x1d
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                                0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                                0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                                0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                                0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                                0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                                0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                                0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                                0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                                0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                                0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                                0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                                0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                                0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                                0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                                0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                                0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                                0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                                0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                                0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                                0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                                0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                                0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                                0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                                0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                                0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                                0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                                0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                                0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                                0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                                0x20000000L
+//BIFPLR2_PCIE_ESM_CAP_6
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                              0x0
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                              0x1
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                              0x2
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                              0x3
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                              0x4
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                              0x5
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                              0x6
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                              0x7
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                              0x8
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                              0x9
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                              0xa
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                              0xb
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                              0xc
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                              0xd
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                              0xe
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                              0xf
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                              0x10
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                              0x11
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                              0x12
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                              0x13
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                              0x14
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                              0x15
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                              0x16
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                              0x17
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                              0x18
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                              0x19
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                              0x1a
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                              0x1b
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                              0x1c
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                              0x1d
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                                0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                                0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                                0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                                0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                                0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                                0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                                0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                                0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                                0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                                0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                                0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                                0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                                0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                                0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                                0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                                0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                                0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                                0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                                0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                                0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                                0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                                0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                                0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                                0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                                0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                                0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                                0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                                0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                                0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                                0x20000000L
+//BIFPLR2_PCIE_ESM_CAP_7
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                              0x0
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                              0x1
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                              0x2
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                              0x3
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                              0x4
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                              0x5
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                              0x6
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                              0x7
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                              0x8
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                              0x9
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                              0xa
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                              0xb
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                              0xc
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                              0xd
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                              0xe
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                              0xf
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                              0x10
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                              0x11
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                              0x12
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                              0x13
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                              0x14
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                              0x15
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                              0x16
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                              0x17
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                              0x18
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                              0x19
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                              0x1a
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                              0x1b
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                              0x1c
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                              0x1d
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                              0x1e
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                                0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                                0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                                0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                                0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                                0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                                0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                                0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                                0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                                0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                                0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                                0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                                0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                                0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                                0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                                0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                                0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                                0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                                0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                                0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                                0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                                0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                                0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                                0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                                0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                                0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                                0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                                0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                                0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                                0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                                0x20000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                                0x40000000L
+//BIFPLR2_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR2_DATA_LINK_FEATURE_CAP
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                         0x0
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                        0x1
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                             0x1f
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                           0x00000001L
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                          0x007FFFFEL
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                               0x80000000L
+//BIFPLR2_DATA_LINK_FEATURE_STATUS
+#define BIFPLR2_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                         0x0
+#define BIFPLR2_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                   0x1f
+#define BIFPLR2_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                           0x007FFFFFL
+#define BIFPLR2_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                     0x80000000L
+//BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                    0x10
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                   0x14
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                      0x000F0000L
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                     0xFFF00000L
+//BIFPLR2_LINK_CAP_16GT
+#define BIFPLR2_LINK_CAP_16GT__RESERVED__SHIFT                                                                0x0
+#define BIFPLR2_LINK_CAP_16GT__RESERVED_MASK                                                                  0xFFFFFFFFL
+//BIFPLR2_LINK_CNTL_16GT
+#define BIFPLR2_LINK_CNTL_16GT__RESERVED__SHIFT                                                               0x0
+#define BIFPLR2_LINK_CNTL_16GT__RESERVED_MASK                                                                 0xFFFFFFFFL
+//BIFPLR2_LINK_STATUS_16GT
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                           0x0
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                     0x1
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                     0x2
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                     0x3
+#define BIFPLR2_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                       0x4
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                             0x00000001L
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                       0x00000002L
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                       0x00000004L
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                       0x00000008L
+#define BIFPLR2_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                         0x00000010L
+//BIFPLR2_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR2_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR2_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR2_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR2_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR2_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR2_MARGINING_PORT_CAP
+#define BIFPLR2_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                            0x0
+#define BIFPLR2_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                              0x0001L
+//BIFPLR2_MARGINING_PORT_STATUS
+#define BIFPLR2_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                                 0x0
+#define BIFPLR2_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                        0x1
+#define BIFPLR2_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                   0x0001L
+#define BIFPLR2_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                          0x0002L
+//BIFPLR2_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR2_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR2_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR2_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR2_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR2_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR2_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR2_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR2_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR2_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR2_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR2_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR2_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR2_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR2_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR2_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR2_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR2_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR2_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR2_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR2_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_PCIE_CCIX_CAP_LIST
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                            0x10
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                           0x14
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                               0x0000FFFFL
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                              0x000F0000L
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                             0xFFF00000L
+//BIFPLR2_PCIE_CCIX_HEADER_1
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR2_PCIE_CCIX_HEADER_2
+#define BIFPLR2_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR2_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                               0xFFFFL
+//BIFPLR2_PCIE_CCIX_CAP
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                      0x0
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                         0x1
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                        0x3
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                    0x4
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                          0x8
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                        0x0001L
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                           0x0006L
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                          0x0008L
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                      0x0070L
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                            0x0700L
+//BIFPLR2_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                              0x0
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                                0x1
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                                0x2
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                               0x5
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                               0x9
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                               0xe
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                                0x00000001L
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                  0x00000002L
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                  0x00000004L
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                                 0x00000020L
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                                 0x00000200L
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                                 0x00004000L
+//BIFPLR2_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR2_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                       0x0
+#define BIFPLR2_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIFPLR2_PCIE_CCIX_ESM_STATUS
+#define BIFPLR2_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                            0x0
+#define BIFPLR2_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                         0x7
+#define BIFPLR2_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                              0x0000007FL
+#define BIFPLR2_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                           0x00000080L
+//BIFPLR2_PCIE_CCIX_ESM_CNTL
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                     0x0
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                            0x7
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                     0x8
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                         0xf
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                           0x10
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                           0x14
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                  0x18
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                    0x19
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                              0x1a
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                       0x0000007FL
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                              0x00000080L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                       0x00007F00L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                           0x00008000L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                             0x00070000L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                             0x00700000L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                    0x01000000L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                      0x02000000L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                                0x1C000000L
+//BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_PCIE_CCIX_TRANS_CAP
+#define BIFPLR2_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                                 0x0
+#define BIFPLR2_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                   0x00000001L
+//BIFPLR2_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR2_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                                 0x0
+#define BIFPLR2_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                   0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+//BIFPLR3_VENDOR_ID
+#define BIFPLR3_VENDOR_ID__VENDOR_ID__SHIFT                                                                   0x0
+#define BIFPLR3_VENDOR_ID__VENDOR_ID_MASK                                                                     0xFFFFL
+//BIFPLR3_DEVICE_ID
+#define BIFPLR3_DEVICE_ID__DEVICE_ID__SHIFT                                                                   0x0
+#define BIFPLR3_DEVICE_ID__DEVICE_ID_MASK                                                                     0xFFFFL
+//BIFPLR3_COMMAND
+#define BIFPLR3_COMMAND__IO_ACCESS_EN__SHIFT                                                                  0x0
+#define BIFPLR3_COMMAND__MEM_ACCESS_EN__SHIFT                                                                 0x1
+#define BIFPLR3_COMMAND__BUS_MASTER_EN__SHIFT                                                                 0x2
+#define BIFPLR3_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                              0x3
+#define BIFPLR3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                       0x4
+#define BIFPLR3_COMMAND__PAL_SNOOP_EN__SHIFT                                                                  0x5
+#define BIFPLR3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                         0x6
+#define BIFPLR3_COMMAND__AD_STEPPING__SHIFT                                                                   0x7
+#define BIFPLR3_COMMAND__SERR_EN__SHIFT                                                                       0x8
+#define BIFPLR3_COMMAND__FAST_B2B_EN__SHIFT                                                                   0x9
+#define BIFPLR3_COMMAND__INT_DIS__SHIFT                                                                       0xa
+#define BIFPLR3_COMMAND__IO_ACCESS_EN_MASK                                                                    0x0001L
+#define BIFPLR3_COMMAND__MEM_ACCESS_EN_MASK                                                                   0x0002L
+#define BIFPLR3_COMMAND__BUS_MASTER_EN_MASK                                                                   0x0004L
+#define BIFPLR3_COMMAND__SPECIAL_CYCLE_EN_MASK                                                                0x0008L
+#define BIFPLR3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                         0x0010L
+#define BIFPLR3_COMMAND__PAL_SNOOP_EN_MASK                                                                    0x0020L
+#define BIFPLR3_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                           0x0040L
+#define BIFPLR3_COMMAND__AD_STEPPING_MASK                                                                     0x0080L
+#define BIFPLR3_COMMAND__SERR_EN_MASK                                                                         0x0100L
+#define BIFPLR3_COMMAND__FAST_B2B_EN_MASK                                                                     0x0200L
+#define BIFPLR3_COMMAND__INT_DIS_MASK                                                                         0x0400L
+//BIFPLR3_STATUS
+#define BIFPLR3_STATUS__IMMEDIATE_READINESS__SHIFT                                                            0x0
+#define BIFPLR3_STATUS__INT_STATUS__SHIFT                                                                     0x3
+#define BIFPLR3_STATUS__CAP_LIST__SHIFT                                                                       0x4
+#define BIFPLR3_STATUS__PCI_66_CAP__SHIFT                                                                     0x5
+#define BIFPLR3_STATUS__FAST_BACK_CAPABLE__SHIFT                                                              0x7
+#define BIFPLR3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                       0x8
+#define BIFPLR3_STATUS__DEVSEL_TIMING__SHIFT                                                                  0x9
+#define BIFPLR3_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                            0xb
+#define BIFPLR3_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                          0xc
+#define BIFPLR3_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                          0xd
+#define BIFPLR3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                          0xe
+#define BIFPLR3_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                          0xf
+#define BIFPLR3_STATUS__IMMEDIATE_READINESS_MASK                                                              0x0001L
+#define BIFPLR3_STATUS__INT_STATUS_MASK                                                                       0x0008L
+#define BIFPLR3_STATUS__CAP_LIST_MASK                                                                         0x0010L
+#define BIFPLR3_STATUS__PCI_66_CAP_MASK                                                                       0x0020L
+#define BIFPLR3_STATUS__FAST_BACK_CAPABLE_MASK                                                                0x0080L
+#define BIFPLR3_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                         0x0100L
+#define BIFPLR3_STATUS__DEVSEL_TIMING_MASK                                                                    0x0600L
+#define BIFPLR3_STATUS__SIGNAL_TARGET_ABORT_MASK                                                              0x0800L
+#define BIFPLR3_STATUS__RECEIVED_TARGET_ABORT_MASK                                                            0x1000L
+#define BIFPLR3_STATUS__RECEIVED_MASTER_ABORT_MASK                                                            0x2000L
+#define BIFPLR3_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                            0x4000L
+#define BIFPLR3_STATUS__PARITY_ERROR_DETECTED_MASK                                                            0x8000L
+//BIFPLR3_REVISION_ID
+#define BIFPLR3_REVISION_ID__MINOR_REV_ID__SHIFT                                                              0x0
+#define BIFPLR3_REVISION_ID__MAJOR_REV_ID__SHIFT                                                              0x4
+#define BIFPLR3_REVISION_ID__MINOR_REV_ID_MASK                                                                0x0FL
+#define BIFPLR3_REVISION_ID__MAJOR_REV_ID_MASK                                                                0xF0L
+//BIFPLR3_PROG_INTERFACE
+#define BIFPLR3_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                         0x0
+#define BIFPLR3_PROG_INTERFACE__PROG_INTERFACE_MASK                                                           0xFFL
+//BIFPLR3_SUB_CLASS
+#define BIFPLR3_SUB_CLASS__SUB_CLASS__SHIFT                                                                   0x0
+#define BIFPLR3_SUB_CLASS__SUB_CLASS_MASK                                                                     0xFFL
+//BIFPLR3_BASE_CLASS
+#define BIFPLR3_BASE_CLASS__BASE_CLASS__SHIFT                                                                 0x0
+#define BIFPLR3_BASE_CLASS__BASE_CLASS_MASK                                                                   0xFFL
+//BIFPLR3_CACHE_LINE
+#define BIFPLR3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                            0x0
+#define BIFPLR3_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                              0xFFL
+//BIFPLR3_LATENCY
+#define BIFPLR3_LATENCY__LATENCY_TIMER__SHIFT                                                                 0x0
+#define BIFPLR3_LATENCY__LATENCY_TIMER_MASK                                                                   0xFFL
+//BIFPLR3_HEADER
+#define BIFPLR3_HEADER__HEADER_TYPE__SHIFT                                                                    0x0
+#define BIFPLR3_HEADER__DEVICE_TYPE__SHIFT                                                                    0x7
+#define BIFPLR3_HEADER__HEADER_TYPE_MASK                                                                      0x7FL
+#define BIFPLR3_HEADER__DEVICE_TYPE_MASK                                                                      0x80L
+//BIFPLR3_BIST
+#define BIFPLR3_BIST__BIST_COMP__SHIFT                                                                        0x0
+#define BIFPLR3_BIST__BIST_STRT__SHIFT                                                                        0x6
+#define BIFPLR3_BIST__BIST_CAP__SHIFT                                                                         0x7
+#define BIFPLR3_BIST__BIST_COMP_MASK                                                                          0x0FL
+#define BIFPLR3_BIST__BIST_STRT_MASK                                                                          0x40L
+#define BIFPLR3_BIST__BIST_CAP_MASK                                                                           0x80L
+//BIFPLR3_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                    0x0
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                  0x8
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                    0x10
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                        0x18
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                      0x000000FFL
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                    0x0000FF00L
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                      0x00FF0000L
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                          0xFF000000L
+//BIFPLR3_IO_BASE_LIMIT
+#define BIFPLR3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                            0x0
+#define BIFPLR3_IO_BASE_LIMIT__IO_BASE__SHIFT                                                                 0x4
+#define BIFPLR3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                           0x8
+#define BIFPLR3_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                                0xc
+#define BIFPLR3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                              0x000FL
+#define BIFPLR3_IO_BASE_LIMIT__IO_BASE_MASK                                                                   0x00F0L
+#define BIFPLR3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                             0x0F00L
+#define BIFPLR3_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                  0xF000L
+//BIFPLR3_SECONDARY_STATUS
+#define BIFPLR3_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIFPLR3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIFPLR3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIFPLR3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIFPLR3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIFPLR3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIFPLR3_SECONDARY_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIFPLR3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIFPLR3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIFPLR3_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIFPLR3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIFPLR3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIFPLR3_MEM_BASE_LIMIT
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                         0x4
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                         0x10
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                        0x14
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                            0x0000000FL
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                           0x0000FFF0L
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                           0x000F0000L
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                          0xFFF00000L
+//BIFPLR3_PREF_BASE_LIMIT
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                    0x0
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                   0x4
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                   0x10
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                  0x14
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                      0x0000000FL
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                     0x0000FFF0L
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                     0x000F0000L
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                    0xFFF00000L
+//BIFPLR3_PREF_BASE_UPPER
+#define BIFPLR3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                       0x0
+#define BIFPLR3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                         0xFFFFFFFFL
+//BIFPLR3_PREF_LIMIT_UPPER
+#define BIFPLR3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                     0x0
+#define BIFPLR3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_IO_BASE_LIMIT_HI
+#define BIFPLR3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                        0x0
+#define BIFPLR3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                       0x10
+#define BIFPLR3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                          0x0000FFFFL
+#define BIFPLR3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                         0xFFFF0000L
+//BIFPLR3_CAP_PTR
+#define BIFPLR3_CAP_PTR__CAP_PTR__SHIFT                                                                       0x0
+#define BIFPLR3_CAP_PTR__CAP_PTR_MASK                                                                         0xFFL
+//BIFPLR3_ROM_BASE_ADDR
+#define BIFPLR3_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                               0x0
+#define BIFPLR3_ROM_BASE_ADDR__BASE_ADDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR3_INTERRUPT_LINE
+#define BIFPLR3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                         0x0
+#define BIFPLR3_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                           0xFFL
+//BIFPLR3_INTERRUPT_PIN
+#define BIFPLR3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                           0x0
+#define BIFPLR3_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                             0xFFL
+//BIFPLR3_IRQ_BRIDGE_CNTL
+#define BIFPLR3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                    0x0
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                               0x1
+#define BIFPLR3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                                0x2
+#define BIFPLR3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                                0x3
+#define BIFPLR3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                               0x4
+#define BIFPLR3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                     0x5
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                   0x6
+#define BIFPLR3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                           0x7
+#define BIFPLR3_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                                 0x8
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                               0x9
+#define BIFPLR3_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                  0xa
+#define BIFPLR3_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                             0xb
+#define BIFPLR3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                      0x0001L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                                 0x0002L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                  0x0004L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                  0x0008L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                                 0x0010L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                       0x0020L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                     0x0040L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                             0x0080L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                   0x0100L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                                 0x0200L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                    0x0400L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                               0x0800L
+//BIFPLR3_EXT_BRIDGE_CNTL
+#define BIFPLR3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                         0x0
+#define BIFPLR3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                           0x01L
+//BIFPLR3_VENDOR_CAP_LIST
+#define BIFPLR3_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR3_VENDOR_CAP_LIST__LENGTH__SHIFT                                                                0x10
+#define BIFPLR3_VENDOR_CAP_LIST__CAP_ID_MASK                                                                  0x000000FFL
+#define BIFPLR3_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                                0x0000FF00L
+#define BIFPLR3_VENDOR_CAP_LIST__LENGTH_MASK                                                                  0x00FF0000L
+//BIFPLR3_ADAPTER_ID_W
+#define BIFPLR3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                      0x0
+#define BIFPLR3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                             0x10
+#define BIFPLR3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                               0xFFFF0000L
+//BIFPLR3_PMI_CAP_LIST
+#define BIFPLR3_PMI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR3_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR3_PMI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR3_PMI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR3_PMI_CAP
+#define BIFPLR3_PMI_CAP__VERSION__SHIFT                                                                       0x0
+#define BIFPLR3_PMI_CAP__PME_CLOCK__SHIFT                                                                     0x3
+#define BIFPLR3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                           0x4
+#define BIFPLR3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                             0x5
+#define BIFPLR3_PMI_CAP__AUX_CURRENT__SHIFT                                                                   0x6
+#define BIFPLR3_PMI_CAP__D1_SUPPORT__SHIFT                                                                    0x9
+#define BIFPLR3_PMI_CAP__D2_SUPPORT__SHIFT                                                                    0xa
+#define BIFPLR3_PMI_CAP__PME_SUPPORT__SHIFT                                                                   0xb
+#define BIFPLR3_PMI_CAP__VERSION_MASK                                                                         0x0007L
+#define BIFPLR3_PMI_CAP__PME_CLOCK_MASK                                                                       0x0008L
+#define BIFPLR3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                             0x0010L
+#define BIFPLR3_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                               0x0020L
+#define BIFPLR3_PMI_CAP__AUX_CURRENT_MASK                                                                     0x01C0L
+#define BIFPLR3_PMI_CAP__D1_SUPPORT_MASK                                                                      0x0200L
+#define BIFPLR3_PMI_CAP__D2_SUPPORT_MASK                                                                      0x0400L
+#define BIFPLR3_PMI_CAP__PME_SUPPORT_MASK                                                                     0xF800L
+//BIFPLR3_PMI_STATUS_CNTL
+#define BIFPLR3_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                           0x0
+#define BIFPLR3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                         0x3
+#define BIFPLR3_PMI_STATUS_CNTL__PME_EN__SHIFT                                                                0x8
+#define BIFPLR3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                           0x9
+#define BIFPLR3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                            0xd
+#define BIFPLR3_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                            0xf
+#define BIFPLR3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                         0x16
+#define BIFPLR3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                            0x17
+#define BIFPLR3_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                              0x18
+#define BIFPLR3_PMI_STATUS_CNTL__POWER_STATE_MASK                                                             0x00000003L
+#define BIFPLR3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                           0x00000008L
+#define BIFPLR3_PMI_STATUS_CNTL__PME_EN_MASK                                                                  0x00000100L
+#define BIFPLR3_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                             0x00001E00L
+#define BIFPLR3_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                              0x00006000L
+#define BIFPLR3_PMI_STATUS_CNTL__PME_STATUS_MASK                                                              0x00008000L
+#define BIFPLR3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                           0x00400000L
+#define BIFPLR3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                              0x00800000L
+#define BIFPLR3_PMI_STATUS_CNTL__PMI_DATA_MASK                                                                0xFF000000L
+//BIFPLR3_PCIE_CAP_LIST
+#define BIFPLR3_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR3_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR3_PCIE_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR3_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR3_PCIE_CAP
+#define BIFPLR3_PCIE_CAP__VERSION__SHIFT                                                                      0x0
+#define BIFPLR3_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                  0x4
+#define BIFPLR3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                             0x8
+#define BIFPLR3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                              0x9
+#define BIFPLR3_PCIE_CAP__VERSION_MASK                                                                        0x000FL
+#define BIFPLR3_PCIE_CAP__DEVICE_TYPE_MASK                                                                    0x00F0L
+#define BIFPLR3_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                               0x0100L
+#define BIFPLR3_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                                0x3E00L
+//BIFPLR3_DEVICE_CAP
+#define BIFPLR3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                        0x0
+#define BIFPLR3_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                               0x3
+#define BIFPLR3_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                               0x5
+#define BIFPLR3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                     0x6
+#define BIFPLR3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                      0x9
+#define BIFPLR3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                   0xf
+#define BIFPLR3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                  0x12
+#define BIFPLR3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                  0x1a
+#define BIFPLR3_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                                0x1c
+#define BIFPLR3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                          0x00000007L
+#define BIFPLR3_DEVICE_CAP__PHANTOM_FUNC_MASK                                                                 0x00000018L
+#define BIFPLR3_DEVICE_CAP__EXTENDED_TAG_MASK                                                                 0x00000020L
+#define BIFPLR3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                       0x000001C0L
+#define BIFPLR3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                        0x00000E00L
+#define BIFPLR3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                     0x00008000L
+#define BIFPLR3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                    0x03FC0000L
+#define BIFPLR3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                    0x0C000000L
+#define BIFPLR3_DEVICE_CAP__FLR_CAPABLE_MASK                                                                  0x10000000L
+//BIFPLR3_DEVICE_CNTL
+#define BIFPLR3_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                               0x0
+#define BIFPLR3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                          0x1
+#define BIFPLR3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                              0x2
+#define BIFPLR3_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                             0x3
+#define BIFPLR3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                            0x4
+#define BIFPLR3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                          0x5
+#define BIFPLR3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                           0x8
+#define BIFPLR3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                           0x9
+#define BIFPLR3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                           0xa
+#define BIFPLR3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                               0xb
+#define BIFPLR3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                     0xc
+#define BIFPLR3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                       0xf
+#define BIFPLR3_DEVICE_CNTL__CORR_ERR_EN_MASK                                                                 0x0001L
+#define BIFPLR3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                            0x0002L
+#define BIFPLR3_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                                0x0004L
+#define BIFPLR3_DEVICE_CNTL__USR_REPORT_EN_MASK                                                               0x0008L
+#define BIFPLR3_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                              0x0010L
+#define BIFPLR3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                            0x00E0L
+#define BIFPLR3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                             0x0100L
+#define BIFPLR3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                             0x0200L
+#define BIFPLR3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                             0x0400L
+#define BIFPLR3_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                                 0x0800L
+#define BIFPLR3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                       0x7000L
+#define BIFPLR3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                         0x8000L
+//BIFPLR3_DEVICE_STATUS
+#define BIFPLR3_DEVICE_STATUS__CORR_ERR__SHIFT                                                                0x0
+#define BIFPLR3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                           0x1
+#define BIFPLR3_DEVICE_STATUS__FATAL_ERR__SHIFT                                                               0x2
+#define BIFPLR3_DEVICE_STATUS__USR_DETECTED__SHIFT                                                            0x3
+#define BIFPLR3_DEVICE_STATUS__AUX_PWR__SHIFT                                                                 0x4
+#define BIFPLR3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                       0x5
+#define BIFPLR3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                           0x6
+#define BIFPLR3_DEVICE_STATUS__CORR_ERR_MASK                                                                  0x0001L
+#define BIFPLR3_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                             0x0002L
+#define BIFPLR3_DEVICE_STATUS__FATAL_ERR_MASK                                                                 0x0004L
+#define BIFPLR3_DEVICE_STATUS__USR_DETECTED_MASK                                                              0x0008L
+#define BIFPLR3_DEVICE_STATUS__AUX_PWR_MASK                                                                   0x0010L
+#define BIFPLR3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                         0x0020L
+#define BIFPLR3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                             0x0040L
+//BIFPLR3_LINK_CAP
+#define BIFPLR3_LINK_CAP__LINK_SPEED__SHIFT                                                                   0x0
+#define BIFPLR3_LINK_CAP__LINK_WIDTH__SHIFT                                                                   0x4
+#define BIFPLR3_LINK_CAP__PM_SUPPORT__SHIFT                                                                   0xa
+#define BIFPLR3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                             0xc
+#define BIFPLR3_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                              0xf
+#define BIFPLR3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                       0x12
+#define BIFPLR3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                  0x13
+#define BIFPLR3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                  0x14
+#define BIFPLR3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                     0x15
+#define BIFPLR3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                  0x16
+#define BIFPLR3_LINK_CAP__PORT_NUMBER__SHIFT                                                                  0x18
+#define BIFPLR3_LINK_CAP__LINK_SPEED_MASK                                                                     0x0000000FL
+#define BIFPLR3_LINK_CAP__LINK_WIDTH_MASK                                                                     0x000003F0L
+#define BIFPLR3_LINK_CAP__PM_SUPPORT_MASK                                                                     0x00000C00L
+#define BIFPLR3_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                               0x00007000L
+#define BIFPLR3_LINK_CAP__L1_EXIT_LATENCY_MASK                                                                0x00038000L
+#define BIFPLR3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                         0x00040000L
+#define BIFPLR3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                    0x00080000L
+#define BIFPLR3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                    0x00100000L
+#define BIFPLR3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                       0x00200000L
+#define BIFPLR3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                    0x00400000L
+#define BIFPLR3_LINK_CAP__PORT_NUMBER_MASK                                                                    0xFF000000L
+//BIFPLR3_LINK_CNTL
+#define BIFPLR3_LINK_CNTL__PM_CONTROL__SHIFT                                                                  0x0
+#define BIFPLR3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                           0x3
+#define BIFPLR3_LINK_CNTL__LINK_DIS__SHIFT                                                                    0x4
+#define BIFPLR3_LINK_CNTL__RETRAIN_LINK__SHIFT                                                                0x5
+#define BIFPLR3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                            0x6
+#define BIFPLR3_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                               0x7
+#define BIFPLR3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                   0x8
+#define BIFPLR3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                                 0x9
+#define BIFPLR3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                   0xa
+#define BIFPLR3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                   0xb
+#define BIFPLR3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                       0xe
+#define BIFPLR3_LINK_CNTL__PM_CONTROL_MASK                                                                    0x0003L
+#define BIFPLR3_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                             0x0008L
+#define BIFPLR3_LINK_CNTL__LINK_DIS_MASK                                                                      0x0010L
+#define BIFPLR3_LINK_CNTL__RETRAIN_LINK_MASK                                                                  0x0020L
+#define BIFPLR3_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                              0x0040L
+#define BIFPLR3_LINK_CNTL__EXTENDED_SYNC_MASK                                                                 0x0080L
+#define BIFPLR3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                     0x0100L
+#define BIFPLR3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                   0x0200L
+#define BIFPLR3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                     0x0400L
+#define BIFPLR3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                     0x0800L
+#define BIFPLR3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                         0xC000L
+//BIFPLR3_LINK_STATUS
+#define BIFPLR3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                     0x4
+#define BIFPLR3_LINK_STATUS__LINK_TRAINING__SHIFT                                                             0xb
+#define BIFPLR3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                            0xc
+#define BIFPLR3_LINK_STATUS__DL_ACTIVE__SHIFT                                                                 0xd
+#define BIFPLR3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                                 0xe
+#define BIFPLR3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                                 0xf
+#define BIFPLR3_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                       0x03F0L
+#define BIFPLR3_LINK_STATUS__LINK_TRAINING_MASK                                                               0x0800L
+#define BIFPLR3_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                              0x1000L
+#define BIFPLR3_LINK_STATUS__DL_ACTIVE_MASK                                                                   0x2000L
+#define BIFPLR3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                   0x4000L
+#define BIFPLR3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                   0x8000L
+//BIFPLR3_SLOT_CAP
+#define BIFPLR3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                          0x0
+#define BIFPLR3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                       0x1
+#define BIFPLR3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                           0x2
+#define BIFPLR3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                       0x3
+#define BIFPLR3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                        0x4
+#define BIFPLR3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                             0x5
+#define BIFPLR3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                              0x6
+#define BIFPLR3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                         0x7
+#define BIFPLR3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                         0xf
+#define BIFPLR3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                                0x11
+#define BIFPLR3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                               0x12
+#define BIFPLR3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                            0x13
+#define BIFPLR3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                            0x00000001L
+#define BIFPLR3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                         0x00000002L
+#define BIFPLR3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                             0x00000004L
+#define BIFPLR3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                         0x00000008L
+#define BIFPLR3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                          0x00000010L
+#define BIFPLR3_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                               0x00000020L
+#define BIFPLR3_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                                0x00000040L
+#define BIFPLR3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                           0x00007F80L
+#define BIFPLR3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                           0x00018000L
+#define BIFPLR3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                  0x00020000L
+#define BIFPLR3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                                 0x00040000L
+#define BIFPLR3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                              0xFFF80000L
+//BIFPLR3_SLOT_CNTL
+#define BIFPLR3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                      0x0
+#define BIFPLR3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                       0x1
+#define BIFPLR3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                       0x2
+#define BIFPLR3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                  0x3
+#define BIFPLR3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                   0x4
+#define BIFPLR3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                             0x5
+#define BIFPLR3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                         0x6
+#define BIFPLR3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                          0x8
+#define BIFPLR3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                         0xa
+#define BIFPLR3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                  0xb
+#define BIFPLR3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                         0xc
+#define BIFPLR3_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                                 0xd
+#define BIFPLR3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                        0x0001L
+#define BIFPLR3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                         0x0002L
+#define BIFPLR3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                         0x0004L
+#define BIFPLR3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                    0x0008L
+#define BIFPLR3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                     0x0010L
+#define BIFPLR3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                               0x0020L
+#define BIFPLR3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                           0x00C0L
+#define BIFPLR3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                            0x0300L
+#define BIFPLR3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                           0x0400L
+#define BIFPLR3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                    0x0800L
+#define BIFPLR3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                           0x1000L
+#define BIFPLR3_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                   0x2000L
+//BIFPLR3_SLOT_STATUS
+#define BIFPLR3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                       0x0
+#define BIFPLR3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                        0x1
+#define BIFPLR3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                        0x2
+#define BIFPLR3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                   0x3
+#define BIFPLR3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                         0x4
+#define BIFPLR3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                          0x5
+#define BIFPLR3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                     0x6
+#define BIFPLR3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                              0x7
+#define BIFPLR3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                          0x8
+#define BIFPLR3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                         0x0001L
+#define BIFPLR3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                          0x0002L
+#define BIFPLR3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                          0x0004L
+#define BIFPLR3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                     0x0008L
+#define BIFPLR3_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                           0x0010L
+#define BIFPLR3_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                            0x0020L
+#define BIFPLR3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                       0x0040L
+#define BIFPLR3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                                0x0080L
+#define BIFPLR3_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                            0x0100L
+//BIFPLR3_ROOT_CNTL
+#define BIFPLR3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                         0x0
+#define BIFPLR3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                     0x1
+#define BIFPLR3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                        0x2
+#define BIFPLR3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                             0x3
+#define BIFPLR3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                  0x4
+#define BIFPLR3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                           0x0001L
+#define BIFPLR3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                       0x0002L
+#define BIFPLR3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                          0x0004L
+#define BIFPLR3_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                               0x0008L
+#define BIFPLR3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                    0x0010L
+//BIFPLR3_ROOT_CAP
+#define BIFPLR3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                      0x0
+#define BIFPLR3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                        0x0001L
+//BIFPLR3_ROOT_STATUS
+#define BIFPLR3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                          0x0
+#define BIFPLR3_ROOT_STATUS__PME_STATUS__SHIFT                                                                0x10
+#define BIFPLR3_ROOT_STATUS__PME_PENDING__SHIFT                                                               0x11
+#define BIFPLR3_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR3_ROOT_STATUS__PME_STATUS_MASK                                                                  0x00010000L
+#define BIFPLR3_ROOT_STATUS__PME_PENDING_MASK                                                                 0x00020000L
+//BIFPLR3_DEVICE_CAP2
+#define BIFPLR3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                               0x0
+#define BIFPLR3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                                 0x4
+#define BIFPLR3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                  0x5
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                                0x6
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                                0x7
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                                0x8
+#define BIFPLR3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                    0x9
+#define BIFPLR3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                                 0xa
+#define BIFPLR3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                             0xb
+#define BIFPLR3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                        0xc
+#define BIFPLR3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                             0xe
+#define BIFPLR3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                           0x10
+#define BIFPLR3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                           0x11
+#define BIFPLR3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                            0x12
+#define BIFPLR3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                              0x14
+#define BIFPLR3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                              0x15
+#define BIFPLR3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                  0x16
+#define BIFPLR3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                            0x18
+#define BIFPLR3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                             0x1a
+#define BIFPLR3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                                 0x0000000FL
+#define BIFPLR3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                   0x00000010L
+#define BIFPLR3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                    0x00000020L
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                  0x00000040L
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                  0x00000080L
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                  0x00000100L
+#define BIFPLR3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                      0x00000200L
+#define BIFPLR3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                   0x00000400L
+#define BIFPLR3_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                               0x00000800L
+#define BIFPLR3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                          0x00003000L
+#define BIFPLR3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                               0x0000C000L
+#define BIFPLR3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                             0x00010000L
+#define BIFPLR3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                             0x00020000L
+#define BIFPLR3_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                              0x000C0000L
+#define BIFPLR3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                                0x00100000L
+#define BIFPLR3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                                0x00200000L
+#define BIFPLR3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                    0x00C00000L
+#define BIFPLR3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                              0x03000000L
+#define BIFPLR3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                               0x04000000L
+#define BIFPLR3_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR3_DEVICE_CNTL2
+#define BIFPLR3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                        0x0
+#define BIFPLR3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                          0x4
+#define BIFPLR3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                        0x5
+#define BIFPLR3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                      0x6
+#define BIFPLR3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                                 0x7
+#define BIFPLR3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                       0x8
+#define BIFPLR3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                    0x9
+#define BIFPLR3_DEVICE_CNTL2__LTR_EN__SHIFT                                                                   0xa
+#define BIFPLR3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                             0xb
+#define BIFPLR3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                             0xc
+#define BIFPLR3_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                  0xd
+#define BIFPLR3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                              0xf
+#define BIFPLR3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                          0x000FL
+#define BIFPLR3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                            0x0010L
+#define BIFPLR3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                          0x0020L
+#define BIFPLR3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                        0x0040L
+#define BIFPLR3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                   0x0080L
+#define BIFPLR3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                         0x0100L
+#define BIFPLR3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                      0x0200L
+#define BIFPLR3_DEVICE_CNTL2__LTR_EN_MASK                                                                     0x0400L
+#define BIFPLR3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                               0x0800L
+#define BIFPLR3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                               0x1000L
+#define BIFPLR3_DEVICE_CNTL2__OBFF_EN_MASK                                                                    0x6000L
+#define BIFPLR3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                                0x8000L
+//BIFPLR3_DEVICE_STATUS2
+#define BIFPLR3_DEVICE_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR3_DEVICE_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR3_LINK_CAP2
+#define BIFPLR3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                        0x1
+#define BIFPLR3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                         0x8
+#define BIFPLR3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                    0x10
+#define BIFPLR3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                   0x17
+#define BIFPLR3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                   0x18
+#define BIFPLR3_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                               0x1f
+#define BIFPLR3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                          0x000000FEL
+#define BIFPLR3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                           0x00000100L
+#define BIFPLR3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                      0x007F0000L
+#define BIFPLR3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                     0x00800000L
+#define BIFPLR3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                     0x01000000L
+#define BIFPLR3_LINK_CAP2__DRS_SUPPORTED_MASK                                                                 0x80000000L
+//BIFPLR3_LINK_CNTL2
+#define BIFPLR3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                          0x0
+#define BIFPLR3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                           0x4
+#define BIFPLR3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                                0x5
+#define BIFPLR3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                      0x6
+#define BIFPLR3_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                                0x7
+#define BIFPLR3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                       0xa
+#define BIFPLR3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                             0xb
+#define BIFPLR3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                      0xc
+#define BIFPLR3_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                            0x000FL
+#define BIFPLR3_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                             0x0010L
+#define BIFPLR3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                  0x0020L
+#define BIFPLR3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                        0x0040L
+#define BIFPLR3_LINK_CNTL2__XMIT_MARGIN_MASK                                                                  0x0380L
+#define BIFPLR3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                         0x0400L
+#define BIFPLR3_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                               0x0800L
+#define BIFPLR3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                        0xF000L
+//BIFPLR3_LINK_STATUS2
+#define BIFPLR3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                     0x0
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                                0x1
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                          0x2
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                          0x3
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                          0x4
+#define BIFPLR3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                            0x5
+#define BIFPLR3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                        0x6
+#define BIFPLR3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                        0x7
+#define BIFPLR3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                     0x8
+#define BIFPLR3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                            0xc
+#define BIFPLR3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                     0xf
+#define BIFPLR3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                       0x0001L
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                  0x0002L
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                            0x0004L
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                            0x0008L
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                            0x0010L
+#define BIFPLR3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                              0x0020L
+#define BIFPLR3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                          0x0040L
+#define BIFPLR3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                          0x0080L
+#define BIFPLR3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                       0x0300L
+#define BIFPLR3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                              0x7000L
+#define BIFPLR3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                       0x8000L
+//BIFPLR3_SLOT_CAP2
+#define BIFPLR3_SLOT_CAP2__RESERVED__SHIFT                                                                    0x0
+#define BIFPLR3_SLOT_CAP2__RESERVED_MASK                                                                      0xFFFFFFFFL
+//BIFPLR3_SLOT_CNTL2
+#define BIFPLR3_SLOT_CNTL2__RESERVED__SHIFT                                                                   0x0
+#define BIFPLR3_SLOT_CNTL2__RESERVED_MASK                                                                     0xFFFFL
+//BIFPLR3_SLOT_STATUS2
+#define BIFPLR3_SLOT_STATUS2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR3_SLOT_STATUS2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR3_MSI_CAP_LIST
+#define BIFPLR3_MSI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR3_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR3_MSI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR3_MSI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR3_MSI_MSG_CNTL
+#define BIFPLR3_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                   0x0
+#define BIFPLR3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                            0x1
+#define BIFPLR3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                             0x4
+#define BIFPLR3_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                                0x7
+#define BIFPLR3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                                0x8
+#define BIFPLR3_MSI_MSG_CNTL__MSI_EN_MASK                                                                     0x0001L
+#define BIFPLR3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                              0x000EL
+#define BIFPLR3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                               0x0070L
+#define BIFPLR3_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                  0x0080L
+#define BIFPLR3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                  0x0100L
+//BIFPLR3_MSI_MSG_ADDR_LO
+#define BIFPLR3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                       0x2
+#define BIFPLR3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                         0xFFFFFFFCL
+//BIFPLR3_MSI_MSG_ADDR_HI
+#define BIFPLR3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                       0x0
+#define BIFPLR3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                         0xFFFFFFFFL
+//BIFPLR3_MSI_MSG_DATA
+#define BIFPLR3_MSI_MSG_DATA__MSI_DATA__SHIFT                                                                 0x0
+#define BIFPLR3_MSI_MSG_DATA__MSI_DATA_MASK                                                                   0xFFFFL
+//BIFPLR3_MSI_MSG_DATA_64
+#define BIFPLR3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                           0x0
+#define BIFPLR3_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                             0xFFFFL
+//BIFPLR3_SSID_CAP_LIST
+#define BIFPLR3_SSID_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR3_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR3_SSID_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR3_SSID_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR3_SSID_CAP
+#define BIFPLR3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                          0x0
+#define BIFPLR3_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                                 0x10
+#define BIFPLR3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR3_SSID_CAP__SUBSYSTEM_ID_MASK                                                                   0xFFFF0000L
+//BIFPLR3_MSI_MAP_CAP_LIST
+#define BIFPLR3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                               0x0
+#define BIFPLR3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                             0x8
+#define BIFPLR3_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                                 0x00FFL
+#define BIFPLR3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                               0xFF00L
+//BIFPLR3_MSI_MAP_CAP
+#define BIFPLR3_MSI_MAP_CAP__EN__SHIFT                                                                        0x0
+#define BIFPLR3_MSI_MAP_CAP__FIXD__SHIFT                                                                      0x1
+#define BIFPLR3_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                  0xb
+#define BIFPLR3_MSI_MAP_CAP__EN_MASK                                                                          0x0001L
+#define BIFPLR3_MSI_MAP_CAP__FIXD_MASK                                                                        0x0002L
+#define BIFPLR3_MSI_MAP_CAP__CAP_TYPE_MASK                                                                    0xF800L
+//BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                      0x0
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                     0x10
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                  0x14
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                       0x000F0000L
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                    0xFFF00000L
+//BIFPLR3_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR3_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR3_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR3_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                       0x4
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                         0x8
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                       0xa
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                      0x00000007L
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                         0x00000070L
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                           0x00000300L
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                         0x00000C00L
+//BIFPLR3_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                      0x0
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                             0x18
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                        0x000000FFL
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                               0xFF000000L
+//BIFPLR3_PCIE_PORT_VC_CNTL
+#define BIFPLR3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                   0x0
+#define BIFPLR3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                       0x1
+#define BIFPLR3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                     0x0001L
+#define BIFPLR3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                         0x000EL
+//BIFPLR3_PCIE_PORT_VC_STATUS
+#define BIFPLR3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                               0x0
+#define BIFPLR3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                                 0x0001L
+//BIFPLR3_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR3_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR3_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR3_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR3_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR3_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIFPLR3_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                              0x0
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                                0xFFFFFFFFL
+//BIFPLR3_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                              0x0
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                                0xFFFFFFFFL
+//BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR3_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                                 0x4
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                              0x5
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                                 0xc
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                  0xd
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                             0xe
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                           0xf
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                               0x10
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                                0x11
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                                 0x12
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                                0x13
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                          0x14
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                           0x15
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                          0x16
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                          0x17
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                                 0x18
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                  0x19
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                             0x1a
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                   0x00000010L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                                0x00000020L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                   0x00001000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                    0x00002000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                               0x00004000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                             0x00008000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                                 0x00010000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                  0x00020000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                   0x00040000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                  0x00080000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                            0x00100000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                             0x00200000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                            0x00400000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                            0x00800000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                   0x01000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                    0x02000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                               0x04000000L
+//BIFPLR3_PCIE_UNCORR_ERR_MASK
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                     0x4
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                  0x5
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                     0xc
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                      0xd
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                                 0xe
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                               0xf
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                   0x10
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                    0x11
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                     0x12
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                    0x13
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                              0x14
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                               0x15
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                              0x16
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                              0x17
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                     0x18
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                      0x19
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                                 0x1a
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                       0x00000010L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                    0x00000020L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                       0x00001000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                        0x00002000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                   0x00004000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                                 0x00008000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                     0x00010000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                      0x00020000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                       0x00040000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                      0x00080000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                                0x00100000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                                 0x00200000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                                0x00400000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                                0x00800000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                       0x01000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                        0x02000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                   0x04000000L
+//BIFPLR3_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                             0x4
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                          0x5
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                             0xc
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                              0xd
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                         0xe
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                       0xf
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                           0x10
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                            0x11
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                             0x12
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                            0x13
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                      0x14
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                       0x15
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                      0x16
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                      0x17
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                             0x18
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                              0x19
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                         0x1a
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                               0x00000010L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                            0x00000020L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                               0x00001000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                                0x00002000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                           0x00004000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                         0x00008000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                             0x00010000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                              0x00020000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                               0x00040000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                              0x00080000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                        0x00100000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                         0x00200000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                        0x00400000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                        0x00800000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                               0x01000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                                0x02000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                           0x04000000L
+//BIFPLR3_PCIE_CORR_ERR_STATUS
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                   0x0
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                   0x6
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                  0x7
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                       0x8
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                      0xc
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                     0xd
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                              0xe
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                              0xf
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                     0x00000001L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                     0x00000040L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                    0x00000080L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                         0x00000100L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                        0x00001000L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                       0x00002000L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                                0x00004000L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                                0x00008000L
+//BIFPLR3_PCIE_CORR_ERR_MASK
+#define BIFPLR3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                       0x0
+#define BIFPLR3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                       0x6
+#define BIFPLR3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                      0x7
+#define BIFPLR3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                           0x8
+#define BIFPLR3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                          0xc
+#define BIFPLR3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                         0xd
+#define BIFPLR3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                  0xe
+#define BIFPLR3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                  0xf
+#define BIFPLR3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                         0x00000001L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                         0x00000040L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                        0x00000080L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                             0x00000100L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                            0x00001000L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                           0x00002000L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                    0x00004000L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                    0x00008000L
+//BIFPLR3_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                   0x0
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                  0x7
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                   0x8
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                              0x9
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                               0xa
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                          0xb
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                  0xc
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                     0x0000001FL
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                    0x00000080L
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                     0x00000100L
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                                0x00000200L
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                                 0x00000400L
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                            0x00000800L
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                    0x00001000L
+//BIFPLR3_PCIE_HDR_LOG0
+#define BIFPLR3_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR3_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR3_PCIE_HDR_LOG1
+#define BIFPLR3_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR3_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR3_PCIE_HDR_LOG2
+#define BIFPLR3_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR3_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR3_PCIE_HDR_LOG3
+#define BIFPLR3_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR3_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR3_PCIE_ROOT_ERR_CMD
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                     0x0
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                                 0x1
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                    0x2
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                       0x00000001L
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                   0x00000002L
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                      0x00000004L
+//BIFPLR3_PCIE_ROOT_ERR_STATUS
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                               0x1
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                          0x2
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                     0x3
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                        0x4
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                          0x5
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                             0x6
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                              0x1b
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                      0x00000001L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                                 0x00000002L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                            0x00000004L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                       0x00000008L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                          0x00000010L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                            0x00000020L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                               0x00000040L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                                0xF8000000L
+//BIFPLR3_PCIE_ERR_SRC_ID
+#define BIFPLR3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                       0x0
+#define BIFPLR3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                             0x10
+#define BIFPLR3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                               0xFFFF0000L
+//BIFPLR3_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR3_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR3_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR3_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR3_PCIE_LINK_CNTL3
+#define BIFPLR3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                  0x0
+#define BIFPLR3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                          0x1
+#define BIFPLR3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                    0x00000001L
+#define BIFPLR3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                            0x00000002L
+//BIFPLR3_PCIE_LANE_ERROR_STATUS
+#define BIFPLR3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                         0x0
+#define BIFPLR3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                           0x0000FFFFL
+//BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR3_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR3_PCIE_ACS_CAP
+#define BIFPLR3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                        0x0
+#define BIFPLR3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                     0x1
+#define BIFPLR3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                     0x2
+#define BIFPLR3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                  0x3
+#define BIFPLR3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                      0x4
+#define BIFPLR3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                       0x5
+#define BIFPLR3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                    0x6
+#define BIFPLR3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                               0x8
+#define BIFPLR3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                          0x0001L
+#define BIFPLR3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                       0x0002L
+#define BIFPLR3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                       0x0004L
+#define BIFPLR3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                    0x0008L
+#define BIFPLR3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                        0x0010L
+#define BIFPLR3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                         0x0020L
+#define BIFPLR3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                      0x0040L
+#define BIFPLR3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                                 0xFF00L
+//BIFPLR3_PCIE_ACS_CNTL
+#define BIFPLR3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                                 0x1
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                                 0x2
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                              0x3
+#define BIFPLR3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                  0x4
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                   0x5
+#define BIFPLR3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                                0x6
+#define BIFPLR3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                      0x0001L
+#define BIFPLR3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                   0x0002L
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                   0x0004L
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                                0x0008L
+#define BIFPLR3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                    0x0010L
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                     0x0020L
+#define BIFPLR3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                  0x0040L
+//BIFPLR3_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR3_PCIE_MC_CAP
+#define BIFPLR3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                              0x0
+#define BIFPLR3_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                           0x8
+#define BIFPLR3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                        0xf
+#define BIFPLR3_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                                0x003FL
+#define BIFPLR3_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                             0x3F00L
+#define BIFPLR3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                          0x8000L
+//BIFPLR3_PCIE_MC_CNTL
+#define BIFPLR3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                             0x0
+#define BIFPLR3_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                                0xf
+#define BIFPLR3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                               0x003FL
+#define BIFPLR3_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                  0x8000L
+//BIFPLR3_PCIE_MC_ADDR0
+#define BIFPLR3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                            0x0
+#define BIFPLR3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                          0xc
+#define BIFPLR3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                              0x0000003FL
+#define BIFPLR3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                            0xFFFFF000L
+//BIFPLR3_PCIE_MC_ADDR1
+#define BIFPLR3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                          0x0
+#define BIFPLR3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                            0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_RCV0
+#define BIFPLR3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                             0x0
+#define BIFPLR3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                               0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_RCV1
+#define BIFPLR3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                             0x0
+#define BIFPLR3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                               0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_BLOCK_ALL0
+#define BIFPLR3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                     0x0
+#define BIFPLR3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_BLOCK_ALL1
+#define BIFPLR3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                     0x0
+#define BIFPLR3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                  0x0
+#define BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                    0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                  0x0
+#define BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                    0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                  0x0
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                                 0x6
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                    0x0000003FL
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                   0xFFFFFFC0L
+//BIFPLR3_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                                 0x0
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                   0xFFFFFFFFL
+//BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR3_PCIE_L1_PM_SUB_CAP
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                              0x0
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                              0x1
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                                0x2
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                                0x3
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                                0x4
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                               0x8
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                              0x10
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                              0x13
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                                0x00000001L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                                0x00000002L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                  0x00000004L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                  0x00000008L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                  0x00000010L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                                 0x0000FF00L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                                0x00030000L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                                0x00F80000L
+//BIFPLR3_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                    0x1
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                      0x2
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                      0x3
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                          0x8
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                          0x1d
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                      0x00000001L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                      0x00000002L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                        0x00000004L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                        0x00000008L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                            0x0000FF00L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                            0xE0000000L
+//BIFPLR3_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                                 0x0
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                                 0x3
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                   0x00000003L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                   0x000000F8L
+//BIFPLR3_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR3_PCIE_DPC_CAP_LIST
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                               0x5
+#define BIFPLR3_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                              0x6
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                   0x7
+#define BIFPLR3_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                     0x8
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                               0xc
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                      0x001FL
+#define BIFPLR3_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                                 0x0020L
+#define BIFPLR3_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                                0x0040L
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                     0x0080L
+#define BIFPLR3_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                       0x0F00L
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                                 0x1000L
+//BIFPLR3_PCIE_DPC_CNTL
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                      0x0
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                  0x2
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                    0x3
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                      0x4
+#define BIFPLR3_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                     0x5
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                    0x6
+#define BIFPLR3_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                                0x7
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                        0x0003L
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                    0x0004L
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                      0x0008L
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                        0x0010L
+#define BIFPLR3_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                       0x0020L
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                      0x0040L
+#define BIFPLR3_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                  0x0080L
+//BIFPLR3_PCIE_DPC_STATUS
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                    0x1
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                  0x3
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                           0x4
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                          0x5
+#define BIFPLR3_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                            0x8
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                      0x0001L
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                      0x0006L
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                    0x0008L
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                             0x0010L
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                            0x0060L
+#define BIFPLR3_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                              0x1F00L
+//BIFPLR3_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR3_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                          0x0
+#define BIFPLR3_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                            0xFFFFL
+//BIFPLR3_PCIE_RP_PIO_STATUS
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR3_PCIE_RP_PIO_MASK
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                           0x0
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                           0x1
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                              0x2
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                            0x8
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                            0x9
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                               0xa
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                           0x10
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                           0x11
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                              0x12
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                             0x00000001L
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                             0x00000002L
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                                0x00000004L
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                              0x00000100L
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                              0x00000200L
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                                 0x00000400L
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                             0x00010000L
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                             0x00020000L
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                                0x00040000L
+//BIFPLR3_PCIE_RP_PIO_SEVERITY
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR3_PCIE_RP_PIO_SYSERROR
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR3_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                      0x0
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                      0x1
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                         0x2
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                       0x8
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                       0x9
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                          0xa
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                      0x10
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                      0x11
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                         0x12
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                        0x00000001L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                        0x00000002L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                           0x00000004L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                         0x00000100L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                         0x00000200L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                            0x00000400L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                        0x00010000L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                        0x00020000L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                           0x00040000L
+//BIFPLR3_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR3_PCIE_ESM_CAP_LIST
+#define BIFPLR3_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR3_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                             0x10
+#define BIFPLR3_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                            0x14
+#define BIFPLR3_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                                0x0000FFFFL
+#define BIFPLR3_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                               0x000F0000L
+#define BIFPLR3_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                              0xFFF00000L
+//BIFPLR3_PCIE_ESM_HEADER_1
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                       0x0
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                         0x10
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                         0x14
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                           0x000F0000L
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                           0xFFF00000L
+//BIFPLR3_PCIE_ESM_HEADER_2
+#define BIFPLR3_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR3_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                                0xFFFFL
+//BIFPLR3_PCIE_ESM_STATUS
+#define BIFPLR3_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                  0x9
+#define BIFPLR3_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                      0x01FFL
+#define BIFPLR3_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                    0x0E00L
+//BIFPLR3_PCIE_ESM_CTRL
+#define BIFPLR3_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                             0xf
+#define BIFPLR3_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                               0x8000L
+//BIFPLR3_PCIE_ESM_CAP_1
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                               0x0
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                               0x1
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                               0x2
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                               0x3
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                               0x4
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                               0x5
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                               0x6
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                               0x7
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                               0x8
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                               0x9
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                               0xa
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                               0xb
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                               0xc
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                               0xd
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                               0xe
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                               0xf
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                               0x10
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                               0x11
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                               0x12
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                               0x13
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                              0x14
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                              0x15
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                              0x16
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                              0x17
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                              0x18
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                              0x19
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                              0x1a
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                              0x1b
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                              0x1c
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                              0x1d
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                                 0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                                 0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                                 0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                                 0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                                 0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                                 0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                                 0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                                 0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                                 0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                                 0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                                 0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                                 0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                                 0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                                 0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                                 0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                                 0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                                 0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                                 0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                                 0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                                 0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                                0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                                0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                                0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                                0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                                0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                                0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                                0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                                0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                                0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                                0x20000000L
+//BIFPLR3_PCIE_ESM_CAP_2
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                              0x0
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                              0x1
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                              0x2
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                              0x3
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                              0x4
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                              0x5
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                              0x6
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                              0x7
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                              0x8
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                              0x9
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                              0xa
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                              0xb
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                              0xc
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                              0xd
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                              0xe
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                              0xf
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                              0x10
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                              0x11
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                              0x12
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                              0x13
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                              0x14
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                              0x15
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                              0x16
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                              0x17
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                              0x18
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                              0x19
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                              0x1a
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                              0x1b
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                              0x1c
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                              0x1d
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                                0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                                0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                                0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                                0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                                0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                                0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                                0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                                0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                                0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                                0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                                0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                                0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                                0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                                0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                                0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                                0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                                0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                                0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                                0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                                0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                                0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                                0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                                0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                                0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                                0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                                0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                                0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                                0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                                0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                                0x20000000L
+//BIFPLR3_PCIE_ESM_CAP_3
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                              0x0
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                              0x1
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                              0x2
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                              0x3
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                              0x4
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                              0x5
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                              0x6
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                              0x7
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                              0x8
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                              0x9
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                              0xa
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                              0xb
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                              0xc
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                              0xd
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                              0xe
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                              0xf
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                              0x10
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                              0x11
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                              0x12
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                              0x13
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                                0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                                0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                                0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                                0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                                0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                                0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                                0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                                0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                                0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                                0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                                0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                                0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                                0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                                0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                                0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                                0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                                0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                                0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                                0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                                0x00080000L
+//BIFPLR3_PCIE_ESM_CAP_4
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                              0x0
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                              0x1
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                              0x2
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                              0x3
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                              0x4
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                              0x5
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                              0x6
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                              0x7
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                              0x8
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                              0x9
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                              0xa
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                              0xb
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                              0xc
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                              0xd
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                              0xe
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                              0xf
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                              0x10
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                              0x11
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                              0x12
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                              0x13
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                              0x14
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                              0x15
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                              0x16
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                              0x17
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                              0x18
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                              0x19
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                              0x1a
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                              0x1b
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                              0x1c
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                              0x1d
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                                0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                                0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                                0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                                0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                                0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                                0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                                0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                                0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                                0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                                0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                                0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                                0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                                0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                                0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                                0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                                0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                                0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                                0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                                0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                                0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                                0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                                0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                                0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                                0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                                0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                                0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                                0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                                0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                                0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                                0x20000000L
+//BIFPLR3_PCIE_ESM_CAP_5
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                              0x0
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                              0x1
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                              0x2
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                              0x3
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                              0x4
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                              0x5
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                              0x6
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                              0x7
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                              0x8
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                              0x9
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                              0xa
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                              0xb
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                              0xc
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                              0xd
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                              0xe
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                              0xf
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                              0x10
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                              0x11
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                              0x12
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                              0x13
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                              0x14
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                              0x15
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                              0x16
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                              0x17
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                              0x18
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                              0x19
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                              0x1a
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                              0x1b
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                              0x1c
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                              0x1d
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                                0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                                0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                                0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                                0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                                0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                                0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                                0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                                0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                                0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                                0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                                0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                                0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                                0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                                0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                                0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                                0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                                0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                                0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                                0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                                0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                                0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                                0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                                0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                                0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                                0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                                0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                                0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                                0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                                0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                                0x20000000L
+//BIFPLR3_PCIE_ESM_CAP_6
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                              0x0
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                              0x1
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                              0x2
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                              0x3
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                              0x4
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                              0x5
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                              0x6
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                              0x7
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                              0x8
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                              0x9
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                              0xa
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                              0xb
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                              0xc
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                              0xd
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                              0xe
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                              0xf
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                              0x10
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                              0x11
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                              0x12
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                              0x13
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                              0x14
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                              0x15
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                              0x16
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                              0x17
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                              0x18
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                              0x19
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                              0x1a
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                              0x1b
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                              0x1c
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                              0x1d
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                                0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                                0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                                0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                                0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                                0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                                0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                                0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                                0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                                0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                                0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                                0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                                0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                                0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                                0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                                0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                                0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                                0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                                0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                                0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                                0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                                0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                                0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                                0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                                0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                                0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                                0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                                0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                                0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                                0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                                0x20000000L
+//BIFPLR3_PCIE_ESM_CAP_7
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                              0x0
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                              0x1
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                              0x2
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                              0x3
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                              0x4
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                              0x5
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                              0x6
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                              0x7
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                              0x8
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                              0x9
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                              0xa
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                              0xb
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                              0xc
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                              0xd
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                              0xe
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                              0xf
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                              0x10
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                              0x11
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                              0x12
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                              0x13
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                              0x14
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                              0x15
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                              0x16
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                              0x17
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                              0x18
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                              0x19
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                              0x1a
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                              0x1b
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                              0x1c
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                              0x1d
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                              0x1e
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                                0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                                0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                                0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                                0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                                0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                                0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                                0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                                0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                                0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                                0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                                0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                                0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                                0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                                0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                                0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                                0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                                0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                                0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                                0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                                0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                                0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                                0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                                0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                                0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                                0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                                0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                                0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                                0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                                0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                                0x20000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                                0x40000000L
+//BIFPLR3_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR3_DATA_LINK_FEATURE_CAP
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                         0x0
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                        0x1
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                             0x1f
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                           0x00000001L
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                          0x007FFFFEL
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                               0x80000000L
+//BIFPLR3_DATA_LINK_FEATURE_STATUS
+#define BIFPLR3_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                         0x0
+#define BIFPLR3_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                   0x1f
+#define BIFPLR3_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                           0x007FFFFFL
+#define BIFPLR3_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                     0x80000000L
+//BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                    0x10
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                   0x14
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                      0x000F0000L
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                     0xFFF00000L
+//BIFPLR3_LINK_CAP_16GT
+#define BIFPLR3_LINK_CAP_16GT__RESERVED__SHIFT                                                                0x0
+#define BIFPLR3_LINK_CAP_16GT__RESERVED_MASK                                                                  0xFFFFFFFFL
+//BIFPLR3_LINK_CNTL_16GT
+#define BIFPLR3_LINK_CNTL_16GT__RESERVED__SHIFT                                                               0x0
+#define BIFPLR3_LINK_CNTL_16GT__RESERVED_MASK                                                                 0xFFFFFFFFL
+//BIFPLR3_LINK_STATUS_16GT
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                           0x0
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                     0x1
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                     0x2
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                     0x3
+#define BIFPLR3_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                       0x4
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                             0x00000001L
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                       0x00000002L
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                       0x00000004L
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                       0x00000008L
+#define BIFPLR3_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                         0x00000010L
+//BIFPLR3_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR3_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR3_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR3_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR3_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR3_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR3_MARGINING_PORT_CAP
+#define BIFPLR3_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                            0x0
+#define BIFPLR3_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                              0x0001L
+//BIFPLR3_MARGINING_PORT_STATUS
+#define BIFPLR3_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                                 0x0
+#define BIFPLR3_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                        0x1
+#define BIFPLR3_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                   0x0001L
+#define BIFPLR3_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                          0x0002L
+//BIFPLR3_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR3_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR3_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR3_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR3_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR3_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR3_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR3_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR3_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR3_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR3_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR3_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR3_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR3_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR3_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR3_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR3_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR3_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR3_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR3_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR3_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_PCIE_CCIX_CAP_LIST
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                            0x10
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                           0x14
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                               0x0000FFFFL
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                              0x000F0000L
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                             0xFFF00000L
+//BIFPLR3_PCIE_CCIX_HEADER_1
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR3_PCIE_CCIX_HEADER_2
+#define BIFPLR3_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR3_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                               0xFFFFL
+//BIFPLR3_PCIE_CCIX_CAP
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                      0x0
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                         0x1
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                        0x3
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                    0x4
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                          0x8
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                        0x0001L
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                           0x0006L
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                          0x0008L
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                      0x0070L
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                            0x0700L
+//BIFPLR3_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                              0x0
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                                0x1
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                                0x2
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                               0x5
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                               0x9
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                               0xe
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                                0x00000001L
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                  0x00000002L
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                  0x00000004L
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                                 0x00000020L
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                                 0x00000200L
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                                 0x00004000L
+//BIFPLR3_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR3_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                       0x0
+#define BIFPLR3_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIFPLR3_PCIE_CCIX_ESM_STATUS
+#define BIFPLR3_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                            0x0
+#define BIFPLR3_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                         0x7
+#define BIFPLR3_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                              0x0000007FL
+#define BIFPLR3_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                           0x00000080L
+//BIFPLR3_PCIE_CCIX_ESM_CNTL
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                     0x0
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                            0x7
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                     0x8
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                         0xf
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                           0x10
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                           0x14
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                  0x18
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                    0x19
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                              0x1a
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                       0x0000007FL
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                              0x00000080L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                       0x00007F00L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                           0x00008000L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                             0x00070000L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                             0x00700000L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                    0x01000000L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                      0x02000000L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                                0x1C000000L
+//BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_PCIE_CCIX_TRANS_CAP
+#define BIFPLR3_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                                 0x0
+#define BIFPLR3_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                   0x00000001L
+//BIFPLR3_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR3_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                                 0x0
+#define BIFPLR3_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                   0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+//BIFPLR4_VENDOR_ID
+#define BIFPLR4_VENDOR_ID__VENDOR_ID__SHIFT                                                                   0x0
+#define BIFPLR4_VENDOR_ID__VENDOR_ID_MASK                                                                     0xFFFFL
+//BIFPLR4_DEVICE_ID
+#define BIFPLR4_DEVICE_ID__DEVICE_ID__SHIFT                                                                   0x0
+#define BIFPLR4_DEVICE_ID__DEVICE_ID_MASK                                                                     0xFFFFL
+//BIFPLR4_COMMAND
+#define BIFPLR4_COMMAND__IO_ACCESS_EN__SHIFT                                                                  0x0
+#define BIFPLR4_COMMAND__MEM_ACCESS_EN__SHIFT                                                                 0x1
+#define BIFPLR4_COMMAND__BUS_MASTER_EN__SHIFT                                                                 0x2
+#define BIFPLR4_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                              0x3
+#define BIFPLR4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                       0x4
+#define BIFPLR4_COMMAND__PAL_SNOOP_EN__SHIFT                                                                  0x5
+#define BIFPLR4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                         0x6
+#define BIFPLR4_COMMAND__AD_STEPPING__SHIFT                                                                   0x7
+#define BIFPLR4_COMMAND__SERR_EN__SHIFT                                                                       0x8
+#define BIFPLR4_COMMAND__FAST_B2B_EN__SHIFT                                                                   0x9
+#define BIFPLR4_COMMAND__INT_DIS__SHIFT                                                                       0xa
+#define BIFPLR4_COMMAND__IO_ACCESS_EN_MASK                                                                    0x0001L
+#define BIFPLR4_COMMAND__MEM_ACCESS_EN_MASK                                                                   0x0002L
+#define BIFPLR4_COMMAND__BUS_MASTER_EN_MASK                                                                   0x0004L
+#define BIFPLR4_COMMAND__SPECIAL_CYCLE_EN_MASK                                                                0x0008L
+#define BIFPLR4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                         0x0010L
+#define BIFPLR4_COMMAND__PAL_SNOOP_EN_MASK                                                                    0x0020L
+#define BIFPLR4_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                           0x0040L
+#define BIFPLR4_COMMAND__AD_STEPPING_MASK                                                                     0x0080L
+#define BIFPLR4_COMMAND__SERR_EN_MASK                                                                         0x0100L
+#define BIFPLR4_COMMAND__FAST_B2B_EN_MASK                                                                     0x0200L
+#define BIFPLR4_COMMAND__INT_DIS_MASK                                                                         0x0400L
+//BIFPLR4_STATUS
+#define BIFPLR4_STATUS__IMMEDIATE_READINESS__SHIFT                                                            0x0
+#define BIFPLR4_STATUS__INT_STATUS__SHIFT                                                                     0x3
+#define BIFPLR4_STATUS__CAP_LIST__SHIFT                                                                       0x4
+#define BIFPLR4_STATUS__PCI_66_CAP__SHIFT                                                                     0x5
+#define BIFPLR4_STATUS__FAST_BACK_CAPABLE__SHIFT                                                              0x7
+#define BIFPLR4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                       0x8
+#define BIFPLR4_STATUS__DEVSEL_TIMING__SHIFT                                                                  0x9
+#define BIFPLR4_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                            0xb
+#define BIFPLR4_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                          0xc
+#define BIFPLR4_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                          0xd
+#define BIFPLR4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                          0xe
+#define BIFPLR4_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                          0xf
+#define BIFPLR4_STATUS__IMMEDIATE_READINESS_MASK                                                              0x0001L
+#define BIFPLR4_STATUS__INT_STATUS_MASK                                                                       0x0008L
+#define BIFPLR4_STATUS__CAP_LIST_MASK                                                                         0x0010L
+#define BIFPLR4_STATUS__PCI_66_CAP_MASK                                                                       0x0020L
+#define BIFPLR4_STATUS__FAST_BACK_CAPABLE_MASK                                                                0x0080L
+#define BIFPLR4_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                         0x0100L
+#define BIFPLR4_STATUS__DEVSEL_TIMING_MASK                                                                    0x0600L
+#define BIFPLR4_STATUS__SIGNAL_TARGET_ABORT_MASK                                                              0x0800L
+#define BIFPLR4_STATUS__RECEIVED_TARGET_ABORT_MASK                                                            0x1000L
+#define BIFPLR4_STATUS__RECEIVED_MASTER_ABORT_MASK                                                            0x2000L
+#define BIFPLR4_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                            0x4000L
+#define BIFPLR4_STATUS__PARITY_ERROR_DETECTED_MASK                                                            0x8000L
+//BIFPLR4_REVISION_ID
+#define BIFPLR4_REVISION_ID__MINOR_REV_ID__SHIFT                                                              0x0
+#define BIFPLR4_REVISION_ID__MAJOR_REV_ID__SHIFT                                                              0x4
+#define BIFPLR4_REVISION_ID__MINOR_REV_ID_MASK                                                                0x0FL
+#define BIFPLR4_REVISION_ID__MAJOR_REV_ID_MASK                                                                0xF0L
+//BIFPLR4_PROG_INTERFACE
+#define BIFPLR4_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                         0x0
+#define BIFPLR4_PROG_INTERFACE__PROG_INTERFACE_MASK                                                           0xFFL
+//BIFPLR4_SUB_CLASS
+#define BIFPLR4_SUB_CLASS__SUB_CLASS__SHIFT                                                                   0x0
+#define BIFPLR4_SUB_CLASS__SUB_CLASS_MASK                                                                     0xFFL
+//BIFPLR4_BASE_CLASS
+#define BIFPLR4_BASE_CLASS__BASE_CLASS__SHIFT                                                                 0x0
+#define BIFPLR4_BASE_CLASS__BASE_CLASS_MASK                                                                   0xFFL
+//BIFPLR4_CACHE_LINE
+#define BIFPLR4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                            0x0
+#define BIFPLR4_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                              0xFFL
+//BIFPLR4_LATENCY
+#define BIFPLR4_LATENCY__LATENCY_TIMER__SHIFT                                                                 0x0
+#define BIFPLR4_LATENCY__LATENCY_TIMER_MASK                                                                   0xFFL
+//BIFPLR4_HEADER
+#define BIFPLR4_HEADER__HEADER_TYPE__SHIFT                                                                    0x0
+#define BIFPLR4_HEADER__DEVICE_TYPE__SHIFT                                                                    0x7
+#define BIFPLR4_HEADER__HEADER_TYPE_MASK                                                                      0x7FL
+#define BIFPLR4_HEADER__DEVICE_TYPE_MASK                                                                      0x80L
+//BIFPLR4_BIST
+#define BIFPLR4_BIST__BIST_COMP__SHIFT                                                                        0x0
+#define BIFPLR4_BIST__BIST_STRT__SHIFT                                                                        0x6
+#define BIFPLR4_BIST__BIST_CAP__SHIFT                                                                         0x7
+#define BIFPLR4_BIST__BIST_COMP_MASK                                                                          0x0FL
+#define BIFPLR4_BIST__BIST_STRT_MASK                                                                          0x40L
+#define BIFPLR4_BIST__BIST_CAP_MASK                                                                           0x80L
+//BIFPLR4_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                    0x0
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                  0x8
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                    0x10
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                        0x18
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                      0x000000FFL
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                    0x0000FF00L
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                      0x00FF0000L
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                          0xFF000000L
+//BIFPLR4_IO_BASE_LIMIT
+#define BIFPLR4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                            0x0
+#define BIFPLR4_IO_BASE_LIMIT__IO_BASE__SHIFT                                                                 0x4
+#define BIFPLR4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                           0x8
+#define BIFPLR4_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                                0xc
+#define BIFPLR4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                              0x000FL
+#define BIFPLR4_IO_BASE_LIMIT__IO_BASE_MASK                                                                   0x00F0L
+#define BIFPLR4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                             0x0F00L
+#define BIFPLR4_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                  0xF000L
+//BIFPLR4_SECONDARY_STATUS
+#define BIFPLR4_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIFPLR4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIFPLR4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIFPLR4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIFPLR4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIFPLR4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIFPLR4_SECONDARY_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIFPLR4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIFPLR4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIFPLR4_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIFPLR4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIFPLR4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIFPLR4_MEM_BASE_LIMIT
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                         0x4
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                         0x10
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                        0x14
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                            0x0000000FL
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                           0x0000FFF0L
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                           0x000F0000L
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                          0xFFF00000L
+//BIFPLR4_PREF_BASE_LIMIT
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                    0x0
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                   0x4
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                   0x10
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                  0x14
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                      0x0000000FL
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                     0x0000FFF0L
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                     0x000F0000L
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                    0xFFF00000L
+//BIFPLR4_PREF_BASE_UPPER
+#define BIFPLR4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                       0x0
+#define BIFPLR4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                         0xFFFFFFFFL
+//BIFPLR4_PREF_LIMIT_UPPER
+#define BIFPLR4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                     0x0
+#define BIFPLR4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_IO_BASE_LIMIT_HI
+#define BIFPLR4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                        0x0
+#define BIFPLR4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                       0x10
+#define BIFPLR4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                          0x0000FFFFL
+#define BIFPLR4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                         0xFFFF0000L
+//BIFPLR4_CAP_PTR
+#define BIFPLR4_CAP_PTR__CAP_PTR__SHIFT                                                                       0x0
+#define BIFPLR4_CAP_PTR__CAP_PTR_MASK                                                                         0xFFL
+//BIFPLR4_ROM_BASE_ADDR
+#define BIFPLR4_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                               0x0
+#define BIFPLR4_ROM_BASE_ADDR__BASE_ADDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR4_INTERRUPT_LINE
+#define BIFPLR4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                         0x0
+#define BIFPLR4_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                           0xFFL
+//BIFPLR4_INTERRUPT_PIN
+#define BIFPLR4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                           0x0
+#define BIFPLR4_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                             0xFFL
+//BIFPLR4_IRQ_BRIDGE_CNTL
+#define BIFPLR4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                    0x0
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                               0x1
+#define BIFPLR4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                                0x2
+#define BIFPLR4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                                0x3
+#define BIFPLR4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                               0x4
+#define BIFPLR4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                     0x5
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                   0x6
+#define BIFPLR4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                           0x7
+#define BIFPLR4_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                                 0x8
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                               0x9
+#define BIFPLR4_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                  0xa
+#define BIFPLR4_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                             0xb
+#define BIFPLR4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                      0x0001L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                                 0x0002L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                  0x0004L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                  0x0008L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                                 0x0010L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                       0x0020L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                     0x0040L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                             0x0080L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                   0x0100L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                                 0x0200L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                    0x0400L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                               0x0800L
+//BIFPLR4_EXT_BRIDGE_CNTL
+#define BIFPLR4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                         0x0
+#define BIFPLR4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                           0x01L
+//BIFPLR4_VENDOR_CAP_LIST
+#define BIFPLR4_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR4_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR4_VENDOR_CAP_LIST__LENGTH__SHIFT                                                                0x10
+#define BIFPLR4_VENDOR_CAP_LIST__CAP_ID_MASK                                                                  0x000000FFL
+#define BIFPLR4_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                                0x0000FF00L
+#define BIFPLR4_VENDOR_CAP_LIST__LENGTH_MASK                                                                  0x00FF0000L
+//BIFPLR4_ADAPTER_ID_W
+#define BIFPLR4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                      0x0
+#define BIFPLR4_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                             0x10
+#define BIFPLR4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR4_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                               0xFFFF0000L
+//BIFPLR4_PMI_CAP_LIST
+#define BIFPLR4_PMI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR4_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR4_PMI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR4_PMI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR4_PMI_CAP
+#define BIFPLR4_PMI_CAP__VERSION__SHIFT                                                                       0x0
+#define BIFPLR4_PMI_CAP__PME_CLOCK__SHIFT                                                                     0x3
+#define BIFPLR4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                           0x4
+#define BIFPLR4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                             0x5
+#define BIFPLR4_PMI_CAP__AUX_CURRENT__SHIFT                                                                   0x6
+#define BIFPLR4_PMI_CAP__D1_SUPPORT__SHIFT                                                                    0x9
+#define BIFPLR4_PMI_CAP__D2_SUPPORT__SHIFT                                                                    0xa
+#define BIFPLR4_PMI_CAP__PME_SUPPORT__SHIFT                                                                   0xb
+#define BIFPLR4_PMI_CAP__VERSION_MASK                                                                         0x0007L
+#define BIFPLR4_PMI_CAP__PME_CLOCK_MASK                                                                       0x0008L
+#define BIFPLR4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                             0x0010L
+#define BIFPLR4_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                               0x0020L
+#define BIFPLR4_PMI_CAP__AUX_CURRENT_MASK                                                                     0x01C0L
+#define BIFPLR4_PMI_CAP__D1_SUPPORT_MASK                                                                      0x0200L
+#define BIFPLR4_PMI_CAP__D2_SUPPORT_MASK                                                                      0x0400L
+#define BIFPLR4_PMI_CAP__PME_SUPPORT_MASK                                                                     0xF800L
+//BIFPLR4_PMI_STATUS_CNTL
+#define BIFPLR4_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                           0x0
+#define BIFPLR4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                         0x3
+#define BIFPLR4_PMI_STATUS_CNTL__PME_EN__SHIFT                                                                0x8
+#define BIFPLR4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                           0x9
+#define BIFPLR4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                            0xd
+#define BIFPLR4_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                            0xf
+#define BIFPLR4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                         0x16
+#define BIFPLR4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                            0x17
+#define BIFPLR4_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                              0x18
+#define BIFPLR4_PMI_STATUS_CNTL__POWER_STATE_MASK                                                             0x00000003L
+#define BIFPLR4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                           0x00000008L
+#define BIFPLR4_PMI_STATUS_CNTL__PME_EN_MASK                                                                  0x00000100L
+#define BIFPLR4_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                             0x00001E00L
+#define BIFPLR4_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                              0x00006000L
+#define BIFPLR4_PMI_STATUS_CNTL__PME_STATUS_MASK                                                              0x00008000L
+#define BIFPLR4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                           0x00400000L
+#define BIFPLR4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                              0x00800000L
+#define BIFPLR4_PMI_STATUS_CNTL__PMI_DATA_MASK                                                                0xFF000000L
+//BIFPLR4_PCIE_CAP_LIST
+#define BIFPLR4_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR4_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR4_PCIE_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR4_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR4_PCIE_CAP
+#define BIFPLR4_PCIE_CAP__VERSION__SHIFT                                                                      0x0
+#define BIFPLR4_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                  0x4
+#define BIFPLR4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                             0x8
+#define BIFPLR4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                              0x9
+#define BIFPLR4_PCIE_CAP__VERSION_MASK                                                                        0x000FL
+#define BIFPLR4_PCIE_CAP__DEVICE_TYPE_MASK                                                                    0x00F0L
+#define BIFPLR4_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                               0x0100L
+#define BIFPLR4_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                                0x3E00L
+//BIFPLR4_DEVICE_CAP
+#define BIFPLR4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                        0x0
+#define BIFPLR4_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                               0x3
+#define BIFPLR4_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                               0x5
+#define BIFPLR4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                     0x6
+#define BIFPLR4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                      0x9
+#define BIFPLR4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                   0xf
+#define BIFPLR4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                  0x12
+#define BIFPLR4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                  0x1a
+#define BIFPLR4_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                                0x1c
+#define BIFPLR4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                          0x00000007L
+#define BIFPLR4_DEVICE_CAP__PHANTOM_FUNC_MASK                                                                 0x00000018L
+#define BIFPLR4_DEVICE_CAP__EXTENDED_TAG_MASK                                                                 0x00000020L
+#define BIFPLR4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                       0x000001C0L
+#define BIFPLR4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                        0x00000E00L
+#define BIFPLR4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                     0x00008000L
+#define BIFPLR4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                    0x03FC0000L
+#define BIFPLR4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                    0x0C000000L
+#define BIFPLR4_DEVICE_CAP__FLR_CAPABLE_MASK                                                                  0x10000000L
+//BIFPLR4_DEVICE_CNTL
+#define BIFPLR4_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                               0x0
+#define BIFPLR4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                          0x1
+#define BIFPLR4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                              0x2
+#define BIFPLR4_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                             0x3
+#define BIFPLR4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                            0x4
+#define BIFPLR4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                          0x5
+#define BIFPLR4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                           0x8
+#define BIFPLR4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                           0x9
+#define BIFPLR4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                           0xa
+#define BIFPLR4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                               0xb
+#define BIFPLR4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                     0xc
+#define BIFPLR4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                       0xf
+#define BIFPLR4_DEVICE_CNTL__CORR_ERR_EN_MASK                                                                 0x0001L
+#define BIFPLR4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                            0x0002L
+#define BIFPLR4_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                                0x0004L
+#define BIFPLR4_DEVICE_CNTL__USR_REPORT_EN_MASK                                                               0x0008L
+#define BIFPLR4_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                              0x0010L
+#define BIFPLR4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                            0x00E0L
+#define BIFPLR4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                             0x0100L
+#define BIFPLR4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                             0x0200L
+#define BIFPLR4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                             0x0400L
+#define BIFPLR4_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                                 0x0800L
+#define BIFPLR4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                       0x7000L
+#define BIFPLR4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                         0x8000L
+//BIFPLR4_DEVICE_STATUS
+#define BIFPLR4_DEVICE_STATUS__CORR_ERR__SHIFT                                                                0x0
+#define BIFPLR4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                           0x1
+#define BIFPLR4_DEVICE_STATUS__FATAL_ERR__SHIFT                                                               0x2
+#define BIFPLR4_DEVICE_STATUS__USR_DETECTED__SHIFT                                                            0x3
+#define BIFPLR4_DEVICE_STATUS__AUX_PWR__SHIFT                                                                 0x4
+#define BIFPLR4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                       0x5
+#define BIFPLR4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                           0x6
+#define BIFPLR4_DEVICE_STATUS__CORR_ERR_MASK                                                                  0x0001L
+#define BIFPLR4_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                             0x0002L
+#define BIFPLR4_DEVICE_STATUS__FATAL_ERR_MASK                                                                 0x0004L
+#define BIFPLR4_DEVICE_STATUS__USR_DETECTED_MASK                                                              0x0008L
+#define BIFPLR4_DEVICE_STATUS__AUX_PWR_MASK                                                                   0x0010L
+#define BIFPLR4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                         0x0020L
+#define BIFPLR4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                             0x0040L
+//BIFPLR4_LINK_CAP
+#define BIFPLR4_LINK_CAP__LINK_SPEED__SHIFT                                                                   0x0
+#define BIFPLR4_LINK_CAP__LINK_WIDTH__SHIFT                                                                   0x4
+#define BIFPLR4_LINK_CAP__PM_SUPPORT__SHIFT                                                                   0xa
+#define BIFPLR4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                             0xc
+#define BIFPLR4_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                              0xf
+#define BIFPLR4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                       0x12
+#define BIFPLR4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                  0x13
+#define BIFPLR4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                  0x14
+#define BIFPLR4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                     0x15
+#define BIFPLR4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                  0x16
+#define BIFPLR4_LINK_CAP__PORT_NUMBER__SHIFT                                                                  0x18
+#define BIFPLR4_LINK_CAP__LINK_SPEED_MASK                                                                     0x0000000FL
+#define BIFPLR4_LINK_CAP__LINK_WIDTH_MASK                                                                     0x000003F0L
+#define BIFPLR4_LINK_CAP__PM_SUPPORT_MASK                                                                     0x00000C00L
+#define BIFPLR4_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                               0x00007000L
+#define BIFPLR4_LINK_CAP__L1_EXIT_LATENCY_MASK                                                                0x00038000L
+#define BIFPLR4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                         0x00040000L
+#define BIFPLR4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                    0x00080000L
+#define BIFPLR4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                    0x00100000L
+#define BIFPLR4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                       0x00200000L
+#define BIFPLR4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                    0x00400000L
+#define BIFPLR4_LINK_CAP__PORT_NUMBER_MASK                                                                    0xFF000000L
+//BIFPLR4_LINK_CNTL
+#define BIFPLR4_LINK_CNTL__PM_CONTROL__SHIFT                                                                  0x0
+#define BIFPLR4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                           0x3
+#define BIFPLR4_LINK_CNTL__LINK_DIS__SHIFT                                                                    0x4
+#define BIFPLR4_LINK_CNTL__RETRAIN_LINK__SHIFT                                                                0x5
+#define BIFPLR4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                            0x6
+#define BIFPLR4_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                               0x7
+#define BIFPLR4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                   0x8
+#define BIFPLR4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                                 0x9
+#define BIFPLR4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                   0xa
+#define BIFPLR4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                   0xb
+#define BIFPLR4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                       0xe
+#define BIFPLR4_LINK_CNTL__PM_CONTROL_MASK                                                                    0x0003L
+#define BIFPLR4_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                             0x0008L
+#define BIFPLR4_LINK_CNTL__LINK_DIS_MASK                                                                      0x0010L
+#define BIFPLR4_LINK_CNTL__RETRAIN_LINK_MASK                                                                  0x0020L
+#define BIFPLR4_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                              0x0040L
+#define BIFPLR4_LINK_CNTL__EXTENDED_SYNC_MASK                                                                 0x0080L
+#define BIFPLR4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                     0x0100L
+#define BIFPLR4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                   0x0200L
+#define BIFPLR4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                     0x0400L
+#define BIFPLR4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                     0x0800L
+#define BIFPLR4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                         0xC000L
+//BIFPLR4_LINK_STATUS
+#define BIFPLR4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                     0x4
+#define BIFPLR4_LINK_STATUS__LINK_TRAINING__SHIFT                                                             0xb
+#define BIFPLR4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                            0xc
+#define BIFPLR4_LINK_STATUS__DL_ACTIVE__SHIFT                                                                 0xd
+#define BIFPLR4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                                 0xe
+#define BIFPLR4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                                 0xf
+#define BIFPLR4_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                       0x03F0L
+#define BIFPLR4_LINK_STATUS__LINK_TRAINING_MASK                                                               0x0800L
+#define BIFPLR4_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                              0x1000L
+#define BIFPLR4_LINK_STATUS__DL_ACTIVE_MASK                                                                   0x2000L
+#define BIFPLR4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                   0x4000L
+#define BIFPLR4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                   0x8000L
+//BIFPLR4_SLOT_CAP
+#define BIFPLR4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                          0x0
+#define BIFPLR4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                       0x1
+#define BIFPLR4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                           0x2
+#define BIFPLR4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                       0x3
+#define BIFPLR4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                        0x4
+#define BIFPLR4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                             0x5
+#define BIFPLR4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                              0x6
+#define BIFPLR4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                         0x7
+#define BIFPLR4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                         0xf
+#define BIFPLR4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                                0x11
+#define BIFPLR4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                               0x12
+#define BIFPLR4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                            0x13
+#define BIFPLR4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                            0x00000001L
+#define BIFPLR4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                         0x00000002L
+#define BIFPLR4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                             0x00000004L
+#define BIFPLR4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                         0x00000008L
+#define BIFPLR4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                          0x00000010L
+#define BIFPLR4_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                               0x00000020L
+#define BIFPLR4_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                                0x00000040L
+#define BIFPLR4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                           0x00007F80L
+#define BIFPLR4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                           0x00018000L
+#define BIFPLR4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                  0x00020000L
+#define BIFPLR4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                                 0x00040000L
+#define BIFPLR4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                              0xFFF80000L
+//BIFPLR4_SLOT_CNTL
+#define BIFPLR4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                      0x0
+#define BIFPLR4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                       0x1
+#define BIFPLR4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                       0x2
+#define BIFPLR4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                  0x3
+#define BIFPLR4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                   0x4
+#define BIFPLR4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                             0x5
+#define BIFPLR4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                         0x6
+#define BIFPLR4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                          0x8
+#define BIFPLR4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                         0xa
+#define BIFPLR4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                  0xb
+#define BIFPLR4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                         0xc
+#define BIFPLR4_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                                 0xd
+#define BIFPLR4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                        0x0001L
+#define BIFPLR4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                         0x0002L
+#define BIFPLR4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                         0x0004L
+#define BIFPLR4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                    0x0008L
+#define BIFPLR4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                     0x0010L
+#define BIFPLR4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                               0x0020L
+#define BIFPLR4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                           0x00C0L
+#define BIFPLR4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                            0x0300L
+#define BIFPLR4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                           0x0400L
+#define BIFPLR4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                    0x0800L
+#define BIFPLR4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                           0x1000L
+#define BIFPLR4_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                   0x2000L
+//BIFPLR4_SLOT_STATUS
+#define BIFPLR4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                       0x0
+#define BIFPLR4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                        0x1
+#define BIFPLR4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                        0x2
+#define BIFPLR4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                   0x3
+#define BIFPLR4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                         0x4
+#define BIFPLR4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                          0x5
+#define BIFPLR4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                     0x6
+#define BIFPLR4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                              0x7
+#define BIFPLR4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                          0x8
+#define BIFPLR4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                         0x0001L
+#define BIFPLR4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                          0x0002L
+#define BIFPLR4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                          0x0004L
+#define BIFPLR4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                     0x0008L
+#define BIFPLR4_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                           0x0010L
+#define BIFPLR4_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                            0x0020L
+#define BIFPLR4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                       0x0040L
+#define BIFPLR4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                                0x0080L
+#define BIFPLR4_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                            0x0100L
+//BIFPLR4_ROOT_CNTL
+#define BIFPLR4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                         0x0
+#define BIFPLR4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                     0x1
+#define BIFPLR4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                        0x2
+#define BIFPLR4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                             0x3
+#define BIFPLR4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                  0x4
+#define BIFPLR4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                           0x0001L
+#define BIFPLR4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                       0x0002L
+#define BIFPLR4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                          0x0004L
+#define BIFPLR4_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                               0x0008L
+#define BIFPLR4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                    0x0010L
+//BIFPLR4_ROOT_CAP
+#define BIFPLR4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                      0x0
+#define BIFPLR4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                        0x0001L
+//BIFPLR4_ROOT_STATUS
+#define BIFPLR4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                          0x0
+#define BIFPLR4_ROOT_STATUS__PME_STATUS__SHIFT                                                                0x10
+#define BIFPLR4_ROOT_STATUS__PME_PENDING__SHIFT                                                               0x11
+#define BIFPLR4_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR4_ROOT_STATUS__PME_STATUS_MASK                                                                  0x00010000L
+#define BIFPLR4_ROOT_STATUS__PME_PENDING_MASK                                                                 0x00020000L
+//BIFPLR4_DEVICE_CAP2
+#define BIFPLR4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                               0x0
+#define BIFPLR4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                                 0x4
+#define BIFPLR4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                  0x5
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                                0x6
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                                0x7
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                                0x8
+#define BIFPLR4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                    0x9
+#define BIFPLR4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                                 0xa
+#define BIFPLR4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                             0xb
+#define BIFPLR4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                        0xc
+#define BIFPLR4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                             0xe
+#define BIFPLR4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                           0x10
+#define BIFPLR4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                           0x11
+#define BIFPLR4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                            0x12
+#define BIFPLR4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                              0x14
+#define BIFPLR4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                              0x15
+#define BIFPLR4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                  0x16
+#define BIFPLR4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                            0x18
+#define BIFPLR4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                             0x1a
+#define BIFPLR4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                                 0x0000000FL
+#define BIFPLR4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                   0x00000010L
+#define BIFPLR4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                    0x00000020L
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                  0x00000040L
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                  0x00000080L
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                  0x00000100L
+#define BIFPLR4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                      0x00000200L
+#define BIFPLR4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                   0x00000400L
+#define BIFPLR4_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                               0x00000800L
+#define BIFPLR4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                          0x00003000L
+#define BIFPLR4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                               0x0000C000L
+#define BIFPLR4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                             0x00010000L
+#define BIFPLR4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                             0x00020000L
+#define BIFPLR4_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                              0x000C0000L
+#define BIFPLR4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                                0x00100000L
+#define BIFPLR4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                                0x00200000L
+#define BIFPLR4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                    0x00C00000L
+#define BIFPLR4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                              0x03000000L
+#define BIFPLR4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                               0x04000000L
+#define BIFPLR4_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR4_DEVICE_CNTL2
+#define BIFPLR4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                        0x0
+#define BIFPLR4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                          0x4
+#define BIFPLR4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                        0x5
+#define BIFPLR4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                      0x6
+#define BIFPLR4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                                 0x7
+#define BIFPLR4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                       0x8
+#define BIFPLR4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                    0x9
+#define BIFPLR4_DEVICE_CNTL2__LTR_EN__SHIFT                                                                   0xa
+#define BIFPLR4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                             0xb
+#define BIFPLR4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                             0xc
+#define BIFPLR4_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                  0xd
+#define BIFPLR4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                              0xf
+#define BIFPLR4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                          0x000FL
+#define BIFPLR4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                            0x0010L
+#define BIFPLR4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                          0x0020L
+#define BIFPLR4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                        0x0040L
+#define BIFPLR4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                   0x0080L
+#define BIFPLR4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                         0x0100L
+#define BIFPLR4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                      0x0200L
+#define BIFPLR4_DEVICE_CNTL2__LTR_EN_MASK                                                                     0x0400L
+#define BIFPLR4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                               0x0800L
+#define BIFPLR4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                               0x1000L
+#define BIFPLR4_DEVICE_CNTL2__OBFF_EN_MASK                                                                    0x6000L
+#define BIFPLR4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                                0x8000L
+//BIFPLR4_DEVICE_STATUS2
+#define BIFPLR4_DEVICE_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR4_DEVICE_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR4_LINK_CAP2
+#define BIFPLR4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                        0x1
+#define BIFPLR4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                         0x8
+#define BIFPLR4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                    0x10
+#define BIFPLR4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                   0x17
+#define BIFPLR4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                   0x18
+#define BIFPLR4_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                               0x1f
+#define BIFPLR4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                          0x000000FEL
+#define BIFPLR4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                           0x00000100L
+#define BIFPLR4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                      0x007F0000L
+#define BIFPLR4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                     0x00800000L
+#define BIFPLR4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                     0x01000000L
+#define BIFPLR4_LINK_CAP2__DRS_SUPPORTED_MASK                                                                 0x80000000L
+//BIFPLR4_LINK_CNTL2
+#define BIFPLR4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                          0x0
+#define BIFPLR4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                           0x4
+#define BIFPLR4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                                0x5
+#define BIFPLR4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                      0x6
+#define BIFPLR4_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                                0x7
+#define BIFPLR4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                       0xa
+#define BIFPLR4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                             0xb
+#define BIFPLR4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                      0xc
+#define BIFPLR4_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                            0x000FL
+#define BIFPLR4_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                             0x0010L
+#define BIFPLR4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                  0x0020L
+#define BIFPLR4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                        0x0040L
+#define BIFPLR4_LINK_CNTL2__XMIT_MARGIN_MASK                                                                  0x0380L
+#define BIFPLR4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                         0x0400L
+#define BIFPLR4_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                               0x0800L
+#define BIFPLR4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                        0xF000L
+//BIFPLR4_LINK_STATUS2
+#define BIFPLR4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                     0x0
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                                0x1
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                          0x2
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                          0x3
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                          0x4
+#define BIFPLR4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                            0x5
+#define BIFPLR4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                        0x6
+#define BIFPLR4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                        0x7
+#define BIFPLR4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                     0x8
+#define BIFPLR4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                            0xc
+#define BIFPLR4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                     0xf
+#define BIFPLR4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                       0x0001L
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                  0x0002L
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                            0x0004L
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                            0x0008L
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                            0x0010L
+#define BIFPLR4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                              0x0020L
+#define BIFPLR4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                          0x0040L
+#define BIFPLR4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                          0x0080L
+#define BIFPLR4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                       0x0300L
+#define BIFPLR4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                              0x7000L
+#define BIFPLR4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                       0x8000L
+//BIFPLR4_SLOT_CAP2
+#define BIFPLR4_SLOT_CAP2__RESERVED__SHIFT                                                                    0x0
+#define BIFPLR4_SLOT_CAP2__RESERVED_MASK                                                                      0xFFFFFFFFL
+//BIFPLR4_SLOT_CNTL2
+#define BIFPLR4_SLOT_CNTL2__RESERVED__SHIFT                                                                   0x0
+#define BIFPLR4_SLOT_CNTL2__RESERVED_MASK                                                                     0xFFFFL
+//BIFPLR4_SLOT_STATUS2
+#define BIFPLR4_SLOT_STATUS2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR4_SLOT_STATUS2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR4_MSI_CAP_LIST
+#define BIFPLR4_MSI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR4_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR4_MSI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR4_MSI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR4_MSI_MSG_CNTL
+#define BIFPLR4_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                   0x0
+#define BIFPLR4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                            0x1
+#define BIFPLR4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                             0x4
+#define BIFPLR4_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                                0x7
+#define BIFPLR4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                                0x8
+#define BIFPLR4_MSI_MSG_CNTL__MSI_EN_MASK                                                                     0x0001L
+#define BIFPLR4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                              0x000EL
+#define BIFPLR4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                               0x0070L
+#define BIFPLR4_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                  0x0080L
+#define BIFPLR4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                  0x0100L
+//BIFPLR4_MSI_MSG_ADDR_LO
+#define BIFPLR4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                       0x2
+#define BIFPLR4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                         0xFFFFFFFCL
+//BIFPLR4_MSI_MSG_ADDR_HI
+#define BIFPLR4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                       0x0
+#define BIFPLR4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                         0xFFFFFFFFL
+//BIFPLR4_MSI_MSG_DATA
+#define BIFPLR4_MSI_MSG_DATA__MSI_DATA__SHIFT                                                                 0x0
+#define BIFPLR4_MSI_MSG_DATA__MSI_DATA_MASK                                                                   0xFFFFL
+//BIFPLR4_MSI_MSG_DATA_64
+#define BIFPLR4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                           0x0
+#define BIFPLR4_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                             0xFFFFL
+//BIFPLR4_SSID_CAP_LIST
+#define BIFPLR4_SSID_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR4_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR4_SSID_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR4_SSID_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR4_SSID_CAP
+#define BIFPLR4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                          0x0
+#define BIFPLR4_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                                 0x10
+#define BIFPLR4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR4_SSID_CAP__SUBSYSTEM_ID_MASK                                                                   0xFFFF0000L
+//BIFPLR4_MSI_MAP_CAP_LIST
+#define BIFPLR4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                               0x0
+#define BIFPLR4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                             0x8
+#define BIFPLR4_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                                 0x00FFL
+#define BIFPLR4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                               0xFF00L
+//BIFPLR4_MSI_MAP_CAP
+#define BIFPLR4_MSI_MAP_CAP__EN__SHIFT                                                                        0x0
+#define BIFPLR4_MSI_MAP_CAP__FIXD__SHIFT                                                                      0x1
+#define BIFPLR4_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                  0xb
+#define BIFPLR4_MSI_MAP_CAP__EN_MASK                                                                          0x0001L
+#define BIFPLR4_MSI_MAP_CAP__FIXD_MASK                                                                        0x0002L
+#define BIFPLR4_MSI_MAP_CAP__CAP_TYPE_MASK                                                                    0xF800L
+//BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                      0x0
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                     0x10
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                  0x14
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                       0x000F0000L
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                    0xFFF00000L
+//BIFPLR4_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR4_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR4_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR4_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                       0x4
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                         0x8
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                       0xa
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                      0x00000007L
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                         0x00000070L
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                           0x00000300L
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                         0x00000C00L
+//BIFPLR4_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                      0x0
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                             0x18
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                        0x000000FFL
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                               0xFF000000L
+//BIFPLR4_PCIE_PORT_VC_CNTL
+#define BIFPLR4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                   0x0
+#define BIFPLR4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                       0x1
+#define BIFPLR4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                     0x0001L
+#define BIFPLR4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                         0x000EL
+//BIFPLR4_PCIE_PORT_VC_STATUS
+#define BIFPLR4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                               0x0
+#define BIFPLR4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                                 0x0001L
+//BIFPLR4_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR4_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR4_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR4_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR4_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR4_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIFPLR4_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                              0x0
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                                0xFFFFFFFFL
+//BIFPLR4_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                              0x0
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                                0xFFFFFFFFL
+//BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR4_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                                 0x4
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                              0x5
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                                 0xc
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                  0xd
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                             0xe
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                           0xf
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                               0x10
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                                0x11
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                                 0x12
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                                0x13
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                          0x14
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                           0x15
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                          0x16
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                          0x17
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                                 0x18
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                  0x19
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                             0x1a
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                   0x00000010L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                                0x00000020L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                   0x00001000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                    0x00002000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                               0x00004000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                             0x00008000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                                 0x00010000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                  0x00020000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                   0x00040000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                  0x00080000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                            0x00100000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                             0x00200000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                            0x00400000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                            0x00800000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                   0x01000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                    0x02000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                               0x04000000L
+//BIFPLR4_PCIE_UNCORR_ERR_MASK
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                     0x4
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                  0x5
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                     0xc
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                      0xd
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                                 0xe
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                               0xf
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                   0x10
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                    0x11
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                     0x12
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                    0x13
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                              0x14
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                               0x15
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                              0x16
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                              0x17
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                     0x18
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                      0x19
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                                 0x1a
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                       0x00000010L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                    0x00000020L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                       0x00001000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                        0x00002000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                   0x00004000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                                 0x00008000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                     0x00010000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                      0x00020000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                       0x00040000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                      0x00080000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                                0x00100000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                                 0x00200000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                                0x00400000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                                0x00800000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                       0x01000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                        0x02000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                   0x04000000L
+//BIFPLR4_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                             0x4
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                          0x5
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                             0xc
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                              0xd
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                         0xe
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                       0xf
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                           0x10
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                            0x11
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                             0x12
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                            0x13
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                      0x14
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                       0x15
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                      0x16
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                      0x17
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                             0x18
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                              0x19
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                         0x1a
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                               0x00000010L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                            0x00000020L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                               0x00001000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                                0x00002000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                           0x00004000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                         0x00008000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                             0x00010000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                              0x00020000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                               0x00040000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                              0x00080000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                        0x00100000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                         0x00200000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                        0x00400000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                        0x00800000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                               0x01000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                                0x02000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                           0x04000000L
+//BIFPLR4_PCIE_CORR_ERR_STATUS
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                   0x0
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                   0x6
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                  0x7
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                       0x8
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                      0xc
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                     0xd
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                              0xe
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                              0xf
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                     0x00000001L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                     0x00000040L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                    0x00000080L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                         0x00000100L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                        0x00001000L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                       0x00002000L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                                0x00004000L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                                0x00008000L
+//BIFPLR4_PCIE_CORR_ERR_MASK
+#define BIFPLR4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                       0x0
+#define BIFPLR4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                       0x6
+#define BIFPLR4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                      0x7
+#define BIFPLR4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                           0x8
+#define BIFPLR4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                          0xc
+#define BIFPLR4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                         0xd
+#define BIFPLR4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                  0xe
+#define BIFPLR4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                  0xf
+#define BIFPLR4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                         0x00000001L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                         0x00000040L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                        0x00000080L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                             0x00000100L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                            0x00001000L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                           0x00002000L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                    0x00004000L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                    0x00008000L
+//BIFPLR4_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                   0x0
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                  0x7
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                   0x8
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                              0x9
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                               0xa
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                          0xb
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                  0xc
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                     0x0000001FL
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                    0x00000080L
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                     0x00000100L
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                                0x00000200L
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                                 0x00000400L
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                            0x00000800L
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                    0x00001000L
+//BIFPLR4_PCIE_HDR_LOG0
+#define BIFPLR4_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR4_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR4_PCIE_HDR_LOG1
+#define BIFPLR4_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR4_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR4_PCIE_HDR_LOG2
+#define BIFPLR4_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR4_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR4_PCIE_HDR_LOG3
+#define BIFPLR4_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR4_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR4_PCIE_ROOT_ERR_CMD
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                     0x0
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                                 0x1
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                    0x2
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                       0x00000001L
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                   0x00000002L
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                      0x00000004L
+//BIFPLR4_PCIE_ROOT_ERR_STATUS
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                               0x1
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                          0x2
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                     0x3
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                        0x4
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                          0x5
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                             0x6
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                              0x1b
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                      0x00000001L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                                 0x00000002L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                            0x00000004L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                       0x00000008L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                          0x00000010L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                            0x00000020L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                               0x00000040L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                                0xF8000000L
+//BIFPLR4_PCIE_ERR_SRC_ID
+#define BIFPLR4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                       0x0
+#define BIFPLR4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                             0x10
+#define BIFPLR4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                               0xFFFF0000L
+//BIFPLR4_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR4_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR4_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR4_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR4_PCIE_LINK_CNTL3
+#define BIFPLR4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                  0x0
+#define BIFPLR4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                          0x1
+#define BIFPLR4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                    0x00000001L
+#define BIFPLR4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                            0x00000002L
+//BIFPLR4_PCIE_LANE_ERROR_STATUS
+#define BIFPLR4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                         0x0
+#define BIFPLR4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                           0x0000FFFFL
+//BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR4_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR4_PCIE_ACS_CAP
+#define BIFPLR4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                        0x0
+#define BIFPLR4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                     0x1
+#define BIFPLR4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                     0x2
+#define BIFPLR4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                  0x3
+#define BIFPLR4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                      0x4
+#define BIFPLR4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                       0x5
+#define BIFPLR4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                    0x6
+#define BIFPLR4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                               0x8
+#define BIFPLR4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                          0x0001L
+#define BIFPLR4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                       0x0002L
+#define BIFPLR4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                       0x0004L
+#define BIFPLR4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                    0x0008L
+#define BIFPLR4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                        0x0010L
+#define BIFPLR4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                         0x0020L
+#define BIFPLR4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                      0x0040L
+#define BIFPLR4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                                 0xFF00L
+//BIFPLR4_PCIE_ACS_CNTL
+#define BIFPLR4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                                 0x1
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                                 0x2
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                              0x3
+#define BIFPLR4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                  0x4
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                   0x5
+#define BIFPLR4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                                0x6
+#define BIFPLR4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                      0x0001L
+#define BIFPLR4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                   0x0002L
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                   0x0004L
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                                0x0008L
+#define BIFPLR4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                    0x0010L
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                     0x0020L
+#define BIFPLR4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                  0x0040L
+//BIFPLR4_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR4_PCIE_MC_CAP
+#define BIFPLR4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                              0x0
+#define BIFPLR4_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                           0x8
+#define BIFPLR4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                        0xf
+#define BIFPLR4_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                                0x003FL
+#define BIFPLR4_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                             0x3F00L
+#define BIFPLR4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                          0x8000L
+//BIFPLR4_PCIE_MC_CNTL
+#define BIFPLR4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                             0x0
+#define BIFPLR4_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                                0xf
+#define BIFPLR4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                               0x003FL
+#define BIFPLR4_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                  0x8000L
+//BIFPLR4_PCIE_MC_ADDR0
+#define BIFPLR4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                            0x0
+#define BIFPLR4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                          0xc
+#define BIFPLR4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                              0x0000003FL
+#define BIFPLR4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                            0xFFFFF000L
+//BIFPLR4_PCIE_MC_ADDR1
+#define BIFPLR4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                          0x0
+#define BIFPLR4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                            0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_RCV0
+#define BIFPLR4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                             0x0
+#define BIFPLR4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                               0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_RCV1
+#define BIFPLR4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                             0x0
+#define BIFPLR4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                               0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_BLOCK_ALL0
+#define BIFPLR4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                     0x0
+#define BIFPLR4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_BLOCK_ALL1
+#define BIFPLR4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                     0x0
+#define BIFPLR4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                  0x0
+#define BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                    0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                  0x0
+#define BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                    0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                  0x0
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                                 0x6
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                    0x0000003FL
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                   0xFFFFFFC0L
+//BIFPLR4_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                                 0x0
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                   0xFFFFFFFFL
+//BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR4_PCIE_L1_PM_SUB_CAP
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                              0x0
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                              0x1
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                                0x2
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                                0x3
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                                0x4
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                               0x8
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                              0x10
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                              0x13
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                                0x00000001L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                                0x00000002L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                  0x00000004L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                  0x00000008L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                  0x00000010L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                                 0x0000FF00L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                                0x00030000L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                                0x00F80000L
+//BIFPLR4_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                    0x1
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                      0x2
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                      0x3
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                          0x8
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                          0x1d
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                      0x00000001L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                      0x00000002L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                        0x00000004L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                        0x00000008L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                            0x0000FF00L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                            0xE0000000L
+//BIFPLR4_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                                 0x0
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                                 0x3
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                   0x00000003L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                   0x000000F8L
+//BIFPLR4_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR4_PCIE_DPC_CAP_LIST
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                               0x5
+#define BIFPLR4_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                              0x6
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                   0x7
+#define BIFPLR4_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                     0x8
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                               0xc
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                      0x001FL
+#define BIFPLR4_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                                 0x0020L
+#define BIFPLR4_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                                0x0040L
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                     0x0080L
+#define BIFPLR4_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                       0x0F00L
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                                 0x1000L
+//BIFPLR4_PCIE_DPC_CNTL
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                      0x0
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                  0x2
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                    0x3
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                      0x4
+#define BIFPLR4_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                     0x5
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                    0x6
+#define BIFPLR4_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                                0x7
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                        0x0003L
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                    0x0004L
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                      0x0008L
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                        0x0010L
+#define BIFPLR4_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                       0x0020L
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                      0x0040L
+#define BIFPLR4_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                  0x0080L
+//BIFPLR4_PCIE_DPC_STATUS
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                    0x1
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                  0x3
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                           0x4
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                          0x5
+#define BIFPLR4_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                            0x8
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                      0x0001L
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                      0x0006L
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                    0x0008L
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                             0x0010L
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                            0x0060L
+#define BIFPLR4_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                              0x1F00L
+//BIFPLR4_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR4_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                          0x0
+#define BIFPLR4_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                            0xFFFFL
+//BIFPLR4_PCIE_RP_PIO_STATUS
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR4_PCIE_RP_PIO_MASK
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                           0x0
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                           0x1
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                              0x2
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                            0x8
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                            0x9
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                               0xa
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                           0x10
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                           0x11
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                              0x12
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                             0x00000001L
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                             0x00000002L
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                                0x00000004L
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                              0x00000100L
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                              0x00000200L
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                                 0x00000400L
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                             0x00010000L
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                             0x00020000L
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                                0x00040000L
+//BIFPLR4_PCIE_RP_PIO_SEVERITY
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR4_PCIE_RP_PIO_SYSERROR
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR4_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                      0x0
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                      0x1
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                         0x2
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                       0x8
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                       0x9
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                          0xa
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                      0x10
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                      0x11
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                         0x12
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                        0x00000001L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                        0x00000002L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                           0x00000004L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                         0x00000100L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                         0x00000200L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                            0x00000400L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                        0x00010000L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                        0x00020000L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                           0x00040000L
+//BIFPLR4_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR4_PCIE_ESM_CAP_LIST
+#define BIFPLR4_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR4_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                             0x10
+#define BIFPLR4_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                            0x14
+#define BIFPLR4_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                                0x0000FFFFL
+#define BIFPLR4_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                               0x000F0000L
+#define BIFPLR4_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                              0xFFF00000L
+//BIFPLR4_PCIE_ESM_HEADER_1
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                       0x0
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                         0x10
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                         0x14
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                           0x000F0000L
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                           0xFFF00000L
+//BIFPLR4_PCIE_ESM_HEADER_2
+#define BIFPLR4_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR4_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                                0xFFFFL
+//BIFPLR4_PCIE_ESM_STATUS
+#define BIFPLR4_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                  0x9
+#define BIFPLR4_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                      0x01FFL
+#define BIFPLR4_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                    0x0E00L
+//BIFPLR4_PCIE_ESM_CTRL
+#define BIFPLR4_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                             0xf
+#define BIFPLR4_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                               0x8000L
+//BIFPLR4_PCIE_ESM_CAP_1
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                               0x0
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                               0x1
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                               0x2
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                               0x3
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                               0x4
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                               0x5
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                               0x6
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                               0x7
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                               0x8
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                               0x9
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                               0xa
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                               0xb
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                               0xc
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                               0xd
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                               0xe
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                               0xf
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                               0x10
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                               0x11
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                               0x12
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                               0x13
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                              0x14
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                              0x15
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                              0x16
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                              0x17
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                              0x18
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                              0x19
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                              0x1a
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                              0x1b
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                              0x1c
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                              0x1d
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                                 0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                                 0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                                 0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                                 0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                                 0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                                 0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                                 0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                                 0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                                 0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                                 0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                                 0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                                 0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                                 0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                                 0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                                 0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                                 0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                                 0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                                 0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                                 0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                                 0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                                0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                                0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                                0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                                0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                                0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                                0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                                0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                                0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                                0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                                0x20000000L
+//BIFPLR4_PCIE_ESM_CAP_2
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                              0x0
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                              0x1
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                              0x2
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                              0x3
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                              0x4
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                              0x5
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                              0x6
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                              0x7
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                              0x8
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                              0x9
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                              0xa
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                              0xb
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                              0xc
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                              0xd
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                              0xe
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                              0xf
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                              0x10
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                              0x11
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                              0x12
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                              0x13
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                              0x14
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                              0x15
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                              0x16
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                              0x17
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                              0x18
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                              0x19
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                              0x1a
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                              0x1b
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                              0x1c
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                              0x1d
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                                0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                                0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                                0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                                0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                                0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                                0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                                0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                                0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                                0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                                0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                                0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                                0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                                0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                                0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                                0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                                0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                                0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                                0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                                0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                                0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                                0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                                0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                                0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                                0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                                0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                                0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                                0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                                0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                                0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                                0x20000000L
+//BIFPLR4_PCIE_ESM_CAP_3
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                              0x0
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                              0x1
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                              0x2
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                              0x3
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                              0x4
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                              0x5
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                              0x6
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                              0x7
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                              0x8
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                              0x9
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                              0xa
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                              0xb
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                              0xc
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                              0xd
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                              0xe
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                              0xf
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                              0x10
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                              0x11
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                              0x12
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                              0x13
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                                0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                                0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                                0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                                0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                                0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                                0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                                0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                                0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                                0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                                0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                                0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                                0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                                0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                                0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                                0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                                0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                                0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                                0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                                0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                                0x00080000L
+//BIFPLR4_PCIE_ESM_CAP_4
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                              0x0
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                              0x1
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                              0x2
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                              0x3
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                              0x4
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                              0x5
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                              0x6
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                              0x7
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                              0x8
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                              0x9
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                              0xa
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                              0xb
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                              0xc
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                              0xd
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                              0xe
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                              0xf
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                              0x10
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                              0x11
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                              0x12
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                              0x13
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                              0x14
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                              0x15
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                              0x16
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                              0x17
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                              0x18
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                              0x19
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                              0x1a
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                              0x1b
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                              0x1c
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                              0x1d
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                                0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                                0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                                0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                                0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                                0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                                0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                                0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                                0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                                0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                                0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                                0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                                0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                                0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                                0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                                0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                                0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                                0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                                0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                                0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                                0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                                0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                                0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                                0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                                0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                                0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                                0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                                0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                                0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                                0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                                0x20000000L
+//BIFPLR4_PCIE_ESM_CAP_5
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                              0x0
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                              0x1
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                              0x2
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                              0x3
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                              0x4
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                              0x5
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                              0x6
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                              0x7
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                              0x8
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                              0x9
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                              0xa
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                              0xb
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                              0xc
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                              0xd
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                              0xe
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                              0xf
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                              0x10
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                              0x11
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                              0x12
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                              0x13
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                              0x14
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                              0x15
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                              0x16
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                              0x17
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                              0x18
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                              0x19
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                              0x1a
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                              0x1b
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                              0x1c
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                              0x1d
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                                0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                                0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                                0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                                0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                                0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                                0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                                0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                                0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                                0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                                0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                                0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                                0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                                0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                                0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                                0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                                0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                                0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                                0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                                0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                                0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                                0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                                0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                                0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                                0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                                0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                                0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                                0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                                0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                                0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                                0x20000000L
+//BIFPLR4_PCIE_ESM_CAP_6
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                              0x0
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                              0x1
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                              0x2
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                              0x3
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                              0x4
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                              0x5
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                              0x6
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                              0x7
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                              0x8
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                              0x9
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                              0xa
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                              0xb
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                              0xc
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                              0xd
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                              0xe
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                              0xf
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                              0x10
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                              0x11
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                              0x12
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                              0x13
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                              0x14
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                              0x15
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                              0x16
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                              0x17
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                              0x18
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                              0x19
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                              0x1a
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                              0x1b
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                              0x1c
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                              0x1d
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                                0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                                0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                                0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                                0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                                0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                                0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                                0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                                0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                                0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                                0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                                0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                                0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                                0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                                0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                                0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                                0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                                0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                                0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                                0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                                0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                                0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                                0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                                0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                                0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                                0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                                0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                                0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                                0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                                0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                                0x20000000L
+//BIFPLR4_PCIE_ESM_CAP_7
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                              0x0
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                              0x1
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                              0x2
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                              0x3
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                              0x4
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                              0x5
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                              0x6
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                              0x7
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                              0x8
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                              0x9
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                              0xa
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                              0xb
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                              0xc
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                              0xd
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                              0xe
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                              0xf
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                              0x10
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                              0x11
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                              0x12
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                              0x13
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                              0x14
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                              0x15
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                              0x16
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                              0x17
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                              0x18
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                              0x19
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                              0x1a
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                              0x1b
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                              0x1c
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                              0x1d
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                              0x1e
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                                0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                                0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                                0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                                0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                                0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                                0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                                0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                                0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                                0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                                0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                                0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                                0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                                0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                                0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                                0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                                0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                                0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                                0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                                0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                                0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                                0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                                0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                                0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                                0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                                0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                                0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                                0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                                0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                                0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                                0x20000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                                0x40000000L
+//BIFPLR4_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR4_DATA_LINK_FEATURE_CAP
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                         0x0
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                        0x1
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                             0x1f
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                           0x00000001L
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                          0x007FFFFEL
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                               0x80000000L
+//BIFPLR4_DATA_LINK_FEATURE_STATUS
+#define BIFPLR4_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                         0x0
+#define BIFPLR4_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                   0x1f
+#define BIFPLR4_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                           0x007FFFFFL
+#define BIFPLR4_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                     0x80000000L
+//BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                    0x10
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                   0x14
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                      0x000F0000L
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                     0xFFF00000L
+//BIFPLR4_LINK_CAP_16GT
+#define BIFPLR4_LINK_CAP_16GT__RESERVED__SHIFT                                                                0x0
+#define BIFPLR4_LINK_CAP_16GT__RESERVED_MASK                                                                  0xFFFFFFFFL
+//BIFPLR4_LINK_CNTL_16GT
+#define BIFPLR4_LINK_CNTL_16GT__RESERVED__SHIFT                                                               0x0
+#define BIFPLR4_LINK_CNTL_16GT__RESERVED_MASK                                                                 0xFFFFFFFFL
+//BIFPLR4_LINK_STATUS_16GT
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                           0x0
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                     0x1
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                     0x2
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                     0x3
+#define BIFPLR4_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                       0x4
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                             0x00000001L
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                       0x00000002L
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                       0x00000004L
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                       0x00000008L
+#define BIFPLR4_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                         0x00000010L
+//BIFPLR4_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR4_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR4_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR4_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR4_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR4_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR4_MARGINING_PORT_CAP
+#define BIFPLR4_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                            0x0
+#define BIFPLR4_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                              0x0001L
+//BIFPLR4_MARGINING_PORT_STATUS
+#define BIFPLR4_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                                 0x0
+#define BIFPLR4_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                        0x1
+#define BIFPLR4_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                   0x0001L
+#define BIFPLR4_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                          0x0002L
+//BIFPLR4_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR4_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR4_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR4_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR4_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR4_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR4_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR4_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR4_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR4_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR4_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR4_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR4_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR4_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR4_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR4_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR4_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR4_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR4_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR4_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR4_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_PCIE_CCIX_CAP_LIST
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                            0x10
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                           0x14
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                               0x0000FFFFL
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                              0x000F0000L
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                             0xFFF00000L
+//BIFPLR4_PCIE_CCIX_HEADER_1
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR4_PCIE_CCIX_HEADER_2
+#define BIFPLR4_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR4_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                               0xFFFFL
+//BIFPLR4_PCIE_CCIX_CAP
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                      0x0
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                         0x1
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                        0x3
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                    0x4
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                          0x8
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                        0x0001L
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                           0x0006L
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                          0x0008L
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                      0x0070L
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                            0x0700L
+//BIFPLR4_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                              0x0
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                                0x1
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                                0x2
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                               0x5
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                               0x9
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                               0xe
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                                0x00000001L
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                  0x00000002L
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                  0x00000004L
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                                 0x00000020L
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                                 0x00000200L
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                                 0x00004000L
+//BIFPLR4_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR4_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                       0x0
+#define BIFPLR4_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIFPLR4_PCIE_CCIX_ESM_STATUS
+#define BIFPLR4_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                            0x0
+#define BIFPLR4_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                         0x7
+#define BIFPLR4_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                              0x0000007FL
+#define BIFPLR4_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                           0x00000080L
+//BIFPLR4_PCIE_CCIX_ESM_CNTL
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                     0x0
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                            0x7
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                     0x8
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                         0xf
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                           0x10
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                           0x14
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                  0x18
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                    0x19
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                              0x1a
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                       0x0000007FL
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                              0x00000080L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                       0x00007F00L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                           0x00008000L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                             0x00070000L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                             0x00700000L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                    0x01000000L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                      0x02000000L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                                0x1C000000L
+//BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_PCIE_CCIX_TRANS_CAP
+#define BIFPLR4_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                                 0x0
+#define BIFPLR4_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                   0x00000001L
+//BIFPLR4_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR4_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                                 0x0
+#define BIFPLR4_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                   0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+//BIFPLR5_VENDOR_ID
+#define BIFPLR5_VENDOR_ID__VENDOR_ID__SHIFT                                                                   0x0
+#define BIFPLR5_VENDOR_ID__VENDOR_ID_MASK                                                                     0xFFFFL
+//BIFPLR5_DEVICE_ID
+#define BIFPLR5_DEVICE_ID__DEVICE_ID__SHIFT                                                                   0x0
+#define BIFPLR5_DEVICE_ID__DEVICE_ID_MASK                                                                     0xFFFFL
+//BIFPLR5_COMMAND
+#define BIFPLR5_COMMAND__IO_ACCESS_EN__SHIFT                                                                  0x0
+#define BIFPLR5_COMMAND__MEM_ACCESS_EN__SHIFT                                                                 0x1
+#define BIFPLR5_COMMAND__BUS_MASTER_EN__SHIFT                                                                 0x2
+#define BIFPLR5_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                              0x3
+#define BIFPLR5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                       0x4
+#define BIFPLR5_COMMAND__PAL_SNOOP_EN__SHIFT                                                                  0x5
+#define BIFPLR5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                         0x6
+#define BIFPLR5_COMMAND__AD_STEPPING__SHIFT                                                                   0x7
+#define BIFPLR5_COMMAND__SERR_EN__SHIFT                                                                       0x8
+#define BIFPLR5_COMMAND__FAST_B2B_EN__SHIFT                                                                   0x9
+#define BIFPLR5_COMMAND__INT_DIS__SHIFT                                                                       0xa
+#define BIFPLR5_COMMAND__IO_ACCESS_EN_MASK                                                                    0x0001L
+#define BIFPLR5_COMMAND__MEM_ACCESS_EN_MASK                                                                   0x0002L
+#define BIFPLR5_COMMAND__BUS_MASTER_EN_MASK                                                                   0x0004L
+#define BIFPLR5_COMMAND__SPECIAL_CYCLE_EN_MASK                                                                0x0008L
+#define BIFPLR5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                         0x0010L
+#define BIFPLR5_COMMAND__PAL_SNOOP_EN_MASK                                                                    0x0020L
+#define BIFPLR5_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                           0x0040L
+#define BIFPLR5_COMMAND__AD_STEPPING_MASK                                                                     0x0080L
+#define BIFPLR5_COMMAND__SERR_EN_MASK                                                                         0x0100L
+#define BIFPLR5_COMMAND__FAST_B2B_EN_MASK                                                                     0x0200L
+#define BIFPLR5_COMMAND__INT_DIS_MASK                                                                         0x0400L
+//BIFPLR5_STATUS
+#define BIFPLR5_STATUS__IMMEDIATE_READINESS__SHIFT                                                            0x0
+#define BIFPLR5_STATUS__INT_STATUS__SHIFT                                                                     0x3
+#define BIFPLR5_STATUS__CAP_LIST__SHIFT                                                                       0x4
+#define BIFPLR5_STATUS__PCI_66_CAP__SHIFT                                                                     0x5
+#define BIFPLR5_STATUS__FAST_BACK_CAPABLE__SHIFT                                                              0x7
+#define BIFPLR5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                       0x8
+#define BIFPLR5_STATUS__DEVSEL_TIMING__SHIFT                                                                  0x9
+#define BIFPLR5_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                            0xb
+#define BIFPLR5_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                          0xc
+#define BIFPLR5_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                          0xd
+#define BIFPLR5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                          0xe
+#define BIFPLR5_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                          0xf
+#define BIFPLR5_STATUS__IMMEDIATE_READINESS_MASK                                                              0x0001L
+#define BIFPLR5_STATUS__INT_STATUS_MASK                                                                       0x0008L
+#define BIFPLR5_STATUS__CAP_LIST_MASK                                                                         0x0010L
+#define BIFPLR5_STATUS__PCI_66_CAP_MASK                                                                       0x0020L
+#define BIFPLR5_STATUS__FAST_BACK_CAPABLE_MASK                                                                0x0080L
+#define BIFPLR5_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                         0x0100L
+#define BIFPLR5_STATUS__DEVSEL_TIMING_MASK                                                                    0x0600L
+#define BIFPLR5_STATUS__SIGNAL_TARGET_ABORT_MASK                                                              0x0800L
+#define BIFPLR5_STATUS__RECEIVED_TARGET_ABORT_MASK                                                            0x1000L
+#define BIFPLR5_STATUS__RECEIVED_MASTER_ABORT_MASK                                                            0x2000L
+#define BIFPLR5_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                            0x4000L
+#define BIFPLR5_STATUS__PARITY_ERROR_DETECTED_MASK                                                            0x8000L
+//BIFPLR5_REVISION_ID
+#define BIFPLR5_REVISION_ID__MINOR_REV_ID__SHIFT                                                              0x0
+#define BIFPLR5_REVISION_ID__MAJOR_REV_ID__SHIFT                                                              0x4
+#define BIFPLR5_REVISION_ID__MINOR_REV_ID_MASK                                                                0x0FL
+#define BIFPLR5_REVISION_ID__MAJOR_REV_ID_MASK                                                                0xF0L
+//BIFPLR5_PROG_INTERFACE
+#define BIFPLR5_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                         0x0
+#define BIFPLR5_PROG_INTERFACE__PROG_INTERFACE_MASK                                                           0xFFL
+//BIFPLR5_SUB_CLASS
+#define BIFPLR5_SUB_CLASS__SUB_CLASS__SHIFT                                                                   0x0
+#define BIFPLR5_SUB_CLASS__SUB_CLASS_MASK                                                                     0xFFL
+//BIFPLR5_BASE_CLASS
+#define BIFPLR5_BASE_CLASS__BASE_CLASS__SHIFT                                                                 0x0
+#define BIFPLR5_BASE_CLASS__BASE_CLASS_MASK                                                                   0xFFL
+//BIFPLR5_CACHE_LINE
+#define BIFPLR5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                            0x0
+#define BIFPLR5_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                              0xFFL
+//BIFPLR5_LATENCY
+#define BIFPLR5_LATENCY__LATENCY_TIMER__SHIFT                                                                 0x0
+#define BIFPLR5_LATENCY__LATENCY_TIMER_MASK                                                                   0xFFL
+//BIFPLR5_HEADER
+#define BIFPLR5_HEADER__HEADER_TYPE__SHIFT                                                                    0x0
+#define BIFPLR5_HEADER__DEVICE_TYPE__SHIFT                                                                    0x7
+#define BIFPLR5_HEADER__HEADER_TYPE_MASK                                                                      0x7FL
+#define BIFPLR5_HEADER__DEVICE_TYPE_MASK                                                                      0x80L
+//BIFPLR5_BIST
+#define BIFPLR5_BIST__BIST_COMP__SHIFT                                                                        0x0
+#define BIFPLR5_BIST__BIST_STRT__SHIFT                                                                        0x6
+#define BIFPLR5_BIST__BIST_CAP__SHIFT                                                                         0x7
+#define BIFPLR5_BIST__BIST_COMP_MASK                                                                          0x0FL
+#define BIFPLR5_BIST__BIST_STRT_MASK                                                                          0x40L
+#define BIFPLR5_BIST__BIST_CAP_MASK                                                                           0x80L
+//BIFPLR5_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                    0x0
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                  0x8
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                    0x10
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                        0x18
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                      0x000000FFL
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                    0x0000FF00L
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                      0x00FF0000L
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                          0xFF000000L
+//BIFPLR5_IO_BASE_LIMIT
+#define BIFPLR5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                            0x0
+#define BIFPLR5_IO_BASE_LIMIT__IO_BASE__SHIFT                                                                 0x4
+#define BIFPLR5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                           0x8
+#define BIFPLR5_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                                0xc
+#define BIFPLR5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                              0x000FL
+#define BIFPLR5_IO_BASE_LIMIT__IO_BASE_MASK                                                                   0x00F0L
+#define BIFPLR5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                             0x0F00L
+#define BIFPLR5_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                  0xF000L
+//BIFPLR5_SECONDARY_STATUS
+#define BIFPLR5_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIFPLR5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIFPLR5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIFPLR5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIFPLR5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIFPLR5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIFPLR5_SECONDARY_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIFPLR5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIFPLR5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIFPLR5_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIFPLR5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIFPLR5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIFPLR5_MEM_BASE_LIMIT
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                         0x4
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                         0x10
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                        0x14
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                            0x0000000FL
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                           0x0000FFF0L
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                           0x000F0000L
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                          0xFFF00000L
+//BIFPLR5_PREF_BASE_LIMIT
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                    0x0
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                   0x4
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                   0x10
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                  0x14
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                      0x0000000FL
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                     0x0000FFF0L
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                     0x000F0000L
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                    0xFFF00000L
+//BIFPLR5_PREF_BASE_UPPER
+#define BIFPLR5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                       0x0
+#define BIFPLR5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                         0xFFFFFFFFL
+//BIFPLR5_PREF_LIMIT_UPPER
+#define BIFPLR5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                     0x0
+#define BIFPLR5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_IO_BASE_LIMIT_HI
+#define BIFPLR5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                        0x0
+#define BIFPLR5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                       0x10
+#define BIFPLR5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                          0x0000FFFFL
+#define BIFPLR5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                         0xFFFF0000L
+//BIFPLR5_CAP_PTR
+#define BIFPLR5_CAP_PTR__CAP_PTR__SHIFT                                                                       0x0
+#define BIFPLR5_CAP_PTR__CAP_PTR_MASK                                                                         0xFFL
+//BIFPLR5_ROM_BASE_ADDR
+#define BIFPLR5_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                               0x0
+#define BIFPLR5_ROM_BASE_ADDR__BASE_ADDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR5_INTERRUPT_LINE
+#define BIFPLR5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                         0x0
+#define BIFPLR5_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                           0xFFL
+//BIFPLR5_INTERRUPT_PIN
+#define BIFPLR5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                           0x0
+#define BIFPLR5_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                             0xFFL
+//BIFPLR5_IRQ_BRIDGE_CNTL
+#define BIFPLR5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                    0x0
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                               0x1
+#define BIFPLR5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                                0x2
+#define BIFPLR5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                                0x3
+#define BIFPLR5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                               0x4
+#define BIFPLR5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                     0x5
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                   0x6
+#define BIFPLR5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                           0x7
+#define BIFPLR5_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                                 0x8
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                               0x9
+#define BIFPLR5_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                  0xa
+#define BIFPLR5_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                             0xb
+#define BIFPLR5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                      0x0001L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                                 0x0002L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                  0x0004L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                  0x0008L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                                 0x0010L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                       0x0020L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                     0x0040L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                             0x0080L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                   0x0100L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                                 0x0200L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                    0x0400L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                               0x0800L
+//BIFPLR5_EXT_BRIDGE_CNTL
+#define BIFPLR5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                         0x0
+#define BIFPLR5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                           0x01L
+//BIFPLR5_VENDOR_CAP_LIST
+#define BIFPLR5_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR5_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR5_VENDOR_CAP_LIST__LENGTH__SHIFT                                                                0x10
+#define BIFPLR5_VENDOR_CAP_LIST__CAP_ID_MASK                                                                  0x000000FFL
+#define BIFPLR5_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                                0x0000FF00L
+#define BIFPLR5_VENDOR_CAP_LIST__LENGTH_MASK                                                                  0x00FF0000L
+//BIFPLR5_ADAPTER_ID_W
+#define BIFPLR5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                      0x0
+#define BIFPLR5_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                             0x10
+#define BIFPLR5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR5_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                               0xFFFF0000L
+//BIFPLR5_PMI_CAP_LIST
+#define BIFPLR5_PMI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR5_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR5_PMI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR5_PMI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR5_PMI_CAP
+#define BIFPLR5_PMI_CAP__VERSION__SHIFT                                                                       0x0
+#define BIFPLR5_PMI_CAP__PME_CLOCK__SHIFT                                                                     0x3
+#define BIFPLR5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                           0x4
+#define BIFPLR5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                             0x5
+#define BIFPLR5_PMI_CAP__AUX_CURRENT__SHIFT                                                                   0x6
+#define BIFPLR5_PMI_CAP__D1_SUPPORT__SHIFT                                                                    0x9
+#define BIFPLR5_PMI_CAP__D2_SUPPORT__SHIFT                                                                    0xa
+#define BIFPLR5_PMI_CAP__PME_SUPPORT__SHIFT                                                                   0xb
+#define BIFPLR5_PMI_CAP__VERSION_MASK                                                                         0x0007L
+#define BIFPLR5_PMI_CAP__PME_CLOCK_MASK                                                                       0x0008L
+#define BIFPLR5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                             0x0010L
+#define BIFPLR5_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                               0x0020L
+#define BIFPLR5_PMI_CAP__AUX_CURRENT_MASK                                                                     0x01C0L
+#define BIFPLR5_PMI_CAP__D1_SUPPORT_MASK                                                                      0x0200L
+#define BIFPLR5_PMI_CAP__D2_SUPPORT_MASK                                                                      0x0400L
+#define BIFPLR5_PMI_CAP__PME_SUPPORT_MASK                                                                     0xF800L
+//BIFPLR5_PMI_STATUS_CNTL
+#define BIFPLR5_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                           0x0
+#define BIFPLR5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                         0x3
+#define BIFPLR5_PMI_STATUS_CNTL__PME_EN__SHIFT                                                                0x8
+#define BIFPLR5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                           0x9
+#define BIFPLR5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                            0xd
+#define BIFPLR5_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                            0xf
+#define BIFPLR5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                         0x16
+#define BIFPLR5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                            0x17
+#define BIFPLR5_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                              0x18
+#define BIFPLR5_PMI_STATUS_CNTL__POWER_STATE_MASK                                                             0x00000003L
+#define BIFPLR5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                           0x00000008L
+#define BIFPLR5_PMI_STATUS_CNTL__PME_EN_MASK                                                                  0x00000100L
+#define BIFPLR5_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                             0x00001E00L
+#define BIFPLR5_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                              0x00006000L
+#define BIFPLR5_PMI_STATUS_CNTL__PME_STATUS_MASK                                                              0x00008000L
+#define BIFPLR5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                           0x00400000L
+#define BIFPLR5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                              0x00800000L
+#define BIFPLR5_PMI_STATUS_CNTL__PMI_DATA_MASK                                                                0xFF000000L
+//BIFPLR5_PCIE_CAP_LIST
+#define BIFPLR5_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR5_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR5_PCIE_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR5_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR5_PCIE_CAP
+#define BIFPLR5_PCIE_CAP__VERSION__SHIFT                                                                      0x0
+#define BIFPLR5_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                  0x4
+#define BIFPLR5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                             0x8
+#define BIFPLR5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                              0x9
+#define BIFPLR5_PCIE_CAP__VERSION_MASK                                                                        0x000FL
+#define BIFPLR5_PCIE_CAP__DEVICE_TYPE_MASK                                                                    0x00F0L
+#define BIFPLR5_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                               0x0100L
+#define BIFPLR5_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                                0x3E00L
+//BIFPLR5_DEVICE_CAP
+#define BIFPLR5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                        0x0
+#define BIFPLR5_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                               0x3
+#define BIFPLR5_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                               0x5
+#define BIFPLR5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                     0x6
+#define BIFPLR5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                      0x9
+#define BIFPLR5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                   0xf
+#define BIFPLR5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                  0x12
+#define BIFPLR5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                  0x1a
+#define BIFPLR5_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                                0x1c
+#define BIFPLR5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                          0x00000007L
+#define BIFPLR5_DEVICE_CAP__PHANTOM_FUNC_MASK                                                                 0x00000018L
+#define BIFPLR5_DEVICE_CAP__EXTENDED_TAG_MASK                                                                 0x00000020L
+#define BIFPLR5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                       0x000001C0L
+#define BIFPLR5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                        0x00000E00L
+#define BIFPLR5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                     0x00008000L
+#define BIFPLR5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                    0x03FC0000L
+#define BIFPLR5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                    0x0C000000L
+#define BIFPLR5_DEVICE_CAP__FLR_CAPABLE_MASK                                                                  0x10000000L
+//BIFPLR5_DEVICE_CNTL
+#define BIFPLR5_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                               0x0
+#define BIFPLR5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                          0x1
+#define BIFPLR5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                              0x2
+#define BIFPLR5_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                             0x3
+#define BIFPLR5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                            0x4
+#define BIFPLR5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                          0x5
+#define BIFPLR5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                           0x8
+#define BIFPLR5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                           0x9
+#define BIFPLR5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                           0xa
+#define BIFPLR5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                               0xb
+#define BIFPLR5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                     0xc
+#define BIFPLR5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                       0xf
+#define BIFPLR5_DEVICE_CNTL__CORR_ERR_EN_MASK                                                                 0x0001L
+#define BIFPLR5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                            0x0002L
+#define BIFPLR5_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                                0x0004L
+#define BIFPLR5_DEVICE_CNTL__USR_REPORT_EN_MASK                                                               0x0008L
+#define BIFPLR5_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                              0x0010L
+#define BIFPLR5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                            0x00E0L
+#define BIFPLR5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                             0x0100L
+#define BIFPLR5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                             0x0200L
+#define BIFPLR5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                             0x0400L
+#define BIFPLR5_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                                 0x0800L
+#define BIFPLR5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                       0x7000L
+#define BIFPLR5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                         0x8000L
+//BIFPLR5_DEVICE_STATUS
+#define BIFPLR5_DEVICE_STATUS__CORR_ERR__SHIFT                                                                0x0
+#define BIFPLR5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                           0x1
+#define BIFPLR5_DEVICE_STATUS__FATAL_ERR__SHIFT                                                               0x2
+#define BIFPLR5_DEVICE_STATUS__USR_DETECTED__SHIFT                                                            0x3
+#define BIFPLR5_DEVICE_STATUS__AUX_PWR__SHIFT                                                                 0x4
+#define BIFPLR5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                       0x5
+#define BIFPLR5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                           0x6
+#define BIFPLR5_DEVICE_STATUS__CORR_ERR_MASK                                                                  0x0001L
+#define BIFPLR5_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                             0x0002L
+#define BIFPLR5_DEVICE_STATUS__FATAL_ERR_MASK                                                                 0x0004L
+#define BIFPLR5_DEVICE_STATUS__USR_DETECTED_MASK                                                              0x0008L
+#define BIFPLR5_DEVICE_STATUS__AUX_PWR_MASK                                                                   0x0010L
+#define BIFPLR5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                         0x0020L
+#define BIFPLR5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                             0x0040L
+//BIFPLR5_LINK_CAP
+#define BIFPLR5_LINK_CAP__LINK_SPEED__SHIFT                                                                   0x0
+#define BIFPLR5_LINK_CAP__LINK_WIDTH__SHIFT                                                                   0x4
+#define BIFPLR5_LINK_CAP__PM_SUPPORT__SHIFT                                                                   0xa
+#define BIFPLR5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                             0xc
+#define BIFPLR5_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                              0xf
+#define BIFPLR5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                       0x12
+#define BIFPLR5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                  0x13
+#define BIFPLR5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                  0x14
+#define BIFPLR5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                     0x15
+#define BIFPLR5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                  0x16
+#define BIFPLR5_LINK_CAP__PORT_NUMBER__SHIFT                                                                  0x18
+#define BIFPLR5_LINK_CAP__LINK_SPEED_MASK                                                                     0x0000000FL
+#define BIFPLR5_LINK_CAP__LINK_WIDTH_MASK                                                                     0x000003F0L
+#define BIFPLR5_LINK_CAP__PM_SUPPORT_MASK                                                                     0x00000C00L
+#define BIFPLR5_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                               0x00007000L
+#define BIFPLR5_LINK_CAP__L1_EXIT_LATENCY_MASK                                                                0x00038000L
+#define BIFPLR5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                         0x00040000L
+#define BIFPLR5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                    0x00080000L
+#define BIFPLR5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                    0x00100000L
+#define BIFPLR5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                       0x00200000L
+#define BIFPLR5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                    0x00400000L
+#define BIFPLR5_LINK_CAP__PORT_NUMBER_MASK                                                                    0xFF000000L
+//BIFPLR5_LINK_CNTL
+#define BIFPLR5_LINK_CNTL__PM_CONTROL__SHIFT                                                                  0x0
+#define BIFPLR5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                           0x3
+#define BIFPLR5_LINK_CNTL__LINK_DIS__SHIFT                                                                    0x4
+#define BIFPLR5_LINK_CNTL__RETRAIN_LINK__SHIFT                                                                0x5
+#define BIFPLR5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                            0x6
+#define BIFPLR5_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                               0x7
+#define BIFPLR5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                   0x8
+#define BIFPLR5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                                 0x9
+#define BIFPLR5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                   0xa
+#define BIFPLR5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                   0xb
+#define BIFPLR5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                       0xe
+#define BIFPLR5_LINK_CNTL__PM_CONTROL_MASK                                                                    0x0003L
+#define BIFPLR5_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                             0x0008L
+#define BIFPLR5_LINK_CNTL__LINK_DIS_MASK                                                                      0x0010L
+#define BIFPLR5_LINK_CNTL__RETRAIN_LINK_MASK                                                                  0x0020L
+#define BIFPLR5_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                              0x0040L
+#define BIFPLR5_LINK_CNTL__EXTENDED_SYNC_MASK                                                                 0x0080L
+#define BIFPLR5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                     0x0100L
+#define BIFPLR5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                   0x0200L
+#define BIFPLR5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                     0x0400L
+#define BIFPLR5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                     0x0800L
+#define BIFPLR5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                         0xC000L
+//BIFPLR5_LINK_STATUS
+#define BIFPLR5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                     0x4
+#define BIFPLR5_LINK_STATUS__LINK_TRAINING__SHIFT                                                             0xb
+#define BIFPLR5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                            0xc
+#define BIFPLR5_LINK_STATUS__DL_ACTIVE__SHIFT                                                                 0xd
+#define BIFPLR5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                                 0xe
+#define BIFPLR5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                                 0xf
+#define BIFPLR5_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                       0x03F0L
+#define BIFPLR5_LINK_STATUS__LINK_TRAINING_MASK                                                               0x0800L
+#define BIFPLR5_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                              0x1000L
+#define BIFPLR5_LINK_STATUS__DL_ACTIVE_MASK                                                                   0x2000L
+#define BIFPLR5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                   0x4000L
+#define BIFPLR5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                   0x8000L
+//BIFPLR5_SLOT_CAP
+#define BIFPLR5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                          0x0
+#define BIFPLR5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                       0x1
+#define BIFPLR5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                           0x2
+#define BIFPLR5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                       0x3
+#define BIFPLR5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                        0x4
+#define BIFPLR5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                             0x5
+#define BIFPLR5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                              0x6
+#define BIFPLR5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                         0x7
+#define BIFPLR5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                         0xf
+#define BIFPLR5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                                0x11
+#define BIFPLR5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                               0x12
+#define BIFPLR5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                            0x13
+#define BIFPLR5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                            0x00000001L
+#define BIFPLR5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                         0x00000002L
+#define BIFPLR5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                             0x00000004L
+#define BIFPLR5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                         0x00000008L
+#define BIFPLR5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                          0x00000010L
+#define BIFPLR5_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                               0x00000020L
+#define BIFPLR5_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                                0x00000040L
+#define BIFPLR5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                           0x00007F80L
+#define BIFPLR5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                           0x00018000L
+#define BIFPLR5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                  0x00020000L
+#define BIFPLR5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                                 0x00040000L
+#define BIFPLR5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                              0xFFF80000L
+//BIFPLR5_SLOT_CNTL
+#define BIFPLR5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                      0x0
+#define BIFPLR5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                       0x1
+#define BIFPLR5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                       0x2
+#define BIFPLR5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                  0x3
+#define BIFPLR5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                   0x4
+#define BIFPLR5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                             0x5
+#define BIFPLR5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                         0x6
+#define BIFPLR5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                          0x8
+#define BIFPLR5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                         0xa
+#define BIFPLR5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                  0xb
+#define BIFPLR5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                         0xc
+#define BIFPLR5_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                                 0xd
+#define BIFPLR5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                        0x0001L
+#define BIFPLR5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                         0x0002L
+#define BIFPLR5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                         0x0004L
+#define BIFPLR5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                    0x0008L
+#define BIFPLR5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                     0x0010L
+#define BIFPLR5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                               0x0020L
+#define BIFPLR5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                           0x00C0L
+#define BIFPLR5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                            0x0300L
+#define BIFPLR5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                           0x0400L
+#define BIFPLR5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                    0x0800L
+#define BIFPLR5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                           0x1000L
+#define BIFPLR5_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                   0x2000L
+//BIFPLR5_SLOT_STATUS
+#define BIFPLR5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                       0x0
+#define BIFPLR5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                        0x1
+#define BIFPLR5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                        0x2
+#define BIFPLR5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                   0x3
+#define BIFPLR5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                         0x4
+#define BIFPLR5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                          0x5
+#define BIFPLR5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                     0x6
+#define BIFPLR5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                              0x7
+#define BIFPLR5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                          0x8
+#define BIFPLR5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                         0x0001L
+#define BIFPLR5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                          0x0002L
+#define BIFPLR5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                          0x0004L
+#define BIFPLR5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                     0x0008L
+#define BIFPLR5_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                           0x0010L
+#define BIFPLR5_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                            0x0020L
+#define BIFPLR5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                       0x0040L
+#define BIFPLR5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                                0x0080L
+#define BIFPLR5_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                            0x0100L
+//BIFPLR5_ROOT_CNTL
+#define BIFPLR5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                         0x0
+#define BIFPLR5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                     0x1
+#define BIFPLR5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                        0x2
+#define BIFPLR5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                             0x3
+#define BIFPLR5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                  0x4
+#define BIFPLR5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                           0x0001L
+#define BIFPLR5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                       0x0002L
+#define BIFPLR5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                          0x0004L
+#define BIFPLR5_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                               0x0008L
+#define BIFPLR5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                    0x0010L
+//BIFPLR5_ROOT_CAP
+#define BIFPLR5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                      0x0
+#define BIFPLR5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                        0x0001L
+//BIFPLR5_ROOT_STATUS
+#define BIFPLR5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                          0x0
+#define BIFPLR5_ROOT_STATUS__PME_STATUS__SHIFT                                                                0x10
+#define BIFPLR5_ROOT_STATUS__PME_PENDING__SHIFT                                                               0x11
+#define BIFPLR5_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR5_ROOT_STATUS__PME_STATUS_MASK                                                                  0x00010000L
+#define BIFPLR5_ROOT_STATUS__PME_PENDING_MASK                                                                 0x00020000L
+//BIFPLR5_DEVICE_CAP2
+#define BIFPLR5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                               0x0
+#define BIFPLR5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                                 0x4
+#define BIFPLR5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                  0x5
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                                0x6
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                                0x7
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                                0x8
+#define BIFPLR5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                    0x9
+#define BIFPLR5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                                 0xa
+#define BIFPLR5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                             0xb
+#define BIFPLR5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                        0xc
+#define BIFPLR5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                             0xe
+#define BIFPLR5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                           0x10
+#define BIFPLR5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                           0x11
+#define BIFPLR5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                            0x12
+#define BIFPLR5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                              0x14
+#define BIFPLR5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                              0x15
+#define BIFPLR5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                  0x16
+#define BIFPLR5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                            0x18
+#define BIFPLR5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                             0x1a
+#define BIFPLR5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                                 0x0000000FL
+#define BIFPLR5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                   0x00000010L
+#define BIFPLR5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                    0x00000020L
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                  0x00000040L
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                  0x00000080L
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                  0x00000100L
+#define BIFPLR5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                      0x00000200L
+#define BIFPLR5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                   0x00000400L
+#define BIFPLR5_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                               0x00000800L
+#define BIFPLR5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                          0x00003000L
+#define BIFPLR5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                               0x0000C000L
+#define BIFPLR5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                             0x00010000L
+#define BIFPLR5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                             0x00020000L
+#define BIFPLR5_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                              0x000C0000L
+#define BIFPLR5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                                0x00100000L
+#define BIFPLR5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                                0x00200000L
+#define BIFPLR5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                    0x00C00000L
+#define BIFPLR5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                              0x03000000L
+#define BIFPLR5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                               0x04000000L
+#define BIFPLR5_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR5_DEVICE_CNTL2
+#define BIFPLR5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                        0x0
+#define BIFPLR5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                          0x4
+#define BIFPLR5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                        0x5
+#define BIFPLR5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                      0x6
+#define BIFPLR5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                                 0x7
+#define BIFPLR5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                       0x8
+#define BIFPLR5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                    0x9
+#define BIFPLR5_DEVICE_CNTL2__LTR_EN__SHIFT                                                                   0xa
+#define BIFPLR5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                             0xb
+#define BIFPLR5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                             0xc
+#define BIFPLR5_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                  0xd
+#define BIFPLR5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                              0xf
+#define BIFPLR5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                          0x000FL
+#define BIFPLR5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                            0x0010L
+#define BIFPLR5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                          0x0020L
+#define BIFPLR5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                        0x0040L
+#define BIFPLR5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                   0x0080L
+#define BIFPLR5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                         0x0100L
+#define BIFPLR5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                      0x0200L
+#define BIFPLR5_DEVICE_CNTL2__LTR_EN_MASK                                                                     0x0400L
+#define BIFPLR5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                               0x0800L
+#define BIFPLR5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                               0x1000L
+#define BIFPLR5_DEVICE_CNTL2__OBFF_EN_MASK                                                                    0x6000L
+#define BIFPLR5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                                0x8000L
+//BIFPLR5_DEVICE_STATUS2
+#define BIFPLR5_DEVICE_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR5_DEVICE_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR5_LINK_CAP2
+#define BIFPLR5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                        0x1
+#define BIFPLR5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                         0x8
+#define BIFPLR5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                    0x10
+#define BIFPLR5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                   0x17
+#define BIFPLR5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                   0x18
+#define BIFPLR5_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                               0x1f
+#define BIFPLR5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                          0x000000FEL
+#define BIFPLR5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                           0x00000100L
+#define BIFPLR5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                      0x007F0000L
+#define BIFPLR5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                     0x00800000L
+#define BIFPLR5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                     0x01000000L
+#define BIFPLR5_LINK_CAP2__DRS_SUPPORTED_MASK                                                                 0x80000000L
+//BIFPLR5_LINK_CNTL2
+#define BIFPLR5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                          0x0
+#define BIFPLR5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                           0x4
+#define BIFPLR5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                                0x5
+#define BIFPLR5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                      0x6
+#define BIFPLR5_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                                0x7
+#define BIFPLR5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                       0xa
+#define BIFPLR5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                             0xb
+#define BIFPLR5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                      0xc
+#define BIFPLR5_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                            0x000FL
+#define BIFPLR5_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                             0x0010L
+#define BIFPLR5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                  0x0020L
+#define BIFPLR5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                        0x0040L
+#define BIFPLR5_LINK_CNTL2__XMIT_MARGIN_MASK                                                                  0x0380L
+#define BIFPLR5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                         0x0400L
+#define BIFPLR5_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                               0x0800L
+#define BIFPLR5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                        0xF000L
+//BIFPLR5_LINK_STATUS2
+#define BIFPLR5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                     0x0
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                                0x1
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                          0x2
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                          0x3
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                          0x4
+#define BIFPLR5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                            0x5
+#define BIFPLR5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                        0x6
+#define BIFPLR5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                        0x7
+#define BIFPLR5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                     0x8
+#define BIFPLR5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                            0xc
+#define BIFPLR5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                     0xf
+#define BIFPLR5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                       0x0001L
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                  0x0002L
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                            0x0004L
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                            0x0008L
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                            0x0010L
+#define BIFPLR5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                              0x0020L
+#define BIFPLR5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                          0x0040L
+#define BIFPLR5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                          0x0080L
+#define BIFPLR5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                       0x0300L
+#define BIFPLR5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                              0x7000L
+#define BIFPLR5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                       0x8000L
+//BIFPLR5_SLOT_CAP2
+#define BIFPLR5_SLOT_CAP2__RESERVED__SHIFT                                                                    0x0
+#define BIFPLR5_SLOT_CAP2__RESERVED_MASK                                                                      0xFFFFFFFFL
+//BIFPLR5_SLOT_CNTL2
+#define BIFPLR5_SLOT_CNTL2__RESERVED__SHIFT                                                                   0x0
+#define BIFPLR5_SLOT_CNTL2__RESERVED_MASK                                                                     0xFFFFL
+//BIFPLR5_SLOT_STATUS2
+#define BIFPLR5_SLOT_STATUS2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR5_SLOT_STATUS2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR5_MSI_CAP_LIST
+#define BIFPLR5_MSI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR5_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR5_MSI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR5_MSI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR5_MSI_MSG_CNTL
+#define BIFPLR5_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                   0x0
+#define BIFPLR5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                            0x1
+#define BIFPLR5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                             0x4
+#define BIFPLR5_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                                0x7
+#define BIFPLR5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                                0x8
+#define BIFPLR5_MSI_MSG_CNTL__MSI_EN_MASK                                                                     0x0001L
+#define BIFPLR5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                              0x000EL
+#define BIFPLR5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                               0x0070L
+#define BIFPLR5_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                  0x0080L
+#define BIFPLR5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                  0x0100L
+//BIFPLR5_MSI_MSG_ADDR_LO
+#define BIFPLR5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                       0x2
+#define BIFPLR5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                         0xFFFFFFFCL
+//BIFPLR5_MSI_MSG_ADDR_HI
+#define BIFPLR5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                       0x0
+#define BIFPLR5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                         0xFFFFFFFFL
+//BIFPLR5_MSI_MSG_DATA
+#define BIFPLR5_MSI_MSG_DATA__MSI_DATA__SHIFT                                                                 0x0
+#define BIFPLR5_MSI_MSG_DATA__MSI_DATA_MASK                                                                   0xFFFFL
+//BIFPLR5_MSI_MSG_DATA_64
+#define BIFPLR5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                           0x0
+#define BIFPLR5_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                             0xFFFFL
+//BIFPLR5_SSID_CAP_LIST
+#define BIFPLR5_SSID_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR5_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR5_SSID_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR5_SSID_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR5_SSID_CAP
+#define BIFPLR5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                          0x0
+#define BIFPLR5_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                                 0x10
+#define BIFPLR5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR5_SSID_CAP__SUBSYSTEM_ID_MASK                                                                   0xFFFF0000L
+//BIFPLR5_MSI_MAP_CAP_LIST
+#define BIFPLR5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                               0x0
+#define BIFPLR5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                             0x8
+#define BIFPLR5_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                                 0x00FFL
+#define BIFPLR5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                               0xFF00L
+//BIFPLR5_MSI_MAP_CAP
+#define BIFPLR5_MSI_MAP_CAP__EN__SHIFT                                                                        0x0
+#define BIFPLR5_MSI_MAP_CAP__FIXD__SHIFT                                                                      0x1
+#define BIFPLR5_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                  0xb
+#define BIFPLR5_MSI_MAP_CAP__EN_MASK                                                                          0x0001L
+#define BIFPLR5_MSI_MAP_CAP__FIXD_MASK                                                                        0x0002L
+#define BIFPLR5_MSI_MAP_CAP__CAP_TYPE_MASK                                                                    0xF800L
+//BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                      0x0
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                     0x10
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                  0x14
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                       0x000F0000L
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                    0xFFF00000L
+//BIFPLR5_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR5_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR5_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR5_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                       0x4
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                         0x8
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                       0xa
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                      0x00000007L
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                         0x00000070L
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                           0x00000300L
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                         0x00000C00L
+//BIFPLR5_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                      0x0
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                             0x18
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                        0x000000FFL
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                               0xFF000000L
+//BIFPLR5_PCIE_PORT_VC_CNTL
+#define BIFPLR5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                   0x0
+#define BIFPLR5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                       0x1
+#define BIFPLR5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                     0x0001L
+#define BIFPLR5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                         0x000EL
+//BIFPLR5_PCIE_PORT_VC_STATUS
+#define BIFPLR5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                               0x0
+#define BIFPLR5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                                 0x0001L
+//BIFPLR5_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR5_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR5_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR5_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR5_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR5_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIFPLR5_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                              0x0
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                                0xFFFFFFFFL
+//BIFPLR5_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                              0x0
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                                0xFFFFFFFFL
+//BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR5_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                                 0x4
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                              0x5
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                                 0xc
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                  0xd
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                             0xe
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                           0xf
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                               0x10
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                                0x11
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                                 0x12
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                                0x13
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                          0x14
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                           0x15
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                          0x16
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                          0x17
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                                 0x18
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                  0x19
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                             0x1a
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                   0x00000010L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                                0x00000020L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                   0x00001000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                    0x00002000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                               0x00004000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                             0x00008000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                                 0x00010000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                  0x00020000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                   0x00040000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                  0x00080000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                            0x00100000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                             0x00200000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                            0x00400000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                            0x00800000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                   0x01000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                    0x02000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                               0x04000000L
+//BIFPLR5_PCIE_UNCORR_ERR_MASK
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                     0x4
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                  0x5
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                     0xc
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                      0xd
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                                 0xe
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                               0xf
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                   0x10
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                    0x11
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                     0x12
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                    0x13
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                              0x14
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                               0x15
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                              0x16
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                              0x17
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                     0x18
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                      0x19
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                                 0x1a
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                       0x00000010L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                    0x00000020L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                       0x00001000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                        0x00002000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                   0x00004000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                                 0x00008000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                     0x00010000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                      0x00020000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                       0x00040000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                      0x00080000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                                0x00100000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                                 0x00200000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                                0x00400000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                                0x00800000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                       0x01000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                        0x02000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                   0x04000000L
+//BIFPLR5_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                             0x4
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                          0x5
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                             0xc
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                              0xd
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                         0xe
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                       0xf
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                           0x10
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                            0x11
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                             0x12
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                            0x13
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                      0x14
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                       0x15
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                      0x16
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                      0x17
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                             0x18
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                              0x19
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                         0x1a
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                               0x00000010L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                            0x00000020L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                               0x00001000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                                0x00002000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                           0x00004000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                         0x00008000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                             0x00010000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                              0x00020000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                               0x00040000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                              0x00080000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                        0x00100000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                         0x00200000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                        0x00400000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                        0x00800000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                               0x01000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                                0x02000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                           0x04000000L
+//BIFPLR5_PCIE_CORR_ERR_STATUS
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                   0x0
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                   0x6
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                  0x7
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                       0x8
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                      0xc
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                     0xd
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                              0xe
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                              0xf
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                     0x00000001L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                     0x00000040L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                    0x00000080L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                         0x00000100L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                        0x00001000L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                       0x00002000L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                                0x00004000L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                                0x00008000L
+//BIFPLR5_PCIE_CORR_ERR_MASK
+#define BIFPLR5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                       0x0
+#define BIFPLR5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                       0x6
+#define BIFPLR5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                      0x7
+#define BIFPLR5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                           0x8
+#define BIFPLR5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                          0xc
+#define BIFPLR5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                         0xd
+#define BIFPLR5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                  0xe
+#define BIFPLR5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                  0xf
+#define BIFPLR5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                         0x00000001L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                         0x00000040L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                        0x00000080L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                             0x00000100L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                            0x00001000L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                           0x00002000L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                    0x00004000L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                    0x00008000L
+//BIFPLR5_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                   0x0
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                  0x7
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                   0x8
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                              0x9
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                               0xa
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                          0xb
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                  0xc
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                     0x0000001FL
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                    0x00000080L
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                     0x00000100L
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                                0x00000200L
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                                 0x00000400L
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                            0x00000800L
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                    0x00001000L
+//BIFPLR5_PCIE_HDR_LOG0
+#define BIFPLR5_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR5_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR5_PCIE_HDR_LOG1
+#define BIFPLR5_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR5_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR5_PCIE_HDR_LOG2
+#define BIFPLR5_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR5_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR5_PCIE_HDR_LOG3
+#define BIFPLR5_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR5_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR5_PCIE_ROOT_ERR_CMD
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                     0x0
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                                 0x1
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                    0x2
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                       0x00000001L
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                   0x00000002L
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                      0x00000004L
+//BIFPLR5_PCIE_ROOT_ERR_STATUS
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                               0x1
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                          0x2
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                     0x3
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                        0x4
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                          0x5
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                             0x6
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                              0x1b
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                      0x00000001L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                                 0x00000002L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                            0x00000004L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                       0x00000008L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                          0x00000010L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                            0x00000020L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                               0x00000040L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                                0xF8000000L
+//BIFPLR5_PCIE_ERR_SRC_ID
+#define BIFPLR5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                       0x0
+#define BIFPLR5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                             0x10
+#define BIFPLR5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                               0xFFFF0000L
+//BIFPLR5_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR5_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR5_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR5_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR5_PCIE_LINK_CNTL3
+#define BIFPLR5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                  0x0
+#define BIFPLR5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                          0x1
+#define BIFPLR5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                    0x00000001L
+#define BIFPLR5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                            0x00000002L
+//BIFPLR5_PCIE_LANE_ERROR_STATUS
+#define BIFPLR5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                         0x0
+#define BIFPLR5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                           0x0000FFFFL
+//BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR5_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR5_PCIE_ACS_CAP
+#define BIFPLR5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                        0x0
+#define BIFPLR5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                     0x1
+#define BIFPLR5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                     0x2
+#define BIFPLR5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                  0x3
+#define BIFPLR5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                      0x4
+#define BIFPLR5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                       0x5
+#define BIFPLR5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                    0x6
+#define BIFPLR5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                               0x8
+#define BIFPLR5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                          0x0001L
+#define BIFPLR5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                       0x0002L
+#define BIFPLR5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                       0x0004L
+#define BIFPLR5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                    0x0008L
+#define BIFPLR5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                        0x0010L
+#define BIFPLR5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                         0x0020L
+#define BIFPLR5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                      0x0040L
+#define BIFPLR5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                                 0xFF00L
+//BIFPLR5_PCIE_ACS_CNTL
+#define BIFPLR5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                                 0x1
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                                 0x2
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                              0x3
+#define BIFPLR5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                  0x4
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                   0x5
+#define BIFPLR5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                                0x6
+#define BIFPLR5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                      0x0001L
+#define BIFPLR5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                   0x0002L
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                   0x0004L
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                                0x0008L
+#define BIFPLR5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                    0x0010L
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                     0x0020L
+#define BIFPLR5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                  0x0040L
+//BIFPLR5_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR5_PCIE_MC_CAP
+#define BIFPLR5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                              0x0
+#define BIFPLR5_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                           0x8
+#define BIFPLR5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                        0xf
+#define BIFPLR5_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                                0x003FL
+#define BIFPLR5_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                             0x3F00L
+#define BIFPLR5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                          0x8000L
+//BIFPLR5_PCIE_MC_CNTL
+#define BIFPLR5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                             0x0
+#define BIFPLR5_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                                0xf
+#define BIFPLR5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                               0x003FL
+#define BIFPLR5_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                  0x8000L
+//BIFPLR5_PCIE_MC_ADDR0
+#define BIFPLR5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                            0x0
+#define BIFPLR5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                          0xc
+#define BIFPLR5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                              0x0000003FL
+#define BIFPLR5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                            0xFFFFF000L
+//BIFPLR5_PCIE_MC_ADDR1
+#define BIFPLR5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                          0x0
+#define BIFPLR5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                            0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_RCV0
+#define BIFPLR5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                             0x0
+#define BIFPLR5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                               0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_RCV1
+#define BIFPLR5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                             0x0
+#define BIFPLR5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                               0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_BLOCK_ALL0
+#define BIFPLR5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                     0x0
+#define BIFPLR5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_BLOCK_ALL1
+#define BIFPLR5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                     0x0
+#define BIFPLR5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                  0x0
+#define BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                    0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                  0x0
+#define BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                    0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                  0x0
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                                 0x6
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                    0x0000003FL
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                   0xFFFFFFC0L
+//BIFPLR5_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                                 0x0
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                   0xFFFFFFFFL
+//BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR5_PCIE_L1_PM_SUB_CAP
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                              0x0
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                              0x1
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                                0x2
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                                0x3
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                                0x4
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                               0x8
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                              0x10
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                              0x13
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                                0x00000001L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                                0x00000002L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                  0x00000004L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                  0x00000008L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                  0x00000010L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                                 0x0000FF00L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                                0x00030000L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                                0x00F80000L
+//BIFPLR5_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                    0x1
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                      0x2
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                      0x3
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                          0x8
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                          0x1d
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                      0x00000001L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                      0x00000002L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                        0x00000004L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                        0x00000008L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                            0x0000FF00L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                            0xE0000000L
+//BIFPLR5_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                                 0x0
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                                 0x3
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                   0x00000003L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                   0x000000F8L
+//BIFPLR5_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR5_PCIE_DPC_CAP_LIST
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                               0x5
+#define BIFPLR5_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                              0x6
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                   0x7
+#define BIFPLR5_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                     0x8
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                               0xc
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                      0x001FL
+#define BIFPLR5_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                                 0x0020L
+#define BIFPLR5_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                                0x0040L
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                     0x0080L
+#define BIFPLR5_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                       0x0F00L
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                                 0x1000L
+//BIFPLR5_PCIE_DPC_CNTL
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                      0x0
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                  0x2
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                    0x3
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                      0x4
+#define BIFPLR5_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                     0x5
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                    0x6
+#define BIFPLR5_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                                0x7
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                        0x0003L
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                    0x0004L
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                      0x0008L
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                        0x0010L
+#define BIFPLR5_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                       0x0020L
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                      0x0040L
+#define BIFPLR5_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                  0x0080L
+//BIFPLR5_PCIE_DPC_STATUS
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                    0x1
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                  0x3
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                           0x4
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                          0x5
+#define BIFPLR5_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                            0x8
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                      0x0001L
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                      0x0006L
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                    0x0008L
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                             0x0010L
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                            0x0060L
+#define BIFPLR5_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                              0x1F00L
+//BIFPLR5_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR5_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                          0x0
+#define BIFPLR5_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                            0xFFFFL
+//BIFPLR5_PCIE_RP_PIO_STATUS
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR5_PCIE_RP_PIO_MASK
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                           0x0
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                           0x1
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                              0x2
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                            0x8
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                            0x9
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                               0xa
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                           0x10
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                           0x11
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                              0x12
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                             0x00000001L
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                             0x00000002L
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                                0x00000004L
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                              0x00000100L
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                              0x00000200L
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                                 0x00000400L
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                             0x00010000L
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                             0x00020000L
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                                0x00040000L
+//BIFPLR5_PCIE_RP_PIO_SEVERITY
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR5_PCIE_RP_PIO_SYSERROR
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR5_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                      0x0
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                      0x1
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                         0x2
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                       0x8
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                       0x9
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                          0xa
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                      0x10
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                      0x11
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                         0x12
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                        0x00000001L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                        0x00000002L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                           0x00000004L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                         0x00000100L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                         0x00000200L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                            0x00000400L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                        0x00010000L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                        0x00020000L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                           0x00040000L
+//BIFPLR5_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR5_PCIE_ESM_CAP_LIST
+#define BIFPLR5_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR5_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                             0x10
+#define BIFPLR5_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                            0x14
+#define BIFPLR5_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                                0x0000FFFFL
+#define BIFPLR5_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                               0x000F0000L
+#define BIFPLR5_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                              0xFFF00000L
+//BIFPLR5_PCIE_ESM_HEADER_1
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                       0x0
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                         0x10
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                         0x14
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                           0x000F0000L
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                           0xFFF00000L
+//BIFPLR5_PCIE_ESM_HEADER_2
+#define BIFPLR5_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR5_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                                0xFFFFL
+//BIFPLR5_PCIE_ESM_STATUS
+#define BIFPLR5_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                  0x9
+#define BIFPLR5_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                      0x01FFL
+#define BIFPLR5_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                    0x0E00L
+//BIFPLR5_PCIE_ESM_CTRL
+#define BIFPLR5_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                             0xf
+#define BIFPLR5_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                               0x8000L
+//BIFPLR5_PCIE_ESM_CAP_1
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                               0x0
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                               0x1
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                               0x2
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                               0x3
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                               0x4
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                               0x5
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                               0x6
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                               0x7
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                               0x8
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                               0x9
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                               0xa
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                               0xb
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                               0xc
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                               0xd
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                               0xe
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                               0xf
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                               0x10
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                               0x11
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                               0x12
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                               0x13
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                              0x14
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                              0x15
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                              0x16
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                              0x17
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                              0x18
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                              0x19
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                              0x1a
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                              0x1b
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                              0x1c
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                              0x1d
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                                 0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                                 0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                                 0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                                 0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                                 0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                                 0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                                 0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                                 0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                                 0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                                 0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                                 0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                                 0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                                 0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                                 0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                                 0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                                 0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                                 0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                                 0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                                 0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                                 0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                                0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                                0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                                0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                                0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                                0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                                0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                                0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                                0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                                0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                                0x20000000L
+//BIFPLR5_PCIE_ESM_CAP_2
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                              0x0
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                              0x1
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                              0x2
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                              0x3
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                              0x4
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                              0x5
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                              0x6
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                              0x7
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                              0x8
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                              0x9
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                              0xa
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                              0xb
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                              0xc
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                              0xd
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                              0xe
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                              0xf
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                              0x10
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                              0x11
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                              0x12
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                              0x13
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                              0x14
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                              0x15
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                              0x16
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                              0x17
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                              0x18
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                              0x19
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                              0x1a
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                              0x1b
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                              0x1c
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                              0x1d
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                                0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                                0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                                0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                                0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                                0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                                0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                                0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                                0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                                0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                                0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                                0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                                0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                                0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                                0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                                0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                                0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                                0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                                0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                                0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                                0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                                0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                                0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                                0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                                0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                                0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                                0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                                0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                                0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                                0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                                0x20000000L
+//BIFPLR5_PCIE_ESM_CAP_3
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                              0x0
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                              0x1
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                              0x2
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                              0x3
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                              0x4
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                              0x5
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                              0x6
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                              0x7
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                              0x8
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                              0x9
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                              0xa
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                              0xb
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                              0xc
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                              0xd
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                              0xe
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                              0xf
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                              0x10
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                              0x11
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                              0x12
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                              0x13
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                                0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                                0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                                0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                                0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                                0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                                0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                                0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                                0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                                0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                                0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                                0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                                0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                                0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                                0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                                0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                                0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                                0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                                0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                                0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                                0x00080000L
+//BIFPLR5_PCIE_ESM_CAP_4
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                              0x0
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                              0x1
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                              0x2
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                              0x3
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                              0x4
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                              0x5
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                              0x6
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                              0x7
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                              0x8
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                              0x9
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                              0xa
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                              0xb
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                              0xc
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                              0xd
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                              0xe
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                              0xf
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                              0x10
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                              0x11
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                              0x12
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                              0x13
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                              0x14
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                              0x15
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                              0x16
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                              0x17
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                              0x18
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                              0x19
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                              0x1a
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                              0x1b
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                              0x1c
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                              0x1d
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                                0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                                0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                                0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                                0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                                0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                                0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                                0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                                0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                                0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                                0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                                0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                                0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                                0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                                0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                                0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                                0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                                0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                                0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                                0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                                0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                                0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                                0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                                0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                                0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                                0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                                0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                                0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                                0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                                0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                                0x20000000L
+//BIFPLR5_PCIE_ESM_CAP_5
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                              0x0
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                              0x1
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                              0x2
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                              0x3
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                              0x4
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                              0x5
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                              0x6
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                              0x7
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                              0x8
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                              0x9
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                              0xa
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                              0xb
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                              0xc
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                              0xd
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                              0xe
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                              0xf
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                              0x10
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                              0x11
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                              0x12
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                              0x13
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                              0x14
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                              0x15
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                              0x16
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                              0x17
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                              0x18
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                              0x19
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                              0x1a
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                              0x1b
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                              0x1c
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                              0x1d
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                                0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                                0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                                0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                                0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                                0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                                0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                                0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                                0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                                0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                                0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                                0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                                0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                                0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                                0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                                0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                                0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                                0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                                0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                                0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                                0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                                0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                                0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                                0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                                0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                                0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                                0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                                0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                                0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                                0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                                0x20000000L
+//BIFPLR5_PCIE_ESM_CAP_6
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                              0x0
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                              0x1
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                              0x2
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                              0x3
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                              0x4
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                              0x5
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                              0x6
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                              0x7
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                              0x8
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                              0x9
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                              0xa
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                              0xb
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                              0xc
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                              0xd
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                              0xe
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                              0xf
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                              0x10
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                              0x11
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                              0x12
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                              0x13
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                              0x14
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                              0x15
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                              0x16
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                              0x17
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                              0x18
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                              0x19
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                              0x1a
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                              0x1b
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                              0x1c
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                              0x1d
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                                0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                                0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                                0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                                0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                                0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                                0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                                0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                                0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                                0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                                0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                                0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                                0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                                0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                                0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                                0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                                0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                                0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                                0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                                0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                                0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                                0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                                0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                                0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                                0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                                0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                                0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                                0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                                0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                                0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                                0x20000000L
+//BIFPLR5_PCIE_ESM_CAP_7
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                              0x0
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                              0x1
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                              0x2
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                              0x3
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                              0x4
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                              0x5
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                              0x6
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                              0x7
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                              0x8
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                              0x9
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                              0xa
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                              0xb
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                              0xc
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                              0xd
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                              0xe
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                              0xf
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                              0x10
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                              0x11
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                              0x12
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                              0x13
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                              0x14
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                              0x15
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                              0x16
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                              0x17
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                              0x18
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                              0x19
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                              0x1a
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                              0x1b
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                              0x1c
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                              0x1d
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                              0x1e
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                                0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                                0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                                0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                                0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                                0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                                0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                                0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                                0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                                0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                                0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                                0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                                0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                                0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                                0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                                0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                                0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                                0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                                0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                                0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                                0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                                0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                                0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                                0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                                0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                                0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                                0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                                0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                                0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                                0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                                0x20000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                                0x40000000L
+//BIFPLR5_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR5_DATA_LINK_FEATURE_CAP
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                         0x0
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                        0x1
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                             0x1f
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                           0x00000001L
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                          0x007FFFFEL
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                               0x80000000L
+//BIFPLR5_DATA_LINK_FEATURE_STATUS
+#define BIFPLR5_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                         0x0
+#define BIFPLR5_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                   0x1f
+#define BIFPLR5_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                           0x007FFFFFL
+#define BIFPLR5_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                     0x80000000L
+//BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                    0x10
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                   0x14
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                      0x000F0000L
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                     0xFFF00000L
+//BIFPLR5_LINK_CAP_16GT
+#define BIFPLR5_LINK_CAP_16GT__RESERVED__SHIFT                                                                0x0
+#define BIFPLR5_LINK_CAP_16GT__RESERVED_MASK                                                                  0xFFFFFFFFL
+//BIFPLR5_LINK_CNTL_16GT
+#define BIFPLR5_LINK_CNTL_16GT__RESERVED__SHIFT                                                               0x0
+#define BIFPLR5_LINK_CNTL_16GT__RESERVED_MASK                                                                 0xFFFFFFFFL
+//BIFPLR5_LINK_STATUS_16GT
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                           0x0
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                     0x1
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                     0x2
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                     0x3
+#define BIFPLR5_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                       0x4
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                             0x00000001L
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                       0x00000002L
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                       0x00000004L
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                       0x00000008L
+#define BIFPLR5_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                         0x00000010L
+//BIFPLR5_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR5_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR5_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR5_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR5_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR5_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR5_MARGINING_PORT_CAP
+#define BIFPLR5_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                            0x0
+#define BIFPLR5_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                              0x0001L
+//BIFPLR5_MARGINING_PORT_STATUS
+#define BIFPLR5_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                                 0x0
+#define BIFPLR5_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                        0x1
+#define BIFPLR5_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                   0x0001L
+#define BIFPLR5_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                          0x0002L
+//BIFPLR5_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR5_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR5_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR5_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR5_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR5_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR5_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR5_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR5_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR5_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR5_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR5_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR5_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR5_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR5_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR5_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR5_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR5_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR5_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR5_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR5_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_PCIE_CCIX_CAP_LIST
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                            0x10
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                           0x14
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                               0x0000FFFFL
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                              0x000F0000L
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                             0xFFF00000L
+//BIFPLR5_PCIE_CCIX_HEADER_1
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR5_PCIE_CCIX_HEADER_2
+#define BIFPLR5_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR5_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                               0xFFFFL
+//BIFPLR5_PCIE_CCIX_CAP
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                      0x0
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                         0x1
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                        0x3
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                    0x4
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                          0x8
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                        0x0001L
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                           0x0006L
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                          0x0008L
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                      0x0070L
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                            0x0700L
+//BIFPLR5_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                              0x0
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                                0x1
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                                0x2
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                               0x5
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                               0x9
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                               0xe
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                                0x00000001L
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                  0x00000002L
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                  0x00000004L
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                                 0x00000020L
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                                 0x00000200L
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                                 0x00004000L
+//BIFPLR5_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR5_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                       0x0
+#define BIFPLR5_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIFPLR5_PCIE_CCIX_ESM_STATUS
+#define BIFPLR5_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                            0x0
+#define BIFPLR5_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                         0x7
+#define BIFPLR5_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                              0x0000007FL
+#define BIFPLR5_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                           0x00000080L
+//BIFPLR5_PCIE_CCIX_ESM_CNTL
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                     0x0
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                            0x7
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                     0x8
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                         0xf
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                           0x10
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                           0x14
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                  0x18
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                    0x19
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                              0x1a
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                       0x0000007FL
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                              0x00000080L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                       0x00007F00L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                           0x00008000L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                             0x00070000L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                             0x00700000L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                    0x01000000L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                      0x02000000L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                                0x1C000000L
+//BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_PCIE_CCIX_TRANS_CAP
+#define BIFPLR5_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                                 0x0
+#define BIFPLR5_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                   0x00000001L
+//BIFPLR5_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR5_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                                 0x0
+#define BIFPLR5_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                   0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+//BIFPLR6_VENDOR_ID
+#define BIFPLR6_VENDOR_ID__VENDOR_ID__SHIFT                                                                   0x0
+#define BIFPLR6_VENDOR_ID__VENDOR_ID_MASK                                                                     0xFFFFL
+//BIFPLR6_DEVICE_ID
+#define BIFPLR6_DEVICE_ID__DEVICE_ID__SHIFT                                                                   0x0
+#define BIFPLR6_DEVICE_ID__DEVICE_ID_MASK                                                                     0xFFFFL
+//BIFPLR6_COMMAND
+#define BIFPLR6_COMMAND__IO_ACCESS_EN__SHIFT                                                                  0x0
+#define BIFPLR6_COMMAND__MEM_ACCESS_EN__SHIFT                                                                 0x1
+#define BIFPLR6_COMMAND__BUS_MASTER_EN__SHIFT                                                                 0x2
+#define BIFPLR6_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                              0x3
+#define BIFPLR6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                       0x4
+#define BIFPLR6_COMMAND__PAL_SNOOP_EN__SHIFT                                                                  0x5
+#define BIFPLR6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                         0x6
+#define BIFPLR6_COMMAND__AD_STEPPING__SHIFT                                                                   0x7
+#define BIFPLR6_COMMAND__SERR_EN__SHIFT                                                                       0x8
+#define BIFPLR6_COMMAND__FAST_B2B_EN__SHIFT                                                                   0x9
+#define BIFPLR6_COMMAND__INT_DIS__SHIFT                                                                       0xa
+#define BIFPLR6_COMMAND__IO_ACCESS_EN_MASK                                                                    0x0001L
+#define BIFPLR6_COMMAND__MEM_ACCESS_EN_MASK                                                                   0x0002L
+#define BIFPLR6_COMMAND__BUS_MASTER_EN_MASK                                                                   0x0004L
+#define BIFPLR6_COMMAND__SPECIAL_CYCLE_EN_MASK                                                                0x0008L
+#define BIFPLR6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                         0x0010L
+#define BIFPLR6_COMMAND__PAL_SNOOP_EN_MASK                                                                    0x0020L
+#define BIFPLR6_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                           0x0040L
+#define BIFPLR6_COMMAND__AD_STEPPING_MASK                                                                     0x0080L
+#define BIFPLR6_COMMAND__SERR_EN_MASK                                                                         0x0100L
+#define BIFPLR6_COMMAND__FAST_B2B_EN_MASK                                                                     0x0200L
+#define BIFPLR6_COMMAND__INT_DIS_MASK                                                                         0x0400L
+//BIFPLR6_STATUS
+#define BIFPLR6_STATUS__IMMEDIATE_READINESS__SHIFT                                                            0x0
+#define BIFPLR6_STATUS__INT_STATUS__SHIFT                                                                     0x3
+#define BIFPLR6_STATUS__CAP_LIST__SHIFT                                                                       0x4
+#define BIFPLR6_STATUS__PCI_66_CAP__SHIFT                                                                     0x5
+#define BIFPLR6_STATUS__FAST_BACK_CAPABLE__SHIFT                                                              0x7
+#define BIFPLR6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                       0x8
+#define BIFPLR6_STATUS__DEVSEL_TIMING__SHIFT                                                                  0x9
+#define BIFPLR6_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                            0xb
+#define BIFPLR6_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                          0xc
+#define BIFPLR6_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                          0xd
+#define BIFPLR6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                          0xe
+#define BIFPLR6_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                          0xf
+#define BIFPLR6_STATUS__IMMEDIATE_READINESS_MASK                                                              0x0001L
+#define BIFPLR6_STATUS__INT_STATUS_MASK                                                                       0x0008L
+#define BIFPLR6_STATUS__CAP_LIST_MASK                                                                         0x0010L
+#define BIFPLR6_STATUS__PCI_66_CAP_MASK                                                                       0x0020L
+#define BIFPLR6_STATUS__FAST_BACK_CAPABLE_MASK                                                                0x0080L
+#define BIFPLR6_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                         0x0100L
+#define BIFPLR6_STATUS__DEVSEL_TIMING_MASK                                                                    0x0600L
+#define BIFPLR6_STATUS__SIGNAL_TARGET_ABORT_MASK                                                              0x0800L
+#define BIFPLR6_STATUS__RECEIVED_TARGET_ABORT_MASK                                                            0x1000L
+#define BIFPLR6_STATUS__RECEIVED_MASTER_ABORT_MASK                                                            0x2000L
+#define BIFPLR6_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                            0x4000L
+#define BIFPLR6_STATUS__PARITY_ERROR_DETECTED_MASK                                                            0x8000L
+//BIFPLR6_REVISION_ID
+#define BIFPLR6_REVISION_ID__MINOR_REV_ID__SHIFT                                                              0x0
+#define BIFPLR6_REVISION_ID__MAJOR_REV_ID__SHIFT                                                              0x4
+#define BIFPLR6_REVISION_ID__MINOR_REV_ID_MASK                                                                0x0FL
+#define BIFPLR6_REVISION_ID__MAJOR_REV_ID_MASK                                                                0xF0L
+//BIFPLR6_PROG_INTERFACE
+#define BIFPLR6_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                         0x0
+#define BIFPLR6_PROG_INTERFACE__PROG_INTERFACE_MASK                                                           0xFFL
+//BIFPLR6_SUB_CLASS
+#define BIFPLR6_SUB_CLASS__SUB_CLASS__SHIFT                                                                   0x0
+#define BIFPLR6_SUB_CLASS__SUB_CLASS_MASK                                                                     0xFFL
+//BIFPLR6_BASE_CLASS
+#define BIFPLR6_BASE_CLASS__BASE_CLASS__SHIFT                                                                 0x0
+#define BIFPLR6_BASE_CLASS__BASE_CLASS_MASK                                                                   0xFFL
+//BIFPLR6_CACHE_LINE
+#define BIFPLR6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                            0x0
+#define BIFPLR6_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                              0xFFL
+//BIFPLR6_LATENCY
+#define BIFPLR6_LATENCY__LATENCY_TIMER__SHIFT                                                                 0x0
+#define BIFPLR6_LATENCY__LATENCY_TIMER_MASK                                                                   0xFFL
+//BIFPLR6_HEADER
+#define BIFPLR6_HEADER__HEADER_TYPE__SHIFT                                                                    0x0
+#define BIFPLR6_HEADER__DEVICE_TYPE__SHIFT                                                                    0x7
+#define BIFPLR6_HEADER__HEADER_TYPE_MASK                                                                      0x7FL
+#define BIFPLR6_HEADER__DEVICE_TYPE_MASK                                                                      0x80L
+//BIFPLR6_BIST
+#define BIFPLR6_BIST__BIST_COMP__SHIFT                                                                        0x0
+#define BIFPLR6_BIST__BIST_STRT__SHIFT                                                                        0x6
+#define BIFPLR6_BIST__BIST_CAP__SHIFT                                                                         0x7
+#define BIFPLR6_BIST__BIST_COMP_MASK                                                                          0x0FL
+#define BIFPLR6_BIST__BIST_STRT_MASK                                                                          0x40L
+#define BIFPLR6_BIST__BIST_CAP_MASK                                                                           0x80L
+//BIFPLR6_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                    0x0
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                  0x8
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                    0x10
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                        0x18
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                      0x000000FFL
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                    0x0000FF00L
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                      0x00FF0000L
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                          0xFF000000L
+//BIFPLR6_IO_BASE_LIMIT
+#define BIFPLR6_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                            0x0
+#define BIFPLR6_IO_BASE_LIMIT__IO_BASE__SHIFT                                                                 0x4
+#define BIFPLR6_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                           0x8
+#define BIFPLR6_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                                0xc
+#define BIFPLR6_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                              0x000FL
+#define BIFPLR6_IO_BASE_LIMIT__IO_BASE_MASK                                                                   0x00F0L
+#define BIFPLR6_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                             0x0F00L
+#define BIFPLR6_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                  0xF000L
+//BIFPLR6_SECONDARY_STATUS
+#define BIFPLR6_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIFPLR6_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIFPLR6_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIFPLR6_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIFPLR6_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIFPLR6_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIFPLR6_SECONDARY_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIFPLR6_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIFPLR6_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIFPLR6_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIFPLR6_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIFPLR6_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIFPLR6_MEM_BASE_LIMIT
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                         0x4
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                         0x10
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                        0x14
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                            0x0000000FL
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                           0x0000FFF0L
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                           0x000F0000L
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                          0xFFF00000L
+//BIFPLR6_PREF_BASE_LIMIT
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                    0x0
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                   0x4
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                   0x10
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                  0x14
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                      0x0000000FL
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                     0x0000FFF0L
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                     0x000F0000L
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                    0xFFF00000L
+//BIFPLR6_PREF_BASE_UPPER
+#define BIFPLR6_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                       0x0
+#define BIFPLR6_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                         0xFFFFFFFFL
+//BIFPLR6_PREF_LIMIT_UPPER
+#define BIFPLR6_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                     0x0
+#define BIFPLR6_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_IO_BASE_LIMIT_HI
+#define BIFPLR6_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                        0x0
+#define BIFPLR6_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                       0x10
+#define BIFPLR6_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                          0x0000FFFFL
+#define BIFPLR6_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                         0xFFFF0000L
+//BIFPLR6_CAP_PTR
+#define BIFPLR6_CAP_PTR__CAP_PTR__SHIFT                                                                       0x0
+#define BIFPLR6_CAP_PTR__CAP_PTR_MASK                                                                         0xFFL
+//BIFPLR6_ROM_BASE_ADDR
+#define BIFPLR6_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                               0x0
+#define BIFPLR6_ROM_BASE_ADDR__BASE_ADDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR6_INTERRUPT_LINE
+#define BIFPLR6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                         0x0
+#define BIFPLR6_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                           0xFFL
+//BIFPLR6_INTERRUPT_PIN
+#define BIFPLR6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                           0x0
+#define BIFPLR6_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                             0xFFL
+//BIFPLR6_IRQ_BRIDGE_CNTL
+#define BIFPLR6_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                    0x0
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                               0x1
+#define BIFPLR6_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                                0x2
+#define BIFPLR6_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                                0x3
+#define BIFPLR6_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                               0x4
+#define BIFPLR6_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                     0x5
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                   0x6
+#define BIFPLR6_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                           0x7
+#define BIFPLR6_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                                 0x8
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                               0x9
+#define BIFPLR6_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                  0xa
+#define BIFPLR6_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                             0xb
+#define BIFPLR6_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                      0x0001L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                                 0x0002L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                  0x0004L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                  0x0008L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                                 0x0010L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                       0x0020L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                     0x0040L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                             0x0080L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                   0x0100L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                                 0x0200L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                    0x0400L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                               0x0800L
+//BIFPLR6_EXT_BRIDGE_CNTL
+#define BIFPLR6_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                         0x0
+#define BIFPLR6_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                           0x01L
+//BIFPLR6_VENDOR_CAP_LIST
+#define BIFPLR6_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR6_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR6_VENDOR_CAP_LIST__LENGTH__SHIFT                                                                0x10
+#define BIFPLR6_VENDOR_CAP_LIST__CAP_ID_MASK                                                                  0x000000FFL
+#define BIFPLR6_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                                0x0000FF00L
+#define BIFPLR6_VENDOR_CAP_LIST__LENGTH_MASK                                                                  0x00FF0000L
+//BIFPLR6_ADAPTER_ID_W
+#define BIFPLR6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                      0x0
+#define BIFPLR6_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                             0x10
+#define BIFPLR6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR6_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                               0xFFFF0000L
+//BIFPLR6_PMI_CAP_LIST
+#define BIFPLR6_PMI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR6_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR6_PMI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR6_PMI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR6_PMI_CAP
+#define BIFPLR6_PMI_CAP__VERSION__SHIFT                                                                       0x0
+#define BIFPLR6_PMI_CAP__PME_CLOCK__SHIFT                                                                     0x3
+#define BIFPLR6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                           0x4
+#define BIFPLR6_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                             0x5
+#define BIFPLR6_PMI_CAP__AUX_CURRENT__SHIFT                                                                   0x6
+#define BIFPLR6_PMI_CAP__D1_SUPPORT__SHIFT                                                                    0x9
+#define BIFPLR6_PMI_CAP__D2_SUPPORT__SHIFT                                                                    0xa
+#define BIFPLR6_PMI_CAP__PME_SUPPORT__SHIFT                                                                   0xb
+#define BIFPLR6_PMI_CAP__VERSION_MASK                                                                         0x0007L
+#define BIFPLR6_PMI_CAP__PME_CLOCK_MASK                                                                       0x0008L
+#define BIFPLR6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                             0x0010L
+#define BIFPLR6_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                               0x0020L
+#define BIFPLR6_PMI_CAP__AUX_CURRENT_MASK                                                                     0x01C0L
+#define BIFPLR6_PMI_CAP__D1_SUPPORT_MASK                                                                      0x0200L
+#define BIFPLR6_PMI_CAP__D2_SUPPORT_MASK                                                                      0x0400L
+#define BIFPLR6_PMI_CAP__PME_SUPPORT_MASK                                                                     0xF800L
+//BIFPLR6_PMI_STATUS_CNTL
+#define BIFPLR6_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                           0x0
+#define BIFPLR6_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                         0x3
+#define BIFPLR6_PMI_STATUS_CNTL__PME_EN__SHIFT                                                                0x8
+#define BIFPLR6_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                           0x9
+#define BIFPLR6_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                            0xd
+#define BIFPLR6_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                            0xf
+#define BIFPLR6_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                         0x16
+#define BIFPLR6_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                            0x17
+#define BIFPLR6_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                              0x18
+#define BIFPLR6_PMI_STATUS_CNTL__POWER_STATE_MASK                                                             0x00000003L
+#define BIFPLR6_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                           0x00000008L
+#define BIFPLR6_PMI_STATUS_CNTL__PME_EN_MASK                                                                  0x00000100L
+#define BIFPLR6_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                             0x00001E00L
+#define BIFPLR6_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                              0x00006000L
+#define BIFPLR6_PMI_STATUS_CNTL__PME_STATUS_MASK                                                              0x00008000L
+#define BIFPLR6_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                           0x00400000L
+#define BIFPLR6_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                              0x00800000L
+#define BIFPLR6_PMI_STATUS_CNTL__PMI_DATA_MASK                                                                0xFF000000L
+//BIFPLR6_PCIE_CAP_LIST
+#define BIFPLR6_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR6_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR6_PCIE_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR6_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR6_PCIE_CAP
+#define BIFPLR6_PCIE_CAP__VERSION__SHIFT                                                                      0x0
+#define BIFPLR6_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                  0x4
+#define BIFPLR6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                             0x8
+#define BIFPLR6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                              0x9
+#define BIFPLR6_PCIE_CAP__VERSION_MASK                                                                        0x000FL
+#define BIFPLR6_PCIE_CAP__DEVICE_TYPE_MASK                                                                    0x00F0L
+#define BIFPLR6_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                               0x0100L
+#define BIFPLR6_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                                0x3E00L
+//BIFPLR6_DEVICE_CAP
+#define BIFPLR6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                        0x0
+#define BIFPLR6_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                               0x3
+#define BIFPLR6_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                               0x5
+#define BIFPLR6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                     0x6
+#define BIFPLR6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                      0x9
+#define BIFPLR6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                   0xf
+#define BIFPLR6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                  0x12
+#define BIFPLR6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                  0x1a
+#define BIFPLR6_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                                0x1c
+#define BIFPLR6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                          0x00000007L
+#define BIFPLR6_DEVICE_CAP__PHANTOM_FUNC_MASK                                                                 0x00000018L
+#define BIFPLR6_DEVICE_CAP__EXTENDED_TAG_MASK                                                                 0x00000020L
+#define BIFPLR6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                       0x000001C0L
+#define BIFPLR6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                        0x00000E00L
+#define BIFPLR6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                     0x00008000L
+#define BIFPLR6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                    0x03FC0000L
+#define BIFPLR6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                    0x0C000000L
+#define BIFPLR6_DEVICE_CAP__FLR_CAPABLE_MASK                                                                  0x10000000L
+//BIFPLR6_DEVICE_CNTL
+#define BIFPLR6_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                               0x0
+#define BIFPLR6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                          0x1
+#define BIFPLR6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                              0x2
+#define BIFPLR6_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                             0x3
+#define BIFPLR6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                            0x4
+#define BIFPLR6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                          0x5
+#define BIFPLR6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                           0x8
+#define BIFPLR6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                           0x9
+#define BIFPLR6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                           0xa
+#define BIFPLR6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                               0xb
+#define BIFPLR6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                     0xc
+#define BIFPLR6_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                       0xf
+#define BIFPLR6_DEVICE_CNTL__CORR_ERR_EN_MASK                                                                 0x0001L
+#define BIFPLR6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                            0x0002L
+#define BIFPLR6_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                                0x0004L
+#define BIFPLR6_DEVICE_CNTL__USR_REPORT_EN_MASK                                                               0x0008L
+#define BIFPLR6_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                              0x0010L
+#define BIFPLR6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                            0x00E0L
+#define BIFPLR6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                             0x0100L
+#define BIFPLR6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                             0x0200L
+#define BIFPLR6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                             0x0400L
+#define BIFPLR6_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                                 0x0800L
+#define BIFPLR6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                       0x7000L
+#define BIFPLR6_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                         0x8000L
+//BIFPLR6_DEVICE_STATUS
+#define BIFPLR6_DEVICE_STATUS__CORR_ERR__SHIFT                                                                0x0
+#define BIFPLR6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                           0x1
+#define BIFPLR6_DEVICE_STATUS__FATAL_ERR__SHIFT                                                               0x2
+#define BIFPLR6_DEVICE_STATUS__USR_DETECTED__SHIFT                                                            0x3
+#define BIFPLR6_DEVICE_STATUS__AUX_PWR__SHIFT                                                                 0x4
+#define BIFPLR6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                       0x5
+#define BIFPLR6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                           0x6
+#define BIFPLR6_DEVICE_STATUS__CORR_ERR_MASK                                                                  0x0001L
+#define BIFPLR6_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                             0x0002L
+#define BIFPLR6_DEVICE_STATUS__FATAL_ERR_MASK                                                                 0x0004L
+#define BIFPLR6_DEVICE_STATUS__USR_DETECTED_MASK                                                              0x0008L
+#define BIFPLR6_DEVICE_STATUS__AUX_PWR_MASK                                                                   0x0010L
+#define BIFPLR6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                         0x0020L
+#define BIFPLR6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                             0x0040L
+//BIFPLR6_LINK_CAP
+#define BIFPLR6_LINK_CAP__LINK_SPEED__SHIFT                                                                   0x0
+#define BIFPLR6_LINK_CAP__LINK_WIDTH__SHIFT                                                                   0x4
+#define BIFPLR6_LINK_CAP__PM_SUPPORT__SHIFT                                                                   0xa
+#define BIFPLR6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                             0xc
+#define BIFPLR6_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                              0xf
+#define BIFPLR6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                       0x12
+#define BIFPLR6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                  0x13
+#define BIFPLR6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                  0x14
+#define BIFPLR6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                     0x15
+#define BIFPLR6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                  0x16
+#define BIFPLR6_LINK_CAP__PORT_NUMBER__SHIFT                                                                  0x18
+#define BIFPLR6_LINK_CAP__LINK_SPEED_MASK                                                                     0x0000000FL
+#define BIFPLR6_LINK_CAP__LINK_WIDTH_MASK                                                                     0x000003F0L
+#define BIFPLR6_LINK_CAP__PM_SUPPORT_MASK                                                                     0x00000C00L
+#define BIFPLR6_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                               0x00007000L
+#define BIFPLR6_LINK_CAP__L1_EXIT_LATENCY_MASK                                                                0x00038000L
+#define BIFPLR6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                         0x00040000L
+#define BIFPLR6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                    0x00080000L
+#define BIFPLR6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                    0x00100000L
+#define BIFPLR6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                       0x00200000L
+#define BIFPLR6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                    0x00400000L
+#define BIFPLR6_LINK_CAP__PORT_NUMBER_MASK                                                                    0xFF000000L
+//BIFPLR6_LINK_CNTL
+#define BIFPLR6_LINK_CNTL__PM_CONTROL__SHIFT                                                                  0x0
+#define BIFPLR6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                           0x3
+#define BIFPLR6_LINK_CNTL__LINK_DIS__SHIFT                                                                    0x4
+#define BIFPLR6_LINK_CNTL__RETRAIN_LINK__SHIFT                                                                0x5
+#define BIFPLR6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                            0x6
+#define BIFPLR6_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                               0x7
+#define BIFPLR6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                   0x8
+#define BIFPLR6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                                 0x9
+#define BIFPLR6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                   0xa
+#define BIFPLR6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                   0xb
+#define BIFPLR6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                       0xe
+#define BIFPLR6_LINK_CNTL__PM_CONTROL_MASK                                                                    0x0003L
+#define BIFPLR6_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                             0x0008L
+#define BIFPLR6_LINK_CNTL__LINK_DIS_MASK                                                                      0x0010L
+#define BIFPLR6_LINK_CNTL__RETRAIN_LINK_MASK                                                                  0x0020L
+#define BIFPLR6_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                              0x0040L
+#define BIFPLR6_LINK_CNTL__EXTENDED_SYNC_MASK                                                                 0x0080L
+#define BIFPLR6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                     0x0100L
+#define BIFPLR6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                   0x0200L
+#define BIFPLR6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                     0x0400L
+#define BIFPLR6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                     0x0800L
+#define BIFPLR6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                         0xC000L
+//BIFPLR6_LINK_STATUS
+#define BIFPLR6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                     0x4
+#define BIFPLR6_LINK_STATUS__LINK_TRAINING__SHIFT                                                             0xb
+#define BIFPLR6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                            0xc
+#define BIFPLR6_LINK_STATUS__DL_ACTIVE__SHIFT                                                                 0xd
+#define BIFPLR6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                                 0xe
+#define BIFPLR6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                                 0xf
+#define BIFPLR6_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                       0x03F0L
+#define BIFPLR6_LINK_STATUS__LINK_TRAINING_MASK                                                               0x0800L
+#define BIFPLR6_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                              0x1000L
+#define BIFPLR6_LINK_STATUS__DL_ACTIVE_MASK                                                                   0x2000L
+#define BIFPLR6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                   0x4000L
+#define BIFPLR6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                   0x8000L
+//BIFPLR6_SLOT_CAP
+#define BIFPLR6_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                          0x0
+#define BIFPLR6_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                       0x1
+#define BIFPLR6_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                           0x2
+#define BIFPLR6_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                       0x3
+#define BIFPLR6_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                        0x4
+#define BIFPLR6_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                             0x5
+#define BIFPLR6_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                              0x6
+#define BIFPLR6_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                         0x7
+#define BIFPLR6_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                         0xf
+#define BIFPLR6_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                                0x11
+#define BIFPLR6_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                               0x12
+#define BIFPLR6_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                            0x13
+#define BIFPLR6_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                            0x00000001L
+#define BIFPLR6_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                         0x00000002L
+#define BIFPLR6_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                             0x00000004L
+#define BIFPLR6_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                         0x00000008L
+#define BIFPLR6_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                          0x00000010L
+#define BIFPLR6_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                               0x00000020L
+#define BIFPLR6_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                                0x00000040L
+#define BIFPLR6_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                           0x00007F80L
+#define BIFPLR6_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                           0x00018000L
+#define BIFPLR6_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                  0x00020000L
+#define BIFPLR6_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                                 0x00040000L
+#define BIFPLR6_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                              0xFFF80000L
+//BIFPLR6_SLOT_CNTL
+#define BIFPLR6_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                      0x0
+#define BIFPLR6_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                       0x1
+#define BIFPLR6_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                       0x2
+#define BIFPLR6_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                  0x3
+#define BIFPLR6_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                   0x4
+#define BIFPLR6_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                             0x5
+#define BIFPLR6_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                         0x6
+#define BIFPLR6_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                          0x8
+#define BIFPLR6_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                         0xa
+#define BIFPLR6_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                  0xb
+#define BIFPLR6_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                         0xc
+#define BIFPLR6_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                                 0xd
+#define BIFPLR6_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                        0x0001L
+#define BIFPLR6_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                         0x0002L
+#define BIFPLR6_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                         0x0004L
+#define BIFPLR6_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                    0x0008L
+#define BIFPLR6_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                     0x0010L
+#define BIFPLR6_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                               0x0020L
+#define BIFPLR6_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                           0x00C0L
+#define BIFPLR6_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                            0x0300L
+#define BIFPLR6_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                           0x0400L
+#define BIFPLR6_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                    0x0800L
+#define BIFPLR6_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                           0x1000L
+#define BIFPLR6_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                   0x2000L
+//BIFPLR6_SLOT_STATUS
+#define BIFPLR6_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                       0x0
+#define BIFPLR6_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                        0x1
+#define BIFPLR6_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                        0x2
+#define BIFPLR6_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                   0x3
+#define BIFPLR6_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                         0x4
+#define BIFPLR6_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                          0x5
+#define BIFPLR6_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                     0x6
+#define BIFPLR6_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                              0x7
+#define BIFPLR6_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                          0x8
+#define BIFPLR6_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                         0x0001L
+#define BIFPLR6_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                          0x0002L
+#define BIFPLR6_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                          0x0004L
+#define BIFPLR6_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                     0x0008L
+#define BIFPLR6_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                           0x0010L
+#define BIFPLR6_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                            0x0020L
+#define BIFPLR6_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                       0x0040L
+#define BIFPLR6_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                                0x0080L
+#define BIFPLR6_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                            0x0100L
+//BIFPLR6_ROOT_CNTL
+#define BIFPLR6_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                         0x0
+#define BIFPLR6_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                     0x1
+#define BIFPLR6_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                        0x2
+#define BIFPLR6_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                             0x3
+#define BIFPLR6_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                  0x4
+#define BIFPLR6_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                           0x0001L
+#define BIFPLR6_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                       0x0002L
+#define BIFPLR6_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                          0x0004L
+#define BIFPLR6_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                               0x0008L
+#define BIFPLR6_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                    0x0010L
+//BIFPLR6_ROOT_CAP
+#define BIFPLR6_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                      0x0
+#define BIFPLR6_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                        0x0001L
+//BIFPLR6_ROOT_STATUS
+#define BIFPLR6_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                          0x0
+#define BIFPLR6_ROOT_STATUS__PME_STATUS__SHIFT                                                                0x10
+#define BIFPLR6_ROOT_STATUS__PME_PENDING__SHIFT                                                               0x11
+#define BIFPLR6_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR6_ROOT_STATUS__PME_STATUS_MASK                                                                  0x00010000L
+#define BIFPLR6_ROOT_STATUS__PME_PENDING_MASK                                                                 0x00020000L
+//BIFPLR6_DEVICE_CAP2
+#define BIFPLR6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                               0x0
+#define BIFPLR6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                                 0x4
+#define BIFPLR6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                  0x5
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                                0x6
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                                0x7
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                                0x8
+#define BIFPLR6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                    0x9
+#define BIFPLR6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                                 0xa
+#define BIFPLR6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                             0xb
+#define BIFPLR6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                        0xc
+#define BIFPLR6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                             0xe
+#define BIFPLR6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                           0x10
+#define BIFPLR6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                           0x11
+#define BIFPLR6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                            0x12
+#define BIFPLR6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                              0x14
+#define BIFPLR6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                              0x15
+#define BIFPLR6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                  0x16
+#define BIFPLR6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                            0x18
+#define BIFPLR6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                             0x1a
+#define BIFPLR6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                                 0x0000000FL
+#define BIFPLR6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                   0x00000010L
+#define BIFPLR6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                    0x00000020L
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                  0x00000040L
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                  0x00000080L
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                  0x00000100L
+#define BIFPLR6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                      0x00000200L
+#define BIFPLR6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                   0x00000400L
+#define BIFPLR6_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                               0x00000800L
+#define BIFPLR6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                          0x00003000L
+#define BIFPLR6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                               0x0000C000L
+#define BIFPLR6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                             0x00010000L
+#define BIFPLR6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                             0x00020000L
+#define BIFPLR6_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                              0x000C0000L
+#define BIFPLR6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                                0x00100000L
+#define BIFPLR6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                                0x00200000L
+#define BIFPLR6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                    0x00C00000L
+#define BIFPLR6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                              0x03000000L
+#define BIFPLR6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                               0x04000000L
+#define BIFPLR6_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR6_DEVICE_CNTL2
+#define BIFPLR6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                        0x0
+#define BIFPLR6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                          0x4
+#define BIFPLR6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                        0x5
+#define BIFPLR6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                      0x6
+#define BIFPLR6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                                 0x7
+#define BIFPLR6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                       0x8
+#define BIFPLR6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                    0x9
+#define BIFPLR6_DEVICE_CNTL2__LTR_EN__SHIFT                                                                   0xa
+#define BIFPLR6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                             0xb
+#define BIFPLR6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                             0xc
+#define BIFPLR6_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                  0xd
+#define BIFPLR6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                              0xf
+#define BIFPLR6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                          0x000FL
+#define BIFPLR6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                            0x0010L
+#define BIFPLR6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                          0x0020L
+#define BIFPLR6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                        0x0040L
+#define BIFPLR6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                   0x0080L
+#define BIFPLR6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                         0x0100L
+#define BIFPLR6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                      0x0200L
+#define BIFPLR6_DEVICE_CNTL2__LTR_EN_MASK                                                                     0x0400L
+#define BIFPLR6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                               0x0800L
+#define BIFPLR6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                               0x1000L
+#define BIFPLR6_DEVICE_CNTL2__OBFF_EN_MASK                                                                    0x6000L
+#define BIFPLR6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                                0x8000L
+//BIFPLR6_DEVICE_STATUS2
+#define BIFPLR6_DEVICE_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR6_DEVICE_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR6_LINK_CAP2
+#define BIFPLR6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                        0x1
+#define BIFPLR6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                         0x8
+#define BIFPLR6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                    0x10
+#define BIFPLR6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                   0x17
+#define BIFPLR6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                   0x18
+#define BIFPLR6_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                               0x1f
+#define BIFPLR6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                          0x000000FEL
+#define BIFPLR6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                           0x00000100L
+#define BIFPLR6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                      0x007F0000L
+#define BIFPLR6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                     0x00800000L
+#define BIFPLR6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                     0x01000000L
+#define BIFPLR6_LINK_CAP2__DRS_SUPPORTED_MASK                                                                 0x80000000L
+//BIFPLR6_LINK_CNTL2
+#define BIFPLR6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                          0x0
+#define BIFPLR6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                           0x4
+#define BIFPLR6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                                0x5
+#define BIFPLR6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                      0x6
+#define BIFPLR6_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                                0x7
+#define BIFPLR6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                       0xa
+#define BIFPLR6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                             0xb
+#define BIFPLR6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                      0xc
+#define BIFPLR6_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                            0x000FL
+#define BIFPLR6_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                             0x0010L
+#define BIFPLR6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                  0x0020L
+#define BIFPLR6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                        0x0040L
+#define BIFPLR6_LINK_CNTL2__XMIT_MARGIN_MASK                                                                  0x0380L
+#define BIFPLR6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                         0x0400L
+#define BIFPLR6_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                               0x0800L
+#define BIFPLR6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                        0xF000L
+//BIFPLR6_LINK_STATUS2
+#define BIFPLR6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                     0x0
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                                0x1
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                          0x2
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                          0x3
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                          0x4
+#define BIFPLR6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                            0x5
+#define BIFPLR6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                        0x6
+#define BIFPLR6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                        0x7
+#define BIFPLR6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                     0x8
+#define BIFPLR6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                            0xc
+#define BIFPLR6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                     0xf
+#define BIFPLR6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                       0x0001L
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                  0x0002L
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                            0x0004L
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                            0x0008L
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                            0x0010L
+#define BIFPLR6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                              0x0020L
+#define BIFPLR6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                          0x0040L
+#define BIFPLR6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                          0x0080L
+#define BIFPLR6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                       0x0300L
+#define BIFPLR6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                              0x7000L
+#define BIFPLR6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                       0x8000L
+//BIFPLR6_SLOT_CAP2
+#define BIFPLR6_SLOT_CAP2__RESERVED__SHIFT                                                                    0x0
+#define BIFPLR6_SLOT_CAP2__RESERVED_MASK                                                                      0xFFFFFFFFL
+//BIFPLR6_SLOT_CNTL2
+#define BIFPLR6_SLOT_CNTL2__RESERVED__SHIFT                                                                   0x0
+#define BIFPLR6_SLOT_CNTL2__RESERVED_MASK                                                                     0xFFFFL
+//BIFPLR6_SLOT_STATUS2
+#define BIFPLR6_SLOT_STATUS2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR6_SLOT_STATUS2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR6_MSI_CAP_LIST
+#define BIFPLR6_MSI_CAP_LIST__CAP_ID__SHIFT                                                                   0x0
+#define BIFPLR6_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                                 0x8
+#define BIFPLR6_MSI_CAP_LIST__CAP_ID_MASK                                                                     0x00FFL
+#define BIFPLR6_MSI_CAP_LIST__NEXT_PTR_MASK                                                                   0xFF00L
+//BIFPLR6_MSI_MSG_CNTL
+#define BIFPLR6_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                   0x0
+#define BIFPLR6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                            0x1
+#define BIFPLR6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                             0x4
+#define BIFPLR6_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                                0x7
+#define BIFPLR6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                                0x8
+#define BIFPLR6_MSI_MSG_CNTL__MSI_EN_MASK                                                                     0x0001L
+#define BIFPLR6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                              0x000EL
+#define BIFPLR6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                               0x0070L
+#define BIFPLR6_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                  0x0080L
+#define BIFPLR6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                  0x0100L
+//BIFPLR6_MSI_MSG_ADDR_LO
+#define BIFPLR6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                       0x2
+#define BIFPLR6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                         0xFFFFFFFCL
+//BIFPLR6_MSI_MSG_ADDR_HI
+#define BIFPLR6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                       0x0
+#define BIFPLR6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                         0xFFFFFFFFL
+//BIFPLR6_MSI_MSG_DATA
+#define BIFPLR6_MSI_MSG_DATA__MSI_DATA__SHIFT                                                                 0x0
+#define BIFPLR6_MSI_MSG_DATA__MSI_DATA_MASK                                                                   0xFFFFL
+//BIFPLR6_MSI_MSG_DATA_64
+#define BIFPLR6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                           0x0
+#define BIFPLR6_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                             0xFFFFL
+//BIFPLR6_SSID_CAP_LIST
+#define BIFPLR6_SSID_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define BIFPLR6_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                                0x8
+#define BIFPLR6_SSID_CAP_LIST__CAP_ID_MASK                                                                    0x00FFL
+#define BIFPLR6_SSID_CAP_LIST__NEXT_PTR_MASK                                                                  0xFF00L
+//BIFPLR6_SSID_CAP
+#define BIFPLR6_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                          0x0
+#define BIFPLR6_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                                 0x10
+#define BIFPLR6_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR6_SSID_CAP__SUBSYSTEM_ID_MASK                                                                   0xFFFF0000L
+//BIFPLR6_MSI_MAP_CAP_LIST
+#define BIFPLR6_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                               0x0
+#define BIFPLR6_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                             0x8
+#define BIFPLR6_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                                 0x00FFL
+#define BIFPLR6_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                               0xFF00L
+//BIFPLR6_MSI_MAP_CAP
+#define BIFPLR6_MSI_MAP_CAP__EN__SHIFT                                                                        0x0
+#define BIFPLR6_MSI_MAP_CAP__FIXD__SHIFT                                                                      0x1
+#define BIFPLR6_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                  0xb
+#define BIFPLR6_MSI_MAP_CAP__EN_MASK                                                                          0x0001L
+#define BIFPLR6_MSI_MAP_CAP__FIXD_MASK                                                                        0x0002L
+#define BIFPLR6_MSI_MAP_CAP__CAP_TYPE_MASK                                                                    0xF800L
+//BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                      0x0
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                     0x10
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                  0x14
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                       0x000F0000L
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                    0xFFF00000L
+//BIFPLR6_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR6_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                         0x0
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                           0xFFFFFFFFL
+//BIFPLR6_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR6_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                       0x4
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                         0x8
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                       0xa
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                      0x00000007L
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                         0x00000070L
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                           0x00000300L
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                         0x00000C00L
+//BIFPLR6_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                      0x0
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                             0x18
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                        0x000000FFL
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                               0xFF000000L
+//BIFPLR6_PCIE_PORT_VC_CNTL
+#define BIFPLR6_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                   0x0
+#define BIFPLR6_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                       0x1
+#define BIFPLR6_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                     0x0001L
+#define BIFPLR6_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                         0x000EL
+//BIFPLR6_PCIE_PORT_VC_STATUS
+#define BIFPLR6_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                               0x0
+#define BIFPLR6_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                                 0x0001L
+//BIFPLR6_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR6_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR6_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR6_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR6_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR6_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR6_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR6_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                              0xf
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                  0x10
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                                0x00008000L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                    0x007F0000L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR6_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                  0x0
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                                0x1
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                            0x10
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                                0x11
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                          0x18
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                      0x1f
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                    0x00000001L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                  0x000000FEL
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                              0x00010000L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                  0x000E0000L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                            0x07000000L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                        0x80000000L
+//BIFPLR6_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR6_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                        0x0
+#define BIFPLR6_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                       0x1
+#define BIFPLR6_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                          0x0001L
+#define BIFPLR6_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                         0x0002L
+//BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIFPLR6_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                              0x0
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                                0xFFFFFFFFL
+//BIFPLR6_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                              0x0
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                                0xFFFFFFFFL
+//BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR6_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                                 0x4
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                              0x5
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                                 0xc
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                  0xd
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                             0xe
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                           0xf
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                               0x10
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                                0x11
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                                 0x12
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                                0x13
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                          0x14
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                           0x15
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                          0x16
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                          0x17
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                                 0x18
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                  0x19
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                             0x1a
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                   0x00000010L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                                0x00000020L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                   0x00001000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                    0x00002000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                               0x00004000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                             0x00008000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                                 0x00010000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                  0x00020000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                   0x00040000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                  0x00080000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                            0x00100000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                             0x00200000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                            0x00400000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                            0x00800000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                   0x01000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                    0x02000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                               0x04000000L
+//BIFPLR6_PCIE_UNCORR_ERR_MASK
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                     0x4
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                  0x5
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                     0xc
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                      0xd
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                                 0xe
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                               0xf
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                   0x10
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                    0x11
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                     0x12
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                    0x13
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                              0x14
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                               0x15
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                              0x16
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                              0x17
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                     0x18
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                      0x19
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                                 0x1a
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                       0x00000010L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                    0x00000020L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                       0x00001000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                        0x00002000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                   0x00004000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                                 0x00008000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                     0x00010000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                      0x00020000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                       0x00040000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                      0x00080000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                                0x00100000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                                 0x00200000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                                0x00400000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                                0x00800000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                       0x01000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                        0x02000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                   0x04000000L
+//BIFPLR6_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                             0x4
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                          0x5
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                             0xc
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                              0xd
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                         0xe
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                       0xf
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                           0x10
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                            0x11
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                             0x12
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                            0x13
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                      0x14
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                       0x15
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                      0x16
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                      0x17
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                             0x18
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                              0x19
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                         0x1a
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                               0x00000010L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                            0x00000020L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                               0x00001000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                                0x00002000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                           0x00004000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                         0x00008000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                             0x00010000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                              0x00020000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                               0x00040000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                              0x00080000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                        0x00100000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                         0x00200000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                        0x00400000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                        0x00800000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                               0x01000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                                0x02000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                           0x04000000L
+//BIFPLR6_PCIE_CORR_ERR_STATUS
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                   0x0
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                   0x6
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                  0x7
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                       0x8
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                      0xc
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                     0xd
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                              0xe
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                              0xf
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                     0x00000001L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                     0x00000040L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                    0x00000080L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                         0x00000100L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                        0x00001000L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                       0x00002000L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                                0x00004000L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                                0x00008000L
+//BIFPLR6_PCIE_CORR_ERR_MASK
+#define BIFPLR6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                       0x0
+#define BIFPLR6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                       0x6
+#define BIFPLR6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                      0x7
+#define BIFPLR6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                           0x8
+#define BIFPLR6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                          0xc
+#define BIFPLR6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                         0xd
+#define BIFPLR6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                  0xe
+#define BIFPLR6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                  0xf
+#define BIFPLR6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                         0x00000001L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                         0x00000040L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                        0x00000080L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                             0x00000100L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                            0x00001000L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                           0x00002000L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                    0x00004000L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                    0x00008000L
+//BIFPLR6_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                   0x0
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                  0x7
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                   0x8
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                              0x9
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                               0xa
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                          0xb
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                  0xc
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                     0x0000001FL
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                    0x00000080L
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                     0x00000100L
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                                0x00000200L
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                                 0x00000400L
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                            0x00000800L
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                    0x00001000L
+//BIFPLR6_PCIE_HDR_LOG0
+#define BIFPLR6_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR6_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR6_PCIE_HDR_LOG1
+#define BIFPLR6_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR6_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR6_PCIE_HDR_LOG2
+#define BIFPLR6_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR6_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR6_PCIE_HDR_LOG3
+#define BIFPLR6_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                                 0x0
+#define BIFPLR6_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                   0xFFFFFFFFL
+//BIFPLR6_PCIE_ROOT_ERR_CMD
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                     0x0
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                                 0x1
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                    0x2
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                       0x00000001L
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                   0x00000002L
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                      0x00000004L
+//BIFPLR6_PCIE_ROOT_ERR_STATUS
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                               0x1
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                          0x2
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                     0x3
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                        0x4
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                          0x5
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                             0x6
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                              0x1b
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                      0x00000001L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                                 0x00000002L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                            0x00000004L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                       0x00000008L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                          0x00000010L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                            0x00000020L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                               0x00000040L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                                0xF8000000L
+//BIFPLR6_PCIE_ERR_SRC_ID
+#define BIFPLR6_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                       0x0
+#define BIFPLR6_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                             0x10
+#define BIFPLR6_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR6_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                               0xFFFF0000L
+//BIFPLR6_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR6_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR6_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR6_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                       0x0
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                         0xFFFFFFFFL
+//BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR6_PCIE_LINK_CNTL3
+#define BIFPLR6_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                  0x0
+#define BIFPLR6_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                          0x1
+#define BIFPLR6_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                    0x00000001L
+#define BIFPLR6_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                            0x00000002L
+//BIFPLR6_PCIE_LANE_ERROR_STATUS
+#define BIFPLR6_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                         0x0
+#define BIFPLR6_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                           0x0000FFFFL
+//BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0x4
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                 0x8
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                            0xc
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                 0x000FL
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                            0x0070L
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                   0x0F00L
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                              0x7000L
+//BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                              0x0
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0x4
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                                0x8
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                           0xc
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                                0x000FL
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                           0x0070L
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                  0x0F00L
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                             0x7000L
+//BIFPLR6_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR6_PCIE_ACS_CAP
+#define BIFPLR6_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                        0x0
+#define BIFPLR6_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                     0x1
+#define BIFPLR6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                     0x2
+#define BIFPLR6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                  0x3
+#define BIFPLR6_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                      0x4
+#define BIFPLR6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                       0x5
+#define BIFPLR6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                    0x6
+#define BIFPLR6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                               0x8
+#define BIFPLR6_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                          0x0001L
+#define BIFPLR6_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                       0x0002L
+#define BIFPLR6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                       0x0004L
+#define BIFPLR6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                    0x0008L
+#define BIFPLR6_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                        0x0010L
+#define BIFPLR6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                         0x0020L
+#define BIFPLR6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                      0x0040L
+#define BIFPLR6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                                 0xFF00L
+//BIFPLR6_PCIE_ACS_CNTL
+#define BIFPLR6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                                 0x1
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                                 0x2
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                              0x3
+#define BIFPLR6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                  0x4
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                   0x5
+#define BIFPLR6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                                0x6
+#define BIFPLR6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                      0x0001L
+#define BIFPLR6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                   0x0002L
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                   0x0004L
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                                0x0008L
+#define BIFPLR6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                    0x0010L
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                     0x0020L
+#define BIFPLR6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                  0x0040L
+//BIFPLR6_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR6_PCIE_MC_CAP
+#define BIFPLR6_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                              0x0
+#define BIFPLR6_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                           0x8
+#define BIFPLR6_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                        0xf
+#define BIFPLR6_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                                0x003FL
+#define BIFPLR6_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                             0x3F00L
+#define BIFPLR6_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                          0x8000L
+//BIFPLR6_PCIE_MC_CNTL
+#define BIFPLR6_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                             0x0
+#define BIFPLR6_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                                0xf
+#define BIFPLR6_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                               0x003FL
+#define BIFPLR6_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                  0x8000L
+//BIFPLR6_PCIE_MC_ADDR0
+#define BIFPLR6_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                            0x0
+#define BIFPLR6_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                          0xc
+#define BIFPLR6_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                              0x0000003FL
+#define BIFPLR6_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                            0xFFFFF000L
+//BIFPLR6_PCIE_MC_ADDR1
+#define BIFPLR6_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                          0x0
+#define BIFPLR6_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                            0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_RCV0
+#define BIFPLR6_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                             0x0
+#define BIFPLR6_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                               0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_RCV1
+#define BIFPLR6_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                             0x0
+#define BIFPLR6_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                               0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_BLOCK_ALL0
+#define BIFPLR6_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                     0x0
+#define BIFPLR6_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_BLOCK_ALL1
+#define BIFPLR6_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                     0x0
+#define BIFPLR6_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                  0x0
+#define BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                    0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                  0x0
+#define BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                    0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                  0x0
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                                 0x6
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                    0x0000003FL
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                   0xFFFFFFC0L
+//BIFPLR6_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                                 0x0
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                   0xFFFFFFFFL
+//BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR6_PCIE_L1_PM_SUB_CAP
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                              0x0
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                              0x1
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                                0x2
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                                0x3
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                                0x4
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                               0x8
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                              0x10
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                              0x13
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                                0x00000001L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                                0x00000002L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                  0x00000004L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                  0x00000008L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                  0x00000010L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                                 0x0000FF00L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                                0x00030000L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                                0x00F80000L
+//BIFPLR6_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                    0x1
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                      0x2
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                      0x3
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                          0x8
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                          0x1d
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                      0x00000001L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                      0x00000002L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                        0x00000004L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                        0x00000008L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                            0x0000FF00L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                            0xE0000000L
+//BIFPLR6_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                                 0x0
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                                 0x3
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                   0x00000003L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                   0x000000F8L
+//BIFPLR6_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR6_PCIE_DPC_CAP_LIST
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                               0x5
+#define BIFPLR6_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                              0x6
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                   0x7
+#define BIFPLR6_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                     0x8
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                               0xc
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                      0x001FL
+#define BIFPLR6_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                                 0x0020L
+#define BIFPLR6_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                                0x0040L
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                     0x0080L
+#define BIFPLR6_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                       0x0F00L
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                                 0x1000L
+//BIFPLR6_PCIE_DPC_CNTL
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                      0x0
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                  0x2
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                    0x3
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                      0x4
+#define BIFPLR6_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                     0x5
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                    0x6
+#define BIFPLR6_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                                0x7
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                        0x0003L
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                    0x0004L
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                      0x0008L
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                        0x0010L
+#define BIFPLR6_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                       0x0020L
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                      0x0040L
+#define BIFPLR6_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                  0x0080L
+//BIFPLR6_PCIE_DPC_STATUS
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                    0x1
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                  0x3
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                           0x4
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                          0x5
+#define BIFPLR6_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                            0x8
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                      0x0001L
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                      0x0006L
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                    0x0008L
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                             0x0010L
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                            0x0060L
+#define BIFPLR6_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                              0x1F00L
+//BIFPLR6_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR6_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                          0x0
+#define BIFPLR6_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                            0xFFFFL
+//BIFPLR6_PCIE_RP_PIO_STATUS
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR6_PCIE_RP_PIO_MASK
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                           0x0
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                           0x1
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                              0x2
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                            0x8
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                            0x9
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                               0xa
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                           0x10
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                           0x11
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                              0x12
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                             0x00000001L
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                             0x00000002L
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                                0x00000004L
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                              0x00000100L
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                              0x00000200L
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                                 0x00000400L
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                             0x00010000L
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                             0x00020000L
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                                0x00040000L
+//BIFPLR6_PCIE_RP_PIO_SEVERITY
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR6_PCIE_RP_PIO_SYSERROR
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR6_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                      0x0
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                      0x1
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                         0x2
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                       0x8
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                       0x9
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                          0xa
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                      0x10
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                      0x11
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                         0x12
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                        0x00000001L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                        0x00000002L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                           0x00000004L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                         0x00000100L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                         0x00000200L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                            0x00000400L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                        0x00010000L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                        0x00020000L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                           0x00040000L
+//BIFPLR6_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                          0x0
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                            0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                      0xFFFFFFFFL
+//BIFPLR6_PCIE_ESM_CAP_LIST
+#define BIFPLR6_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR6_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                             0x10
+#define BIFPLR6_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                            0x14
+#define BIFPLR6_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                                0x0000FFFFL
+#define BIFPLR6_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                               0x000F0000L
+#define BIFPLR6_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                              0xFFF00000L
+//BIFPLR6_PCIE_ESM_HEADER_1
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                       0x0
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                         0x10
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                         0x14
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                         0x0000FFFFL
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                           0x000F0000L
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                           0xFFF00000L
+//BIFPLR6_PCIE_ESM_HEADER_2
+#define BIFPLR6_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR6_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                                0xFFFFL
+//BIFPLR6_PCIE_ESM_STATUS
+#define BIFPLR6_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                  0x9
+#define BIFPLR6_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                      0x01FFL
+#define BIFPLR6_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                    0x0E00L
+//BIFPLR6_PCIE_ESM_CTRL
+#define BIFPLR6_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                             0xf
+#define BIFPLR6_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                               0x8000L
+//BIFPLR6_PCIE_ESM_CAP_1
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                               0x0
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                               0x1
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                               0x2
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                               0x3
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                               0x4
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                               0x5
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                               0x6
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                               0x7
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                               0x8
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                               0x9
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                               0xa
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                               0xb
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                               0xc
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                               0xd
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                               0xe
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                               0xf
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                               0x10
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                               0x11
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                               0x12
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                               0x13
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                              0x14
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                              0x15
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                              0x16
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                              0x17
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                              0x18
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                              0x19
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                              0x1a
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                              0x1b
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                              0x1c
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                              0x1d
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                                 0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                                 0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                                 0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                                 0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                                 0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                                 0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                                 0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                                 0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                                 0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                                 0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                                 0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                                 0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                                 0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                                 0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                                 0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                                 0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                                 0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                                 0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                                 0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                                 0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                                0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                                0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                                0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                                0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                                0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                                0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                                0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                                0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                                0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                                0x20000000L
+//BIFPLR6_PCIE_ESM_CAP_2
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                              0x0
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                              0x1
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                              0x2
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                              0x3
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                              0x4
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                              0x5
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                              0x6
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                              0x7
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                              0x8
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                              0x9
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                              0xa
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                              0xb
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                              0xc
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                              0xd
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                              0xe
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                              0xf
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                              0x10
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                              0x11
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                              0x12
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                              0x13
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                              0x14
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                              0x15
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                              0x16
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                              0x17
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                              0x18
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                              0x19
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                              0x1a
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                              0x1b
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                              0x1c
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                              0x1d
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                                0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                                0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                                0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                                0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                                0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                                0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                                0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                                0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                                0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                                0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                                0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                                0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                                0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                                0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                                0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                                0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                                0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                                0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                                0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                                0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                                0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                                0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                                0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                                0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                                0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                                0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                                0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                                0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                                0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                                0x20000000L
+//BIFPLR6_PCIE_ESM_CAP_3
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                              0x0
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                              0x1
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                              0x2
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                              0x3
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                              0x4
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                              0x5
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                              0x6
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                              0x7
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                              0x8
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                              0x9
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                              0xa
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                              0xb
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                              0xc
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                              0xd
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                              0xe
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                              0xf
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                              0x10
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                              0x11
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                              0x12
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                              0x13
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                                0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                                0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                                0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                                0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                                0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                                0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                                0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                                0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                                0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                                0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                                0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                                0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                                0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                                0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                                0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                                0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                                0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                                0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                                0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                                0x00080000L
+//BIFPLR6_PCIE_ESM_CAP_4
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                              0x0
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                              0x1
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                              0x2
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                              0x3
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                              0x4
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                              0x5
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                              0x6
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                              0x7
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                              0x8
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                              0x9
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                              0xa
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                              0xb
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                              0xc
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                              0xd
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                              0xe
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                              0xf
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                              0x10
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                              0x11
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                              0x12
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                              0x13
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                              0x14
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                              0x15
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                              0x16
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                              0x17
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                              0x18
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                              0x19
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                              0x1a
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                              0x1b
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                              0x1c
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                              0x1d
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                                0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                                0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                                0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                                0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                                0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                                0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                                0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                                0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                                0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                                0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                                0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                                0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                                0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                                0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                                0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                                0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                                0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                                0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                                0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                                0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                                0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                                0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                                0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                                0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                                0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                                0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                                0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                                0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                                0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                                0x20000000L
+//BIFPLR6_PCIE_ESM_CAP_5
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                              0x0
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                              0x1
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                              0x2
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                              0x3
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                              0x4
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                              0x5
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                              0x6
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                              0x7
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                              0x8
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                              0x9
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                              0xa
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                              0xb
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                              0xc
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                              0xd
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                              0xe
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                              0xf
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                              0x10
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                              0x11
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                              0x12
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                              0x13
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                              0x14
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                              0x15
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                              0x16
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                              0x17
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                              0x18
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                              0x19
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                              0x1a
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                              0x1b
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                              0x1c
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                              0x1d
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                                0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                                0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                                0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                                0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                                0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                                0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                                0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                                0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                                0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                                0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                                0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                                0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                                0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                                0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                                0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                                0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                                0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                                0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                                0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                                0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                                0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                                0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                                0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                                0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                                0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                                0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                                0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                                0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                                0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                                0x20000000L
+//BIFPLR6_PCIE_ESM_CAP_6
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                              0x0
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                              0x1
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                              0x2
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                              0x3
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                              0x4
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                              0x5
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                              0x6
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                              0x7
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                              0x8
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                              0x9
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                              0xa
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                              0xb
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                              0xc
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                              0xd
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                              0xe
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                              0xf
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                              0x10
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                              0x11
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                              0x12
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                              0x13
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                              0x14
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                              0x15
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                              0x16
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                              0x17
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                              0x18
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                              0x19
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                              0x1a
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                              0x1b
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                              0x1c
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                              0x1d
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                                0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                                0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                                0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                                0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                                0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                                0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                                0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                                0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                                0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                                0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                                0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                                0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                                0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                                0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                                0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                                0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                                0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                                0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                                0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                                0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                                0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                                0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                                0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                                0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                                0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                                0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                                0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                                0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                                0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                                0x20000000L
+//BIFPLR6_PCIE_ESM_CAP_7
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                              0x0
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                              0x1
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                              0x2
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                              0x3
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                              0x4
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                              0x5
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                              0x6
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                              0x7
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                              0x8
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                              0x9
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                              0xa
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                              0xb
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                              0xc
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                              0xd
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                              0xe
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                              0xf
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                              0x10
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                              0x11
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                              0x12
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                              0x13
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                              0x14
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                              0x15
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                              0x16
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                              0x17
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                              0x18
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                              0x19
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                              0x1a
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                              0x1b
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                              0x1c
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                              0x1d
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                              0x1e
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                                0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                                0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                                0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                                0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                                0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                                0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                                0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                                0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                                0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                                0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                                0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                                0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                                0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                                0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                                0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                                0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                                0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                                0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                                0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                                0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                                0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                                0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                                0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                                0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                                0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                                0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                                0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                                0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                                0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                                0x20000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                                0x40000000L
+//BIFPLR6_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                         0x10
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                        0x14
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                            0x0000FFFFL
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                           0x000F0000L
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                          0xFFF00000L
+//BIFPLR6_DATA_LINK_FEATURE_CAP
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                         0x0
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                        0x1
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                             0x1f
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                           0x00000001L
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                          0x007FFFFEL
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                               0x80000000L
+//BIFPLR6_DATA_LINK_FEATURE_STATUS
+#define BIFPLR6_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                         0x0
+#define BIFPLR6_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                   0x1f
+#define BIFPLR6_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                           0x007FFFFFL
+#define BIFPLR6_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                     0x80000000L
+//BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                    0x10
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                   0x14
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                      0x000F0000L
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                     0xFFF00000L
+//BIFPLR6_LINK_CAP_16GT
+#define BIFPLR6_LINK_CAP_16GT__RESERVED__SHIFT                                                                0x0
+#define BIFPLR6_LINK_CAP_16GT__RESERVED_MASK                                                                  0xFFFFFFFFL
+//BIFPLR6_LINK_CNTL_16GT
+#define BIFPLR6_LINK_CNTL_16GT__RESERVED__SHIFT                                                               0x0
+#define BIFPLR6_LINK_CNTL_16GT__RESERVED_MASK                                                                 0xFFFFFFFFL
+//BIFPLR6_LINK_STATUS_16GT
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                           0x0
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                     0x1
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                     0x2
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                     0x3
+#define BIFPLR6_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                       0x4
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                             0x00000001L
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                       0x00000002L
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                       0x00000004L
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                       0x00000008L
+#define BIFPLR6_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                         0x00000010L
+//BIFPLR6_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR6_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR6_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR6_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR6_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                     0x0
+#define BIFPLR6_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                       0x0000FFFFL
+//BIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                               0x0
+#define BIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                               0x4
+#define BIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                                 0x0FL
+#define BIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                                 0xF0L
+//BIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                   0x10
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                  0x14
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                     0x000F0000L
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                    0xFFF00000L
+//BIFPLR6_MARGINING_PORT_CAP
+#define BIFPLR6_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                            0x0
+#define BIFPLR6_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                              0x0001L
+//BIFPLR6_MARGINING_PORT_STATUS
+#define BIFPLR6_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                                 0x0
+#define BIFPLR6_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                        0x1
+#define BIFPLR6_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                   0x0001L
+#define BIFPLR6_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                          0x0002L
+//BIFPLR6_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR6_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR6_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR6_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR6_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR6_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR6_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR6_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR6_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR6_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR6_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR6_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR6_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR6_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR6_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR6_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR6_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR6_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR6_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                     0x0
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                         0x3
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                         0x6
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                      0x8
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                       0x0007L
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                           0x0038L
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                           0x0040L
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                        0xFF00L
+//BIFPLR6_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                            0x0
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                                0x3
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                                0x6
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                             0x8
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                              0x0007L
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                  0x0038L
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                  0x0040L
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                               0xFF00L
+//BIFPLR6_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_PCIE_CCIX_CAP_LIST
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                            0x10
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                           0x14
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                               0x0000FFFFL
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                              0x000F0000L
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                             0xFFF00000L
+//BIFPLR6_PCIE_CCIX_HEADER_1
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR6_PCIE_CCIX_HEADER_2
+#define BIFPLR6_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR6_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                               0xFFFFL
+//BIFPLR6_PCIE_CCIX_CAP
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                      0x0
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                         0x1
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                        0x3
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                    0x4
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                          0x8
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                        0x0001L
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                           0x0006L
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                          0x0008L
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                      0x0070L
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                            0x0700L
+//BIFPLR6_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                              0x0
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                                0x1
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                                0x2
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                               0x5
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                               0x9
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                               0xe
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                                0x00000001L
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                  0x00000002L
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                  0x00000004L
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                                 0x00000020L
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                                 0x00000200L
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                                 0x00004000L
+//BIFPLR6_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR6_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                       0x0
+#define BIFPLR6_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIFPLR6_PCIE_CCIX_ESM_STATUS
+#define BIFPLR6_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                            0x0
+#define BIFPLR6_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                         0x7
+#define BIFPLR6_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                              0x0000007FL
+#define BIFPLR6_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                           0x00000080L
+//BIFPLR6_PCIE_CCIX_ESM_CNTL
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                     0x0
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                            0x7
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                     0x8
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                         0xf
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                           0x10
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                           0x14
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                  0x18
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                    0x19
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                              0x1a
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                       0x0000007FL
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                              0x00000080L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                       0x00007F00L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                           0x00008000L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                             0x00070000L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                             0x00700000L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                    0x01000000L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                      0x02000000L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                                0x1C000000L
+//BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                       0x0
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                       0x4
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                         0x0FL
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                         0xF0L
+//BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_PCIE_CCIX_TRANS_CAP
+#define BIFPLR6_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                                 0x0
+#define BIFPLR6_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                   0x00000001L
+//BIFPLR6_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR6_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                                 0x0
+#define BIFPLR6_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                   0x00000001L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1
+//BIF_BX_PF0_MM_INDEX
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT                                                                 0x0
+#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT                                                                   0x1f
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK                                                                   0x7FFFFFFFL
+#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK                                                                     0x80000000L
+//BIF_BX_PF0_MM_DATA
+#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT                                                                    0x0
+#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK                                                                      0xFFFFFFFFL
+//BIF_BX_PF0_MM_INDEX_HI
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                           0x0
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                             0xFFFFFFFFL
+//BIF_BX_PF0_RSMU_INDEX
+#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT                                                              0x0
+#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK                                                                0xFFFFFFFFL
+//BIF_BX_PF0_RSMU_DATA
+#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT                                                                0x0
+#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK                                                                  0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC:1
+//BIF_BX0_PCIE_INDEX
+#define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT                                                                 0x0
+#define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK                                                                   0xFFFFFFFFL
+//BIF_BX0_PCIE_DATA
+#define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT                                                                   0x0
+#define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK                                                                     0xFFFFFFFFL
+//BIF_BX0_PCIE_INDEX2
+#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT                                                               0x0
+#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK                                                                 0xFFFFFFFFL
+//BIF_BX0_PCIE_DATA2
+#define BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT                                                                 0x0
+#define BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK                                                                   0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_0
+#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_1
+#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_2
+#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_3
+#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_0
+#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_1
+#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_2
+#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_3
+#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_4
+#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_5
+#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_6
+#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_7
+#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_8
+#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_9
+#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_10
+#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_11
+#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_12
+#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_13
+#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_14
+#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_15
+#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIF_RLC_INTR_CNTL
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT                                                    0x0
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT                                             0x1
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT                                                   0x2
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT                                              0x3
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK                                                      0x00000001L
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK                                               0x00000002L
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK                                                     0x00000004L
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK                                                0x00000008L
+//BIF_BX0_BIF_VCE_INTR_CNTL
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT                                                    0x0
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT                                             0x1
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT                                                   0x2
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT                                              0x3
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK                                                      0x00000001L
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK                                               0x00000002L
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK                                                     0x00000004L
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK                                                0x00000008L
+//BIF_BX0_BIF_UVD_INTR_CNTL
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT                                                    0x0
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT                                             0x1
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT                                                   0x2
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT                                              0x3
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT                                                        0x1c
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK                                                      0x00000001L
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK                                               0x00000002L
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK                                                     0x00000004L
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK                                                0x00000008L
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK                                                          0xF0000000L
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK                                                         0x000000FFL
+//BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT                                                 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK                                                   0xFFFFFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT                                                   0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK                                                     0xFFFFFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT                                 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK                                   0xFFFFFFFFL
+
+
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+//RCC_STRAP0_RCC_BIF_STRAP0
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT                                                  0x0
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT                                                   0x2
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT                                               0x3
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT                                               0x6
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT                                                    0x7
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT                                                 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT                                  0x9
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT                                         0xa
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT                                     0xb
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT                                              0xc
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT                                             0xd
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                     0xe
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                  0xf
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT                                              0x10
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT                                           0x11
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT                                                      0x18
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT                                                 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT                                                0x1a
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT                                      0x1d
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT                                                   0x1e
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT                                            0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK                                                    0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK                                                     0x00000004L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK                                                 0x00000038L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK                                                 0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK                                                      0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK                                                   0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK                                    0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK                                           0x00000400L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK                                       0x00000800L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK                                                0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK                                               0x00002000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                       0x00004000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                    0x00008000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK                                                0x00010000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK                                             0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK                                                        0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK                                                   0x02000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK                                                  0x04000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK                                       0x08000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK                                        0x20000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK                                                     0x40000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK                                              0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP1
+#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT                                                      0x1
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT                                      0x3
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT                                     0x5
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                       0x6
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT                                               0x7
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT                                                  0x8
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT                                                 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT                                                  0xa
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT                                        0xc
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT                                                    0xd
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT                                                    0xf
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT                                             0x11
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT                                             0x12
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT                                                        0x13
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT                                                   0x14
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT                                                     0x15
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT                                             0x16
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT                                     0x17
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT                                             0x1a
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT                                       0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT                                                     0x1d
+#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK                                                        0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK                                        0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK                                       0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK                                         0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK                                                 0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK                                                    0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK                                                   0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK                                                    0x00000C00L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK                                          0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK                                                      0x00006000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK                                                      0x00018000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK                                               0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK                                               0x00040000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK                                                          0x00080000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK                                                     0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK                                                       0x00200000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK                                               0x00400000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK                                       0x00800000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK                                               0x04000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK                                         0x18000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK                                                       0x20000000L
+//RCC_STRAP0_RCC_BIF_STRAP2
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT                                     0x0
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT                                            0x3
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT                                            0x4
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT                                        0x5
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT                                      0x6
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT                                 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT                                        0x9
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT                                   0xa
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT                                                 0xd
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT                                             0xe
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT                                 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT                                         0x10
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT                                        0x18
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT                            0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK                                       0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK                                              0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK                                              0x00000010L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK                                          0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK                                        0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK                                   0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK                                          0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK                                     0x00000C00L
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK                                                   0x00002000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK                                               0x00004000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK                                   0x00008000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK                                           0x00FF0000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK                                          0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK                              0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP3
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT                                         0x0
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT                                       0x10
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK                                         0xFFFF0000L
+//RCC_STRAP0_RCC_BIF_STRAP4
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT                                          0x0
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT                                           0x10
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK                                            0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK                                             0xFFFF0000L
+//RCC_STRAP0_RCC_BIF_STRAP5
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT                                         0x0
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT                                      0x10
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT                                   0x11
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT                                    0x12
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT                                        0x13
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT                                    0x14
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT                                         0x16
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT                          0x18
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x19
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT                                           0x1c
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK                                        0x00010000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK                                     0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK                                      0x00040000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK                                          0x00080000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK                                      0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK                                           0x00C00000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK                            0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x06000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x08000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK                                             0x70000000L
+//RCC_STRAP0_RCC_BIF_STRAP6
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT                                          0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT                                          0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT                                          0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT                                0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT                                       0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT                                   0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT                            0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT                             0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT                             0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT                                      0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK                                            0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK                                            0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK                                            0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK                                  0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK                                         0x001FFFE0L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK                                     0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK                              0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK                               0x0E000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK                               0x70000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK                                        0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT                                       0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT                                   0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK                                         0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK                                     0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT                                 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT                                          0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT                                      0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT                                          0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT                                      0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT                                  0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT                             0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT                                0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT                                    0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT                              0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT                      0xd
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT                                    0xe
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT                                            0xf
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT                                    0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT                                    0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT                                  0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT                             0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT                                   0x17
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT                              0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT                                    0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK                                   0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK                                            0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK                                        0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK                                            0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK                                        0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK                                    0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK                               0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK                                  0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK                                      0x00000E00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK                                0x00001000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK                        0x00002000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK                                      0x00004000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK                                              0x00008000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK                                      0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK                                      0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK                                    0x000C0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK                               0x00700000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK                                     0x03800000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK                                0x1C000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK                                      0xE0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT                     0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT                                             0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT                                          0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT                                0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT                                          0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT                                  0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT                                   0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT                                     0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0xb
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0xe
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT                                         0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT                                      0x1b
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT                                       0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT                                         0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK                       0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK                                               0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK                                            0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK                                  0x00000038L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK                                            0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK                                    0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK                                     0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK                                       0x00000600L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x00003800L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK  0x0003C000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x001C0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK  0x01E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK                                           0x06000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK                                        0x18000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK                                         0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK                                           0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT                              0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT                              0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT                              0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK                                0xFF000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT                              0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT                        0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT                                 0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT                                  0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT                                           0x13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT                                           0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT                                        0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT                                0x16
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT                           0x17
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT                        0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT                        0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT                     0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT                         0x1b
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT                          0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT                       0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT                                         0x1e
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT                                            0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK                          0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK                                   0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK                                    0x00040000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK                                             0x00080000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK                                             0x00100000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK                                          0x00200000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK                                  0x00400000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK                             0x00800000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK                          0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK                          0x02000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK                       0x04000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK                           0x08000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK                            0x10000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK                         0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK                                           0x40000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK                                              0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT                                         0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT                         0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT                      0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                      0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                   0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT     0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT     0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT                              0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT                            0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT                     0x13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK                                           0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK                           0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK                        0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                        0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                     0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK       0x00000F00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK       0x0000F000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK                                0x00030000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK                              0x00040000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK                       0x00080000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT                                        0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT                                    0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT                                    0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT                                          0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT                                          0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT                                          0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK                                          0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK                                      0x00000F00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK                                      0x0000F000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK                                            0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK                                            0x1F000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK                                            0xE0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT                              0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT                              0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT                              0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK                                0xFF000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT                              0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT                                       0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK                                         0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT                       0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK                                0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK                         0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT                                 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT                                0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK                                   0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK                                   0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK                                  0x00FF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT                                      0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK                                        0x0000FFFFL
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT                                        0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT                                 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT                                       0x6
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT                                   0x7
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT                                 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT                          0xe
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT                                          0xf
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT                                          0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT                                          0x11
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT                                0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT                                          0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT                                           0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT                                   0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT                                     0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT                                        0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT                  0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT               0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT                       0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK                                          0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK                                   0x0000003EL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK                                         0x00000040L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK                                     0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK                                   0x00003E00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK                            0x00004000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK                                            0x00008000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK                                            0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK                                            0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK                                  0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK                                            0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK                                             0x00800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK                                     0x07000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK                                       0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK                                          0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK                    0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK                 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK                         0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT                      0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT                                          0x1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT                                       0x2
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT                              0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT                                         0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT                                  0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT                                         0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT                        0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT                       0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT                                0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT                                       0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT                               0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK                        0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK                                            0x00000002L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK                                         0x0003FFFCL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK                                0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK                                           0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK                                    0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK                                           0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK                          0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK                         0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK                                  0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK                                         0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK                                 0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT                                       0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT                                     0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT                                   0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT                                  0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK                                   0x000003FFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK                                         0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK                                       0x0F800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK                                     0x70000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK                                    0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT                                   0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT                            0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK                                     0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK                              0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT                                0x3
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT                                     0x4
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT                                      0x7
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT                                     0x9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT                                     0xd
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                           0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT                                  0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT                                  0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT                                         0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT                                0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT                           0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK                                0x00000007L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK                                  0x00000008L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK                                       0x00000070L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK                                        0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK                                       0x00001E00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK                                       0x0000E000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK                             0x00070000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK                                    0x00780000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK                                    0x03800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK                                           0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK                                  0x38000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK                             0xC0000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT                           0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT                               0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT                        0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT                                    0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT                                 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT                                 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK                             0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK                                 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK                          0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK                                      0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK                                   0x00C00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK                                   0x0F000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT                                       0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT                                    0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT                                    0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT                                         0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT                           0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT                                      0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT                                      0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK                                         0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK                                      0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK                                      0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK                                           0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK                             0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK                                        0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK                                        0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP10
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP11
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP12
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT                                 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT                                 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT                                0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK                                   0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK                                   0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK                                  0x00FF0000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT                                      0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK                                        0x0000FFFFL
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT                                   0x7
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT                                   0x8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT                                 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT                          0xe
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT                                          0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT                                          0x11
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT                                          0x12
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT                                0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT                                          0x15
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT                                          0x16
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT                                           0x17
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT                                   0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT                                        0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT                  0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT               0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT                       0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK                                     0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK                                     0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK                                   0x00003E00L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK                            0x00004000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK                                            0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK                                            0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK                                            0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK                                  0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK                                            0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK                                            0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK                                             0x00800000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK                                     0x07000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK                                          0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK                    0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK                 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK                         0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT                      0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT                                          0x1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT                                       0x2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT                                          0x12
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT                              0x13
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT                                         0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT                                         0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT                        0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT                       0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT                                       0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT                               0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK                        0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK                                            0x00000002L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK                                         0x0003FFFCL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK                                            0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK                                0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK                                           0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK                                           0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK                          0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK                         0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK                                         0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK                                 0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT                                 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT                                       0x15
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT                                          0x16
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT                                     0x17
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT                                   0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT                                  0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK                                   0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK                                         0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK                                            0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK                                       0x0F800000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK                                     0x70000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK                                    0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT                                   0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT                            0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK                                     0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK                              0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT                                        0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT                                  0x2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK                                          0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00000002L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK                                    0x00000004L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP7
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1:1
+//RCC_EP_DEV0_0_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
+//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
+//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
+//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
+//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                  0x3
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                    0x00000008L
+//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                           0x1d
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                             0x20000000L
+//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT                                         0x4
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK                                           0x00000010L
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
+//RCC_EP_DEV0_0_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
+//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                            0x8
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                               0x12
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                   0x18
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                   0x19
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                   0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT                                   0x1b
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT                                   0x1c
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT                                   0x1d
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT                                   0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT                                   0x1f
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                              0x00000700L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                 0x00040000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                     0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                     0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                     0x04000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK                                     0x08000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK                                     0x10000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK                                     0x20000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK                                     0x40000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK                                     0x80000000L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                          0x0
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                          0x1
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                          0x2
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                            0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                            0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                            0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1:1
+//RCC_DWN_DEV0_0_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
+//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
+//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
+//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
+//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                 0x3
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                   0x00000008L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT                                                0x11
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT                                        0x15
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK                                                     0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK                                                  0x00020000L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK                                          0x00E00000L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT                                             0x18
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                          0x1d
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK                                               0x01000000L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                            0x20000000L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT                                    0x2
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK                                      0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1:1
+//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                             0x8
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                    0xb
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                               0x00000700L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                      0x00000800L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
+//RCC_DWNP_DEV0_0_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
+//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                           0x0
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                           0x1
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                           0x2
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                             0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                             0x00000002L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                             0x00000004L
+//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                               0x0
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
+//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT                                          0xa
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK                                            0x00000400L
+//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1
+//RCC_DEV0_EPF0_0_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                                0x0
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                       0x1
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                  0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                         0x00000002L
+//RCC_DEV0_EPF0_0_RCC_ERR_LOG_1
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_1__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_1__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_1__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_1__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_0_RCC_ERR_LOG_2
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_2__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_2__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_2__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_2__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                       0x00000001L
+//RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_1
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_1__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_1__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_2
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_2__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_2__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_1
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_1__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_1__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_2
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_2__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_2__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_1
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_1__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_1__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_2
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_2__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_2__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                       0x0
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                            0x1f
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                         0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                              0x80000000L
+//RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1__IOV_ENABLE_MASK                                            0x80000000L
+//RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2__IOV_ENABLE_MASK                                            0x80000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1:1
+//RCC_DEV0_0_RCC_ERR_INT_CNTL
+#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT                                0x0
+#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK                                  0x00000001L
+//RCC_DEV0_0_RCC_BACO_CNTL_MISC
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT                                                 0x0
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT                                                  0x1
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK                                                   0x00000001L
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK                                                    0x00000002L
+//RCC_DEV0_0_RCC_RESET_EN
+#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT                                                      0xf
+#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK                                                        0x00008000L
+//RCC_DEV0_0_RCC_VDM_SUPPORT
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT                                                       0x0
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT                                                      0x1
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT                                                  0x2
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT                                        0x3
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT                                    0x4
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK                                                         0x00000001L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK                                                        0x00000002L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK                                                    0x00000004L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK                                          0x00000008L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK                                      0x00000010L
+//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT                                 0x0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT                              0x1
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT                                0x2
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT                                 0x3
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT                           0x4
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT                                  0x5
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT                                 0xb
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT                                 0x12
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT                                0x19
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK                                   0x00000001L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK                                0x00000002L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK                                  0x00000004L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK                                   0x00000008L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK                             0x00000010L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK                                    0x000007E0L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK                                   0x0003F800L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK                                   0x01FC0000L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK                                  0xFE000000L
+//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT                             0x0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT                              0x6
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT                                         0xc
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT                                      0x11
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK                               0x0000003FL
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK                                0x00000FC0L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK                                           0x0001F000L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK                                        0x00FE0000L
+//RCC_DEV0_0_RCC_GPUIOV_REGION
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT                                                       0x0
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT                                                       0x4
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK                                                         0x00000007L
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK                                                         0x00000070L
+//RCC_DEV0_0_RCC_GPU_HOSTVM_EN
+#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT                                                    0x0
+#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK                                                      0x00000001L
+//RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT                              0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT                                    0x1
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK                                0x00000001L
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK                                      0x00000002L
+//RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT                        0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK                          0xFFFFL
+//RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT                                    0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK                                      0xFFFFL
+//RCC_DEV0_0_RCC_PEER_REG_RANGE0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT                                                     0x0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT                                                       0x10
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK                                                       0x0000FFFFL
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK                                                         0xFFFF0000L
+//RCC_DEV0_0_RCC_PEER_REG_RANGE1
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT                                                     0x0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT                                                       0x10
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK                                                       0x0000FFFFL
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK                                                         0xFFFF0000L
+//RCC_DEV0_0_RCC_BUS_CNTL
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT                                                            0x2
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT                                                           0x3
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT                                                            0x4
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT                                                         0x5
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT                                                        0x6
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT                                                         0x7
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT                                                        0x8
+#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT                                                 0xc
+#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT                                           0xd
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x10
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x11
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x12
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x13
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x14
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x15
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT                                                 0x18
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                 0x19
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT                                            0x1c
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                            0x1d
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK                                                              0x00000004L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK                                                             0x00000008L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK                                                              0x00000010L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK                                                           0x00000020L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK                                                          0x00000040L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK                                                           0x00000080L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK                                                          0x00000100L
+#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK                                                   0x00001000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK                                             0x00002000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00010000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00020000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00040000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00080000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00100000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00200000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK                                                   0x01000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK                                                   0x0E000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK                                              0x10000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK                                              0xE0000000L
+//RCC_DEV0_0_RCC_CONFIG_CNTL
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT                                                     0x0
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT                                               0x2
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT                                                        0x3
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK                                                       0x00000001L
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK                                                 0x00000004L
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK                                                          0x00000018L
+//RCC_DEV0_0_RCC_CONFIG_F0_BASE
+#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT                                                         0x0
+#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK                                                           0xFFFFFFFFL
+//RCC_DEV0_0_RCC_CONFIG_APER_SIZE
+#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT                                                     0x0
+#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK                                                       0xFFFFFFFFL
+//RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE
+#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT                                             0x0
+#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK                                               0x07FFFFFFL
+//RCC_DEV0_0_RCC_XDMA_LO
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT                                                   0x0
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT                                                       0x1f
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK                                                     0x7FFFFFFFL
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK                                                         0x80000000L
+//RCC_DEV0_0_RCC_XDMA_HI
+#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT                                                   0x0
+#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK                                                     0x7FFFFFFFL
+//RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT                                   0x7
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT                                 0x8
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT                                    0x9
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT                                    0xa
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT                                 0xb
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT                                  0xc
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT                                      0xd
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT                      0xe
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT                                 0x10
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT                           0x11
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT                               0x12
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT                     0x13
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK                                     0x00000080L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK                                   0x00000100L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK                                      0x00000200L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK                                      0x00000400L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK                                   0x00000800L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK                                    0x00001000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK                                        0x00002000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK                        0x00004000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK                                   0x00010000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK                             0x00020000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK                                 0x00040000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK                       0x00080000L
+//RCC_DEV0_0_RCC_BUSNUM_CNTL1
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT                                                           0x0
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK                                                             0x000000FFL
+//RCC_DEV0_0_RCC_BUSNUM_LIST0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT                                                               0x0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT                                                               0x8
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT                                                               0x10
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT                                                               0x18
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK                                                                 0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK                                                                 0x0000FF00L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK                                                                 0x00FF0000L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK                                                                 0xFF000000L
+//RCC_DEV0_0_RCC_BUSNUM_LIST1
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT                                                               0x0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT                                                               0x8
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT                                                               0x10
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT                                                               0x18
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK                                                                 0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK                                                                 0x0000FF00L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK                                                                 0x00FF0000L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK                                                                 0xFF000000L
+//RCC_DEV0_0_RCC_BUSNUM_CNTL2
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT                                                    0x0
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT                                                     0x8
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT                                                       0x10
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT                                           0x11
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK                                                      0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK                                                       0x00000100L
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK                                                         0x00010000L
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK                                             0x00020000L
+//RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM
+#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT                                                   0x0
+#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK                                                     0x00000001L
+//RCC_DEV0_0_RCC_HOST_BUSNUM
+#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT                                                            0x0
+#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK                                                              0x0000FFFFL
+//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT                                                   0x0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT                                                   0x8
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT                                                   0x10
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT                                                   0x18
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK                                                     0x000000FFL
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK                                                     0x0000FF00L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK                                                     0x00FF0000L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK                                                     0xFF000000L
+//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT                                                   0x0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT                                                   0x8
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT                                                   0x10
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT                                                   0x18
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK                                                     0x000000FFL
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK                                                     0x0000FF00L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK                                                     0x00FF0000L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK                                                     0xFF000000L
+//RCC_DEV0_0_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT                                                  0x0
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT                                                 0x8
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK                                                    0x00000001L
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK                                                   0x00000100L
+//RCC_DEV0_0_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT                                             0x0
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT                                              0x1
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT                                             0x2
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT                                          0x3
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT                                             0x10
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK                                               0x00000001L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK                                                0x00000002L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK                                               0x00000004L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK                                            0x00000008L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK                                               0xFFFF0000L
+//RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT                                            0x0
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT                                            0x8
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK                                              0x000000FFL
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK                                              0x00001F00L
+//RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT                                         0x0
+#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK                                           0x000003FFL
+//RCC_DEV0_0_RCC_MH_ARB_CNTL
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT                                                        0x0
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT                                                0x1
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK                                                          0x00000001L
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK                                                  0x00007FFEL
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1:1
+//BIF_BX0_CC_BIF_BX_STRAP0
+#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT                                                       0x19
+#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK                                                         0xFE000000L
+//BIF_BX0_CC_BIF_BX_PINSTRAP0
+//BIF_BX0_BIF_MM_INDACCESS_CNTL
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT                                                0x1
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK                                                  0x00000002L
+//BIF_BX0_BUS_CNTL
+#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT                                                        0x6
+#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT                                                        0x7
+#define BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT                                                                    0xa
+#define BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT                                                                    0xd
+#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT                                                                0x10
+#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT                                                                0x11
+#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT                                                               0x12
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT                                              0x18
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT                                          0x19
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT                                         0x1a
+#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT                                        0x1b
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT                                          0x1c
+#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT                                                     0x1d
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT                                                          0x1e
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT                                                          0x1f
+#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK                                                          0x00000040L
+#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK                                                          0x00000080L
+#define BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK                                                                      0x00001C00L
+#define BIF_BX0_BUS_CNTL__SET_MC_TC_MASK                                                                      0x0000E000L
+#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK                                                                  0x00010000L
+#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK                                                                  0x00020000L
+#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK                                                                 0x00040000L
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK                                                0x01000000L
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK                                            0x02000000L
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK                                           0x04000000L
+#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK                                          0x08000000L
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK                                            0x10000000L
+#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK                                                       0x20000000L
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK                                                            0x40000000L
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK                                                            0x80000000L
+//BIF_BX0_BIF_SCRATCH0
+#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT                                                             0x0
+#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_BIF_SCRATCH1
+#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT                                                             0x0
+#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_BX_RESET_EN
+#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT                                                  0x10
+#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK                                                    0x00010000L
+//BIF_BX0_MM_CFGREGS_CNTL
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT                                                       0x0
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT                                                        0x6
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT                                                       0x1f
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK                                                         0x00000007L
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK                                                          0x000000C0L
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK                                                         0x80000000L
+//BIF_BX0_BX_RESET_CNTL
+#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT                                                           0x0
+#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK                                                             0x00000001L
+//BIF_BX0_INTERRUPT_CNTL
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT                                                   0x0
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT                                                         0x1
+#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT                                                     0x3
+#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT                                                       0x4
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT                                                 0xf
+#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT                                               0x10
+#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT                                   0x11
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT                                              0x12
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK                                                     0x00000001L
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK                                                           0x00000002L
+#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK                                                       0x00000008L
+#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK                                                         0x000000F0L
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK                                                   0x00008000L
+#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK                                                 0x00010000L
+#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK                                     0x00020000L
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK                                                0x00040000L
+//BIF_BX0_INTERRUPT_CNTL2
+#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT                                                      0x0
+#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK                                                        0xFFFFFFFFL
+//BIF_BX0_CLKREQB_PAD_CNTL
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT                                                        0x0
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT                                                      0x1
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT                                                     0x2
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT                                                    0x3
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT                                                      0x5
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT                                                      0x6
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT                                                      0x7
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT                                                      0x8
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT                                                    0x9
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT                                                     0xa
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT                                                   0xb
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT                                                  0xc
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT                                                        0xd
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK                                                          0x00000001L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK                                                        0x00000002L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK                                                       0x00000004L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK                                                      0x00000018L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK                                                        0x00000020L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK                                                        0x00000040L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK                                                        0x00000080L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK                                                        0x00000100L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK                                                      0x00000200L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK                                                       0x00000400L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK                                                     0x00000800L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK                                                    0x00001000L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK                                                          0x00002000L
+//BIF_BX0_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT                                          0x0
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT                                          0x1
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT                                          0x2
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT                                          0x3
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT                             0xb
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT                                      0xc
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT                                          0xd
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT                                           0xf
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT                                           0x10
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT                   0x18
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK                                            0x00000001L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK                                            0x00000002L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK                                            0x00000004L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK                                            0x00000008L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK                               0x00000800L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK                                        0x00001000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK                                            0x00002000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK                                             0x00008000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK                                             0x00FF0000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK                     0x01000000L
+//BIF_BX0_BIF_DOORBELL_CNTL
+#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT                                                       0x0
+#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT                                                     0x1
+#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT                                                    0x2
+#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT                                         0x3
+#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT                                                 0x4
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT                                                  0x18
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT                                               0x19
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT                                               0x1a
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT                                               0x1b
+#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK                                                         0x00000001L
+#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK                                                       0x00000002L
+#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK                                                      0x00000004L
+#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK                                           0x00000008L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK                                                   0x00000010L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK                                                    0x01000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK                                                 0x02000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK                                                 0x04000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK                                                 0x08000000L
+//BIF_BX0_BIF_DOORBELL_INT_CNTL
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT                                       0x0
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT                                      0x1
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT                            0x2
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT                                        0x10
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT                                       0x11
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT                             0x12
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT                                      0x18
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT                                     0x19
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT                           0x1a
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                               0x1c
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1d
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1e
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK                                         0x00000001L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK                                        0x00000002L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK                              0x00000004L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK                                          0x00010000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK                                         0x00020000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK                               0x00040000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK                                        0x01000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK                                       0x02000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK                             0x04000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK                                 0x10000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x20000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x40000000L
+//BIF_BX0_BIF_FB_EN
+#define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT                                                                  0x0
+#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT                                                                 0x1
+#define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK                                                                    0x00000001L
+#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK                                                                   0x00000002L
+//BIF_BX0_BIF_INTR_CNTL
+#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT                                                        0x0
+#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK                                                          0x00000001L
+//BIF_BX0_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                        0x0
+#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                          0x7FFFFFFFL
+//BIF_BX0_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT                                        0x0
+#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK                                          0x7FFFFFFFL
+//BIF_BX0_MEM_TYPE_CNTL
+#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT                                                        0x0
+#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK                                                          0x00000001L
+//BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT                                                     0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT                                                  0x1
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT                                                    0x8
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK                                                       0x00000001L
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK                                                    0x00000002L
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK                                                      0x00000100L
+//BIF_BX0_NBIF_GFX_ADDR_LUT_0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_1
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_2
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_3
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_4
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_5
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_6
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_7
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_8
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_9
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_10
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_11
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_12
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_13
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_14
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_15
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
+#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
+//BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
+#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
+//BIF_BX0_BIF_RB_CNTL
+#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT                                                                 0x0
+#define BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT                                                                   0x1
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT                                                     0x8
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT                                                      0x9
+#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT                                                               0x11
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT                                                      0x1a
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT                                                          0x1d
+#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT                                                     0x1e
+#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT                                                       0x1f
+#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK                                                                   0x00000001L
+#define BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK                                                                     0x0000003EL
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK                                                       0x00000100L
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK                                                        0x00003E00L
+#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK                                                                 0x00020000L
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK                                                        0x1C000000L
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK                                                            0x20000000L
+#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK                                                       0x40000000L
+#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK                                                         0x80000000L
+//BIF_BX0_BIF_RB_BASE
+#define BIF_BX0_BIF_RB_BASE__ADDR__SHIFT                                                                      0x0
+#define BIF_BX0_BIF_RB_BASE__ADDR_MASK                                                                        0xFFFFFFFFL
+//BIF_BX0_BIF_RB_RPTR
+#define BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT                                                                    0x2
+#define BIF_BX0_BIF_RB_RPTR__OFFSET_MASK                                                                      0x0003FFFCL
+//BIF_BX0_BIF_RB_WPTR
+#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT                                                           0x0
+#define BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT                                                                    0x2
+#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK                                                             0x00000001L
+#define BIF_BX0_BIF_RB_WPTR__OFFSET_MASK                                                                      0x0003FFFCL
+//BIF_BX0_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK                                                                0x000000FFL
+//BIF_BX0_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT                                                              0x2
+#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK                                                                0xFFFFFFFCL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1:1
+//BIF_BX_PF0_BIF_BME_STATUS
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                                      0x0
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                                0x10
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                                        0x00000001L
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                                  0x00010000L
+//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                                0x0
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                             0x1
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                                0x2
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                                    0x3
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                          0x10
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                                       0x11
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                          0x12
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                              0x13
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                                  0x00000001L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                               0x00000002L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                                  0x00000004L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                                      0x00000008L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                            0x00010000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                                         0x00020000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                            0x00040000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                                0x00080000L
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT          0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK            0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT            0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK              0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT                      0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT                    0x1
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT                    0x8
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK                        0x00000001L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK                      0x00000002L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK                      0x000FFF00L
+//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                                    0x0
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                                      0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                                    0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                                      0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT                          0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                            0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT                0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK                  0x00000001L
+//BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT                                                         0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT                                                         0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT                                                         0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT                                                         0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT                                                         0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT                                                         0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT                                                         0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT                                                         0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT                                                         0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT                                                         0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT                                                       0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT                                                       0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT                                                   0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT                                                   0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT                                                   0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT                                                   0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT                                                   0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT                                                   0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT                                                   0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT                                                   0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT                                                   0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT                                                   0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT                                                  0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT                                                  0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT                                                  0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT                                                  0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT                                                  0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT                                                  0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT                                                  0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT                                                  0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT                                                  0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT                                                  0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK                                                           0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK                                                           0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK                                                           0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK                                                           0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK                                                           0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK                                                           0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK                                                           0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK                                                           0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK                                                           0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK                                                           0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK                                                         0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK                                                         0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK                                                     0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK                                                     0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK                                                     0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK                                                     0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK                                                     0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK                                                     0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK                                                     0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK                                                     0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK                                                     0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK                                                     0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK                                                    0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK                                                    0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK                                                    0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK                                                    0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK                                                    0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK                                                    0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK                                                    0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK                                                    0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK                                                    0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK                                                    0x80000000L
+//BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT                                                    0x0
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT                                                    0x1
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT                                                    0x2
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT                                                    0x3
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT                                                    0x4
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT                                                    0x5
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT                                                    0x6
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT                                                    0x7
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT                                                    0x8
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT                                                    0x9
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT                                                  0xa
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT                                                  0xb
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT                                              0xc
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT                                              0xd
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT                                              0xe
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT                                              0xf
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT                                              0x10
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT                                              0x11
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT                                              0x12
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT                                              0x13
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT                                              0x14
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT                                              0x15
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT                                             0x16
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT                                             0x17
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT                                             0x18
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT                                             0x19
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT                                             0x1a
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT                                             0x1b
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT                                             0x1c
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT                                             0x1d
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT                                             0x1e
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT                                             0x1f
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK                                                      0x00000001L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK                                                      0x00000002L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK                                                      0x00000004L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK                                                      0x00000008L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK                                                      0x00000010L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK                                                      0x00000020L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK                                                      0x00000040L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK                                                      0x00000080L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK                                                      0x00000100L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK                                                      0x00000200L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK                                                    0x00000400L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK                                                    0x00000800L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK                                                0x00001000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK                                                0x00002000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK                                                0x00004000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK                                                0x00008000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK                                                0x00010000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK                                                0x00020000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK                                                0x00040000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK                                                0x00080000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK                                                0x00100000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK                                                0x00200000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK                                               0x00400000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK                                               0x00800000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK                                               0x01000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK                                               0x02000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK                                               0x04000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK                                               0x08000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK                                               0x10000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK                                               0x20000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK                                               0x40000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK                                               0x80000000L
+//BIF_BX_PF0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                              0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                              0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                              0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                              0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                              0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                              0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                              0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                              0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                              0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                              0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                            0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                            0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                                        0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                                        0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                                        0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                                        0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                                        0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                                        0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                                        0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                                        0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                                        0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                                        0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                                       0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                                       0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                                       0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                                       0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                                       0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                                       0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                                       0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                                       0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                                       0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                                       0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                                0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                                0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                                0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                                0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                                0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                                0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                                0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                                0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                                0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                                0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                              0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                              0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                                          0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                                          0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                                          0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                                          0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                                          0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                                          0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                                          0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                                          0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                                          0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                                          0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                                         0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                                         0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                                         0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                                         0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                                         0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                                         0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                                         0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                                         0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                                         0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                                         0x80000000L
+//BIF_BX_PF0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                             0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                             0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                             0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                             0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                             0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                             0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                             0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                             0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                             0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                             0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                           0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                           0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                                       0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                                       0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                                       0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                                       0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                                       0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                                       0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                                       0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                                       0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                                       0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                                       0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                                      0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                                      0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                                      0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                                      0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                                      0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                                      0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                                      0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                                      0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                                      0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                                      0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                               0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                               0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                               0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                               0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                               0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                               0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                               0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                               0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                               0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                               0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                             0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                             0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                                         0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                                         0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                                         0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                                         0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                                         0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                                         0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                                         0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                                         0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                                         0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                                         0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                                        0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                                        0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                                        0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                                        0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                                        0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                                        0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                                        0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                                        0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                                        0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                                        0x80000000L
+//BIF_BX_PF0_BIF_TRANS_PENDING
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                            0x0
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                            0x1
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                              0x00000001L
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                              0x00000002L
+//BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                                0x0
+#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                                  0x00000001L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_1__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_1__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_2__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_2__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_1__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_1__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_2__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_2__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_1__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_1__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_2__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_2__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                                0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                  0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_1__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_1__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_2__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_2__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_1__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_1__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_2__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_2__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_1__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_1__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_2__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_2__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_1__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_1__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_2__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_2__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                                0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                  0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_1__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_1__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_2__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_2__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_1__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_1__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_2__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_2__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_1__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_1__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_2__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_2__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_1__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_1__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_2__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_2__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                                0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                  0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_1__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_1__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_2__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_2__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_1__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_1__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_2__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_2__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_1__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_1__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_2__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_2__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_1__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_1__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_2__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_2__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                                0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                  0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_1__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_1__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_2__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_2__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                               0x1
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT                                               0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT                                               0x3
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                                 0x00000001L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                                 0x00000002L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK                                                 0x00000004L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK                                                 0x00000008L
+//RCC_DEV0_EPF0_0_GFXMSIX_PBA_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_2__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_3__SHIFT                                             0x3
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_2_MASK                                               0x00000004L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_3_MASK                                               0x00000008L
+//RCC_DEV0_EPF0_0_GFXMSIX_PBA_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_2__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_3__SHIFT                                             0x3
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_2_MASK                                               0x00000004L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_3_MASK                                               0x00000008L
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+//GDC0_NGDC_SDP_PORT_CTRL
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT                                                 0x0
+#define GDC0_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT                                   0xf
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT                                               0x10
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK                                                   0x000000FFL
+#define GDC0_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN_MASK                                     0x00008000L
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK                                                 0x000F0000L
+//GDC0_SHUB_REGS_IF_CTL
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT                                0x0
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK                                  0x00000001L
+//GDC0_NGDC_SDP_PORT_CTRL_SOCCLK
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT                                   0x0
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_POOL_NUM_SOCCLK__SHIFT                                    0x8
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC0_RSV__SHIFT                                       0x10
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC5_RSV__SHIFT                                       0x14
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC6_RSV__SHIFT                                       0x18
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_H__SHIFT                                 0x1c
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK                                     0x000000FFL
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_POOL_NUM_SOCCLK_MASK                                      0x0000FF00L
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC0_RSV_MASK                                         0x000F0000L
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC5_RSV_MASK                                         0x00F00000L
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC6_RSV_MASK                                         0x0F000000L
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_H_MASK                                   0xF0000000L
+//GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC0_RSV__SHIFT                                        0x0
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC1_RSV__SHIFT                                        0x4
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC5_RSV__SHIFT                                        0x8
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC6_RSV__SHIFT                                        0xc
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC0_RSV__SHIFT                                   0x10
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC1_RSV__SHIFT                                   0x14
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC0_RSV_MASK                                          0x0000000FL
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC1_RSV_MASK                                          0x000000F0L
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC5_RSV_MASK                                          0x00000F00L
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC6_RSV_MASK                                          0x0000F000L
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC0_RSV_MASK                                     0x000F0000L
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC1_RSV_MASK                                     0x00F00000L
+//GDC0_NBIF_GFX_DOORBELL_STATUS
+#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT                                          0x0
+#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK                                            0x00000001L
+//GDC0_BIF_SDMA0_DOORBELL_RANGE
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
+//GDC0_BIF_IH_DOORBELL_RANGE
+#define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT                                                             0x2
+#define GDC0_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT                                                               0x10
+#define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET_MASK                                                               0x00000FFCL
+#define GDC0_BIF_IH_DOORBELL_RANGE__SIZE_MASK                                                                 0x001F0000L
+//GDC0_BIF_VCN0_DOORBELL_RANGE
+#define GDC0_BIF_VCN0_DOORBELL_RANGE__OFFSET__SHIFT                                                           0x2
+#define GDC0_BIF_VCN0_DOORBELL_RANGE__SIZE__SHIFT                                                             0x10
+#define GDC0_BIF_VCN0_DOORBELL_RANGE__OFFSET_MASK                                                             0x00000FFCL
+#define GDC0_BIF_VCN0_DOORBELL_RANGE__SIZE_MASK                                                               0x001F0000L
+//GDC0_BIF_RLC_DOORBELL_RANGE
+#define GDC0_BIF_RLC_DOORBELL_RANGE__OFFSET__SHIFT                                                            0x2
+#define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT                                                              0x10
+#define GDC0_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK                                                              0x00000FFCL
+#define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE_MASK                                                                0x001F0000L
+//GDC0_ATDMA_MISC_CNTL
+#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT                                                             0x0
+#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT                                                 0x1
+#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT                                                           0x2
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT                                                           0x8
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT                                                           0x10
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT                                                           0x18
+#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK                                                               0x00000001L
+#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK                                                   0x00000002L
+#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK                                                             0x0000000CL
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK                                                             0x0000FF00L
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK                                                             0x00FF0000L
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK                                                             0xFF000000L
+//GDC0_BIF_DOORBELL_FENCE_CNTL
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT                                         0x0
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT                                      0x1
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT                                      0x2
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE__SHIFT                                        0x4
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE__SHIFT                                      0x5
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE__SHIFT                                      0x6
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE__SHIFT                                      0x7
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE__SHIFT                                      0x8
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT                                  0x10
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK                                           0x00000001L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK                                        0x00000002L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK                                        0x00000004L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE_MASK                                          0x00000010L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE_MASK                                        0x00000020L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE_MASK                                        0x00000040L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE_MASK                                        0x00000080L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE_MASK                                        0x00000100L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK                                    0x00010000L
+//GDC0_S2A_MISC_CNTL
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT                                           0x0
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT                                           0x1
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT                                              0x2
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS__SHIFT                                             0x5
+#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT                                                               0x8
+#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT                                                                0xa
+#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT                                                              0xc
+#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT                                                              0x10
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS__SHIFT                                           0x18
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS__SHIFT                                           0x19
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS__SHIFT                                           0x1a
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS__SHIFT                                           0x1b
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK                                             0x00000001L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK                                             0x00000002L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK                                                0x00000004L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS_MASK                                               0x00000020L
+#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK                                                                 0x00000300L
+#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK                                                                  0x00000C00L
+#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK                                                                0x00003000L
+#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK                                                                0x000F0000L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS_MASK                                             0x01000000L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS_MASK                                             0x02000000L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS_MASK                                             0x04000000L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS_MASK                                             0x08000000L
+//GDC0_SHUBCLK_DPM_CTRL
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_MODE__SHIFT                                                        0x0
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_ENABLE__SHIFT                                                      0x1
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMAWR_QUANT__SHIFT                                                 0x2
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMARD_QUANT__SHIFT                                                 0xa
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_CLEAR__SHIFT                                                       0x12
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_MODE_MASK                                                          0x00000001L
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_ENABLE_MASK                                                        0x00000002L
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMAWR_QUANT_MASK                                                   0x000003FCL
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMARD_QUANT_MASK                                                   0x0003FC00L
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_CLEAR_MASK                                                         0x00040000L
+//GDC0_SHUBCLK_DPM_WR_WEIGHT
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_4B__SHIFT                                           0x0
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_8B__SHIFT                                           0x5
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_16B__SHIFT                                          0xa
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_32B__SHIFT                                          0xf
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_64B__SHIFT                                          0x14
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_4B_MASK                                             0x0000001FL
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_8B_MASK                                             0x000003E0L
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_16B_MASK                                            0x00007C00L
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_32B_MASK                                            0x000F8000L
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_64B_MASK                                            0x01F00000L
+//GDC0_SHUBCLK_DPM_RD_WEIGHT
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_4B__SHIFT                                           0x0
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_8B__SHIFT                                           0x5
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_16B__SHIFT                                          0xa
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_32B__SHIFT                                          0xf
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_64B__SHIFT                                          0x14
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_4B_MASK                                             0x0000001FL
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_8B_MASK                                             0x000003E0L
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_16B_MASK                                            0x00007C00L
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_32B_MASK                                            0x000F8000L
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_64B_MASK                                            0x01F00000L
+//GDC0_SHUBCLK_DPM_WR_CNT
+#define GDC0_SHUBCLK_DPM_WR_CNT__SHUBCLK_DPM_WR_COUNTER__SHIFT                                                0x0
+#define GDC0_SHUBCLK_DPM_WR_CNT__SHUBCLK_DPM_WR_COUNTER_MASK                                                  0xFFFFFFFFL
+//GDC0_SHUBCLK_DPM_RD_CNT
+#define GDC0_SHUBCLK_DPM_RD_CNT__SHUBCLK_DPM_RD_COUNTER__SHIFT                                                0x0
+#define GDC0_SHUBCLK_DPM_RD_CNT__SHUBCLK_DPM_RD_COUNTER_MASK                                                  0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect
+//OBFF_EMU_CFG_SOCCLK
+#define OBFF_EMU_CFG_SOCCLK__OBFF_EMU_DMA_EN__SHIFT                                                           0x0
+#define OBFF_EMU_CFG_SOCCLK__ATHUB_URGENT_MODE__SHIFT                                                         0x1
+#define OBFF_EMU_CFG_SOCCLK__OBFF_EMU_DMA_EN_MASK                                                             0x00000001L
+#define OBFF_EMU_CFG_SOCCLK__ATHUB_URGENT_MODE_MASK                                                           0x00000006L
+//HST_CLK0_SW0_CL0_CNTL
+#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+//HST_CLK0_SW0_CL1_CNTL
+#define HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+//HST_CLK0_SW0_CL2_CNTL
+#define HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+//HST_CLK0_SW1_CL0_CNTL
+#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+//HST_CLK0_SW1_CL1_CNTL
+#define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+//OBFF_EMU_CFG_SHUBCLK
+#define OBFF_EMU_CFG_SHUBCLK__URGENT_MERGE_CTRL0__SHIFT                                                       0x0
+#define OBFF_EMU_CFG_SHUBCLK__URGENT_MERGE_CTRL0_MASK                                                         0x00000001L
+//HST_CLK1_SW0_CL0_CNTL
+#define HST_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define HST_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define HST_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define HST_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+//OBFF_EMU_CFG_NICCLK
+//HST_CLK2_SW0_CL0_CNTL
+#define HST_CLK2_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define HST_CLK2_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define HST_CLK2_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define HST_CLK2_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+
+
+// addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk
+//GDCSOC_ERR_RSP_CNTL
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS__SHIFT                                                       0x0
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL__SHIFT                                                    0x1
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN__SHIFT                                                     0x2
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA__SHIFT                                                   0x3
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN__SHIFT                                              0x4
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN__SHIFT                                          0x5
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS_MASK                                                         0x00000001L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL_MASK                                                      0x00000002L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN_MASK                                                       0x00000004L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA_MASK                                                     0x00000008L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN_MASK                                                0x00000010L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN_MASK                                            0x00000020L
+//GDCSOC_RAS_CENTRAL_STATUS
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT                                              0x0
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT                                             0x1
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT                                              0x2
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT                                             0x3
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK                                                0x00000001L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK                                               0x00000002L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK                                                0x00000004L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK                                               0x00000008L
+//GDCSOC_RAS_LEAF0_CTRL
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+//GDCSOC_RAS_LEAF1_CTRL
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+//GDCSOC_RAS_LEAF2_CTRL
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+//GDCSOC_RAS_LEAF3_CTRL
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+//GDCSOC_RAS_LEAF4_CTRL
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+//GDCSOC_RAS_LEAF5_CTRL
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+//GDCSOC_RAS_LEAF0_STATUS
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF1_STATUS
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF2_STATUS
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF3_STATUS
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF4_STATUS
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF5_STATUS
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSHUB_ERR_RSP_CNTL
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_BYPASS__SHIFT                                                     0x0
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_ACCUM_SEL__SHIFT                                                  0x1
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_FORCE_EN__SHIFT                                                   0x2
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_FORCE_DATA__SHIFT                                                 0x3
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_STATUS_ACCUM_EN__SHIFT                                            0x4
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_DATASTATUS_ACCUM_EN__SHIFT                                        0x5
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_BYPASS_MASK                                                       0x00000001L
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_ACCUM_SEL_MASK                                                    0x00000002L
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_FORCE_EN_MASK                                                     0x00000004L
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_FORCE_DATA_MASK                                                   0x00000008L
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_STATUS_ACCUM_EN_MASK                                              0x00000010L
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_DATASTATUS_ACCUM_EN_MASK                                          0x00000020L
+//GDCSHUB_RAS_CENTRAL_STATUS
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_EgStall_det__SHIFT                                            0x0
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_ErrEvent_det__SHIFT                                           0x1
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_EgStall_det__SHIFT                                            0x2
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_ErrEvent_det__SHIFT                                           0x3
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_EgStall_det_MASK                                              0x00000001L
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_ErrEvent_det_MASK                                             0x00000002L
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_EgStall_det_MASK                                              0x00000004L
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_ErrEvent_det_MASK                                             0x00000008L
+//GDCSHUB_RAS_LEAF0_CTRL
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT                                0x0
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT                              0x1
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT                                 0x2
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT                              0x3
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT                                 0x4
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                         0x5
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT                            0x6
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT                               0xa
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT                            0xb
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK                                  0x00000001L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK                                0x00000002L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK                                   0x00000004L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK                                0x00000008L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK                                   0x00000010L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK                           0x00000020L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK                              0x00000040L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK                                 0x00000400L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK                              0x00000800L
+//GDCSHUB_RAS_LEAF1_CTRL
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT                                0x0
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT                              0x1
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT                                 0x2
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT                              0x3
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT                                 0x4
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                         0x5
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT                            0x6
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT                               0xa
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT                            0xb
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK                                  0x00000001L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK                                0x00000002L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK                                   0x00000004L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK                                0x00000008L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK                                   0x00000010L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK                           0x00000020L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK                              0x00000040L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK                                 0x00000400L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK                              0x00000800L
+//GDCSHUB_RAS_LEAF2_CTRL
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT                                0x0
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT                              0x1
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT                                 0x2
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT                              0x3
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT                                 0x4
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                         0x5
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT                            0x6
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT                               0xa
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT                            0xb
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK                                  0x00000001L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK                                0x00000002L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK                                   0x00000004L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK                                0x00000008L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK                                   0x00000010L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK                           0x00000020L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK                              0x00000040L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK                                 0x00000400L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK                              0x00000800L
+//GDCSHUB_RAS_LEAF3_CTRL
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT                                0x0
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT                              0x1
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT                                 0x2
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT                              0x3
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT                                 0x4
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                         0x5
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT                            0x6
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT                               0xa
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT                            0xb
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK                                  0x00000001L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK                                0x00000002L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK                                   0x00000004L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK                                0x00000008L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK                                   0x00000010L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK                           0x00000020L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK                              0x00000040L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK                                 0x00000400L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK                              0x00000800L
+//GDCSHUB_RAS_LEAF0_STATUS
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT                              0x0
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT                              0x1
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT                              0x2
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT                         0x8
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                    0x9
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT                         0xa
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                    0xb
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK                                0x00000001L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK                                0x00000002L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK                                0x00000004L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK                           0x00000100L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK                      0x00000200L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK                           0x00000400L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK                      0x00000800L
+//GDCSHUB_RAS_LEAF1_STATUS
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT                              0x0
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT                              0x1
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT                              0x2
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT                         0x8
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                    0x9
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT                         0xa
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                    0xb
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK                                0x00000001L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK                                0x00000002L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK                                0x00000004L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK                           0x00000100L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK                      0x00000200L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK                           0x00000400L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK                      0x00000800L
+//GDCSHUB_RAS_LEAF2_STATUS
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT                              0x0
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT                              0x1
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT                              0x2
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT                         0x8
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                    0x9
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT                         0xa
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                    0xb
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK                                0x00000001L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK                                0x00000002L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK                                0x00000004L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK                           0x00000100L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK                      0x00000200L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK                           0x00000400L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK                      0x00000800L
+//GDCSHUB_RAS_LEAF3_STATUS
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT                              0x0
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT                              0x1
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT                              0x2
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT                         0x8
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                    0x9
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT                         0xa
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                    0xb
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK                                0x00000001L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK                                0x00000002L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK                                0x00000004L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK                           0x00000100L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK                      0x00000200L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK                           0x00000400L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK                      0x00000800L
+//GDCNIC_ERR_RSP_CNTL
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_BYPASS__SHIFT                                                       0x0
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_ACCUM_SEL__SHIFT                                                    0x1
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_FORCE_EN__SHIFT                                                     0x2
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_FORCE_DATA__SHIFT                                                   0x3
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_STATUS_ACCUM_EN__SHIFT                                              0x4
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_DATASTATUS_ACCUM_EN__SHIFT                                          0x5
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_BYPASS_MASK                                                         0x00000001L
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_ACCUM_SEL_MASK                                                      0x00000002L
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_FORCE_EN_MASK                                                       0x00000004L
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_FORCE_DATA_MASK                                                     0x00000008L
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_STATUS_ACCUM_EN_MASK                                                0x00000010L
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_DATASTATUS_ACCUM_EN_MASK                                            0x00000020L
+//GDCNIC_RAS_CENTRAL_STATUS
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_L2C_EgStall_det__SHIFT                                              0x0
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_L2C_ErrEvent_det__SHIFT                                             0x1
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_C2L_EgStall_det__SHIFT                                              0x2
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_C2L_ErrEvent_det__SHIFT                                             0x3
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_L2C_EgStall_det_MASK                                                0x00000001L
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_L2C_ErrEvent_det_MASK                                               0x00000002L
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_C2L_EgStall_det_MASK                                                0x00000004L
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_C2L_ErrEvent_det_MASK                                               0x00000008L
+//GDCNIC_RAS_LEAF0_CTRL
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+//GDCNIC_RAS_LEAF1_CTRL
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+//GDCNIC_RAS_LEAF2_CTRL
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+//GDCNIC_RAS_LEAF0_STATUS
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCNIC_RAS_LEAF1_STATUS
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCNIC_RAS_LEAF2_STATUS
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+
+
+// addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC
+//SHUB_PF_FLR_RST
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT                                                              0x0
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT                                                              0x1
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT                                                              0x2
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT                                                              0x3
+#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT                                                              0x4
+#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT                                                              0x5
+#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT                                                              0x6
+#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT                                                              0x7
+#define SHUB_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT                                                              0x8
+#define SHUB_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT                                                              0x9
+#define SHUB_PF_FLR_RST__DEV2_PF0_FLR_RST__SHIFT                                                              0x10
+#define SHUB_PF_FLR_RST__DEV2_PF1_FLR_RST__SHIFT                                                              0x11
+#define SHUB_PF_FLR_RST__DEV2_PF2_FLR_RST__SHIFT                                                              0x12
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK                                                                0x00000001L
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK                                                                0x00000002L
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK                                                                0x00000004L
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK                                                                0x00000008L
+#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK                                                                0x00000010L
+#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK                                                                0x00000020L
+#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK                                                                0x00000040L
+#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK                                                                0x00000080L
+#define SHUB_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK                                                                0x00000100L
+#define SHUB_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK                                                                0x00000200L
+#define SHUB_PF_FLR_RST__DEV2_PF0_FLR_RST_MASK                                                                0x00010000L
+#define SHUB_PF_FLR_RST__DEV2_PF1_FLR_RST_MASK                                                                0x00020000L
+#define SHUB_PF_FLR_RST__DEV2_PF2_FLR_RST_MASK                                                                0x00040000L
+//SHUB_GFX_DRV_VPU_RST
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT                                                        0x0
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK                                                          0x00000001L
+//SHUB_LINK_RESET
+#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT                                                                 0x0
+#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT                                                                 0x1
+#define SHUB_LINK_RESET__LINK_P2_RESET__SHIFT                                                                 0x2
+#define SHUB_LINK_RESET__LINK_P3_RESET__SHIFT                                                                 0x3
+#define SHUB_LINK_RESET__LINK_P0_RESET_MASK                                                                   0x00000001L
+#define SHUB_LINK_RESET__LINK_P1_RESET_MASK                                                                   0x00000002L
+#define SHUB_LINK_RESET__LINK_P2_RESET_MASK                                                                   0x00000004L
+#define SHUB_LINK_RESET__LINK_P3_RESET_MASK                                                                   0x00000008L
+//SHUB_HARD_RST_CTRL
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT                                                               0x0
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT                                                               0x1
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT                                                               0x2
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT                                                          0x4
+#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT                                                          0x5
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK                                                                 0x00000001L
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK                                                                 0x00000002L
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK                                                                 0x00000004L
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK                                                            0x00000010L
+#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK                                                            0x00000020L
+//SHUB_SOFT_RST_CTRL
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT                                                               0x0
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT                                                               0x1
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT                                                               0x2
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT                                                          0x4
+#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT                                                          0x5
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK                                                                 0x00000001L
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK                                                                 0x00000002L
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK                                                                 0x00000004L
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK                                                            0x00000010L
+#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK                                                            0x00000020L
+//SHUB_SDP_PORT_RST
+#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT                                                   0x1
+#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT                                                      0x2
+#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT                                                      0x3
+#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT                                                 0x4
+#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT                                                         0x6
+#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST__SHIFT                                                        0x7
+#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT                                                        0x8
+#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT                                                        0x9
+#define SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT                                                                0x18
+#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK                                                     0x00000002L
+#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK                                                        0x00000004L
+#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK                                                        0x00000008L
+#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK                                                   0x00000010L
+#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK                                                           0x00000040L
+#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST_MASK                                                          0x00000080L
+#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK                                                          0x00000100L
+#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK                                                          0x00000200L
+#define SHUB_SDP_PORT_RST__SION_AON_RST_MASK                                                                  0x01000000L
+
+
+
+
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+//BIF_CFG_DEV0_RC0_VENDOR_ID
+#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV0_RC0_DEVICE_ID
+#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV0_RC0_COMMAND
+#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT                                                             0x1
+#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT                                                        0x2
+#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                0x6
+#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT                                                              0x8
+#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT                                                              0xa
+#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK                                                                0x0001L
+#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK                                                               0x0002L
+#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK                                                          0x0004L
+#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK                                                            0x0080L
+#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK                                                                0x0100L
+#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK                                                                0x0400L
+//BIF_CFG_DEV0_RC0_STATUS
+#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT                                                            0x3
+#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT                                                              0x4
+#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT                                                            0x5
+#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                              0x8
+#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                 0xd
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK                                                              0x0008L
+#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK                                                                0x0010L
+#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK                                                              0x0020L
+#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                0x0100L
+#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK                                                           0x0600L
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                   0x2000L
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                   0x4000L
+#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK                                                   0x8000L
+//BIF_CFG_DEV0_RC0_REVISION_ID
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK                                                       0x0FL
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK                                                       0xF0L
+//BIF_CFG_DEV0_RC0_PROG_INTERFACE
+#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_RC0_SUB_CLASS
+#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK                                                            0xFFL
+//BIF_CFG_DEV0_RC0_BASE_CLASS
+#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK                                                          0xFFL
+//BIF_CFG_DEV0_RC0_CACHE_LINE
+#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                     0xFFL
+//BIF_CFG_DEV0_RC0_LATENCY
+#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK                                                          0xFFL
+//BIF_CFG_DEV0_RC0_HEADER
+#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK                                                             0x7FL
+#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK                                                             0x80L
+//BIF_CFG_DEV0_RC0_BIST
+#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT                                                               0x6
+#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT                                                                0x7
+#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK                                                                 0x0FL
+#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK                                                                 0x40L
+#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK                                                                  0x80L
+//BIF_CFG_DEV0_RC0_BASE_ADDR_1
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_BASE_ADDR_2
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                               0x18
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                           0x0000FF00L
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                             0x00FF0000L
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                       0xc
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                     0x000FL
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                    0x0F00L
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                         0xF000L
+//BIF_CFG_DEV0_RC0_SECONDARY_STATUS
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                           0x7
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                    0x8
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                               0x9
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                         0xb
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                       0xc
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                       0xd
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                       0xe
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                             0x0080L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                      0x0100L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                 0x0600L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                           0x0800L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                         0x1000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                         0x2000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                         0x4000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                         0x8000L
+//BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                0x4
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                0x10
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                               0x14
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                   0x0000000FL
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                  0x0000FFF0L
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                          0x4
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                             0x0000000FL
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                            0x0000FFF0L
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC0_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                              0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                              0x10
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                0xFFFF0000L
+//BIF_CFG_DEV0_RC0_CAP_PTR
+#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK                                                                0xFFL
+//BIF_CFG_DEV0_RC0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_RC0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                    0xFFL
+//BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                      0x1
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                        0x8
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                      0x9
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                         0xa
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                    0xb
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                        0x0002L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                              0x0020L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                          0x0100L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                        0x0200L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                           0x0400L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                      0x0800L
+//BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                  0x01L
+//BIF_CFG_DEV0_RC0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV0_RC0_PMI_CAP
+#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT                                                            0x3
+#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                  0x4
+#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT                                                           0x9
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT                                                          0xb
+#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK                                                                0x0007L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK                                                              0x0008L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                    0x0010L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK                                                            0x01C0L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK                                                             0x0200L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK                                                             0x0400L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK                                                            0xF800L
+//BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                0x16
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                   0x17
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                     0x18
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                    0x00000003L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                  0x00000008L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK                                                         0x00000100L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                    0x00001E00L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                     0x00006000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                     0x00008000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                  0x00400000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                     0x00800000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                       0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_RC0_PCIE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK                                                               0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK                                                           0x00F0L
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                      0x0100L
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                       0x3E00L
+//BIF_CFG_DEV0_RC0_DEVICE_CAP
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                      0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                            0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                             0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                          0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                       0x1c
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                        0x00000018L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK                                                        0x00000020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                              0x000001C0L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                               0x00000E00L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                            0x00008000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK                                                         0x10000000L
+//BIF_CFG_DEV0_RC0_DEVICE_CNTL
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                  0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                      0xb
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                            0xc
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                              0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                   0x00E0L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                    0x0100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                    0x0200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                    0x0400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                        0x0800L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                              0x7000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                0x8000L
+//BIF_CFG_DEV0_RC0_DEVICE_STATUS
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                      0x2
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                              0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                    0x0002L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK                                                        0x0004L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                0x0020L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                    0x0040L
+//BIF_CFG_DEV0_RC0_LINK_CAP
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                    0xc
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                              0x12
+#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                         0x13
+#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                            0x15
+#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                         0x16
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT                                                         0x18
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK                                                            0x0000000FL
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK                                                            0x000003F0L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK                                                            0x00000C00L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                      0x00007000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                       0x00038000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                0x00040000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                           0x00080000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                           0x00100000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                              0x00200000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                           0x00400000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK                                                           0xFF000000L
+//BIF_CFG_DEV0_RC0_LINK_CNTL
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                   0x6
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                          0xb
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                              0xe
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK                                                           0x0003L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                     0x0040L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                            0x0100L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                            0x0400L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                            0x0800L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                0xC000L
+//BIF_CFG_DEV0_RC0_LINK_STATUS
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                            0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT                                                    0xb
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                        0xe
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                        0xf
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                 0x000FL
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                              0x03F0L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK                                                      0x0800L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                     0x1000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK                                                          0x2000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                          0x4000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                          0x8000L
+//BIF_CFG_DEV0_RC0_SLOT_CAP
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                              0x1
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                              0x3
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                               0x4
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                     0x6
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                0xf
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                      0x12
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                   0x13
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                   0x00000001L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                0x00000002L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                    0x00000004L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                0x00000008L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                 0x00000010L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                      0x00000020L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                       0x00000040L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                  0x00007F80L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                  0x00018000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                         0x00020000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                        0x00040000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                     0xFFF80000L
+//BIF_CFG_DEV0_RC0_SLOT_CNTL
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                              0x2
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                         0x3
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                0x6
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                0xa
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                         0xb
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                0xc
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                        0xd
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                               0x0001L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                0x0004L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                           0x0008L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                            0x0010L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                  0x00C0L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                   0x0300L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                  0x0400L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                           0x0800L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                          0x2000L
+//BIF_CFG_DEV0_RC0_SLOT_STATUS
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                               0x1
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                               0x2
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                          0x3
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                0x4
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                            0x6
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                     0x7
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                0x0001L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                 0x0004L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                            0x0008L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                              0x0040L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                       0x0080L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                   0x0100L
+//BIF_CFG_DEV0_RC0_ROOT_CNTL
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                               0x2
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                 0x0004L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                           0x0010L
+//BIF_CFG_DEV0_RC0_ROOT_CAP
+#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                               0x0001L
+//BIF_CFG_DEV0_RC0_ROOT_STATUS
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT                                                       0x10
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT                                                      0x11
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK                                                         0x00010000L
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK                                                        0x00020000L
+//BIF_CFG_DEV0_RC0_DEVICE_CAP2
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                        0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                         0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                       0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                       0x7
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                           0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                        0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                    0xb
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                               0xc
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                    0xe
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                  0x10
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                  0x11
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                   0x12
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                     0x14
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                     0x15
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                         0x16
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                   0x18
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                    0x1f
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                        0x0000000FL
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                          0x00000010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                           0x00000020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                         0x00000080L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                             0x00000200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                          0x00000400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                      0x00000800L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                 0x00003000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                      0x0000C000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                     0x000C0000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                       0x00100000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                           0x00C00000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                     0x03000000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                      0x04000000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                      0x80000000L
+//BIF_CFG_DEV0_RC0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                               0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                             0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                        0x7
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                              0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                           0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                    0xb
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                    0xc
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                         0xd
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                 0x000FL
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                 0x0020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                               0x0040L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                          0x0080L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                0x0100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                             0x0200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                      0x0800L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                      0x1000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK                                                           0x6000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                       0x8000L
+//BIF_CFG_DEV0_RC0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK                                                        0xFFFFL
+//BIF_CFG_DEV0_RC0_LINK_CAP2
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                               0x1
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                0x8
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                          0x17
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                          0x18
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                      0x1f
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                 0x000000FEL
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                  0x00000100L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                             0x007F0000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                            0x00800000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                            0x01000000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK                                                        0x80000000L
+//BIF_CFG_DEV0_RC0_LINK_CNTL2
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                       0x5
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                             0x6
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                              0xa
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                    0xb
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                             0xc
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                   0x000FL
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                         0x0020L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                               0x0040L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK                                                         0x0380L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                0x0400L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                      0x0800L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                               0xF000L
+//BIF_CFG_DEV0_RC0_LINK_STATUS2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                       0x1
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                 0x2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                 0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                   0x5
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                               0x6
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                               0x7
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                            0x8
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                              0x0001L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                         0x0002L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                   0x0004L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                   0x0008L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                   0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                     0x0020L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                 0x0080L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                              0x0300L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                     0x7000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                              0x8000L
+//BIF_CFG_DEV0_RC0_SLOT_CAP2
+#define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SLOT_CNTL2
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK                                                            0xFFFFL
+//BIF_CFG_DEV0_RC0_SLOT_STATUS2
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK                                                          0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV0_RC0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                            0x9
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK                                                            0x0001L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                     0x000EL
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                      0x0070L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                         0x0100L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                              0x0200L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                               0x0400L
+//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                              0x2
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                0xFFFFFFFCL
+//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK                                                          0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                  0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                    0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                            0xFFFFL
+//BIF_CFG_DEV0_RC0_SSID_CAP_LIST
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_RC0_SSID_CAP
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                        0x10
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK                                                          0xFFFF0000L
+//BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_RC0_MSI_MAP_CAP
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD__SHIFT                                                             0x1
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                         0xb
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN_MASK                                                                 0x0001L
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD_MASK                                                               0x0002L
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE_MASK                                                           0xF800L
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                            0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                               0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                              0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                              0x4
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                0x8
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                              0xa
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                             0x00000007L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                0x00000070L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                  0x00000300L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                0x00000C00L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                    0x18
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                               0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                      0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                              0x1
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                            0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                0x000EL
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                        0x0001L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x007F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x003F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                        0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                     0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                         0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                        0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                       0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                  0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                 0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                 0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                        0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                         0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                    0x1a
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                          0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                       0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                          0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                           0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                        0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                         0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                          0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                         0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                   0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                   0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                   0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                          0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                           0x02000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                      0x04000000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                         0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                            0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                             0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                           0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                            0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                           0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                     0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                      0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                     0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                     0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                            0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                             0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                        0x1a
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                              0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                           0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                              0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                               0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                        0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                            0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                             0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                              0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                             0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                       0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                        0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                       0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                              0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                               0x02000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                          0x04000000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                    0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                    0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                     0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                              0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                  0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                   0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                    0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                   0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                             0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                              0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                             0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                             0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                    0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                     0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                0x1a
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                      0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                   0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                      0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                       0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                     0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                      0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                     0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                               0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                               0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                               0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                      0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                       0x02000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                  0x04000000L
+//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                         0x7
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                             0xc
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                            0xd
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                            0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                           0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                               0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                              0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                       0x00008000L
+//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                              0x6
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                             0x7
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                0xd
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                         0xe
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                         0xf
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                               0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                           0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                           0x00008000L
+//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                         0x7
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                     0x9
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                      0xa
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                 0xb
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                         0xc
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                            0x0000001FL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                           0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                            0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                       0x00000200L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                        0x00000400L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                   0x00000800L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                           0x00001000L
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                           0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                             0x00000004L
+//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                      0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                 0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                            0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                               0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                    0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                     0x1b
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                        0x00000002L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                   0x00000004L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                              0x00000008L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                   0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                       0xF8000000L
+//BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                    0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                      0xFFFF0000L
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                   0x00000002L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                  0x0000FFFFL
+//BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                            0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                            0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                         0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                              0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                           0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                              0x0002L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                              0x0004L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                           0x0008L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                               0x0010L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                0x0020L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                             0x0040L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                        0xFF00L
+//BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                        0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                     0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                          0x0004L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                       0x0008L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                         0x0040L
+//BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                    0x0
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                    0x1f
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                      0x007FFFFFL
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                      0x80000000L
+//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                  0x007FFFFFL
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_RC0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                            0x1
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                    0x00000001L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                              0x00000002L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                              0x00000004L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                              0x00000008L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                0x00000010L
+//BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT          0x0
+#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK            0x0000FFFFL
+//BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                   0x0
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                     0x0001L
+//BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                        0x0
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                               0x1
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                          0x0001L
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                 0x0002L
+//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+//BIF_CFG_DEV1_RC0_VENDOR_ID
+#define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV1_RC0_DEVICE_ID
+#define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV1_RC0_COMMAND
+#define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN__SHIFT                                                              0x0
+#define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN__SHIFT                                                             0x1
+#define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN__SHIFT                                                        0x2
+#define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN__SHIFT                                                         0x5
+#define BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                0x6
+#define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING__SHIFT                                                          0x7
+#define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN__SHIFT                                                              0x8
+#define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN__SHIFT                                                          0x9
+#define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS__SHIFT                                                              0xa
+#define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN_MASK                                                                0x0001L
+#define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN_MASK                                                               0x0002L
+#define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN_MASK                                                          0x0004L
+#define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN_MASK                                                           0x0020L
+#define BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                  0x0040L
+#define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING_MASK                                                            0x0080L
+#define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN_MASK                                                                0x0100L
+#define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN_MASK                                                            0x0200L
+#define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS_MASK                                                                0x0400L
+//BIF_CFG_DEV1_RC0_STATUS
+#define BIF_CFG_DEV1_RC0_STATUS__IMMEDIATE_READINESS__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS__SHIFT                                                            0x3
+#define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST__SHIFT                                                              0x4
+#define BIF_CFG_DEV1_RC0_STATUS__PCI_66_CAP__SHIFT                                                            0x5
+#define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                     0x7
+#define BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                              0x8
+#define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING__SHIFT                                                         0x9
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                   0xb
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                 0xc
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                 0xd
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                 0xe
+#define BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                 0xf
+#define BIF_CFG_DEV1_RC0_STATUS__IMMEDIATE_READINESS_MASK                                                     0x0001L
+#define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS_MASK                                                              0x0008L
+#define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST_MASK                                                                0x0010L
+#define BIF_CFG_DEV1_RC0_STATUS__PCI_66_CAP_MASK                                                              0x0020L
+#define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE_MASK                                                       0x0080L
+#define BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                0x0100L
+#define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING_MASK                                                           0x0600L
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                     0x0800L
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                   0x1000L
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                   0x2000L
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                   0x4000L
+#define BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED_MASK                                                   0x8000L
+//BIF_CFG_DEV1_RC0_REVISION_ID
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                     0x4
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID_MASK                                                       0x0FL
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID_MASK                                                       0xF0L
+//BIF_CFG_DEV1_RC0_PROG_INTERFACE
+#define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                  0xFFL
+//BIF_CFG_DEV1_RC0_SUB_CLASS
+#define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS_MASK                                                            0xFFL
+//BIF_CFG_DEV1_RC0_BASE_CLASS
+#define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS_MASK                                                          0xFFL
+//BIF_CFG_DEV1_RC0_CACHE_LINE
+#define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                     0xFFL
+//BIF_CFG_DEV1_RC0_LATENCY
+#define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER_MASK                                                          0xFFL
+//BIF_CFG_DEV1_RC0_HEADER
+#define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE__SHIFT                                                           0x7
+#define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE_MASK                                                             0x7FL
+#define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE_MASK                                                             0x80L
+//BIF_CFG_DEV1_RC0_BIST
+#define BIF_CFG_DEV1_RC0_BIST__BIST_COMP__SHIFT                                                               0x0
+#define BIF_CFG_DEV1_RC0_BIST__BIST_STRT__SHIFT                                                               0x6
+#define BIF_CFG_DEV1_RC0_BIST__BIST_CAP__SHIFT                                                                0x7
+#define BIF_CFG_DEV1_RC0_BIST__BIST_COMP_MASK                                                                 0x0FL
+#define BIF_CFG_DEV1_RC0_BIST__BIST_STRT_MASK                                                                 0x40L
+#define BIF_CFG_DEV1_RC0_BIST__BIST_CAP_MASK                                                                  0x80L
+//BIF_CFG_DEV1_RC0_BASE_ADDR_1
+#define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_BASE_ADDR_2
+#define BIF_CFG_DEV1_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC0_BASE_ADDR_2__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                         0x8
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                           0x10
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                               0x18
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                             0x000000FFL
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                           0x0000FF00L
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                             0x00FF0000L
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                 0xFF000000L
+//BIF_CFG_DEV1_RC0_IO_BASE_LIMIT
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                        0x4
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                  0x8
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                       0xc
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                     0x000FL
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                    0x0F00L
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                         0xF000L
+//BIF_CFG_DEV1_RC0_SECONDARY_STATUS
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                  0x5
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                           0x7
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                    0x8
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                               0x9
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                         0xb
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                       0xc
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                       0xd
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                       0xe
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                       0xf
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                    0x0020L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                             0x0080L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                      0x0100L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                 0x0600L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                           0x0800L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                         0x1000L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                         0x2000L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                         0x4000L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                         0x8000L
+//BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                0x4
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                0x10
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                               0x14
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                   0x0000000FL
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                  0x0000FFF0L
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                          0x4
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                          0x10
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                         0x14
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                             0x0000000FL
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                            0x0000FFF0L
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                            0x000F0000L
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                           0xFFF00000L
+//BIF_CFG_DEV1_RC0_PREF_BASE_UPPER
+#define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                              0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                              0x10
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                0xFFFF0000L
+//BIF_CFG_DEV1_RC0_CAP_PTR
+#define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR__SHIFT                                                              0x0
+#define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR_MASK                                                                0xFFL
+//BIF_CFG_DEV1_RC0_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_INTERRUPT_LINE
+#define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                  0xFFL
+//BIF_CFG_DEV1_RC0_INTERRUPT_PIN
+#define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                    0xFFL
+//BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                      0x1
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                       0x3
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                      0x4
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                            0x5
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                          0x6
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                  0x7
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                        0x8
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                      0x9
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                         0xa
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                    0xb
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                        0x0002L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                         0x0008L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                        0x0010L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                              0x0020L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                            0x0040L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                    0x0080L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                          0x0100L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                        0x0200L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                           0x0400L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                      0x0800L
+//BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                  0x01L
+//BIF_CFG_DEV1_RC0_PMI_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV1_RC0_PMI_CAP
+#define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION__SHIFT                                                              0x0
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK__SHIFT                                                            0x3
+#define BIF_CFG_DEV1_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                  0x4
+#define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                    0x5
+#define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT__SHIFT                                                          0x6
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT__SHIFT                                                           0x9
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT__SHIFT                                                           0xa
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT__SHIFT                                                          0xb
+#define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION_MASK                                                                0x0007L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK_MASK                                                              0x0008L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                    0x0010L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                      0x0020L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT_MASK                                                            0x01C0L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT_MASK                                                             0x0200L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT_MASK                                                             0x0400L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT_MASK                                                            0xF800L
+//BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                0x3
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                       0x8
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                  0x9
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                   0xd
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                   0xf
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                0x16
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                   0x17
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                     0x18
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                    0x00000003L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                  0x00000008L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN_MASK                                                         0x00000100L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                    0x00001E00L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                     0x00006000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                     0x00008000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                  0x00400000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                     0x00800000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                       0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV1_RC0_PCIE_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                         0x4
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                     0x9
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION_MASK                                                               0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE_MASK                                                           0x00F0L
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                      0x0100L
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                       0x3E00L
+//BIF_CFG_DEV1_RC0_DEVICE_CAP
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                      0x3
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                      0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                            0x6
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                             0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                          0xf
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                       0x1c
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                 0x00000007L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                        0x00000018L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG_MASK                                                        0x00000020L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                              0x000001C0L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                               0x00000E00L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                            0x00008000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE_MASK                                                         0x10000000L
+//BIF_CFG_DEV1_RC0_DEVICE_CNTL
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                 0x1
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                 0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                  0x8
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                  0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                  0xa
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                      0xb
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                            0xc
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                              0xf
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                   0x0002L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                     0x0010L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                   0x00E0L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                    0x0100L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                    0x0200L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                    0x0400L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                        0x0800L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                              0x7000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                0x8000L
+//BIF_CFG_DEV1_RC0_DEVICE_STATUS
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                  0x1
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                      0x2
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                   0x3
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR__SHIFT                                                        0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                              0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                  0x6
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR_MASK                                                         0x0001L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                    0x0002L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR_MASK                                                        0x0004L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED_MASK                                                     0x0008L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR_MASK                                                          0x0010L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                0x0020L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                    0x0040L
+//BIF_CFG_DEV1_RC0_LINK_CAP
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH__SHIFT                                                          0x4
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                    0xc
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                     0xf
+#define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                              0x12
+#define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                         0x13
+#define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                         0x14
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                            0x15
+#define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                         0x16
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER__SHIFT                                                         0x18
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED_MASK                                                            0x0000000FL
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH_MASK                                                            0x000003F0L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT_MASK                                                            0x00000C00L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                      0x00007000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                       0x00038000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                0x00040000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                           0x00080000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                           0x00100000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                              0x00200000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                           0x00400000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER_MASK                                                           0xFF000000L
+//BIF_CFG_DEV1_RC0_LINK_CNTL
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                  0x3
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS__SHIFT                                                           0x4
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                       0x5
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                   0x6
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                      0x7
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                          0xb
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                              0xe
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL_MASK                                                           0x0003L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                    0x0008L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS_MASK                                                             0x0010L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK_MASK                                                         0x0020L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                     0x0040L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC_MASK                                                        0x0080L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                            0x0100L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                            0x0400L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                            0x0800L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                0xC000L
+//BIF_CFG_DEV1_RC0_LINK_STATUS
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                            0x4
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING__SHIFT                                                    0xb
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                   0xc
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE__SHIFT                                                        0xd
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                        0xe
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                        0xf
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                 0x000FL
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                              0x03F0L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING_MASK                                                      0x0800L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                     0x1000L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE_MASK                                                          0x2000L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                          0x4000L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                          0x8000L
+//BIF_CFG_DEV1_RC0_SLOT_CAP
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                              0x1
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                  0x2
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                              0x3
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                               0x4
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                    0x5
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                     0x6
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                0x7
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                0xf
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                       0x11
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                      0x12
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                   0x13
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                   0x00000001L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                0x00000002L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                    0x00000004L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                0x00000008L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                 0x00000010L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                      0x00000020L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                       0x00000040L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                  0x00007F80L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                  0x00018000L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                         0x00020000L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                        0x00040000L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                     0xFFF80000L
+//BIF_CFG_DEV1_RC0_SLOT_CNTL
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                              0x2
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                         0x3
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                0x6
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                 0x8
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                0xa
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                         0xb
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                0xc
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                        0xd
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                               0x0001L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                0x0004L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                           0x0008L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                            0x0010L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                  0x00C0L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                   0x0300L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                  0x0400L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                           0x0800L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                  0x1000L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                          0x2000L
+//BIF_CFG_DEV1_RC0_SLOT_STATUS
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                               0x1
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                               0x2
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                          0x3
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                0x4
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                 0x5
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                            0x6
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                     0x7
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                 0x8
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                0x0001L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                 0x0002L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                 0x0004L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                            0x0008L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                  0x0010L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                   0x0020L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                              0x0040L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                       0x0080L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                   0x0100L
+//BIF_CFG_DEV1_RC0_ROOT_CNTL
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                               0x2
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                  0x0001L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                 0x0004L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                           0x0010L
+//BIF_CFG_DEV1_RC0_ROOT_CAP
+#define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                               0x0001L
+//BIF_CFG_DEV1_RC0_ROOT_STATUS
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS__SHIFT                                                       0x10
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING__SHIFT                                                      0x11
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS_MASK                                                         0x00010000L
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING_MASK                                                        0x00020000L
+//BIF_CFG_DEV1_RC0_DEVICE_CAP2
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                      0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                        0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                         0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                       0x6
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                       0x7
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                       0x8
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                           0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                        0xa
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                    0xb
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                               0xc
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                    0xe
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                  0x10
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                  0x11
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                   0x12
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                     0x14
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                     0x15
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                         0x16
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                   0x18
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                    0x1a
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                    0x1f
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                        0x0000000FL
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                          0x00000010L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                           0x00000020L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                         0x00000040L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                         0x00000080L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                         0x00000100L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                             0x00000200L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                          0x00000400L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                      0x00000800L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                 0x00003000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                      0x0000C000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                    0x00010000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                    0x00020000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                     0x000C0000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                       0x00100000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                       0x00200000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                           0x00C00000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                     0x03000000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                      0x04000000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                      0x80000000L
+//BIF_CFG_DEV1_RC0_DEVICE_CNTL2
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                 0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                               0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                             0x6
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                        0x7
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                              0x8
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                           0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN__SHIFT                                                          0xa
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                    0xb
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                    0xc
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                         0xd
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                     0xf
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                 0x000FL
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                   0x0010L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                 0x0020L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                               0x0040L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                          0x0080L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                0x0100L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                             0x0200L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN_MASK                                                            0x0400L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                      0x0800L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                      0x1000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN_MASK                                                           0x6000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                       0x8000L
+//BIF_CFG_DEV1_RC0_DEVICE_STATUS2
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED_MASK                                                        0xFFFFL
+//BIF_CFG_DEV1_RC0_LINK_CAP2
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                               0x1
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                0x8
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                           0x10
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                          0x17
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                          0x18
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                      0x1f
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                 0x000000FEL
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                  0x00000100L
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                             0x007F0000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                            0x00800000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                            0x01000000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__DRS_SUPPORTED_MASK                                                        0x80000000L
+//BIF_CFG_DEV1_RC0_LINK_CNTL2
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                  0x4
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                       0x5
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                             0x6
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                       0x7
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                              0xa
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                    0xb
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                             0xc
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                   0x000FL
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                    0x0010L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                         0x0020L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                               0x0040L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN_MASK                                                         0x0380L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                0x0400L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                      0x0800L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                               0xF000L
+//BIF_CFG_DEV1_RC0_LINK_STATUS2
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                       0x1
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                 0x2
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                 0x4
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                   0x5
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                               0x6
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                               0x7
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                            0x8
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                   0xc
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                            0xf
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                              0x0001L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                         0x0002L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                   0x0004L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                   0x0008L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                   0x0010L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                     0x0020L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                 0x0040L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                 0x0080L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                              0x0300L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                     0x7000L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                              0x8000L
+//BIF_CFG_DEV1_RC0_SLOT_CAP2
+#define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_SLOT_CNTL2
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED_MASK                                                            0xFFFFL
+//BIF_CFG_DEV1_RC0_SLOT_STATUS2
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED_MASK                                                          0xFFFFL
+//BIF_CFG_DEV1_RC0_MSI_CAP_LIST
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV1_RC0_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                   0x1
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                    0x4
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                       0x7
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                       0x8
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                            0x9
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN_MASK                                                            0x0001L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                     0x000EL
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                      0x0070L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                         0x0080L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                         0x0100L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                              0x0200L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                               0x0400L
+//BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                              0x2
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                0xFFFFFFFCL
+//BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_MSI_MSG_DATA
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA_MASK                                                          0xFFFFL
+//BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                  0xFFFFL
+//BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                    0xFFFFL
+//BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                            0xFFFFL
+//BIF_CFG_DEV1_RC0_SSID_CAP_LIST
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV1_RC0_SSID_CAP
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                        0x10
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID_MASK                                                          0xFFFF0000L
+//BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV1_RC0_MSI_MAP_CAP
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN__SHIFT                                                               0x0
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD__SHIFT                                                             0x1
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                         0xb
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN_MASK                                                                 0x0001L
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD_MASK                                                               0x0002L
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE_MASK                                                           0xF800L
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                            0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                         0x14
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                               0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                              0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                           0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                              0x4
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                0x8
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                              0xa
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                             0x00000007L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                0x00000070L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                  0x00000300L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                0x00000C00L
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                    0x18
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                               0x000000FFL
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                      0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                              0x1
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                            0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                0x000EL
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                        0x0001L
+//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x007F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x003F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                     0x0
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                     0x0
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                        0x4
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                     0x5
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                        0xc
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                         0xd
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                      0x10
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                       0x11
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                        0x12
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                       0x13
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                  0x15
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                 0x16
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                 0x17
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                        0x18
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                         0x19
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                    0x1a
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                          0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                       0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                          0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                           0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                    0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                        0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                         0x00020000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                          0x00040000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                         0x00080000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                   0x00100000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                    0x00200000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                   0x00400000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                   0x00800000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                          0x01000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                           0x02000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                      0x04000000L
+//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                            0x4
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                         0x5
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                            0xc
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                             0xd
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                          0x10
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                           0x11
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                            0x12
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                           0x13
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                     0x14
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                      0x15
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                     0x16
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                     0x17
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                            0x18
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                             0x19
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                        0x1a
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                              0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                           0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                              0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                               0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                        0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                            0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                             0x00020000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                              0x00040000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                             0x00080000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                       0x00100000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                        0x00200000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                       0x00400000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                       0x00800000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                              0x01000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                               0x02000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                          0x04000000L
+//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                    0x4
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                    0xc
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                     0xd
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                0xe
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                              0xf
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                  0x10
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                   0x11
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                    0x12
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                   0x13
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                             0x14
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                              0x15
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                             0x16
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                             0x17
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                    0x18
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                     0x19
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                0x1a
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                      0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                   0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                      0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                       0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                  0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                    0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                     0x00020000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                      0x00040000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                     0x00080000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                               0x00100000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                0x00200000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                               0x00400000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                               0x00800000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                      0x01000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                       0x02000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                  0x04000000L
+//BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                          0x6
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                         0x7
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                             0xc
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                            0xd
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                            0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                            0x00000040L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                           0x00000080L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                0x00000100L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                               0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                              0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                       0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                       0x00008000L
+//BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                              0x6
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                             0x7
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                  0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                0xd
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                         0xe
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                         0xf
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                0x00000040L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                               0x00000080L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                    0x00000100L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                   0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                  0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                           0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                           0x00008000L
+//BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                         0x7
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                     0x9
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                      0xa
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                 0xb
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                         0xc
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                            0x0000001FL
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                           0x00000080L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                            0x00000100L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                       0x00000200L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                        0x00000400L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                   0x00000800L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                           0x00001000L
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                           0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                              0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                          0x00000002L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                             0x00000004L
+//BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                      0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                 0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                            0x3
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                               0x4
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                    0x6
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                     0x1b
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                             0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                        0x00000002L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                   0x00000004L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                              0x00000008L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                 0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                   0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                      0x00000040L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                       0xF8000000L
+//BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                    0x10
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                      0xFFFF0000L
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                         0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                           0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                   0x00000002L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                  0x0000FFFFL
+//BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                            0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                            0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                         0x3
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                             0x4
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                              0x5
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                           0x6
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                              0x0002L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                              0x0004L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                           0x0008L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                               0x0010L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                0x0020L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                             0x0040L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                        0xFF00L
+//BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                        0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                     0x3
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                          0x0004L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                       0x0008L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                         0x0040L
+//BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                    0x0
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                    0x1f
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                      0x007FFFFFL
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                      0x80000000L
+//BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                0x0
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                          0x1f
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                  0x007FFFFFL
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                            0x80000000L
+//BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV1_RC0_LINK_CAP_16GT
+#define BIF_CFG_DEV1_RC0_LINK_CAP_16GT__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_RC0_LINK_CAP_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_LINK_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LINK_CNTL_16GT__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_RC0_LINK_CNTL_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_LINK_STATUS_16GT
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                  0x0
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                            0x1
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                            0x2
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                            0x3
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                              0x4
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                    0x00000001L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                              0x00000002L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                              0x00000004L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                              0x00000008L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                0x00000010L
+//BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT          0x0
+#define BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK            0x0000FFFFL
+//BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                   0x0
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                     0x0001L
+//BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                        0x0
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                               0x1
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                          0x0001L
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                 0x0002L
+//BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp
+//BIF_CFG_DEV2_RC0_VENDOR_ID
+#define BIF_CFG_DEV2_RC0_VENDOR_ID__VENDOR_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC0_VENDOR_ID__VENDOR_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV2_RC0_DEVICE_ID
+#define BIF_CFG_DEV2_RC0_DEVICE_ID__DEVICE_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_ID__DEVICE_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV2_RC0_COMMAND
+#define BIF_CFG_DEV2_RC0_COMMAND__IOEN_DN__SHIFT                                                              0x0
+#define BIF_CFG_DEV2_RC0_COMMAND__MEMEN_DN__SHIFT                                                             0x1
+#define BIF_CFG_DEV2_RC0_COMMAND__BUS_MASTER_EN__SHIFT                                                        0x2
+#define BIF_CFG_DEV2_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV2_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV2_RC0_COMMAND__PAL_SNOOP_EN__SHIFT                                                         0x5
+#define BIF_CFG_DEV2_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                0x6
+#define BIF_CFG_DEV2_RC0_COMMAND__AD_STEPPING__SHIFT                                                          0x7
+#define BIF_CFG_DEV2_RC0_COMMAND__SERR_EN__SHIFT                                                              0x8
+#define BIF_CFG_DEV2_RC0_COMMAND__FAST_B2B_EN__SHIFT                                                          0x9
+#define BIF_CFG_DEV2_RC0_COMMAND__INT_DIS__SHIFT                                                              0xa
+#define BIF_CFG_DEV2_RC0_COMMAND__IOEN_DN_MASK                                                                0x0001L
+#define BIF_CFG_DEV2_RC0_COMMAND__MEMEN_DN_MASK                                                               0x0002L
+#define BIF_CFG_DEV2_RC0_COMMAND__BUS_MASTER_EN_MASK                                                          0x0004L
+#define BIF_CFG_DEV2_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV2_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV2_RC0_COMMAND__PAL_SNOOP_EN_MASK                                                           0x0020L
+#define BIF_CFG_DEV2_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                  0x0040L
+#define BIF_CFG_DEV2_RC0_COMMAND__AD_STEPPING_MASK                                                            0x0080L
+#define BIF_CFG_DEV2_RC0_COMMAND__SERR_EN_MASK                                                                0x0100L
+#define BIF_CFG_DEV2_RC0_COMMAND__FAST_B2B_EN_MASK                                                            0x0200L
+#define BIF_CFG_DEV2_RC0_COMMAND__INT_DIS_MASK                                                                0x0400L
+//BIF_CFG_DEV2_RC0_STATUS
+#define BIF_CFG_DEV2_RC0_STATUS__IMMEDIATE_READINESS__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_RC0_STATUS__INT_STATUS__SHIFT                                                            0x3
+#define BIF_CFG_DEV2_RC0_STATUS__CAP_LIST__SHIFT                                                              0x4
+#define BIF_CFG_DEV2_RC0_STATUS__PCI_66_CAP__SHIFT                                                            0x5
+#define BIF_CFG_DEV2_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                     0x7
+#define BIF_CFG_DEV2_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                              0x8
+#define BIF_CFG_DEV2_RC0_STATUS__DEVSEL_TIMING__SHIFT                                                         0x9
+#define BIF_CFG_DEV2_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                   0xb
+#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                 0xc
+#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                 0xd
+#define BIF_CFG_DEV2_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                 0xe
+#define BIF_CFG_DEV2_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                 0xf
+#define BIF_CFG_DEV2_RC0_STATUS__IMMEDIATE_READINESS_MASK                                                     0x0001L
+#define BIF_CFG_DEV2_RC0_STATUS__INT_STATUS_MASK                                                              0x0008L
+#define BIF_CFG_DEV2_RC0_STATUS__CAP_LIST_MASK                                                                0x0010L
+#define BIF_CFG_DEV2_RC0_STATUS__PCI_66_CAP_MASK                                                              0x0020L
+#define BIF_CFG_DEV2_RC0_STATUS__FAST_BACK_CAPABLE_MASK                                                       0x0080L
+#define BIF_CFG_DEV2_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                0x0100L
+#define BIF_CFG_DEV2_RC0_STATUS__DEVSEL_TIMING_MASK                                                           0x0600L
+#define BIF_CFG_DEV2_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                     0x0800L
+#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                   0x1000L
+#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                   0x2000L
+#define BIF_CFG_DEV2_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                   0x4000L
+#define BIF_CFG_DEV2_RC0_STATUS__PARITY_ERROR_DETECTED_MASK                                                   0x8000L
+//BIF_CFG_DEV2_RC0_REVISION_ID
+#define BIF_CFG_DEV2_RC0_REVISION_ID__MINOR_REV_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                     0x4
+#define BIF_CFG_DEV2_RC0_REVISION_ID__MINOR_REV_ID_MASK                                                       0x0FL
+#define BIF_CFG_DEV2_RC0_REVISION_ID__MAJOR_REV_ID_MASK                                                       0xF0L
+//BIF_CFG_DEV2_RC0_PROG_INTERFACE
+#define BIF_CFG_DEV2_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                  0xFFL
+//BIF_CFG_DEV2_RC0_SUB_CLASS
+#define BIF_CFG_DEV2_RC0_SUB_CLASS__SUB_CLASS__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC0_SUB_CLASS__SUB_CLASS_MASK                                                            0xFFL
+//BIF_CFG_DEV2_RC0_BASE_CLASS
+#define BIF_CFG_DEV2_RC0_BASE_CLASS__BASE_CLASS__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC0_BASE_CLASS__BASE_CLASS_MASK                                                          0xFFL
+//BIF_CFG_DEV2_RC0_CACHE_LINE
+#define BIF_CFG_DEV2_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                     0xFFL
+//BIF_CFG_DEV2_RC0_LATENCY
+#define BIF_CFG_DEV2_RC0_LATENCY__LATENCY_TIMER__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC0_LATENCY__LATENCY_TIMER_MASK                                                          0xFFL
+//BIF_CFG_DEV2_RC0_HEADER
+#define BIF_CFG_DEV2_RC0_HEADER__HEADER_TYPE__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_RC0_HEADER__DEVICE_TYPE__SHIFT                                                           0x7
+#define BIF_CFG_DEV2_RC0_HEADER__HEADER_TYPE_MASK                                                             0x7FL
+#define BIF_CFG_DEV2_RC0_HEADER__DEVICE_TYPE_MASK                                                             0x80L
+//BIF_CFG_DEV2_RC0_BIST
+#define BIF_CFG_DEV2_RC0_BIST__BIST_COMP__SHIFT                                                               0x0
+#define BIF_CFG_DEV2_RC0_BIST__BIST_STRT__SHIFT                                                               0x6
+#define BIF_CFG_DEV2_RC0_BIST__BIST_CAP__SHIFT                                                                0x7
+#define BIF_CFG_DEV2_RC0_BIST__BIST_COMP_MASK                                                                 0x0FL
+#define BIF_CFG_DEV2_RC0_BIST__BIST_STRT_MASK                                                                 0x40L
+#define BIF_CFG_DEV2_RC0_BIST__BIST_CAP_MASK                                                                  0x80L
+//BIF_CFG_DEV2_RC0_BASE_ADDR_1
+#define BIF_CFG_DEV2_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC0_BASE_ADDR_1__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_BASE_ADDR_2
+#define BIF_CFG_DEV2_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC0_BASE_ADDR_2__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                         0x8
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                           0x10
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                               0x18
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                           0x0000FF00L
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                             0x00FF0000L
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                 0xFF000000L
+//BIF_CFG_DEV2_RC0_IO_BASE_LIMIT
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                        0x4
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                  0x8
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                       0xc
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                     0x000FL
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                    0x0F00L
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                         0xF000L
+//BIF_CFG_DEV2_RC0_SECONDARY_STATUS
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                  0x5
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                           0x7
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                    0x8
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                               0x9
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                         0xb
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                       0xc
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                       0xd
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                       0xe
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                       0xf
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                    0x0020L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                             0x0080L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                      0x0100L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                 0x0600L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                           0x0800L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                         0x1000L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                         0x2000L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                         0x4000L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                         0x8000L
+//BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                0x4
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                0x10
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                               0x14
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                   0x0000000FL
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                  0x0000FFF0L
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                          0x4
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                          0x10
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                         0x14
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                             0x0000000FL
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                            0x0000FFF0L
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                            0x000F0000L
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                           0xFFF00000L
+//BIF_CFG_DEV2_RC0_PREF_BASE_UPPER
+#define BIF_CFG_DEV2_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                            0x0
+#define BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                              0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                               0x0
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                              0x10
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                0xFFFF0000L
+//BIF_CFG_DEV2_RC0_CAP_PTR
+#define BIF_CFG_DEV2_RC0_CAP_PTR__CAP_PTR__SHIFT                                                              0x0
+#define BIF_CFG_DEV2_RC0_CAP_PTR__CAP_PTR_MASK                                                                0xFFL
+//BIF_CFG_DEV2_RC0_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_INTERRUPT_LINE
+#define BIF_CFG_DEV2_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                  0xFFL
+//BIF_CFG_DEV2_RC0_INTERRUPT_PIN
+#define BIF_CFG_DEV2_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                    0xFFL
+//BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                      0x1
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                       0x3
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                      0x4
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                            0x5
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                          0x6
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                  0x7
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                        0x8
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                      0x9
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                         0xa
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                    0xb
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                        0x0002L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                         0x0008L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                        0x0010L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                              0x0020L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                            0x0040L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                    0x0080L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                          0x0100L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                        0x0200L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                           0x0400L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                      0x0800L
+//BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                  0x01L
+//BIF_CFG_DEV2_RC0_PMI_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV2_RC0_PMI_CAP
+#define BIF_CFG_DEV2_RC0_PMI_CAP__VERSION__SHIFT                                                              0x0
+#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_CLOCK__SHIFT                                                            0x3
+#define BIF_CFG_DEV2_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                  0x4
+#define BIF_CFG_DEV2_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_RC0_PMI_CAP__AUX_CURRENT__SHIFT                                                          0x6
+#define BIF_CFG_DEV2_RC0_PMI_CAP__D1_SUPPORT__SHIFT                                                           0x9
+#define BIF_CFG_DEV2_RC0_PMI_CAP__D2_SUPPORT__SHIFT                                                           0xa
+#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_SUPPORT__SHIFT                                                          0xb
+#define BIF_CFG_DEV2_RC0_PMI_CAP__VERSION_MASK                                                                0x0007L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_CLOCK_MASK                                                              0x0008L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                    0x0010L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                      0x0020L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__AUX_CURRENT_MASK                                                            0x01C0L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__D1_SUPPORT_MASK                                                             0x0200L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__D2_SUPPORT_MASK                                                             0x0400L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_SUPPORT_MASK                                                            0xF800L
+//BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                0x3
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                       0x8
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                  0x9
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                   0xd
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                   0xf
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                0x16
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                   0x17
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                     0x18
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                    0x00000003L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                  0x00000008L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_EN_MASK                                                         0x00000100L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                    0x00001E00L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                     0x00006000L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                     0x00008000L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                  0x00400000L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                     0x00800000L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                       0xFF000000L
+//BIF_CFG_DEV2_RC0_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV2_RC0_PCIE_CAP
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                         0x4
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                     0x9
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__VERSION_MASK                                                               0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__DEVICE_TYPE_MASK                                                           0x00F0L
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                      0x0100L
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                       0x3E00L
+//BIF_CFG_DEV2_RC0_DEVICE_CAP
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                               0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                      0x3
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                      0x5
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                            0x6
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                             0x9
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                          0xf
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                       0x1c
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                 0x00000007L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                        0x00000018L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__EXTENDED_TAG_MASK                                                        0x00000020L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                              0x000001C0L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                               0x00000E00L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                            0x00008000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__FLR_CAPABLE_MASK                                                         0x10000000L
+//BIF_CFG_DEV2_RC0_DEVICE_CNTL
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                 0x1
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                 0x5
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                  0x8
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                  0x9
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                  0xa
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                      0xb
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                            0xc
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                              0xf
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                   0x0002L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                     0x0010L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                   0x00E0L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                    0x0100L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                    0x0200L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                    0x0400L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                        0x0800L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                              0x7000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                0x8000L
+//BIF_CFG_DEV2_RC0_DEVICE_STATUS
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__CORR_ERR__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                  0x1
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                      0x2
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                   0x3
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__AUX_PWR__SHIFT                                                        0x4
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                              0x5
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                  0x6
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__CORR_ERR_MASK                                                         0x0001L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                    0x0002L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__FATAL_ERR_MASK                                                        0x0004L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__USR_DETECTED_MASK                                                     0x0008L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__AUX_PWR_MASK                                                          0x0010L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                0x0020L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                    0x0040L
+//BIF_CFG_DEV2_RC0_LINK_CAP
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_SPEED__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_WIDTH__SHIFT                                                          0x4
+#define BIF_CFG_DEV2_RC0_LINK_CAP__PM_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV2_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                    0xc
+#define BIF_CFG_DEV2_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                     0xf
+#define BIF_CFG_DEV2_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                              0x12
+#define BIF_CFG_DEV2_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                         0x13
+#define BIF_CFG_DEV2_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                         0x14
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                            0x15
+#define BIF_CFG_DEV2_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                         0x16
+#define BIF_CFG_DEV2_RC0_LINK_CAP__PORT_NUMBER__SHIFT                                                         0x18
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_SPEED_MASK                                                            0x0000000FL
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_WIDTH_MASK                                                            0x000003F0L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__PM_SUPPORT_MASK                                                            0x00000C00L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                      0x00007000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                       0x00038000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                0x00040000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                           0x00080000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                           0x00100000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                              0x00200000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                           0x00400000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__PORT_NUMBER_MASK                                                           0xFF000000L
+//BIF_CFG_DEV2_RC0_LINK_CNTL
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__PM_CONTROL__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_DIS__SHIFT                                                           0x4
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                       0x5
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                   0x6
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                      0x7
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                          0xb
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                              0xe
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__PM_CONTROL_MASK                                                           0x0003L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                    0x0008L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_DIS_MASK                                                             0x0010L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__RETRAIN_LINK_MASK                                                         0x0020L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                     0x0040L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__EXTENDED_SYNC_MASK                                                        0x0080L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                            0x0100L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                            0x0400L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                            0x0800L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                0xC000L
+//BIF_CFG_DEV2_RC0_LINK_STATUS
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                               0x0
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                            0x4
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_TRAINING__SHIFT                                                    0xb
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                   0xc
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__DL_ACTIVE__SHIFT                                                        0xd
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                        0xe
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                        0xf
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                 0x000FL
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                              0x03F0L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_TRAINING_MASK                                                      0x0800L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                     0x1000L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__DL_ACTIVE_MASK                                                          0x2000L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                          0x4000L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                          0x8000L
+//BIF_CFG_DEV2_RC0_SLOT_CAP
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                              0x1
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                  0x2
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                              0x3
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                               0x4
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                     0x6
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                0x7
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                0xf
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                       0x11
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                      0x12
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                   0x13
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                   0x00000001L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                0x00000002L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                    0x00000004L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                0x00000008L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                 0x00000010L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                      0x00000020L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                       0x00000040L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                  0x00007F80L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                  0x00018000L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                         0x00020000L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                        0x00040000L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                     0xFFF80000L
+//BIF_CFG_DEV2_RC0_SLOT_CNTL
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                             0x0
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                              0x2
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                         0x3
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                0x6
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                 0x8
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                0xa
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                         0xb
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                0xc
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                        0xd
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                               0x0001L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                0x0004L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                           0x0008L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                            0x0010L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                  0x00C0L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                   0x0300L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                  0x0400L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                           0x0800L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                  0x1000L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                          0x2000L
+//BIF_CFG_DEV2_RC0_SLOT_STATUS
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                               0x1
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                               0x2
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                          0x3
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                0x4
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                 0x5
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                            0x6
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                     0x7
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                 0x8
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                0x0001L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                 0x0002L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                 0x0004L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                            0x0008L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                  0x0010L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                   0x0020L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                              0x0040L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                       0x0080L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                   0x0100L
+//BIF_CFG_DEV2_RC0_ROOT_CNTL
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                               0x2
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                  0x0001L
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                 0x0004L
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                           0x0010L
+//BIF_CFG_DEV2_RC0_ROOT_CAP
+#define BIF_CFG_DEV2_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                             0x0
+#define BIF_CFG_DEV2_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                               0x0001L
+//BIF_CFG_DEV2_RC0_ROOT_STATUS
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_STATUS__SHIFT                                                       0x10
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_PENDING__SHIFT                                                      0x11
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_STATUS_MASK                                                         0x00010000L
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_PENDING_MASK                                                        0x00020000L
+//BIF_CFG_DEV2_RC0_DEVICE_CAP2
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                      0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                        0x4
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                         0x5
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                       0x6
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                       0x7
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                       0x8
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                           0x9
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                        0xa
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                    0xb
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                               0xc
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                    0xe
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                  0x10
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                  0x11
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                   0x12
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                     0x14
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                     0x15
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                         0x16
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                   0x18
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                    0x1a
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                    0x1f
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                        0x0000000FL
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                          0x00000010L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                           0x00000020L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                         0x00000040L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                         0x00000080L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                         0x00000100L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                             0x00000200L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                          0x00000400L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                      0x00000800L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                 0x00003000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                      0x0000C000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                    0x00010000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                    0x00020000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                     0x000C0000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                       0x00100000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                       0x00200000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                           0x00C00000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                     0x03000000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                      0x04000000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                      0x80000000L
+//BIF_CFG_DEV2_RC0_DEVICE_CNTL2
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                               0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                 0x4
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                               0x5
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                             0x6
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                        0x7
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                              0x8
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                           0x9
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__LTR_EN__SHIFT                                                          0xa
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                    0xb
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                    0xc
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                         0xd
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                     0xf
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                 0x000FL
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                   0x0010L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                 0x0020L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                               0x0040L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                          0x0080L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                0x0100L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                             0x0200L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__LTR_EN_MASK                                                            0x0400L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                      0x0800L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                      0x1000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__OBFF_EN_MASK                                                           0x6000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                       0x8000L
+//BIF_CFG_DEV2_RC0_DEVICE_STATUS2
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS2__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS2__RESERVED_MASK                                                        0xFFFFL
+//BIF_CFG_DEV2_RC0_LINK_CAP2
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                               0x1
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                0x8
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                           0x10
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                          0x17
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                          0x18
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                      0x1f
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                 0x000000FEL
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                  0x00000100L
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                             0x007F0000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                            0x00800000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                            0x01000000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__DRS_SUPPORTED_MASK                                                        0x80000000L
+//BIF_CFG_DEV2_RC0_LINK_CNTL2
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                  0x4
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                       0x5
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                             0x6
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                       0x7
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                              0xa
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                    0xb
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                             0xc
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                   0x000FL
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                    0x0010L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                         0x0020L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                               0x0040L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__XMIT_MARGIN_MASK                                                         0x0380L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                0x0400L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                      0x0800L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                               0xF000L
+//BIF_CFG_DEV2_RC0_LINK_STATUS2
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                            0x0
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                       0x1
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                 0x2
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                 0x3
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                 0x4
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                   0x5
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                               0x6
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                               0x7
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                            0x8
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                   0xc
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                            0xf
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                              0x0001L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                         0x0002L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                   0x0004L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                   0x0008L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                   0x0010L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                     0x0020L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                 0x0040L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                 0x0080L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                              0x0300L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                     0x7000L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                              0x8000L
+//BIF_CFG_DEV2_RC0_SLOT_CAP2
+#define BIF_CFG_DEV2_RC0_SLOT_CAP2__RESERVED__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_RC0_SLOT_CAP2__RESERVED_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_SLOT_CNTL2
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL2__RESERVED__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL2__RESERVED_MASK                                                            0xFFFFL
+//BIF_CFG_DEV2_RC0_SLOT_STATUS2
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS2__RESERVED__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS2__RESERVED_MASK                                                          0xFFFFL
+//BIF_CFG_DEV2_RC0_MSI_CAP_LIST
+#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV2_RC0_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                   0x1
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                    0x4
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                       0x7
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                       0x8
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                            0x9
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EN_MASK                                                            0x0001L
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                     0x000EL
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                      0x0070L
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                         0x0080L
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                         0x0100L
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                              0x0200L
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                               0x0400L
+//BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                              0x2
+#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                0xFFFFFFFCL
+//BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_MSI_MSG_DATA
+#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA__MSI_DATA_MASK                                                          0xFFFFL
+//BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                  0xFFFFL
+//BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                    0xFFFFL
+//BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                          0x0
+#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                            0xFFFFL
+//BIF_CFG_DEV2_RC0_SSID_CAP_LIST
+#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV2_RC0_SSID_CAP
+#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                        0x10
+#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_ID_MASK                                                          0xFFFF0000L
+//BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_RC0_MSI_MAP_CAP
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__EN__SHIFT                                                               0x0
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__FIXD__SHIFT                                                             0x1
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                         0xb
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__EN_MASK                                                                 0x0001L
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__FIXD_MASK                                                               0x0002L
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__CAP_TYPE_MASK                                                           0xF800L
+//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                             0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                            0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                         0x14
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                               0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                              0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                           0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                              0x4
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                0x8
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                              0xa
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                             0x00000007L
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                0x00000070L
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                  0x00000300L
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                0x00000C00L
+//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                             0x0
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                    0x18
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                               0x000000FFL
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                      0xFF000000L
+//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                          0x0
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                              0x1
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                            0x0001L
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                0x000EL
+//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                        0x0001L
+//BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x007F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x003F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                     0x0
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                     0x0
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                        0x4
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                     0x5
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                        0xc
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                         0xd
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                      0x10
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                       0x11
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                        0x12
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                       0x13
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                  0x15
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                 0x16
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                 0x17
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                        0x18
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                         0x19
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                    0x1a
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                          0x00000010L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                       0x00000020L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                          0x00001000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                           0x00002000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                    0x00008000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                        0x00010000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                         0x00020000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                          0x00040000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                         0x00080000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                   0x00100000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                    0x00200000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                   0x00400000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                   0x00800000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                          0x01000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                           0x02000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                      0x04000000L
+//BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                            0x4
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                         0x5
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                            0xc
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                             0xd
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                          0x10
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                           0x11
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                            0x12
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                           0x13
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                     0x14
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                      0x15
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                     0x16
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                     0x17
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                            0x18
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                             0x19
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                        0x1a
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                              0x00000010L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                           0x00000020L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                              0x00001000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                               0x00002000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                        0x00008000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                            0x00010000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                             0x00020000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                              0x00040000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                             0x00080000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                       0x00100000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                        0x00200000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                       0x00400000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                       0x00800000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                              0x01000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                               0x02000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                          0x04000000L
+//BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                    0x4
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                 0x5
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                    0xc
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                     0xd
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                0xe
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                              0xf
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                  0x10
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                   0x11
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                    0x12
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                   0x13
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                             0x14
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                              0x15
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                             0x16
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                             0x17
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                    0x18
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                     0x19
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                0x1a
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                      0x00000010L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                   0x00000020L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                      0x00001000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                       0x00002000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                  0x00004000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                0x00008000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                    0x00010000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                     0x00020000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                      0x00040000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                     0x00080000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                               0x00100000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                0x00200000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                               0x00400000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                               0x00800000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                      0x01000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                       0x02000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                  0x04000000L
+//BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                          0x0
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                          0x6
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                         0x7
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                              0x8
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                             0xc
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                            0xd
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                            0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                            0x00000040L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                           0x00000080L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                0x00000100L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                               0x00001000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                              0x00002000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                       0x00004000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                       0x00008000L
+//BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                              0x6
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                             0x7
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                  0x8
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                0xd
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                         0xe
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                         0xf
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                0x00000040L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                               0x00000080L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                    0x00000100L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                   0x00001000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                  0x00002000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                           0x00004000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                           0x00008000L
+//BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                          0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                         0x7
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                     0x9
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                      0xa
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                 0xb
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                         0xc
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                            0x0000001FL
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                           0x00000080L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                            0x00000100L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                       0x00000200L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                        0x00000400L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                   0x00000800L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                           0x00001000L
+//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                           0x2
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                              0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                          0x00000002L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                             0x00000004L
+//BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                      0x1
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                 0x2
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                            0x3
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                               0x4
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                 0x5
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                    0x6
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                     0x1b
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                             0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                        0x00000002L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                   0x00000004L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                              0x00000008L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                 0x00000010L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                   0x00000020L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                      0x00000040L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                       0xF8000000L
+//BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                    0x10
+#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                      0xFFFF0000L
+//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                         0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                 0x1
+#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                           0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                   0x00000002L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                  0x0000FFFFL
+//BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                               0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                            0x1
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                            0x2
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                         0x3
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                             0x4
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                              0x5
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                           0x6
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                 0x0001L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                              0x0002L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                              0x0004L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                           0x0008L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                               0x0010L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                0x0020L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                             0x0040L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                        0xFF00L
+//BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                        0x2
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                     0x3
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                          0x0004L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                       0x0008L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                         0x0040L
+//BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                    0x0
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                    0x1f
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                      0x007FFFFFL
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                      0x80000000L
+//BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                0x0
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                          0x1f
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                  0x007FFFFFL
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                            0x80000000L
+//BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV2_RC0_LINK_CAP_16GT
+#define BIF_CFG_DEV2_RC0_LINK_CAP_16GT__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_RC0_LINK_CAP_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_LINK_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LINK_CNTL_16GT__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_RC0_LINK_CNTL_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_LINK_STATUS_16GT
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                  0x0
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                            0x1
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                            0x2
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                            0x3
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                              0x4
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                    0x00000001L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                              0x00000002L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                              0x00000004L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                              0x00000008L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                0x00000010L
+//BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT          0x0
+#define BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK            0x0000FFFFL
+//BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                   0x0
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                     0x0001L
+//BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                        0x0
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                               0x1
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                          0x0001L
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                 0x0002L
+//BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF1_MM_INDEX
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT                                                                 0x0
+#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT                                                                   0x1f
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK                                                                   0x7FFFFFFFL
+#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK                                                                     0x80000000L
+//BIF_BX_PF1_MM_DATA
+#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT                                                                    0x0
+#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK                                                                      0xFFFFFFFFL
+//BIF_BX_PF1_MM_INDEX_HI
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                           0x0
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+//BIF_BX1_PCIE_INDEX
+#define BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT                                                                 0x0
+#define BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK                                                                   0xFFFFFFFFL
+//BIF_BX1_PCIE_DATA
+#define BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT                                                                   0x0
+#define BIF_BX1_PCIE_DATA__PCIE_DATA_MASK                                                                     0xFFFFFFFFL
+//BIF_BX1_PCIE_INDEX2
+#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT                                                               0x0
+#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK                                                                 0xFFFFFFFFL
+//BIF_BX1_PCIE_DATA2
+#define BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT                                                                 0x0
+#define BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK                                                                   0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_0
+#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_1
+#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_2
+#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_3
+#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_0
+#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_1
+#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_2
+#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_3
+#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_4
+#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_5
+#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_6
+#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_7
+#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_8
+#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_9
+#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_10
+#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_11
+#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_12
+#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_13
+#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_14
+#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_15
+#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIF_RLC_INTR_CNTL
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT                                                    0x0
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT                                             0x1
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT                                                   0x2
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT                                              0x3
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK                                                      0x00000001L
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK                                               0x00000002L
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK                                                     0x00000004L
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK                                                0x00000008L
+//BIF_BX1_BIF_VCE_INTR_CNTL
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT                                                    0x0
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT                                             0x1
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT                                                   0x2
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT                                              0x3
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK                                                      0x00000001L
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK                                               0x00000002L
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK                                                     0x00000004L
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK                                                0x00000008L
+//BIF_BX1_BIF_UVD_INTR_CNTL
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT                                                    0x0
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT                                             0x1
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT                                                   0x2
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT                                              0x3
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT                                                        0x1c
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK                                                      0x00000001L
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK                                               0x00000002L
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK                                                     0x00000004L
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK                                                0x00000008L
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK                                                          0xF0000000L
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK                                                         0x000000FFL
+//BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT                                                 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK                                                   0xFFFFFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT                                                   0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK                                                     0xFFFFFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT                                 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK                                   0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1:1
+//RCC_STRAP1_RCC_BIF_STRAP0
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT                                                  0x0
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT                                                   0x2
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT                                               0x3
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT                                               0x6
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT                                                    0x7
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT                                                 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT                                  0x9
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT                                         0xa
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT                                     0xb
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT                                              0xc
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT                                             0xd
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                     0xe
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                  0xf
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT                                              0x10
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT                                           0x11
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT                                                      0x18
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT                                                 0x19
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT                                                0x1a
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT                                      0x1d
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT                                                   0x1e
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT                                            0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK                                                    0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK                                                     0x00000004L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK                                                 0x00000038L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK                                                 0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK                                                      0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK                                                   0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK                                    0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK                                           0x00000400L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK                                       0x00000800L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK                                                0x00001000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK                                               0x00002000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                       0x00004000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                    0x00008000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK                                                0x00010000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK                                             0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK                                                        0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK                                                   0x02000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK                                                  0x04000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK                                       0x08000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK                                        0x20000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK                                                     0x40000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK                                              0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP1
+#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT                                                      0x1
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT                                      0x3
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT                                     0x5
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                       0x6
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT                                               0x7
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT                                                  0x8
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT                                                 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT                                                  0xa
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT                                        0xc
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT                                                    0xd
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT                                                    0xf
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT                                             0x11
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT                                             0x12
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT                                                        0x13
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT                                                   0x14
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT                                                     0x15
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT                                             0x16
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT                                     0x17
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT                                             0x1a
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT                                       0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT                                                     0x1d
+#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK                                                        0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK                                        0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK                                       0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK                                         0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK                                                 0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK                                                    0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK                                                   0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK                                                    0x00000C00L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK                                          0x00001000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK                                                      0x00006000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK                                                      0x00018000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK                                               0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK                                               0x00040000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK                                                          0x00080000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK                                                     0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK                                                       0x00200000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK                                               0x00400000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK                                       0x00800000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK                                               0x04000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK                                         0x18000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK                                                       0x20000000L
+//RCC_STRAP1_RCC_BIF_STRAP2
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT                                     0x0
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT                                            0x3
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT                                            0x4
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT                                        0x5
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT                                      0x6
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT                                 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT                                        0x9
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT                                   0xa
+#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT                                                 0xd
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT                                             0xe
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT                                 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT                                         0x10
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT                                        0x18
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT                            0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK                                       0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK                                              0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK                                              0x00000010L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK                                          0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK                                        0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK                                   0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK                                          0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK                                     0x00000C00L
+#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK                                                   0x00002000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK                                               0x00004000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK                                   0x00008000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK                                           0x00FF0000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK                                          0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK                              0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP3
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT                                         0x0
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT                                       0x10
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK                                         0xFFFF0000L
+//RCC_STRAP1_RCC_BIF_STRAP4
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT                                          0x0
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT                                           0x10
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK                                            0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK                                             0xFFFF0000L
+//RCC_STRAP1_RCC_BIF_STRAP5
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT                                         0x0
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT                                      0x10
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT                                   0x11
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT                                    0x12
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT                                        0x13
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT                                    0x14
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT                                         0x16
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT                          0x18
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x19
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT                                           0x1c
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK                                        0x00010000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK                                     0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK                                      0x00040000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK                                          0x00080000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK                                      0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK                                           0x00C00000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK                            0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x06000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x08000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK                                             0x70000000L
+//RCC_STRAP1_RCC_BIF_STRAP6
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT                                          0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT                                          0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT                                          0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT                                0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT                                       0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT                                   0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT                            0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT                             0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT                             0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT                                      0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK                                            0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK                                            0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK                                            0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK                                  0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK                                         0x001FFFE0L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK                                     0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK                              0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK                               0x0E000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK                               0x70000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK                                        0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT                                       0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT                                   0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK                                         0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK                                     0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT                                 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT                                          0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT                                      0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT                                          0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT                                      0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT                                  0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT                             0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT                                0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT                                    0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT                              0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT                      0xd
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT                                    0xe
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT                                            0xf
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT                                    0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT                                    0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT                                  0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT                             0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT                                   0x17
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT                              0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT                                    0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK                                   0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK                                            0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK                                        0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK                                            0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK                                        0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK                                    0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK                               0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK                                  0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK                                      0x00000E00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK                                0x00001000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK                        0x00002000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK                                      0x00004000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK                                              0x00008000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK                                      0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK                                      0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK                                    0x000C0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK                               0x00700000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK                                     0x03800000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK                                0x1C000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK                                      0xE0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT                     0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT                                             0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT                                          0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT                                0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT                                          0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT                                  0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT                                   0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT                                     0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0xb
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0xe
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT                                         0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT                                      0x1b
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT                                       0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT                                         0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK                       0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK                                               0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK                                            0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK                                  0x00000038L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK                                            0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK                                    0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK                                     0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK                                       0x00000600L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x00003800L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK  0x0003C000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x001C0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK  0x01E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK                                           0x06000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK                                        0x18000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK                                         0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK                                           0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT                              0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT                              0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT                              0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK                                0xFF000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT                              0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT                        0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT                                 0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT                                  0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT                                           0x13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT                                           0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT                                        0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT                                0x16
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT                           0x17
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT                        0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT                        0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT                     0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT                         0x1b
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT                          0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT                       0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT                                         0x1e
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT                                            0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK                          0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK                                   0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK                                    0x00040000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK                                             0x00080000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK                                             0x00100000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK                                          0x00200000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK                                  0x00400000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK                             0x00800000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK                          0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK                          0x02000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK                       0x04000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK                           0x08000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK                            0x10000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK                         0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK                                           0x40000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK                                              0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT                                         0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT                         0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT                      0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                      0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                   0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT     0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT     0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT                              0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT                            0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT                     0x13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK                                           0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK                           0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK                        0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                        0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                     0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK       0x00000F00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK       0x0000F000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK                                0x00030000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK                              0x00040000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK                       0x00080000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT                                        0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT                                    0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT                                    0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT                                          0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT                                          0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT                                          0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK                                          0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK                                      0x00000F00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK                                      0x0000F000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK                                            0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK                                            0x1F000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK                                            0xE0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT                              0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT                              0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT                              0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK                                0xFF000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT                              0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT                                       0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK                                         0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT                       0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK                                0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK                         0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT                                 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT                                0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK                                   0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK                                   0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK                                  0x00FF0000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT                                      0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK                                        0x0000FFFFL
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT                                        0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT                                 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT                                       0x6
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT                                   0x7
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT                                 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT                          0xe
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT                                          0xf
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT                                          0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT                                          0x11
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT                                0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT                                          0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT                                           0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT                                   0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT                                     0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT                                        0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT                  0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT               0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT                       0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK                                          0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK                                   0x0000003EL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK                                         0x00000040L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK                                     0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK                                   0x00003E00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK                            0x00004000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK                                            0x00008000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK                                            0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK                                            0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK                                  0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK                                            0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK                                             0x00800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK                                     0x07000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK                                       0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK                                          0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK                    0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK                 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK                         0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT                      0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT                                          0x1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT                                       0x2
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT                              0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT                                         0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT                                  0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT                                         0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT                        0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT                       0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT                                0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT                                       0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT                               0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK                        0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK                                            0x00000002L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK                                         0x0003FFFCL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK                                0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK                                           0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK                                    0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK                                           0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK                          0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK                         0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK                                  0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK                                         0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK                                 0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT                                       0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT                                     0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT                                   0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT                                  0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK                                   0x000003FFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK                                         0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK                                       0x0F800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK                                     0x70000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK                                    0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT                                   0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT                            0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK                                     0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK                              0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT                                0x3
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT                                     0x4
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT                                      0x7
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT                                     0x9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT                                     0xd
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                           0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT                                  0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT                                  0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT                                         0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT                                0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT                           0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK                                0x00000007L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK                                  0x00000008L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK                                       0x00000070L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK                                        0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK                                       0x00001E00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK                                       0x0000E000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK                             0x00070000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK                                    0x00780000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK                                    0x03800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK                                           0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK                                  0x38000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK                             0xC0000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT                           0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT                               0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT                        0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT                                    0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT                                 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT                                 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK                             0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK                                 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK                          0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK                                      0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK                                   0x00C00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK                                   0x0F000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT                                       0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT                                    0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT                                    0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT                                         0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT                           0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT                                      0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT                                      0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK                                         0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK                                      0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK                                      0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK                                           0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK                             0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK                                        0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK                                        0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP10
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP11
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP12
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT                                 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT                                 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT                                0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK                                   0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK                                   0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK                                  0x00FF0000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT                                      0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK                                        0x0000FFFFL
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT                                   0x7
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT                                   0x8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT                                 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT                          0xe
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT                                          0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT                                          0x11
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT                                          0x12
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT                                0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT                                          0x15
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT                                          0x16
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT                                           0x17
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT                                   0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT                                        0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT                  0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT               0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT                       0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK                                     0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK                                     0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK                                   0x00003E00L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK                            0x00004000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK                                            0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK                                            0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK                                            0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK                                  0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK                                            0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK                                            0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK                                             0x00800000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK                                     0x07000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK                                          0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK                    0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK                 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK                         0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT                      0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT                                          0x1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT                                       0x2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT                                          0x12
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT                              0x13
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT                                         0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT                                         0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT                        0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT                       0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT                                       0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT                               0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK                        0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK                                            0x00000002L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK                                         0x0003FFFCL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK                                            0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK                                0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK                                           0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK                                           0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK                          0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK                         0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK                                         0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK                                 0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT                                 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT                                       0x15
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT                                          0x16
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT                                     0x17
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT                                   0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT                                  0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK                                   0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK                                         0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK                                            0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK                                       0x0F800000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK                                     0x70000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK                                    0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT                                   0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT                            0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK                                     0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK                              0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT                                        0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT                                  0x2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK                                          0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00000002L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK                                    0x00000004L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP7
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+//RCC_EP_DEV0_1_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
+//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
+//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
+//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                  0x3
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                    0x00000008L
+//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                           0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                             0x20000000L
+//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT                                         0x4
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK                                           0x00000010L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
+//RCC_EP_DEV0_1_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
+//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                            0x8
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                               0x12
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                   0x18
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                   0x19
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                   0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT                                   0x1b
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT                                   0x1c
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT                                   0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT                                   0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT                                   0x1f
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                              0x00000700L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                 0x00040000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                     0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                     0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                     0x04000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK                                     0x08000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK                                     0x10000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK                                     0x20000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK                                     0x40000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK                                     0x80000000L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                          0x0
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                          0x1
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                          0x2
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                            0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                            0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                            0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+//RCC_DWN_DEV0_1_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
+//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
+//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
+//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
+//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                 0x3
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                   0x00000008L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT                                                0x11
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT                                        0x15
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK                                                     0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK                                                  0x00020000L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK                                          0x00E00000L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT                                             0x18
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                          0x1d
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK                                               0x01000000L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                            0x20000000L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT                                    0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK                                      0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                             0x8
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                    0xb
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                               0x00000700L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                      0x00000800L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
+//RCC_DWNP_DEV0_1_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
+//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                           0x0
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                           0x1
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                           0x2
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                             0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                             0x00000002L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                             0x00000004L
+//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                               0x0
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
+//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT                                          0xa
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK                                            0x00000400L
+//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+//RCC_DEV0_1_RCC_ERR_INT_CNTL
+#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT                                0x0
+#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK                                  0x00000001L
+//RCC_DEV0_1_RCC_BACO_CNTL_MISC
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT                                                 0x0
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT                                                  0x1
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK                                                   0x00000001L
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK                                                    0x00000002L
+//RCC_DEV0_1_RCC_RESET_EN
+#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT                                                      0xf
+#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK                                                        0x00008000L
+//RCC_DEV0_1_RCC_VDM_SUPPORT
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT                                                       0x0
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT                                                      0x1
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT                                                  0x2
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT                                        0x3
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT                                    0x4
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK                                                         0x00000001L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK                                                        0x00000002L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK                                                    0x00000004L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK                                          0x00000008L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK                                      0x00000010L
+//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT                                 0x0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT                              0x1
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT                                0x2
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT                                 0x3
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT                           0x4
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT                                  0x5
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT                                 0xb
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT                                 0x12
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT                                0x19
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK                                   0x00000001L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK                                0x00000002L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK                                  0x00000004L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK                                   0x00000008L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK                             0x00000010L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK                                    0x000007E0L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK                                   0x0003F800L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK                                   0x01FC0000L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK                                  0xFE000000L
+//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT                             0x0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT                              0x6
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT                                         0xc
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT                                      0x11
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK                               0x0000003FL
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK                                0x00000FC0L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK                                           0x0001F000L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK                                        0x00FE0000L
+//RCC_DEV0_1_RCC_GPUIOV_REGION
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT                                                       0x0
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT                                                       0x4
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK                                                         0x00000007L
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK                                                         0x00000070L
+//RCC_DEV0_1_RCC_GPU_HOSTVM_EN
+#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT                                                    0x0
+#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK                                                      0x00000001L
+//RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT                              0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT                                    0x1
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK                                0x00000001L
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK                                      0x00000002L
+//RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT                        0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK                          0xFFFFL
+//RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT                                    0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK                                      0xFFFFL
+//RCC_DEV0_1_RCC_PEER_REG_RANGE0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT                                                     0x0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT                                                       0x10
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK                                                       0x0000FFFFL
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK                                                         0xFFFF0000L
+//RCC_DEV0_1_RCC_PEER_REG_RANGE1
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT                                                     0x0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT                                                       0x10
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK                                                       0x0000FFFFL
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK                                                         0xFFFF0000L
+//RCC_DEV0_1_RCC_BUS_CNTL
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT                                                            0x2
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT                                                           0x3
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT                                                            0x4
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT                                                         0x5
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT                                                        0x6
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT                                                         0x7
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT                                                        0x8
+#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT                                                 0xc
+#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT                                           0xd
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x10
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x11
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x12
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x13
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x14
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x15
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT                                                 0x18
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                 0x19
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT                                            0x1c
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                            0x1d
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK                                                              0x00000004L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK                                                             0x00000008L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK                                                              0x00000010L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK                                                           0x00000020L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK                                                          0x00000040L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK                                                           0x00000080L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK                                                          0x00000100L
+#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK                                                   0x00001000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK                                             0x00002000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00010000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00020000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00040000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00080000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00100000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00200000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK                                                   0x01000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK                                                   0x0E000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK                                              0x10000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK                                              0xE0000000L
+//RCC_DEV0_1_RCC_CONFIG_CNTL
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT                                                     0x0
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT                                               0x2
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT                                                        0x3
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK                                                       0x00000001L
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK                                                 0x00000004L
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK                                                          0x00000018L
+//RCC_DEV0_1_RCC_CONFIG_F0_BASE
+#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT                                                         0x0
+#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK                                                           0xFFFFFFFFL
+//RCC_DEV0_1_RCC_CONFIG_APER_SIZE
+#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT                                                     0x0
+#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK                                                       0xFFFFFFFFL
+//RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE
+#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT                                             0x0
+#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK                                               0x07FFFFFFL
+//RCC_DEV0_1_RCC_XDMA_LO
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT                                                   0x0
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT                                                       0x1f
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK                                                     0x7FFFFFFFL
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK                                                         0x80000000L
+//RCC_DEV0_1_RCC_XDMA_HI
+#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT                                                   0x0
+#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK                                                     0x7FFFFFFFL
+//RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT                                   0x7
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT                                 0x8
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT                                    0x9
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT                                    0xa
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT                                 0xb
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT                                  0xc
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT                                      0xd
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT                      0xe
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT                                 0x10
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT                           0x11
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT                               0x12
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT                     0x13
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK                                     0x00000080L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK                                   0x00000100L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK                                      0x00000200L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK                                      0x00000400L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK                                   0x00000800L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK                                    0x00001000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK                                        0x00002000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK                        0x00004000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK                                   0x00010000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK                             0x00020000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK                                 0x00040000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK                       0x00080000L
+//RCC_DEV0_1_RCC_BUSNUM_CNTL1
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT                                                           0x0
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK                                                             0x000000FFL
+//RCC_DEV0_1_RCC_BUSNUM_LIST0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT                                                               0x0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT                                                               0x8
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT                                                               0x10
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT                                                               0x18
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK                                                                 0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK                                                                 0x0000FF00L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK                                                                 0x00FF0000L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK                                                                 0xFF000000L
+//RCC_DEV0_1_RCC_BUSNUM_LIST1
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT                                                               0x0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT                                                               0x8
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT                                                               0x10
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT                                                               0x18
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK                                                                 0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK                                                                 0x0000FF00L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK                                                                 0x00FF0000L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK                                                                 0xFF000000L
+//RCC_DEV0_1_RCC_BUSNUM_CNTL2
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT                                                    0x0
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT                                                     0x8
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT                                                       0x10
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT                                           0x11
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK                                                      0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK                                                       0x00000100L
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK                                                         0x00010000L
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK                                             0x00020000L
+//RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM
+#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT                                                   0x0
+#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK                                                     0x00000001L
+//RCC_DEV0_1_RCC_HOST_BUSNUM
+#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT                                                            0x0
+#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK                                                              0x0000FFFFL
+//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT                                                   0x0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT                                                   0x8
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT                                                   0x10
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT                                                   0x18
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK                                                     0x000000FFL
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK                                                     0x0000FF00L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK                                                     0x00FF0000L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK                                                     0xFF000000L
+//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT                                                   0x0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT                                                   0x8
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT                                                   0x10
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT                                                   0x18
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK                                                     0x000000FFL
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK                                                     0x0000FF00L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK                                                     0x00FF0000L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK                                                     0xFF000000L
+//RCC_DEV0_1_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT                                                  0x0
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT                                                 0x8
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK                                                    0x00000001L
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK                                                   0x00000100L
+//RCC_DEV0_1_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT                                             0x0
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT                                              0x1
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT                                             0x2
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT                                          0x3
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT                                             0x10
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK                                               0x00000001L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK                                                0x00000002L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK                                               0x00000004L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK                                            0x00000008L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK                                               0xFFFF0000L
+//RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT                                            0x0
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT                                            0x8
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK                                              0x000000FFL
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK                                              0x00001F00L
+//RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT                                         0x0
+#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK                                           0x000003FFL
+//RCC_DEV0_1_RCC_MH_ARB_CNTL
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT                                                        0x0
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT                                                0x1
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK                                                          0x00000001L
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK                                                  0x00007FFEL
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+//BIF_BX1_CC_BIF_BX_STRAP0
+#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT                                                       0x19
+#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK                                                         0xFE000000L
+//BIF_BX1_CC_BIF_BX_PINSTRAP0
+//BIF_BX1_BIF_MM_INDACCESS_CNTL
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT                                                0x1
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK                                                  0x00000002L
+//BIF_BX1_BUS_CNTL
+#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT                                                        0x6
+#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT                                                        0x7
+#define BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT                                                                    0xa
+#define BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT                                                                    0xd
+#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT                                                                0x10
+#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT                                                                0x11
+#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT                                                               0x12
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT                                              0x18
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT                                          0x19
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT                                         0x1a
+#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT                                        0x1b
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT                                          0x1c
+#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT                                                     0x1d
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT                                                          0x1e
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT                                                          0x1f
+#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK                                                          0x00000040L
+#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK                                                          0x00000080L
+#define BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK                                                                      0x00001C00L
+#define BIF_BX1_BUS_CNTL__SET_MC_TC_MASK                                                                      0x0000E000L
+#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK                                                                  0x00010000L
+#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK                                                                  0x00020000L
+#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK                                                                 0x00040000L
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK                                                0x01000000L
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK                                            0x02000000L
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK                                           0x04000000L
+#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK                                          0x08000000L
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK                                            0x10000000L
+#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK                                                       0x20000000L
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK                                                            0x40000000L
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK                                                            0x80000000L
+//BIF_BX1_BIF_SCRATCH0
+#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT                                                             0x0
+#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_BIF_SCRATCH1
+#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT                                                             0x0
+#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_BX_RESET_EN
+#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT                                                  0x10
+#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK                                                    0x00010000L
+//BIF_BX1_MM_CFGREGS_CNTL
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT                                                       0x0
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT                                                        0x6
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT                                                       0x1f
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK                                                         0x00000007L
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK                                                          0x000000C0L
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK                                                         0x80000000L
+//BIF_BX1_BX_RESET_CNTL
+#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT                                                           0x0
+#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK                                                             0x00000001L
+//BIF_BX1_INTERRUPT_CNTL
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT                                                   0x0
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT                                                         0x1
+#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT                                                     0x3
+#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT                                                       0x4
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT                                                 0xf
+#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT                                               0x10
+#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT                                   0x11
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT                                              0x12
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK                                                     0x00000001L
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK                                                           0x00000002L
+#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK                                                       0x00000008L
+#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK                                                         0x000000F0L
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK                                                   0x00008000L
+#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK                                                 0x00010000L
+#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK                                     0x00020000L
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK                                                0x00040000L
+//BIF_BX1_INTERRUPT_CNTL2
+#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT                                                      0x0
+#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK                                                        0xFFFFFFFFL
+//BIF_BX1_CLKREQB_PAD_CNTL
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT                                                        0x0
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT                                                      0x1
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT                                                     0x2
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT                                                    0x3
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT                                                      0x5
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT                                                      0x6
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT                                                      0x7
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT                                                      0x8
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT                                                    0x9
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT                                                     0xa
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT                                                   0xb
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT                                                  0xc
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT                                                        0xd
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK                                                          0x00000001L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK                                                        0x00000002L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK                                                       0x00000004L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK                                                      0x00000018L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK                                                        0x00000020L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK                                                        0x00000040L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK                                                        0x00000080L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK                                                        0x00000100L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK                                                      0x00000200L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK                                                       0x00000400L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK                                                     0x00000800L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK                                                    0x00001000L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK                                                          0x00002000L
+//BIF_BX1_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT                                          0x0
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT                                          0x1
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT                                          0x2
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT                                          0x3
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT                             0xb
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT                                      0xc
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT                                          0xd
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT                                           0xf
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT                                           0x10
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT                   0x18
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK                                            0x00000001L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK                                            0x00000002L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK                                            0x00000004L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK                                            0x00000008L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK                               0x00000800L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK                                        0x00001000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK                                            0x00002000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK                                             0x00008000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK                                             0x00FF0000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK                     0x01000000L
+//BIF_BX1_BIF_DOORBELL_CNTL
+#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT                                                       0x0
+#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT                                                     0x1
+#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT                                                    0x2
+#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT                                         0x3
+#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT                                                 0x4
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT                                                  0x18
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT                                               0x19
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT                                               0x1a
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT                                               0x1b
+#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK                                                         0x00000001L
+#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK                                                       0x00000002L
+#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK                                                      0x00000004L
+#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK                                           0x00000008L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK                                                   0x00000010L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK                                                    0x01000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK                                                 0x02000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK                                                 0x04000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK                                                 0x08000000L
+//BIF_BX1_BIF_DOORBELL_INT_CNTL
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT                                       0x0
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT                                      0x1
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT                            0x2
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT                                        0x10
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT                                       0x11
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT                             0x12
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT                                      0x18
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT                                     0x19
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT                           0x1a
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                               0x1c
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1d
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1e
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK                                         0x00000001L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK                                        0x00000002L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK                              0x00000004L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK                                          0x00010000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK                                         0x00020000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK                               0x00040000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK                                        0x01000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK                                       0x02000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK                             0x04000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK                                 0x10000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x20000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x40000000L
+//BIF_BX1_BIF_FB_EN
+#define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT                                                                  0x0
+#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT                                                                 0x1
+#define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK                                                                    0x00000001L
+#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK                                                                   0x00000002L
+//BIF_BX1_BIF_INTR_CNTL
+#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT                                                        0x0
+#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK                                                          0x00000001L
+//BIF_BX1_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                        0x0
+#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                          0x7FFFFFFFL
+//BIF_BX1_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT                                        0x0
+#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK                                          0x7FFFFFFFL
+//BIF_BX1_MEM_TYPE_CNTL
+#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT                                                        0x0
+#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK                                                          0x00000001L
+//BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT                                                     0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT                                                  0x1
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT                                                    0x8
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK                                                       0x00000001L
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK                                                    0x00000002L
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK                                                      0x00000100L
+//BIF_BX1_NBIF_GFX_ADDR_LUT_0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_1
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_2
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_3
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_4
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_5
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_6
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_7
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_8
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_9
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_10
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_11
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_12
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_13
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_14
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_15
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_VF_REGWR_EN
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT                                                           0x0
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT                                                           0x1
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT                                                           0x2
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT                                                           0x3
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT                                                           0x4
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT                                                           0x5
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT                                                           0x6
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT                                                           0x7
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT                                                           0x8
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT                                                           0x9
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT                                                          0xa
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT                                                          0xb
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT                                                          0xc
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT                                                          0xd
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT                                                          0xe
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT                                                          0xf
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT                                                          0x10
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT                                                          0x11
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT                                                          0x12
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT                                                          0x13
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT                                                          0x14
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT                                                          0x15
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT                                                          0x16
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT                                                          0x17
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT                                                          0x18
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT                                                          0x19
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT                                                          0x1a
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT                                                          0x1b
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT                                                          0x1c
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT                                                          0x1d
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT                                                          0x1e
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK                                                             0x00000001L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK                                                             0x00000002L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK                                                             0x00000004L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK                                                             0x00000008L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK                                                             0x00000010L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK                                                             0x00000020L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK                                                             0x00000040L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK                                                             0x00000080L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK                                                             0x00000100L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK                                                             0x00000200L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK                                                            0x00000400L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK                                                            0x00000800L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK                                                            0x00001000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK                                                            0x00002000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK                                                            0x00004000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK                                                            0x00008000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK                                                            0x00010000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK                                                            0x00020000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK                                                            0x00040000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK                                                            0x00080000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK                                                            0x00100000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK                                                            0x00200000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK                                                            0x00400000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK                                                            0x00800000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK                                                            0x01000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK                                                            0x02000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK                                                            0x04000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK                                                            0x08000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK                                                            0x10000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK                                                            0x20000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK                                                            0x40000000L
+//BIF_BX1_VF_DOORBELL_EN
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT                                                     0x0
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT                                                     0x1
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT                                                     0x2
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT                                                     0x3
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT                                                     0x4
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT                                                     0x5
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT                                                     0x6
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT                                                     0x7
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT                                                     0x8
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT                                                     0x9
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT                                                    0xa
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT                                                    0xb
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT                                                    0xc
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT                                                    0xd
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT                                                    0xe
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT                                                    0xf
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT                                                    0x10
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT                                                    0x11
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT                                                    0x12
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT                                                    0x13
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT                                                    0x14
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT                                                    0x15
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT                                                    0x16
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT                                                    0x17
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT                                                    0x18
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT                                                    0x19
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT                                                    0x1a
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT                                                    0x1b
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT                                                    0x1c
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT                                                    0x1d
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT                                                    0x1e
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT                                                 0x1f
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK                                                       0x00000001L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK                                                       0x00000002L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK                                                       0x00000004L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK                                                       0x00000008L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK                                                       0x00000010L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK                                                       0x00000020L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK                                                       0x00000040L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK                                                       0x00000080L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK                                                       0x00000100L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK                                                       0x00000200L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK                                                      0x00000400L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK                                                      0x00000800L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK                                                      0x00001000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK                                                      0x00002000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK                                                      0x00004000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK                                                      0x00008000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK                                                      0x00010000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK                                                      0x00020000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK                                                      0x00040000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK                                                      0x00080000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK                                                      0x00100000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK                                                      0x00200000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK                                                      0x00400000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK                                                      0x00800000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK                                                      0x01000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK                                                      0x02000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK                                                      0x04000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK                                                      0x08000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK                                                      0x10000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK                                                      0x20000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK                                                      0x40000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK                                                   0x80000000L
+//BIF_BX1_VF_FB_EN
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT                                                                 0x0
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT                                                                 0x1
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT                                                                 0x2
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT                                                                 0x3
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT                                                                 0x4
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT                                                                 0x5
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT                                                                 0x6
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT                                                                 0x7
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT                                                                 0x8
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT                                                                 0x9
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT                                                                0xa
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT                                                                0xb
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT                                                                0xc
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT                                                                0xd
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT                                                                0xe
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT                                                                0xf
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT                                                                0x10
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT                                                                0x11
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT                                                                0x12
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT                                                                0x13
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT                                                                0x14
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT                                                                0x15
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT                                                                0x16
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT                                                                0x17
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT                                                                0x18
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT                                                                0x19
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT                                                                0x1a
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT                                                                0x1b
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT                                                                0x1c
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT                                                                0x1d
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT                                                                0x1e
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK                                                                   0x00000001L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK                                                                   0x00000002L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK                                                                   0x00000004L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK                                                                   0x00000008L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK                                                                   0x00000010L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK                                                                   0x00000020L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK                                                                   0x00000040L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK                                                                   0x00000080L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK                                                                   0x00000100L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK                                                                   0x00000200L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK                                                                  0x00000400L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK                                                                  0x00000800L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK                                                                  0x00001000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK                                                                  0x00002000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK                                                                  0x00004000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK                                                                  0x00008000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK                                                                  0x00010000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK                                                                  0x00020000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK                                                                  0x00040000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK                                                                  0x00080000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK                                                                  0x00100000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK                                                                  0x00200000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK                                                                  0x00400000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK                                                                  0x00800000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK                                                                  0x01000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK                                                                  0x02000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK                                                                  0x04000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK                                                                  0x08000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK                                                                  0x10000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK                                                                  0x20000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK                                                                  0x40000000L
+//BIF_BX1_VF_REGWR_STATUS
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT                                                   0x0
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT                                                   0x1
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT                                                   0x2
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT                                                   0x3
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT                                                   0x4
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT                                                   0x5
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT                                                   0x6
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT                                                   0x7
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT                                                   0x8
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT                                                   0x9
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT                                                  0xa
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT                                                  0xb
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT                                                  0xc
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT                                                  0xd
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT                                                  0xe
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT                                                  0xf
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT                                                  0x10
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT                                                  0x11
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT                                                  0x12
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT                                                  0x13
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT                                                  0x14
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT                                                  0x15
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT                                                  0x16
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT                                                  0x17
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT                                                  0x18
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT                                                  0x19
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT                                                  0x1a
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT                                                  0x1b
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT                                                  0x1c
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT                                                  0x1d
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT                                                  0x1e
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK                                                     0x00000001L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK                                                     0x00000002L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK                                                     0x00000004L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK                                                     0x00000008L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK                                                     0x00000010L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK                                                     0x00000020L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK                                                     0x00000040L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK                                                     0x00000080L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK                                                     0x00000100L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK                                                     0x00000200L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK                                                    0x00000400L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK                                                    0x00000800L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK                                                    0x00001000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK                                                    0x00002000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK                                                    0x00004000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK                                                    0x00008000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK                                                    0x00010000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK                                                    0x00020000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK                                                    0x00040000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK                                                    0x00080000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK                                                    0x00100000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK                                                    0x00200000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK                                                    0x00400000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK                                                    0x00800000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK                                                    0x01000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK                                                    0x02000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK                                                    0x04000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK                                                    0x08000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK                                                    0x10000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK                                                    0x20000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK                                                    0x40000000L
+//BIF_BX1_VF_DOORBELL_STATUS
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT                                             0x0
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT                                             0x1
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT                                             0x2
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT                                             0x3
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT                                             0x4
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT                                             0x5
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT                                             0x6
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT                                             0x7
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT                                             0x8
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT                                             0x9
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT                                            0xa
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT                                            0xb
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT                                            0xc
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT                                            0xd
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT                                            0xe
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT                                            0xf
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT                                            0x10
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT                                            0x11
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT                                            0x12
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT                                            0x13
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT                                            0x14
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT                                            0x15
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT                                            0x16
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT                                            0x17
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT                                            0x18
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT                                            0x19
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT                                            0x1a
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT                                            0x1b
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT                                            0x1c
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT                                            0x1d
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT                                            0x1e
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK                                               0x00000001L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK                                               0x00000002L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK                                               0x00000004L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK                                               0x00000008L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK                                               0x00000010L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK                                               0x00000020L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK                                               0x00000040L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK                                               0x00000080L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK                                               0x00000100L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK                                               0x00000200L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK                                              0x00000400L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK                                              0x00000800L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK                                              0x00001000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK                                              0x00002000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK                                              0x00004000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK                                              0x00008000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK                                              0x00010000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK                                              0x00020000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK                                              0x00040000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK                                              0x00080000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK                                              0x00100000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK                                              0x00200000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK                                              0x00400000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK                                              0x00800000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK                                              0x01000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK                                              0x02000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK                                              0x04000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK                                              0x08000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK                                              0x10000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK                                              0x20000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK                                              0x40000000L
+//BIF_BX1_VF_FB_STATUS
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT                                                         0x0
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT                                                         0x1
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT                                                         0x2
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT                                                         0x3
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT                                                         0x4
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT                                                         0x5
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT                                                         0x6
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT                                                         0x7
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT                                                         0x8
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT                                                         0x9
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT                                                        0xa
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT                                                        0xb
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT                                                        0xc
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT                                                        0xd
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT                                                        0xe
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT                                                        0xf
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT                                                        0x10
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT                                                        0x11
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT                                                        0x12
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT                                                        0x13
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT                                                        0x14
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT                                                        0x15
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT                                                        0x16
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT                                                        0x17
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT                                                        0x18
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT                                                        0x19
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT                                                        0x1a
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT                                                        0x1b
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT                                                        0x1c
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT                                                        0x1d
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT                                                        0x1e
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK                                                           0x00000001L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK                                                           0x00000002L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK                                                           0x00000004L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK                                                           0x00000008L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK                                                           0x00000010L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK                                                           0x00000020L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK                                                           0x00000040L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK                                                           0x00000080L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK                                                           0x00000100L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK                                                           0x00000200L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK                                                          0x00000400L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK                                                          0x00000800L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK                                                          0x00001000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK                                                          0x00002000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK                                                          0x00004000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK                                                          0x00008000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK                                                          0x00010000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK                                                          0x00020000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK                                                          0x00040000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK                                                          0x00080000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK                                                          0x00100000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK                                                          0x00200000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK                                                          0x00400000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK                                                          0x00800000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK                                                          0x01000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK                                                          0x02000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK                                                          0x04000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK                                                          0x08000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK                                                          0x10000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK                                                          0x20000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK                                                          0x40000000L
+//BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
+#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
+//BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
+#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
+//BIF_BX1_BIF_RB_CNTL
+#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT                                                                 0x0
+#define BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT                                                                   0x1
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT                                                     0x8
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT                                                      0x9
+#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT                                                               0x11
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT                                                      0x1a
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT                                                          0x1d
+#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT                                                     0x1e
+#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT                                                       0x1f
+#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK                                                                   0x00000001L
+#define BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK                                                                     0x0000003EL
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK                                                       0x00000100L
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK                                                        0x00003E00L
+#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK                                                                 0x00020000L
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK                                                        0x1C000000L
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK                                                            0x20000000L
+#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK                                                       0x40000000L
+#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK                                                         0x80000000L
+//BIF_BX1_BIF_RB_BASE
+#define BIF_BX1_BIF_RB_BASE__ADDR__SHIFT                                                                      0x0
+#define BIF_BX1_BIF_RB_BASE__ADDR_MASK                                                                        0xFFFFFFFFL
+//BIF_BX1_BIF_RB_RPTR
+#define BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT                                                                    0x2
+#define BIF_BX1_BIF_RB_RPTR__OFFSET_MASK                                                                      0x0003FFFCL
+//BIF_BX1_BIF_RB_WPTR
+#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT                                                           0x0
+#define BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT                                                                    0x2
+#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK                                                             0x00000001L
+#define BIF_BX1_BIF_RB_WPTR__OFFSET_MASK                                                                      0x0003FFFCL
+//BIF_BX1_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK                                                                0x000000FFL
+//BIF_BX1_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT                                                              0x2
+#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK                                                                0xFFFFFFFCL
+//BIF_BX1_MAILBOX_INDEX
+#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT                                                           0x0
+#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK                                                             0x0000001FL
+//BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE
+#define BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT                                         0x0
+#define BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK                                           0x0000000FL
+//BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE
+#define BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT                                         0x0
+#define BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK                                           0x0000000FL
+//BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT                                 0x0
+#define BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK                                   0x0000000FL
+//BIF_BX1_BIF_PERSTB_PAD_CNTL
+#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT                                                   0x0
+#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK                                                     0x0000FFFFL
+//BIF_BX1_BIF_PX_EN_PAD_CNTL
+#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT                                                     0x0
+#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK                                                       0x000000FFL
+//BIF_BX1_BIF_REFPADKIN_PAD_CNTL
+#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT                                             0x0
+#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK                                               0x000000FFL
+//BIF_BX1_BIF_CLKREQB_PAD_CNTL
+#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT                                                 0x0
+#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK                                                   0x00FFFFFFL
+//BIF_BX1_BIF_PWRBRK_PAD_CNTL
+#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT                                                   0x0
+#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK                                                     0x000000FFL
+//BIF_BX1_BIF_WAKEB_PAD_CNTL
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT                                                   0x0
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT                                                      0x1
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT                                                         0x2
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT                                                         0x3
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT                                                       0x4
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT                                                     0x5
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT                                                     0x6
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT                                                    0x7
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK                                                     0x00000001L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK                                                        0x00000002L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK                                                           0x00000004L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK                                                           0x00000008L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK                                                         0x00000010L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK                                                       0x00000020L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK                                                       0x00000040L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK                                                      0x00000080L
+//BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT                                                    0x0
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT                                                    0x1
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT                                                  0x2
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT                                                0x3
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT                                                0x4
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT                                              0x5
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK                                                      0x00000001L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK                                                      0x00000002L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK                                                    0x00000004L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK                                                  0x00000008L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK                                                  0x00000010L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK                                                0x00000020L
+//BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID__SHIFT                                        0x0
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH__SHIFT                                      0x1
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID_MASK                                          0x00000001L
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH_MASK                                        0xFFFFFFFEL
+//BIF_BX1_BIF_S5_MEM_POWER_CTRL0
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0__SHIFT                                         0x0
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0_MASK                                           0xFFFFFFFFL
+//BIF_BX1_BIF_S5_MEM_POWER_CTRL1
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32__SHIFT                                        0x0
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL__SHIFT                                             0xa
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32_MASK                                          0x000003FFL
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL_MASK                                               0x00000400L
+//BIF_BX1_BIF_S5_DUMMY_REGS
+#define BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS__SHIFT                                                   0x0
+#define BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF1_BIF_BME_STATUS
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                                      0x0
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                                0x10
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                                        0x00000001L
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                                  0x00010000L
+//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                                0x0
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                             0x1
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                                0x2
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                                    0x3
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                          0x10
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                                       0x11
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                          0x12
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                              0x13
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                                  0x00000001L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                               0x00000002L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                                  0x00000004L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                                      0x00000008L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                            0x00010000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                                         0x00020000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                            0x00040000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                                0x00080000L
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT          0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK            0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT            0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK              0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT                      0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT                    0x1
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT                    0x8
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK                        0x00000001L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK                      0x00000002L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK                      0x000FFF00L
+//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                                    0x0
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                                      0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                                    0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                                      0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT                          0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                            0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT                0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK                  0x00000001L
+//BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT                                                         0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT                                                         0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT                                                         0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT                                                         0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT                                                         0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT                                                         0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT                                                         0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT                                                         0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT                                                         0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT                                                         0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT                                                       0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT                                                       0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT                                                   0xc
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT                                                   0xd
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT                                                   0xe
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT                                                   0xf
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT                                                   0x10
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT                                                   0x11
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT                                                   0x12
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT                                                   0x13
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT                                                   0x14
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT                                                   0x15
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT                                                  0x16
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT                                                  0x17
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT                                                  0x18
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT                                                  0x19
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT                                                  0x1a
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT                                                  0x1b
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT                                                  0x1c
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT                                                  0x1d
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT                                                  0x1e
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT                                                  0x1f
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK                                                           0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK                                                           0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK                                                           0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK                                                           0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK                                                           0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK                                                           0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK                                                           0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK                                                           0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK                                                           0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK                                                           0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK                                                         0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK                                                         0x00000800L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK                                                     0x00001000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK                                                     0x00002000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK                                                     0x00004000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK                                                     0x00008000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK                                                     0x00010000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK                                                     0x00020000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK                                                     0x00040000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK                                                     0x00080000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK                                                     0x00100000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK                                                     0x00200000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK                                                    0x00400000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK                                                    0x00800000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK                                                    0x01000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK                                                    0x02000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK                                                    0x04000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK                                                    0x08000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK                                                    0x10000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK                                                    0x20000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK                                                    0x40000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK                                                    0x80000000L
+//BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT                                                    0x0
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT                                                    0x1
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT                                                    0x2
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT                                                    0x3
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT                                                    0x4
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT                                                    0x5
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT                                                    0x6
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT                                                    0x7
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT                                                    0x8
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT                                                    0x9
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT                                                  0xa
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT                                                  0xb
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT                                              0xc
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT                                              0xd
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT                                              0xe
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT                                              0xf
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT                                              0x10
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT                                              0x11
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT                                              0x12
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT                                              0x13
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT                                              0x14
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT                                              0x15
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT                                             0x16
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT                                             0x17
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT                                             0x18
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT                                             0x19
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT                                             0x1a
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT                                             0x1b
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT                                             0x1c
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT                                             0x1d
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT                                             0x1e
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT                                             0x1f
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK                                                      0x00000001L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK                                                      0x00000002L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK                                                      0x00000004L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK                                                      0x00000008L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK                                                      0x00000010L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK                                                      0x00000020L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK                                                      0x00000040L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK                                                      0x00000080L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK                                                      0x00000100L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK                                                      0x00000200L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK                                                    0x00000400L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK                                                    0x00000800L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK                                                0x00001000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK                                                0x00002000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK                                                0x00004000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK                                                0x00008000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK                                                0x00010000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK                                                0x00020000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK                                                0x00040000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK                                                0x00080000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK                                                0x00100000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK                                                0x00200000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK                                               0x00400000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK                                               0x00800000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK                                               0x01000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK                                               0x02000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK                                               0x04000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK                                               0x08000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK                                               0x10000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK                                               0x20000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK                                               0x40000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK                                               0x80000000L
+//BIF_BX_PF1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                              0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                              0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                              0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                              0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                              0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                              0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                              0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                              0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                              0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                              0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                            0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                            0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                                        0xc
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                                        0xd
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                                        0xe
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                                        0xf
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                                        0x10
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                                        0x11
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                                        0x12
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                                        0x13
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                                        0x14
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                                        0x15
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                                       0x16
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                                       0x17
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                                       0x18
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                                       0x19
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                                       0x1a
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                                       0x1b
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                                       0x1c
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                                       0x1d
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                                       0x1e
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                                       0x1f
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                                0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                                0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                                0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                                0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                                0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                                0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                                0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                                0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                                0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                                0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                              0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                              0x00000800L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                                          0x00001000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                                          0x00002000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                                          0x00004000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                                          0x00008000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                                          0x00010000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                                          0x00020000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                                          0x00040000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                                          0x00080000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                                          0x00100000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                                          0x00200000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                                         0x00400000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                                         0x00800000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                                         0x01000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                                         0x02000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                                         0x04000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                                         0x08000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                                         0x10000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                                         0x20000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                                         0x40000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                                         0x80000000L
+//BIF_BX_PF1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                             0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                             0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                             0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                             0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                             0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                             0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                             0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                             0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                             0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                             0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                           0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                           0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                                       0xc
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                                       0xd
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                                       0xe
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                                       0xf
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                                       0x10
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                                       0x11
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                                       0x12
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                                       0x13
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                                       0x14
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                                       0x15
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                                      0x16
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                                      0x17
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                                      0x18
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                                      0x19
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                                      0x1a
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                                      0x1b
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                                      0x1c
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                                      0x1d
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                                      0x1e
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                                      0x1f
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                               0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                               0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                               0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                               0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                               0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                               0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                               0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                               0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                               0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                               0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                             0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                             0x00000800L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                                         0x00001000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                                         0x00002000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                                         0x00004000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                                         0x00008000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                                         0x00010000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                                         0x00020000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                                         0x00040000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                                         0x00080000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                                         0x00100000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                                         0x00200000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                                        0x00400000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                                        0x00800000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                                        0x01000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                                        0x02000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                                        0x04000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                                        0x08000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                                        0x10000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                                        0x20000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                                        0x40000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                                        0x80000000L
+//BIF_BX_PF1_BIF_TRANS_PENDING
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                            0x0
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                            0x1
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                              0x00000001L
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                              0x00000002L
+//BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                                0x0
+#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                                  0x00000001L
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_CONTROL
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                                      0x0
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                                        0x1
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                                      0x8
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                                        0x9
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                                        0x00000001L
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                          0x00000002L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                                        0x00000100L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                          0x00000200L
+//BIF_BX_PF1_MAILBOX_INT_CNTL
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                                      0x0
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                                        0x1
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                                        0x00000001L
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                          0x00000002L
+//BIF_BX_PF1_BIF_VMHV_MAILBOX
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                                      0x0
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                                    0x1
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                                         0x8
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                                        0xf
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                                         0x10
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                                        0x17
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                          0x18
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                          0x19
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                                        0x00000001L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                                      0x00000002L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                           0x00000F00L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                          0x00008000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                           0x000F0000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                          0x00800000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                            0x01000000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                            0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT                                          0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT                                          0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT                                          0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT                                0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT                                       0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT                                   0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT                            0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT                             0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT                             0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT                                      0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK                                            0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK                                            0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK                                            0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK                                  0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK                                         0x001FFFE0L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK                                     0x00E00000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK                              0x01000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK                               0x0E000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK                               0x70000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK                                        0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT                                       0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT                                   0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK                                         0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK                                     0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT                                 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT                                          0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT                                      0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT                                          0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT                                      0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT                                  0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT                             0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT                                0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT                                    0x9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT                              0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT                      0xd
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT                                    0xe
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT                                            0xf
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT                                    0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT                                    0x11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT                                  0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT                             0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT                                   0x17
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT                              0x1a
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT                                    0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK                                   0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK                                            0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK                                        0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK                                            0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK                                        0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK                                    0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK                               0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK                                  0x00000100L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK                                      0x00000E00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK                                0x00001000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK                        0x00002000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK                                      0x00004000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK                                              0x00008000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK                                      0x00010000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK                                      0x00020000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK                                    0x000C0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK                               0x00700000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK                                     0x03800000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK                                0x1C000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK                                      0xE0000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT                     0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT                                             0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT                                          0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT                                0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT                                          0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT                                  0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT                                   0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT                                     0x9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0xb
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0xe
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT                                         0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT                                      0x1b
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT                                       0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT                                         0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK                       0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK                                               0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK                                            0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK                                  0x00000038L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK                                            0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK                                    0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK                                     0x00000100L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK                                       0x00000600L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x00003800L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK  0x0003C000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x001C0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK  0x01E00000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK                                           0x06000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK                                        0x18000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK                                         0x20000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK                                           0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT                              0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT                              0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT                              0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK                                0xFF000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT                              0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT                        0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT                                 0x11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT                                  0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT                                           0x13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT                                           0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT                                        0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT                                0x16
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT                           0x17
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT                        0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT                        0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT                     0x1a
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT                         0x1b
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT                          0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT                       0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT                                         0x1e
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT                                            0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK                          0x00010000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK                                   0x00020000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK                                    0x00040000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK                                             0x00080000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK                                             0x00100000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK                                          0x00200000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK                                  0x00400000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK                             0x00800000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK                          0x01000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK                          0x02000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK                       0x04000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK                           0x08000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK                            0x10000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK                         0x20000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK                                           0x40000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK                                              0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT                                         0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT                         0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT                      0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                      0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                   0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT     0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT     0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT                              0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT                            0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT                     0x13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK                                           0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK                           0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK                        0x00000020L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                        0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                     0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK       0x00000F00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK       0x0000F000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK                                0x00030000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK                              0x00040000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK                       0x00080000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT                                        0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT                                    0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT                                    0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT                                          0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT                                          0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT                                          0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK                                          0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK                                      0x00000F00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK                                      0x0000F000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK                                            0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK                                            0x1F000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK                                            0xE0000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT                              0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT                              0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT                              0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK                                0xFF000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT                              0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT                                       0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK                                         0xFFFF0000L
+//RCC_DEV1_PORT_STRAP0
+#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT                                                     0x1
+#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT                                                     0x2
+#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT                                                     0x3
+#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT                                           0x4
+#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT                                                  0x5
+#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__SHIFT                                              0x15
+#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT                                       0x18
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT                                        0x19
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT                                        0x1c
+#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT                                                 0x1f
+#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1_MASK                                                       0x00000002L
+#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1_MASK                                                       0x00000004L
+#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1_MASK                                                       0x00000008L
+#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1_MASK                                             0x00000010L
+#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1_MASK                                                    0x001FFFE0L
+#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1_MASK                                                0x00E00000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1_MASK                                         0x01000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1_MASK                                          0x0E000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1_MASK                                          0x70000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1_MASK                                                   0x80000000L
+//RCC_DEV1_PORT_STRAP1
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT                                                  0x0
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT                                              0x10
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1_MASK                                                    0x0000FFFFL
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1_MASK                                                0xFFFF0000L
+//RCC_DEV1_PORT_STRAP2
+#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT                                            0x0
+#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT                                                     0x1
+#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT                                                 0x2
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT                                                     0x3
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT                                                 0x4
+#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT                                             0x6
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT                                        0x7
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT                                           0x8
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT                                               0x9
+#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT                                         0xc
+#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT                                 0xd
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT                                               0xe
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT                                                       0xf
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT                                               0x10
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV1__SHIFT                                               0x11
+#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT                                             0x12
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT                                        0x14
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT                                              0x17
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT                                         0x1a
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT                                               0x1d
+#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1_MASK                                              0x00000001L
+#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1_MASK                                                       0x00000002L
+#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1_MASK                                                   0x00000004L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1_MASK                                                       0x00000008L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1_MASK                                                   0x00000010L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1_MASK                                               0x00000040L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1_MASK                                          0x00000080L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1_MASK                                             0x00000100L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1_MASK                                                 0x00000E00L
+#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1_MASK                                           0x00001000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1_MASK                                   0x00002000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1_MASK                                                 0x00004000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1_MASK                                                         0x00008000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1_MASK                                                 0x00010000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV1_MASK                                                 0x00020000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1_MASK                                               0x000C0000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1_MASK                                          0x00700000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1_MASK                                                0x03800000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1_MASK                                           0x1C000000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1_MASK                                                 0xE0000000L
+//RCC_DEV1_PORT_STRAP3
+#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT                                0x0
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT                                                        0x1
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT                                                     0x2
+#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT                                           0x3
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT                                                     0x6
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT                                             0x7
+#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT                                              0x8
+#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT                                                0x9
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT    0xb
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT         0xe
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT      0x12
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT           0x15
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT                                                    0x19
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT                                                 0x1b
+#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT                                                  0x1d
+#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT                                                    0x1f
+#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1_MASK                                  0x00000001L
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1_MASK                                                          0x00000002L
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1_MASK                                                       0x00000004L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1_MASK                                             0x00000038L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1_MASK                                                       0x00000040L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1_MASK                                               0x00000080L
+#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1_MASK                                                0x00000100L
+#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1_MASK                                                  0x00000600L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK      0x00003800L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1_MASK           0x0003C000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK        0x001C0000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1_MASK             0x01E00000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1_MASK                                                      0x06000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1_MASK                                                   0x18000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1_MASK                                                    0x20000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1_MASK                                                      0x80000000L
+//RCC_DEV1_PORT_STRAP4
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT                                         0x0
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT                                         0x8
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT                                         0x10
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT                                         0x18
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1_MASK                                           0x000000FFL
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1_MASK                                           0x0000FF00L
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1_MASK                                           0x00FF0000L
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1_MASK                                           0xFF000000L
+//RCC_DEV1_PORT_STRAP5
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT                                         0x0
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT                                         0x8
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT                                   0x10
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT                                            0x11
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT                                             0x12
+#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT                                                      0x13
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT                                                      0x14
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT                                                   0x15
+#define RCC_DEV1_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV1__SHIFT                                           0x16
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT                                      0x17
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT                                   0x18
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT                                   0x19
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT                                0x1a
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT                                    0x1b
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT                                     0x1c
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT                                  0x1d
+#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT                                                    0x1e
+#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT                                                       0x1f
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1_MASK                                           0x000000FFL
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1_MASK                                           0x0000FF00L
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1_MASK                                     0x00010000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1_MASK                                              0x00020000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1_MASK                                               0x00040000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1_MASK                                                        0x00080000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1_MASK                                                        0x00100000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1_MASK                                                     0x00200000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV1_MASK                                             0x00400000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1_MASK                                        0x00800000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1_MASK                                     0x01000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1_MASK                                     0x02000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1_MASK                                  0x04000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1_MASK                                      0x08000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1_MASK                                       0x10000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1_MASK                                    0x20000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1_MASK                                                      0x40000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1_MASK                                                         0x80000000L
+//RCC_DEV1_PORT_STRAP6
+#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT                                                    0x0
+#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT                                    0x1
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV1__SHIFT                                     0x3
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV1__SHIFT                                     0x4
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV1__SHIFT                                 0x5
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV1__SHIFT                                 0x6
+#define RCC_DEV1_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV1__SHIFT                              0x7
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV1__SHIFT                0x8
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV1__SHIFT                0xc
+#define RCC_DEV1_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV1__SHIFT                                         0x10
+#define RCC_DEV1_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV1__SHIFT                                       0x12
+#define RCC_DEV1_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV1__SHIFT                                0x13
+#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1_MASK                                                      0x00000001L
+#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1_MASK                                      0x00000002L
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV1_MASK                                       0x00000008L
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV1_MASK                                       0x00000010L
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV1_MASK                                   0x00000020L
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV1_MASK                                   0x00000040L
+#define RCC_DEV1_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV1_MASK                                0x00000080L
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV1_MASK                  0x00000F00L
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV1_MASK                  0x0000F000L
+#define RCC_DEV1_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV1_MASK                                           0x00030000L
+#define RCC_DEV1_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV1_MASK                                         0x00040000L
+#define RCC_DEV1_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV1_MASK                                  0x00080000L
+//RCC_DEV1_PORT_STRAP7
+#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT                                                   0x0
+#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT                                               0x8
+#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT                                               0xc
+#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT                                                     0x10
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT                                                     0x18
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT                                                     0x1d
+#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1_MASK                                                     0x000000FFL
+#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1_MASK                                                 0x00000F00L
+#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1_MASK                                                 0x0000F000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1_MASK                                                       0x00FF0000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1_MASK                                                       0x1F000000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1_MASK                                                       0xE0000000L
+//RCC_DEV1_PORT_STRAP8
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV1__SHIFT                                         0x0
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV1__SHIFT                                         0x8
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV1__SHIFT                                         0x10
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV1__SHIFT                                         0x18
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV1_MASK                                           0x000000FFL
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV1_MASK                                           0x0000FF00L
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV1_MASK                                           0x00FF0000L
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV1_MASK                                           0xFF000000L
+//RCC_DEV1_PORT_STRAP9
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV1__SHIFT                                         0x0
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV1__SHIFT                                         0x8
+#define RCC_DEV1_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV1__SHIFT                                                  0x10
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV1_MASK                                           0x000000FFL
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV1_MASK                                           0x0000FF00L
+#define RCC_DEV1_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV1_MASK                                                    0xFFFF0000L
+//RCC_DEV2_PORT_STRAP0
+#define RCC_DEV2_PORT_STRAP0__STRAP_ARI_EN_DN_DEV2__SHIFT                                                     0x1
+#define RCC_DEV2_PORT_STRAP0__STRAP_ACS_EN_DN_DEV2__SHIFT                                                     0x2
+#define RCC_DEV2_PORT_STRAP0__STRAP_AER_EN_DN_DEV2__SHIFT                                                     0x3
+#define RCC_DEV2_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV2__SHIFT                                           0x4
+#define RCC_DEV2_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV2__SHIFT                                                  0x5
+#define RCC_DEV2_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV2__SHIFT                                              0x15
+#define RCC_DEV2_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV2__SHIFT                                       0x18
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV2__SHIFT                                        0x19
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV2__SHIFT                                        0x1c
+#define RCC_DEV2_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV2__SHIFT                                                 0x1f
+#define RCC_DEV2_PORT_STRAP0__STRAP_ARI_EN_DN_DEV2_MASK                                                       0x00000002L
+#define RCC_DEV2_PORT_STRAP0__STRAP_ACS_EN_DN_DEV2_MASK                                                       0x00000004L
+#define RCC_DEV2_PORT_STRAP0__STRAP_AER_EN_DN_DEV2_MASK                                                       0x00000008L
+#define RCC_DEV2_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV2_MASK                                             0x00000010L
+#define RCC_DEV2_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV2_MASK                                                    0x001FFFE0L
+#define RCC_DEV2_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV2_MASK                                                0x00E00000L
+#define RCC_DEV2_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV2_MASK                                         0x01000000L
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV2_MASK                                          0x0E000000L
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV2_MASK                                          0x70000000L
+#define RCC_DEV2_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV2_MASK                                                   0x80000000L
+//RCC_DEV2_PORT_STRAP1
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV2__SHIFT                                                  0x0
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV2__SHIFT                                              0x10
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV2_MASK                                                    0x0000FFFFL
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV2_MASK                                                0xFFFF0000L
+//RCC_DEV2_PORT_STRAP2
+#define RCC_DEV2_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV2__SHIFT                                            0x0
+#define RCC_DEV2_PORT_STRAP2__STRAP_DSN_EN_DN_DEV2__SHIFT                                                     0x1
+#define RCC_DEV2_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV2__SHIFT                                                 0x2
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECN1P1_EN_DEV2__SHIFT                                                     0x3
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV2__SHIFT                                                 0x4
+#define RCC_DEV2_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV2__SHIFT                                             0x6
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV2__SHIFT                                        0x7
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV2__SHIFT                                           0x8
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV2__SHIFT                                               0x9
+#define RCC_DEV2_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV2__SHIFT                                         0xc
+#define RCC_DEV2_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV2__SHIFT                                 0xd
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV2__SHIFT                                               0xe
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_EN_DEV2__SHIFT                                                       0xf
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV2__SHIFT                                               0x10
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV2__SHIFT                                               0x11
+#define RCC_DEV2_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV2__SHIFT                                             0x12
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV2__SHIFT                                        0x14
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV2__SHIFT                                              0x17
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV2__SHIFT                                         0x1a
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV2__SHIFT                                               0x1d
+#define RCC_DEV2_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV2_MASK                                              0x00000001L
+#define RCC_DEV2_PORT_STRAP2__STRAP_DSN_EN_DN_DEV2_MASK                                                       0x00000002L
+#define RCC_DEV2_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV2_MASK                                                   0x00000004L
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECN1P1_EN_DEV2_MASK                                                       0x00000008L
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV2_MASK                                                   0x00000010L
+#define RCC_DEV2_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV2_MASK                                               0x00000040L
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV2_MASK                                          0x00000080L
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV2_MASK                                             0x00000100L
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV2_MASK                                                 0x00000E00L
+#define RCC_DEV2_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV2_MASK                                           0x00001000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV2_MASK                                   0x00002000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV2_MASK                                                 0x00004000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_EN_DEV2_MASK                                                         0x00008000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV2_MASK                                                 0x00010000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV2_MASK                                                 0x00020000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV2_MASK                                               0x000C0000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV2_MASK                                          0x00700000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV2_MASK                                                0x03800000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV2_MASK                                           0x1C000000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV2_MASK                                                 0xE0000000L
+//RCC_DEV2_PORT_STRAP3
+#define RCC_DEV2_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV2__SHIFT                                0x0
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DEV2__SHIFT                                                        0x1
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DN_DEV2__SHIFT                                                     0x2
+#define RCC_DEV2_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV2__SHIFT                                           0x3
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSI_EN_DN_DEV2__SHIFT                                                     0x6
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV2__SHIFT                                             0x7
+#define RCC_DEV2_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV2__SHIFT                                              0x8
+#define RCC_DEV2_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV2__SHIFT                                                0x9
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV2__SHIFT    0xb
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV2__SHIFT         0xe
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV2__SHIFT      0x12
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV2__SHIFT           0x15
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DEV2__SHIFT                                                    0x19
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV2__SHIFT                                                 0x1b
+#define RCC_DEV2_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV2__SHIFT                                                  0x1d
+#define RCC_DEV2_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV2__SHIFT                                                    0x1f
+#define RCC_DEV2_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV2_MASK                                  0x00000001L
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DEV2_MASK                                                          0x00000002L
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DN_DEV2_MASK                                                       0x00000004L
+#define RCC_DEV2_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV2_MASK                                             0x00000038L
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSI_EN_DN_DEV2_MASK                                                       0x00000040L
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV2_MASK                                               0x00000080L
+#define RCC_DEV2_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV2_MASK                                                0x00000100L
+#define RCC_DEV2_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV2_MASK                                                  0x00000600L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV2_MASK      0x00003800L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV2_MASK           0x0003C000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV2_MASK        0x001C0000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV2_MASK             0x01E00000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DEV2_MASK                                                      0x06000000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV2_MASK                                                   0x18000000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV2_MASK                                                    0x20000000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV2_MASK                                                      0x80000000L
+//RCC_DEV2_PORT_STRAP4
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV2__SHIFT                                         0x0
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV2__SHIFT                                         0x8
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV2__SHIFT                                         0x10
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV2__SHIFT                                         0x18
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV2_MASK                                           0x000000FFL
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV2_MASK                                           0x0000FF00L
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV2_MASK                                           0x00FF0000L
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV2_MASK                                           0xFF000000L
+//RCC_DEV2_PORT_STRAP5
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV2__SHIFT                                         0x0
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV2__SHIFT                                         0x8
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV2__SHIFT                                   0x10
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV2__SHIFT                                            0x11
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV2__SHIFT                                             0x12
+#define RCC_DEV2_PORT_STRAP5__STRAP_VC_EN_DN_DEV2__SHIFT                                                      0x13
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DEV2__SHIFT                                                      0x14
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV2__SHIFT                                                   0x15
+#define RCC_DEV2_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV2__SHIFT                                           0x16
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV2__SHIFT                                      0x17
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV2__SHIFT                                   0x18
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV2__SHIFT                                   0x19
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV2__SHIFT                                0x1a
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV2__SHIFT                                    0x1b
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV2__SHIFT                                     0x1c
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV2__SHIFT                                  0x1d
+#define RCC_DEV2_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV2__SHIFT                                                    0x1e
+#define RCC_DEV2_PORT_STRAP5__STRAP_SSID_EN_DEV2__SHIFT                                                       0x1f
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV2_MASK                                           0x000000FFL
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV2_MASK                                           0x0000FF00L
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV2_MASK                                     0x00010000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV2_MASK                                              0x00020000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV2_MASK                                               0x00040000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_VC_EN_DN_DEV2_MASK                                                        0x00080000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DEV2_MASK                                                        0x00100000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV2_MASK                                                     0x00200000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV2_MASK                                             0x00400000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV2_MASK                                        0x00800000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV2_MASK                                     0x01000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV2_MASK                                     0x02000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV2_MASK                                  0x04000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV2_MASK                                      0x08000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV2_MASK                                       0x10000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV2_MASK                                    0x20000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV2_MASK                                                      0x40000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_SSID_EN_DEV2_MASK                                                         0x80000000L
+//RCC_DEV2_PORT_STRAP6
+#define RCC_DEV2_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV2__SHIFT                                                    0x0
+#define RCC_DEV2_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV2__SHIFT                                    0x1
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV2__SHIFT                                     0x3
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV2__SHIFT                                     0x4
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV2__SHIFT                                 0x5
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV2__SHIFT                                 0x6
+#define RCC_DEV2_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV2__SHIFT                              0x7
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV2__SHIFT                0x8
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV2__SHIFT                0xc
+#define RCC_DEV2_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV2__SHIFT                                         0x10
+#define RCC_DEV2_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV2__SHIFT                                       0x12
+#define RCC_DEV2_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV2__SHIFT                                0x13
+#define RCC_DEV2_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV2_MASK                                                      0x00000001L
+#define RCC_DEV2_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV2_MASK                                      0x00000002L
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV2_MASK                                       0x00000008L
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV2_MASK                                       0x00000010L
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV2_MASK                                   0x00000020L
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV2_MASK                                   0x00000040L
+#define RCC_DEV2_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV2_MASK                                0x00000080L
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV2_MASK                  0x00000F00L
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV2_MASK                  0x0000F000L
+#define RCC_DEV2_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV2_MASK                                           0x00030000L
+#define RCC_DEV2_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV2_MASK                                         0x00040000L
+#define RCC_DEV2_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV2_MASK                                  0x00080000L
+//RCC_DEV2_PORT_STRAP7
+#define RCC_DEV2_PORT_STRAP7__STRAP_PORT_NUMBER_DEV2__SHIFT                                                   0x0
+#define RCC_DEV2_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV2__SHIFT                                               0x8
+#define RCC_DEV2_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV2__SHIFT                                               0xc
+#define RCC_DEV2_PORT_STRAP7__STRAP_RP_BUSNUM_DEV2__SHIFT                                                     0x10
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_DEVNUM_DEV2__SHIFT                                                     0x18
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_FUNCID_DEV2__SHIFT                                                     0x1d
+#define RCC_DEV2_PORT_STRAP7__STRAP_PORT_NUMBER_DEV2_MASK                                                     0x000000FFL
+#define RCC_DEV2_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV2_MASK                                                 0x00000F00L
+#define RCC_DEV2_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV2_MASK                                                 0x0000F000L
+#define RCC_DEV2_PORT_STRAP7__STRAP_RP_BUSNUM_DEV2_MASK                                                       0x00FF0000L
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_DEVNUM_DEV2_MASK                                                       0x1F000000L
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_FUNCID_DEV2_MASK                                                       0xE0000000L
+//RCC_DEV2_PORT_STRAP8
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV2__SHIFT                                         0x0
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV2__SHIFT                                         0x8
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV2__SHIFT                                         0x10
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV2__SHIFT                                         0x18
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV2_MASK                                           0x000000FFL
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV2_MASK                                           0x0000FF00L
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV2_MASK                                           0x00FF0000L
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV2_MASK                                           0xFF000000L
+//RCC_DEV2_PORT_STRAP9
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV2__SHIFT                                         0x0
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV2__SHIFT                                         0x8
+#define RCC_DEV2_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV2__SHIFT                                                  0x10
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV2_MASK                                           0x000000FFL
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV2_MASK                                           0x0000FF00L
+#define RCC_DEV2_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV2_MASK                                                    0xFFFF0000L
+//RCC_STRAP2_RCC_BIF_STRAP0
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT                                                  0x0
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT                                                   0x2
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT                                               0x3
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT                                               0x6
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT                                                    0x7
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT                                                 0x8
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT                                  0x9
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT                                         0xa
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT                                     0xb
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT                                              0xc
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT                                             0xd
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                     0xe
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                  0xf
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT                                              0x10
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT                                           0x11
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT                                                      0x18
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT                                                 0x19
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT                                                0x1a
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT                                      0x1d
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT                                                   0x1e
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT                                            0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK                                                    0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK                                                     0x00000004L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK                                                 0x00000038L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK                                                 0x00000040L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK                                                      0x00000080L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK                                                   0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK                                    0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK                                           0x00000400L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK                                       0x00000800L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK                                                0x00001000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK                                               0x00002000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                       0x00004000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                    0x00008000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK                                                0x00010000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK                                             0x00020000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK                                                        0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK                                                   0x02000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK                                                  0x04000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK                                       0x08000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK                                        0x20000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK                                                     0x40000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK                                              0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP1
+#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT                                                      0x1
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT                                      0x3
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT                                     0x5
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                       0x6
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT                                               0x7
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT                                                  0x8
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT                                                 0x9
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT                                                  0xa
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT                                        0xc
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT                                                    0xd
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT                                                    0xf
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT                                             0x11
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT                                             0x12
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT                                                        0x13
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT                                                   0x14
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT                                                     0x15
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT                                             0x16
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT                                     0x17
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT                                             0x1a
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT                                       0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT                                                     0x1d
+#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK                                                        0x00000002L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK                                        0x00000008L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK                                       0x00000020L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK                                         0x00000040L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK                                                 0x00000080L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK                                                    0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK                                                   0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK                                                    0x00000C00L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK                                          0x00001000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK                                                      0x00006000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK                                                      0x00018000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK                                               0x00020000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK                                               0x00040000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK                                                          0x00080000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK                                                     0x00100000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK                                                       0x00200000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK                                               0x00400000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK                                       0x00800000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK                                               0x04000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK                                         0x18000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK                                                       0x20000000L
+//RCC_STRAP2_RCC_BIF_STRAP2
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT                                     0x0
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT                                            0x3
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT                                            0x4
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT                                        0x5
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT                                      0x6
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT                                 0x8
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT                                        0x9
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT                                   0xa
+#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT                                                 0xd
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT                                             0xe
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT                                 0xf
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT                                         0x10
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT                                        0x18
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT                            0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK                                       0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK                                              0x00000008L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK                                              0x00000010L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK                                          0x00000020L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK                                        0x00000040L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK                                   0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK                                          0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK                                     0x00000C00L
+#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK                                                   0x00002000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK                                               0x00004000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK                                   0x00008000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK                                           0x00FF0000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK                                          0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK                              0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP3
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT                                         0x0
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT                                       0x10
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK                                         0xFFFF0000L
+//RCC_STRAP2_RCC_BIF_STRAP4
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT                                          0x0
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT                                           0x10
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK                                            0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK                                             0xFFFF0000L
+//RCC_STRAP2_RCC_BIF_STRAP5
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT                                         0x0
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT                                      0x10
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT                                   0x11
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT                                    0x12
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT                                        0x13
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT                                    0x14
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT                                         0x16
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT                          0x18
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x19
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT                                           0x1c
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK                                        0x00010000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK                                     0x00020000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK                                      0x00040000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK                                          0x00080000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK                                      0x00100000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK                                           0x00C00000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK                            0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x06000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x08000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK                                             0x70000000L
+//RCC_STRAP2_RCC_BIF_STRAP6
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT                       0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK                                0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK                         0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT                                        0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT                                 0x1
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT                                       0x6
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT                                   0x7
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT                                 0x9
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT                          0xe
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT                                          0xf
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT                                          0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT                                          0x11
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT                                0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT                                          0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT                                           0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT                                   0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT                                     0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT                                        0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT                  0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT               0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT                       0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK                                          0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK                                   0x0000003EL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK                                         0x00000040L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK                                     0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK                                   0x00003E00L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK                            0x00004000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK                                            0x00008000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK                                            0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK                                            0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK                                  0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK                                            0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK                                             0x00800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK                                     0x07000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK                                       0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK                                          0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK                    0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK                 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK                         0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT                      0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT                                          0x1
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT                                       0x2
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT                              0x13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT                                         0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT                                  0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT                                         0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT                        0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT                       0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT                                0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT                                       0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT                               0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK                        0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK                                            0x00000002L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK                                         0x0003FFFCL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK                                0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK                                           0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK                                    0x00E00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK                                           0x01000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK                          0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK                         0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK                                  0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK                                         0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK                                 0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT                                       0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT                                     0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT                                   0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT                                  0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK                                   0x000003FFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK                                         0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK                                       0x0F800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK                                     0x70000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK                                    0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT                                   0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT                            0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK                                     0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK                              0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT                                0x3
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT                                     0x4
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT                                      0x7
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT                                     0x9
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT                                     0xd
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                           0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT                                  0x13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT                                  0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT                                         0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT                                0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT                           0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK                                0x00000007L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK                                  0x00000008L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK                                       0x00000070L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK                                        0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK                                       0x00001E00L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK                                       0x0000E000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK                             0x00070000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK                                    0x00780000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK                                    0x03800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK                                           0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK                                  0x38000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK                             0xC0000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT                           0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT                               0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT                        0x13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT                                    0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT                                 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT                                 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK                             0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK                                 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK                          0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK                                      0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK                                   0x00C00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK                                   0x0F000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT                                 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT                                0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK                                   0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK                                   0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK                                  0x00FF0000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT                                      0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK                                        0x0000FFFFL
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT                                       0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT                                    0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT                                    0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT                                         0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT                           0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT                                      0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT                                      0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK                                         0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK                                      0x000F0000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK                                      0x00F00000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK                                           0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK                             0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK                                        0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK                                        0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT                                   0x7
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT                                   0x8
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT                                 0x9
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT                          0xe
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT                                          0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT                                          0x11
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT                                          0x12
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT                                0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT                                          0x15
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT                                          0x16
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT                                           0x17
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT                                   0x18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT                                        0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT                  0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT               0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT                       0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK                                     0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK                                     0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK                                   0x00003E00L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK                            0x00004000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK                                            0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK                                            0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK                                            0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK                                  0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK                                            0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK                                            0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK                                             0x00800000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK                                     0x07000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK                                          0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK                    0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK                 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK                         0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT                      0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT                                          0x1
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT                                       0x2
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT                                          0x12
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT                              0x13
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT                                         0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT                                         0x18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT                        0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT                       0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT                                       0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT                               0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK                        0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK                                            0x00000002L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK                                         0x0003FFFCL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK                                            0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK                                0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK                                           0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK                                           0x01000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK                          0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK                         0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK                                         0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK                                 0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT                                 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT                                       0x15
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT                                          0x16
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT                                     0x17
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT                                   0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT                                  0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK                                   0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK                                         0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK                                            0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK                                       0x0F800000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK                                     0x70000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK                                    0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT                                   0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT                            0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK                                     0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK                              0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT                                        0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x1
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT                                  0x2
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK                                          0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00000002L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK                                    0x00000004L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP7
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP10
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP11
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP12
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT                                 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT                                 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT                                0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK                                   0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK                                   0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK                                  0x00FF0000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT                                      0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK                                        0x0000FFFFL
+//RCC_DEV0_EPF2_STRAP0
+#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT                                                  0x0
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT                                               0x10
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT                                               0x14
+#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT                                                    0x1c
+#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT                                      0x1d
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT                                                 0x1e
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT                                                 0x1f
+#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2_MASK                                                    0x0000FFFFL
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2_MASK                                                 0x000F0000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2_MASK                                                 0x00F00000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2_MASK                                                      0x10000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_MASK                                        0x20000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2_MASK                                                   0x40000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2_MASK                                                   0x80000000L
+//RCC_DEV0_EPF2_STRAP2
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT                                              0x7
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT                                              0x8
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2__SHIFT                                            0x9
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT                                     0xe
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT                                                     0x10
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT                                                     0x11
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT                                           0x14
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT                                                     0x15
+#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT                                                      0x17
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT                                              0x18
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2__SHIFT                                                   0x1c
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2__SHIFT                             0x1d
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2__SHIFT                          0x1e
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2__SHIFT                                  0x1f
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK                                                0x00000080L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2_MASK                                                0x00000100L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2_MASK                                              0x00003E00L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_MASK                                       0x00004000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2_MASK                                                       0x00010000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2_MASK                                                       0x00020000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2_MASK                                             0x00100000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2_MASK                                                       0x00200000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2_MASK                                                        0x00800000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2_MASK                                                0x07000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2_MASK                                                     0x10000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2_MASK                               0x20000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2_MASK                            0x40000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2_MASK                                    0x80000000L
+//RCC_DEV0_EPF2_STRAP3
+#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT                                 0x0
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT                                                     0x1
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT                                                  0x2
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT                                                     0x12
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT                                         0x13
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT                                                    0x14
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT                                                    0x18
+#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT                                   0x1a
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT                                  0x1b
+#define RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2__SHIFT                                                  0x1d
+#define RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2__SHIFT                                          0x1e
+#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_MASK                                   0x00000001L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2_MASK                                                       0x00000002L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2_MASK                                                    0x0003FFFCL
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2_MASK                                                       0x00040000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2_MASK                                           0x00080000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2_MASK                                                      0x00100000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2_MASK                                                      0x01000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_MASK                                     0x04000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_MASK                                    0x08000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2_MASK                                                    0x20000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2_MASK                                            0x40000000L
+//RCC_DEV0_EPF2_STRAP4
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT                                            0x14
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT                                                  0x15
+#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT                                                     0x16
+#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT                                                0x17
+#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT                                              0x1c
+#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT                                             0x1f
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2_MASK                                              0x00100000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2_MASK                                                    0x00200000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2_MASK                                                       0x00400000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2_MASK                                                  0x0F800000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2_MASK                                                0x70000000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2_MASK                                               0x80000000L
+//RCC_DEV0_EPF2_STRAP5
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT                                              0x0
+#define RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2__SHIFT                                       0x1e
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2_MASK                                                0x0000FFFFL
+#define RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2_MASK                                         0x40000000L
+//RCC_DEV0_EPF2_STRAP6
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT                                                   0x0
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT                                      0x1
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT                                                   0x8
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__SHIFT                                      0x9
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2_MASK                                                     0x00000001L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2_MASK                                        0x00000002L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2_MASK                                                     0x00000100L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2_MASK                                        0x00000200L
+//RCC_DEV0_EPF2_STRAP7
+//RCC_DEV0_EPF2_STRAP10
+//RCC_DEV0_EPF2_STRAP11
+//RCC_DEV0_EPF2_STRAP12
+//RCC_DEV0_EPF2_STRAP13
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT                                            0x0
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT                                            0x8
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT                                           0x10
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2_MASK                                              0x000000FFL
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2_MASK                                              0x0000FF00L
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2_MASK                                             0x00FF0000L
+//RCC_DEV0_EPF2_STRAP14
+#define RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2__SHIFT                                                 0x0
+#define RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2_MASK                                                   0x0000FFFFL
+//RCC_DEV0_EPF3_STRAP0
+#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT                                                  0x0
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT                                               0x10
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT                                               0x14
+#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT                                                    0x1c
+#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT                                      0x1d
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT                                                 0x1e
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT                                                 0x1f
+#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3_MASK                                                    0x0000FFFFL
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3_MASK                                                 0x000F0000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3_MASK                                                 0x00F00000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3_MASK                                                      0x10000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_MASK                                        0x20000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3_MASK                                                   0x40000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3_MASK                                                   0x80000000L
+//RCC_DEV0_EPF3_STRAP2
+#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT                                              0x7
+#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT                                              0x8
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3__SHIFT                                            0x9
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT                                     0xe
+#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT                                                     0x10
+#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT                                                     0x11
+#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT                                           0x14
+#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT                                                     0x15
+#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT                                                      0x17
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT                                              0x18
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3__SHIFT                                                   0x1c
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3__SHIFT                             0x1d
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3__SHIFT                          0x1e
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3__SHIFT                                  0x1f
+#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3_MASK                                                0x00000080L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3_MASK                                                0x00000100L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3_MASK                                              0x00003E00L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_MASK                                       0x00004000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3_MASK                                                       0x00010000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3_MASK                                                       0x00020000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3_MASK                                             0x00100000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3_MASK                                                       0x00200000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3_MASK                                                        0x00800000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3_MASK                                                0x07000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3_MASK                                                     0x10000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3_MASK                               0x20000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3_MASK                            0x40000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3_MASK                                    0x80000000L
+//RCC_DEV0_EPF3_STRAP3
+#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT                                 0x0
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT                                                     0x1
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT                                                  0x2
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT                                                     0x12
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT                                         0x13
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT                                                    0x14
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT                                                    0x18
+#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT                                   0x1a
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT                                  0x1b
+#define RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3__SHIFT                                                  0x1d
+#define RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3__SHIFT                                          0x1e
+#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_MASK                                   0x00000001L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3_MASK                                                       0x00000002L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3_MASK                                                    0x0003FFFCL
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3_MASK                                                       0x00040000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3_MASK                                           0x00080000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3_MASK                                                      0x00100000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3_MASK                                                      0x01000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_MASK                                     0x04000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_MASK                                    0x08000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3_MASK                                                    0x20000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3_MASK                                            0x40000000L
+//RCC_DEV0_EPF3_STRAP4
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT                                            0x14
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT                                                  0x15
+#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT                                                     0x16
+#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT                                                0x17
+#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT                                              0x1c
+#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT                                             0x1f
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3_MASK                                              0x00100000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3_MASK                                                    0x00200000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3_MASK                                                       0x00400000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3_MASK                                                  0x0F800000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3_MASK                                                0x70000000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3_MASK                                               0x80000000L
+//RCC_DEV0_EPF3_STRAP5
+#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT                                              0x0
+#define RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3__SHIFT                                       0x1e
+#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3_MASK                                                0x0000FFFFL
+#define RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3_MASK                                         0x40000000L
+//RCC_DEV0_EPF3_STRAP6
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT                                                   0x0
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__SHIFT                                      0x1
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3_MASK                                                     0x00000001L
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3_MASK                                        0x00000002L
+//RCC_DEV0_EPF3_STRAP7
+#define RCC_DEV0_EPF3_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F3__SHIFT                                            0x5
+#define RCC_DEV0_EPF3_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F3_MASK                                              0x0000FFE0L
+//RCC_DEV0_EPF3_STRAP10
+//RCC_DEV0_EPF3_STRAP11
+//RCC_DEV0_EPF3_STRAP12
+//RCC_DEV0_EPF3_STRAP13
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT                                            0x0
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT                                            0x8
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT                                           0x10
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3_MASK                                              0x000000FFL
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3_MASK                                              0x0000FF00L
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3_MASK                                             0x00FF0000L
+//RCC_DEV0_EPF3_STRAP14
+#define RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3__SHIFT                                                 0x0
+#define RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3_MASK                                                   0x0000FFFFL
+//RCC_DEV0_EPF4_STRAP0
+#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT                                                  0x0
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT                                               0x10
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT                                               0x14
+#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT                                                    0x1c
+#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT                                      0x1d
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT                                                 0x1e
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT                                                 0x1f
+#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4_MASK                                                    0x0000FFFFL
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4_MASK                                                 0x000F0000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4_MASK                                                 0x00F00000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4_MASK                                                      0x10000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4_MASK                                        0x20000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4_MASK                                                   0x40000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4_MASK                                                   0x80000000L
+//RCC_DEV0_EPF4_STRAP2
+#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT                                              0x7
+#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT                                              0x8
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4__SHIFT                                            0x9
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT                                     0xe
+#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT                                                     0x10
+#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT                                                     0x11
+#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT                                           0x14
+#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT                                                     0x15
+#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT                                                      0x17
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT                                              0x18
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4__SHIFT                                                   0x1c
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4__SHIFT                             0x1d
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4__SHIFT                          0x1e
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4__SHIFT                                  0x1f
+#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4_MASK                                                0x00000080L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4_MASK                                                0x00000100L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4_MASK                                              0x00003E00L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4_MASK                                       0x00004000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4_MASK                                                       0x00010000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4_MASK                                                       0x00020000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4_MASK                                             0x00100000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4_MASK                                                       0x00200000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4_MASK                                                        0x00800000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4_MASK                                                0x07000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4_MASK                                                     0x10000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4_MASK                               0x20000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4_MASK                            0x40000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4_MASK                                    0x80000000L
+//RCC_DEV0_EPF4_STRAP3
+#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT                                 0x0
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT                                                     0x1
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT                                                  0x2
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT                                                     0x12
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT                                         0x13
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT                                                    0x14
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT                                                    0x18
+#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT                                   0x1a
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT                                  0x1b
+#define RCC_DEV0_EPF4_STRAP3__STRAP_CLK_PM_EN_DEV0_F4__SHIFT                                                  0x1d
+#define RCC_DEV0_EPF4_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F4__SHIFT                                          0x1e
+#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4_MASK                                   0x00000001L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4_MASK                                                       0x00000002L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4_MASK                                                    0x0003FFFCL
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4_MASK                                                       0x00040000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4_MASK                                           0x00080000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4_MASK                                                      0x00100000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4_MASK                                                      0x01000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4_MASK                                     0x04000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4_MASK                                    0x08000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_CLK_PM_EN_DEV0_F4_MASK                                                    0x20000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F4_MASK                                            0x40000000L
+//RCC_DEV0_EPF4_STRAP4
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT                                            0x14
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT                                                  0x15
+#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT                                                     0x16
+#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT                                                0x17
+#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT                                              0x1c
+#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT                                             0x1f
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4_MASK                                              0x00100000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4_MASK                                                    0x00200000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4_MASK                                                       0x00400000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4_MASK                                                  0x0F800000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4_MASK                                                0x70000000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4_MASK                                               0x80000000L
+//RCC_DEV0_EPF4_STRAP5
+#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT                                              0x0
+#define RCC_DEV0_EPF4_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F4__SHIFT                                       0x1e
+#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4_MASK                                                0x0000FFFFL
+#define RCC_DEV0_EPF4_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F4_MASK                                         0x40000000L
+//RCC_DEV0_EPF4_STRAP6
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT                                                   0x0
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__SHIFT                                      0x1
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4_MASK                                                     0x00000001L
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4_MASK                                        0x00000002L
+//RCC_DEV0_EPF4_STRAP7
+#define RCC_DEV0_EPF4_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F4__SHIFT                                            0x5
+#define RCC_DEV0_EPF4_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F4_MASK                                              0x0000FFE0L
+//RCC_DEV0_EPF4_STRAP13
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT                                            0x0
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT                                            0x8
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT                                           0x10
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4_MASK                                              0x000000FFL
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4_MASK                                              0x0000FF00L
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4_MASK                                             0x00FF0000L
+//RCC_DEV0_EPF4_STRAP14
+#define RCC_DEV0_EPF4_STRAP14__STRAP_VENDOR_ID_DEV0_F4__SHIFT                                                 0x0
+#define RCC_DEV0_EPF4_STRAP14__STRAP_VENDOR_ID_DEV0_F4_MASK                                                   0x0000FFFFL
+//RCC_DEV0_EPF5_STRAP0
+#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT                                                  0x0
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT                                               0x10
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT                                               0x14
+#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT                                                    0x1c
+#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT                                      0x1d
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT                                                 0x1e
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT                                                 0x1f
+#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5_MASK                                                    0x0000FFFFL
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5_MASK                                                 0x000F0000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5_MASK                                                 0x00F00000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5_MASK                                                      0x10000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5_MASK                                        0x20000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5_MASK                                                   0x40000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5_MASK                                                   0x80000000L
+//RCC_DEV0_EPF5_STRAP2
+#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT                                              0x7
+#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT                                              0x8
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5__SHIFT                                            0x9
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT                                     0xe
+#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT                                                     0x10
+#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT                                                     0x11
+#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT                                           0x14
+#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT                                                     0x15
+#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT                                                      0x17
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT                                              0x18
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5__SHIFT                                                   0x1c
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5__SHIFT                             0x1d
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5__SHIFT                          0x1e
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5__SHIFT                                  0x1f
+#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5_MASK                                                0x00000080L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5_MASK                                                0x00000100L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5_MASK                                              0x00003E00L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5_MASK                                       0x00004000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5_MASK                                                       0x00010000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5_MASK                                                       0x00020000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5_MASK                                             0x00100000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5_MASK                                                       0x00200000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5_MASK                                                        0x00800000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5_MASK                                                0x07000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5_MASK                                                     0x10000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5_MASK                               0x20000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5_MASK                            0x40000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5_MASK                                    0x80000000L
+//RCC_DEV0_EPF5_STRAP3
+#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT                                 0x0
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT                                                     0x1
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT                                                  0x2
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT                                                     0x12
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT                                         0x13
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT                                                    0x14
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT                                                    0x18
+#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT                                   0x1a
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT                                  0x1b
+#define RCC_DEV0_EPF5_STRAP3__STRAP_CLK_PM_EN_DEV0_F5__SHIFT                                                  0x1d
+#define RCC_DEV0_EPF5_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F5__SHIFT                                          0x1e
+#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5_MASK                                   0x00000001L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5_MASK                                                       0x00000002L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5_MASK                                                    0x0003FFFCL
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5_MASK                                                       0x00040000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5_MASK                                           0x00080000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5_MASK                                                      0x00100000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5_MASK                                                      0x01000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5_MASK                                     0x04000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5_MASK                                    0x08000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_CLK_PM_EN_DEV0_F5_MASK                                                    0x20000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F5_MASK                                            0x40000000L
+//RCC_DEV0_EPF5_STRAP4
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT                                            0x14
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT                                                  0x15
+#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT                                                     0x16
+#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT                                                0x17
+#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT                                              0x1c
+#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT                                             0x1f
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5_MASK                                              0x00100000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5_MASK                                                    0x00200000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5_MASK                                                       0x00400000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5_MASK                                                  0x0F800000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5_MASK                                                0x70000000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5_MASK                                               0x80000000L
+//RCC_DEV0_EPF5_STRAP5
+#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT                                              0x0
+#define RCC_DEV0_EPF5_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F5__SHIFT                                       0x1e
+#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5_MASK                                                0x0000FFFFL
+#define RCC_DEV0_EPF5_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F5_MASK                                         0x40000000L
+//RCC_DEV0_EPF5_STRAP6
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT                                                   0x0
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__SHIFT                                      0x1
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5_MASK                                                     0x00000001L
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5_MASK                                        0x00000002L
+//RCC_DEV0_EPF5_STRAP7
+//RCC_DEV0_EPF5_STRAP13
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT                                            0x0
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT                                            0x8
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT                                           0x10
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5_MASK                                              0x000000FFL
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5_MASK                                              0x0000FF00L
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5_MASK                                             0x00FF0000L
+//RCC_DEV0_EPF5_STRAP14
+#define RCC_DEV0_EPF5_STRAP14__STRAP_VENDOR_ID_DEV0_F5__SHIFT                                                 0x0
+#define RCC_DEV0_EPF5_STRAP14__STRAP_VENDOR_ID_DEV0_F5_MASK                                                   0x0000FFFFL
+//RCC_DEV0_EPF6_STRAP0
+#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT                                                  0x0
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT                                               0x10
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT                                               0x14
+#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT                                                    0x1c
+#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT                                      0x1d
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT                                                 0x1e
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT                                                 0x1f
+#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6_MASK                                                    0x0000FFFFL
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6_MASK                                                 0x000F0000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6_MASK                                                 0x00F00000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6_MASK                                                      0x10000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6_MASK                                        0x20000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6_MASK                                                   0x40000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6_MASK                                                   0x80000000L
+//RCC_DEV0_EPF6_STRAP2
+#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT                                              0x7
+#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT                                              0x8
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6__SHIFT                                            0x9
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT                                     0xe
+#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT                                                     0x10
+#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT                                                     0x11
+#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT                                           0x14
+#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT                                                     0x15
+#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT                                                      0x17
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT                                              0x18
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6__SHIFT                                                   0x1c
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6__SHIFT                             0x1d
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6__SHIFT                          0x1e
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6__SHIFT                                  0x1f
+#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6_MASK                                                0x00000080L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6_MASK                                                0x00000100L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6_MASK                                              0x00003E00L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6_MASK                                       0x00004000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6_MASK                                                       0x00010000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6_MASK                                                       0x00020000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6_MASK                                             0x00100000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6_MASK                                                       0x00200000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6_MASK                                                        0x00800000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6_MASK                                                0x07000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6_MASK                                                     0x10000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6_MASK                               0x20000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6_MASK                            0x40000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6_MASK                                    0x80000000L
+//RCC_DEV0_EPF6_STRAP3
+#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT                                 0x0
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT                                                     0x1
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT                                                  0x2
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT                                                     0x12
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT                                         0x13
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT                                                    0x14
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT                                                    0x18
+#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT                                   0x1a
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT                                  0x1b
+#define RCC_DEV0_EPF6_STRAP3__STRAP_CLK_PM_EN_DEV0_F6__SHIFT                                                  0x1d
+#define RCC_DEV0_EPF6_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F6__SHIFT                                          0x1e
+#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6_MASK                                   0x00000001L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6_MASK                                                       0x00000002L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6_MASK                                                    0x0003FFFCL
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6_MASK                                                       0x00040000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6_MASK                                           0x00080000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6_MASK                                                      0x00100000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6_MASK                                                      0x01000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6_MASK                                     0x04000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6_MASK                                    0x08000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_CLK_PM_EN_DEV0_F6_MASK                                                    0x20000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F6_MASK                                            0x40000000L
+//RCC_DEV0_EPF6_STRAP4
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT                                            0x14
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT                                                  0x15
+#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT                                                     0x16
+#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT                                                0x17
+#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT                                              0x1c
+#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT                                             0x1f
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6_MASK                                              0x00100000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6_MASK                                                    0x00200000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6_MASK                                                       0x00400000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6_MASK                                                  0x0F800000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6_MASK                                                0x70000000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6_MASK                                               0x80000000L
+//RCC_DEV0_EPF6_STRAP5
+#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT                                              0x0
+#define RCC_DEV0_EPF6_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F6__SHIFT                                       0x1e
+#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6_MASK                                                0x0000FFFFL
+#define RCC_DEV0_EPF6_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F6_MASK                                         0x40000000L
+//RCC_DEV0_EPF6_STRAP6
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT                                                   0x0
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__SHIFT                                      0x1
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6_MASK                                                     0x00000001L
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6_MASK                                        0x00000002L
+//RCC_DEV0_EPF6_STRAP7
+//RCC_DEV0_EPF6_STRAP13
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT                                            0x0
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT                                            0x8
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT                                           0x10
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6_MASK                                              0x000000FFL
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6_MASK                                              0x0000FF00L
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6_MASK                                             0x00FF0000L
+//RCC_DEV0_EPF6_STRAP14
+#define RCC_DEV0_EPF6_STRAP14__STRAP_VENDOR_ID_DEV0_F6__SHIFT                                                 0x0
+#define RCC_DEV0_EPF6_STRAP14__STRAP_VENDOR_ID_DEV0_F6_MASK                                                   0x0000FFFFL
+//RCC_DEV0_EPF7_STRAP0
+#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__SHIFT                                                  0x0
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__SHIFT                                               0x10
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__SHIFT                                               0x14
+#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__SHIFT                                                    0x1c
+#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__SHIFT                                      0x1d
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__SHIFT                                                 0x1e
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__SHIFT                                                 0x1f
+#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7_MASK                                                    0x0000FFFFL
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7_MASK                                                 0x000F0000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7_MASK                                                 0x00F00000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7_MASK                                                      0x10000000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7_MASK                                        0x20000000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7_MASK                                                   0x40000000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7_MASK                                                   0x80000000L
+//RCC_DEV0_EPF7_STRAP2
+#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__SHIFT                                              0x7
+#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__SHIFT                                              0x8
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F7__SHIFT                                            0x9
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__SHIFT                                     0xe
+#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__SHIFT                                                     0x10
+#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__SHIFT                                                     0x11
+#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__SHIFT                                           0x14
+#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__SHIFT                                                     0x15
+#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__SHIFT                                                      0x17
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__SHIFT                                              0x18
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_EN_DEV0_F7__SHIFT                                                   0x1c
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F7__SHIFT                             0x1d
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F7__SHIFT                          0x1e
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F7__SHIFT                                  0x1f
+#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7_MASK                                                0x00000080L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7_MASK                                                0x00000100L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F7_MASK                                              0x00003E00L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7_MASK                                       0x00004000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7_MASK                                                       0x00010000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7_MASK                                                       0x00020000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7_MASK                                             0x00100000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7_MASK                                                       0x00200000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7_MASK                                                        0x00800000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7_MASK                                                0x07000000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_EN_DEV0_F7_MASK                                                     0x10000000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F7_MASK                               0x20000000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F7_MASK                            0x40000000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F7_MASK                                    0x80000000L
+//RCC_DEV0_EPF7_STRAP3
+#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__SHIFT                                 0x0
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__SHIFT                                                     0x1
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__SHIFT                                                  0x2
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__SHIFT                                                     0x12
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__SHIFT                                         0x13
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__SHIFT                                                    0x14
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__SHIFT                                                    0x18
+#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__SHIFT                                   0x1a
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__SHIFT                                  0x1b
+#define RCC_DEV0_EPF7_STRAP3__STRAP_CLK_PM_EN_DEV0_F7__SHIFT                                                  0x1d
+#define RCC_DEV0_EPF7_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F7__SHIFT                                          0x1e
+#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7_MASK                                   0x00000001L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7_MASK                                                       0x00000002L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7_MASK                                                    0x0003FFFCL
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7_MASK                                                       0x00040000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7_MASK                                           0x00080000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7_MASK                                                      0x00100000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7_MASK                                                      0x01000000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7_MASK                                     0x04000000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7_MASK                                    0x08000000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_CLK_PM_EN_DEV0_F7_MASK                                                    0x20000000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F7_MASK                                            0x40000000L
+//RCC_DEV0_EPF7_STRAP4
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__SHIFT                                            0x14
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__SHIFT                                                  0x15
+#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__SHIFT                                                     0x16
+#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__SHIFT                                                0x17
+#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__SHIFT                                              0x1c
+#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__SHIFT                                             0x1f
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7_MASK                                              0x00100000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7_MASK                                                    0x00200000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7_MASK                                                       0x00400000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7_MASK                                                  0x0F800000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7_MASK                                                0x70000000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7_MASK                                               0x80000000L
+//RCC_DEV0_EPF7_STRAP5
+#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__SHIFT                                              0x0
+#define RCC_DEV0_EPF7_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F7__SHIFT                                       0x1e
+#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7_MASK                                                0x0000FFFFL
+#define RCC_DEV0_EPF7_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F7_MASK                                         0x40000000L
+//RCC_DEV0_EPF7_STRAP6
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__SHIFT                                                   0x0
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__SHIFT                                      0x1
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__SHIFT                                                   0x8
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__SHIFT                                      0x9
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7_MASK                                                     0x00000001L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7_MASK                                        0x00000002L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7_MASK                                                     0x00000100L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7_MASK                                        0x00000200L
+//RCC_DEV0_EPF7_STRAP7
+//RCC_DEV0_EPF7_STRAP13
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__SHIFT                                            0x0
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__SHIFT                                            0x8
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__SHIFT                                           0x10
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7_MASK                                              0x000000FFL
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7_MASK                                              0x0000FF00L
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7_MASK                                             0x00FF0000L
+//RCC_DEV0_EPF7_STRAP14
+#define RCC_DEV0_EPF7_STRAP14__STRAP_VENDOR_ID_DEV0_F7__SHIFT                                                 0x0
+#define RCC_DEV0_EPF7_STRAP14__STRAP_VENDOR_ID_DEV0_F7_MASK                                                   0x0000FFFFL
+//RCC_DEV1_EPF0_STRAP0
+#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT                                                  0x0
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT                                               0x10
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT                                               0x14
+#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT                                                    0x1c
+#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT                                      0x1d
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT                                                 0x1e
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT                                                 0x1f
+#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0_MASK                                                    0x0000FFFFL
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0_MASK                                                 0x000F0000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0_MASK                                                 0x00F00000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0_MASK                                                      0x10000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0_MASK                                        0x20000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0_MASK                                                   0x40000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0_MASK                                                   0x80000000L
+//RCC_DEV1_EPF0_STRAP2
+#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT                                              0x7
+#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT                                              0x8
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F0__SHIFT                                            0x9
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT                                     0xe
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT                                                     0xf
+#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT                                                     0x10
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT                                                     0x11
+#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT                                           0x14
+#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT                                                     0x15
+#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT                                                      0x17
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT                                              0x18
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EN_DEV1_F0__SHIFT                                                   0x1c
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F0__SHIFT                             0x1d
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F0__SHIFT                          0x1e
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F0__SHIFT                                  0x1f
+#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0_MASK                                                0x00000080L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0_MASK                                                0x00000100L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F0_MASK                                              0x00003E00L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0_MASK                                       0x00004000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0_MASK                                                       0x00008000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0_MASK                                                       0x00010000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0_MASK                                                       0x00020000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0_MASK                                             0x00100000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0_MASK                                                       0x00200000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0_MASK                                                        0x00800000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0_MASK                                                0x07000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EN_DEV1_F0_MASK                                                     0x10000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F0_MASK                               0x20000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F0_MASK                            0x40000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F0_MASK                                    0x80000000L
+//RCC_DEV1_EPF0_STRAP3
+#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT                                 0x0
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT                                                     0x1
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT                                                  0x2
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT                                                     0x12
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT                                         0x13
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT                                                    0x14
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT                                                    0x18
+#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT                                   0x1a
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT                                  0x1b
+#define RCC_DEV1_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV1_F0__SHIFT                                                  0x1d
+#define RCC_DEV1_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV1_F0__SHIFT                                          0x1e
+#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0_MASK                                   0x00000001L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0_MASK                                                       0x00000002L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0_MASK                                                    0x0003FFFCL
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0_MASK                                                       0x00040000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0_MASK                                           0x00080000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0_MASK                                                      0x00100000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0_MASK                                                      0x01000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0_MASK                                     0x04000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0_MASK                                    0x08000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV1_F0_MASK                                                    0x20000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV1_F0_MASK                                            0x40000000L
+//RCC_DEV1_EPF0_STRAP4
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT                                            0x14
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT                                                  0x15
+#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT                                                     0x16
+#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT                                                0x17
+#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT                                              0x1c
+#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__SHIFT                                             0x1f
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0_MASK                                              0x00100000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0_MASK                                                    0x00200000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0_MASK                                                       0x00400000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0_MASK                                                  0x0F800000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0_MASK                                                0x70000000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0_MASK                                               0x80000000L
+//RCC_DEV1_EPF0_STRAP5
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT                                              0x0
+#define RCC_DEV1_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV1_F0__SHIFT                                       0x1e
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0_MASK                                                0x0000FFFFL
+#define RCC_DEV1_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV1_F0_MASK                                         0x40000000L
+//RCC_DEV1_EPF0_STRAP6
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT                                                   0x0
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__SHIFT                                      0x1
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0_MASK                                                     0x00000001L
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0_MASK                                        0x00000002L
+//RCC_DEV1_EPF0_STRAP7
+//RCC_DEV1_EPF0_STRAP13
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT                                            0x0
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT                                            0x8
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT                                           0x10
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0_MASK                                              0x000000FFL
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0_MASK                                              0x0000FF00L
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0_MASK                                             0x00FF0000L
+//RCC_DEV1_EPF0_STRAP14
+#define RCC_DEV1_EPF0_STRAP14__STRAP_VENDOR_ID_DEV1_F0__SHIFT                                                 0x0
+#define RCC_DEV1_EPF0_STRAP14__STRAP_VENDOR_ID_DEV1_F0_MASK                                                   0x0000FFFFL
+//RCC_DEV1_EPF1_STRAP0
+#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__SHIFT                                                  0x0
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__SHIFT                                               0x10
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__SHIFT                                               0x14
+#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__SHIFT                                                    0x1c
+#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__SHIFT                                      0x1d
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__SHIFT                                                 0x1e
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__SHIFT                                                 0x1f
+#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1_MASK                                                    0x0000FFFFL
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1_MASK                                                 0x000F0000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1_MASK                                                 0x00F00000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1_MASK                                                      0x10000000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1_MASK                                        0x20000000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1_MASK                                                   0x40000000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1_MASK                                                   0x80000000L
+//RCC_DEV1_EPF1_STRAP2
+#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__SHIFT                                              0x7
+#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__SHIFT                                              0x8
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F1__SHIFT                                            0x9
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__SHIFT                                     0xe
+#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__SHIFT                                                     0x10
+#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__SHIFT                                                     0x11
+#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__SHIFT                                           0x14
+#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__SHIFT                                                     0x15
+#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__SHIFT                                                      0x17
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__SHIFT                                              0x18
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_EN_DEV1_F1__SHIFT                                                   0x1c
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F1__SHIFT                             0x1d
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F1__SHIFT                          0x1e
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F1__SHIFT                                  0x1f
+#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1_MASK                                                0x00000080L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1_MASK                                                0x00000100L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F1_MASK                                              0x00003E00L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1_MASK                                       0x00004000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1_MASK                                                       0x00010000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1_MASK                                                       0x00020000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1_MASK                                             0x00100000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1_MASK                                                       0x00200000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1_MASK                                                        0x00800000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1_MASK                                                0x07000000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_EN_DEV1_F1_MASK                                                     0x10000000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F1_MASK                               0x20000000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F1_MASK                            0x40000000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F1_MASK                                    0x80000000L
+//RCC_DEV1_EPF1_STRAP3
+#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__SHIFT                                 0x0
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__SHIFT                                                     0x1
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__SHIFT                                                  0x2
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__SHIFT                                                     0x12
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__SHIFT                                         0x13
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__SHIFT                                                    0x14
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__SHIFT                                                    0x18
+#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__SHIFT                                   0x1a
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__SHIFT                                  0x1b
+#define RCC_DEV1_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV1_F1__SHIFT                                                  0x1d
+#define RCC_DEV1_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV1_F1__SHIFT                                          0x1e
+#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1_MASK                                   0x00000001L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1_MASK                                                       0x00000002L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1_MASK                                                    0x0003FFFCL
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1_MASK                                                       0x00040000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1_MASK                                           0x00080000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1_MASK                                                      0x00100000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1_MASK                                                      0x01000000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1_MASK                                     0x04000000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1_MASK                                    0x08000000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV1_F1_MASK                                                    0x20000000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV1_F1_MASK                                            0x40000000L
+//RCC_DEV1_EPF1_STRAP4
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__SHIFT                                            0x14
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__SHIFT                                                  0x15
+#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__SHIFT                                                     0x16
+#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__SHIFT                                                0x17
+#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__SHIFT                                              0x1c
+#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__SHIFT                                             0x1f
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1_MASK                                              0x00100000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1_MASK                                                    0x00200000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1_MASK                                                       0x00400000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1_MASK                                                  0x0F800000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1_MASK                                                0x70000000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1_MASK                                               0x80000000L
+//RCC_DEV1_EPF1_STRAP5
+#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__SHIFT                                              0x0
+#define RCC_DEV1_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV1_F1__SHIFT                                       0x1e
+#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1_MASK                                                0x0000FFFFL
+#define RCC_DEV1_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV1_F1_MASK                                         0x40000000L
+//RCC_DEV1_EPF1_STRAP6
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__SHIFT                                                   0x0
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__SHIFT                                      0x1
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__SHIFT                                                   0x8
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__SHIFT                                      0x9
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__SHIFT                                                   0x10
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__SHIFT                                      0x11
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1_MASK                                                     0x00000001L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1_MASK                                        0x00000002L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1_MASK                                                     0x00000100L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1_MASK                                        0x00000200L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1_MASK                                                     0x00010000L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1_MASK                                        0x00020000L
+//RCC_DEV1_EPF1_STRAP7
+#define RCC_DEV1_EPF1_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV1_F1__SHIFT                                            0x5
+#define RCC_DEV1_EPF1_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV1_F1_MASK                                              0x0000FFE0L
+//RCC_DEV1_EPF1_STRAP13
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__SHIFT                                            0x0
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__SHIFT                                            0x8
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__SHIFT                                           0x10
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1_MASK                                              0x000000FFL
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1_MASK                                              0x0000FF00L
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1_MASK                                             0x00FF0000L
+//RCC_DEV1_EPF1_STRAP14
+#define RCC_DEV1_EPF1_STRAP14__STRAP_VENDOR_ID_DEV1_F1__SHIFT                                                 0x0
+#define RCC_DEV1_EPF1_STRAP14__STRAP_VENDOR_ID_DEV1_F1_MASK                                                   0x0000FFFFL
+//RCC_DEV1_EPF2_STRAP0
+//RCC_DEV1_EPF2_STRAP2
+//RCC_DEV1_EPF2_STRAP3
+//RCC_DEV1_EPF2_STRAP4
+//RCC_DEV1_EPF2_STRAP5
+//RCC_DEV1_EPF2_STRAP6
+//RCC_DEV1_EPF2_STRAP13
+//RCC_DEV1_EPF2_STRAP14
+//RCC_DEV1_EPF3_STRAP0
+//RCC_DEV1_EPF3_STRAP2
+//RCC_DEV1_EPF3_STRAP3
+//RCC_DEV1_EPF3_STRAP4
+//RCC_DEV1_EPF3_STRAP5
+//RCC_DEV1_EPF3_STRAP6
+//RCC_DEV1_EPF3_STRAP13
+//RCC_DEV1_EPF3_STRAP14
+//RCC_DEV1_EPF4_STRAP0
+//RCC_DEV1_EPF4_STRAP2
+//RCC_DEV1_EPF4_STRAP3
+//RCC_DEV1_EPF4_STRAP4
+//RCC_DEV1_EPF4_STRAP5
+//RCC_DEV1_EPF4_STRAP6
+//RCC_DEV1_EPF4_STRAP13
+//RCC_DEV1_EPF4_STRAP14
+//RCC_DEV1_EPF5_STRAP0
+//RCC_DEV1_EPF5_STRAP2
+//RCC_DEV1_EPF5_STRAP3
+//RCC_DEV1_EPF5_STRAP4
+//RCC_DEV1_EPF5_STRAP5
+//RCC_DEV1_EPF5_STRAP6
+//RCC_DEV1_EPF5_STRAP13
+//RCC_DEV1_EPF5_STRAP14
+//RCC_DEV2_EPF0_STRAP0
+#define RCC_DEV2_EPF0_STRAP0__STRAP_DEVICE_ID_DEV2_F0__SHIFT                                                  0x0
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F0__SHIFT                                               0x10
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV2_F0__SHIFT                                               0x14
+#define RCC_DEV2_EPF0_STRAP0__STRAP_FUNC_EN_DEV2_F0__SHIFT                                                    0x1c
+#define RCC_DEV2_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F0__SHIFT                                      0x1d
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV2_F0__SHIFT                                                 0x1e
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV2_F0__SHIFT                                                 0x1f
+#define RCC_DEV2_EPF0_STRAP0__STRAP_DEVICE_ID_DEV2_F0_MASK                                                    0x0000FFFFL
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F0_MASK                                                 0x000F0000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV2_F0_MASK                                                 0x00F00000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_FUNC_EN_DEV2_F0_MASK                                                      0x10000000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F0_MASK                                        0x20000000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV2_F0_MASK                                                   0x40000000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV2_F0_MASK                                                   0x80000000L
+//RCC_DEV2_EPF0_STRAP2
+#define RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0__SHIFT                                              0x7
+#define RCC_DEV2_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F0__SHIFT                                              0x8
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F0__SHIFT                                            0x9
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F0__SHIFT                                     0xe
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ARI_EN_DEV2_F0__SHIFT                                                     0xf
+#define RCC_DEV2_EPF0_STRAP2__STRAP_AER_EN_DEV2_F0__SHIFT                                                     0x10
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ACS_EN_DEV2_F0__SHIFT                                                     0x11
+#define RCC_DEV2_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F0__SHIFT                                           0x14
+#define RCC_DEV2_EPF0_STRAP2__STRAP_DPA_EN_DEV2_F0__SHIFT                                                     0x15
+#define RCC_DEV2_EPF0_STRAP2__STRAP_VC_EN_DEV2_F0__SHIFT                                                      0x17
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F0__SHIFT                                              0x18
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EN_DEV2_F0__SHIFT                                                   0x1c
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F0__SHIFT                             0x1d
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F0__SHIFT                          0x1e
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F0__SHIFT                                  0x1f
+#define RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK                                                0x00000080L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F0_MASK                                                0x00000100L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F0_MASK                                              0x00003E00L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F0_MASK                                       0x00004000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ARI_EN_DEV2_F0_MASK                                                       0x00008000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_AER_EN_DEV2_F0_MASK                                                       0x00010000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ACS_EN_DEV2_F0_MASK                                                       0x00020000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F0_MASK                                             0x00100000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_DPA_EN_DEV2_F0_MASK                                                       0x00200000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_VC_EN_DEV2_F0_MASK                                                        0x00800000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F0_MASK                                                0x07000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EN_DEV2_F0_MASK                                                     0x10000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F0_MASK                               0x20000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F0_MASK                            0x40000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F0_MASK                                    0x80000000L
+//RCC_DEV2_EPF0_STRAP3
+#define RCC_DEV2_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F0__SHIFT                                 0x0
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PWR_EN_DEV2_F0__SHIFT                                                     0x1
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV2_F0__SHIFT                                                  0x2
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_EN_DEV2_F0__SHIFT                                                     0x12
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F0__SHIFT                                         0x13
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSIX_EN_DEV2_F0__SHIFT                                                    0x14
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PMC_DSI_DEV2_F0__SHIFT                                                    0x18
+#define RCC_DEV2_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F0__SHIFT                                   0x1a
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F0__SHIFT                                  0x1b
+#define RCC_DEV2_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV2_F0__SHIFT                                                  0x1d
+#define RCC_DEV2_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F0__SHIFT                                          0x1e
+#define RCC_DEV2_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F0_MASK                                   0x00000001L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PWR_EN_DEV2_F0_MASK                                                       0x00000002L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV2_F0_MASK                                                    0x0003FFFCL
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_EN_DEV2_F0_MASK                                                       0x00040000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F0_MASK                                           0x00080000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSIX_EN_DEV2_F0_MASK                                                      0x00100000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PMC_DSI_DEV2_F0_MASK                                                      0x01000000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F0_MASK                                     0x04000000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F0_MASK                                    0x08000000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV2_F0_MASK                                                    0x20000000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F0_MASK                                            0x40000000L
+//RCC_DEV2_EPF0_STRAP4
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F0__SHIFT                                            0x14
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV2_F0__SHIFT                                                  0x15
+#define RCC_DEV2_EPF0_STRAP4__STRAP_FLR_EN_DEV2_F0__SHIFT                                                     0x16
+#define RCC_DEV2_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV2_F0__SHIFT                                                0x17
+#define RCC_DEV2_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F0__SHIFT                                              0x1c
+#define RCC_DEV2_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F0__SHIFT                                             0x1f
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F0_MASK                                              0x00100000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV2_F0_MASK                                                    0x00200000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_FLR_EN_DEV2_F0_MASK                                                       0x00400000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV2_F0_MASK                                                  0x0F800000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F0_MASK                                                0x70000000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F0_MASK                                               0x80000000L
+//RCC_DEV2_EPF0_STRAP5
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F0__SHIFT                                              0x0
+#define RCC_DEV2_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F0__SHIFT                                       0x1e
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F0_MASK                                                0x0000FFFFL
+#define RCC_DEV2_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F0_MASK                                         0x40000000L
+//RCC_DEV2_EPF0_STRAP6
+#define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_EN_DEV2_F0__SHIFT                                                   0x0
+#define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV2_F0__SHIFT                                      0x1
+#define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_EN_DEV2_F0_MASK                                                     0x00000001L
+#define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV2_F0_MASK                                        0x00000002L
+//RCC_DEV2_EPF0_STRAP7
+#define RCC_DEV2_EPF0_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV2_F0__SHIFT                                            0x5
+#define RCC_DEV2_EPF0_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV2_F0_MASK                                              0x0000FFE0L
+//RCC_DEV2_EPF0_STRAP13
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F0__SHIFT                                            0x0
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F0__SHIFT                                            0x8
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F0__SHIFT                                           0x10
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F0_MASK                                              0x000000FFL
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F0_MASK                                              0x0000FF00L
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F0_MASK                                             0x00FF0000L
+//RCC_DEV2_EPF0_STRAP14
+#define RCC_DEV2_EPF0_STRAP14__STRAP_VENDOR_ID_DEV2_F0__SHIFT                                                 0x0
+#define RCC_DEV2_EPF0_STRAP14__STRAP_VENDOR_ID_DEV2_F0_MASK                                                   0x0000FFFFL
+//RCC_DEV2_EPF1_STRAP0
+#define RCC_DEV2_EPF1_STRAP0__STRAP_DEVICE_ID_DEV2_F1__SHIFT                                                  0x0
+#define RCC_DEV2_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F1__SHIFT                                               0x10
+#define RCC_DEV2_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV2_F1__SHIFT                                               0x14
+#define RCC_DEV2_EPF1_STRAP0__STRAP_FUNC_EN_DEV2_F1__SHIFT                                                    0x1c
+#define RCC_DEV2_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F1__SHIFT                                      0x1d
+#define RCC_DEV2_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV2_F1__SHIFT                                                 0x1e
+#define RCC_DEV2_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV2_F1__SHIFT                                                 0x1f
+#define RCC_DEV2_EPF1_STRAP0__STRAP_DEVICE_ID_DEV2_F1_MASK                                                    0x0000FFFFL
+#define RCC_DEV2_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F1_MASK                                                 0x000F0000L
+#define RCC_DEV2_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV2_F1_MASK                                                 0x00F00000L
+#define RCC_DEV2_EPF1_STRAP0__STRAP_FUNC_EN_DEV2_F1_MASK                                                      0x10000000L
+#define RCC_DEV2_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F1_MASK                                        0x20000000L
+#define RCC_DEV2_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV2_F1_MASK                                                   0x40000000L
+#define RCC_DEV2_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV2_F1_MASK                                                   0x80000000L
+//RCC_DEV2_EPF1_STRAP2
+#define RCC_DEV2_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F1__SHIFT                                              0x7
+#define RCC_DEV2_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F1__SHIFT                                              0x8
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F1__SHIFT                                            0x9
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F1__SHIFT                                     0xe
+#define RCC_DEV2_EPF1_STRAP2__STRAP_AER_EN_DEV2_F1__SHIFT                                                     0x10
+#define RCC_DEV2_EPF1_STRAP2__STRAP_ACS_EN_DEV2_F1__SHIFT                                                     0x11
+#define RCC_DEV2_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F1__SHIFT                                           0x14
+#define RCC_DEV2_EPF1_STRAP2__STRAP_DPA_EN_DEV2_F1__SHIFT                                                     0x15
+#define RCC_DEV2_EPF1_STRAP2__STRAP_VC_EN_DEV2_F1__SHIFT                                                      0x17
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F1__SHIFT                                              0x18
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_EN_DEV2_F1__SHIFT                                                   0x1c
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F1__SHIFT                             0x1d
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F1__SHIFT                          0x1e
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F1__SHIFT                                  0x1f
+#define RCC_DEV2_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F1_MASK                                                0x00000080L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F1_MASK                                                0x00000100L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F1_MASK                                              0x00003E00L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F1_MASK                                       0x00004000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_AER_EN_DEV2_F1_MASK                                                       0x00010000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_ACS_EN_DEV2_F1_MASK                                                       0x00020000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F1_MASK                                             0x00100000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_DPA_EN_DEV2_F1_MASK                                                       0x00200000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_VC_EN_DEV2_F1_MASK                                                        0x00800000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F1_MASK                                                0x07000000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_EN_DEV2_F1_MASK                                                     0x10000000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F1_MASK                               0x20000000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F1_MASK                            0x40000000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F1_MASK                                    0x80000000L
+//RCC_DEV2_EPF1_STRAP3
+#define RCC_DEV2_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F1__SHIFT                                 0x0
+#define RCC_DEV2_EPF1_STRAP3__STRAP_PWR_EN_DEV2_F1__SHIFT                                                     0x1
+#define RCC_DEV2_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV2_F1__SHIFT                                                  0x2
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSI_EN_DEV2_F1__SHIFT                                                     0x12
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F1__SHIFT                                         0x13
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSIX_EN_DEV2_F1__SHIFT                                                    0x14
+#define RCC_DEV2_EPF1_STRAP3__STRAP_PMC_DSI_DEV2_F1__SHIFT                                                    0x18
+#define RCC_DEV2_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F1__SHIFT                                   0x1a
+#define RCC_DEV2_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F1__SHIFT                                  0x1b
+#define RCC_DEV2_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV2_F1__SHIFT                                                  0x1d
+#define RCC_DEV2_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F1__SHIFT                                          0x1e
+#define RCC_DEV2_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F1_MASK                                   0x00000001L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_PWR_EN_DEV2_F1_MASK                                                       0x00000002L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV2_F1_MASK                                                    0x0003FFFCL
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSI_EN_DEV2_F1_MASK                                                       0x00040000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F1_MASK                                           0x00080000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSIX_EN_DEV2_F1_MASK                                                      0x00100000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_PMC_DSI_DEV2_F1_MASK                                                      0x01000000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F1_MASK                                     0x04000000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F1_MASK                                    0x08000000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV2_F1_MASK                                                    0x20000000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F1_MASK                                            0x40000000L
+//RCC_DEV2_EPF1_STRAP4
+#define RCC_DEV2_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F1__SHIFT                                            0x14
+#define RCC_DEV2_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV2_F1__SHIFT                                                  0x15
+#define RCC_DEV2_EPF1_STRAP4__STRAP_FLR_EN_DEV2_F1__SHIFT                                                     0x16
+#define RCC_DEV2_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV2_F1__SHIFT                                                0x17
+#define RCC_DEV2_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F1__SHIFT                                              0x1c
+#define RCC_DEV2_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F1__SHIFT                                             0x1f
+#define RCC_DEV2_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F1_MASK                                              0x00100000L
+#define RCC_DEV2_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV2_F1_MASK                                                    0x00200000L
+#define RCC_DEV2_EPF1_STRAP4__STRAP_FLR_EN_DEV2_F1_MASK                                                       0x00400000L
+#define RCC_DEV2_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV2_F1_MASK                                                  0x0F800000L
+#define RCC_DEV2_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F1_MASK                                                0x70000000L
+#define RCC_DEV2_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F1_MASK                                               0x80000000L
+//RCC_DEV2_EPF1_STRAP5
+#define RCC_DEV2_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F1__SHIFT                                              0x0
+#define RCC_DEV2_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F1__SHIFT                                       0x1e
+#define RCC_DEV2_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F1_MASK                                                0x0000FFFFL
+#define RCC_DEV2_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F1_MASK                                         0x40000000L
+//RCC_DEV2_EPF1_STRAP6
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER0_EN_DEV2_F1__SHIFT                                                   0x0
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER1_EN_DEV2_F1__SHIFT                                                   0x8
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER2_EN_DEV2_F1__SHIFT                                                   0x10
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER3_EN_DEV2_F1__SHIFT                                                   0x18
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV2_F1__SHIFT                                      0x19
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER0_EN_DEV2_F1_MASK                                                     0x00000001L
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER1_EN_DEV2_F1_MASK                                                     0x00000100L
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER2_EN_DEV2_F1_MASK                                                     0x00010000L
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER3_EN_DEV2_F1_MASK                                                     0x01000000L
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV2_F1_MASK                                        0x02000000L
+//RCC_DEV2_EPF1_STRAP13
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F1__SHIFT                                            0x0
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F1__SHIFT                                            0x8
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F1__SHIFT                                           0x10
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F1_MASK                                              0x000000FFL
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F1_MASK                                              0x0000FF00L
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F1_MASK                                             0x00FF0000L
+//RCC_DEV2_EPF1_STRAP14
+#define RCC_DEV2_EPF1_STRAP14__STRAP_VENDOR_ID_DEV2_F1__SHIFT                                                 0x0
+#define RCC_DEV2_EPF1_STRAP14__STRAP_VENDOR_ID_DEV2_F1_MASK                                                   0x0000FFFFL
+//RCC_DEV2_EPF2_STRAP0
+#define RCC_DEV2_EPF2_STRAP0__STRAP_DEVICE_ID_DEV2_F2__SHIFT                                                  0x0
+#define RCC_DEV2_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F2__SHIFT                                               0x10
+#define RCC_DEV2_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV2_F2__SHIFT                                               0x14
+#define RCC_DEV2_EPF2_STRAP0__STRAP_FUNC_EN_DEV2_F2__SHIFT                                                    0x1c
+#define RCC_DEV2_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F2__SHIFT                                      0x1d
+#define RCC_DEV2_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV2_F2__SHIFT                                                 0x1e
+#define RCC_DEV2_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV2_F2__SHIFT                                                 0x1f
+#define RCC_DEV2_EPF2_STRAP0__STRAP_DEVICE_ID_DEV2_F2_MASK                                                    0x0000FFFFL
+#define RCC_DEV2_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F2_MASK                                                 0x000F0000L
+#define RCC_DEV2_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV2_F2_MASK                                                 0x00F00000L
+#define RCC_DEV2_EPF2_STRAP0__STRAP_FUNC_EN_DEV2_F2_MASK                                                      0x10000000L
+#define RCC_DEV2_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F2_MASK                                        0x20000000L
+#define RCC_DEV2_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV2_F2_MASK                                                   0x40000000L
+#define RCC_DEV2_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV2_F2_MASK                                                   0x80000000L
+//RCC_DEV2_EPF2_STRAP2
+#define RCC_DEV2_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F2__SHIFT                                              0x7
+#define RCC_DEV2_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F2__SHIFT                                              0x8
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F2__SHIFT                                            0x9
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F2__SHIFT                                     0xe
+#define RCC_DEV2_EPF2_STRAP2__STRAP_AER_EN_DEV2_F2__SHIFT                                                     0x10
+#define RCC_DEV2_EPF2_STRAP2__STRAP_ACS_EN_DEV2_F2__SHIFT                                                     0x11
+#define RCC_DEV2_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F2__SHIFT                                           0x14
+#define RCC_DEV2_EPF2_STRAP2__STRAP_DPA_EN_DEV2_F2__SHIFT                                                     0x15
+#define RCC_DEV2_EPF2_STRAP2__STRAP_VC_EN_DEV2_F2__SHIFT                                                      0x17
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F2__SHIFT                                              0x18
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_EN_DEV2_F2__SHIFT                                                   0x1c
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F2__SHIFT                             0x1d
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F2__SHIFT                          0x1e
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F2__SHIFT                                  0x1f
+#define RCC_DEV2_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F2_MASK                                                0x00000080L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F2_MASK                                                0x00000100L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F2_MASK                                              0x00003E00L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F2_MASK                                       0x00004000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_AER_EN_DEV2_F2_MASK                                                       0x00010000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_ACS_EN_DEV2_F2_MASK                                                       0x00020000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F2_MASK                                             0x00100000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_DPA_EN_DEV2_F2_MASK                                                       0x00200000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_VC_EN_DEV2_F2_MASK                                                        0x00800000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F2_MASK                                                0x07000000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_EN_DEV2_F2_MASK                                                     0x10000000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F2_MASK                               0x20000000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F2_MASK                            0x40000000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F2_MASK                                    0x80000000L
+//RCC_DEV2_EPF2_STRAP3
+#define RCC_DEV2_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F2__SHIFT                                 0x0
+#define RCC_DEV2_EPF2_STRAP3__STRAP_PWR_EN_DEV2_F2__SHIFT                                                     0x1
+#define RCC_DEV2_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV2_F2__SHIFT                                                  0x2
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSI_EN_DEV2_F2__SHIFT                                                     0x12
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F2__SHIFT                                         0x13
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSIX_EN_DEV2_F2__SHIFT                                                    0x14
+#define RCC_DEV2_EPF2_STRAP3__STRAP_PMC_DSI_DEV2_F2__SHIFT                                                    0x18
+#define RCC_DEV2_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F2__SHIFT                                   0x1a
+#define RCC_DEV2_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F2__SHIFT                                  0x1b
+#define RCC_DEV2_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV2_F2__SHIFT                                                  0x1d
+#define RCC_DEV2_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F2__SHIFT                                          0x1e
+#define RCC_DEV2_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F2_MASK                                   0x00000001L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_PWR_EN_DEV2_F2_MASK                                                       0x00000002L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV2_F2_MASK                                                    0x0003FFFCL
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSI_EN_DEV2_F2_MASK                                                       0x00040000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F2_MASK                                           0x00080000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSIX_EN_DEV2_F2_MASK                                                      0x00100000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_PMC_DSI_DEV2_F2_MASK                                                      0x01000000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F2_MASK                                     0x04000000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F2_MASK                                    0x08000000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV2_F2_MASK                                                    0x20000000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F2_MASK                                            0x40000000L
+//RCC_DEV2_EPF2_STRAP4
+#define RCC_DEV2_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F2__SHIFT                                            0x14
+#define RCC_DEV2_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV2_F2__SHIFT                                                  0x15
+#define RCC_DEV2_EPF2_STRAP4__STRAP_FLR_EN_DEV2_F2__SHIFT                                                     0x16
+#define RCC_DEV2_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV2_F2__SHIFT                                                0x17
+#define RCC_DEV2_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F2__SHIFT                                              0x1c
+#define RCC_DEV2_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F2__SHIFT                                             0x1f
+#define RCC_DEV2_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F2_MASK                                              0x00100000L
+#define RCC_DEV2_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV2_F2_MASK                                                    0x00200000L
+#define RCC_DEV2_EPF2_STRAP4__STRAP_FLR_EN_DEV2_F2_MASK                                                       0x00400000L
+#define RCC_DEV2_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV2_F2_MASK                                                  0x0F800000L
+#define RCC_DEV2_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F2_MASK                                                0x70000000L
+#define RCC_DEV2_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F2_MASK                                               0x80000000L
+//RCC_DEV2_EPF2_STRAP5
+#define RCC_DEV2_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F2__SHIFT                                              0x0
+#define RCC_DEV2_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F2__SHIFT                                       0x1e
+#define RCC_DEV2_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F2_MASK                                                0x0000FFFFL
+#define RCC_DEV2_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F2_MASK                                         0x40000000L
+//RCC_DEV2_EPF2_STRAP6
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER0_EN_DEV2_F2__SHIFT                                                   0x0
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV2_F2__SHIFT                                      0x1
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER1_EN_DEV2_F2__SHIFT                                                   0x8
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER0_EN_DEV2_F2_MASK                                                     0x00000001L
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV2_F2_MASK                                        0x00000002L
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER1_EN_DEV2_F2_MASK                                                     0x00000100L
+//RCC_DEV2_EPF2_STRAP13
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F2__SHIFT                                            0x0
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F2__SHIFT                                            0x8
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F2__SHIFT                                           0x10
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F2_MASK                                              0x000000FFL
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F2_MASK                                              0x0000FF00L
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F2_MASK                                             0x00FF0000L
+//RCC_DEV2_EPF2_STRAP14
+#define RCC_DEV2_EPF2_STRAP14__STRAP_VENDOR_ID_DEV2_F2__SHIFT                                                 0x0
+#define RCC_DEV2_EPF2_STRAP14__STRAP_VENDOR_ID_DEV2_F2_MASK                                                   0x0000FFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC
+//RCC_DEV0_2_RCC_VDM_SUPPORT
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT                                                       0x0
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT                                                      0x1
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT                                                  0x2
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT                                        0x3
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT                                    0x4
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK                                                         0x00000001L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK                                                        0x00000002L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK                                                    0x00000004L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK                                          0x00000008L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK                                      0x00000010L
+//RCC_DEV0_2_RCC_BUS_CNTL
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT                                                            0x2
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT                                                           0x3
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT                                                            0x4
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT                                                         0x5
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT                                                        0x6
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT                                                         0x7
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT                                                        0x8
+#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT                                                 0xc
+#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT                                           0xd
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x10
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x11
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x12
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x13
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x14
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x15
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT                                                 0x18
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                 0x19
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT                                            0x1c
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                            0x1d
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK                                                              0x00000004L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK                                                             0x00000008L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK                                                              0x00000010L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK                                                           0x00000020L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK                                                          0x00000040L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK                                                           0x00000080L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK                                                          0x00000100L
+#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK                                                   0x00001000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK                                             0x00002000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00010000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00020000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00040000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00080000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00100000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00200000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK                                                   0x01000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK                                                   0x0E000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK                                              0x10000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK                                              0xE0000000L
+//RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT                                   0x7
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT                                 0x8
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT                                    0x9
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT                                    0xa
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT                                 0xb
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT                                  0xc
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT                                      0xd
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT                      0xe
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT                                 0x10
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT                           0x11
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT                               0x12
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT                     0x13
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK                                     0x00000080L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK                                   0x00000100L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK                                      0x00000200L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK                                      0x00000400L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK                                   0x00000800L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK                                    0x00001000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK                                        0x00002000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK                        0x00004000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK                                   0x00010000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK                             0x00020000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK                                 0x00040000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK                       0x00080000L
+//RCC_DEV0_2_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT                                                  0x0
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT                                                 0x8
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK                                                    0x00000001L
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK                                                   0x00000100L
+//RCC_DEV0_2_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT                                             0x0
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT                                              0x1
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT                                             0x2
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT                                          0x3
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT                                             0x10
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK                                               0x00000001L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK                                                0x00000002L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK                                               0x00000004L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK                                            0x00000008L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK                                               0xFFFF0000L
+//RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT                                            0x0
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT                                            0x8
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK                                              0x000000FFL
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK                                              0x00001F00L
+//RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT                                         0x0
+#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK                                           0x000003FFL
+//RCC_DEV0_2_RCC_MH_ARB_CNTL
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT                                                        0x0
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT                                                0x1
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK                                                          0x00000001L
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK                                                  0x00007FFEL
+//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT                                 0x0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT                              0x1
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT                                0x2
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT                                 0x3
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT                           0x4
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT                                  0x5
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT                                 0xb
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT                                 0x12
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT                                0x19
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK                                   0x00000001L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK                                0x00000002L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK                                  0x00000004L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK                                   0x00000008L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK                             0x00000010L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK                                    0x000007E0L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK                                   0x0003F800L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK                                   0x01FC0000L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK                                  0xFE000000L
+//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT                             0x0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT                              0x6
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT                                         0xc
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT                                      0x11
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK                               0x0000003FL
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK                                0x00000FC0L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK                                           0x0001F000L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK                                        0x00FE0000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC
+//RCC_EP_DEV0_2_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
+#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
+//RCC_EP_DEV0_2_EP_PCIE_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
+//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
+//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
+//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
+//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
+#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
+//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                  0x3
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                    0x00000008L
+//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
+//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                           0x1d
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                             0x20000000L
+//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT                                         0x4
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK                                           0x00000010L
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
+#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
+//RCC_EP_DEV0_2_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
+#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
+//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
+//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
+//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                            0x8
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                               0x12
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                   0x18
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                   0x19
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                   0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT                                   0x1b
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT                                   0x1c
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT                                   0x1d
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT                                   0x1e
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT                                   0x1f
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                              0x00000700L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                 0x00040000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                     0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                     0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                     0x04000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK                                     0x08000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK                                     0x10000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK                                     0x20000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK                                     0x40000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK                                     0x80000000L
+//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
+//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                          0x0
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                          0x1
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                          0x2
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                            0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                            0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                            0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC
+//RCC_DWN_DEV0_2_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
+//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
+//RCC_DWN_DEV0_2_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
+//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
+#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
+//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
+#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
+//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
+//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                 0x3
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                   0x00000008L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT                                                0x11
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT                                        0x15
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK                                                     0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK                                                  0x00020000L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK                                          0x00E00000L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT                                             0x18
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                          0x1d
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK                                               0x01000000L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                            0x20000000L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT                                    0x2
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK                                      0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC
+//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                             0x8
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                    0xb
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                               0x00000700L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                      0x00000800L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
+//RCC_DWNP_DEV0_2_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
+//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                           0x0
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                           0x1
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                           0x2
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                             0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                             0x00000002L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                             0x00000004L
+//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                               0x0
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
+//RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT                                          0xa
+#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK                                            0x00000400L
+//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
+#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev1_RCCPORTDEC
+//RCC_DEV1_RCC_VDM_SUPPORT
+#define RCC_DEV1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT                                                         0x0
+#define RCC_DEV1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT                                                        0x1
+#define RCC_DEV1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT                                                    0x2
+#define RCC_DEV1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT                                          0x3
+#define RCC_DEV1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT                                      0x4
+#define RCC_DEV1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK                                                           0x00000001L
+#define RCC_DEV1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK                                                          0x00000002L
+#define RCC_DEV1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK                                                      0x00000004L
+#define RCC_DEV1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK                                            0x00000008L
+#define RCC_DEV1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK                                        0x00000010L
+//RCC_DEV1_RCC_BUS_CNTL
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT                                                              0x2
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT                                                             0x3
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT                                                              0x4
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT                                                           0x5
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT                                                          0x6
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT                                                           0x7
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT                                                          0x8
+#define RCC_DEV1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT                                                   0xc
+#define RCC_DEV1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT                                             0xd
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT                                            0x10
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT                                            0x11
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT                                            0x12
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT                                            0x13
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT                                            0x14
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT                                            0x15
+#define RCC_DEV1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT                                                   0x18
+#define RCC_DEV1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                   0x19
+#define RCC_DEV1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT                                              0x1c
+#define RCC_DEV1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                              0x1d
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS_MASK                                                                0x00000004L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK                                                               0x00000008L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_BM_DIS_MASK                                                                0x00000010L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK                                                             0x00000020L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK                                                            0x00000040L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK                                                             0x00000080L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK                                                            0x00000100L
+#define RCC_DEV1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK                                                     0x00001000L
+#define RCC_DEV1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK                                               0x00002000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK                                              0x00010000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK                                              0x00020000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK                                              0x00040000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK                                              0x00080000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK                                              0x00100000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK                                              0x00200000L
+#define RCC_DEV1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK                                                     0x01000000L
+#define RCC_DEV1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK                                                     0x0E000000L
+#define RCC_DEV1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK                                                0x10000000L
+#define RCC_DEV1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK                                                0xE0000000L
+//RCC_DEV1_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT                                     0x7
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT                                   0x8
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT                                      0x9
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT                                      0xa
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT                                   0xb
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT                                    0xc
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT                                        0xd
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT                        0xe
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT                                   0x10
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT                             0x11
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT                                 0x12
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT                       0x13
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK                                       0x00000080L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK                                     0x00000100L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK                                        0x00000200L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK                                        0x00000400L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK                                     0x00000800L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK                                      0x00001000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK                                          0x00002000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK                          0x00004000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK                                     0x00010000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK                               0x00020000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK                                   0x00040000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK                         0x00080000L
+//RCC_DEV1_RCC_DEV0_LINK_CNTL
+#define RCC_DEV1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT                                                    0x0
+#define RCC_DEV1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT                                                   0x8
+#define RCC_DEV1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK                                                      0x00000001L
+#define RCC_DEV1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK                                                     0x00000100L
+//RCC_DEV1_RCC_CMN_LINK_CNTL
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT                                               0x0
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT                                                0x1
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT                                               0x2
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT                                            0x3
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT                                               0x10
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK                                                 0x00000001L
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK                                                  0x00000002L
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK                                                 0x00000004L
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK                                              0x00000008L
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK                                                 0xFFFF0000L
+//RCC_DEV1_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT                                              0x0
+#define RCC_DEV1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT                                              0x8
+#define RCC_DEV1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK                                                0x000000FFL
+#define RCC_DEV1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK                                                0x00001F00L
+//RCC_DEV1_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT                                           0x0
+#define RCC_DEV1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK                                             0x000003FFL
+//RCC_DEV1_RCC_MH_ARB_CNTL
+#define RCC_DEV1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT                                                          0x0
+#define RCC_DEV1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT                                                  0x1
+#define RCC_DEV1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK                                                            0x00000001L
+#define RCC_DEV1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK                                                    0x00007FFEL
+//RCC_DEV1_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT                                   0x0
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT                                0x1
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT                                  0x2
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT                                   0x3
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT                             0x4
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT                                    0x5
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT                                   0xb
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT                                   0x12
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT                                  0x19
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK                                     0x00000001L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK                                  0x00000002L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK                                    0x00000004L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK                                     0x00000008L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK                               0x00000010L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK                                      0x000007E0L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK                                     0x0003F800L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK                                     0x01FC0000L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK                                    0xFE000000L
+//RCC_DEV1_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT                               0x0
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT                                0x6
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT                                           0xc
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT                                        0x11
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK                                 0x0000003FL
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK                                  0x00000FC0L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK                                             0x0001F000L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK                                          0x00FE0000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev1_RCCPORTDEC
+//RCC_EP_DEV1_EP_PCIE_SCRATCH
+#define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                      0x0
+#define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RCC_EP_DEV1_EP_PCIE_CNTL
+#define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                    0x7
+#define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                              0x8
+#define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                 0x1e
+#define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                      0x00000080L
+#define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                                0x00000100L
+#define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                   0x40000000L
+//RCC_EP_DEV1_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                  0x0
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                             0x1
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                                 0x2
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                              0x3
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                  0x4
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                           0x6
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                    0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                               0x00000002L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                   0x00000004L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                                0x00000008L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                    0x00000010L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                             0x00000040L
+//RCC_EP_DEV1_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                            0x0
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                       0x1
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                           0x2
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                        0x3
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                            0x4
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                     0x6
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                              0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                         0x00000002L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                             0x00000004L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                          0x00000008L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                              0x00000010L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                       0x00000040L
+//RCC_EP_DEV1_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                     0x0
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                       0x00000001L
+//RCC_EP_DEV1_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                                0x7
+#define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                  0x00000080L
+//RCC_EP_DEV1_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                         0x0
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                    0x1
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                    0x2
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                    0x3
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                           0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                      0x00000002L
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                      0x00000004L
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                      0x00000008L
+//RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                        0x0
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                         0x3
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                        0x6
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                       0x7
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                        0xa
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                       0xd
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                                 0xe
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                   0xf
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                              0x10
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                     0x11
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                          0x00000007L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                           0x00000038L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                          0x00000040L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                         0x00000380L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                          0x00001C00L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                         0x00002000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                   0x00004000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                     0x00008000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                                0x00010000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                       0x00020000L
+//RCC_EP_DEV1_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                             0x1d
+#define RCC_EP_DEV1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                               0x20000000L
+//RCC_EP_DEV1_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT                                           0x4
+#define RCC_EP_DEV1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK                                             0x00000010L
+//RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
+//RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0xFFL
+//RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                               0x0
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                           0x8
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                                 0x001FL
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                             0x0100L
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV1_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                             0x0
+#define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                               0x1FL
+//RCC_EP_DEV1_EP_PCIEP_RESERVED
+#define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                  0x0
+#define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                    0xFFFFFFFFL
+//RCC_EP_DEV1_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                   0xa
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                    0xc
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                     0x18
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                     0x19
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                     0x1a
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                     0x00000C00L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                      0x00003000L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                       0x01000000L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                       0x02000000L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                       0x04000000L
+//RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                  0x0
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                    0x3
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                       0x8
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                    0x00000007L
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                      0x000000F8L
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                         0x0000FF00L
+//RCC_EP_DEV1_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                0x0
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                              0x8
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                         0x11
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                                 0x12
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                     0x18
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                     0x19
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                     0x1a
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT                                     0x1b
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT                                     0x1c
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT                                     0x1d
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT                                     0x1e
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT                                     0x1f
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                  0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                0x00000700L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                           0x00020000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                   0x00040000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                       0x01000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                       0x02000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                       0x04000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK                                       0x08000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK                                       0x10000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK                                       0x20000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK                                       0x40000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK                                       0x80000000L
+//RCC_EP_DEV1_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                         0x8
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                  0x9
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                           0x14
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                         0x15
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                           0x16
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                        0x18
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                            0x19
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                        0x1a
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                           0x00000100L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                    0x00000200L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                             0x00100000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                           0x00200000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                             0x00400000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                          0x01000000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                              0x02000000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                          0x04000000L
+//RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                            0x0
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                            0x1
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                            0x2
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                              0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                              0x00000002L
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                              0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev1_RCCPORTDEC
+//RCC_DWN_DEV1_DN_PCIE_RESERVED
+#define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                   0x0
+#define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                     0xFFFFFFFFL
+//RCC_DWN_DEV1_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                     0x0
+#define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                       0xFFFFFFFFL
+//RCC_DWN_DEV1_DN_PCIE_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                      0x0
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                                0x7
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                0x1e
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                        0x00000001L
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                  0x00000080L
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                  0x40000000L
+//RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                  0x19
+#define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                    0x06000000L
+//RCC_DWN_DEV1_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                                 0x1c
+#define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                   0x70000000L
+//RCC_DWN_DEV1_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                               0x7
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                     0x8
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                 0x00000080L
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                       0x00000100L
+//RCC_DWN_DEV1_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                        0x0
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                   0x1
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                   0x2
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                   0x3
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                          0x00000001L
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                     0x00000002L
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                     0x00000004L
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                     0x00000008L
+//RCC_DWN_DEV1_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT                                                     0x0
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT                                                  0x11
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT                                          0x15
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK                                                       0x00000001L
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK                                                    0x00020000L
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK                                            0x00E00000L
+//RCC_DWN_DEV1_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT                                               0x18
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                            0x1d
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK                                                 0x01000000L
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                              0x20000000L
+//RCC_DWN_DEV1_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT                                      0x2
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK                                        0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev1_RCCPORTDEC
+//RCC_DWNP_DEV1_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                 0x0
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                               0x8
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                      0xb
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                          0x11
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                   0x00000001L
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                 0x00000700L
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                        0x00000800L
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                            0x00020000L
+//RCC_DWNP_DEV1_PCIE_RX_CNTL
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                          0x8
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                                0x9
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                            0x14
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                       0x15
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                             0x1b
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                            0x00000100L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                  0x00000200L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                              0x00100000L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                         0x00200000L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                               0x08000000L
+//RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                             0x0
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                             0x1
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                             0x2
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                               0x00000001L
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                               0x00000002L
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                               0x00000004L
+//RCC_DWNP_DEV1_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                                 0x0
+#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                       0x1b
+#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                   0x00000001L
+#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                         0x08000000L
+//RCC_DWNP_DEV1_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT                                            0xa
+#define RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK                                              0x00000400L
+//RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                       0x0
+#define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev2_RCCPORTDEC
+//RCC_DEV2_RCC_VDM_SUPPORT
+#define RCC_DEV2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT                                                         0x0
+#define RCC_DEV2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT                                                        0x1
+#define RCC_DEV2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT                                                    0x2
+#define RCC_DEV2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT                                          0x3
+#define RCC_DEV2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT                                      0x4
+#define RCC_DEV2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK                                                           0x00000001L
+#define RCC_DEV2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK                                                          0x00000002L
+#define RCC_DEV2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK                                                      0x00000004L
+#define RCC_DEV2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK                                            0x00000008L
+#define RCC_DEV2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK                                        0x00000010L
+//RCC_DEV2_RCC_BUS_CNTL
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT                                                              0x2
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT                                                             0x3
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT                                                              0x4
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT                                                           0x5
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT                                                          0x6
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT                                                           0x7
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT                                                          0x8
+#define RCC_DEV2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT                                                   0xc
+#define RCC_DEV2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT                                             0xd
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT                                            0x10
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT                                            0x11
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT                                            0x12
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT                                            0x13
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT                                            0x14
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT                                            0x15
+#define RCC_DEV2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT                                                   0x18
+#define RCC_DEV2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                   0x19
+#define RCC_DEV2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT                                              0x1c
+#define RCC_DEV2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                              0x1d
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS_MASK                                                                0x00000004L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK                                                               0x00000008L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_BM_DIS_MASK                                                                0x00000010L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK                                                             0x00000020L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK                                                            0x00000040L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK                                                             0x00000080L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK                                                            0x00000100L
+#define RCC_DEV2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK                                                     0x00001000L
+#define RCC_DEV2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK                                               0x00002000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK                                              0x00010000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK                                              0x00020000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK                                              0x00040000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK                                              0x00080000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK                                              0x00100000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK                                              0x00200000L
+#define RCC_DEV2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK                                                     0x01000000L
+#define RCC_DEV2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK                                                     0x0E000000L
+#define RCC_DEV2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK                                                0x10000000L
+#define RCC_DEV2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK                                                0xE0000000L
+//RCC_DEV2_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT                                     0x7
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT                                   0x8
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT                                      0x9
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT                                      0xa
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT                                   0xb
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT                                    0xc
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT                                        0xd
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT                        0xe
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT                                   0x10
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT                             0x11
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT                                 0x12
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT                       0x13
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK                                       0x00000080L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK                                     0x00000100L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK                                        0x00000200L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK                                        0x00000400L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK                                     0x00000800L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK                                      0x00001000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK                                          0x00002000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK                          0x00004000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK                                     0x00010000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK                               0x00020000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK                                   0x00040000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK                         0x00080000L
+//RCC_DEV2_RCC_DEV0_LINK_CNTL
+#define RCC_DEV2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT                                                    0x0
+#define RCC_DEV2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT                                                   0x8
+#define RCC_DEV2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK                                                      0x00000001L
+#define RCC_DEV2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK                                                     0x00000100L
+//RCC_DEV2_RCC_CMN_LINK_CNTL
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT                                               0x0
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT                                                0x1
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT                                               0x2
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT                                            0x3
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT                                               0x10
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK                                                 0x00000001L
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK                                                  0x00000002L
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK                                                 0x00000004L
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK                                              0x00000008L
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK                                                 0xFFFF0000L
+//RCC_DEV2_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT                                              0x0
+#define RCC_DEV2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT                                              0x8
+#define RCC_DEV2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK                                                0x000000FFL
+#define RCC_DEV2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK                                                0x00001F00L
+//RCC_DEV2_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT                                           0x0
+#define RCC_DEV2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK                                             0x000003FFL
+//RCC_DEV2_RCC_MH_ARB_CNTL
+#define RCC_DEV2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT                                                          0x0
+#define RCC_DEV2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT                                                  0x1
+#define RCC_DEV2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK                                                            0x00000001L
+#define RCC_DEV2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK                                                    0x00007FFEL
+//RCC_DEV2_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT                                   0x0
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT                                0x1
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT                                  0x2
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT                                   0x3
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT                             0x4
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT                                    0x5
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT                                   0xb
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT                                   0x12
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT                                  0x19
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK                                     0x00000001L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK                                  0x00000002L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK                                    0x00000004L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK                                     0x00000008L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK                               0x00000010L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK                                      0x000007E0L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK                                     0x0003F800L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK                                     0x01FC0000L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK                                    0xFE000000L
+//RCC_DEV2_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT                               0x0
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT                                0x6
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT                                           0xc
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT                                        0x11
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK                                 0x0000003FL
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK                                  0x00000FC0L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK                                             0x0001F000L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK                                          0x00FE0000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev2_RCCPORTDEC
+//RCC_EP_DEV2_EP_PCIE_SCRATCH
+#define RCC_EP_DEV2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                      0x0
+#define RCC_EP_DEV2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RCC_EP_DEV2_EP_PCIE_CNTL
+#define RCC_EP_DEV2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                    0x7
+#define RCC_EP_DEV2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                              0x8
+#define RCC_EP_DEV2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                 0x1e
+#define RCC_EP_DEV2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                      0x00000080L
+#define RCC_EP_DEV2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                                0x00000100L
+#define RCC_EP_DEV2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                   0x40000000L
+//RCC_EP_DEV2_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                  0x0
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                             0x1
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                                 0x2
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                              0x3
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                  0x4
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                           0x6
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                    0x00000001L
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                               0x00000002L
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                   0x00000004L
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                                0x00000008L
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                    0x00000010L
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                             0x00000040L
+//RCC_EP_DEV2_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                            0x0
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                       0x1
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                           0x2
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                        0x3
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                            0x4
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                     0x6
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                              0x00000001L
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                         0x00000002L
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                             0x00000004L
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                          0x00000008L
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                              0x00000010L
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                       0x00000040L
+//RCC_EP_DEV2_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                     0x0
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                       0x00000001L
+//RCC_EP_DEV2_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                                0x7
+#define RCC_EP_DEV2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                  0x00000080L
+//RCC_EP_DEV2_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                         0x0
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                    0x1
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                    0x2
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                    0x3
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                           0x00000001L
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                      0x00000002L
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                      0x00000004L
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                      0x00000008L
+//RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                        0x0
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                         0x3
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                        0x6
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                       0x7
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                        0xa
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                       0xd
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                                 0xe
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                   0xf
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                              0x10
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                     0x11
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                          0x00000007L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                           0x00000038L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                          0x00000040L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                         0x00000380L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                          0x00001C00L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                         0x00002000L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                   0x00004000L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                     0x00008000L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                                0x00010000L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                       0x00020000L
+//RCC_EP_DEV2_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                             0x1d
+#define RCC_EP_DEV2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                               0x20000000L
+//RCC_EP_DEV2_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT                                           0x4
+#define RCC_EP_DEV2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK                                             0x00000010L
+//RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
+//RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0xFFL
+//RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                               0x0
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                           0x8
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                                 0x001FL
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                             0x0100L
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                               0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                                 0xFFL
+//RCC_EP_DEV2_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                             0x0
+#define RCC_EP_DEV2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                               0x1FL
+//RCC_EP_DEV2_EP_PCIEP_RESERVED
+#define RCC_EP_DEV2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                  0x0
+#define RCC_EP_DEV2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                    0xFFFFFFFFL
+//RCC_EP_DEV2_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                   0xa
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                    0xc
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                     0x18
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                     0x19
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                     0x1a
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                     0x00000C00L
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                      0x00003000L
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                       0x01000000L
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                       0x02000000L
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                       0x04000000L
+//RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                  0x0
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                    0x3
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                       0x8
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                    0x00000007L
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                      0x000000F8L
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                         0x0000FF00L
+//RCC_EP_DEV2_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                0x0
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                              0x8
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                         0x11
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                                 0x12
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                     0x18
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                     0x19
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                     0x1a
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT                                     0x1b
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT                                     0x1c
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT                                     0x1d
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT                                     0x1e
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT                                     0x1f
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                  0x00000001L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                0x00000700L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                           0x00020000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                   0x00040000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                       0x01000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                       0x02000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                       0x04000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK                                       0x08000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK                                       0x10000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK                                       0x20000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK                                       0x40000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK                                       0x80000000L
+//RCC_EP_DEV2_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                         0x8
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                  0x9
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                           0x14
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                         0x15
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                           0x16
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                        0x18
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                            0x19
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                        0x1a
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                           0x00000100L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                    0x00000200L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                             0x00100000L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                           0x00200000L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                             0x00400000L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                          0x01000000L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                              0x02000000L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                          0x04000000L
+//RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                            0x0
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                            0x1
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                            0x2
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                              0x00000001L
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                              0x00000002L
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                              0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev2_RCCPORTDEC
+//RCC_DWN_DEV2_DN_PCIE_RESERVED
+#define RCC_DWN_DEV2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                   0x0
+#define RCC_DWN_DEV2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                     0xFFFFFFFFL
+//RCC_DWN_DEV2_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                     0x0
+#define RCC_DWN_DEV2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                       0xFFFFFFFFL
+//RCC_DWN_DEV2_DN_PCIE_CNTL
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                      0x0
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                                0x7
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                0x1e
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                        0x00000001L
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                  0x00000080L
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                  0x40000000L
+//RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                  0x19
+#define RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                    0x06000000L
+//RCC_DWN_DEV2_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                                 0x1c
+#define RCC_DWN_DEV2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                   0x70000000L
+//RCC_DWN_DEV2_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                               0x7
+#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                     0x8
+#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                 0x00000080L
+#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                       0x00000100L
+//RCC_DWN_DEV2_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                        0x0
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                   0x1
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                   0x2
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                   0x3
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                          0x00000001L
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                     0x00000002L
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                     0x00000004L
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                     0x00000008L
+//RCC_DWN_DEV2_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT                                                     0x0
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT                                                  0x11
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT                                          0x15
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK                                                       0x00000001L
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK                                                    0x00020000L
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK                                            0x00E00000L
+//RCC_DWN_DEV2_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT                                               0x18
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                            0x1d
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK                                                 0x01000000L
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                              0x20000000L
+//RCC_DWN_DEV2_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT                                      0x2
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK                                        0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev2_RCCPORTDEC
+//RCC_DWNP_DEV2_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                 0x0
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                               0x8
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                      0xb
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                          0x11
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                   0x00000001L
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                 0x00000700L
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                        0x00000800L
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                            0x00020000L
+//RCC_DWNP_DEV2_PCIE_RX_CNTL
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                          0x8
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                                0x9
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                            0x14
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                       0x15
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                             0x1b
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                            0x00000100L
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                  0x00000200L
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                              0x00100000L
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                         0x00200000L
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                               0x08000000L
+//RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                             0x0
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                             0x1
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                             0x2
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                               0x00000001L
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                               0x00000002L
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                               0x00000004L
+//RCC_DWNP_DEV2_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                                 0x0
+#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                       0x1b
+#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                   0x00000001L
+#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                         0x08000000L
+//RCC_DWNP_DEV2_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT                                            0xa
+#define RCC_DWNP_DEV2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK                                              0x00000400L
+//RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                       0x0
+#define RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk
+//NBIF_STRAP_BIOS_CNTL
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT                                                       0x0
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK                                                         0x00000001L
+//MISC_SCRATCH
+#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT                                                                    0x0
+#define MISC_SCRATCH__MISC_SCRATCH0_MASK                                                                      0xFFFFFFFFL
+//INTR_LINE_POLARITY
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT                                                    0x0
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1__SHIFT                                                    0x8
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV2__SHIFT                                                    0x10
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK                                                      0x000000FFL
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1_MASK                                                      0x0000FF00L
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV2_MASK                                                      0x00FF0000L
+//INTR_LINE_ENABLE
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT                                                        0x0
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1__SHIFT                                                        0x8
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV2__SHIFT                                                        0x10
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK                                                          0x000000FFL
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1_MASK                                                          0x0000FF00L
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV2_MASK                                                          0x00FF0000L
+//OUTSTANDING_VC_ALLOC
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT                                                0x0
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT                                                0x2
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT                                                0x4
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT                                                0x6
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT                                                0x8
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT                                                0xa
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT                                                0xc
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT                                                0xe
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT                                                     0x10
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT                                                0x18
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT                                                0x1a
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT                                                     0x1c
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK                                                  0x00000003L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK                                                  0x0000000CL
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK                                                  0x00000030L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK                                                  0x000000C0L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK                                                  0x00000300L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK                                                  0x00000C00L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK                                                  0x00003000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK                                                  0x0000C000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK                                                       0x000F0000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK                                                  0x03000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK                                                  0x0C000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK                                                       0xF0000000L
+//BIFC_MISC_CTRL0
+#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT                                                           0x4
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT                                                     0x8
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT                                                            0x9
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT                                                        0xa
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT                                                   0xb
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT                                                   0xc
+#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT                                                      0xd
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT                                                     0x10
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT                                                     0x11
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT                                               0x12
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT                                                              0x13
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT                                                         0x14
+#define BIFC_MISC_CTRL0__VC5_DMA_IOCFG_DIS__SHIFT                                                             0x17
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT                                                      0x18
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT                                                             0x19
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT                                                               0x1a
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT                                                       0x1b
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT                                                              0x1c
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT                                                            0x1f
+#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK                                                             0x000000F0L
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK                                                       0x00000100L
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK                                                              0x00000200L
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK                                                          0x00000400L
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK                                                     0x00000800L
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK                                                     0x00001000L
+#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK                                                        0x00002000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK                                                       0x00010000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK                                                       0x00020000L
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK                                                 0x00040000L
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK                                                                0x00080000L
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK                                                           0x00100000L
+#define BIFC_MISC_CTRL0__VC5_DMA_IOCFG_DIS_MASK                                                               0x00800000L
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK                                                        0x01000000L
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK                                                               0x02000000L
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK                                                                 0x04000000L
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK                                                         0x08000000L
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK                                                                0x10000000L
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK                                                              0x80000000L
+//BIFC_MISC_CTRL1
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT                                                    0x0
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT                                                         0x1
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT                                                         0x2
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT                                                    0x3
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT                                                      0x4
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT                                           0x5
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT                                                          0x6
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT                                                        0x7
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT                                                      0x8
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT                                                  0xa
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT                                                        0xc
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT                                                 0xd
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT                                           0xe
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT                                                              0xf
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT                                                       0x10
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT                                                       0x11
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT                                                       0x12
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT                                                       0x13
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT                                           0x14
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT                                                  0x17
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT                                                      0x18
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT                                                    0x19
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT                                                      0x1a
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT                                                    0x1b
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT                                       0x1c
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT                                                                 0x1d
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT                                                          0x1e
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK                                                      0x00000001L
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK                                                           0x00000002L
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK                                                           0x00000004L
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK                                                      0x00000008L
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK                                                        0x00000010L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK                                             0x00000020L
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK                                                            0x00000040L
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK                                                          0x00000080L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK                                                        0x00000300L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK                                                    0x00000C00L
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK                                                          0x00001000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK                                                   0x00002000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK                                             0x00004000L
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK                                                                0x00008000L
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK                                                         0x00010000L
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK                                                         0x00020000L
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK                                                         0x00040000L
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK                                                         0x00080000L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK                                             0x00100000L
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK                                                    0x00800000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK                                                        0x01000000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK                                                      0x02000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK                                                        0x04000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK                                                      0x08000000L
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK                                         0x10000000L
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK                                                                   0x20000000L
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK                                                            0xC0000000L
+//BIFC_BME_ERR_LOG
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT                                                       0x0
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT                                                       0x1
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT                                                       0x2
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT                                                       0x3
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT                                                       0x4
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT                                                       0x5
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT                                                       0x6
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT                                                       0x7
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0__SHIFT                                                       0x8
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1__SHIFT                                                       0x9
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F0__SHIFT                                                       0xc
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F1__SHIFT                                                       0xd
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F2__SHIFT                                                       0xe
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT                                                 0x10
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT                                                 0x11
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT                                                 0x12
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT                                                 0x13
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT                                                 0x14
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT                                                 0x15
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT                                                 0x16
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT                                                 0x17
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0__SHIFT                                                 0x18
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1__SHIFT                                                 0x19
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F0__SHIFT                                                 0x1c
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F1__SHIFT                                                 0x1d
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F2__SHIFT                                                 0x1e
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0_MASK                                                         0x00000001L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1_MASK                                                         0x00000002L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2_MASK                                                         0x00000004L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3_MASK                                                         0x00000008L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4_MASK                                                         0x00000010L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5_MASK                                                         0x00000020L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6_MASK                                                         0x00000040L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7_MASK                                                         0x00000080L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0_MASK                                                         0x00000100L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1_MASK                                                         0x00000200L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F0_MASK                                                         0x00001000L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F1_MASK                                                         0x00002000L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F2_MASK                                                         0x00004000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK                                                   0x00010000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK                                                   0x00020000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK                                                   0x00040000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK                                                   0x00080000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4_MASK                                                   0x00100000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5_MASK                                                   0x00200000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6_MASK                                                   0x00400000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7_MASK                                                   0x00800000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0_MASK                                                   0x01000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1_MASK                                                   0x02000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F0_MASK                                                   0x10000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F1_MASK                                                   0x20000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F2_MASK                                                   0x40000000L
+//BIFC_LC_TIMER_CTRL
+#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT                                                      0x0
+#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT                                                        0x10
+#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK                                                        0x0000FFFFL
+#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK                                                          0xFFFF0000L
+//BIFC_RCCBIH_BME_ERR_LOG0
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT                                            0x0
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT                                            0x1
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT                                            0x2
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT                                            0x3
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT                                            0x4
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT                                            0x5
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT                                            0x6
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT                                            0x7
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT                                            0x8
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT                                            0x9
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT                                      0x10
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT                                      0x11
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT                                      0x12
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT                                      0x13
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT                                      0x14
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT                                      0x15
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT                                      0x16
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT                                      0x17
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT                                      0x18
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT                                      0x19
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK                                              0x00000001L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK                                              0x00000002L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2_MASK                                              0x00000004L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3_MASK                                              0x00000008L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4_MASK                                              0x00000010L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5_MASK                                              0x00000020L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6_MASK                                              0x00000040L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7_MASK                                              0x00000080L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F0_MASK                                              0x00000100L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F1_MASK                                              0x00000200L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK                                        0x00010000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK                                        0x00020000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK                                        0x00040000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK                                        0x00080000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK                                        0x00100000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK                                        0x00200000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK                                        0x00400000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK                                        0x00800000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0_MASK                                        0x01000000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1_MASK                                        0x02000000L
+//BIFC_RCCBIH_BME_ERR_LOG1
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F0__SHIFT                                            0x0
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F1__SHIFT                                            0x1
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F2__SHIFT                                            0x2
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F0__SHIFT                                      0x10
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F1__SHIFT                                      0x11
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F2__SHIFT                                      0x12
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F0_MASK                                              0x00000001L
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F1_MASK                                              0x00000002L
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F2_MASK                                              0x00000004L
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F0_MASK                                        0x00010000L
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F1_MASK                                        0x00020000L
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F2_MASK                                        0x00040000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F0__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F0__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F1__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F1__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F0_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F0_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F1_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F1_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F2__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F2__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F3__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F3__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F2_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F2_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F3_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F3_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F4__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F4__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F5__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F5__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F4_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F4_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F5_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F5_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F6__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F6__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F7__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F7__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F6_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F6_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F7_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F7_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F0__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F0__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F0__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F0__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F0__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F0__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F0__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F0__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F1__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F1__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F1__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F1__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F1__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F1__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F1__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F1__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F0_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F0_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F0_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F0_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F0_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F0_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F0_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F0_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F1_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F1_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F1_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F1_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F1_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F1_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F1_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F1_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F2__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F2__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F2__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F2__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F2__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F2__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F2__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F2__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F3__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F3__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F3__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F3__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F3__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F3__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F3__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F3__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F2_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F2_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F2_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F2_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F2_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F2_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F2_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F2_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F3_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F3_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F3_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F3_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F3_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F3_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F3_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F3_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F4__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F4__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F4__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F4__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F4__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F4__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F4__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F4__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F5__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F5__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F5__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F5__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F5__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F5__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F5__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F5__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F4_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F4_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F4_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F4_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F4_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F4_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F4_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F4_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F5_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F5_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F5_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F5_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F5_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F5_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F5_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F5_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F6__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F6__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F6__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F6__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F6__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F6__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F6__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F6__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F7__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F7__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F7__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F7__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F7__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F7__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F7__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F7__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F6_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F6_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F6_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F6_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F6_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F6_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F6_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F6_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F7_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F7_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F7_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F7_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F7_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F7_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F7_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F7_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_CNTL2_DEV0
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT                               0x0
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT                               0x4
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT                               0x8
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT                               0xc
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT                               0x10
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT                               0x14
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT                               0x18
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT                               0x1c
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK                                 0x00000001L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK                                 0x00000010L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK                                 0x00000100L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK                                 0x00001000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK                                 0x00010000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK                                 0x00100000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK                                 0x01000000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK                                 0x10000000L
+//BIFC_DMA_ATTR_CNTL2_DEV1
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F0__SHIFT                               0x0
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F1__SHIFT                               0x4
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F2__SHIFT                               0x8
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F3__SHIFT                               0xc
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F4__SHIFT                               0x10
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F5__SHIFT                               0x14
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F6__SHIFT                               0x18
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F7__SHIFT                               0x1c
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F0_MASK                                 0x00000001L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F1_MASK                                 0x00000010L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F2_MASK                                 0x00000100L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F3_MASK                                 0x00001000L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F4_MASK                                 0x00010000L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F5_MASK                                 0x00100000L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F6_MASK                                 0x01000000L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F7_MASK                                 0x10000000L
+//BIFC_DMA_ATTR_CNTL2_DEV2
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F0__SHIFT                               0x0
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F1__SHIFT                               0x4
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F2__SHIFT                               0x8
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F3__SHIFT                               0xc
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F4__SHIFT                               0x10
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F5__SHIFT                               0x14
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F6__SHIFT                               0x18
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F7__SHIFT                               0x1c
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F0_MASK                                 0x00000001L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F1_MASK                                 0x00000010L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F2_MASK                                 0x00000100L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F3_MASK                                 0x00001000L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F4_MASK                                 0x00010000L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F5_MASK                                 0x00100000L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F6_MASK                                 0x01000000L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F7_MASK                                 0x10000000L
+//BME_DUMMY_CNTL_0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT                                                     0x0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT                                                     0x2
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT                                                     0x4
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT                                                     0x6
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT                                                     0x8
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT                                                     0xa
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT                                                     0xc
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT                                                     0xe
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0__SHIFT                                                     0x10
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1__SHIFT                                                     0x12
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2__SHIFT                                                     0x14
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3__SHIFT                                                     0x16
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4__SHIFT                                                     0x18
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5__SHIFT                                                     0x1a
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6__SHIFT                                                     0x1c
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7__SHIFT                                                     0x1e
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK                                                       0x00000003L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK                                                       0x0000000CL
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK                                                       0x00000030L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK                                                       0x000000C0L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK                                                       0x00000300L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK                                                       0x00000C00L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK                                                       0x00003000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK                                                       0x0000C000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0_MASK                                                       0x00030000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1_MASK                                                       0x000C0000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2_MASK                                                       0x00300000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3_MASK                                                       0x00C00000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4_MASK                                                       0x03000000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5_MASK                                                       0x0C000000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6_MASK                                                       0x30000000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7_MASK                                                       0xC0000000L
+//BME_DUMMY_CNTL_1
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F0__SHIFT                                                     0x0
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F1__SHIFT                                                     0x2
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F2__SHIFT                                                     0x4
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F3__SHIFT                                                     0x6
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F4__SHIFT                                                     0x8
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F5__SHIFT                                                     0xa
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F6__SHIFT                                                     0xc
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F7__SHIFT                                                     0xe
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F0_MASK                                                       0x00000003L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F1_MASK                                                       0x0000000CL
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F2_MASK                                                       0x00000030L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F3_MASK                                                       0x000000C0L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F4_MASK                                                       0x00000300L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F5_MASK                                                       0x00000C00L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F6_MASK                                                       0x00003000L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F7_MASK                                                       0x0000C000L
+//BIFC_HSTARB_CNTL
+#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT                                                                  0x0
+#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT                                                               0x8
+#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK                                                                    0x00000003L
+#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK                                                                 0x00000100L
+//BIFC_GSI_CNTL
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT                                                            0x0
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT                                                            0x2
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT                                                         0x5
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT                                                      0x6
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT                                                    0x7
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT                                                   0x8
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT                                                      0x9
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT                                                            0xa
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT                                                            0xc
+#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT                                               0xe
+#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT                                                       0xf
+#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT                                                                0x10
+#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT                                                       0x11
+#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT                                                              0x1b
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT                                                    0x1c
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT                                                   0x1d
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT                                                      0x1e
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT                                                        0x1f
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK                                                              0x00000003L
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK                                                              0x0000001CL
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK                                                           0x00000020L
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK                                                        0x00000040L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK                                                      0x00000080L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK                                                     0x00000100L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK                                                        0x00000200L
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK                                                              0x00000C00L
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK                                                              0x00003000L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK                                                 0x00004000L
+#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK                                                         0x00008000L
+#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK                                                                  0x00010000L
+#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK                                                         0x00020000L
+#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK                                                                0x08000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK                                                      0x10000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK                                                     0x20000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK                                                        0x40000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK                                                          0x80000000L
+//BIFC_PCIEFUNC_CNTL
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT                                                0x0
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT                                             0x10
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK                                                  0x0000FFFFL
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK                                               0x00010000L
+//BIFC_PASID_CHECK_DIS
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT                                                  0x0
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT                                                  0x1
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2__SHIFT                                                  0x2
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3__SHIFT                                                  0x3
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F4__SHIFT                                                  0x4
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F5__SHIFT                                                  0x5
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F6__SHIFT                                                  0x6
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F7__SHIFT                                                  0x7
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F0__SHIFT                                                  0x8
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F1__SHIFT                                                  0x9
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F0__SHIFT                                                  0x10
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F1__SHIFT                                                  0x11
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F2__SHIFT                                                  0x12
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK                                                    0x00000001L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK                                                    0x00000002L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2_MASK                                                    0x00000004L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3_MASK                                                    0x00000008L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F4_MASK                                                    0x00000010L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F5_MASK                                                    0x00000020L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F6_MASK                                                    0x00000040L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F7_MASK                                                    0x00000080L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F0_MASK                                                    0x00000100L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F1_MASK                                                    0x00000200L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F0_MASK                                                    0x00010000L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F1_MASK                                                    0x00020000L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F2_MASK                                                    0x00040000L
+//BIFC_SDP_CNTL_0
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT                                                     0x0
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT                                                     0x8
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT                                                 0x10
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT                                                 0x18
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK                                                       0x000000FFL
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK                                                       0x0000FF00L
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK                                                   0x00FF0000L
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK                                                   0xFF000000L
+//BIFC_SDP_CNTL_1
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT                                                            0x0
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT                                                            0x1
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT                                                        0x2
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT                                                        0x3
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT                                               0x4
+#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT                                                         0x5
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT                                           0x7
+#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT                                                       0x8
+#define BIFC_SDP_CNTL_1__NBIF_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT                                           0x1e
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK                                                              0x00000001L
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK                                                              0x00000002L
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK                                                          0x00000004L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK                                                          0x00000008L
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK                                                 0x00000010L
+#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK                                                           0x00000020L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK                                             0x00000080L
+#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK                                                         0x00000100L
+#define BIFC_SDP_CNTL_1__NBIF_OBFF_HW_URGENT_EARLY_WAKEUP_EN_MASK                                             0x40000000L
+//BIFC_PASID_STS
+#define BIFC_PASID_STS__PASID_STS__SHIFT                                                                      0x0
+#define BIFC_PASID_STS__PASID_STS_MASK                                                                        0x0000000FL
+//BIFC_ATHUB_ACT_CNTL
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT                                                0x0
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT                                                0x8
+#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS__SHIFT                                                   0x9
+#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS__SHIFT                                                   0xa
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT                                          0xb
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK                                                  0x00000007L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK                                                  0x00000100L
+#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS_MASK                                                     0x00000200L
+#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS_MASK                                                     0x00000400L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK                                            0x00000800L
+//BIFC_PERF_CNTL_0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT                                                          0x0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT                                                          0x1
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT                                                       0x8
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT                                                       0x9
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT                                                         0x10
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT                                                         0x18
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK                                                            0x00000001L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK                                                            0x00000002L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK                                                         0x00000100L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK                                                         0x00000200L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK                                                           0x007F0000L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK                                                           0x7F000000L
+//BIFC_PERF_CNTL_1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT                                                           0x0
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT                                                           0x1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT                                                        0x8
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT                                                        0x9
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT                                                          0x10
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT                                                          0x18
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK                                                             0x00000001L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK                                                             0x00000002L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK                                                          0x00000100L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK                                                          0x00000200L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK                                                            0x007F0000L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK                                                            0xFF000000L
+//BIFC_PERF_CNT_MMIO_RD
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT                                                  0x0
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE_MASK                                                    0xFFFFFFFFL
+//BIFC_PERF_CNT_MMIO_WR
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT                                                  0x0
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE_MASK                                                    0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_RD
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT                                                    0x0
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE_MASK                                                      0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_WR
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT                                                    0x0
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE_MASK                                                      0xFFFFFFFFL
+//NBIF_REGIF_ERRSET_CTRL
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT                                         0x0
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK                                           0x00000001L
+//BIFC_SDP_CNTL_2
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT                                                    0x0
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT                                                  0x8
+#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT                                                   0x10
+#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT                                                   0x18
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK                                                      0x000000FFL
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK                                                    0x00000F00L
+#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK                                                     0x000F0000L
+#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK                                                     0x0F000000L
+//NBIF_PGMST_CTRL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT                                                        0x0
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT                                                                0x8
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT                                                    0xa
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT                                                        0xe
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK                                                          0x000000FFL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK                                                                  0x00000100L
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK                                                      0x00003C00L
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK                                                          0x0000C000L
+//NBIF_PGSLV_CTRL
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT                                                      0x0
+#define NBIF_PGSLV_CTRL__NBIF_CFG_PGSLV_EXTCLK_0_IDLE_HYSTERESIS__SHIFT                                       0x5
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK                                                        0x0000001FL
+#define NBIF_PGSLV_CTRL__NBIF_CFG_PGSLV_EXTCLK_0_IDLE_HYSTERESIS_MASK                                         0x000003E0L
+//NBIF_PG_MISC_CTRL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT                                          0x0
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT                                          0x5
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT                                                        0xa
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT                                                           0xd
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT                                                        0xe
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT                                                           0x10
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT                                             0x18
+#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT                                                   0x1e
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT                                                   0x1f
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK                                            0x0000001FL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK                                            0x000003E0L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK                                                          0x00000400L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK                                                             0x00002000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK                                                          0x00004000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK                                                             0x00010000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK                                               0x3F000000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK                                                     0x40000000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK                                                     0x80000000L
+//NBIF_HST_MISC_CTRL
+//SMN_MST_EP_CNTL3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT                                                0x0
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT                                                0x1
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT                                                0x2
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT                                                0x3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT                                                0x4
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT                                                0x5
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT                                                0x6
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT                                                0x7
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0__SHIFT                                                0x8
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1__SHIFT                                                0x9
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2__SHIFT                                                0xa
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3__SHIFT                                                0xb
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4__SHIFT                                                0xc
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5__SHIFT                                                0xd
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6__SHIFT                                                0xe
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7__SHIFT                                                0xf
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF0__SHIFT                                                0x10
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF1__SHIFT                                                0x11
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF2__SHIFT                                                0x12
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF3__SHIFT                                                0x13
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF4__SHIFT                                                0x14
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF5__SHIFT                                                0x15
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF6__SHIFT                                                0x16
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF7__SHIFT                                                0x17
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK                                                  0x00000001L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK                                                  0x00000002L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK                                                  0x00000004L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK                                                  0x00000008L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK                                                  0x00000010L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK                                                  0x00000020L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK                                                  0x00000040L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK                                                  0x00000080L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0_MASK                                                  0x00000100L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1_MASK                                                  0x00000200L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2_MASK                                                  0x00000400L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3_MASK                                                  0x00000800L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4_MASK                                                  0x00001000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5_MASK                                                  0x00002000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6_MASK                                                  0x00004000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7_MASK                                                  0x00008000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF0_MASK                                                  0x00010000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF1_MASK                                                  0x00020000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF2_MASK                                                  0x00040000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF3_MASK                                                  0x00080000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF4_MASK                                                  0x00100000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF5_MASK                                                  0x00200000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF6_MASK                                                  0x00400000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF7_MASK                                                  0x00800000L
+//SMN_MST_EP_CNTL4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT                                                0x0
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT                                                0x1
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT                                                0x2
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT                                                0x3
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT                                                0x4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT                                                0x5
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT                                                0x6
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT                                                0x7
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0__SHIFT                                                0x8
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1__SHIFT                                                0x9
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2__SHIFT                                                0xa
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3__SHIFT                                                0xb
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4__SHIFT                                                0xc
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5__SHIFT                                                0xd
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6__SHIFT                                                0xe
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7__SHIFT                                                0xf
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF0__SHIFT                                                0x10
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF1__SHIFT                                                0x11
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF2__SHIFT                                                0x12
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF3__SHIFT                                                0x13
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF4__SHIFT                                                0x14
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF5__SHIFT                                                0x15
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF6__SHIFT                                                0x16
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF7__SHIFT                                                0x17
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK                                                  0x00000001L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK                                                  0x00000002L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK                                                  0x00000004L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK                                                  0x00000008L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK                                                  0x00000010L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK                                                  0x00000020L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK                                                  0x00000040L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK                                                  0x00000080L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0_MASK                                                  0x00000100L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1_MASK                                                  0x00000200L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2_MASK                                                  0x00000400L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3_MASK                                                  0x00000800L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4_MASK                                                  0x00001000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5_MASK                                                  0x00002000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6_MASK                                                  0x00004000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7_MASK                                                  0x00008000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF0_MASK                                                  0x00010000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF1_MASK                                                  0x00020000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF2_MASK                                                  0x00040000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF3_MASK                                                  0x00080000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF4_MASK                                                  0x00100000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF5_MASK                                                  0x00200000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF6_MASK                                                  0x00400000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF7_MASK                                                  0x00800000L
+//SMN_MST_CNTL1
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT                                                    0x0
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT                                               0x10
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1__SHIFT                                               0x11
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV2__SHIFT                                               0x12
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK                                                      0x00000001L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK                                                 0x00010000L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1_MASK                                                 0x00020000L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV2_MASK                                                 0x00040000L
+//SMN_MST_EP_CNTL5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT                                         0x0
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT                                         0x1
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT                                         0x2
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT                                         0x3
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT                                         0x4
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT                                         0x5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT                                         0x6
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT                                         0x7
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0__SHIFT                                         0x8
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1__SHIFT                                         0x9
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2__SHIFT                                         0xa
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3__SHIFT                                         0xb
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4__SHIFT                                         0xc
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5__SHIFT                                         0xd
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6__SHIFT                                         0xe
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7__SHIFT                                         0xf
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF0__SHIFT                                         0x10
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF1__SHIFT                                         0x11
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF2__SHIFT                                         0x12
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF3__SHIFT                                         0x13
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF4__SHIFT                                         0x14
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF5__SHIFT                                         0x15
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF6__SHIFT                                         0x16
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF7__SHIFT                                         0x17
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK                                           0x00000001L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK                                           0x00000002L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK                                           0x00000004L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK                                           0x00000008L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK                                           0x00000010L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK                                           0x00000020L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK                                           0x00000040L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK                                           0x00000080L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0_MASK                                           0x00000100L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1_MASK                                           0x00000200L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2_MASK                                           0x00000400L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3_MASK                                           0x00000800L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4_MASK                                           0x00001000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5_MASK                                           0x00002000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6_MASK                                           0x00004000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7_MASK                                           0x00008000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF0_MASK                                           0x00010000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF1_MASK                                           0x00020000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF2_MASK                                           0x00040000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF3_MASK                                           0x00080000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF4_MASK                                           0x00100000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF5_MASK                                           0x00200000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF6_MASK                                           0x00400000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF7_MASK                                           0x00800000L
+//BIF_SELFRING_BUFFER_VID
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT                                                  0x0
+#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT                                                    0x8
+#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT                                          0x10
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK                                                    0x000000FFL
+#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK                                                      0x0000FF00L
+#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK                                            0x00FF0000L
+//BIF_SELFRING_VECTOR_CNTL
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT                                                0x0
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT                                                      0x1
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK                                                  0x00000001L
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK                                                        0x00000002L
+//NBIF_STRAP_WRITE_CTRL
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT                                            0x0
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK                                              0x00000001L
+//NBIF_INTX_DSTATE_MISC_CNTL
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT                                      0x0
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT                                      0x1
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT                                    0x2
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT                                         0x3
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT                                         0x4
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT                                                     0x5
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT                                                     0x6
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT                                                   0x7
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK                                        0x00000001L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK                                        0x00000002L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK                                      0x00000004L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK                                           0x00000008L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK                                           0x00000010L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK                                                       0x00000020L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK                                                       0x00000040L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK                                                     0x00000080L
+//NBIF_PENDING_MISC_CNTL
+#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT                                                   0x0
+#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT                                                   0x1
+#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK                                                     0x00000001L
+#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK                                                     0x00000002L
+//BIF_GMI_WRR_WEIGHT
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT                                               0x1d
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT                                                       0x1e
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT                                                  0x1f
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK                                                 0x20000000L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK                                                         0x40000000L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK                                                    0x80000000L
+//BIF_GMI_WRR_WEIGHT2
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT                                                     0x0
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT                                                     0x8
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT                                                     0x10
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT                                                     0x18
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK                                                       0x000000FFL
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK                                                       0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK                                                       0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK                                                       0xFF000000L
+//BIF_GMI_WRR_WEIGHT3
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT                                                     0x0
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT                                                     0x8
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT                                                     0x10
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT                                                     0x18
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK                                                       0x000000FFL
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK                                                       0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK                                                       0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK                                                       0xFF000000L
+//NBIF_PWRBRK_REQUEST
+#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT                                                       0x0
+#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK                                                         0x00000001L
+//BIF_ATOMIC_ERR_LOG_DEV0_F0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F4
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F5
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F6
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F7
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_OPCODE_DEV0_F7__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_REQEN_LOW_DEV0_F7__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_LENGTH_DEV0_F7__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_NR_DEV0_F7__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F7__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F7__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F7__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_NR_DEV0_F7__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_OPCODE_DEV0_F7_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_REQEN_LOW_DEV0_F7_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_LENGTH_DEV0_F7_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_NR_DEV0_F7_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F7_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F7_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F7_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_NR_DEV0_F7_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV1_F0
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_OPCODE_DEV1_F0__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_REQEN_LOW_DEV1_F0__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_LENGTH_DEV1_F0__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_NR_DEV1_F0__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_OPCODE_DEV1_F0__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV1_F0__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_LENGTH_DEV1_F0__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_NR_DEV1_F0__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_OPCODE_DEV1_F0_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_REQEN_LOW_DEV1_F0_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_LENGTH_DEV1_F0_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_NR_DEV1_F0_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_OPCODE_DEV1_F0_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV1_F0_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_LENGTH_DEV1_F0_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_NR_DEV1_F0_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV1_F1
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_OPCODE_DEV1_F1__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_REQEN_LOW_DEV1_F1__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_LENGTH_DEV1_F1__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_NR_DEV1_F1__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_OPCODE_DEV1_F1__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV1_F1__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_LENGTH_DEV1_F1__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_NR_DEV1_F1__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_OPCODE_DEV1_F1_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_REQEN_LOW_DEV1_F1_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_LENGTH_DEV1_F1_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_NR_DEV1_F1_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_OPCODE_DEV1_F1_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV1_F1_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_LENGTH_DEV1_F1_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_NR_DEV1_F1_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV2_F0
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_OPCODE_DEV2_F0__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_REQEN_LOW_DEV2_F0__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_LENGTH_DEV2_F0__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_NR_DEV2_F0__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_OPCODE_DEV2_F0__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F0__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_LENGTH_DEV2_F0__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_NR_DEV2_F0__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_OPCODE_DEV2_F0_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_REQEN_LOW_DEV2_F0_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_LENGTH_DEV2_F0_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_NR_DEV2_F0_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_OPCODE_DEV2_F0_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F0_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_LENGTH_DEV2_F0_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_NR_DEV2_F0_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV2_F1
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_OPCODE_DEV2_F1__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_REQEN_LOW_DEV2_F1__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_LENGTH_DEV2_F1__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_NR_DEV2_F1__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_OPCODE_DEV2_F1__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F1__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_LENGTH_DEV2_F1__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_NR_DEV2_F1__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_OPCODE_DEV2_F1_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_REQEN_LOW_DEV2_F1_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_LENGTH_DEV2_F1_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_NR_DEV2_F1_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_OPCODE_DEV2_F1_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F1_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_LENGTH_DEV2_F1_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_NR_DEV2_F1_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV2_F2
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_OPCODE_DEV2_F2__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_REQEN_LOW_DEV2_F2__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_LENGTH_DEV2_F2__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_NR_DEV2_F2__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_OPCODE_DEV2_F2__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F2__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_LENGTH_DEV2_F2__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_NR_DEV2_F2__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_OPCODE_DEV2_F2_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_REQEN_LOW_DEV2_F2_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_LENGTH_DEV2_F2_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_NR_DEV2_F2_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_OPCODE_DEV2_F2_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F2_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_LENGTH_DEV2_F2_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_NR_DEV2_F2_MASK                                           0x00080000L
+//BIF_DMA_MP4_ERR_LOG
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT                                                    0x0
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT                                               0x1
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT                                              0x10
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT                                         0x11
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK                                                      0x00000001L
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK                                                 0x00000002L
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK                                                0x00010000L
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK                                           0x00020000L
+//BIF_PASID_ERR_LOG
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT                                                           0x0
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT                                                           0x1
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2__SHIFT                                                           0x2
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3__SHIFT                                                           0x3
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F4__SHIFT                                                           0x4
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F5__SHIFT                                                           0x5
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F6__SHIFT                                                           0x6
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F7__SHIFT                                                           0x7
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV1_F0__SHIFT                                                           0x8
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV1_F1__SHIFT                                                           0x9
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F0__SHIFT                                                           0x10
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F1__SHIFT                                                           0x11
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F2__SHIFT                                                           0x12
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK                                                             0x00000001L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK                                                             0x00000002L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2_MASK                                                             0x00000004L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3_MASK                                                             0x00000008L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F4_MASK                                                             0x00000010L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F5_MASK                                                             0x00000020L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F6_MASK                                                             0x00000040L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F7_MASK                                                             0x00000080L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV1_F0_MASK                                                             0x00000100L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV1_F1_MASK                                                             0x00000200L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F0_MASK                                                             0x00010000L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F1_MASK                                                             0x00020000L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F2_MASK                                                             0x00040000L
+//BIF_PASID_ERR_CLR
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT                                                       0x0
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT                                                       0x1
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2__SHIFT                                                       0x2
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3__SHIFT                                                       0x3
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F4__SHIFT                                                       0x4
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F5__SHIFT                                                       0x5
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F6__SHIFT                                                       0x6
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F7__SHIFT                                                       0x7
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F0__SHIFT                                                       0x8
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F1__SHIFT                                                       0x9
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F0__SHIFT                                                       0x10
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F1__SHIFT                                                       0x11
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F2__SHIFT                                                       0x12
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK                                                         0x00000001L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK                                                         0x00000002L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2_MASK                                                         0x00000004L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3_MASK                                                         0x00000008L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F4_MASK                                                         0x00000010L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F5_MASK                                                         0x00000020L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F6_MASK                                                         0x00000040L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F7_MASK                                                         0x00000080L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F0_MASK                                                         0x00000100L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F1_MASK                                                         0x00000200L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F0_MASK                                                         0x00010000L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F1_MASK                                                         0x00020000L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F2_MASK                                                         0x00040000L
+//OBFF_EMU_CFG
+#define OBFF_EMU_CFG__OBFF_EMU_INTR_EN__SHIFT                                                                 0x0
+#define OBFF_EMU_CFG__OBFF_EMU_INTR_EN_MASK                                                                   0x00000001L
+//EP0_INTR_URGENT_CAP
+#define EP0_INTR_URGENT_CAP__EP0_F0_INTR_URGENT_MODE__SHIFT                                                   0x0
+#define EP0_INTR_URGENT_CAP__EP0_F1_INTR_URGENT_MODE__SHIFT                                                   0x2
+#define EP0_INTR_URGENT_CAP__EP0_F2_INTR_URGENT_MODE__SHIFT                                                   0x4
+#define EP0_INTR_URGENT_CAP__EP0_F3_INTR_URGENT_MODE__SHIFT                                                   0x6
+#define EP0_INTR_URGENT_CAP__EP0_F4_INTR_URGENT_MODE__SHIFT                                                   0x8
+#define EP0_INTR_URGENT_CAP__EP0_F5_INTR_URGENT_MODE__SHIFT                                                   0xa
+#define EP0_INTR_URGENT_CAP__EP0_F6_INTR_URGENT_MODE__SHIFT                                                   0xc
+#define EP0_INTR_URGENT_CAP__EP0_F7_INTR_URGENT_MODE__SHIFT                                                   0xe
+#define EP0_INTR_URGENT_CAP__EP0_F0_INTR_URGENT_MODE_MASK                                                     0x00000003L
+#define EP0_INTR_URGENT_CAP__EP0_F1_INTR_URGENT_MODE_MASK                                                     0x0000000CL
+#define EP0_INTR_URGENT_CAP__EP0_F2_INTR_URGENT_MODE_MASK                                                     0x00000030L
+#define EP0_INTR_URGENT_CAP__EP0_F3_INTR_URGENT_MODE_MASK                                                     0x000000C0L
+#define EP0_INTR_URGENT_CAP__EP0_F4_INTR_URGENT_MODE_MASK                                                     0x00000300L
+#define EP0_INTR_URGENT_CAP__EP0_F5_INTR_URGENT_MODE_MASK                                                     0x00000C00L
+#define EP0_INTR_URGENT_CAP__EP0_F6_INTR_URGENT_MODE_MASK                                                     0x00003000L
+#define EP0_INTR_URGENT_CAP__EP0_F7_INTR_URGENT_MODE_MASK                                                     0x0000C000L
+//EP1_INTR_URGENT_CAP
+#define EP1_INTR_URGENT_CAP__EP1_F0_INTR_URGENT_MODE__SHIFT                                                   0x0
+#define EP1_INTR_URGENT_CAP__EP1_F1_INTR_URGENT_MODE__SHIFT                                                   0x2
+#define EP1_INTR_URGENT_CAP__EP1_F0_INTR_URGENT_MODE_MASK                                                     0x00000003L
+#define EP1_INTR_URGENT_CAP__EP1_F1_INTR_URGENT_MODE_MASK                                                     0x0000000CL
+//EP2_INTR_URGENT_CAP
+#define EP2_INTR_URGENT_CAP__EP2_F0_INTR_URGENT_MODE__SHIFT                                                   0x0
+#define EP2_INTR_URGENT_CAP__EP2_F1_INTR_URGENT_MODE__SHIFT                                                   0x2
+#define EP2_INTR_URGENT_CAP__EP2_F2_INTR_URGENT_MODE__SHIFT                                                   0x4
+#define EP2_INTR_URGENT_CAP__EP2_F0_INTR_URGENT_MODE_MASK                                                     0x00000003L
+#define EP2_INTR_URGENT_CAP__EP2_F1_INTR_URGENT_MODE_MASK                                                     0x0000000CL
+#define EP2_INTR_URGENT_CAP__EP2_F2_INTR_URGENT_MODE_MASK                                                     0x00000030L
+//EP_PEND_BLOCK_MSK
+#define EP_PEND_BLOCK_MSK__EP0_F0_PEND_BLOCK_MSK__SHIFT                                                       0x0
+#define EP_PEND_BLOCK_MSK__EP0_F1_PEND_BLOCK_MSK__SHIFT                                                       0x1
+#define EP_PEND_BLOCK_MSK__EP0_F2_PEND_BLOCK_MSK__SHIFT                                                       0x2
+#define EP_PEND_BLOCK_MSK__EP0_F3_PEND_BLOCK_MSK__SHIFT                                                       0x3
+#define EP_PEND_BLOCK_MSK__EP0_F4_PEND_BLOCK_MSK__SHIFT                                                       0x4
+#define EP_PEND_BLOCK_MSK__EP0_F5_PEND_BLOCK_MSK__SHIFT                                                       0x5
+#define EP_PEND_BLOCK_MSK__EP0_F6_PEND_BLOCK_MSK__SHIFT                                                       0x6
+#define EP_PEND_BLOCK_MSK__EP0_F7_PEND_BLOCK_MSK__SHIFT                                                       0x7
+#define EP_PEND_BLOCK_MSK__EP1_F0_PEND_BLOCK_MSK__SHIFT                                                       0x8
+#define EP_PEND_BLOCK_MSK__EP1_F1_PEND_BLOCK_MSK__SHIFT                                                       0x9
+#define EP_PEND_BLOCK_MSK__EP2_F0_PEND_BLOCK_MSK__SHIFT                                                       0x10
+#define EP_PEND_BLOCK_MSK__EP2_F1_PEND_BLOCK_MSK__SHIFT                                                       0x11
+#define EP_PEND_BLOCK_MSK__EP2_F2_PEND_BLOCK_MSK__SHIFT                                                       0x12
+#define EP_PEND_BLOCK_MSK__EP0_F0_PEND_BLOCK_MSK_MASK                                                         0x00000001L
+#define EP_PEND_BLOCK_MSK__EP0_F1_PEND_BLOCK_MSK_MASK                                                         0x00000002L
+#define EP_PEND_BLOCK_MSK__EP0_F2_PEND_BLOCK_MSK_MASK                                                         0x00000004L
+#define EP_PEND_BLOCK_MSK__EP0_F3_PEND_BLOCK_MSK_MASK                                                         0x00000008L
+#define EP_PEND_BLOCK_MSK__EP0_F4_PEND_BLOCK_MSK_MASK                                                         0x00000010L
+#define EP_PEND_BLOCK_MSK__EP0_F5_PEND_BLOCK_MSK_MASK                                                         0x00000020L
+#define EP_PEND_BLOCK_MSK__EP0_F6_PEND_BLOCK_MSK_MASK                                                         0x00000040L
+#define EP_PEND_BLOCK_MSK__EP0_F7_PEND_BLOCK_MSK_MASK                                                         0x00000080L
+#define EP_PEND_BLOCK_MSK__EP1_F0_PEND_BLOCK_MSK_MASK                                                         0x00000100L
+#define EP_PEND_BLOCK_MSK__EP1_F1_PEND_BLOCK_MSK_MASK                                                         0x00000200L
+#define EP_PEND_BLOCK_MSK__EP2_F0_PEND_BLOCK_MSK_MASK                                                         0x00010000L
+#define EP_PEND_BLOCK_MSK__EP2_F1_PEND_BLOCK_MSK_MASK                                                         0x00020000L
+#define EP_PEND_BLOCK_MSK__EP2_F2_PEND_BLOCK_MSK_MASK                                                         0x00040000L
+//NBIF_VWIRE_CTRL
+#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT                                                              0x0
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT                                                       0x4
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT                                                                0x8
+#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT                                                          0x10
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT                                                       0x14
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT                                                              0x1a
+#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK                                                                0x00000001L
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK                                                         0x000000F0L
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK                                                                  0x00000100L
+#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK                                                            0x00010000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK                                                         0x00F00000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK                                                                0x0C000000L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT                                              0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT                                              0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT                                              0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT                                              0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT                                              0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT                                              0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT                                              0x6
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS__SHIFT                                              0x7
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS__SHIFT                                              0x8
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS__SHIFT                                              0x9
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET10_DIS__SHIFT                                             0xa
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET11_DIS__SHIFT                                             0xb
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET12_DIS__SHIFT                                             0xc
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET13_DIS__SHIFT                                             0xd
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET14_DIS__SHIFT                                             0xe
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET15_DIS__SHIFT                                             0xf
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET16_DIS__SHIFT                                             0x10
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET17_DIS__SHIFT                                             0x11
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET18_DIS__SHIFT                                             0x12
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET19_DIS__SHIFT                                             0x13
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET20_DIS__SHIFT                                             0x14
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET21_DIS__SHIFT                                             0x15
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET22_DIS__SHIFT                                             0x16
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET23_DIS__SHIFT                                             0x17
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET24_DIS__SHIFT                                             0x18
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET25_DIS__SHIFT                                             0x19
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET26_DIS__SHIFT                                             0x1a
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK                                                0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK                                                0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK                                                0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK                                                0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK                                                0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK                                                0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK                                                0x00000040L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS_MASK                                                0x00000080L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS_MASK                                                0x00000100L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS_MASK                                                0x00000200L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET10_DIS_MASK                                               0x00000400L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET11_DIS_MASK                                               0x00000800L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET12_DIS_MASK                                               0x00001000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET13_DIS_MASK                                               0x00002000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET14_DIS_MASK                                               0x00004000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET15_DIS_MASK                                               0x00008000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET16_DIS_MASK                                               0x00010000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET17_DIS_MASK                                               0x00020000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET18_DIS_MASK                                               0x00040000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET19_DIS_MASK                                               0x00080000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET20_DIS_MASK                                               0x00100000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET21_DIS_MASK                                               0x00200000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET22_DIS_MASK                                               0x00400000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET23_DIS_MASK                                               0x00800000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET24_DIS_MASK                                               0x01000000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET25_DIS_MASK                                               0x02000000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET26_DIS_MASK                                               0x04000000L
+//NBIF_SMN_VWR_VCHG_RST_CTRL0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT                                     0x0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT                                     0x1
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT                                     0x2
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT                                     0x3
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT                                     0x4
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT                                     0x5
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT                                     0x6
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV__SHIFT                                     0x7
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV__SHIFT                                     0x8
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV__SHIFT                                     0x9
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET10_RST_DEF_REV__SHIFT                                    0xa
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET11_RST_DEF_REV__SHIFT                                    0xb
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET12_RST_DEF_REV__SHIFT                                    0xc
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET13_RST_DEF_REV__SHIFT                                    0xd
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET14_RST_DEF_REV__SHIFT                                    0xe
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET15_RST_DEF_REV__SHIFT                                    0xf
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET16_RST_DEF_REV__SHIFT                                    0x10
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET17_RST_DEF_REV__SHIFT                                    0x11
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET18_RST_DEF_REV__SHIFT                                    0x12
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET19_RST_DEF_REV__SHIFT                                    0x13
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET20_RST_DEF_REV__SHIFT                                    0x14
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET21_RST_DEF_REV__SHIFT                                    0x15
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET22_RST_DEF_REV__SHIFT                                    0x16
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET23_RST_DEF_REV__SHIFT                                    0x17
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET24_RST_DEF_REV__SHIFT                                    0x18
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET25_RST_DEF_REV__SHIFT                                    0x19
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET26_RST_DEF_REV__SHIFT                                    0x1a
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK                                       0x00000001L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK                                       0x00000002L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK                                       0x00000004L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK                                       0x00000008L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK                                       0x00000010L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK                                       0x00000020L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK                                       0x00000040L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV_MASK                                       0x00000080L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV_MASK                                       0x00000100L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV_MASK                                       0x00000200L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET10_RST_DEF_REV_MASK                                      0x00000400L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET11_RST_DEF_REV_MASK                                      0x00000800L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET12_RST_DEF_REV_MASK                                      0x00001000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET13_RST_DEF_REV_MASK                                      0x00002000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET14_RST_DEF_REV_MASK                                      0x00004000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET15_RST_DEF_REV_MASK                                      0x00008000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET16_RST_DEF_REV_MASK                                      0x00010000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET17_RST_DEF_REV_MASK                                      0x00020000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET18_RST_DEF_REV_MASK                                      0x00040000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET19_RST_DEF_REV_MASK                                      0x00080000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET20_RST_DEF_REV_MASK                                      0x00100000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET21_RST_DEF_REV_MASK                                      0x00200000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET22_RST_DEF_REV_MASK                                      0x00400000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET23_RST_DEF_REV_MASK                                      0x00800000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET24_RST_DEF_REV_MASK                                      0x01000000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET25_RST_DEF_REV_MASK                                      0x02000000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET26_RST_DEF_REV_MASK                                      0x04000000L
+//NBIF_SMN_VWR_VCHG_TRIG
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT                                                 0x0
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT                                                 0x1
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT                                                 0x2
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT                                                 0x3
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT                                                 0x4
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT                                                 0x5
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT                                                 0x6
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG__SHIFT                                                 0x7
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG__SHIFT                                                 0x8
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG__SHIFT                                                 0x9
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET10_TRIG__SHIFT                                                0xa
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET11_TRIG__SHIFT                                                0xb
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET12_TRIG__SHIFT                                                0xc
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET13_TRIG__SHIFT                                                0xd
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET14_TRIG__SHIFT                                                0xe
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET15_TRIG__SHIFT                                                0xf
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET16_TRIG__SHIFT                                                0x10
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET17_TRIG__SHIFT                                                0x11
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET18_TRIG__SHIFT                                                0x12
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET19_TRIG__SHIFT                                                0x13
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET20_TRIG__SHIFT                                                0x14
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET21_TRIG__SHIFT                                                0x15
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET22_TRIG__SHIFT                                                0x16
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET23_TRIG__SHIFT                                                0x17
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET24_TRIG__SHIFT                                                0x18
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET25_TRIG__SHIFT                                                0x19
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET26_TRIG__SHIFT                                                0x1a
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK                                                   0x00000001L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK                                                   0x00000002L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK                                                   0x00000004L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK                                                   0x00000008L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK                                                   0x00000010L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK                                                   0x00000020L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK                                                   0x00000040L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG_MASK                                                   0x00000080L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG_MASK                                                   0x00000100L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG_MASK                                                   0x00000200L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET10_TRIG_MASK                                                  0x00000400L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET11_TRIG_MASK                                                  0x00000800L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET12_TRIG_MASK                                                  0x00001000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET13_TRIG_MASK                                                  0x00002000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET14_TRIG_MASK                                                  0x00004000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET15_TRIG_MASK                                                  0x00008000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET16_TRIG_MASK                                                  0x00010000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET17_TRIG_MASK                                                  0x00020000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET18_TRIG_MASK                                                  0x00040000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET19_TRIG_MASK                                                  0x00080000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET20_TRIG_MASK                                                  0x00100000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET21_TRIG_MASK                                                  0x00200000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET22_TRIG_MASK                                                  0x00400000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET23_TRIG_MASK                                                  0x00800000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET24_TRIG_MASK                                                  0x01000000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET25_TRIG_MASK                                                  0x02000000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET26_TRIG_MASK                                                  0x04000000L
+//NBIF_SMN_VWR_WTRIG_CNTL
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT                                                0x0
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT                                                0x1
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT                                                0x2
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT                                                0x3
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT                                                0x4
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT                                                0x5
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT                                                0x6
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS__SHIFT                                                0x7
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS__SHIFT                                                0x8
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS__SHIFT                                                0x9
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET10_DIS__SHIFT                                               0xa
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET11_DIS__SHIFT                                               0xb
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET12_DIS__SHIFT                                               0xc
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET13_DIS__SHIFT                                               0xd
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET14_DIS__SHIFT                                               0xe
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET15_DIS__SHIFT                                               0xf
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET16_DIS__SHIFT                                               0x10
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET17_DIS__SHIFT                                               0x11
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET18_DIS__SHIFT                                               0x12
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET19_DIS__SHIFT                                               0x13
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET20_DIS__SHIFT                                               0x14
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET21_DIS__SHIFT                                               0x15
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET22_DIS__SHIFT                                               0x16
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET23_DIS__SHIFT                                               0x17
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET24_DIS__SHIFT                                               0x18
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET25_DIS__SHIFT                                               0x19
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET26_DIS__SHIFT                                               0x1a
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK                                                  0x00000001L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK                                                  0x00000002L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK                                                  0x00000004L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK                                                  0x00000008L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK                                                  0x00000010L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK                                                  0x00000020L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK                                                  0x00000040L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS_MASK                                                  0x00000080L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS_MASK                                                  0x00000100L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS_MASK                                                  0x00000200L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET10_DIS_MASK                                                 0x00000400L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET11_DIS_MASK                                                 0x00000800L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET12_DIS_MASK                                                 0x00001000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET13_DIS_MASK                                                 0x00002000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET14_DIS_MASK                                                 0x00004000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET15_DIS_MASK                                                 0x00008000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET16_DIS_MASK                                                 0x00010000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET17_DIS_MASK                                                 0x00020000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET18_DIS_MASK                                                 0x00040000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET19_DIS_MASK                                                 0x00080000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET20_DIS_MASK                                                 0x00100000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET21_DIS_MASK                                                 0x00200000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET22_DIS_MASK                                                 0x00400000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET23_DIS_MASK                                                 0x00800000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET24_DIS_MASK                                                 0x01000000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET25_DIS_MASK                                                 0x02000000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET26_DIS_MASK                                                 0x04000000L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL_1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT                                0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT                                0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT                                0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT                                0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT                                0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT                                0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT                                0x6
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV__SHIFT                                0x7
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV__SHIFT                                0x8
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV__SHIFT                                0x9
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET10_DIFFDET_DEF_REV__SHIFT                               0xa
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET11_DIFFDET_DEF_REV__SHIFT                               0xb
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET12_DIFFDET_DEF_REV__SHIFT                               0xc
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET13_DIFFDET_DEF_REV__SHIFT                               0xd
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET14_DIFFDET_DEF_REV__SHIFT                               0xe
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET15_DIFFDET_DEF_REV__SHIFT                               0xf
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET16_DIFFDET_DEF_REV__SHIFT                               0x10
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET17_DIFFDET_DEF_REV__SHIFT                               0x11
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET18_DIFFDET_DEF_REV__SHIFT                               0x12
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET19_DIFFDET_DEF_REV__SHIFT                               0x13
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET20_DIFFDET_DEF_REV__SHIFT                               0x14
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET21_DIFFDET_DEF_REV__SHIFT                               0x15
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET22_DIFFDET_DEF_REV__SHIFT                               0x16
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET23_DIFFDET_DEF_REV__SHIFT                               0x17
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET24_DIFFDET_DEF_REV__SHIFT                               0x18
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET25_DIFFDET_DEF_REV__SHIFT                               0x19
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET26_DIFFDET_DEF_REV__SHIFT                               0x1a
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK                                  0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK                                  0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK                                  0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK                                  0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK                                  0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK                                  0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK                                  0x00000040L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV_MASK                                  0x00000080L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV_MASK                                  0x00000100L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV_MASK                                  0x00000200L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET10_DIFFDET_DEF_REV_MASK                                 0x00000400L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET11_DIFFDET_DEF_REV_MASK                                 0x00000800L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET12_DIFFDET_DEF_REV_MASK                                 0x00001000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET13_DIFFDET_DEF_REV_MASK                                 0x00002000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET14_DIFFDET_DEF_REV_MASK                                 0x00004000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET15_DIFFDET_DEF_REV_MASK                                 0x00008000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET16_DIFFDET_DEF_REV_MASK                                 0x00010000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET17_DIFFDET_DEF_REV_MASK                                 0x00020000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET18_DIFFDET_DEF_REV_MASK                                 0x00040000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET19_DIFFDET_DEF_REV_MASK                                 0x00080000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET20_DIFFDET_DEF_REV_MASK                                 0x00100000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET21_DIFFDET_DEF_REV_MASK                                 0x00200000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET22_DIFFDET_DEF_REV_MASK                                 0x00400000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET23_DIFFDET_DEF_REV_MASK                                 0x00800000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET24_DIFFDET_DEF_REV_MASK                                 0x01000000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET25_DIFFDET_DEF_REV_MASK                                 0x02000000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET26_DIFFDET_DEF_REV_MASK                                 0x04000000L
+//NBIF_MGCG_CTRL_LCLK
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT                                                         0x0
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT                                                       0x1
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT                                                 0x2
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT                                                    0xa
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT                                                    0xb
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT                                                    0xc
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT                                                    0xd
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK                                                           0x00000001L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK                                                         0x00000002L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK                                                   0x000003FCL
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK                                                      0x00000400L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK                                                      0x00000800L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK                                                      0x00001000L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK                                                      0x00002000L
+//NBIF_DS_CTRL_LCLK
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT                                                             0x0
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT                                                          0x10
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK                                                               0x00000001L
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK                                                            0xFFFF0000L
+//SMN_MST_CNTL0
+#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT                                                                    0x0
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT                                                           0x8
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT                                                           0x9
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT                                                            0xa
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT                                                      0xb
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT                                                      0x10
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1__SHIFT                                                      0x11
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV2__SHIFT                                                      0x12
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT                                                      0x14
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1__SHIFT                                                      0x15
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV2__SHIFT                                                      0x16
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT                                                       0x18
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1__SHIFT                                                       0x19
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV2__SHIFT                                                       0x1a
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT                                                 0x1c
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1__SHIFT                                                 0x1d
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV2__SHIFT                                                 0x1e
+#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK                                                                      0x00000003L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK                                                             0x00000100L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK                                                             0x00000200L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK                                                              0x00000400L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK                                                        0x00000800L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK                                                        0x00010000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1_MASK                                                        0x00020000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV2_MASK                                                        0x00040000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK                                                        0x00100000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1_MASK                                                        0x00200000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV2_MASK                                                        0x00400000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK                                                         0x01000000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1_MASK                                                         0x02000000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV2_MASK                                                         0x04000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK                                                   0x10000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1_MASK                                                   0x20000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV2_MASK                                                   0x40000000L
+//SMN_MST_EP_CNTL1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT                                                 0x0
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT                                                 0x1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT                                                 0x2
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT                                                 0x3
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT                                                 0x4
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT                                                 0x5
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT                                                 0x6
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT                                                 0x7
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0__SHIFT                                                 0x8
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1__SHIFT                                                 0x9
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2__SHIFT                                                 0xa
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3__SHIFT                                                 0xb
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4__SHIFT                                                 0xc
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5__SHIFT                                                 0xd
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6__SHIFT                                                 0xe
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7__SHIFT                                                 0xf
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF0__SHIFT                                                 0x10
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF1__SHIFT                                                 0x11
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF2__SHIFT                                                 0x12
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF3__SHIFT                                                 0x13
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF4__SHIFT                                                 0x14
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF5__SHIFT                                                 0x15
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF6__SHIFT                                                 0x16
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF7__SHIFT                                                 0x17
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK                                                   0x00000001L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK                                                   0x00000002L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK                                                   0x00000004L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK                                                   0x00000008L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK                                                   0x00000010L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK                                                   0x00000020L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK                                                   0x00000040L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK                                                   0x00000080L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0_MASK                                                   0x00000100L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1_MASK                                                   0x00000200L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2_MASK                                                   0x00000400L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3_MASK                                                   0x00000800L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4_MASK                                                   0x00001000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5_MASK                                                   0x00002000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6_MASK                                                   0x00004000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7_MASK                                                   0x00008000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF0_MASK                                                   0x00010000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF1_MASK                                                   0x00020000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF2_MASK                                                   0x00040000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF3_MASK                                                   0x00080000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF4_MASK                                                   0x00100000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF5_MASK                                                   0x00200000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF6_MASK                                                   0x00400000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF7_MASK                                                   0x00800000L
+//SMN_MST_EP_CNTL2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT                                           0x0
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT                                           0x1
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT                                           0x2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT                                           0x3
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT                                           0x4
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT                                           0x5
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT                                           0x6
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT                                           0x7
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0__SHIFT                                           0x8
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1__SHIFT                                           0x9
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2__SHIFT                                           0xa
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3__SHIFT                                           0xb
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4__SHIFT                                           0xc
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5__SHIFT                                           0xd
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6__SHIFT                                           0xe
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7__SHIFT                                           0xf
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF0__SHIFT                                           0x10
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF1__SHIFT                                           0x11
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF2__SHIFT                                           0x12
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF3__SHIFT                                           0x13
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF4__SHIFT                                           0x14
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF5__SHIFT                                           0x15
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF6__SHIFT                                           0x16
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF7__SHIFT                                           0x17
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK                                             0x00000001L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK                                             0x00000002L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK                                             0x00000004L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK                                             0x00000008L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK                                             0x00000010L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK                                             0x00000020L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK                                             0x00000040L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK                                             0x00000080L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0_MASK                                             0x00000100L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1_MASK                                             0x00000200L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2_MASK                                             0x00000400L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3_MASK                                             0x00000800L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4_MASK                                             0x00001000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5_MASK                                             0x00002000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6_MASK                                             0x00004000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7_MASK                                             0x00008000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF0_MASK                                             0x00010000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF1_MASK                                             0x00020000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF2_MASK                                             0x00040000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF3_MASK                                             0x00080000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF4_MASK                                             0x00100000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF5_MASK                                             0x00200000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF6_MASK                                             0x00400000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF7_MASK                                             0x00800000L
+//NBIF_SDP_VWR_VCHG_DIS_CTRL
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT                                           0x0
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT                                           0x1
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT                                           0x2
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT                                           0x3
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT                                           0x4
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT                                           0x5
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT                                           0x6
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT                                           0x7
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT                                           0x18
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK                                             0x00000001L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK                                             0x00000002L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK                                             0x00000004L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK                                             0x00000008L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK                                             0x00000010L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK                                             0x00000020L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK                                             0x00000040L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK                                             0x00000080L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK                                             0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT                                  0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT                                  0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT                                  0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT                                  0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT                                  0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT                                  0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT                                  0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT                                  0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT                                  0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK                                    0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK                                    0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK                                    0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK                                    0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK                                    0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK                                    0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK                                    0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK                                    0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK                                    0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT                                 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT                                 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT                                 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT                                 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT                                 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT                                 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT                                 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT                                 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT                                 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK                                   0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK                                   0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK                                   0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK                                   0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK                                   0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK                                   0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK                                   0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK                                   0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK                                   0x01000000L
+//NBIF_SDP_VWR_VCHG_TRIG
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT                                              0x0
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT                                              0x1
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT                                              0x2
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT                                              0x3
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT                                              0x4
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT                                              0x5
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT                                              0x6
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT                                              0x7
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT                                              0x18
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK                                                0x00000001L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK                                                0x00000002L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK                                                0x00000004L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK                                                0x00000008L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK                                                0x00000010L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK                                                0x00000020L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK                                                0x00000040L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK                                                0x00000080L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK                                                0x01000000L
+//NBIF_SHUB_TODET_CTRL
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT                                                       0x0
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT                                               0x1
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT                                               0x8
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT                                                  0x10
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK                                                         0x00000001L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK                                                 0x00000002L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK                                                 0x00000700L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK                                                    0xFFFF0000L
+//NBIF_SHUB_TODET_CLIENT_CTRL
+#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT                                         0x0
+#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK                                           0xFFFFFFFFL
+//NBIF_SHUB_TODET_CLIENT_STATUS
+#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT                                   0x0
+#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK                                     0xFFFFFFFFL
+//NBIF_SHUB_TODET_SYNCFLOOD_CTRL
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT                                   0x0
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK                                     0xFFFFFFFFL
+//BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
+//BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
+//BIFC_GMI_SDP_REQ_POOLCRED_ALLOC
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                     0x0
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                     0x4
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                     0x8
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                     0xc
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                     0x10
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                     0x14
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                     0x18
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                     0x1c
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                       0x0000000FL
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                       0x000000F0L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                       0x00000F00L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                       0x0000F000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                       0x000F0000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                       0x00F00000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                       0x0F000000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                       0xF0000000L
+//BIFC_GMI_SDP_DAT_POOLCRED_ALLOC
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                     0x0
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                     0x4
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                     0x8
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                     0xc
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                     0x10
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                     0x14
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                     0x18
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                     0x1c
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                       0x0000000FL
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                       0x000000F0L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                       0x00000F00L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                       0x0000F000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                       0x000F0000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                       0x00F00000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                       0x0F000000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                       0xF0000000L
+//BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                   0x8
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                   0xc
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                   0x10
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                   0x14
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                   0x18
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                   0x1c
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                     0x00000F00L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                     0x0000F000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                     0x000F0000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                     0x00F00000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                     0x0F000000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                     0xF0000000L
+//BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                   0x8
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                   0xc
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                   0x10
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                   0x14
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                   0x18
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                   0x1c
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                     0x00000F00L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                     0x0000F000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                     0x000F0000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                     0x00F00000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                     0x0F000000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                     0xF0000000L
+//DISCON_HYSTERESIS_HEAD_CTRL
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT                                   0x0
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT                                   0x8
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK                                     0x0000000FL
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK                                     0x00000F00L
+//BIFC_PCIE_BDF_CNTL0
+#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL0__SHIFT                                           0x0
+#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL1__SHIFT                                           0x10
+#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL0_MASK                                             0x0000FFFFL
+#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL1_MASK                                             0xFFFF0000L
+//BIFC_PCIE_BDF_CNTL1
+#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL2__SHIFT                                           0x0
+#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL3__SHIFT                                           0x10
+#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL2_MASK                                             0x0000FFFFL
+#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL3_MASK                                             0xFFFF0000L
+//BIFC_EARLY_WAKEUP_CNTL
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT                                     0x0
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT                                    0x1
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT                                     0x2
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK                                       0x00000001L
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK                                      0x00000002L
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK                                       0x00000004L
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk
+//HARD_RST_CTRL
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT                                                                 0x0
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT                                                          0x1
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT                                                                 0x2
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT                                                          0x3
+#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT                                                                   0x4
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT                                                            0x5
+#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT                                                                   0x6
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT                                                            0x7
+#define HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT                                                               0x9
+#define HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT                                                               0xa
+#define HARD_RST_CTRL__STRAP_RST_EN__SHIFT                                                                    0x17
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT                                                              0x1c
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT                                                              0x1d
+#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT                                                                 0x1e
+#define HARD_RST_CTRL__CORE_RST_EN__SHIFT                                                                     0x1f
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK                                                                   0x00000001L
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK                                                            0x00000002L
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK                                                                   0x00000004L
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK                                                            0x00000008L
+#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK                                                                     0x00000010L
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK                                                              0x00000020L
+#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK                                                                     0x00000040L
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK                                                              0x00000080L
+#define HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK                                                                 0x00000200L
+#define HARD_RST_CTRL__SION_AON_RESET_EN_MASK                                                                 0x00000400L
+#define HARD_RST_CTRL__STRAP_RST_EN_MASK                                                                      0x00800000L
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK                                                                0x10000000L
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK                                                                0x20000000L
+#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK                                                                   0x40000000L
+#define HARD_RST_CTRL__CORE_RST_EN_MASK                                                                       0x80000000L
+//SELF_SOFT_RST
+#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT                                                                   0x0
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT                                                            0x1
+#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT                                                                   0x2
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT                                                            0x3
+#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT                                                                     0x4
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT                                                              0x5
+#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT                                                                     0x6
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT                                                              0x7
+#define SELF_SOFT_RST__DSPT1_CFG_RST__SHIFT                                                                   0x8
+#define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST__SHIFT                                                            0x9
+#define SELF_SOFT_RST__DSPT1_PRV_RST__SHIFT                                                                   0xa
+#define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST__SHIFT                                                            0xb
+#define SELF_SOFT_RST__EP1_CFG_RST__SHIFT                                                                     0xc
+#define SELF_SOFT_RST__EP1_CFG_STICKY_RST__SHIFT                                                              0xd
+#define SELF_SOFT_RST__EP1_PRV_RST__SHIFT                                                                     0xe
+#define SELF_SOFT_RST__EP1_PRV_STICKY_RST__SHIFT                                                              0xf
+#define SELF_SOFT_RST__DSPT2_CFG_RST__SHIFT                                                                   0x10
+#define SELF_SOFT_RST__DSPT2_CFG_STICKY_RST__SHIFT                                                            0x11
+#define SELF_SOFT_RST__DSPT2_PRV_RST__SHIFT                                                                   0x12
+#define SELF_SOFT_RST__DSPT2_PRV_STICKY_RST__SHIFT                                                            0x13
+#define SELF_SOFT_RST__EP2_CFG_RST__SHIFT                                                                     0x14
+#define SELF_SOFT_RST__EP2_CFG_STICKY_RST__SHIFT                                                              0x15
+#define SELF_SOFT_RST__EP2_PRV_RST__SHIFT                                                                     0x16
+#define SELF_SOFT_RST__EP2_PRV_STICKY_RST__SHIFT                                                              0x17
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT                                                               0x18
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT                                                               0x19
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT                                                               0x1a
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT                                                               0x1b
+#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT                                                                 0x1c
+#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT                                                                 0x1d
+#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT                                                                    0x1e
+#define SELF_SOFT_RST__CORE_RST__SHIFT                                                                        0x1f
+#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK                                                                     0x00000001L
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK                                                              0x00000002L
+#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK                                                                     0x00000004L
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK                                                              0x00000008L
+#define SELF_SOFT_RST__EP0_CFG_RST_MASK                                                                       0x00000010L
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK                                                                0x00000020L
+#define SELF_SOFT_RST__EP0_PRV_RST_MASK                                                                       0x00000040L
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK                                                                0x00000080L
+#define SELF_SOFT_RST__DSPT1_CFG_RST_MASK                                                                     0x00000100L
+#define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST_MASK                                                              0x00000200L
+#define SELF_SOFT_RST__DSPT1_PRV_RST_MASK                                                                     0x00000400L
+#define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST_MASK                                                              0x00000800L
+#define SELF_SOFT_RST__EP1_CFG_RST_MASK                                                                       0x00001000L
+#define SELF_SOFT_RST__EP1_CFG_STICKY_RST_MASK                                                                0x00002000L
+#define SELF_SOFT_RST__EP1_PRV_RST_MASK                                                                       0x00004000L
+#define SELF_SOFT_RST__EP1_PRV_STICKY_RST_MASK                                                                0x00008000L
+#define SELF_SOFT_RST__DSPT2_CFG_RST_MASK                                                                     0x00010000L
+#define SELF_SOFT_RST__DSPT2_CFG_STICKY_RST_MASK                                                              0x00020000L
+#define SELF_SOFT_RST__DSPT2_PRV_RST_MASK                                                                     0x00040000L
+#define SELF_SOFT_RST__DSPT2_PRV_STICKY_RST_MASK                                                              0x00080000L
+#define SELF_SOFT_RST__EP2_CFG_RST_MASK                                                                       0x00100000L
+#define SELF_SOFT_RST__EP2_CFG_STICKY_RST_MASK                                                                0x00200000L
+#define SELF_SOFT_RST__EP2_PRV_RST_MASK                                                                       0x00400000L
+#define SELF_SOFT_RST__EP2_PRV_STICKY_RST_MASK                                                                0x00800000L
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK                                                                 0x01000000L
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK                                                                 0x02000000L
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK                                                                 0x04000000L
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK                                                                 0x08000000L
+#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK                                                                   0x10000000L
+#define SELF_SOFT_RST__CORE_STICKY_RST_MASK                                                                   0x20000000L
+#define SELF_SOFT_RST__RELOAD_STRAP_MASK                                                                      0x40000000L
+#define SELF_SOFT_RST__CORE_RST_MASK                                                                          0x80000000L
+//BIF_GFX_DRV_VPU_RST
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT                                                      0x0
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT                                              0x1
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT                                               0x2
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT                                                      0x3
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT                                               0x4
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT                                                      0x5
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT                                               0x6
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT                                                      0x7
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK                                                        0x00000001L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK                                                0x00000002L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK                                                 0x00000004L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK                                                        0x00000008L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK                                                 0x00000010L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK                                                        0x00000020L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK                                                 0x00000040L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK                                                        0x00000080L
+//BIF_RST_MISC_CTRL
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT                                                    0x0
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT                                                                0x2
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT                                                            0x4
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT                                                     0x5
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT                                                      0x6
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT                                                     0x8
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT                                                          0x9
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT                                                       0xa
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT                                                           0xd
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT                                                          0xf
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT                                              0x11
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT                                                       0x17
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT                                                    0x18
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK                                                      0x00000001L
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK                                                                  0x0000000CL
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK                                                              0x00000010L
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK                                                       0x00000020L
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK                                                        0x00000040L
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK                                                       0x00000100L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK                                                            0x00000200L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK                                                         0x00001C00L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK                                                             0x00006000L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK                                                            0x00018000L
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK                                                0x000E0000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK                                                         0x00800000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK                                                      0x03000000L
+//BIF_RST_MISC_CTRL2
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT                                                    0x10
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT                                                    0x11
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT                                                   0x12
+#define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE__SHIFT                                                   0x13
+#define BIF_RST_MISC_CTRL2__ENDP2_LNK_RST_TRANS_IDLE__SHIFT                                                   0x14
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT                                                         0x1f
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK                                                      0x00010000L
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK                                                      0x00020000L
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK                                                     0x00040000L
+#define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE_MASK                                                     0x00080000L
+#define BIF_RST_MISC_CTRL2__ENDP2_LNK_RST_TRANS_IDLE_MASK                                                     0x00100000L
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK                                                           0x80000000L
+//BIF_RST_MISC_CTRL3
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT                                                                0x0
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT                                                        0x4
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT                                                           0x6
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT                                                    0x7
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT                                                    0xa
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT                                                    0xd
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK                                                                  0x0000000FL
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK                                                          0x00000030L
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK                                                             0x00000040L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK                                                      0x00000380L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK                                                      0x00001C00L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK                                                      0x0000E000L
+//DEV0_PF0_FLR_RST_CTRL
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT                                                               0x5
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT                                                        0x6
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT                                                               0x7
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT                                                          0x8
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT                                                  0x9
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT                                                   0xa
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT                                                          0xb
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT                                                   0xc
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT                                                            0xd
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT                                                     0xe
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT                                                            0xf
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT                                                            0x10
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT                                                   0x1f
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK                                                                 0x00000020L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK                                                          0x00000040L
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK                                                                 0x00000080L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK                                                            0x00000100L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK                                                    0x00000200L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK                                                     0x00000400L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK                                                            0x00000800L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK                                                     0x00001000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK                                                              0x00002000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK                                                       0x00004000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK                                                              0x00008000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK                                                              0x00010000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK                                                     0x80000000L
+//DEV0_PF1_FLR_RST_CTRL
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV0_PF2_FLR_RST_CTRL
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV0_PF3_FLR_RST_CTRL
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV0_PF4_FLR_RST_CTRL
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV0_PF5_FLR_RST_CTRL
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV0_PF6_FLR_RST_CTRL
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV0_PF7_FLR_RST_CTRL
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//BIF_INST_RESET_INTR_STS
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT                                               0x0
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT                                      0x1
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT                                                 0x2
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT                                                 0x3
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT                                                 0x4
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS__SHIFT                                               0x8
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT                                      0x9
+#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_INTR_STS__SHIFT                                               0xa
+#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT                                      0xb
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK                                                 0x00000001L
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK                                        0x00000002L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK                                                   0x00000004L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK                                                   0x00000008L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK                                                   0x00000010L
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS_MASK                                                 0x00000100L
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS_MASK                                        0x00000200L
+#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_INTR_STS_MASK                                                 0x00000400L
+#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_CFG_ONLY_INTR_STS_MASK                                        0x00000800L
+//BIF_PF_FLR_INTR_STS
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT                                                     0x0
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT                                                     0x1
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT                                                     0x2
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT                                                     0x3
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT                                                     0x4
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT                                                     0x5
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT                                                     0x6
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT                                                     0x7
+#define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS__SHIFT                                                     0x8
+#define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS__SHIFT                                                     0x9
+#define BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS__SHIFT                                                     0xa
+#define BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS__SHIFT                                                     0xb
+#define BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS__SHIFT                                                     0xc
+#define BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS__SHIFT                                                     0xd
+#define BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS__SHIFT                                                     0xe
+#define BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS__SHIFT                                                     0xf
+#define BIF_PF_FLR_INTR_STS__DEV2_PF0_FLR_INTR_STS__SHIFT                                                     0x10
+#define BIF_PF_FLR_INTR_STS__DEV2_PF1_FLR_INTR_STS__SHIFT                                                     0x11
+#define BIF_PF_FLR_INTR_STS__DEV2_PF2_FLR_INTR_STS__SHIFT                                                     0x12
+#define BIF_PF_FLR_INTR_STS__DEV2_PF3_FLR_INTR_STS__SHIFT                                                     0x13
+#define BIF_PF_FLR_INTR_STS__DEV2_PF4_FLR_INTR_STS__SHIFT                                                     0x14
+#define BIF_PF_FLR_INTR_STS__DEV2_PF5_FLR_INTR_STS__SHIFT                                                     0x15
+#define BIF_PF_FLR_INTR_STS__DEV2_PF6_FLR_INTR_STS__SHIFT                                                     0x16
+#define BIF_PF_FLR_INTR_STS__DEV2_PF7_FLR_INTR_STS__SHIFT                                                     0x17
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK                                                       0x00000001L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK                                                       0x00000002L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK                                                       0x00000004L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK                                                       0x00000008L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK                                                       0x00000010L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK                                                       0x00000020L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK                                                       0x00000040L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK                                                       0x00000080L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS_MASK                                                       0x00000100L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS_MASK                                                       0x00000200L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS_MASK                                                       0x00000400L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS_MASK                                                       0x00000800L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS_MASK                                                       0x00001000L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS_MASK                                                       0x00002000L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS_MASK                                                       0x00004000L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS_MASK                                                       0x00008000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF0_FLR_INTR_STS_MASK                                                       0x00010000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF1_FLR_INTR_STS_MASK                                                       0x00020000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF2_FLR_INTR_STS_MASK                                                       0x00040000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF3_FLR_INTR_STS_MASK                                                       0x00080000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF4_FLR_INTR_STS_MASK                                                       0x00100000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF5_FLR_INTR_STS_MASK                                                       0x00200000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF6_FLR_INTR_STS_MASK                                                       0x00400000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF7_FLR_INTR_STS_MASK                                                       0x00800000L
+//BIF_D3HOTD0_INTR_STS
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT                                                0x0
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT                                                0x1
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT                                                0x2
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT                                                0x3
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT                                                0x4
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT                                                0x5
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT                                                0x6
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT                                                0x7
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS__SHIFT                                                0x8
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS__SHIFT                                                0x9
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS__SHIFT                                                0xa
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS__SHIFT                                                0xb
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS__SHIFT                                                0xc
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS__SHIFT                                                0xd
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS__SHIFT                                                0xe
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS__SHIFT                                                0xf
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF0_D3HOTD0_INTR_STS__SHIFT                                                0x10
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF1_D3HOTD0_INTR_STS__SHIFT                                                0x11
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF2_D3HOTD0_INTR_STS__SHIFT                                                0x12
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF3_D3HOTD0_INTR_STS__SHIFT                                                0x13
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF4_D3HOTD0_INTR_STS__SHIFT                                                0x14
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF5_D3HOTD0_INTR_STS__SHIFT                                                0x15
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF6_D3HOTD0_INTR_STS__SHIFT                                                0x16
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF7_D3HOTD0_INTR_STS__SHIFT                                                0x17
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK                                                  0x00000001L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK                                                  0x00000002L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK                                                  0x00000004L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK                                                  0x00000008L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK                                                  0x00000010L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK                                                  0x00000020L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK                                                  0x00000040L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK                                                  0x00000080L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS_MASK                                                  0x00000100L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS_MASK                                                  0x00000200L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS_MASK                                                  0x00000400L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS_MASK                                                  0x00000800L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS_MASK                                                  0x00001000L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS_MASK                                                  0x00002000L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS_MASK                                                  0x00004000L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS_MASK                                                  0x00008000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF0_D3HOTD0_INTR_STS_MASK                                                  0x00010000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF1_D3HOTD0_INTR_STS_MASK                                                  0x00020000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF2_D3HOTD0_INTR_STS_MASK                                                  0x00040000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF3_D3HOTD0_INTR_STS_MASK                                                  0x00080000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF4_D3HOTD0_INTR_STS_MASK                                                  0x00100000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF5_D3HOTD0_INTR_STS_MASK                                                  0x00200000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF6_D3HOTD0_INTR_STS_MASK                                                  0x00400000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF7_D3HOTD0_INTR_STS_MASK                                                  0x00800000L
+//BIF_POWER_INTR_STS
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT                                                 0x0
+#define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS__SHIFT                                                 0x1
+#define BIF_POWER_INTR_STS__DEV2_PME_TURN_OFF_INTR_STS__SHIFT                                                 0x2
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT                                                      0x10
+#define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS__SHIFT                                                      0x11
+#define BIF_POWER_INTR_STS__PORT2_DSTATE_INTR_STS__SHIFT                                                      0x12
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK                                                   0x00000001L
+#define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS_MASK                                                   0x00000002L
+#define BIF_POWER_INTR_STS__DEV2_PME_TURN_OFF_INTR_STS_MASK                                                   0x00000004L
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK                                                        0x00010000L
+#define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS_MASK                                                        0x00020000L
+#define BIF_POWER_INTR_STS__PORT2_DSTATE_INTR_STS_MASK                                                        0x00040000L
+//BIF_PF_DSTATE_INTR_STS
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT                                               0x0
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT                                               0x1
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT                                               0x2
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT                                               0x3
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT                                               0x4
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT                                               0x5
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT                                               0x6
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT                                               0x7
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS__SHIFT                                               0x8
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS__SHIFT                                               0x9
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS__SHIFT                                               0xa
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS__SHIFT                                               0xb
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS__SHIFT                                               0xc
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS__SHIFT                                               0xd
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS__SHIFT                                               0xe
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS__SHIFT                                               0xf
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF0_DSTATE_INTR_STS__SHIFT                                               0x10
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF1_DSTATE_INTR_STS__SHIFT                                               0x11
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF2_DSTATE_INTR_STS__SHIFT                                               0x12
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF3_DSTATE_INTR_STS__SHIFT                                               0x13
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF4_DSTATE_INTR_STS__SHIFT                                               0x14
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF5_DSTATE_INTR_STS__SHIFT                                               0x15
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF6_DSTATE_INTR_STS__SHIFT                                               0x16
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF7_DSTATE_INTR_STS__SHIFT                                               0x17
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK                                                 0x00000001L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK                                                 0x00000002L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK                                                 0x00000004L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK                                                 0x00000008L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK                                                 0x00000010L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK                                                 0x00000020L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK                                                 0x00000040L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK                                                 0x00000080L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS_MASK                                                 0x00000100L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS_MASK                                                 0x00000200L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS_MASK                                                 0x00000400L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS_MASK                                                 0x00000800L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS_MASK                                                 0x00001000L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS_MASK                                                 0x00002000L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS_MASK                                                 0x00004000L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS_MASK                                                 0x00008000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF0_DSTATE_INTR_STS_MASK                                                 0x00010000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF1_DSTATE_INTR_STS_MASK                                                 0x00020000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF2_DSTATE_INTR_STS_MASK                                                 0x00040000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF3_DSTATE_INTR_STS_MASK                                                 0x00080000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF4_DSTATE_INTR_STS_MASK                                                 0x00100000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF5_DSTATE_INTR_STS_MASK                                                 0x00200000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF6_DSTATE_INTR_STS_MASK                                                 0x00400000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF7_DSTATE_INTR_STS_MASK                                                 0x00800000L
+//SELF_SOFT_RST_2
+#define SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT                                                                 0x0
+#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT                                                          0x1
+#define SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT                                                                 0x2
+#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT                                                          0x3
+#define SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT                                                                   0x4
+#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT                                                            0x5
+#define SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT                                                                   0x6
+#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT                                                            0x7
+#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT                                                           0x18
+#define SELF_SOFT_RST_2__STRAP_RST__SHIFT                                                                     0x19
+#define SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK                                                                   0x00000001L
+#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK                                                            0x00000002L
+#define SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK                                                                   0x00000004L
+#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK                                                            0x00000008L
+#define SELF_SOFT_RST_2__EP3_CFG_RST_MASK                                                                     0x00000010L
+#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK                                                              0x00000020L
+#define SELF_SOFT_RST_2__EP3_PRV_RST_MASK                                                                     0x00000040L
+#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK                                                              0x00000080L
+#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK                                                             0x01000000L
+#define SELF_SOFT_RST_2__STRAP_RST_MASK                                                                       0x02000000L
+//BIF_INST_RESET_INTR_MASK
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT                                             0x0
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT                                    0x1
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT                                               0x2
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT                                               0x3
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT                                               0x4
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK__SHIFT                                             0x8
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT                                    0x9
+#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_INTR_MASK__SHIFT                                             0xa
+#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT                                    0xb
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK                                               0x00000001L
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK                                      0x00000002L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK                                                 0x00000004L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK                                                 0x00000008L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK                                                 0x00000010L
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK_MASK                                               0x00000100L
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK_MASK                                      0x00000200L
+#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_INTR_MASK_MASK                                               0x00000400L
+#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_CFG_ONLY_INTR_MASK_MASK                                      0x00000800L
+//BIF_PF_FLR_INTR_MASK
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT                                                   0x0
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT                                                   0x1
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT                                                   0x2
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT                                                   0x3
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT                                                   0x4
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT                                                   0x5
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT                                                   0x6
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT                                                   0x7
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK__SHIFT                                                   0x8
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK__SHIFT                                                   0x9
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK__SHIFT                                                   0xa
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK__SHIFT                                                   0xb
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK__SHIFT                                                   0xc
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK__SHIFT                                                   0xd
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK__SHIFT                                                   0xe
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK__SHIFT                                                   0xf
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF0_FLR_INTR_MASK__SHIFT                                                   0x10
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF1_FLR_INTR_MASK__SHIFT                                                   0x11
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF2_FLR_INTR_MASK__SHIFT                                                   0x12
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF3_FLR_INTR_MASK__SHIFT                                                   0x13
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF4_FLR_INTR_MASK__SHIFT                                                   0x14
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF5_FLR_INTR_MASK__SHIFT                                                   0x15
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF6_FLR_INTR_MASK__SHIFT                                                   0x16
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF7_FLR_INTR_MASK__SHIFT                                                   0x17
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK                                                     0x00000001L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK                                                     0x00000002L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK                                                     0x00000004L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK                                                     0x00000008L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK                                                     0x00000010L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK                                                     0x00000020L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK                                                     0x00000040L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK                                                     0x00000080L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK_MASK                                                     0x00000100L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK_MASK                                                     0x00000200L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK_MASK                                                     0x00000400L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK_MASK                                                     0x00000800L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK_MASK                                                     0x00001000L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK_MASK                                                     0x00002000L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK_MASK                                                     0x00004000L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK_MASK                                                     0x00008000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF0_FLR_INTR_MASK_MASK                                                     0x00010000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF1_FLR_INTR_MASK_MASK                                                     0x00020000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF2_FLR_INTR_MASK_MASK                                                     0x00040000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF3_FLR_INTR_MASK_MASK                                                     0x00080000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF4_FLR_INTR_MASK_MASK                                                     0x00100000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF5_FLR_INTR_MASK_MASK                                                     0x00200000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF6_FLR_INTR_MASK_MASK                                                     0x00400000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF7_FLR_INTR_MASK_MASK                                                     0x00800000L
+//BIF_D3HOTD0_INTR_MASK
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT                                              0x0
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT                                              0x1
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT                                              0x2
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT                                              0x3
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT                                              0x4
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT                                              0x5
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT                                              0x6
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT                                              0x7
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK__SHIFT                                              0x8
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK__SHIFT                                              0x9
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK__SHIFT                                              0xa
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK__SHIFT                                              0xb
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK__SHIFT                                              0xc
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK__SHIFT                                              0xd
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK__SHIFT                                              0xe
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK__SHIFT                                              0xf
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF0_D3HOTD0_INTR_MASK__SHIFT                                              0x10
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF1_D3HOTD0_INTR_MASK__SHIFT                                              0x11
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF2_D3HOTD0_INTR_MASK__SHIFT                                              0x12
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF3_D3HOTD0_INTR_MASK__SHIFT                                              0x13
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF4_D3HOTD0_INTR_MASK__SHIFT                                              0x14
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF5_D3HOTD0_INTR_MASK__SHIFT                                              0x15
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF6_D3HOTD0_INTR_MASK__SHIFT                                              0x16
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF7_D3HOTD0_INTR_MASK__SHIFT                                              0x17
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK                                                0x00000001L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK                                                0x00000002L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK                                                0x00000004L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK                                                0x00000008L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK                                                0x00000010L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK                                                0x00000020L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK                                                0x00000040L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK                                                0x00000080L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK_MASK                                                0x00000100L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK_MASK                                                0x00000200L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK_MASK                                                0x00000400L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK_MASK                                                0x00000800L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK_MASK                                                0x00001000L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK_MASK                                                0x00002000L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK_MASK                                                0x00004000L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK_MASK                                                0x00008000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF0_D3HOTD0_INTR_MASK_MASK                                                0x00010000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF1_D3HOTD0_INTR_MASK_MASK                                                0x00020000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF2_D3HOTD0_INTR_MASK_MASK                                                0x00040000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF3_D3HOTD0_INTR_MASK_MASK                                                0x00080000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF4_D3HOTD0_INTR_MASK_MASK                                                0x00100000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF5_D3HOTD0_INTR_MASK_MASK                                                0x00200000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF6_D3HOTD0_INTR_MASK_MASK                                                0x00400000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF7_D3HOTD0_INTR_MASK_MASK                                                0x00800000L
+//BIF_POWER_INTR_MASK
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT                                               0x0
+#define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK__SHIFT                                               0x1
+#define BIF_POWER_INTR_MASK__DEV2_PME_TURN_OFF_INTR_MASK__SHIFT                                               0x2
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT                                                    0x10
+#define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK__SHIFT                                                    0x11
+#define BIF_POWER_INTR_MASK__PORT2_DSTATE_INTR_MASK__SHIFT                                                    0x12
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK                                                 0x00000001L
+#define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK_MASK                                                 0x00000002L
+#define BIF_POWER_INTR_MASK__DEV2_PME_TURN_OFF_INTR_MASK_MASK                                                 0x00000004L
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK                                                      0x00010000L
+#define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK_MASK                                                      0x00020000L
+#define BIF_POWER_INTR_MASK__PORT2_DSTATE_INTR_MASK_MASK                                                      0x00040000L
+//BIF_PF_DSTATE_INTR_MASK
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT                                             0x0
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT                                             0x1
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT                                             0x2
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT                                             0x3
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT                                             0x4
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT                                             0x5
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT                                             0x6
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT                                             0x7
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK__SHIFT                                             0x8
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK__SHIFT                                             0x9
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK__SHIFT                                             0xa
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK__SHIFT                                             0xb
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK__SHIFT                                             0xc
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK__SHIFT                                             0xd
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK__SHIFT                                             0xe
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK__SHIFT                                             0xf
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF0_DSTATE_INTR_MASK__SHIFT                                             0x10
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF1_DSTATE_INTR_MASK__SHIFT                                             0x11
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF2_DSTATE_INTR_MASK__SHIFT                                             0x12
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF3_DSTATE_INTR_MASK__SHIFT                                             0x13
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF4_DSTATE_INTR_MASK__SHIFT                                             0x14
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF5_DSTATE_INTR_MASK__SHIFT                                             0x15
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF6_DSTATE_INTR_MASK__SHIFT                                             0x16
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF7_DSTATE_INTR_MASK__SHIFT                                             0x17
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK                                               0x00000001L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK                                               0x00000002L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK                                               0x00000004L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK                                               0x00000008L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK                                               0x00000010L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK                                               0x00000020L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK                                               0x00000040L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK                                               0x00000080L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK_MASK                                               0x00000100L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK_MASK                                               0x00000200L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK_MASK                                               0x00000400L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK_MASK                                               0x00000800L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK_MASK                                               0x00001000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK_MASK                                               0x00002000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK_MASK                                               0x00004000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK_MASK                                               0x00008000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF0_DSTATE_INTR_MASK_MASK                                               0x00010000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF1_DSTATE_INTR_MASK_MASK                                               0x00020000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF2_DSTATE_INTR_MASK_MASK                                               0x00040000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF3_DSTATE_INTR_MASK_MASK                                               0x00080000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF4_DSTATE_INTR_MASK_MASK                                               0x00100000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF5_DSTATE_INTR_MASK_MASK                                               0x00200000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF6_DSTATE_INTR_MASK_MASK                                               0x00400000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF7_DSTATE_INTR_MASK_MASK                                               0x00800000L
+//BIF_PF_FLR_RST
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT                                                               0x0
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT                                                               0x1
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT                                                               0x2
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT                                                               0x3
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT                                                               0x4
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT                                                               0x5
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT                                                               0x6
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT                                                               0x7
+#define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT                                                               0x8
+#define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT                                                               0x9
+#define BIF_PF_FLR_RST__DEV1_PF2_FLR_RST__SHIFT                                                               0xa
+#define BIF_PF_FLR_RST__DEV1_PF3_FLR_RST__SHIFT                                                               0xb
+#define BIF_PF_FLR_RST__DEV1_PF4_FLR_RST__SHIFT                                                               0xc
+#define BIF_PF_FLR_RST__DEV1_PF5_FLR_RST__SHIFT                                                               0xd
+#define BIF_PF_FLR_RST__DEV1_PF6_FLR_RST__SHIFT                                                               0xe
+#define BIF_PF_FLR_RST__DEV1_PF7_FLR_RST__SHIFT                                                               0xf
+#define BIF_PF_FLR_RST__DEV2_PF0_FLR_RST__SHIFT                                                               0x10
+#define BIF_PF_FLR_RST__DEV2_PF1_FLR_RST__SHIFT                                                               0x11
+#define BIF_PF_FLR_RST__DEV2_PF2_FLR_RST__SHIFT                                                               0x12
+#define BIF_PF_FLR_RST__DEV2_PF3_FLR_RST__SHIFT                                                               0x13
+#define BIF_PF_FLR_RST__DEV2_PF4_FLR_RST__SHIFT                                                               0x14
+#define BIF_PF_FLR_RST__DEV2_PF5_FLR_RST__SHIFT                                                               0x15
+#define BIF_PF_FLR_RST__DEV2_PF6_FLR_RST__SHIFT                                                               0x16
+#define BIF_PF_FLR_RST__DEV2_PF7_FLR_RST__SHIFT                                                               0x17
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK                                                                 0x00000001L
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK                                                                 0x00000002L
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK                                                                 0x00000004L
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK                                                                 0x00000008L
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK                                                                 0x00000010L
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK                                                                 0x00000020L
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK                                                                 0x00000040L
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK                                                                 0x00000080L
+#define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK                                                                 0x00000100L
+#define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK                                                                 0x00000200L
+#define BIF_PF_FLR_RST__DEV1_PF2_FLR_RST_MASK                                                                 0x00000400L
+#define BIF_PF_FLR_RST__DEV1_PF3_FLR_RST_MASK                                                                 0x00000800L
+#define BIF_PF_FLR_RST__DEV1_PF4_FLR_RST_MASK                                                                 0x00001000L
+#define BIF_PF_FLR_RST__DEV1_PF5_FLR_RST_MASK                                                                 0x00002000L
+#define BIF_PF_FLR_RST__DEV1_PF6_FLR_RST_MASK                                                                 0x00004000L
+#define BIF_PF_FLR_RST__DEV1_PF7_FLR_RST_MASK                                                                 0x00008000L
+#define BIF_PF_FLR_RST__DEV2_PF0_FLR_RST_MASK                                                                 0x00010000L
+#define BIF_PF_FLR_RST__DEV2_PF1_FLR_RST_MASK                                                                 0x00020000L
+#define BIF_PF_FLR_RST__DEV2_PF2_FLR_RST_MASK                                                                 0x00040000L
+#define BIF_PF_FLR_RST__DEV2_PF3_FLR_RST_MASK                                                                 0x00080000L
+#define BIF_PF_FLR_RST__DEV2_PF4_FLR_RST_MASK                                                                 0x00100000L
+#define BIF_PF_FLR_RST__DEV2_PF5_FLR_RST_MASK                                                                 0x00200000L
+#define BIF_PF_FLR_RST__DEV2_PF6_FLR_RST_MASK                                                                 0x00400000L
+#define BIF_PF_FLR_RST__DEV2_PF7_FLR_RST_MASK                                                                 0x00800000L
+//BIF_DEV0_PF0_DSTATE_VALUE
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV0_PF1_DSTATE_VALUE
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV0_PF2_DSTATE_VALUE
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV0_PF3_DSTATE_VALUE
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV0_PF4_DSTATE_VALUE
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV0_PF5_DSTATE_VALUE
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV0_PF6_DSTATE_VALUE
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV0_PF7_DSTATE_VALUE
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//DEV0_PF0_D3HOTD0_RST_CTRL
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV0_PF1_D3HOTD0_RST_CTRL
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV0_PF2_D3HOTD0_RST_CTRL
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV0_PF3_D3HOTD0_RST_CTRL
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV0_PF4_D3HOTD0_RST_CTRL
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV0_PF5_D3HOTD0_RST_CTRL
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV0_PF6_D3HOTD0_RST_CTRL
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV0_PF7_D3HOTD0_RST_CTRL
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV1_PF0_FLR_RST_CTRL
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV1_PF1_FLR_RST_CTRL
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV1_PF2_FLR_RST_CTRL
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV1_PF3_FLR_RST_CTRL
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV1_PF4_FLR_RST_CTRL
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV1_PF5_FLR_RST_CTRL
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV1_PF6_FLR_RST_CTRL
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV1_PF7_FLR_RST_CTRL
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//BIF_DEV1_PF0_DSTATE_VALUE
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV1_PF1_DSTATE_VALUE
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV1_PF2_DSTATE_VALUE
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV1_PF3_DSTATE_VALUE
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV1_PF4_DSTATE_VALUE
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV1_PF5_DSTATE_VALUE
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV1_PF6_DSTATE_VALUE
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV1_PF7_DSTATE_VALUE
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//DEV1_PF0_D3HOTD0_RST_CTRL
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV1_PF1_D3HOTD0_RST_CTRL
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV1_PF2_D3HOTD0_RST_CTRL
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV1_PF3_D3HOTD0_RST_CTRL
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV1_PF4_D3HOTD0_RST_CTRL
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV1_PF5_D3HOTD0_RST_CTRL
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV1_PF6_D3HOTD0_RST_CTRL
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV1_PF7_D3HOTD0_RST_CTRL
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV2_PF0_FLR_RST_CTRL
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV2_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV2_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV2_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV2_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV2_PF1_FLR_RST_CTRL
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV2_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV2_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV2_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV2_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV2_PF2_FLR_RST_CTRL
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV2_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV2_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV2_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV2_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV2_PF3_FLR_RST_CTRL
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV2_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV2_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV2_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV2_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV2_PF4_FLR_RST_CTRL
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV2_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV2_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV2_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV2_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV2_PF5_FLR_RST_CTRL
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV2_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV2_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV2_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV2_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV2_PF6_FLR_RST_CTRL
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV2_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV2_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV2_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV2_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//DEV2_PF7_FLR_RST_CTRL
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV2_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV2_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV2_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV2_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV2_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV2_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV2_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV2_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV2_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV2_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV2_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV2_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//BIF_DEV2_PF0_DSTATE_VALUE
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV2_PF1_DSTATE_VALUE
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV2_PF2_DSTATE_VALUE
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV2_PF3_DSTATE_VALUE
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV2_PF4_DSTATE_VALUE
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV2_PF5_DSTATE_VALUE
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV2_PF6_DSTATE_VALUE
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV2_PF7_DSTATE_VALUE
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//DEV2_PF0_D3HOTD0_RST_CTRL
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV2_PF1_D3HOTD0_RST_CTRL
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV2_PF2_D3HOTD0_RST_CTRL
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV2_PF3_D3HOTD0_RST_CTRL
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV2_PF4_D3HOTD0_RST_CTRL
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV2_PF5_D3HOTD0_RST_CTRL
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV2_PF6_D3HOTD0_RST_CTRL
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV2_PF7_D3HOTD0_RST_CTRL
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//BIF_PORT0_DSTATE_VALUE
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT                                                 0x0
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT                                                 0x10
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK                                                   0x00000003L
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK                                                   0x00030000L
+//BIF_PORT1_DSTATE_VALUE
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE__SHIFT                                                 0x0
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE__SHIFT                                                 0x10
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE_MASK                                                   0x00000003L
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE_MASK                                                   0x00030000L
+//BIF_PORT2_DSTATE_VALUE
+#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_TGT_VALUE__SHIFT                                                 0x0
+#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_ACK_VALUE__SHIFT                                                 0x10
+#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_TGT_VALUE_MASK                                                   0x00000003L
+#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_ACK_VALUE_MASK                                                   0x00030000L
+
+
+// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk
+//BIFL_RAS_CENTRAL_CNTL
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT                                             0x1d
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT                                                 0x1e
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT                                      0x1f
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK                                               0x20000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK                                                   0x40000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK                                        0x80000000L
+//BIFL_RAS_CENTRAL_STATUS
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT                                                  0x0
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT                                                 0x1
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT                                                  0x2
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT                                                 0x3
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT                                        0x1d
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT                                            0x1e
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT                                                     0x1f
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK                                                    0x00000001L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK                                                   0x00000002L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK                                                    0x00000004L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK                                                   0x00000008L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK                                          0x20000000L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK                                              0x40000000L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK                                                       0x80000000L
+//BIFL_RAS_LEAF0_CTRL
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+//BIFL_RAS_LEAF1_CTRL
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+//BIFL_RAS_LEAF2_CTRL
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+//BIFL_RAS_LEAF3_CTRL
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+//BIFL_RAS_LEAF0_STATUS
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF1_STATUS
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF2_STATUS
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF3_STATUS
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_IOHUB_RAS_IH_CNTL
+#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT                                                    0x0
+#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK                                                      0x00000001L
+//BIFL_RAS_VWR_FROM_IOHUB
+#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT                                                 0x0
+#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK                                                   0x00000001L
+
+
+// addressBlock: nbio_nbif0_nbif_sion_SIONDEC
+//SION_CL0_RdRsp_BurstTarget_REG0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
+//SION_CL0_RdRsp_BurstTarget_REG1
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG1
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG1
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG1
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG1
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG1
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG1
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG1
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG1
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG1
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG1
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG1
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG1
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG1
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG1
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG1
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG1
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG1
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG1
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG1
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG1
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG1
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG1
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG1
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG1
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG1
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG1
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG1
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG1
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG1
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
+//SION_CNTL_REG0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT                                0x0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT                                0x1
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT                                0x2
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT                                0x3
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT                                0x4
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT                                0x5
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT                                0x6
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT                                0x7
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT                                0x8
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT                                0x9
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT                                0xa
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT                                0xb
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT                                0xc
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT                                0xd
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT                                0xe
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT                                0xf
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT                                0x10
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT                                0x11
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT                                0x12
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT                                0x13
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK                                  0x00000001L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK                                  0x00000002L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK                                  0x00000004L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK                                  0x00000008L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK                                  0x00000010L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK                                  0x00000020L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK                                  0x00000040L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK                                  0x00000080L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK                                  0x00000100L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK                                  0x00000200L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK                                  0x00000400L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK                                  0x00000800L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK                                  0x00001000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK                                  0x00002000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK                                  0x00004000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK                                  0x00008000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK                                  0x00010000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK                                  0x00020000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK                                  0x00040000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK                                  0x00080000L
+//SION_CNTL_REG1
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT                                                    0x0
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT                                                              0x8
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK                                                      0x000000FFL
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK                                                                0x0000FF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF0_0_STATUS
+#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF0_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_0_HEADER
+#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF0_0_BIST
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF0_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                    0x0040L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK                                                           0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                               0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                        0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                          0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                          0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                0x0100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                            0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                    0x003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                 0x3F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                   0x003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                  0x0000003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                            0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                              0xFFE00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                           0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                    0x0020L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                 0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK     0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
+//BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
+#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
+//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
+//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                          0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                         0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                            0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                           0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                     0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                    0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                       0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                         0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT     0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT     0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT     0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT    0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT     0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK        0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK       0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK        0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK       0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK       0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK      0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK        0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK       0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK    0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK    0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK    0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK   0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK    0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK   0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                   0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT               0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                      0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                  0x00000F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                  0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                   0x01000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT               0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT               0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT               0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT               0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT               0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT               0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT               0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT               0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT               0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT               0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT              0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT              0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT              0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT              0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT              0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT              0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                   0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                   0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                   0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                   0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                   0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                   0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                   0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                   0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                   0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                  0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT              0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT                0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT              0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT                0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT                0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT              0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT              0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT                0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT              0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT                0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT              0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT                0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT              0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT              0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT                0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT              0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT                0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT              0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT                0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT              0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT                0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT              0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT                0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT              0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT                0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT              0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                  0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK                0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK                  0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK                0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK                  0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK                0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK                  0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK                0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK                  0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK                0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK                  0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK                0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK                  0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK                0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK                  0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK                0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK                  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK                0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK                  0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK                0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK                0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK                0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK                  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK                0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK                  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK                0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK                  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK                0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                    0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                  0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT                               0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT                    0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK                        0x0000007FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK                                 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK                      0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                  0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT                     0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT                    0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK                      0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK                       0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT                         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK                           0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK                           0x00000070L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK  0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_COMMAND
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF1_0_STATUS
+#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF1_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF1_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF1_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF1_0_LATENCY
+#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF1_0_HEADER
+#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF1_0_BIST
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF1_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF1_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF1_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                    0x0040L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK                                                           0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                               0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                        0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                          0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                          0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                0x0100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                            0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                    0x003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                 0x3F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                   0x003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                  0x0000003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                            0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                              0xFFE00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                  0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                           0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                    0x0020L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT   0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK     0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
+//BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
+//BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
+#define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
+//BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
+//BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                          0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                         0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                            0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                           0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                     0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                    0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                       0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                          0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                         0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT     0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT      0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT     0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT     0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT    0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT     0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK        0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK       0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK        0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK       0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK       0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK      0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK        0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK       0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK    0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK    0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK    0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK   0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK    0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK   0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                   0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT               0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                      0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                  0x00000F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                  0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                   0x01000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT               0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT               0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT               0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT               0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT               0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT               0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT               0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT               0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT               0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT               0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT              0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT              0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT              0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT              0x1b
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                0x1c
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT              0x1d
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                0x1e
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT              0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                   0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                   0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                   0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                   0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                   0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                   0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                   0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                   0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                   0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                   0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                  0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                  0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                  0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                  0x04000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                0x08000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                  0x10000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                0x20000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                  0x40000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT              0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT                0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT              0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT                0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT              0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT                0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT              0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT              0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT                0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT              0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT                0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT              0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT                0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT              0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT              0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT                0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT              0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT                0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT              0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT                0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT              0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT                0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT              0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT                0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT              0x1b
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT                0x1c
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT              0x1d
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                  0x1e
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK                  0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK                0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK                  0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK                0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK                  0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK                0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK                  0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK                0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK                  0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK                0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK                  0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK                0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK                  0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK                0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK                  0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK                0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK                  0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK                0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK                  0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK                0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK                  0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK                0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK                  0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK                0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK                  0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK                0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK                  0x04000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK                0x08000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK                  0x10000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK                0x20000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                    0x40000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                  0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT                               0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT                    0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK                        0x0000007FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK                                 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK                      0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                  0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT                     0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT                    0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK                      0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK                       0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK                      0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT                         0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK                           0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK                           0x00000070L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK  0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_COMMAND
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF2_0_STATUS
+#define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF2_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF2_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF2_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF2_0_LATENCY
+#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF2_0_HEADER
+#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF2_0_BIST
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF2_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF2_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_SBRN
+#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF2_0_FLADJ
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF2_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF2_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF2_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF2_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF2_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_COMMAND
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF3_0_STATUS
+#define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF3_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF3_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF3_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF3_0_LATENCY
+#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF3_0_HEADER
+#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF3_0_BIST
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF3_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF3_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_SBRN
+#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF3_0_FLADJ
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF3_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF3_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF3_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF3_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF3_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF4_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_COMMAND
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF4_0_STATUS
+#define BIF_CFG_DEV0_EPF4_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF4_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF4_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF4_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF4_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF4_0_LATENCY
+#define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF4_0_HEADER
+#define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF4_0_BIST
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF4_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF4_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF4_0_SBRN
+#define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF4_0_FLADJ
+#define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF4_0_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF4_0_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF4_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF4_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF4_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF4_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF4_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF4_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF5_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_COMMAND
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF5_0_STATUS
+#define BIF_CFG_DEV0_EPF5_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF5_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF5_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF5_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF5_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF5_0_LATENCY
+#define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF5_0_HEADER
+#define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF5_0_BIST
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF5_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF5_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF5_0_SBRN
+#define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF5_0_FLADJ
+#define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF5_0_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF5_0_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF5_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF5_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF5_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF5_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF5_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF5_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF6_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_COMMAND
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF6_0_STATUS
+#define BIF_CFG_DEV0_EPF6_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF6_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF6_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF6_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF6_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF6_0_LATENCY
+#define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF6_0_HEADER
+#define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF6_0_BIST
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF6_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF6_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF6_0_SBRN
+#define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF6_0_FLADJ
+#define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF6_0_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF6_0_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF6_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF6_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF6_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF6_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF6_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF6_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF7_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_COMMAND
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF7_0_STATUS
+#define BIF_CFG_DEV0_EPF7_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF7_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF7_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF7_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF7_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF7_0_LATENCY
+#define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF7_0_HEADER
+#define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF7_0_BIST
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF7_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF7_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF7_0_SBRN
+#define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF7_0_FLADJ
+#define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF7_0_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF7_0_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF7_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF7_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF7_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF7_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF7_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF7_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp
+//BIF_CFG_DEV1_EPF0_0_VENDOR_ID
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_DEVICE_ID
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_COMMAND
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV1_EPF0_0_STATUS
+#define BIF_CFG_DEV1_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV1_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV1_EPF0_0_REVISION_ID
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV1_EPF0_0_SUB_CLASS
+#define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_CLASS
+#define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV1_EPF0_0_CACHE_LINE
+#define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV1_EPF0_0_LATENCY
+#define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV1_EPF0_0_HEADER
+#define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV1_EPF0_0_BIST
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV1_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_CAP_PTR
+#define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV1_EPF0_0_MIN_GRANT
+#define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV1_EPF0_0_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PMI_CAP
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_SBRN
+#define BIF_CFG_DEV1_EPF0_0_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV1_EPF0_0_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV1_EPF0_0_FLADJ
+#define BIF_CFG_DEV1_EPF0_0_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV1_EPF0_0_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV1_EPF0_0_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV1_EPF0_0_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV1_EPF0_0_LINK_CAP
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_LINK_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV1_EPF0_0_LINK_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_LINK_CAP2
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV1_EPF0_0_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV1_EPF0_0_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MASK
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_PENDING
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV1_EPF0_0_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_0_MSIX_PBA
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
+//BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
+//BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
+#define BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
+//BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
+//BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp
+//BIF_CFG_DEV1_EPF1_0_VENDOR_ID
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_DEVICE_ID
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_COMMAND
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV1_EPF1_0_STATUS
+#define BIF_CFG_DEV1_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV1_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV1_EPF1_0_REVISION_ID
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV1_EPF1_0_SUB_CLASS
+#define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_CLASS
+#define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV1_EPF1_0_CACHE_LINE
+#define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV1_EPF1_0_LATENCY
+#define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV1_EPF1_0_HEADER
+#define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV1_EPF1_0_BIST
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV1_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_CAP_PTR
+#define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV1_EPF1_0_MIN_GRANT
+#define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV1_EPF1_0_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PMI_CAP
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV1_EPF1_0_SBRN
+#define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV1_EPF1_0_FLADJ
+#define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV1_EPF1_0_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV1_EPF1_0_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV1_EPF1_0_LINK_CAP
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV1_EPF1_0_LINK_CNTL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV1_EPF1_0_LINK_STATUS
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_LINK_CAP2
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV1_EPF1_0_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV1_EPF1_0_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MASK
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_PENDING
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV1_EPF1_0_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_0_MSIX_PBA
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp
+//BIF_CFG_DEV2_EPF0_0_VENDOR_ID
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_DEVICE_ID
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_COMMAND
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV2_EPF0_0_STATUS
+#define BIF_CFG_DEV2_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF0_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF0_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV2_EPF0_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV2_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV2_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV2_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV2_EPF0_0_REVISION_ID
+#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF0_0_SUB_CLASS
+#define BIF_CFG_DEV2_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_CLASS
+#define BIF_CFG_DEV2_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF0_0_CACHE_LINE
+#define BIF_CFG_DEV2_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV2_EPF0_0_LATENCY
+#define BIF_CFG_DEV2_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF0_0_HEADER
+#define BIF_CFG_DEV2_EPF0_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF0_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV2_EPF0_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV2_EPF0_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV2_EPF0_0_BIST
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_CAP_PTR
+#define BIF_CFG_DEV2_EPF0_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF0_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV2_EPF0_0_MIN_GRANT
+#define BIF_CFG_DEV2_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF0_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV2_EPF0_0_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PMI_CAP
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_SBRN
+#define BIF_CFG_DEV2_EPF0_0_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV2_EPF0_0_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV2_EPF0_0_FLADJ
+#define BIF_CFG_DEV2_EPF0_0_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV2_EPF0_0_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV2_EPF0_0_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV2_EPF0_0_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV2_EPF0_0_LINK_CAP
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_LINK_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV2_EPF0_0_LINK_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_LINK_CAP2
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV2_EPF0_0_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV2_EPF0_0_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_MASK
+#define BIF_CFG_DEV2_EPF0_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_PENDING
+#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV2_EPF0_0_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF0_0_MSIX_PBA
+#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
+//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
+//BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
+//BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
+#define BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
+//BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
+//BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf1_bifcfgdecp
+//BIF_CFG_DEV2_EPF1_0_VENDOR_ID
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_DEVICE_ID
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_COMMAND
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV2_EPF1_0_STATUS
+#define BIF_CFG_DEV2_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF1_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF1_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV2_EPF1_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV2_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV2_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV2_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV2_EPF1_0_REVISION_ID
+#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF1_0_SUB_CLASS
+#define BIF_CFG_DEV2_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_CLASS
+#define BIF_CFG_DEV2_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF1_0_CACHE_LINE
+#define BIF_CFG_DEV2_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV2_EPF1_0_LATENCY
+#define BIF_CFG_DEV2_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF1_0_HEADER
+#define BIF_CFG_DEV2_EPF1_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF1_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV2_EPF1_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV2_EPF1_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV2_EPF1_0_BIST
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_CAP_PTR
+#define BIF_CFG_DEV2_EPF1_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF1_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV2_EPF1_0_MIN_GRANT
+#define BIF_CFG_DEV2_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF1_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV2_EPF1_0_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PMI_CAP
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV2_EPF1_0_SBRN
+#define BIF_CFG_DEV2_EPF1_0_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV2_EPF1_0_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV2_EPF1_0_FLADJ
+#define BIF_CFG_DEV2_EPF1_0_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV2_EPF1_0_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV2_EPF1_0_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV2_EPF1_0_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV2_EPF1_0_LINK_CAP
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV2_EPF1_0_LINK_CNTL
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV2_EPF1_0_LINK_STATUS
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_LINK_CAP2
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV2_EPF1_0_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV2_EPF1_0_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_MASK
+#define BIF_CFG_DEV2_EPF1_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_PENDING
+#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV2_EPF1_0_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF1_0_MSIX_PBA
+#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf2_bifcfgdecp
+//BIF_CFG_DEV2_EPF2_0_VENDOR_ID
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_DEVICE_ID
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_COMMAND
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV2_EPF2_0_STATUS
+#define BIF_CFG_DEV2_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF2_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF2_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV2_EPF2_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV2_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV2_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV2_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV2_EPF2_0_REVISION_ID
+#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF2_0_SUB_CLASS
+#define BIF_CFG_DEV2_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_CLASS
+#define BIF_CFG_DEV2_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF2_0_CACHE_LINE
+#define BIF_CFG_DEV2_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV2_EPF2_0_LATENCY
+#define BIF_CFG_DEV2_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF2_0_HEADER
+#define BIF_CFG_DEV2_EPF2_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF2_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV2_EPF2_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV2_EPF2_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV2_EPF2_0_BIST
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_CAP_PTR
+#define BIF_CFG_DEV2_EPF2_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF2_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV2_EPF2_0_MIN_GRANT
+#define BIF_CFG_DEV2_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF2_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV2_EPF2_0_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PMI_CAP
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV2_EPF2_0_SBRN
+#define BIF_CFG_DEV2_EPF2_0_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV2_EPF2_0_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV2_EPF2_0_FLADJ
+#define BIF_CFG_DEV2_EPF2_0_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV2_EPF2_0_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV2_EPF2_0_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV2_EPF2_0_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV2_EPF2_0_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF2_0_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF2_0_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV2_EPF2_0_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV2_EPF2_0_LINK_CAP
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV2_EPF2_0_LINK_CNTL
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV2_EPF2_0_LINK_STATUS
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_LINK_CAP2
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV2_EPF2_0_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV2_EPF2_0_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_MASK
+#define BIF_CFG_DEV2_EPF2_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_PENDING
+#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV2_EPF2_0_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF2_0_MSIX_PBA
+#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+
+
+
+
+// addressBlock: nbio_nbif0_pciemsix_0_mp2_MSIXTDEC
+
+
+
+
+
+
+
+
+// addressBlock: nbio_nbif0_pciemsix_0_mp2_MSIXPDEC
+
+
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+//BIFPLR0_0_VENDOR_ID
+#define BIFPLR0_0_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR0_0_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR0_0_DEVICE_ID
+#define BIFPLR0_0_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR0_0_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR0_0_COMMAND
+#define BIFPLR0_0_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR0_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR0_0_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR0_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR0_0_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR0_0_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR0_0_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR0_0_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR0_0_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR0_0_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR0_0_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR0_0_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR0_0_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR0_0_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR0_0_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR0_0_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR0_0_STATUS
+#define BIFPLR0_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR0_0_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR0_0_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR0_0_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR0_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR0_0_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR0_0_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR0_0_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR0_0_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR0_0_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR0_0_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR0_0_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR0_0_REVISION_ID
+#define BIFPLR0_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR0_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR0_0_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR0_0_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR0_0_PROG_INTERFACE
+#define BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR0_0_SUB_CLASS
+#define BIFPLR0_0_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR0_0_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR0_0_BASE_CLASS
+#define BIFPLR0_0_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR0_0_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR0_0_CACHE_LINE
+#define BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR0_0_LATENCY
+#define BIFPLR0_0_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR0_0_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR0_0_HEADER
+#define BIFPLR0_0_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR0_0_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR0_0_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR0_0_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR0_0_BIST
+#define BIFPLR0_0_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR0_0_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR0_0_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR0_0_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR0_0_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR0_0_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR0_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR0_0_IO_BASE_LIMIT
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR0_0_SECONDARY_STATUS
+#define BIFPLR0_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR0_0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR0_0_MEM_BASE_LIMIT
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR0_0_PREF_BASE_LIMIT
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR0_0_PREF_BASE_UPPER
+#define BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_0_PREF_LIMIT_UPPER
+#define BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR0_0_IO_BASE_LIMIT_HI
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR0_0_CAP_PTR
+#define BIFPLR0_0_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR0_0_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR0_0_ROM_BASE_ADDR
+#define BIFPLR0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR0_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR0_0_INTERRUPT_LINE
+#define BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR0_0_INTERRUPT_PIN
+#define BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR0_0_IRQ_BRIDGE_CNTL
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR0_0_EXT_BRIDGE_CNTL
+#define BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR0_0_VENDOR_CAP_LIST
+#define BIFPLR0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR0_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR0_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR0_0_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR0_0_ADAPTER_ID_W
+#define BIFPLR0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR0_0_PMI_CAP_LIST
+#define BIFPLR0_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR0_0_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR0_0_PMI_CAP
+#define BIFPLR0_0_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR0_0_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR0_0_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR0_0_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR0_0_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR0_0_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR0_0_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR0_0_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR0_0_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR0_0_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR0_0_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR0_0_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR0_0_PMI_STATUS_CNTL
+#define BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR0_0_PCIE_CAP_LIST
+#define BIFPLR0_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR0_0_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR0_0_PCIE_CAP
+#define BIFPLR0_0_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR0_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR0_0_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR0_0_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR0_0_DEVICE_CAP
+#define BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR0_0_DEVICE_CNTL
+#define BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR0_0_DEVICE_STATUS
+#define BIFPLR0_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR0_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR0_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR0_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR0_0_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR0_0_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR0_0_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR0_0_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR0_0_LINK_CAP
+#define BIFPLR0_0_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR0_0_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR0_0_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR0_0_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR0_0_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR0_0_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR0_0_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR0_0_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR0_0_LINK_CNTL
+#define BIFPLR0_0_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR0_0_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR0_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR0_0_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR0_0_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR0_0_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR0_0_LINK_STATUS
+#define BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR0_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR0_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR0_0_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR0_0_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR0_0_SLOT_CAP
+#define BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR0_0_SLOT_CNTL
+#define BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR0_0_SLOT_STATUS
+#define BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR0_0_ROOT_CNTL
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR0_0_ROOT_CAP
+#define BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR0_0_ROOT_STATUS
+#define BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR0_0_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR0_0_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR0_0_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR0_0_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR0_0_DEVICE_CAP2
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR0_0_DEVICE_CNTL2
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR0_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR0_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR0_0_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR0_0_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR0_0_DEVICE_STATUS2
+#define BIFPLR0_0_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR0_0_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR0_0_LINK_CAP2
+#define BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR0_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR0_0_LINK_CNTL2
+#define BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR0_0_LINK_STATUS2
+#define BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR0_0_SLOT_CAP2
+#define BIFPLR0_0_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR0_0_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR0_0_SLOT_CNTL2
+#define BIFPLR0_0_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR0_0_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR0_0_SLOT_STATUS2
+#define BIFPLR0_0_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR0_0_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR0_0_MSI_CAP_LIST
+#define BIFPLR0_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR0_0_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR0_0_MSI_MSG_CNTL
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR0_0_MSI_MSG_ADDR_LO
+#define BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR0_0_MSI_MSG_ADDR_HI
+#define BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_0_MSI_MSG_DATA
+#define BIFPLR0_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR0_0_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR0_0_MSI_MSG_DATA_64
+#define BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR0_0_SSID_CAP_LIST
+#define BIFPLR0_0_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR0_0_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR0_0_SSID_CAP
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR0_0_MSI_MAP_CAP_LIST
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR0_0_MSI_MAP_CAP
+#define BIFPLR0_0_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR0_0_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR0_0_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR0_0_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR0_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR0_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR0_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR0_0_PCIE_PORT_VC_CNTL
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR0_0_PCIE_PORT_VC_STATUS
+#define BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR0_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR0_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR0_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR0_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR0_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR0_0_PCIE_CORR_ERR_MASK
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR0_0_PCIE_HDR_LOG0
+#define BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_HDR_LOG1
+#define BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_HDR_LOG2
+#define BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_HDR_LOG3
+#define BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR0_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR0_0_PCIE_ERR_SRC_ID
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR0_0_PCIE_LINK_CNTL3
+#define BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR0_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR0_0_PCIE_ACS_CAP
+#define BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR0_0_PCIE_ACS_CNTL
+#define BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR0_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR0_0_PCIE_MC_CAP
+#define BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR0_0_PCIE_MC_CNTL
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR0_0_PCIE_MC_ADDR0
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR0_0_PCIE_MC_ADDR1
+#define BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_RCV0
+#define BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_RCV1
+#define BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR0_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR0_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR0_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR0_0_PCIE_DPC_CAP_LIST
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR0_0_PCIE_DPC_CNTL
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR0_0_PCIE_DPC_STATUS
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_STATUS
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_MASK
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR0_0_PCIE_ESM_CAP_LIST
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR0_0_PCIE_ESM_HEADER_1
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR0_0_PCIE_ESM_HEADER_2
+#define BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR0_0_PCIE_ESM_STATUS
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR0_0_PCIE_ESM_CTRL
+#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR0_0_PCIE_ESM_CAP_1
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_2
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_3
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR0_0_PCIE_ESM_CAP_4
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_5
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_6
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_7
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR0_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR0_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR0_0_LINK_CAP_16GT
+#define BIFPLR0_0_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR0_0_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR0_0_LINK_CNTL_16GT
+#define BIFPLR0_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR0_0_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR0_0_LINK_STATUS_16GT
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR0_0_MARGINING_PORT_CAP
+#define BIFPLR0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR0_0_MARGINING_PORT_STATUS
+#define BIFPLR0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR0_0_PCIE_CCIX_HEADER_1
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR0_0_PCIE_CCIX_HEADER_2
+#define BIFPLR0_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR0_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR0_0_PCIE_CCIX_CAP
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR0_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR0_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR0_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR0_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR0_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR0_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR0_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR0_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR0_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR0_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR0_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR0_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR0_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+//BIFPLR1_0_VENDOR_ID
+#define BIFPLR1_0_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR1_0_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR1_0_DEVICE_ID
+#define BIFPLR1_0_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR1_0_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR1_0_COMMAND
+#define BIFPLR1_0_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR1_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR1_0_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR1_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR1_0_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR1_0_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR1_0_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR1_0_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR1_0_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR1_0_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR1_0_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR1_0_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR1_0_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR1_0_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR1_0_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR1_0_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR1_0_STATUS
+#define BIFPLR1_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR1_0_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR1_0_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR1_0_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR1_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR1_0_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR1_0_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR1_0_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR1_0_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR1_0_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR1_0_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR1_0_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR1_0_REVISION_ID
+#define BIFPLR1_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR1_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR1_0_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR1_0_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR1_0_PROG_INTERFACE
+#define BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR1_0_SUB_CLASS
+#define BIFPLR1_0_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR1_0_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR1_0_BASE_CLASS
+#define BIFPLR1_0_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR1_0_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR1_0_CACHE_LINE
+#define BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR1_0_LATENCY
+#define BIFPLR1_0_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR1_0_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR1_0_HEADER
+#define BIFPLR1_0_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR1_0_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR1_0_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR1_0_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR1_0_BIST
+#define BIFPLR1_0_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR1_0_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR1_0_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR1_0_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR1_0_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR1_0_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR1_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR1_0_IO_BASE_LIMIT
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR1_0_SECONDARY_STATUS
+#define BIFPLR1_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR1_0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR1_0_MEM_BASE_LIMIT
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR1_0_PREF_BASE_LIMIT
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR1_0_PREF_BASE_UPPER
+#define BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_0_PREF_LIMIT_UPPER
+#define BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR1_0_IO_BASE_LIMIT_HI
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR1_0_CAP_PTR
+#define BIFPLR1_0_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR1_0_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR1_0_ROM_BASE_ADDR
+#define BIFPLR1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR1_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR1_0_INTERRUPT_LINE
+#define BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR1_0_INTERRUPT_PIN
+#define BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR1_0_IRQ_BRIDGE_CNTL
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR1_0_EXT_BRIDGE_CNTL
+#define BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR1_0_VENDOR_CAP_LIST
+#define BIFPLR1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR1_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR1_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR1_0_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR1_0_ADAPTER_ID_W
+#define BIFPLR1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR1_0_PMI_CAP_LIST
+#define BIFPLR1_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR1_0_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR1_0_PMI_CAP
+#define BIFPLR1_0_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR1_0_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR1_0_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR1_0_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR1_0_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR1_0_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR1_0_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR1_0_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR1_0_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR1_0_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR1_0_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR1_0_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR1_0_PMI_STATUS_CNTL
+#define BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR1_0_PCIE_CAP_LIST
+#define BIFPLR1_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR1_0_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR1_0_PCIE_CAP
+#define BIFPLR1_0_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR1_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR1_0_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR1_0_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR1_0_DEVICE_CAP
+#define BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR1_0_DEVICE_CNTL
+#define BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR1_0_DEVICE_STATUS
+#define BIFPLR1_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR1_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR1_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR1_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR1_0_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR1_0_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR1_0_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR1_0_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR1_0_LINK_CAP
+#define BIFPLR1_0_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR1_0_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR1_0_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR1_0_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR1_0_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR1_0_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR1_0_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR1_0_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR1_0_LINK_CNTL
+#define BIFPLR1_0_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR1_0_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR1_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR1_0_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR1_0_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR1_0_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR1_0_LINK_STATUS
+#define BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR1_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR1_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR1_0_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR1_0_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR1_0_SLOT_CAP
+#define BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR1_0_SLOT_CNTL
+#define BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR1_0_SLOT_STATUS
+#define BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR1_0_ROOT_CNTL
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR1_0_ROOT_CAP
+#define BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR1_0_ROOT_STATUS
+#define BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR1_0_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR1_0_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR1_0_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR1_0_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR1_0_DEVICE_CAP2
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR1_0_DEVICE_CNTL2
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR1_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR1_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR1_0_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR1_0_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR1_0_DEVICE_STATUS2
+#define BIFPLR1_0_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR1_0_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR1_0_LINK_CAP2
+#define BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR1_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR1_0_LINK_CNTL2
+#define BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR1_0_LINK_STATUS2
+#define BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR1_0_SLOT_CAP2
+#define BIFPLR1_0_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR1_0_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR1_0_SLOT_CNTL2
+#define BIFPLR1_0_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR1_0_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR1_0_SLOT_STATUS2
+#define BIFPLR1_0_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR1_0_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR1_0_MSI_CAP_LIST
+#define BIFPLR1_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR1_0_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR1_0_MSI_MSG_CNTL
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR1_0_MSI_MSG_ADDR_LO
+#define BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR1_0_MSI_MSG_ADDR_HI
+#define BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_0_MSI_MSG_DATA
+#define BIFPLR1_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR1_0_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR1_0_MSI_MSG_DATA_64
+#define BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR1_0_SSID_CAP_LIST
+#define BIFPLR1_0_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR1_0_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR1_0_SSID_CAP
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR1_0_MSI_MAP_CAP_LIST
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR1_0_MSI_MAP_CAP
+#define BIFPLR1_0_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR1_0_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR1_0_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR1_0_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR1_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR1_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR1_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR1_0_PCIE_PORT_VC_CNTL
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR1_0_PCIE_PORT_VC_STATUS
+#define BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR1_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR1_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR1_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR1_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR1_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR1_0_PCIE_CORR_ERR_MASK
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR1_0_PCIE_HDR_LOG0
+#define BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_HDR_LOG1
+#define BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_HDR_LOG2
+#define BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_HDR_LOG3
+#define BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR1_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR1_0_PCIE_ERR_SRC_ID
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR1_0_PCIE_LINK_CNTL3
+#define BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR1_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR1_0_PCIE_ACS_CAP
+#define BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR1_0_PCIE_ACS_CNTL
+#define BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR1_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR1_0_PCIE_MC_CAP
+#define BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR1_0_PCIE_MC_CNTL
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR1_0_PCIE_MC_ADDR0
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR1_0_PCIE_MC_ADDR1
+#define BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_RCV0
+#define BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_RCV1
+#define BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR1_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR1_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR1_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR1_0_PCIE_DPC_CAP_LIST
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR1_0_PCIE_DPC_CNTL
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR1_0_PCIE_DPC_STATUS
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_STATUS
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_MASK
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR1_0_PCIE_ESM_CAP_LIST
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR1_0_PCIE_ESM_HEADER_1
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR1_0_PCIE_ESM_HEADER_2
+#define BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR1_0_PCIE_ESM_STATUS
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR1_0_PCIE_ESM_CTRL
+#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR1_0_PCIE_ESM_CAP_1
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_2
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_3
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR1_0_PCIE_ESM_CAP_4
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_5
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_6
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_7
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR1_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR1_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR1_0_LINK_CAP_16GT
+#define BIFPLR1_0_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR1_0_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR1_0_LINK_CNTL_16GT
+#define BIFPLR1_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR1_0_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR1_0_LINK_STATUS_16GT
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR1_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR1_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR1_0_MARGINING_PORT_CAP
+#define BIFPLR1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR1_0_MARGINING_PORT_STATUS
+#define BIFPLR1_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR1_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR1_0_PCIE_CCIX_HEADER_1
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR1_0_PCIE_CCIX_HEADER_2
+#define BIFPLR1_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR1_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR1_0_PCIE_CCIX_CAP
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR1_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR1_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR1_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR1_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR1_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR1_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR1_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR1_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR1_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR1_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR1_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR1_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR1_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+//BIFPLR2_0_VENDOR_ID
+#define BIFPLR2_0_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR2_0_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR2_0_DEVICE_ID
+#define BIFPLR2_0_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR2_0_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR2_0_COMMAND
+#define BIFPLR2_0_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR2_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR2_0_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR2_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR2_0_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR2_0_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR2_0_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR2_0_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR2_0_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR2_0_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR2_0_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR2_0_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR2_0_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR2_0_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR2_0_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR2_0_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR2_0_STATUS
+#define BIFPLR2_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR2_0_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR2_0_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR2_0_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR2_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR2_0_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR2_0_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR2_0_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR2_0_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR2_0_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR2_0_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR2_0_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR2_0_REVISION_ID
+#define BIFPLR2_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR2_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR2_0_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR2_0_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR2_0_PROG_INTERFACE
+#define BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR2_0_SUB_CLASS
+#define BIFPLR2_0_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR2_0_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR2_0_BASE_CLASS
+#define BIFPLR2_0_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR2_0_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR2_0_CACHE_LINE
+#define BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR2_0_LATENCY
+#define BIFPLR2_0_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR2_0_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR2_0_HEADER
+#define BIFPLR2_0_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR2_0_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR2_0_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR2_0_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR2_0_BIST
+#define BIFPLR2_0_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR2_0_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR2_0_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR2_0_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR2_0_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR2_0_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR2_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR2_0_IO_BASE_LIMIT
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR2_0_SECONDARY_STATUS
+#define BIFPLR2_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR2_0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR2_0_MEM_BASE_LIMIT
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR2_0_PREF_BASE_LIMIT
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR2_0_PREF_BASE_UPPER
+#define BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_0_PREF_LIMIT_UPPER
+#define BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR2_0_IO_BASE_LIMIT_HI
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR2_0_CAP_PTR
+#define BIFPLR2_0_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR2_0_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR2_0_ROM_BASE_ADDR
+#define BIFPLR2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR2_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR2_0_INTERRUPT_LINE
+#define BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR2_0_INTERRUPT_PIN
+#define BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR2_0_IRQ_BRIDGE_CNTL
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR2_0_EXT_BRIDGE_CNTL
+#define BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR2_0_VENDOR_CAP_LIST
+#define BIFPLR2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR2_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR2_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR2_0_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR2_0_ADAPTER_ID_W
+#define BIFPLR2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR2_0_PMI_CAP_LIST
+#define BIFPLR2_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR2_0_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR2_0_PMI_CAP
+#define BIFPLR2_0_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR2_0_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR2_0_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR2_0_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR2_0_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR2_0_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR2_0_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR2_0_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR2_0_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR2_0_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR2_0_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR2_0_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR2_0_PMI_STATUS_CNTL
+#define BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR2_0_PCIE_CAP_LIST
+#define BIFPLR2_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR2_0_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR2_0_PCIE_CAP
+#define BIFPLR2_0_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR2_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR2_0_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR2_0_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR2_0_DEVICE_CAP
+#define BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR2_0_DEVICE_CNTL
+#define BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR2_0_DEVICE_STATUS
+#define BIFPLR2_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR2_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR2_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR2_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR2_0_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR2_0_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR2_0_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR2_0_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR2_0_LINK_CAP
+#define BIFPLR2_0_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR2_0_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR2_0_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR2_0_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR2_0_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR2_0_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR2_0_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR2_0_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR2_0_LINK_CNTL
+#define BIFPLR2_0_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR2_0_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR2_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR2_0_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR2_0_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR2_0_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR2_0_LINK_STATUS
+#define BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR2_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR2_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR2_0_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR2_0_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR2_0_SLOT_CAP
+#define BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR2_0_SLOT_CNTL
+#define BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR2_0_SLOT_STATUS
+#define BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR2_0_ROOT_CNTL
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR2_0_ROOT_CAP
+#define BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR2_0_ROOT_STATUS
+#define BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR2_0_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR2_0_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR2_0_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR2_0_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR2_0_DEVICE_CAP2
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR2_0_DEVICE_CNTL2
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR2_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR2_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR2_0_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR2_0_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR2_0_DEVICE_STATUS2
+#define BIFPLR2_0_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR2_0_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR2_0_LINK_CAP2
+#define BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR2_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR2_0_LINK_CNTL2
+#define BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR2_0_LINK_STATUS2
+#define BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR2_0_SLOT_CAP2
+#define BIFPLR2_0_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR2_0_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR2_0_SLOT_CNTL2
+#define BIFPLR2_0_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR2_0_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR2_0_SLOT_STATUS2
+#define BIFPLR2_0_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR2_0_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR2_0_MSI_CAP_LIST
+#define BIFPLR2_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR2_0_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR2_0_MSI_MSG_CNTL
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR2_0_MSI_MSG_ADDR_LO
+#define BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR2_0_MSI_MSG_ADDR_HI
+#define BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_0_MSI_MSG_DATA
+#define BIFPLR2_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR2_0_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR2_0_MSI_MSG_DATA_64
+#define BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR2_0_SSID_CAP_LIST
+#define BIFPLR2_0_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR2_0_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR2_0_SSID_CAP
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR2_0_MSI_MAP_CAP_LIST
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR2_0_MSI_MAP_CAP
+#define BIFPLR2_0_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR2_0_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR2_0_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR2_0_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR2_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR2_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR2_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR2_0_PCIE_PORT_VC_CNTL
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR2_0_PCIE_PORT_VC_STATUS
+#define BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR2_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR2_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR2_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR2_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR2_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR2_0_PCIE_CORR_ERR_MASK
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR2_0_PCIE_HDR_LOG0
+#define BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_HDR_LOG1
+#define BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_HDR_LOG2
+#define BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_HDR_LOG3
+#define BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR2_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR2_0_PCIE_ERR_SRC_ID
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR2_0_PCIE_LINK_CNTL3
+#define BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR2_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR2_0_PCIE_ACS_CAP
+#define BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR2_0_PCIE_ACS_CNTL
+#define BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR2_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR2_0_PCIE_MC_CAP
+#define BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR2_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR2_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR2_0_PCIE_MC_CNTL
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR2_0_PCIE_MC_ADDR0
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR2_0_PCIE_MC_ADDR1
+#define BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_RCV0
+#define BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_RCV1
+#define BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR2_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR2_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR2_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR2_0_PCIE_DPC_CAP_LIST
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR2_0_PCIE_DPC_CNTL
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR2_0_PCIE_DPC_STATUS
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_STATUS
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_MASK
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR2_0_PCIE_ESM_CAP_LIST
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR2_0_PCIE_ESM_HEADER_1
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR2_0_PCIE_ESM_HEADER_2
+#define BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR2_0_PCIE_ESM_STATUS
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR2_0_PCIE_ESM_CTRL
+#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR2_0_PCIE_ESM_CAP_1
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_2
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_3
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR2_0_PCIE_ESM_CAP_4
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_5
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_6
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_7
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR2_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR2_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR2_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR2_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR2_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR2_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR2_0_LINK_CAP_16GT
+#define BIFPLR2_0_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR2_0_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR2_0_LINK_CNTL_16GT
+#define BIFPLR2_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR2_0_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR2_0_LINK_STATUS_16GT
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR2_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR2_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR2_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR2_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR2_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR2_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR2_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR2_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR2_0_MARGINING_PORT_CAP
+#define BIFPLR2_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR2_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR2_0_MARGINING_PORT_STATUS
+#define BIFPLR2_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR2_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR2_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR2_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR2_0_PCIE_CCIX_HEADER_1
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR2_0_PCIE_CCIX_HEADER_2
+#define BIFPLR2_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR2_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR2_0_PCIE_CCIX_CAP
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR2_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR2_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR2_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR2_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR2_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR2_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR2_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR2_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR2_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR2_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR2_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR2_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR2_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+//BIFPLR3_0_VENDOR_ID
+#define BIFPLR3_0_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR3_0_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR3_0_DEVICE_ID
+#define BIFPLR3_0_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR3_0_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR3_0_COMMAND
+#define BIFPLR3_0_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR3_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR3_0_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR3_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR3_0_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR3_0_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR3_0_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR3_0_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR3_0_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR3_0_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR3_0_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR3_0_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR3_0_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR3_0_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR3_0_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR3_0_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR3_0_STATUS
+#define BIFPLR3_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR3_0_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR3_0_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR3_0_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR3_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR3_0_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR3_0_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR3_0_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR3_0_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR3_0_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR3_0_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR3_0_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR3_0_REVISION_ID
+#define BIFPLR3_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR3_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR3_0_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR3_0_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR3_0_PROG_INTERFACE
+#define BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR3_0_SUB_CLASS
+#define BIFPLR3_0_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR3_0_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR3_0_BASE_CLASS
+#define BIFPLR3_0_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR3_0_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR3_0_CACHE_LINE
+#define BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR3_0_LATENCY
+#define BIFPLR3_0_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR3_0_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR3_0_HEADER
+#define BIFPLR3_0_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR3_0_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR3_0_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR3_0_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR3_0_BIST
+#define BIFPLR3_0_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR3_0_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR3_0_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR3_0_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR3_0_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR3_0_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR3_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR3_0_IO_BASE_LIMIT
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR3_0_SECONDARY_STATUS
+#define BIFPLR3_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR3_0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR3_0_MEM_BASE_LIMIT
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR3_0_PREF_BASE_LIMIT
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR3_0_PREF_BASE_UPPER
+#define BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_0_PREF_LIMIT_UPPER
+#define BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR3_0_IO_BASE_LIMIT_HI
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR3_0_CAP_PTR
+#define BIFPLR3_0_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR3_0_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR3_0_ROM_BASE_ADDR
+#define BIFPLR3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR3_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR3_0_INTERRUPT_LINE
+#define BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR3_0_INTERRUPT_PIN
+#define BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR3_0_IRQ_BRIDGE_CNTL
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR3_0_EXT_BRIDGE_CNTL
+#define BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR3_0_VENDOR_CAP_LIST
+#define BIFPLR3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR3_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR3_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR3_0_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR3_0_ADAPTER_ID_W
+#define BIFPLR3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR3_0_PMI_CAP_LIST
+#define BIFPLR3_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR3_0_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR3_0_PMI_CAP
+#define BIFPLR3_0_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR3_0_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR3_0_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR3_0_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR3_0_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR3_0_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR3_0_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR3_0_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR3_0_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR3_0_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR3_0_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR3_0_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR3_0_PMI_STATUS_CNTL
+#define BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR3_0_PCIE_CAP_LIST
+#define BIFPLR3_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR3_0_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR3_0_PCIE_CAP
+#define BIFPLR3_0_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR3_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR3_0_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR3_0_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR3_0_DEVICE_CAP
+#define BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR3_0_DEVICE_CNTL
+#define BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR3_0_DEVICE_STATUS
+#define BIFPLR3_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR3_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR3_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR3_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR3_0_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR3_0_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR3_0_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR3_0_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR3_0_LINK_CAP
+#define BIFPLR3_0_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR3_0_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR3_0_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR3_0_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR3_0_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR3_0_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR3_0_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR3_0_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR3_0_LINK_CNTL
+#define BIFPLR3_0_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR3_0_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR3_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR3_0_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR3_0_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR3_0_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR3_0_LINK_STATUS
+#define BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR3_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR3_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR3_0_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR3_0_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR3_0_SLOT_CAP
+#define BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR3_0_SLOT_CNTL
+#define BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR3_0_SLOT_STATUS
+#define BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR3_0_ROOT_CNTL
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR3_0_ROOT_CAP
+#define BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR3_0_ROOT_STATUS
+#define BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR3_0_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR3_0_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR3_0_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR3_0_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR3_0_DEVICE_CAP2
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR3_0_DEVICE_CNTL2
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR3_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR3_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR3_0_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR3_0_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR3_0_DEVICE_STATUS2
+#define BIFPLR3_0_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR3_0_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR3_0_LINK_CAP2
+#define BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR3_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR3_0_LINK_CNTL2
+#define BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR3_0_LINK_STATUS2
+#define BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR3_0_SLOT_CAP2
+#define BIFPLR3_0_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR3_0_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR3_0_SLOT_CNTL2
+#define BIFPLR3_0_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR3_0_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR3_0_SLOT_STATUS2
+#define BIFPLR3_0_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR3_0_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR3_0_MSI_CAP_LIST
+#define BIFPLR3_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR3_0_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR3_0_MSI_MSG_CNTL
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR3_0_MSI_MSG_ADDR_LO
+#define BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR3_0_MSI_MSG_ADDR_HI
+#define BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_0_MSI_MSG_DATA
+#define BIFPLR3_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR3_0_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR3_0_MSI_MSG_DATA_64
+#define BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR3_0_SSID_CAP_LIST
+#define BIFPLR3_0_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR3_0_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR3_0_SSID_CAP
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR3_0_MSI_MAP_CAP_LIST
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR3_0_MSI_MAP_CAP
+#define BIFPLR3_0_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR3_0_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR3_0_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR3_0_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR3_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR3_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR3_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR3_0_PCIE_PORT_VC_CNTL
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR3_0_PCIE_PORT_VC_STATUS
+#define BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR3_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR3_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR3_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR3_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR3_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR3_0_PCIE_CORR_ERR_MASK
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR3_0_PCIE_HDR_LOG0
+#define BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_HDR_LOG1
+#define BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_HDR_LOG2
+#define BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_HDR_LOG3
+#define BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR3_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR3_0_PCIE_ERR_SRC_ID
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR3_0_PCIE_LINK_CNTL3
+#define BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR3_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR3_0_PCIE_ACS_CAP
+#define BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR3_0_PCIE_ACS_CNTL
+#define BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR3_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR3_0_PCIE_MC_CAP
+#define BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR3_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR3_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR3_0_PCIE_MC_CNTL
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR3_0_PCIE_MC_ADDR0
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR3_0_PCIE_MC_ADDR1
+#define BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_RCV0
+#define BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_RCV1
+#define BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR3_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR3_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR3_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR3_0_PCIE_DPC_CAP_LIST
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR3_0_PCIE_DPC_CNTL
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR3_0_PCIE_DPC_STATUS
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_STATUS
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_MASK
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR3_0_PCIE_ESM_CAP_LIST
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR3_0_PCIE_ESM_HEADER_1
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR3_0_PCIE_ESM_HEADER_2
+#define BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR3_0_PCIE_ESM_STATUS
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR3_0_PCIE_ESM_CTRL
+#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR3_0_PCIE_ESM_CAP_1
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_2
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_3
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR3_0_PCIE_ESM_CAP_4
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_5
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_6
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_7
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR3_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR3_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR3_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR3_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR3_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR3_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR3_0_LINK_CAP_16GT
+#define BIFPLR3_0_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR3_0_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR3_0_LINK_CNTL_16GT
+#define BIFPLR3_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR3_0_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR3_0_LINK_STATUS_16GT
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR3_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR3_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR3_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR3_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR3_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR3_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR3_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR3_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR3_0_MARGINING_PORT_CAP
+#define BIFPLR3_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR3_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR3_0_MARGINING_PORT_STATUS
+#define BIFPLR3_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR3_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR3_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR3_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR3_0_PCIE_CCIX_HEADER_1
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR3_0_PCIE_CCIX_HEADER_2
+#define BIFPLR3_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR3_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR3_0_PCIE_CCIX_CAP
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR3_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR3_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR3_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR3_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR3_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR3_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR3_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR3_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR3_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR3_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR3_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR3_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR3_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+//BIFPLR4_0_VENDOR_ID
+#define BIFPLR4_0_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR4_0_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR4_0_DEVICE_ID
+#define BIFPLR4_0_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR4_0_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR4_0_COMMAND
+#define BIFPLR4_0_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR4_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR4_0_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR4_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR4_0_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR4_0_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR4_0_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR4_0_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR4_0_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR4_0_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR4_0_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR4_0_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR4_0_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR4_0_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR4_0_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR4_0_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR4_0_STATUS
+#define BIFPLR4_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR4_0_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR4_0_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR4_0_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR4_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR4_0_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR4_0_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR4_0_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR4_0_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR4_0_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR4_0_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR4_0_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR4_0_REVISION_ID
+#define BIFPLR4_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR4_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR4_0_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR4_0_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR4_0_PROG_INTERFACE
+#define BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR4_0_SUB_CLASS
+#define BIFPLR4_0_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR4_0_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR4_0_BASE_CLASS
+#define BIFPLR4_0_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR4_0_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR4_0_CACHE_LINE
+#define BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR4_0_LATENCY
+#define BIFPLR4_0_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR4_0_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR4_0_HEADER
+#define BIFPLR4_0_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR4_0_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR4_0_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR4_0_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR4_0_BIST
+#define BIFPLR4_0_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR4_0_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR4_0_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR4_0_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR4_0_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR4_0_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR4_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR4_0_IO_BASE_LIMIT
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR4_0_SECONDARY_STATUS
+#define BIFPLR4_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR4_0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR4_0_MEM_BASE_LIMIT
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR4_0_PREF_BASE_LIMIT
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR4_0_PREF_BASE_UPPER
+#define BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_0_PREF_LIMIT_UPPER
+#define BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR4_0_IO_BASE_LIMIT_HI
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR4_0_CAP_PTR
+#define BIFPLR4_0_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR4_0_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR4_0_ROM_BASE_ADDR
+#define BIFPLR4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR4_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR4_0_INTERRUPT_LINE
+#define BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR4_0_INTERRUPT_PIN
+#define BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR4_0_IRQ_BRIDGE_CNTL
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR4_0_EXT_BRIDGE_CNTL
+#define BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR4_0_VENDOR_CAP_LIST
+#define BIFPLR4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR4_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR4_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR4_0_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR4_0_ADAPTER_ID_W
+#define BIFPLR4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR4_0_PMI_CAP_LIST
+#define BIFPLR4_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR4_0_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR4_0_PMI_CAP
+#define BIFPLR4_0_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR4_0_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR4_0_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR4_0_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR4_0_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR4_0_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR4_0_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR4_0_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR4_0_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR4_0_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR4_0_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR4_0_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR4_0_PMI_STATUS_CNTL
+#define BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR4_0_PCIE_CAP_LIST
+#define BIFPLR4_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR4_0_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR4_0_PCIE_CAP
+#define BIFPLR4_0_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR4_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR4_0_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR4_0_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR4_0_DEVICE_CAP
+#define BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR4_0_DEVICE_CNTL
+#define BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR4_0_DEVICE_STATUS
+#define BIFPLR4_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR4_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR4_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR4_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR4_0_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR4_0_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR4_0_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR4_0_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR4_0_LINK_CAP
+#define BIFPLR4_0_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR4_0_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR4_0_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR4_0_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR4_0_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR4_0_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR4_0_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR4_0_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR4_0_LINK_CNTL
+#define BIFPLR4_0_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR4_0_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR4_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR4_0_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR4_0_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR4_0_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR4_0_LINK_STATUS
+#define BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR4_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR4_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR4_0_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR4_0_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR4_0_SLOT_CAP
+#define BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR4_0_SLOT_CNTL
+#define BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR4_0_SLOT_STATUS
+#define BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR4_0_ROOT_CNTL
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR4_0_ROOT_CAP
+#define BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR4_0_ROOT_STATUS
+#define BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR4_0_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR4_0_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR4_0_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR4_0_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR4_0_DEVICE_CAP2
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR4_0_DEVICE_CNTL2
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR4_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR4_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR4_0_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR4_0_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR4_0_DEVICE_STATUS2
+#define BIFPLR4_0_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR4_0_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR4_0_LINK_CAP2
+#define BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR4_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR4_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR4_0_LINK_CNTL2
+#define BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR4_0_LINK_STATUS2
+#define BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR4_0_SLOT_CAP2
+#define BIFPLR4_0_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR4_0_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR4_0_SLOT_CNTL2
+#define BIFPLR4_0_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR4_0_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR4_0_SLOT_STATUS2
+#define BIFPLR4_0_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR4_0_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR4_0_MSI_CAP_LIST
+#define BIFPLR4_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR4_0_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR4_0_MSI_MSG_CNTL
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR4_0_MSI_MSG_ADDR_LO
+#define BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR4_0_MSI_MSG_ADDR_HI
+#define BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_0_MSI_MSG_DATA
+#define BIFPLR4_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR4_0_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR4_0_MSI_MSG_DATA_64
+#define BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR4_0_SSID_CAP_LIST
+#define BIFPLR4_0_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR4_0_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR4_0_SSID_CAP
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR4_0_MSI_MAP_CAP_LIST
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR4_0_MSI_MAP_CAP
+#define BIFPLR4_0_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR4_0_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR4_0_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR4_0_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR4_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR4_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR4_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR4_0_PCIE_PORT_VC_CNTL
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR4_0_PCIE_PORT_VC_STATUS
+#define BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR4_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR4_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR4_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR4_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR4_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR4_0_PCIE_CORR_ERR_MASK
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR4_0_PCIE_HDR_LOG0
+#define BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_HDR_LOG1
+#define BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_HDR_LOG2
+#define BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_HDR_LOG3
+#define BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR4_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR4_0_PCIE_ERR_SRC_ID
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR4_0_PCIE_LINK_CNTL3
+#define BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR4_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR4_0_PCIE_ACS_CAP
+#define BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR4_0_PCIE_ACS_CNTL
+#define BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR4_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR4_0_PCIE_MC_CAP
+#define BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR4_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR4_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR4_0_PCIE_MC_CNTL
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR4_0_PCIE_MC_ADDR0
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR4_0_PCIE_MC_ADDR1
+#define BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_RCV0
+#define BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_RCV1
+#define BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR4_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR4_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR4_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR4_0_PCIE_DPC_CAP_LIST
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR4_0_PCIE_DPC_CNTL
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR4_0_PCIE_DPC_STATUS
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_STATUS
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_MASK
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR4_0_PCIE_ESM_CAP_LIST
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR4_0_PCIE_ESM_HEADER_1
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR4_0_PCIE_ESM_HEADER_2
+#define BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR4_0_PCIE_ESM_STATUS
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR4_0_PCIE_ESM_CTRL
+#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR4_0_PCIE_ESM_CAP_1
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_2
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_3
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR4_0_PCIE_ESM_CAP_4
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_5
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_6
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_7
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR4_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR4_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR4_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR4_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR4_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR4_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR4_0_LINK_CAP_16GT
+#define BIFPLR4_0_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR4_0_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR4_0_LINK_CNTL_16GT
+#define BIFPLR4_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR4_0_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR4_0_LINK_STATUS_16GT
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR4_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR4_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR4_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR4_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR4_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR4_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR4_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR4_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR4_0_MARGINING_PORT_CAP
+#define BIFPLR4_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR4_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR4_0_MARGINING_PORT_STATUS
+#define BIFPLR4_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR4_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR4_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR4_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR4_0_PCIE_CCIX_HEADER_1
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR4_0_PCIE_CCIX_HEADER_2
+#define BIFPLR4_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR4_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR4_0_PCIE_CCIX_CAP
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR4_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR4_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR4_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR4_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR4_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR4_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR4_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR4_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR4_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR4_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR4_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR4_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR4_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+//BIFPLR5_0_VENDOR_ID
+#define BIFPLR5_0_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR5_0_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR5_0_DEVICE_ID
+#define BIFPLR5_0_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR5_0_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR5_0_COMMAND
+#define BIFPLR5_0_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR5_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR5_0_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR5_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR5_0_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR5_0_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR5_0_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR5_0_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR5_0_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR5_0_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR5_0_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR5_0_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR5_0_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR5_0_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR5_0_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR5_0_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR5_0_STATUS
+#define BIFPLR5_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR5_0_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR5_0_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR5_0_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR5_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR5_0_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR5_0_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR5_0_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR5_0_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR5_0_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR5_0_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR5_0_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR5_0_REVISION_ID
+#define BIFPLR5_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR5_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR5_0_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR5_0_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR5_0_PROG_INTERFACE
+#define BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR5_0_SUB_CLASS
+#define BIFPLR5_0_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR5_0_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR5_0_BASE_CLASS
+#define BIFPLR5_0_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR5_0_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR5_0_CACHE_LINE
+#define BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR5_0_LATENCY
+#define BIFPLR5_0_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR5_0_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR5_0_HEADER
+#define BIFPLR5_0_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR5_0_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR5_0_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR5_0_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR5_0_BIST
+#define BIFPLR5_0_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR5_0_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR5_0_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR5_0_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR5_0_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR5_0_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR5_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR5_0_IO_BASE_LIMIT
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR5_0_SECONDARY_STATUS
+#define BIFPLR5_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR5_0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR5_0_MEM_BASE_LIMIT
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR5_0_PREF_BASE_LIMIT
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR5_0_PREF_BASE_UPPER
+#define BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_0_PREF_LIMIT_UPPER
+#define BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR5_0_IO_BASE_LIMIT_HI
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR5_0_CAP_PTR
+#define BIFPLR5_0_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR5_0_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR5_0_ROM_BASE_ADDR
+#define BIFPLR5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR5_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR5_0_INTERRUPT_LINE
+#define BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR5_0_INTERRUPT_PIN
+#define BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR5_0_IRQ_BRIDGE_CNTL
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR5_0_EXT_BRIDGE_CNTL
+#define BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR5_0_VENDOR_CAP_LIST
+#define BIFPLR5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR5_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR5_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR5_0_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR5_0_ADAPTER_ID_W
+#define BIFPLR5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR5_0_PMI_CAP_LIST
+#define BIFPLR5_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR5_0_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR5_0_PMI_CAP
+#define BIFPLR5_0_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR5_0_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR5_0_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR5_0_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR5_0_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR5_0_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR5_0_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR5_0_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR5_0_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR5_0_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR5_0_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR5_0_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR5_0_PMI_STATUS_CNTL
+#define BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR5_0_PCIE_CAP_LIST
+#define BIFPLR5_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR5_0_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR5_0_PCIE_CAP
+#define BIFPLR5_0_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR5_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR5_0_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR5_0_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR5_0_DEVICE_CAP
+#define BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR5_0_DEVICE_CNTL
+#define BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR5_0_DEVICE_STATUS
+#define BIFPLR5_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR5_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR5_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR5_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR5_0_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR5_0_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR5_0_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR5_0_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR5_0_LINK_CAP
+#define BIFPLR5_0_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR5_0_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR5_0_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR5_0_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR5_0_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR5_0_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR5_0_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR5_0_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR5_0_LINK_CNTL
+#define BIFPLR5_0_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR5_0_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR5_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR5_0_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR5_0_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR5_0_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR5_0_LINK_STATUS
+#define BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR5_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR5_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR5_0_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR5_0_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR5_0_SLOT_CAP
+#define BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR5_0_SLOT_CNTL
+#define BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR5_0_SLOT_STATUS
+#define BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR5_0_ROOT_CNTL
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR5_0_ROOT_CAP
+#define BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR5_0_ROOT_STATUS
+#define BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR5_0_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR5_0_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR5_0_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR5_0_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR5_0_DEVICE_CAP2
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR5_0_DEVICE_CNTL2
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR5_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR5_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR5_0_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR5_0_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR5_0_DEVICE_STATUS2
+#define BIFPLR5_0_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR5_0_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR5_0_LINK_CAP2
+#define BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR5_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR5_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR5_0_LINK_CNTL2
+#define BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR5_0_LINK_STATUS2
+#define BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR5_0_SLOT_CAP2
+#define BIFPLR5_0_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR5_0_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR5_0_SLOT_CNTL2
+#define BIFPLR5_0_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR5_0_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR5_0_SLOT_STATUS2
+#define BIFPLR5_0_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR5_0_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR5_0_MSI_CAP_LIST
+#define BIFPLR5_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR5_0_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR5_0_MSI_MSG_CNTL
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR5_0_MSI_MSG_ADDR_LO
+#define BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR5_0_MSI_MSG_ADDR_HI
+#define BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_0_MSI_MSG_DATA
+#define BIFPLR5_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR5_0_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR5_0_MSI_MSG_DATA_64
+#define BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR5_0_SSID_CAP_LIST
+#define BIFPLR5_0_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR5_0_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR5_0_SSID_CAP
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR5_0_MSI_MAP_CAP_LIST
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR5_0_MSI_MAP_CAP
+#define BIFPLR5_0_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR5_0_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR5_0_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR5_0_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR5_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR5_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR5_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR5_0_PCIE_PORT_VC_CNTL
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR5_0_PCIE_PORT_VC_STATUS
+#define BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR5_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR5_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR5_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR5_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR5_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR5_0_PCIE_CORR_ERR_MASK
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR5_0_PCIE_HDR_LOG0
+#define BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_HDR_LOG1
+#define BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_HDR_LOG2
+#define BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_HDR_LOG3
+#define BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR5_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR5_0_PCIE_ERR_SRC_ID
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR5_0_PCIE_LINK_CNTL3
+#define BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR5_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR5_0_PCIE_ACS_CAP
+#define BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR5_0_PCIE_ACS_CNTL
+#define BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR5_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR5_0_PCIE_MC_CAP
+#define BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR5_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR5_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR5_0_PCIE_MC_CNTL
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR5_0_PCIE_MC_ADDR0
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR5_0_PCIE_MC_ADDR1
+#define BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_RCV0
+#define BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_RCV1
+#define BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR5_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR5_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR5_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR5_0_PCIE_DPC_CAP_LIST
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR5_0_PCIE_DPC_CNTL
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR5_0_PCIE_DPC_STATUS
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_STATUS
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_MASK
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR5_0_PCIE_ESM_CAP_LIST
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR5_0_PCIE_ESM_HEADER_1
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR5_0_PCIE_ESM_HEADER_2
+#define BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR5_0_PCIE_ESM_STATUS
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR5_0_PCIE_ESM_CTRL
+#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR5_0_PCIE_ESM_CAP_1
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_2
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_3
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR5_0_PCIE_ESM_CAP_4
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_5
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_6
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_7
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR5_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR5_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR5_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR5_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR5_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR5_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR5_0_LINK_CAP_16GT
+#define BIFPLR5_0_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR5_0_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR5_0_LINK_CNTL_16GT
+#define BIFPLR5_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR5_0_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR5_0_LINK_STATUS_16GT
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR5_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR5_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR5_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR5_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR5_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR5_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR5_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR5_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR5_0_MARGINING_PORT_CAP
+#define BIFPLR5_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR5_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR5_0_MARGINING_PORT_STATUS
+#define BIFPLR5_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR5_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR5_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR5_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR5_0_PCIE_CCIX_HEADER_1
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR5_0_PCIE_CCIX_HEADER_2
+#define BIFPLR5_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR5_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR5_0_PCIE_CCIX_CAP
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR5_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR5_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR5_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR5_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR5_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR5_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR5_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR5_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR5_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR5_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR5_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR5_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR5_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+//BIFPLR6_0_VENDOR_ID
+#define BIFPLR6_0_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR6_0_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR6_0_DEVICE_ID
+#define BIFPLR6_0_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR6_0_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR6_0_COMMAND
+#define BIFPLR6_0_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR6_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR6_0_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR6_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR6_0_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR6_0_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR6_0_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR6_0_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR6_0_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR6_0_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR6_0_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR6_0_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR6_0_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR6_0_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR6_0_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR6_0_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR6_0_STATUS
+#define BIFPLR6_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR6_0_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR6_0_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR6_0_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR6_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR6_0_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR6_0_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR6_0_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR6_0_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR6_0_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR6_0_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR6_0_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR6_0_REVISION_ID
+#define BIFPLR6_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR6_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR6_0_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR6_0_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR6_0_PROG_INTERFACE
+#define BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR6_0_SUB_CLASS
+#define BIFPLR6_0_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR6_0_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR6_0_BASE_CLASS
+#define BIFPLR6_0_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR6_0_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR6_0_CACHE_LINE
+#define BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR6_0_LATENCY
+#define BIFPLR6_0_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR6_0_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR6_0_HEADER
+#define BIFPLR6_0_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR6_0_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR6_0_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR6_0_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR6_0_BIST
+#define BIFPLR6_0_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR6_0_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR6_0_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR6_0_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR6_0_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR6_0_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR6_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR6_0_IO_BASE_LIMIT
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR6_0_SECONDARY_STATUS
+#define BIFPLR6_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR6_0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR6_0_MEM_BASE_LIMIT
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR6_0_PREF_BASE_LIMIT
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR6_0_PREF_BASE_UPPER
+#define BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_0_PREF_LIMIT_UPPER
+#define BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR6_0_IO_BASE_LIMIT_HI
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR6_0_CAP_PTR
+#define BIFPLR6_0_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR6_0_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR6_0_ROM_BASE_ADDR
+#define BIFPLR6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR6_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR6_0_INTERRUPT_LINE
+#define BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR6_0_INTERRUPT_PIN
+#define BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR6_0_IRQ_BRIDGE_CNTL
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR6_0_EXT_BRIDGE_CNTL
+#define BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR6_0_VENDOR_CAP_LIST
+#define BIFPLR6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR6_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR6_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR6_0_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR6_0_ADAPTER_ID_W
+#define BIFPLR6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR6_0_PMI_CAP_LIST
+#define BIFPLR6_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR6_0_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR6_0_PMI_CAP
+#define BIFPLR6_0_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR6_0_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR6_0_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR6_0_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR6_0_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR6_0_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR6_0_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR6_0_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR6_0_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR6_0_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR6_0_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR6_0_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR6_0_PMI_STATUS_CNTL
+#define BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR6_0_PCIE_CAP_LIST
+#define BIFPLR6_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR6_0_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR6_0_PCIE_CAP
+#define BIFPLR6_0_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR6_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR6_0_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR6_0_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR6_0_DEVICE_CAP
+#define BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR6_0_DEVICE_CNTL
+#define BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR6_0_DEVICE_STATUS
+#define BIFPLR6_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR6_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR6_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR6_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR6_0_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR6_0_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR6_0_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR6_0_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR6_0_LINK_CAP
+#define BIFPLR6_0_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR6_0_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR6_0_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR6_0_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR6_0_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR6_0_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR6_0_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR6_0_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR6_0_LINK_CNTL
+#define BIFPLR6_0_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR6_0_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR6_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR6_0_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR6_0_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR6_0_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR6_0_LINK_STATUS
+#define BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR6_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR6_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR6_0_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR6_0_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR6_0_SLOT_CAP
+#define BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR6_0_SLOT_CNTL
+#define BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR6_0_SLOT_STATUS
+#define BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR6_0_ROOT_CNTL
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR6_0_ROOT_CAP
+#define BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR6_0_ROOT_STATUS
+#define BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR6_0_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR6_0_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR6_0_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR6_0_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR6_0_DEVICE_CAP2
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR6_0_DEVICE_CNTL2
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR6_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR6_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR6_0_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR6_0_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR6_0_DEVICE_STATUS2
+#define BIFPLR6_0_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR6_0_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR6_0_LINK_CAP2
+#define BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR6_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR6_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR6_0_LINK_CNTL2
+#define BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR6_0_LINK_STATUS2
+#define BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR6_0_SLOT_CAP2
+#define BIFPLR6_0_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR6_0_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR6_0_SLOT_CNTL2
+#define BIFPLR6_0_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR6_0_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR6_0_SLOT_STATUS2
+#define BIFPLR6_0_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR6_0_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR6_0_MSI_CAP_LIST
+#define BIFPLR6_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR6_0_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR6_0_MSI_MSG_CNTL
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR6_0_MSI_MSG_ADDR_LO
+#define BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR6_0_MSI_MSG_ADDR_HI
+#define BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_0_MSI_MSG_DATA
+#define BIFPLR6_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR6_0_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR6_0_MSI_MSG_DATA_64
+#define BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR6_0_SSID_CAP_LIST
+#define BIFPLR6_0_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR6_0_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR6_0_SSID_CAP
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR6_0_MSI_MAP_CAP_LIST
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR6_0_MSI_MAP_CAP
+#define BIFPLR6_0_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR6_0_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR6_0_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR6_0_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR6_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR6_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR6_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR6_0_PCIE_PORT_VC_CNTL
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR6_0_PCIE_PORT_VC_STATUS
+#define BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR6_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR6_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR6_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR6_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR6_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR6_0_PCIE_CORR_ERR_MASK
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR6_0_PCIE_HDR_LOG0
+#define BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_HDR_LOG1
+#define BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_HDR_LOG2
+#define BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_HDR_LOG3
+#define BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR6_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR6_0_PCIE_ERR_SRC_ID
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR6_0_PCIE_LINK_CNTL3
+#define BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR6_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR6_0_PCIE_ACS_CAP
+#define BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR6_0_PCIE_ACS_CNTL
+#define BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR6_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR6_0_PCIE_MC_CAP
+#define BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR6_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR6_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR6_0_PCIE_MC_CNTL
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR6_0_PCIE_MC_ADDR0
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR6_0_PCIE_MC_ADDR1
+#define BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_RCV0
+#define BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_RCV1
+#define BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR6_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR6_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR6_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR6_0_PCIE_DPC_CAP_LIST
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR6_0_PCIE_DPC_CNTL
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR6_0_PCIE_DPC_STATUS
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_STATUS
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_MASK
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR6_0_PCIE_ESM_CAP_LIST
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR6_0_PCIE_ESM_HEADER_1
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR6_0_PCIE_ESM_HEADER_2
+#define BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR6_0_PCIE_ESM_STATUS
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR6_0_PCIE_ESM_CTRL
+#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR6_0_PCIE_ESM_CAP_1
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_2
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_3
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR6_0_PCIE_ESM_CAP_4
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_5
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_6
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_7
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR6_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR6_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR6_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR6_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR6_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR6_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR6_0_LINK_CAP_16GT
+#define BIFPLR6_0_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR6_0_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR6_0_LINK_CNTL_16GT
+#define BIFPLR6_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR6_0_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR6_0_LINK_STATUS_16GT
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR6_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR6_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR6_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR6_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR6_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR6_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR6_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR6_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR6_0_MARGINING_PORT_CAP
+#define BIFPLR6_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR6_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR6_0_MARGINING_PORT_STATUS
+#define BIFPLR6_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR6_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR6_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR6_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR6_0_PCIE_CCIX_HEADER_1
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR6_0_PCIE_CCIX_HEADER_2
+#define BIFPLR6_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR6_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR6_0_PCIE_CCIX_CAP
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR6_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR6_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR6_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR6_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR6_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR6_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR6_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR6_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR6_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR6_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR6_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR6_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR6_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp0_pciedir_p
+//BIFP0_PCIEP_RESERVED
+#define BIFP0_PCIEP_RESERVED__RESERVED__SHIFT                                                                 0x0
+#define BIFP0_PCIEP_RESERVED__RESERVED_MASK                                                                   0xFFFFFFFFL
+//BIFP0_PCIEP_SCRATCH
+#define BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT                                                             0x0
+#define BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK                                                               0xFFFFFFFFL
+//BIFP0_PCIEP_PORT_CNTL
+#define BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT                                                         0x0
+#define BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT                                                       0x1
+#define BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT                                                          0x2
+#define BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT                                                           0x3
+#define BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT                                                            0x4
+#define BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT                                                              0x5
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT                                         0x8
+#define BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT                                            0x12
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT                                             0x18
+#define BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT                                            0x1a
+#define BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK                                                           0x00000001L
+#define BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK                                                         0x00000002L
+#define BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK                                                            0x00000004L
+#define BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK                                                             0x00000008L
+#define BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK                                                              0x00000010L
+#define BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK                                                                0x00000020L
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK                                           0x0003FF00L
+#define BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK                                              0x001C0000L
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK                                               0x03000000L
+#define BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK                                              0x0C000000L
+//BIFP0_PCIE_TX_CNTL
+#define BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                            0xa
+#define BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                             0xc
+#define BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT                                                         0xe
+#define BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT                                                           0xf
+#define BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT                                                              0x14
+#define BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT                                                               0x15
+#define BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT                                                     0x16
+#define BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT                                                   0x17
+#define BIFP0_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT                                              0x1b
+#define BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                              0x00000C00L
+#define BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                               0x00003000L
+#define BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK                                                           0x00004000L
+#define BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK                                                             0x00008000L
+#define BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK                                                                0x00100000L
+#define BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P_MASK                                                                 0x00200000L
+#define BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK                                                       0x00400000L
+#define BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK                                                     0x00800000L
+#define BIFP0_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK                                                0x08000000L
+//BIFP0_PCIE_TX_REQUESTER_ID
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                           0x0
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                             0x3
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                                0x8
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                             0x00000007L
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                               0x000000F8L
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                                  0x0000FF00L
+//BIFP0_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT                                                  0x18
+#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK                                                    0x01000000L
+//BIFP0_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT                                          0x18
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT                                   0x1e
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT                                       0x1f
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK                                            0x3F000000L
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK                                     0x40000000L
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK                                         0x80000000L
+//BIFP0_PCIE_TX_SEQ
+#define BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT                                                        0x0
+#define BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT                                                                 0x10
+#define BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK                                                          0x00000FFFL
+#define BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK                                                                   0x0FFF0000L
+//BIFP0_PCIE_TX_REPLAY
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT                                                            0x0
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT                                                      0xe
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT                                                0xf
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT                                                          0x10
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK                                                              0x00000007L
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK                                                        0x00004000L
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK                                                  0x00008000L
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK                                                            0xFFFF0000L
+//BIFP0_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT                                          0x0
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT                                0xc
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK                                            0x00000FFFL
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK                                  0x00001000L
+//BIFP0_PCIE_TX_NOP_DLLP
+#define BIFP0_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT                                                            0x0
+#define BIFP0_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT                                                            0x18
+#define BIFP0_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK                                                              0x00FFFFFFL
+#define BIFP0_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK                                                              0x01000000L
+//BIFP0_PCIE_TX_CNTL_2
+//BIFP0_PCIE_TX_SKID_CTRL
+#define BIFP0_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT                                                  0x0
+#define BIFP0_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT                                            0x4
+#define BIFP0_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK                                                    0x0000000FL
+#define BIFP0_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK                                              0x00000010L
+//BIFP0_PCIE_TX_CREDITS_ADVT_P
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT                                               0x0
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT                                               0x10
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK                                                 0x00003FFFL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK                                                 0x03FF0000L
+//BIFP0_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT                                             0x0
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT                                             0x10
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK                                               0x00003FFFL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK                                               0x03FF0000L
+//BIFP0_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT                                           0x0
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT                                           0x10
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK                                             0x00003FFFL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK                                             0x03FF0000L
+//BIFP0_PCIE_TX_CREDITS_INIT_P
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT                                               0x0
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT                                               0x10
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK                                                 0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK                                                 0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_INIT_NP
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT                                             0x0
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT                                             0x10
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK                                               0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK                                               0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT                                           0x0
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT                                           0x10
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK                                             0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK                                             0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_STATUS
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT                                                0x0
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT                                                0x1
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT                                               0x2
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT                                               0x3
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT                                              0x4
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT                                              0x5
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT                                         0x10
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT                                         0x11
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT                                        0x12
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT                                        0x13
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT                                       0x14
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT                                       0x15
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK                                                  0x00000001L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK                                                  0x00000002L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK                                                 0x00000004L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK                                                 0x00000008L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK                                                0x00000010L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK                                                0x00000020L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK                                           0x00010000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK                                           0x00020000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK                                          0x00040000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK                                          0x00080000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK                                         0x00100000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK                                         0x00200000L
+//BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT                                    0x0
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT                                   0x4
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT                                  0x8
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT                                    0x10
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT                                   0x14
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT                                  0x18
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK                                      0x00000007L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK                                     0x00000070L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK                                    0x00000700L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK                                      0x00070000L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK                                     0x00700000L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK                                    0x07000000L
+//BIFP0_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT                                          0x0
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT                                                  0x3
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT                                           0x6
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT                                                   0x8
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT                                                   0x10
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT                                       0x19
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT                                              0x1c
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK                                            0x00000007L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK                                                    0x00000038L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK                                             0x00000040L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK                                                     0x00003F00L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK                                                     0x003F0000L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK                                         0x02000000L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK                                                0xF0000000L
+//BIFP0_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT                                      0x0
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK                                        0x0000FFFFL
+//BIFP0_PCIE_CCIX_STACKED_BASE
+#define BIFP0_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT                                           0x4
+#define BIFP0_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK                                             0xFFFFFFF0L
+//BIFP0_PCIE_CCIX_STACKED_LIMIT
+#define BIFP0_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT                                         0x4
+#define BIFP0_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK                                           0xFFFFFFF0L
+//BIFP0_PCIE_CCIX_MISC_STATUS
+#define BIFP0_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT                                              0x0
+#define BIFP0_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT                                          0x1
+#define BIFP0_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK                                                0x00000001L
+#define BIFP0_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK                                            0x00000002L
+//BIFP0_PCIE_P_PORT_LANE_STATUS
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT                                              0x0
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT                                                  0x1
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK                                                0x00000001L
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK                                                    0x0000007EL
+//BIFP0_PCIE_FC_P
+#define BIFP0_PCIE_FC_P__PD_CREDITS__SHIFT                                                                    0x0
+#define BIFP0_PCIE_FC_P__PH_CREDITS__SHIFT                                                                    0x10
+#define BIFP0_PCIE_FC_P__PD_CREDITS_MASK                                                                      0x0000FFFFL
+#define BIFP0_PCIE_FC_P__PH_CREDITS_MASK                                                                      0x0FFF0000L
+//BIFP0_PCIE_FC_NP
+#define BIFP0_PCIE_FC_NP__NPD_CREDITS__SHIFT                                                                  0x0
+#define BIFP0_PCIE_FC_NP__NPH_CREDITS__SHIFT                                                                  0x10
+#define BIFP0_PCIE_FC_NP__NPD_CREDITS_MASK                                                                    0x0000FFFFL
+#define BIFP0_PCIE_FC_NP__NPH_CREDITS_MASK                                                                    0x0FFF0000L
+//BIFP0_PCIE_FC_CPL
+#define BIFP0_PCIE_FC_CPL__CPLD_CREDITS__SHIFT                                                                0x0
+#define BIFP0_PCIE_FC_CPL__CPLH_CREDITS__SHIFT                                                                0x10
+#define BIFP0_PCIE_FC_CPL__CPLD_CREDITS_MASK                                                                  0x0000FFFFL
+#define BIFP0_PCIE_FC_CPL__CPLH_CREDITS_MASK                                                                  0x0FFF0000L
+//BIFP0_PCIE_FC_P_VC1
+#define BIFP0_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT                                                    0x0
+#define BIFP0_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT                                                    0x10
+#define BIFP0_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK                                                      0x0000FFFFL
+#define BIFP0_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK                                                      0x0FFF0000L
+//BIFP0_PCIE_FC_NP_VC1
+#define BIFP0_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT                                                  0x0
+#define BIFP0_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT                                                  0x10
+#define BIFP0_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK                                                    0x0000FFFFL
+#define BIFP0_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK                                                    0x0FFF0000L
+//BIFP0_PCIE_FC_CPL_VC1
+#define BIFP0_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT                                                0x0
+#define BIFP0_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT                                                0x10
+#define BIFP0_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK                                                  0x0000FFFFL
+#define BIFP0_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK                                                  0x0FFF0000L
+//BIFP0_PCIE_ERR_CNTL
+#define BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                         0x0
+#define BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT                                                  0x1
+#define BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT                                                     0x2
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT                                                      0x4
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT                                                      0x5
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT                                                      0x6
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT                                                      0x7
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                                       0x8
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                              0xb
+#define BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT                                               0xe
+#define BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT                                              0xf
+#define BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT                                                     0x10
+#define BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                                  0x11
+#define BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                                          0x12
+#define BIFP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT                                                    0x13
+#define BIFP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT                                                     0x14
+#define BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                           0x00000001L
+#define BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK                                                    0x00000002L
+#define BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK                                                       0x00000004L
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK                                                        0x00000010L
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK                                                        0x00000020L
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK                                                        0x00000040L
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK                                                        0x00000080L
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                         0x00000700L
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                                0x00000800L
+#define BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK                                                 0x00004000L
+#define BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK                                                0x00008000L
+#define BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK                                                       0x00010000L
+#define BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                                    0x00020000L
+#define BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                            0x00040000L
+#define BIFP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK                                                      0x00080000L
+#define BIFP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK                                                       0x00100000L
+//BIFP0_PCIE_RX_CNTL
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT                                                           0x0
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT                                                           0x1
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT                                                          0x2
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT                                                          0x3
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT                                                          0x4
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT                                                          0x5
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT                                                           0x6
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT                                                 0x7
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                                  0x8
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                           0x9
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT                                                           0xa
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT                                                            0xb
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT                                                           0xc
+#define BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT                                                        0xd
+#define BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT                                                        0xf
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT                                                         0x10
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT                                                    0x13
+#define BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                                    0x14
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                                  0x15
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                                    0x16
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT                                                    0x17
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                                 0x18
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                                     0x19
+#define BIFP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                                 0x1a
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                                     0x1b
+#define BIFP0_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT                                                              0x1c
+#define BIFP0_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT                                                0x1d
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK                                                             0x00000001L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK                                                             0x00000002L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK                                                            0x00000004L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK                                                            0x00000008L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK                                                            0x00000010L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK                                                            0x00000020L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK                                                             0x00000040L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK                                                   0x00000080L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                                    0x00000100L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                             0x00000200L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK                                                             0x00000400L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK                                                              0x00000800L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK                                                             0x00001000L
+#define BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK                                                          0x00002000L
+#define BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK                                                          0x00008000L
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK                                                           0x00070000L
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK                                                      0x00080000L
+#define BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                                      0x00100000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                                    0x00200000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                                      0x00400000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK                                                      0x00800000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                                   0x01000000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                                       0x02000000L
+#define BIFP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                                   0x04000000L
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                                       0x08000000L
+#define BIFP0_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK                                                                0x10000000L
+#define BIFP0_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK                                                  0x20000000L
+//BIFP0_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT                                              0x0
+#define BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK                                                0x00000FFFL
+//BIFP0_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT                                                0x18
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK                                                  0x01000000L
+//BIFP0_PCIE_RX_CNTL3
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT                                             0x0
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT                                             0x1
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT                                                0x2
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT                                                    0x3
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT                                               0x4
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK                                               0x00000001L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK                                               0x00000002L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK                                                  0x00000004L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK                                                      0x00000008L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK                                                 0x00000010L
+//BIFP0_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT                                     0x0
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT                                     0x10
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK                                       0x00000FFFL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK                                       0x00FF0000L
+//BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT                                   0x0
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT                                   0x10
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK                                     0x00000FFFL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK                                     0x00FF0000L
+//BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT                                 0x0
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT                                 0x10
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK                                   0x00000FFFL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK                                   0x00FF0000L
+//BIFP0_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT                                    0x0
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT                                 0x2
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT                           0x4
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT                             0x6
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT                              0x8
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT                              0xa
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT                                  0xc
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT                         0xe
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT                            0x10
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT                                0x12
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT                           0x14
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT                             0x16
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK                                      0x00000003L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK                                   0x0000000CL
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK                             0x00000030L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK                               0x000000C0L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK                                0x00000300L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK                                0x00000C00L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK                                    0x00003000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK                           0x0000C000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK                              0x00030000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK                                  0x000C0000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK                             0x00300000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK                               0x00C00000L
+//BIFP0_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT                             0x0
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT                      0x2
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT                                 0x4
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT                                  0x6
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT                          0x8
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT                               0xa
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT                            0xc
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT                         0xe
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT                          0x10
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT                       0x12
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK                               0x00000003L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK                        0x0000000CL
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK                                   0x00000030L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK                                    0x000000C0L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK                            0x00000300L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK                                 0x00000C00L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK                              0x00003000L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK                           0x0000C000L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK                            0x00030000L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK                         0x000C0000L
+//BIFP0_PCIEP_NAK_COUNTER
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT                                              0x0
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT                                             0x10
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK                                                0x0000FFFFL
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK                                               0xFFFF0000L
+//BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT                     0x0
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT                     0xa
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT                      0xf
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT                  0x10
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT                  0x1a
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT                   0x1f
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK                       0x000003FFL
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK                       0x00001C00L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK                        0x00008000L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK                    0x03FF0000L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK                    0x1C000000L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK                     0x80000000L
+//BIFP0_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP0_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT                                    0x5
+#define BIFP0_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK                                      0x00000020L
+//BIFP0_PCIE_AER_PRIV_TRIGGER
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT                          0x0
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT                           0x1
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT                         0x2
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK                            0x00000001L
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK                             0x00000002L
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK                           0x00000004L
+//BIFP0_PCIE_LC_CNTL
+#define BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT                                                    0x1
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT                                                   0x2
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT                                                              0x3
+#define BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT                                                       0x4
+#define BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT                                                          0x8
+#define BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT                                                           0xc
+#define BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT                                                           0x10
+#define BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT                                                            0x11
+#define BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT                                                  0x12
+#define BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT                                                      0x14
+#define BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT                                                     0x15
+#define BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT                                                           0x16
+#define BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT                                                        0x17
+#define BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT                                                          0x18
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT                                                             0x19
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT                                                          0x1b
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT                                                           0x1c
+#define BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT                                                 0x1d
+#define BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT                                                         0x1e
+#define BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT                                                          0x1f
+#define BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK                                                      0x00000002L
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK                                                     0x00000004L
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_LINK_MASK                                                                0x00000008L
+#define BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK                                                         0x000000F0L
+#define BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK                                                            0x00000F00L
+#define BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK                                                             0x0000F000L
+#define BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK                                                             0x00010000L
+#define BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK                                                              0x00020000L
+#define BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK                                                    0x000C0000L
+#define BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK                                                        0x00100000L
+#define BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK                                                       0x00200000L
+#define BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK                                                             0x00400000L
+#define BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK                                                          0x00800000L
+#define BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK                                                            0x01000000L
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK                                                               0x06000000L
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK                                                            0x08000000L
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK                                                             0x10000000L
+#define BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK                                                   0x20000000L
+#define BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK                                                           0x40000000L
+#define BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK                                                            0x80000000L
+//BIFP0_PCIE_LC_TRAINING_CNTL
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT                                                  0x0
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT                                             0x4
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT                                 0x5
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT                                        0x6
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT                                            0x7
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT                                                    0x8
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT                                     0xb
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT                                       0xc
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT                                      0xd
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT                                          0xe
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT                                        0xf
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT                                            0x10
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT                                          0x11
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT                                            0x12
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT                                                 0x13
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT                                                 0x14
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT                                        0x15
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT                                          0x16
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT                                 0x18
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT                                    0x19
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT                                        0x1a
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT                                             0x1b
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT                                            0x1c
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT                                 0x1d
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT                                             0x1e
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK                                                    0x0000000FL
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK                                               0x00000010L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK                                   0x00000020L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK                                          0x00000040L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK                                              0x00000080L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK                                                      0x00000700L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK                                       0x00000800L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK                                         0x00001000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK                                        0x00002000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK                                            0x00004000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK                                          0x00008000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK                                              0x00010000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK                                            0x00020000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK                                              0x00040000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK                                                   0x00080000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK                                                   0x00100000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK                                          0x00200000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK                                            0x00C00000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK                                   0x01000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK                                      0x02000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK                                          0x04000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK                                               0x08000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK                                              0x10000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK                                   0x20000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK                                               0xC0000000L
+//BIFP0_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT                                                   0x0
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT                                                0x4
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT                                  0x7
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT                                                 0x8
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT                                        0x9
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT                                               0xa
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT                                            0xb
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT                                          0xc
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT                                              0xd
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT                                      0xe
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT                                              0xf
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT                                               0x11
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT                                               0x12
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT                                         0x13
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT                                          0x14
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT                                          0x15
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT                                         0x17
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT                                       0x18
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT                                  0x19
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT                                    0x1a
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT                                0x1b
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT                                0x1c
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT                                     0x1d
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT                                        0x1e
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT                                      0x1f
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK                                                     0x00000007L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK                                                  0x00000070L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK                                    0x00000080L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK                                                   0x00000100L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK                                          0x00000200L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK                                                 0x00000400L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK                                              0x00000800L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK                                            0x00001000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK                                                0x00002000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK                                        0x00004000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK                                                0x00008000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK                                                 0x00020000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK                                                 0x00040000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK                                           0x00080000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK                                            0x00100000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK                                            0x00600000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK                                           0x00800000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK                                         0x01000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK                                    0x02000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK                                      0x04000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK                                  0x08000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK                                  0x10000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK                                       0x20000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK                                          0x40000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK                                        0x80000000L
+//BIFP0_PCIE_LC_N_FTS_CNTL
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT                                                        0x0
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT                                            0x8
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT                                          0x9
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT                                                         0xa
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT                                               0xe
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT                                              0xf
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT                                                  0x10
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT                                                             0x18
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK                                                          0x000000FFL
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK                                              0x00000100L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK                                            0x00000200L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK                                                           0x00000400L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK                                                 0x00004000L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK                                                0x00008000L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK                                                    0x00FF0000L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK                                                               0xFF000000L
+//BIFP0_PCIE_LC_SPEED_CNTL
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                                     0x0
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                                     0x1
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                                     0x2
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT                                     0x3
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT                                        0x4
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT                                          0x6
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT                                         0x7
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT                                          0x8
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT                                         0x9
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT                                        0xa
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0xb
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0xd
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT                                                 0xe
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT                                 0x10
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT                                         0x11
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT                                        0x12
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT                                         0x13
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT                                          0x14
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT                                         0x15
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT                                          0x16
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT                                         0x17
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT                                          0x18
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT                                               0x19
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT                                              0x1a
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT                                                   0x1c
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT                                    0x1d
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT                                          0x1e
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT                                           0x1f
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                                       0x00000001L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                                       0x00000002L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                                       0x00000004L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK                                       0x00000008L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK                                          0x00000030L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK                                            0x00000040L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK                                           0x00000080L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK                                            0x00000100L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK                                           0x00000200L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK                                          0x00000400L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x00001800L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00002000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK                                                   0x0000C000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK                                   0x00010000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK                                           0x00020000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK                                          0x00040000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK                                           0x00080000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK                                            0x00100000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK                                           0x00200000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK                                            0x00400000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK                                           0x00800000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK                                            0x01000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK                                                 0x02000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK                                                0x0C000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK                                                     0x10000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK                                      0x20000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK                                            0x40000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK                                             0x80000000L
+//BIFP0_PCIE_LC_STATE0
+#define BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT                                                         0x0
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT                                                           0x8
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT                                                           0x10
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT                                                           0x18
+#define BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK                                                           0x0000003FL
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1_MASK                                                             0x00003F00L
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2_MASK                                                             0x003F0000L
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3_MASK                                                             0x3F000000L
+//BIFP0_PCIE_LC_STATE1
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT                                                           0x0
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT                                                           0x8
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT                                                           0x10
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT                                                           0x18
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4_MASK                                                             0x0000003FL
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5_MASK                                                             0x00003F00L
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6_MASK                                                             0x003F0000L
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7_MASK                                                             0x3F000000L
+//BIFP0_PCIE_LC_STATE2
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT                                                           0x0
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT                                                           0x8
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT                                                          0x10
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT                                                          0x18
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8_MASK                                                             0x0000003FL
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9_MASK                                                             0x00003F00L
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10_MASK                                                            0x003F0000L
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11_MASK                                                            0x3F000000L
+//BIFP0_PCIE_LC_STATE3
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT                                                          0x0
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT                                                          0x8
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT                                                          0x10
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT                                                          0x18
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12_MASK                                                            0x0000003FL
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13_MASK                                                            0x00003F00L
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14_MASK                                                            0x003F0000L
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15_MASK                                                            0x3F000000L
+//BIFP0_PCIE_LC_STATE4
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT                                                          0x0
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT                                                          0x8
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT                                                          0x10
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT                                                          0x18
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16_MASK                                                            0x0000003FL
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17_MASK                                                            0x00003F00L
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18_MASK                                                            0x003F0000L
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19_MASK                                                            0x3F000000L
+//BIFP0_PCIE_LC_STATE5
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT                                                          0x0
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT                                                          0x8
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT                                                          0x10
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT                                                          0x18
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20_MASK                                                            0x0000003FL
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21_MASK                                                            0x00003F00L
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22_MASK                                                            0x003F0000L
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23_MASK                                                            0x3F000000L
+//BIFP0_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT                                                 0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT                                                 0x1
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT                                                  0x2
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT                                                  0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT                                                 0x4
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT                                                0x5
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT                                                0x6
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT                                          0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT                                         0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT                                          0xf
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT                                         0x13
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT                                          0x17
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT                                         0x1b
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK                                                   0x00000001L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK                                                   0x00000002L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK                                                    0x00000004L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK                                                    0x00000008L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK                                                   0x00000010L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK                                                  0x00000020L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK                                                  0x00000040L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK                                            0x00000780L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK                                           0x00007800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK                                            0x00078000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK                                           0x00780000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK                                            0x07800000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK                                           0x78000000L
+//BIFP0_PCIE_LC_CNTL2
+#define BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT                                                        0x0
+#define BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT                                                        0x6
+#define BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT                                                  0x7
+#define BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT                                                            0x8
+#define BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT                                                    0x9
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT                                                    0xa
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT                                                          0xb
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT                                               0xc
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT                                              0xd
+#define BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT                                                         0xe
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT                                         0x10
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT                                                       0x11
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT                                                      0x12
+#define BIFP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT                                              0x13
+#define BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT                                                    0x14
+#define BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT                                                  0x15
+#define BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT                                            0x16
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT                                               0x17
+#define BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT                                                 0x19
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT                                             0x1a
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                               0x1b
+#define BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT                                               0x1c
+#define BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT                                                         0x1d
+#define BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT                                       0x1f
+#define BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK                                                          0x0000003FL
+#define BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK                                                          0x00000040L
+#define BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK                                                    0x00000080L
+#define BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK                                                              0x00000100L
+#define BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK                                                      0x00000200L
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK                                                      0x00000400L
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK                                                            0x00000800L
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK                                                 0x00001000L
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK                                                0x00002000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK                                                           0x0000C000L
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK                                           0x00010000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK                                                         0x00020000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK                                                        0x00040000L
+#define BIFP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK                                                0x00080000L
+#define BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK                                                      0x00100000L
+#define BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK                                                    0x00200000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK                                              0x00400000L
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK                                                 0x01800000L
+#define BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK                                                   0x02000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK                                               0x04000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                                 0x08000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK                                                 0x10000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK                                                           0x60000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK                                         0x80000000L
+//BIFP0_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT                                              0x0
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT                                          0x1
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT                                          0x2
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT                                       0x3
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT                                      0x4
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT                                              0x5
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT                                                0x6
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT                                               0x7
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT                                               0x8
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT                                              0x9
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT                              0xa
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT                                        0xb
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK                                                0x00000001L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK                                            0x00000002L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK                                            0x00000004L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK                                         0x00000008L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK                                        0x00000010L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK                                                0x00000020L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK                                                  0x00000040L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK                                                 0x00000080L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK                                                 0x00000100L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK                                                0x00000200L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK                                0x00000400L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK                                          0x00000800L
+//BIFP0_PCIE_LC_CDR_CNTL
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT                                                        0x0
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT                                                       0xc
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT                                                        0x18
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK                                                          0x00000FFFL
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK                                                         0x00FFF000L
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK                                                          0x03000000L
+//BIFP0_PCIE_LC_LANE_CNTL
+#define BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT                                                    0x0
+#define BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK                                                      0x0000FFFFL
+//BIFP0_PCIE_LC_CNTL3
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT                                                      0x0
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT                                                 0x1
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT                                                        0x3
+#define BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT                                                         0x4
+#define BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT                                              0x5
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0x6
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0x8
+#define BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT                                         0x9
+#define BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT                                                   0xa
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT                                                   0xb
+#define BIFP0_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT                                                   0xc
+#define BIFP0_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT                                         0xd
+#define BIFP0_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT                                         0xe
+#define BIFP0_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT                                    0xf
+#define BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT                                                   0x11
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT                                          0x12
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT                                0x13
+#define BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT                                                  0x15
+#define BIFP0_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT                             0x16
+#define BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT                                       0x17
+#define BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT                                                  0x18
+#define BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT                                                      0x1a
+#define BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT                                                         0x1e
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT                                                      0x1f
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK                                                        0x00000001L
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK                                                   0x00000006L
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK                                                          0x00000008L
+#define BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK                                                           0x00000010L
+#define BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK                                                0x00000020L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x000000C0L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00000100L
+#define BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK                                           0x00000200L
+#define BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK                                                     0x00000400L
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK                                                     0x00000800L
+#define BIFP0_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK                                                     0x00001000L
+#define BIFP0_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK                                           0x00002000L
+#define BIFP0_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK                                           0x00004000L
+#define BIFP0_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK                                      0x00008000L
+#define BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK                                                     0x00020000L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK                                            0x00040000L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK                                  0x00180000L
+#define BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK                                                    0x00200000L
+#define BIFP0_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK                               0x00400000L
+#define BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK                                         0x00800000L
+#define BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK                                                    0x03000000L
+#define BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK                                                        0x3C000000L
+#define BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK                                                           0x40000000L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK                                                        0x80000000L
+//BIFP0_PCIE_LC_CNTL4
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT                                                    0x0
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT                                               0x2
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT                                            0x3
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT                                                          0x4
+#define BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT                                                            0x5
+#define BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT                                                           0x6
+#define BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT                                                          0x7
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT                                                     0x8
+#define BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT                                              0xa
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT                                                    0xb
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT                                                       0xc
+#define BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT                                                            0xd
+#define BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT                                                           0xe
+#define BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT                                             0xf
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT                                                0x10
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT                                       0x11
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT                                                 0x12
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT                                                        0x16
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT                                                               0x17
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT                                                  0x18
+#define BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT                                                      0x19
+#define BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT                                              0x1a
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK                                                      0x00000003L
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK                                                 0x00000004L
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK                                              0x00000008L
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK                                                            0x00000010L
+#define BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK                                                              0x00000020L
+#define BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK                                                             0x00000040L
+#define BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK                                                            0x00000080L
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK                                                       0x00000300L
+#define BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK                                                0x00000400L
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK                                                      0x00000800L
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK                                                         0x00001000L
+#define BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK                                                              0x00002000L
+#define BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK                                                             0x00004000L
+#define BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK                                               0x00008000L
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK                                                  0x00010000L
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK                                         0x00020000L
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK                                                   0x003C0000L
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK                                                          0x00400000L
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_SWING_MASK                                                                 0x00800000L
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK                                                    0x01000000L
+#define BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK                                                        0x02000000L
+#define BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK                                                0xFC000000L
+//BIFP0_PCIE_LC_CNTL5
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT                                                 0x0
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT                                                           0x2
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT                                                       0x6
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT                                                           0xa
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT                                                      0x10
+#define BIFP0_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT                                      0x15
+#define BIFP0_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT                                                      0x16
+#define BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT                                        0x18
+#define BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT                                                      0x19
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT                                                     0x1a
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT                                                0x1b
+#define BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT                                                         0x1c
+#define BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT                                                     0x1d
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK                                                   0x00000003L
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK                                                             0x0000003CL
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK                                                         0x000003C0L
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK                                                             0x0000FC00L
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK                                                        0x001F0000L
+#define BIFP0_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK                                        0x00200000L
+#define BIFP0_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK                                                        0x00C00000L
+#define BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK                                          0x01000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK                                                        0x02000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK                                                       0x04000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK                                                  0x08000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK                                                           0x10000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK                                                       0xE0000000L
+//BIFP0_PCIE_LC_FORCE_COEFF
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT                                                  0x0
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT                                             0x1
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT                                                 0x7
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT                                            0xd
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT                                          0x13
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT                                                     0x14
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK                                                    0x00000001L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK                                               0x0000007EL
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK                                                   0x00001F80L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK                                              0x0007E000L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK                                            0x00080000L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK                                                       0x00100000L
+//BIFP0_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT                                                 0x0
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT                                              0x4
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT                                                 0xa
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT                                             0x10
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT                                                    0x16
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT                                          0x1e
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK                                                   0x0000000FL
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK                                                0x000003F0L
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK                                                   0x0000FC00L
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK                                               0x003F0000L
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK                                                      0x3FC00000L
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK                                            0x40000000L
+//BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT                           0x0
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT                                  0x1
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT                                      0x7
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT                                 0xd
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT                                          0x13
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT                                          0x19
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK                             0x00000001L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK                                    0x0000007EL
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK                                        0x00001F80L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK                                   0x0007E000L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK                                            0x01F80000L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK                                            0x7E000000L
+//BIFP0_PCIE_LC_CNTL6
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT                                                         0x0
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT                                                           0x2
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT                                                           0x4
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT                                                          0x6
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT                                                                0x8
+#define BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT                                                      0x9
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT                                                     0xd
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT                                                 0xe
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT                                                   0x10
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT                                           0x12
+#define BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT                                                0x13
+#define BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT                                                     0x14
+#define BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT                                                           0x15
+#define BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT                                                               0x16
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT                                                           0x17
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT                                                      0x18
+#define BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT                                                      0x1f
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK                                                           0x00000003L
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK                                                             0x0000000CL
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK                                                             0x00000030L
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK                                                            0x000000C0L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN_MASK                                                                  0x00000100L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK                                                        0x00001E00L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK                                                       0x00002000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK                                                   0x0000C000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK                                                     0x00030000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK                                             0x00040000L
+#define BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK                                                  0x00080000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK                                                       0x00100000L
+#define BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK                                                             0x00200000L
+#define BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK                                                                 0x00400000L
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK                                                             0x00800000L
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK                                                        0x7F000000L
+#define BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK                                                        0x80000000L
+//BIFP0_PCIE_LC_CNTL7
+#define BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT                                              0x0
+#define BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT                                         0x1
+#define BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT                                             0x2
+#define BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT                                                   0x3
+#define BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT                                                     0x4
+#define BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT                                            0x5
+#define BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT                                                          0x6
+#define BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT                                                0x7
+#define BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT                                                     0x8
+#define BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT                                              0x9
+#define BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT                                               0xa
+#define BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT                                             0xb
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT                                          0xc
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT                                            0xd
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT                                                0x15
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT                                         0x16
+#define BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT                                                     0x17
+#define BIFP0_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT                                              0x18
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT                                                              0x19
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT                                                     0x1b
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT                                                      0x1c
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT                                                          0x1d
+#define BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT                                                          0x1e
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT                                                         0x1f
+#define BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK                                                0x00000001L
+#define BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK                                           0x00000002L
+#define BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK                                               0x00000004L
+#define BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK                                                     0x00000008L
+#define BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK                                                       0x00000010L
+#define BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK                                              0x00000020L
+#define BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK                                                            0x00000040L
+#define BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK                                                  0x00000080L
+#define BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK                                                       0x00000100L
+#define BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK                                                0x00000200L
+#define BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK                                                 0x00000400L
+#define BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK                                               0x00000800L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK                                            0x00001000L
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK                                              0x001FE000L
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK                                                  0x00200000L
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK                                           0x00400000L
+#define BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK                                                       0x00800000L
+#define BIFP0_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK                                                0x01000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_RATES_MASK                                                                0x06000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK                                                       0x08000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK                                                        0x10000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK                                                            0x20000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK                                                            0x40000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK                                                           0x80000000L
+//BIFP0_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT                                           0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                            0x1
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT                           0x2
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT                                           0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT                            0x4
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT                           0x5
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT                                 0x6
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT                                            0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT                                     0x8
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT                                         0x9
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT                                        0xa
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT                                    0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT                                    0xc
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT                                  0xd
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK                                             0x00000001L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK                              0x00000002L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK                             0x00000004L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK                                             0x00000008L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK                              0x00000010L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK                             0x00000020L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK                                   0x00000040L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK                                              0x00000080L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK                                       0x00000100L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK                                           0x00000200L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK                                          0x00000400L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK                                      0x00000800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK                                      0x00001000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK                                    0x00002000L
+//BIFP0_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT                                        0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x1
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT                        0x2
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT                                        0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x4
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT                        0x5
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT                              0x6
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT                                         0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT                                  0x8
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT                                      0x9
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT                                     0xa
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT                                 0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT                                 0xc
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT                               0xd
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK                                          0x00000001L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000002L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK                          0x00000004L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK                                          0x00000008L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000010L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK                          0x00000020L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK                                0x00000040L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK                                           0x00000080L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK                                    0x00000100L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK                                        0x00000200L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK                                       0x00000400L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK                                   0x00000800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK                                   0x00001000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK                                 0x00002000L
+//BIFP0_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT                                         0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT                                              0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT                                         0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT                                                       0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT                                             0xc
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT                                                      0xd
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT                                                    0xf
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT                                                   0x11
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT                                                  0x12
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT                                              0x13
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT                                             0x17
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT                                                 0x1b
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT                                               0x1e
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT                                              0x1f
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK                                           0x00000007L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK                                                0x00000078L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK                                           0x00000780L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK                                                         0x00000800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK                                               0x00001000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK                                                        0x00006000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK                                                      0x00018000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK                                                     0x00020000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK                                                    0x00040000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK                                                0x00780000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK                                               0x07800000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK                                                   0x38000000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK                                                 0x40000000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK                                                0x80000000L
+//BIFP0_PCIEP_STRAP_LC
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT                                                     0x0
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT                                                    0x2
+#define BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT                                                     0x4
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT                                                   0x6
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT                                                      0x8
+#define BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT                                                    0xb
+#define BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT                                                     0xc
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT                                                   0xd
+#define BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT                                                   0xe
+#define BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT                                      0xf
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT                                                   0x10
+#define BIFP0_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                            0x13
+#define BIFP0_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT                                             0x14
+#define BIFP0_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT                                             0x15
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK                                                       0x00000003L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK                                                      0x0000000CL
+#define BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK                                                       0x00000030L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK                                                     0x000000C0L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK                                                        0x00000700L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK                                                      0x00000800L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK                                                       0x00001000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK                                                     0x00002000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK                                                     0x00004000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK                                        0x00008000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK                                                     0x00070000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK                                              0x00080000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK                                               0x00100000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK                                               0x00200000L
+//BIFP0_PCIEP_STRAP_MISC
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT                                                    0x0
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT                                                    0x1
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT                                           0x2
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT                                                   0x3
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT                                                    0x5
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT                                                          0x6
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT                                         0x7
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK                                                      0x00000001L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK                                                      0x00000002L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK                                             0x00000004L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK                                                     0x00000018L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK                                                      0x00000020L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK                                                            0x00000040L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK                                           0x00000080L
+//BIFP0_PCIEP_STRAP_LC2
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT                                                0x0
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT                                             0x1
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT                                                  0x3
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT                                                    0x4
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT                                              0x7
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK                                                  0x00000001L
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK                                               0x00000006L
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK                                                    0x00000008L
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK                                                      0x00000070L
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK                                                0x00000380L
+//BIFP0_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT                                      0x0
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT                                          0x1
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT                                          0x2
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT                                            0x3
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT                                            0x4
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT                                              0x5
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT                                              0x6
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT                                              0x8
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT                                                0x10
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT                                                0x14
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT                                               0x17
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT                                 0x1a
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT                                   0x1b
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT                          0x1c
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK                                        0x00000001L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK                                            0x00000002L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK                                            0x00000004L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK                                              0x00000008L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK                                              0x00000010L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK                                                0x00000020L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK                                                0x000000C0L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK                                                0x00001F00L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK                                                  0x00070000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK                                                  0x00700000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK                                                 0x03800000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK                                   0x04000000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK                                     0x08000000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK                            0x10000000L
+//BIFP0_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT                                              0x0
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT                                          0x8
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK                                                0x000000FFL
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK                                            0x00000700L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+//BIFP0_PCIE_LC_PORT_ORDER
+#define BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT                                                       0x0
+#define BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK                                                         0x0000000FL
+//BIFP0_PCIEP_BCH_ECC_CNTL
+#define BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT                                                     0x0
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT                                              0x8
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT                                                 0x10
+#define BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK                                                       0x00000001L
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK                                                0x0000FF00L
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK                                                   0xFFFF0000L
+//BIFP0_PCIEP_HPGI_PRIVATE
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT                                      0x3
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT                                        0x6
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK                                        0x00000008L
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK                                          0x00000040L
+//BIFP0_PCIEP_HPGI
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT                                                    0x0
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT                                                    0x1
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT                                                  0x2
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT                                                  0x3
+#define BIFP0_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT                                                                0x7
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT                                                0x8
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT                                                0x9
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT                                              0xa
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT                                              0xb
+#define BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT                                 0xf
+#define BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT                                     0x10
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK                                                      0x00000001L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK                                                      0x00000002L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK                                                    0x00000004L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK                                                    0x00000008L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_HOOK_MASK                                                                  0x00000080L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK                                                  0x00000100L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK                                                  0x00000200L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK                                                0x00000400L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK                                                0x00000800L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK                                   0x00008000L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK                                       0x00010000L
+//BIFP0_PCIEP_HCNT_DESCRIPTOR
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT                                    0x0
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT                                 0x1f
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK                                      0x00001FFFL
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK                                   0x80000000L
+//BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT                                          0x0
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT                                        0x10
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK                                            0x0000FFFFL
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK                                          0x00FF0000L
+//BIFP0_PCIE_LC_CNTL8
+#define BIFP0_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT                                                    0x0
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT                                                         0x2
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT                                                  0x3
+#define BIFP0_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT                                                           0x7
+#define BIFP0_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT                                                   0x8
+#define BIFP0_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT                                                      0x9
+#define BIFP0_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT                                            0xa
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT                                               0xb
+#define BIFP0_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT                                      0xc
+#define BIFP0_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT                                                0xd
+#define BIFP0_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT                                                        0x11
+#define BIFP0_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT                                                           0x12
+#define BIFP0_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT                                                       0x16
+#define BIFP0_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT                                                               0x17
+#define BIFP0_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT                                                         0x19
+#define BIFP0_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT                                                0x1a
+#define BIFP0_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT                                                 0x1b
+#define BIFP0_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT                                                         0x1c
+#define BIFP0_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT                                                0x1d
+#define BIFP0_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT                                             0x1e
+#define BIFP0_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK                                                      0x00000003L
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK                                                           0x00000004L
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK                                                    0x00000078L
+#define BIFP0_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK                                                             0x00000080L
+#define BIFP0_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK                                                     0x00000100L
+#define BIFP0_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK                                                        0x00000200L
+#define BIFP0_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK                                              0x00000400L
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK                                                 0x00000800L
+#define BIFP0_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK                                        0x00001000L
+#define BIFP0_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK                                                  0x0001E000L
+#define BIFP0_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK                                                          0x00020000L
+#define BIFP0_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK                                                             0x003C0000L
+#define BIFP0_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK                                                         0x00400000L
+#define BIFP0_PCIE_LC_CNTL8__LC_FOM_TIME_MASK                                                                 0x01800000L
+#define BIFP0_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK                                                           0x02000000L
+#define BIFP0_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK                                                  0x04000000L
+#define BIFP0_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK                                                   0x08000000L
+#define BIFP0_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK                                                           0x10000000L
+#define BIFP0_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK                                                  0x20000000L
+#define BIFP0_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK                                               0xC0000000L
+//BIFP0_PCIE_LC_CNTL9
+#define BIFP0_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT                                           0x0
+#define BIFP0_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT                                              0x1
+#define BIFP0_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT                                                0x3
+#define BIFP0_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT                                                       0x4
+#define BIFP0_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT                                                 0x6
+#define BIFP0_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT                                                 0x8
+#define BIFP0_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT                            0xa
+#define BIFP0_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT                                                   0xb
+#define BIFP0_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT                                               0xc
+#define BIFP0_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT                                                    0xd
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT                                                 0xe
+#define BIFP0_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT                                                 0x18
+#define BIFP0_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT                                                0x19
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT                                                  0x1a
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT                                                 0x1b
+#define BIFP0_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT                                              0x1c
+#define BIFP0_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT                               0x1d
+#define BIFP0_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT                                      0x1e
+#define BIFP0_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT                                      0x1f
+#define BIFP0_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK                                             0x00000001L
+#define BIFP0_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK                                                0x00000006L
+#define BIFP0_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK                                                  0x00000008L
+#define BIFP0_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK                                                         0x00000030L
+#define BIFP0_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK                                                   0x000000C0L
+#define BIFP0_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK                                                   0x00000300L
+#define BIFP0_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK                              0x00000400L
+#define BIFP0_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK                                                     0x00000800L
+#define BIFP0_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK                                                 0x00001000L
+#define BIFP0_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK                                                      0x00002000L
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK                                                   0x00FFC000L
+#define BIFP0_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK                                                   0x01000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK                                                  0x02000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK                                                    0x04000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK                                                   0x08000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK                                                0x10000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK                                 0x20000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK                                        0x40000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK                                        0x80000000L
+//BIFP0_PCIE_LC_FORCE_COEFF2
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT                                                0x0
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT                                           0x1
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT                                               0x7
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT                                          0xd
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT                                        0x13
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK                                                  0x00000001L
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK                                             0x0000007EL
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK                                                 0x00001F80L
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK                                            0x0007E000L
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK                                          0x00080000L
+//BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT                         0x0
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT                                0x1
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT                                    0x7
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT                               0xd
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT                                        0x13
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT                                        0x19
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK                           0x00000001L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK                                  0x0000007EL
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK                                      0x00001F80L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK                                 0x0007E000L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK                                          0x01F80000L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK                                          0x7E000000L
+//BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT                                       0x0
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT                                     0x10
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK                                         0x0000FFFFL
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK                                       0x00FF0000L
+//BIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT             0x0
+#define BIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT               0x1
+#define BIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK               0x00000001L
+#define BIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK                 0x00000002L
+//BIFP0_PCIE_LC_CNTL10
+#define BIFP0_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT                      0x0
+#define BIFP0_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT                                         0x1
+#define BIFP0_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT                                             0x2
+#define BIFP0_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT                                            0x4
+#define BIFP0_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT                                                       0x6
+#define BIFP0_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT                                                      0x10
+#define BIFP0_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT                                     0x1a
+#define BIFP0_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT                                                0x1b
+#define BIFP0_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT                                              0x1d
+#define BIFP0_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT                                 0x1e
+#define BIFP0_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT                                 0x1f
+#define BIFP0_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK                        0x00000001L
+#define BIFP0_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK                                           0x00000002L
+#define BIFP0_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK                                               0x0000000CL
+#define BIFP0_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK                                              0x00000030L
+#define BIFP0_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK                                                         0x0000FFC0L
+#define BIFP0_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK                                                        0x03FF0000L
+#define BIFP0_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK                                       0x04000000L
+#define BIFP0_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK                                                  0x18000000L
+#define BIFP0_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK                                                0x20000000L
+#define BIFP0_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK                                   0x40000000L
+#define BIFP0_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK                                   0x80000000L
+//BIFP0_PCIE_LC_CNTL11
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT                                            0x0
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT                                          0x1
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT                                          0x2
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT                                          0x3
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT                                         0x5
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT                                          0x9
+#define BIFP0_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT                                    0xd
+#define BIFP0_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT                                          0xe
+#define BIFP0_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT                                           0xf
+#define BIFP0_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT                                                0x10
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT                       0x11
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT                         0x12
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT                              0x13
+#define BIFP0_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT                        0x14
+#define BIFP0_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT                                   0x15
+#define BIFP0_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT                                        0x16
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT                                                               0x17
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT                                                        0x18
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT                                                             0x1a
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT                                                             0x1b
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT                                                   0x1c
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT                                                     0x1e
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK                                              0x00000001L
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK                                            0x00000002L
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK                                            0x00000004L
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK                                            0x00000018L
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK                                           0x000001E0L
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK                                            0x00001E00L
+#define BIFP0_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK                                      0x00002000L
+#define BIFP0_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK                                            0x00004000L
+#define BIFP0_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK                                             0x00008000L
+#define BIFP0_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK                                                  0x00010000L
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK                         0x00020000L
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK                           0x00040000L
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK                                0x00080000L
+#define BIFP0_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK                          0x00100000L
+#define BIFP0_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK                                     0x00200000L
+#define BIFP0_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK                                          0x00400000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_EN_MASK                                                                 0x00800000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK                                                          0x03000000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK                                                               0x04000000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK                                                               0x08000000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK                                                     0x30000000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK                                                       0xC0000000L
+//BIFP0_PCIE_LC_CNTL12
+#define BIFP0_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT                                         0x0
+#define BIFP0_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT                                0x1
+#define BIFP0_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT                                        0x2
+#define BIFP0_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT                                            0x3
+#define BIFP0_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT                                 0x4
+#define BIFP0_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT                                      0x5
+#define BIFP0_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT                                         0x6
+#define BIFP0_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT                                                     0x7
+#define BIFP0_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT                                           0x8
+#define BIFP0_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT                                       0x9
+#define BIFP0_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT                                              0xa
+#define BIFP0_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT                                   0xb
+#define BIFP0_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT                                                0xc
+#define BIFP0_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT                                             0xd
+#define BIFP0_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT                                            0xe
+#define BIFP0_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT                                                0xf
+#define BIFP0_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT                                0x10
+#define BIFP0_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT                              0x11
+#define BIFP0_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT                            0x12
+#define BIFP0_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT                                          0x13
+#define BIFP0_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT                                                 0x14
+#define BIFP0_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT                                          0x15
+#define BIFP0_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT                                             0x16
+#define BIFP0_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT                                            0x17
+#define BIFP0_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT                                            0x1f
+#define BIFP0_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK                                           0x00000001L
+#define BIFP0_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK                                  0x00000002L
+#define BIFP0_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK                                          0x00000004L
+#define BIFP0_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK                                              0x00000008L
+#define BIFP0_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK                                   0x00000010L
+#define BIFP0_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK                                        0x00000020L
+#define BIFP0_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK                                           0x00000040L
+#define BIFP0_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK                                                       0x00000080L
+#define BIFP0_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK                                             0x00000100L
+#define BIFP0_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK                                         0x00000200L
+#define BIFP0_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK                                                0x00000400L
+#define BIFP0_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK                                     0x00000800L
+#define BIFP0_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK                                                  0x00001000L
+#define BIFP0_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK                                               0x00002000L
+#define BIFP0_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK                                              0x00004000L
+#define BIFP0_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK                                                  0x00008000L
+#define BIFP0_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK                                  0x00010000L
+#define BIFP0_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK                                0x00020000L
+#define BIFP0_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK                              0x00040000L
+#define BIFP0_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK                                            0x00080000L
+#define BIFP0_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK                                                   0x00100000L
+#define BIFP0_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK                                            0x00200000L
+#define BIFP0_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK                                               0x00400000L
+#define BIFP0_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK                                              0x00800000L
+#define BIFP0_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK                                              0x80000000L
+//BIFP0_PCIE_LC_SAVE_RESTORE_1
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT                                               0x0
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT                                        0x1
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT                                            0x2
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT                                      0xa
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT                                             0xb
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT                                  0xc
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT                                    0xd
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT                                           0xe
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT                                          0x10
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK                                                 0x00000001L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK                                          0x00000002L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK                                              0x000003FCL
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK                                        0x00000400L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK                                               0x00000800L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK                                    0x00001000L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK                                      0x00002000L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK                                             0x0000C000L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK                                            0xFFFF0000L
+//BIFP0_PCIE_LC_SAVE_RESTORE_2
+#define BIFP0_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT                                          0x0
+#define BIFP0_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK                                            0xFFFFFFFFL
+//BIFP0_PCIE_LC_SAVE_RESTORE_3
+#define BIFP0_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT                                0x0
+#define BIFP0_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK                                  0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp1_pciedir_p
+//BIFP1_PCIEP_RESERVED
+#define BIFP1_PCIEP_RESERVED__RESERVED__SHIFT                                                                 0x0
+#define BIFP1_PCIEP_RESERVED__RESERVED_MASK                                                                   0xFFFFFFFFL
+//BIFP1_PCIEP_SCRATCH
+#define BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT                                                             0x0
+#define BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK                                                               0xFFFFFFFFL
+//BIFP1_PCIEP_PORT_CNTL
+#define BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT                                                         0x0
+#define BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT                                                       0x1
+#define BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT                                                          0x2
+#define BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT                                                           0x3
+#define BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT                                                            0x4
+#define BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT                                                              0x5
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT                                         0x8
+#define BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT                                            0x12
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT                                             0x18
+#define BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT                                            0x1a
+#define BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK                                                           0x00000001L
+#define BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK                                                         0x00000002L
+#define BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK                                                            0x00000004L
+#define BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK                                                             0x00000008L
+#define BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK                                                              0x00000010L
+#define BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK                                                                0x00000020L
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK                                           0x0003FF00L
+#define BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK                                              0x001C0000L
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK                                               0x03000000L
+#define BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK                                              0x0C000000L
+//BIFP1_PCIE_TX_CNTL
+#define BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                            0xa
+#define BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                             0xc
+#define BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT                                                         0xe
+#define BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT                                                           0xf
+#define BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT                                                              0x14
+#define BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT                                                               0x15
+#define BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT                                                     0x16
+#define BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT                                                   0x17
+#define BIFP1_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT                                              0x1b
+#define BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                              0x00000C00L
+#define BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                               0x00003000L
+#define BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK                                                           0x00004000L
+#define BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK                                                             0x00008000L
+#define BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK                                                                0x00100000L
+#define BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK                                                                 0x00200000L
+#define BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK                                                       0x00400000L
+#define BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK                                                     0x00800000L
+#define BIFP1_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK                                                0x08000000L
+//BIFP1_PCIE_TX_REQUESTER_ID
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                           0x0
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                             0x3
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                                0x8
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                             0x00000007L
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                               0x000000F8L
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                                  0x0000FF00L
+//BIFP1_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT                                                  0x18
+#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK                                                    0x01000000L
+//BIFP1_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT                                          0x18
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT                                   0x1e
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT                                       0x1f
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK                                            0x3F000000L
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK                                     0x40000000L
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK                                         0x80000000L
+//BIFP1_PCIE_TX_SEQ
+#define BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT                                                        0x0
+#define BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT                                                                 0x10
+#define BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK                                                          0x00000FFFL
+#define BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK                                                                   0x0FFF0000L
+//BIFP1_PCIE_TX_REPLAY
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT                                                            0x0
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT                                                      0xe
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT                                                0xf
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT                                                          0x10
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK                                                              0x00000007L
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK                                                        0x00004000L
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK                                                  0x00008000L
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK                                                            0xFFFF0000L
+//BIFP1_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT                                          0x0
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT                                0xc
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK                                            0x00000FFFL
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK                                  0x00001000L
+//BIFP1_PCIE_TX_NOP_DLLP
+#define BIFP1_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT                                                            0x0
+#define BIFP1_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT                                                            0x18
+#define BIFP1_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK                                                              0x00FFFFFFL
+#define BIFP1_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK                                                              0x01000000L
+//BIFP1_PCIE_TX_CNTL_2
+//BIFP1_PCIE_TX_SKID_CTRL
+#define BIFP1_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT                                                  0x0
+#define BIFP1_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT                                            0x4
+#define BIFP1_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK                                                    0x0000000FL
+#define BIFP1_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK                                              0x00000010L
+//BIFP1_PCIE_TX_CREDITS_ADVT_P
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT                                               0x0
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT                                               0x10
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK                                                 0x00003FFFL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK                                                 0x03FF0000L
+//BIFP1_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT                                             0x0
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT                                             0x10
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK                                               0x00003FFFL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK                                               0x03FF0000L
+//BIFP1_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT                                           0x0
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT                                           0x10
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK                                             0x00003FFFL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK                                             0x03FF0000L
+//BIFP1_PCIE_TX_CREDITS_INIT_P
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT                                               0x0
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT                                               0x10
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK                                                 0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK                                                 0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_INIT_NP
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT                                             0x0
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT                                             0x10
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK                                               0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK                                               0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT                                           0x0
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT                                           0x10
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK                                             0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK                                             0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_STATUS
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT                                                0x0
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT                                                0x1
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT                                               0x2
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT                                               0x3
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT                                              0x4
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT                                              0x5
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT                                         0x10
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT                                         0x11
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT                                        0x12
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT                                        0x13
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT                                       0x14
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT                                       0x15
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK                                                  0x00000001L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK                                                  0x00000002L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK                                                 0x00000004L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK                                                 0x00000008L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK                                                0x00000010L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK                                                0x00000020L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK                                           0x00010000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK                                           0x00020000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK                                          0x00040000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK                                          0x00080000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK                                         0x00100000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK                                         0x00200000L
+//BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT                                    0x0
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT                                   0x4
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT                                  0x8
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT                                    0x10
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT                                   0x14
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT                                  0x18
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK                                      0x00000007L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK                                     0x00000070L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK                                    0x00000700L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK                                      0x00070000L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK                                     0x00700000L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK                                    0x07000000L
+//BIFP1_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT                                          0x0
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT                                                  0x3
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT                                           0x6
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT                                                   0x8
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT                                                   0x10
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT                                       0x19
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT                                              0x1c
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK                                            0x00000007L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK                                                    0x00000038L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK                                             0x00000040L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK                                                     0x00003F00L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK                                                     0x003F0000L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK                                         0x02000000L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK                                                0xF0000000L
+//BIFP1_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT                                      0x0
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK                                        0x0000FFFFL
+//BIFP1_PCIE_CCIX_STACKED_BASE
+#define BIFP1_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT                                           0x4
+#define BIFP1_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK                                             0xFFFFFFF0L
+//BIFP1_PCIE_CCIX_STACKED_LIMIT
+#define BIFP1_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT                                         0x4
+#define BIFP1_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK                                           0xFFFFFFF0L
+//BIFP1_PCIE_CCIX_MISC_STATUS
+#define BIFP1_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT                                              0x0
+#define BIFP1_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT                                          0x1
+#define BIFP1_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK                                                0x00000001L
+#define BIFP1_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK                                            0x00000002L
+//BIFP1_PCIE_P_PORT_LANE_STATUS
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT                                              0x0
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT                                                  0x1
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK                                                0x00000001L
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK                                                    0x0000007EL
+//BIFP1_PCIE_FC_P
+#define BIFP1_PCIE_FC_P__PD_CREDITS__SHIFT                                                                    0x0
+#define BIFP1_PCIE_FC_P__PH_CREDITS__SHIFT                                                                    0x10
+#define BIFP1_PCIE_FC_P__PD_CREDITS_MASK                                                                      0x0000FFFFL
+#define BIFP1_PCIE_FC_P__PH_CREDITS_MASK                                                                      0x0FFF0000L
+//BIFP1_PCIE_FC_NP
+#define BIFP1_PCIE_FC_NP__NPD_CREDITS__SHIFT                                                                  0x0
+#define BIFP1_PCIE_FC_NP__NPH_CREDITS__SHIFT                                                                  0x10
+#define BIFP1_PCIE_FC_NP__NPD_CREDITS_MASK                                                                    0x0000FFFFL
+#define BIFP1_PCIE_FC_NP__NPH_CREDITS_MASK                                                                    0x0FFF0000L
+//BIFP1_PCIE_FC_CPL
+#define BIFP1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT                                                                0x0
+#define BIFP1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT                                                                0x10
+#define BIFP1_PCIE_FC_CPL__CPLD_CREDITS_MASK                                                                  0x0000FFFFL
+#define BIFP1_PCIE_FC_CPL__CPLH_CREDITS_MASK                                                                  0x0FFF0000L
+//BIFP1_PCIE_FC_P_VC1
+#define BIFP1_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT                                                    0x0
+#define BIFP1_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT                                                    0x10
+#define BIFP1_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK                                                      0x0000FFFFL
+#define BIFP1_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK                                                      0x0FFF0000L
+//BIFP1_PCIE_FC_NP_VC1
+#define BIFP1_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT                                                  0x0
+#define BIFP1_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT                                                  0x10
+#define BIFP1_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK                                                    0x0000FFFFL
+#define BIFP1_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK                                                    0x0FFF0000L
+//BIFP1_PCIE_FC_CPL_VC1
+#define BIFP1_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT                                                0x0
+#define BIFP1_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT                                                0x10
+#define BIFP1_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK                                                  0x0000FFFFL
+#define BIFP1_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK                                                  0x0FFF0000L
+//BIFP1_PCIE_ERR_CNTL
+#define BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                         0x0
+#define BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT                                                  0x1
+#define BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT                                                     0x2
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT                                                      0x4
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT                                                      0x5
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT                                                      0x6
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT                                                      0x7
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                                       0x8
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                              0xb
+#define BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT                                               0xe
+#define BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT                                              0xf
+#define BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT                                                     0x10
+#define BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                                  0x11
+#define BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                                          0x12
+#define BIFP1_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT                                                    0x13
+#define BIFP1_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT                                                     0x14
+#define BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                           0x00000001L
+#define BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK                                                    0x00000002L
+#define BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK                                                       0x00000004L
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK                                                        0x00000010L
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK                                                        0x00000020L
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK                                                        0x00000040L
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK                                                        0x00000080L
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                         0x00000700L
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                                0x00000800L
+#define BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK                                                 0x00004000L
+#define BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK                                                0x00008000L
+#define BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK                                                       0x00010000L
+#define BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                                    0x00020000L
+#define BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                            0x00040000L
+#define BIFP1_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK                                                      0x00080000L
+#define BIFP1_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK                                                       0x00100000L
+//BIFP1_PCIE_RX_CNTL
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT                                                           0x0
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT                                                           0x1
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT                                                          0x2
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT                                                          0x3
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT                                                          0x4
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT                                                          0x5
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT                                                           0x6
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT                                                 0x7
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                                  0x8
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                           0x9
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT                                                           0xa
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT                                                            0xb
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT                                                           0xc
+#define BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT                                                        0xd
+#define BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT                                                        0xf
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT                                                         0x10
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT                                                    0x13
+#define BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                                    0x14
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                                  0x15
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                                    0x16
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT                                                    0x17
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                                 0x18
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                                     0x19
+#define BIFP1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                                 0x1a
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                                     0x1b
+#define BIFP1_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT                                                              0x1c
+#define BIFP1_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT                                                0x1d
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK                                                             0x00000001L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK                                                             0x00000002L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK                                                            0x00000004L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK                                                            0x00000008L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK                                                            0x00000010L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK                                                            0x00000020L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK                                                             0x00000040L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK                                                   0x00000080L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                                    0x00000100L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                             0x00000200L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK                                                             0x00000400L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK                                                              0x00000800L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK                                                             0x00001000L
+#define BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK                                                          0x00002000L
+#define BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK                                                          0x00008000L
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK                                                           0x00070000L
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK                                                      0x00080000L
+#define BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                                      0x00100000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                                    0x00200000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                                      0x00400000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK                                                      0x00800000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                                   0x01000000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                                       0x02000000L
+#define BIFP1_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                                   0x04000000L
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                                       0x08000000L
+#define BIFP1_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK                                                                0x10000000L
+#define BIFP1_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK                                                  0x20000000L
+//BIFP1_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT                                              0x0
+#define BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK                                                0x00000FFFL
+//BIFP1_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT                                                0x18
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK                                                  0x01000000L
+//BIFP1_PCIE_RX_CNTL3
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT                                             0x0
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT                                             0x1
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT                                                0x2
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT                                                    0x3
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT                                               0x4
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK                                               0x00000001L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK                                               0x00000002L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK                                                  0x00000004L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK                                                      0x00000008L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK                                                 0x00000010L
+//BIFP1_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT                                     0x0
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT                                     0x10
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK                                       0x00000FFFL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK                                       0x00FF0000L
+//BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT                                   0x0
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT                                   0x10
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK                                     0x00000FFFL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK                                     0x00FF0000L
+//BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT                                 0x0
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT                                 0x10
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK                                   0x00000FFFL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK                                   0x00FF0000L
+//BIFP1_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT                                    0x0
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT                                 0x2
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT                           0x4
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT                             0x6
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT                              0x8
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT                              0xa
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT                                  0xc
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT                         0xe
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT                            0x10
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT                                0x12
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT                           0x14
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT                             0x16
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK                                      0x00000003L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK                                   0x0000000CL
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK                             0x00000030L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK                               0x000000C0L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK                                0x00000300L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK                                0x00000C00L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK                                    0x00003000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK                           0x0000C000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK                              0x00030000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK                                  0x000C0000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK                             0x00300000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK                               0x00C00000L
+//BIFP1_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT                             0x0
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT                      0x2
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT                                 0x4
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT                                  0x6
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT                          0x8
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT                               0xa
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT                            0xc
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT                         0xe
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT                          0x10
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT                       0x12
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK                               0x00000003L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK                        0x0000000CL
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK                                   0x00000030L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK                                    0x000000C0L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK                            0x00000300L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK                                 0x00000C00L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK                              0x00003000L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK                           0x0000C000L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK                            0x00030000L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK                         0x000C0000L
+//BIFP1_PCIEP_NAK_COUNTER
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT                                              0x0
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT                                             0x10
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK                                                0x0000FFFFL
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK                                               0xFFFF0000L
+//BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT                     0x0
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT                     0xa
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT                      0xf
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT                  0x10
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT                  0x1a
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT                   0x1f
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK                       0x000003FFL
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK                       0x00001C00L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK                        0x00008000L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK                    0x03FF0000L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK                    0x1C000000L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK                     0x80000000L
+//BIFP1_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP1_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT                                    0x5
+#define BIFP1_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK                                      0x00000020L
+//BIFP1_PCIE_AER_PRIV_TRIGGER
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT                          0x0
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT                           0x1
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT                         0x2
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK                            0x00000001L
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK                             0x00000002L
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK                           0x00000004L
+//BIFP1_PCIE_LC_CNTL
+#define BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT                                                    0x1
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT                                                   0x2
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT                                                              0x3
+#define BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT                                                       0x4
+#define BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT                                                          0x8
+#define BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT                                                           0xc
+#define BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT                                                           0x10
+#define BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT                                                            0x11
+#define BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT                                                  0x12
+#define BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT                                                      0x14
+#define BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT                                                     0x15
+#define BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT                                                           0x16
+#define BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT                                                        0x17
+#define BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT                                                          0x18
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT                                                             0x19
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT                                                          0x1b
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT                                                           0x1c
+#define BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT                                                 0x1d
+#define BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT                                                         0x1e
+#define BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT                                                          0x1f
+#define BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK                                                      0x00000002L
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK                                                     0x00000004L
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_LINK_MASK                                                                0x00000008L
+#define BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK                                                         0x000000F0L
+#define BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK                                                            0x00000F00L
+#define BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK                                                             0x0000F000L
+#define BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK                                                             0x00010000L
+#define BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK                                                              0x00020000L
+#define BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK                                                    0x000C0000L
+#define BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK                                                        0x00100000L
+#define BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK                                                       0x00200000L
+#define BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK                                                             0x00400000L
+#define BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK                                                          0x00800000L
+#define BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK                                                            0x01000000L
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK                                                               0x06000000L
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK                                                            0x08000000L
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK                                                             0x10000000L
+#define BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK                                                   0x20000000L
+#define BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK                                                           0x40000000L
+#define BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK                                                            0x80000000L
+//BIFP1_PCIE_LC_TRAINING_CNTL
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT                                                  0x0
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT                                             0x4
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT                                 0x5
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT                                        0x6
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT                                            0x7
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT                                                    0x8
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT                                     0xb
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT                                       0xc
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT                                      0xd
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT                                          0xe
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT                                        0xf
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT                                            0x10
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT                                          0x11
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT                                            0x12
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT                                                 0x13
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT                                                 0x14
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT                                        0x15
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT                                          0x16
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT                                 0x18
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT                                    0x19
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT                                        0x1a
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT                                             0x1b
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT                                            0x1c
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT                                 0x1d
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT                                             0x1e
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK                                                    0x0000000FL
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK                                               0x00000010L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK                                   0x00000020L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK                                          0x00000040L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK                                              0x00000080L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK                                                      0x00000700L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK                                       0x00000800L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK                                         0x00001000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK                                        0x00002000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK                                            0x00004000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK                                          0x00008000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK                                              0x00010000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK                                            0x00020000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK                                              0x00040000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK                                                   0x00080000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK                                                   0x00100000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK                                          0x00200000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK                                            0x00C00000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK                                   0x01000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK                                      0x02000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK                                          0x04000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK                                               0x08000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK                                              0x10000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK                                   0x20000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK                                               0xC0000000L
+//BIFP1_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT                                                   0x0
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT                                                0x4
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT                                  0x7
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT                                                 0x8
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT                                        0x9
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT                                               0xa
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT                                            0xb
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT                                          0xc
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT                                              0xd
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT                                      0xe
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT                                              0xf
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT                                               0x11
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT                                               0x12
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT                                         0x13
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT                                          0x14
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT                                          0x15
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT                                         0x17
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT                                       0x18
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT                                  0x19
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT                                    0x1a
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT                                0x1b
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT                                0x1c
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT                                     0x1d
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT                                        0x1e
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT                                      0x1f
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK                                                     0x00000007L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK                                                  0x00000070L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK                                    0x00000080L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK                                                   0x00000100L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK                                          0x00000200L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK                                                 0x00000400L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK                                              0x00000800L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK                                            0x00001000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK                                                0x00002000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK                                        0x00004000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK                                                0x00008000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK                                                 0x00020000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK                                                 0x00040000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK                                           0x00080000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK                                            0x00100000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK                                            0x00600000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK                                           0x00800000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK                                         0x01000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK                                    0x02000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK                                      0x04000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK                                  0x08000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK                                  0x10000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK                                       0x20000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK                                          0x40000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK                                        0x80000000L
+//BIFP1_PCIE_LC_N_FTS_CNTL
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT                                                        0x0
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT                                            0x8
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT                                          0x9
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT                                                         0xa
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT                                               0xe
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT                                              0xf
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT                                                  0x10
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT                                                             0x18
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK                                                          0x000000FFL
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK                                              0x00000100L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK                                            0x00000200L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK                                                           0x00000400L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK                                                 0x00004000L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK                                                0x00008000L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK                                                    0x00FF0000L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK                                                               0xFF000000L
+//BIFP1_PCIE_LC_SPEED_CNTL
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                                     0x0
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                                     0x1
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                                     0x2
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT                                     0x3
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT                                        0x4
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT                                          0x6
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT                                         0x7
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT                                          0x8
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT                                         0x9
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT                                        0xa
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0xb
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0xd
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT                                                 0xe
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT                                 0x10
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT                                         0x11
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT                                        0x12
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT                                         0x13
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT                                          0x14
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT                                         0x15
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT                                          0x16
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT                                         0x17
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT                                          0x18
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT                                               0x19
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT                                              0x1a
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT                                                   0x1c
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT                                    0x1d
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT                                          0x1e
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT                                           0x1f
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                                       0x00000001L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                                       0x00000002L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                                       0x00000004L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK                                       0x00000008L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK                                          0x00000030L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK                                            0x00000040L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK                                           0x00000080L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK                                            0x00000100L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK                                           0x00000200L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK                                          0x00000400L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x00001800L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00002000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK                                                   0x0000C000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK                                   0x00010000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK                                           0x00020000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK                                          0x00040000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK                                           0x00080000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK                                            0x00100000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK                                           0x00200000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK                                            0x00400000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK                                           0x00800000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK                                            0x01000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK                                                 0x02000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK                                                0x0C000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK                                                     0x10000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK                                      0x20000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK                                            0x40000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK                                             0x80000000L
+//BIFP1_PCIE_LC_STATE0
+#define BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT                                                         0x0
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT                                                           0x8
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT                                                           0x10
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT                                                           0x18
+#define BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK                                                           0x0000003FL
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK                                                             0x00003F00L
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK                                                             0x003F0000L
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK                                                             0x3F000000L
+//BIFP1_PCIE_LC_STATE1
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT                                                           0x0
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT                                                           0x8
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT                                                           0x10
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT                                                           0x18
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK                                                             0x0000003FL
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK                                                             0x00003F00L
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK                                                             0x003F0000L
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK                                                             0x3F000000L
+//BIFP1_PCIE_LC_STATE2
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT                                                           0x0
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT                                                           0x8
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT                                                          0x10
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT                                                          0x18
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK                                                             0x0000003FL
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK                                                             0x00003F00L
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK                                                            0x003F0000L
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK                                                            0x3F000000L
+//BIFP1_PCIE_LC_STATE3
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT                                                          0x0
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT                                                          0x8
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT                                                          0x10
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT                                                          0x18
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK                                                            0x0000003FL
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK                                                            0x00003F00L
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK                                                            0x003F0000L
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK                                                            0x3F000000L
+//BIFP1_PCIE_LC_STATE4
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT                                                          0x0
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT                                                          0x8
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT                                                          0x10
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT                                                          0x18
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK                                                            0x0000003FL
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK                                                            0x00003F00L
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK                                                            0x003F0000L
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK                                                            0x3F000000L
+//BIFP1_PCIE_LC_STATE5
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT                                                          0x0
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT                                                          0x8
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT                                                          0x10
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT                                                          0x18
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK                                                            0x0000003FL
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK                                                            0x00003F00L
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK                                                            0x003F0000L
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK                                                            0x3F000000L
+//BIFP1_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT                                                 0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT                                                 0x1
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT                                                  0x2
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT                                                  0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT                                                 0x4
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT                                                0x5
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT                                                0x6
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT                                          0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT                                         0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT                                          0xf
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT                                         0x13
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT                                          0x17
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT                                         0x1b
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK                                                   0x00000001L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK                                                   0x00000002L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK                                                    0x00000004L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK                                                    0x00000008L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK                                                   0x00000010L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK                                                  0x00000020L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK                                                  0x00000040L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK                                            0x00000780L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK                                           0x00007800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK                                            0x00078000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK                                           0x00780000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK                                            0x07800000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK                                           0x78000000L
+//BIFP1_PCIE_LC_CNTL2
+#define BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT                                                        0x0
+#define BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT                                                        0x6
+#define BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT                                                  0x7
+#define BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT                                                            0x8
+#define BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT                                                    0x9
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT                                                    0xa
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT                                                          0xb
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT                                               0xc
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT                                              0xd
+#define BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT                                                         0xe
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT                                         0x10
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT                                                       0x11
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT                                                      0x12
+#define BIFP1_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT                                              0x13
+#define BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT                                                    0x14
+#define BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT                                                  0x15
+#define BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT                                            0x16
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT                                               0x17
+#define BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT                                                 0x19
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT                                             0x1a
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                               0x1b
+#define BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT                                               0x1c
+#define BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT                                                         0x1d
+#define BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT                                       0x1f
+#define BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK                                                          0x0000003FL
+#define BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK                                                          0x00000040L
+#define BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK                                                    0x00000080L
+#define BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK                                                              0x00000100L
+#define BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK                                                      0x00000200L
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK                                                      0x00000400L
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK                                                            0x00000800L
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK                                                 0x00001000L
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK                                                0x00002000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK                                                           0x0000C000L
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK                                           0x00010000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK                                                         0x00020000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK                                                        0x00040000L
+#define BIFP1_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK                                                0x00080000L
+#define BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK                                                      0x00100000L
+#define BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK                                                    0x00200000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK                                              0x00400000L
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK                                                 0x01800000L
+#define BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK                                                   0x02000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK                                               0x04000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                                 0x08000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK                                                 0x10000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK                                                           0x60000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK                                         0x80000000L
+//BIFP1_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT                                              0x0
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT                                          0x1
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT                                          0x2
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT                                       0x3
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT                                      0x4
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT                                              0x5
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT                                                0x6
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT                                               0x7
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT                                               0x8
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT                                              0x9
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT                              0xa
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT                                        0xb
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK                                                0x00000001L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK                                            0x00000002L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK                                            0x00000004L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK                                         0x00000008L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK                                        0x00000010L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK                                                0x00000020L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK                                                  0x00000040L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK                                                 0x00000080L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK                                                 0x00000100L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK                                                0x00000200L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK                                0x00000400L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK                                          0x00000800L
+//BIFP1_PCIE_LC_CDR_CNTL
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT                                                        0x0
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT                                                       0xc
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT                                                        0x18
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK                                                          0x00000FFFL
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK                                                         0x00FFF000L
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK                                                          0x03000000L
+//BIFP1_PCIE_LC_LANE_CNTL
+#define BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT                                                    0x0
+#define BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK                                                      0x0000FFFFL
+//BIFP1_PCIE_LC_CNTL3
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT                                                      0x0
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT                                                 0x1
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT                                                        0x3
+#define BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT                                                         0x4
+#define BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT                                              0x5
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0x6
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0x8
+#define BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT                                         0x9
+#define BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT                                                   0xa
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT                                                   0xb
+#define BIFP1_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT                                                   0xc
+#define BIFP1_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT                                         0xd
+#define BIFP1_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT                                         0xe
+#define BIFP1_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT                                    0xf
+#define BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT                                                   0x11
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT                                          0x12
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT                                0x13
+#define BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT                                                  0x15
+#define BIFP1_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT                             0x16
+#define BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT                                       0x17
+#define BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT                                                  0x18
+#define BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT                                                      0x1a
+#define BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT                                                         0x1e
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT                                                      0x1f
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK                                                        0x00000001L
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK                                                   0x00000006L
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK                                                          0x00000008L
+#define BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK                                                           0x00000010L
+#define BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK                                                0x00000020L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x000000C0L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00000100L
+#define BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK                                           0x00000200L
+#define BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK                                                     0x00000400L
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK                                                     0x00000800L
+#define BIFP1_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK                                                     0x00001000L
+#define BIFP1_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK                                           0x00002000L
+#define BIFP1_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK                                           0x00004000L
+#define BIFP1_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK                                      0x00008000L
+#define BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK                                                     0x00020000L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK                                            0x00040000L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK                                  0x00180000L
+#define BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK                                                    0x00200000L
+#define BIFP1_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK                               0x00400000L
+#define BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK                                         0x00800000L
+#define BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK                                                    0x03000000L
+#define BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK                                                        0x3C000000L
+#define BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK                                                           0x40000000L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK                                                        0x80000000L
+//BIFP1_PCIE_LC_CNTL4
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT                                                    0x0
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT                                               0x2
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT                                            0x3
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT                                                          0x4
+#define BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT                                                            0x5
+#define BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT                                                           0x6
+#define BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT                                                          0x7
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT                                                     0x8
+#define BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT                                              0xa
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT                                                    0xb
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT                                                       0xc
+#define BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT                                                            0xd
+#define BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT                                                           0xe
+#define BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT                                             0xf
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT                                                0x10
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT                                       0x11
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT                                                 0x12
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT                                                        0x16
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT                                                               0x17
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT                                                  0x18
+#define BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT                                                      0x19
+#define BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT                                              0x1a
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK                                                      0x00000003L
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK                                                 0x00000004L
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK                                              0x00000008L
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK                                                            0x00000010L
+#define BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK                                                              0x00000020L
+#define BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK                                                             0x00000040L
+#define BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK                                                            0x00000080L
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK                                                       0x00000300L
+#define BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK                                                0x00000400L
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK                                                      0x00000800L
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK                                                         0x00001000L
+#define BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK                                                              0x00002000L
+#define BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK                                                             0x00004000L
+#define BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK                                               0x00008000L
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK                                                  0x00010000L
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK                                         0x00020000L
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK                                                   0x003C0000L
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK                                                          0x00400000L
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_SWING_MASK                                                                 0x00800000L
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK                                                    0x01000000L
+#define BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK                                                        0x02000000L
+#define BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK                                                0xFC000000L
+//BIFP1_PCIE_LC_CNTL5
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT                                                 0x0
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT                                                           0x2
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT                                                       0x6
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT                                                           0xa
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT                                                      0x10
+#define BIFP1_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT                                      0x15
+#define BIFP1_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT                                                      0x16
+#define BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT                                        0x18
+#define BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT                                                      0x19
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT                                                     0x1a
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT                                                0x1b
+#define BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT                                                         0x1c
+#define BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT                                                     0x1d
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK                                                   0x00000003L
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK                                                             0x0000003CL
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK                                                         0x000003C0L
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK                                                             0x0000FC00L
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK                                                        0x001F0000L
+#define BIFP1_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK                                        0x00200000L
+#define BIFP1_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK                                                        0x00C00000L
+#define BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK                                          0x01000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK                                                        0x02000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK                                                       0x04000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK                                                  0x08000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK                                                           0x10000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK                                                       0xE0000000L
+//BIFP1_PCIE_LC_FORCE_COEFF
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT                                                  0x0
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT                                             0x1
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT                                                 0x7
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT                                            0xd
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT                                          0x13
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT                                                     0x14
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK                                                    0x00000001L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK                                               0x0000007EL
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK                                                   0x00001F80L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK                                              0x0007E000L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK                                            0x00080000L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK                                                       0x00100000L
+//BIFP1_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT                                                 0x0
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT                                              0x4
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT                                                 0xa
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT                                             0x10
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT                                                    0x16
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT                                          0x1e
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK                                                   0x0000000FL
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK                                                0x000003F0L
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK                                                   0x0000FC00L
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK                                               0x003F0000L
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK                                                      0x3FC00000L
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK                                            0x40000000L
+//BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT                           0x0
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT                                  0x1
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT                                      0x7
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT                                 0xd
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT                                          0x13
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT                                          0x19
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK                             0x00000001L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK                                    0x0000007EL
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK                                        0x00001F80L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK                                   0x0007E000L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK                                            0x01F80000L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK                                            0x7E000000L
+//BIFP1_PCIE_LC_CNTL6
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT                                                         0x0
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT                                                           0x2
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT                                                           0x4
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT                                                          0x6
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT                                                                0x8
+#define BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT                                                      0x9
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT                                                     0xd
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT                                                 0xe
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT                                                   0x10
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT                                           0x12
+#define BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT                                                0x13
+#define BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT                                                     0x14
+#define BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT                                                           0x15
+#define BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT                                                               0x16
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT                                                           0x17
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT                                                      0x18
+#define BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT                                                      0x1f
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK                                                           0x00000003L
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK                                                             0x0000000CL
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK                                                             0x00000030L
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK                                                            0x000000C0L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN_MASK                                                                  0x00000100L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK                                                        0x00001E00L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK                                                       0x00002000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK                                                   0x0000C000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK                                                     0x00030000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK                                             0x00040000L
+#define BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK                                                  0x00080000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK                                                       0x00100000L
+#define BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK                                                             0x00200000L
+#define BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK                                                                 0x00400000L
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK                                                             0x00800000L
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK                                                        0x7F000000L
+#define BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK                                                        0x80000000L
+//BIFP1_PCIE_LC_CNTL7
+#define BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT                                              0x0
+#define BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT                                         0x1
+#define BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT                                             0x2
+#define BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT                                                   0x3
+#define BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT                                                     0x4
+#define BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT                                            0x5
+#define BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT                                                          0x6
+#define BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT                                                0x7
+#define BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT                                                     0x8
+#define BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT                                              0x9
+#define BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT                                               0xa
+#define BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT                                             0xb
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT                                          0xc
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT                                            0xd
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT                                                0x15
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT                                         0x16
+#define BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT                                                     0x17
+#define BIFP1_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT                                              0x18
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT                                                              0x19
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT                                                     0x1b
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT                                                      0x1c
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT                                                          0x1d
+#define BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT                                                          0x1e
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT                                                         0x1f
+#define BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK                                                0x00000001L
+#define BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK                                           0x00000002L
+#define BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK                                               0x00000004L
+#define BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK                                                     0x00000008L
+#define BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK                                                       0x00000010L
+#define BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK                                              0x00000020L
+#define BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK                                                            0x00000040L
+#define BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK                                                  0x00000080L
+#define BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK                                                       0x00000100L
+#define BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK                                                0x00000200L
+#define BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK                                                 0x00000400L
+#define BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK                                               0x00000800L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK                                            0x00001000L
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK                                              0x001FE000L
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK                                                  0x00200000L
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK                                           0x00400000L
+#define BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK                                                       0x00800000L
+#define BIFP1_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK                                                0x01000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_RATES_MASK                                                                0x06000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK                                                       0x08000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK                                                        0x10000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK                                                            0x20000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK                                                            0x40000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK                                                           0x80000000L
+//BIFP1_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT                                           0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                            0x1
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT                           0x2
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT                                           0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT                            0x4
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT                           0x5
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT                                 0x6
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT                                            0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT                                     0x8
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT                                         0x9
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT                                        0xa
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT                                    0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT                                    0xc
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT                                  0xd
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK                                             0x00000001L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK                              0x00000002L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK                             0x00000004L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK                                             0x00000008L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK                              0x00000010L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK                             0x00000020L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK                                   0x00000040L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK                                              0x00000080L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK                                       0x00000100L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK                                           0x00000200L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK                                          0x00000400L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK                                      0x00000800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK                                      0x00001000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK                                    0x00002000L
+//BIFP1_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT                                        0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x1
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT                        0x2
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT                                        0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x4
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT                        0x5
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT                              0x6
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT                                         0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT                                  0x8
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT                                      0x9
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT                                     0xa
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT                                 0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT                                 0xc
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT                               0xd
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK                                          0x00000001L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000002L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK                          0x00000004L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK                                          0x00000008L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000010L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK                          0x00000020L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK                                0x00000040L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK                                           0x00000080L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK                                    0x00000100L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK                                        0x00000200L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK                                       0x00000400L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK                                   0x00000800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK                                   0x00001000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK                                 0x00002000L
+//BIFP1_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT                                         0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT                                              0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT                                         0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT                                                       0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT                                             0xc
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT                                                      0xd
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT                                                    0xf
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT                                                   0x11
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT                                                  0x12
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT                                              0x13
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT                                             0x17
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT                                                 0x1b
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT                                               0x1e
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT                                              0x1f
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK                                           0x00000007L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK                                                0x00000078L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK                                           0x00000780L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK                                                         0x00000800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK                                               0x00001000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK                                                        0x00006000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK                                                      0x00018000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK                                                     0x00020000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK                                                    0x00040000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK                                                0x00780000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK                                               0x07800000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK                                                   0x38000000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK                                                 0x40000000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK                                                0x80000000L
+//BIFP1_PCIEP_STRAP_LC
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT                                                     0x0
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT                                                    0x2
+#define BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT                                                     0x4
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT                                                   0x6
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT                                                      0x8
+#define BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT                                                    0xb
+#define BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT                                                     0xc
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT                                                   0xd
+#define BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT                                                   0xe
+#define BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT                                      0xf
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT                                                   0x10
+#define BIFP1_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                            0x13
+#define BIFP1_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT                                             0x14
+#define BIFP1_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT                                             0x15
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK                                                       0x00000003L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK                                                      0x0000000CL
+#define BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK                                                       0x00000030L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK                                                     0x000000C0L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK                                                        0x00000700L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK                                                      0x00000800L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK                                                       0x00001000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK                                                     0x00002000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK                                                     0x00004000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK                                        0x00008000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK                                                     0x00070000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK                                              0x00080000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK                                               0x00100000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK                                               0x00200000L
+//BIFP1_PCIEP_STRAP_MISC
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT                                                    0x0
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT                                                    0x1
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT                                           0x2
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT                                                   0x3
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT                                                    0x5
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT                                                          0x6
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT                                         0x7
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK                                                      0x00000001L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK                                                      0x00000002L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK                                             0x00000004L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK                                                     0x00000018L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK                                                      0x00000020L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK                                                            0x00000040L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK                                           0x00000080L
+//BIFP1_PCIEP_STRAP_LC2
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT                                                0x0
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT                                             0x1
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT                                                  0x3
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT                                                    0x4
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT                                              0x7
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK                                                  0x00000001L
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK                                               0x00000006L
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK                                                    0x00000008L
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK                                                      0x00000070L
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK                                                0x00000380L
+//BIFP1_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT                                      0x0
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT                                          0x1
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT                                          0x2
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT                                            0x3
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT                                            0x4
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT                                              0x5
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT                                              0x6
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT                                              0x8
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT                                                0x10
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT                                                0x14
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT                                               0x17
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT                                 0x1a
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT                                   0x1b
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT                          0x1c
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK                                        0x00000001L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK                                            0x00000002L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK                                            0x00000004L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK                                              0x00000008L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK                                              0x00000010L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK                                                0x00000020L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK                                                0x000000C0L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK                                                0x00001F00L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK                                                  0x00070000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK                                                  0x00700000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK                                                 0x03800000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK                                   0x04000000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK                                     0x08000000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK                            0x10000000L
+//BIFP1_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT                                              0x0
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT                                          0x8
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK                                                0x000000FFL
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK                                            0x00000700L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+//BIFP1_PCIE_LC_PORT_ORDER
+#define BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT                                                       0x0
+#define BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK                                                         0x0000000FL
+//BIFP1_PCIEP_BCH_ECC_CNTL
+#define BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT                                                     0x0
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT                                              0x8
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT                                                 0x10
+#define BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK                                                       0x00000001L
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK                                                0x0000FF00L
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK                                                   0xFFFF0000L
+//BIFP1_PCIEP_HPGI_PRIVATE
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT                                      0x3
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT                                        0x6
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK                                        0x00000008L
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK                                          0x00000040L
+//BIFP1_PCIEP_HPGI
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT                                                    0x0
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT                                                    0x1
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT                                                  0x2
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT                                                  0x3
+#define BIFP1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT                                                                0x7
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT                                                0x8
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT                                                0x9
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT                                              0xa
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT                                              0xb
+#define BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT                                 0xf
+#define BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT                                     0x10
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK                                                      0x00000001L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK                                                      0x00000002L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK                                                    0x00000004L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK                                                    0x00000008L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_HOOK_MASK                                                                  0x00000080L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK                                                  0x00000100L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK                                                  0x00000200L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK                                                0x00000400L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK                                                0x00000800L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK                                   0x00008000L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK                                       0x00010000L
+//BIFP1_PCIEP_HCNT_DESCRIPTOR
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT                                    0x0
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT                                 0x1f
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK                                      0x00001FFFL
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK                                   0x80000000L
+//BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT                                          0x0
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT                                        0x10
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK                                            0x0000FFFFL
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK                                          0x00FF0000L
+//BIFP1_PCIE_LC_CNTL8
+#define BIFP1_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT                                                    0x0
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT                                                         0x2
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT                                                  0x3
+#define BIFP1_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT                                                           0x7
+#define BIFP1_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT                                                   0x8
+#define BIFP1_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT                                                      0x9
+#define BIFP1_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT                                            0xa
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT                                               0xb
+#define BIFP1_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT                                      0xc
+#define BIFP1_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT                                                0xd
+#define BIFP1_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT                                                        0x11
+#define BIFP1_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT                                                           0x12
+#define BIFP1_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT                                                       0x16
+#define BIFP1_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT                                                               0x17
+#define BIFP1_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT                                                         0x19
+#define BIFP1_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT                                                0x1a
+#define BIFP1_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT                                                 0x1b
+#define BIFP1_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT                                                         0x1c
+#define BIFP1_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT                                                0x1d
+#define BIFP1_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT                                             0x1e
+#define BIFP1_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK                                                      0x00000003L
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK                                                           0x00000004L
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK                                                    0x00000078L
+#define BIFP1_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK                                                             0x00000080L
+#define BIFP1_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK                                                     0x00000100L
+#define BIFP1_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK                                                        0x00000200L
+#define BIFP1_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK                                              0x00000400L
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK                                                 0x00000800L
+#define BIFP1_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK                                        0x00001000L
+#define BIFP1_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK                                                  0x0001E000L
+#define BIFP1_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK                                                          0x00020000L
+#define BIFP1_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK                                                             0x003C0000L
+#define BIFP1_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK                                                         0x00400000L
+#define BIFP1_PCIE_LC_CNTL8__LC_FOM_TIME_MASK                                                                 0x01800000L
+#define BIFP1_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK                                                           0x02000000L
+#define BIFP1_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK                                                  0x04000000L
+#define BIFP1_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK                                                   0x08000000L
+#define BIFP1_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK                                                           0x10000000L
+#define BIFP1_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK                                                  0x20000000L
+#define BIFP1_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK                                               0xC0000000L
+//BIFP1_PCIE_LC_CNTL9
+#define BIFP1_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT                                           0x0
+#define BIFP1_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT                                              0x1
+#define BIFP1_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT                                                0x3
+#define BIFP1_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT                                                       0x4
+#define BIFP1_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT                                                 0x6
+#define BIFP1_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT                                                 0x8
+#define BIFP1_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT                            0xa
+#define BIFP1_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT                                                   0xb
+#define BIFP1_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT                                               0xc
+#define BIFP1_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT                                                    0xd
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT                                                 0xe
+#define BIFP1_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT                                                 0x18
+#define BIFP1_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT                                                0x19
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT                                                  0x1a
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT                                                 0x1b
+#define BIFP1_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT                                              0x1c
+#define BIFP1_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT                               0x1d
+#define BIFP1_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT                                      0x1e
+#define BIFP1_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT                                      0x1f
+#define BIFP1_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK                                             0x00000001L
+#define BIFP1_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK                                                0x00000006L
+#define BIFP1_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK                                                  0x00000008L
+#define BIFP1_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK                                                         0x00000030L
+#define BIFP1_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK                                                   0x000000C0L
+#define BIFP1_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK                                                   0x00000300L
+#define BIFP1_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK                              0x00000400L
+#define BIFP1_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK                                                     0x00000800L
+#define BIFP1_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK                                                 0x00001000L
+#define BIFP1_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK                                                      0x00002000L
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK                                                   0x00FFC000L
+#define BIFP1_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK                                                   0x01000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK                                                  0x02000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK                                                    0x04000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK                                                   0x08000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK                                                0x10000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK                                 0x20000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK                                        0x40000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK                                        0x80000000L
+//BIFP1_PCIE_LC_FORCE_COEFF2
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT                                                0x0
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT                                           0x1
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT                                               0x7
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT                                          0xd
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT                                        0x13
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK                                                  0x00000001L
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK                                             0x0000007EL
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK                                                 0x00001F80L
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK                                            0x0007E000L
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK                                          0x00080000L
+//BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT                         0x0
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT                                0x1
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT                                    0x7
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT                               0xd
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT                                        0x13
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT                                        0x19
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK                           0x00000001L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK                                  0x0000007EL
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK                                      0x00001F80L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK                                 0x0007E000L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK                                          0x01F80000L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK                                          0x7E000000L
+//BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT                                       0x0
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT                                     0x10
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK                                         0x0000FFFFL
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK                                       0x00FF0000L
+//BIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT             0x0
+#define BIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT               0x1
+#define BIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK               0x00000001L
+#define BIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK                 0x00000002L
+//BIFP1_PCIE_LC_CNTL10
+#define BIFP1_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT                      0x0
+#define BIFP1_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT                                         0x1
+#define BIFP1_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT                                             0x2
+#define BIFP1_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT                                            0x4
+#define BIFP1_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT                                                       0x6
+#define BIFP1_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT                                                      0x10
+#define BIFP1_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT                                     0x1a
+#define BIFP1_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT                                                0x1b
+#define BIFP1_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT                                              0x1d
+#define BIFP1_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT                                 0x1e
+#define BIFP1_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT                                 0x1f
+#define BIFP1_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK                        0x00000001L
+#define BIFP1_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK                                           0x00000002L
+#define BIFP1_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK                                               0x0000000CL
+#define BIFP1_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK                                              0x00000030L
+#define BIFP1_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK                                                         0x0000FFC0L
+#define BIFP1_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK                                                        0x03FF0000L
+#define BIFP1_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK                                       0x04000000L
+#define BIFP1_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK                                                  0x18000000L
+#define BIFP1_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK                                                0x20000000L
+#define BIFP1_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK                                   0x40000000L
+#define BIFP1_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK                                   0x80000000L
+//BIFP1_PCIE_LC_CNTL11
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT                                            0x0
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT                                          0x1
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT                                          0x2
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT                                          0x3
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT                                         0x5
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT                                          0x9
+#define BIFP1_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT                                    0xd
+#define BIFP1_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT                                          0xe
+#define BIFP1_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT                                           0xf
+#define BIFP1_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT                                                0x10
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT                       0x11
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT                         0x12
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT                              0x13
+#define BIFP1_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT                        0x14
+#define BIFP1_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT                                   0x15
+#define BIFP1_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT                                        0x16
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT                                                               0x17
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT                                                        0x18
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT                                                             0x1a
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT                                                             0x1b
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT                                                   0x1c
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT                                                     0x1e
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK                                              0x00000001L
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK                                            0x00000002L
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK                                            0x00000004L
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK                                            0x00000018L
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK                                           0x000001E0L
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK                                            0x00001E00L
+#define BIFP1_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK                                      0x00002000L
+#define BIFP1_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK                                            0x00004000L
+#define BIFP1_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK                                             0x00008000L
+#define BIFP1_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK                                                  0x00010000L
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK                         0x00020000L
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK                           0x00040000L
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK                                0x00080000L
+#define BIFP1_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK                          0x00100000L
+#define BIFP1_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK                                     0x00200000L
+#define BIFP1_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK                                          0x00400000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_EN_MASK                                                                 0x00800000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK                                                          0x03000000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK                                                               0x04000000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK                                                               0x08000000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK                                                     0x30000000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK                                                       0xC0000000L
+//BIFP1_PCIE_LC_CNTL12
+#define BIFP1_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT                                         0x0
+#define BIFP1_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT                                0x1
+#define BIFP1_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT                                        0x2
+#define BIFP1_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT                                            0x3
+#define BIFP1_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT                                 0x4
+#define BIFP1_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT                                      0x5
+#define BIFP1_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT                                         0x6
+#define BIFP1_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT                                                     0x7
+#define BIFP1_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT                                           0x8
+#define BIFP1_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT                                       0x9
+#define BIFP1_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT                                              0xa
+#define BIFP1_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT                                   0xb
+#define BIFP1_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT                                                0xc
+#define BIFP1_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT                                             0xd
+#define BIFP1_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT                                            0xe
+#define BIFP1_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT                                                0xf
+#define BIFP1_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT                                0x10
+#define BIFP1_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT                              0x11
+#define BIFP1_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT                            0x12
+#define BIFP1_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT                                          0x13
+#define BIFP1_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT                                                 0x14
+#define BIFP1_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT                                          0x15
+#define BIFP1_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT                                             0x16
+#define BIFP1_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT                                            0x17
+#define BIFP1_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT                                            0x1f
+#define BIFP1_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK                                           0x00000001L
+#define BIFP1_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK                                  0x00000002L
+#define BIFP1_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK                                          0x00000004L
+#define BIFP1_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK                                              0x00000008L
+#define BIFP1_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK                                   0x00000010L
+#define BIFP1_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK                                        0x00000020L
+#define BIFP1_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK                                           0x00000040L
+#define BIFP1_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK                                                       0x00000080L
+#define BIFP1_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK                                             0x00000100L
+#define BIFP1_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK                                         0x00000200L
+#define BIFP1_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK                                                0x00000400L
+#define BIFP1_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK                                     0x00000800L
+#define BIFP1_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK                                                  0x00001000L
+#define BIFP1_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK                                               0x00002000L
+#define BIFP1_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK                                              0x00004000L
+#define BIFP1_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK                                                  0x00008000L
+#define BIFP1_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK                                  0x00010000L
+#define BIFP1_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK                                0x00020000L
+#define BIFP1_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK                              0x00040000L
+#define BIFP1_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK                                            0x00080000L
+#define BIFP1_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK                                                   0x00100000L
+#define BIFP1_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK                                            0x00200000L
+#define BIFP1_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK                                               0x00400000L
+#define BIFP1_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK                                              0x00800000L
+#define BIFP1_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK                                              0x80000000L
+//BIFP1_PCIE_LC_SAVE_RESTORE_1
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT                                               0x0
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT                                        0x1
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT                                            0x2
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT                                      0xa
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT                                             0xb
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT                                  0xc
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT                                    0xd
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT                                           0xe
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT                                          0x10
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK                                                 0x00000001L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK                                          0x00000002L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK                                              0x000003FCL
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK                                        0x00000400L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK                                               0x00000800L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK                                    0x00001000L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK                                      0x00002000L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK                                             0x0000C000L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK                                            0xFFFF0000L
+//BIFP1_PCIE_LC_SAVE_RESTORE_2
+#define BIFP1_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT                                          0x0
+#define BIFP1_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK                                            0xFFFFFFFFL
+//BIFP1_PCIE_LC_SAVE_RESTORE_3
+#define BIFP1_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT                                0x0
+#define BIFP1_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK                                  0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp2_pciedir_p
+//BIFP2_PCIEP_RESERVED
+#define BIFP2_PCIEP_RESERVED__RESERVED__SHIFT                                                                 0x0
+#define BIFP2_PCIEP_RESERVED__RESERVED_MASK                                                                   0xFFFFFFFFL
+//BIFP2_PCIEP_SCRATCH
+#define BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT                                                             0x0
+#define BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK                                                               0xFFFFFFFFL
+//BIFP2_PCIEP_PORT_CNTL
+#define BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT                                                         0x0
+#define BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT                                                       0x1
+#define BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT                                                          0x2
+#define BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT                                                           0x3
+#define BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT                                                            0x4
+#define BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT                                                              0x5
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT                                         0x8
+#define BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT                                            0x12
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT                                             0x18
+#define BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT                                            0x1a
+#define BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK                                                           0x00000001L
+#define BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK                                                         0x00000002L
+#define BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK                                                            0x00000004L
+#define BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK                                                             0x00000008L
+#define BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK                                                              0x00000010L
+#define BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK                                                                0x00000020L
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK                                           0x0003FF00L
+#define BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK                                              0x001C0000L
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK                                               0x03000000L
+#define BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK                                              0x0C000000L
+//BIFP2_PCIE_TX_CNTL
+#define BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                            0xa
+#define BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                             0xc
+#define BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT                                                         0xe
+#define BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT                                                           0xf
+#define BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT                                                              0x14
+#define BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT                                                               0x15
+#define BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT                                                     0x16
+#define BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT                                                   0x17
+#define BIFP2_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT                                              0x1b
+#define BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                              0x00000C00L
+#define BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                               0x00003000L
+#define BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK                                                           0x00004000L
+#define BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK                                                             0x00008000L
+#define BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK                                                                0x00100000L
+#define BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK                                                                 0x00200000L
+#define BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK                                                       0x00400000L
+#define BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK                                                     0x00800000L
+#define BIFP2_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK                                                0x08000000L
+//BIFP2_PCIE_TX_REQUESTER_ID
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                           0x0
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                             0x3
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                                0x8
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                             0x00000007L
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                               0x000000F8L
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                                  0x0000FF00L
+//BIFP2_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT                                                  0x18
+#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK                                                    0x01000000L
+//BIFP2_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT                                          0x18
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT                                   0x1e
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT                                       0x1f
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK                                            0x3F000000L
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK                                     0x40000000L
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK                                         0x80000000L
+//BIFP2_PCIE_TX_SEQ
+#define BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT                                                        0x0
+#define BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT                                                                 0x10
+#define BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK                                                          0x00000FFFL
+#define BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK                                                                   0x0FFF0000L
+//BIFP2_PCIE_TX_REPLAY
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT                                                            0x0
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT                                                      0xe
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT                                                0xf
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT                                                          0x10
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK                                                              0x00000007L
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK                                                        0x00004000L
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK                                                  0x00008000L
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK                                                            0xFFFF0000L
+//BIFP2_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT                                          0x0
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT                                0xc
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK                                            0x00000FFFL
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK                                  0x00001000L
+//BIFP2_PCIE_TX_NOP_DLLP
+#define BIFP2_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT                                                            0x0
+#define BIFP2_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT                                                            0x18
+#define BIFP2_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK                                                              0x00FFFFFFL
+#define BIFP2_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK                                                              0x01000000L
+//BIFP2_PCIE_TX_CNTL_2
+//BIFP2_PCIE_TX_SKID_CTRL
+#define BIFP2_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT                                                  0x0
+#define BIFP2_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT                                            0x4
+#define BIFP2_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK                                                    0x0000000FL
+#define BIFP2_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK                                              0x00000010L
+//BIFP2_PCIE_TX_CREDITS_ADVT_P
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT                                               0x0
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT                                               0x10
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK                                                 0x00003FFFL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK                                                 0x03FF0000L
+//BIFP2_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT                                             0x0
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT                                             0x10
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK                                               0x00003FFFL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK                                               0x03FF0000L
+//BIFP2_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT                                           0x0
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT                                           0x10
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK                                             0x00003FFFL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK                                             0x03FF0000L
+//BIFP2_PCIE_TX_CREDITS_INIT_P
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT                                               0x0
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT                                               0x10
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK                                                 0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK                                                 0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_INIT_NP
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT                                             0x0
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT                                             0x10
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK                                               0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK                                               0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT                                           0x0
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT                                           0x10
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK                                             0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK                                             0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_STATUS
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT                                                0x0
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT                                                0x1
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT                                               0x2
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT                                               0x3
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT                                              0x4
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT                                              0x5
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT                                         0x10
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT                                         0x11
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT                                        0x12
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT                                        0x13
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT                                       0x14
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT                                       0x15
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK                                                  0x00000001L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK                                                  0x00000002L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK                                                 0x00000004L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK                                                 0x00000008L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK                                                0x00000010L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK                                                0x00000020L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK                                           0x00010000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK                                           0x00020000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK                                          0x00040000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK                                          0x00080000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK                                         0x00100000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK                                         0x00200000L
+//BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT                                    0x0
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT                                   0x4
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT                                  0x8
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT                                    0x10
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT                                   0x14
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT                                  0x18
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK                                      0x00000007L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK                                     0x00000070L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK                                    0x00000700L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK                                      0x00070000L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK                                     0x00700000L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK                                    0x07000000L
+//BIFP2_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT                                          0x0
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT                                                  0x3
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT                                           0x6
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT                                                   0x8
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT                                                   0x10
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT                                       0x19
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT                                              0x1c
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK                                            0x00000007L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK                                                    0x00000038L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK                                             0x00000040L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK                                                     0x00003F00L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK                                                     0x003F0000L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK                                         0x02000000L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK                                                0xF0000000L
+//BIFP2_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT                                      0x0
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK                                        0x0000FFFFL
+//BIFP2_PCIE_CCIX_STACKED_BASE
+#define BIFP2_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT                                           0x4
+#define BIFP2_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK                                             0xFFFFFFF0L
+//BIFP2_PCIE_CCIX_STACKED_LIMIT
+#define BIFP2_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT                                         0x4
+#define BIFP2_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK                                           0xFFFFFFF0L
+//BIFP2_PCIE_CCIX_MISC_STATUS
+#define BIFP2_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT                                              0x0
+#define BIFP2_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT                                          0x1
+#define BIFP2_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK                                                0x00000001L
+#define BIFP2_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK                                            0x00000002L
+//BIFP2_PCIE_P_PORT_LANE_STATUS
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT                                              0x0
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT                                                  0x1
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK                                                0x00000001L
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK                                                    0x0000007EL
+//BIFP2_PCIE_FC_P
+#define BIFP2_PCIE_FC_P__PD_CREDITS__SHIFT                                                                    0x0
+#define BIFP2_PCIE_FC_P__PH_CREDITS__SHIFT                                                                    0x10
+#define BIFP2_PCIE_FC_P__PD_CREDITS_MASK                                                                      0x0000FFFFL
+#define BIFP2_PCIE_FC_P__PH_CREDITS_MASK                                                                      0x0FFF0000L
+//BIFP2_PCIE_FC_NP
+#define BIFP2_PCIE_FC_NP__NPD_CREDITS__SHIFT                                                                  0x0
+#define BIFP2_PCIE_FC_NP__NPH_CREDITS__SHIFT                                                                  0x10
+#define BIFP2_PCIE_FC_NP__NPD_CREDITS_MASK                                                                    0x0000FFFFL
+#define BIFP2_PCIE_FC_NP__NPH_CREDITS_MASK                                                                    0x0FFF0000L
+//BIFP2_PCIE_FC_CPL
+#define BIFP2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT                                                                0x0
+#define BIFP2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT                                                                0x10
+#define BIFP2_PCIE_FC_CPL__CPLD_CREDITS_MASK                                                                  0x0000FFFFL
+#define BIFP2_PCIE_FC_CPL__CPLH_CREDITS_MASK                                                                  0x0FFF0000L
+//BIFP2_PCIE_FC_P_VC1
+#define BIFP2_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT                                                    0x0
+#define BIFP2_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT                                                    0x10
+#define BIFP2_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK                                                      0x0000FFFFL
+#define BIFP2_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK                                                      0x0FFF0000L
+//BIFP2_PCIE_FC_NP_VC1
+#define BIFP2_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT                                                  0x0
+#define BIFP2_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT                                                  0x10
+#define BIFP2_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK                                                    0x0000FFFFL
+#define BIFP2_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK                                                    0x0FFF0000L
+//BIFP2_PCIE_FC_CPL_VC1
+#define BIFP2_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT                                                0x0
+#define BIFP2_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT                                                0x10
+#define BIFP2_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK                                                  0x0000FFFFL
+#define BIFP2_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK                                                  0x0FFF0000L
+//BIFP2_PCIE_ERR_CNTL
+#define BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                         0x0
+#define BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT                                                  0x1
+#define BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT                                                     0x2
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT                                                      0x4
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT                                                      0x5
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT                                                      0x6
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT                                                      0x7
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                                       0x8
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                              0xb
+#define BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT                                               0xe
+#define BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT                                              0xf
+#define BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT                                                     0x10
+#define BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                                  0x11
+#define BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                                          0x12
+#define BIFP2_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT                                                    0x13
+#define BIFP2_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT                                                     0x14
+#define BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                           0x00000001L
+#define BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK                                                    0x00000002L
+#define BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK                                                       0x00000004L
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK                                                        0x00000010L
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK                                                        0x00000020L
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK                                                        0x00000040L
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK                                                        0x00000080L
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                         0x00000700L
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                                0x00000800L
+#define BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK                                                 0x00004000L
+#define BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK                                                0x00008000L
+#define BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK                                                       0x00010000L
+#define BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                                    0x00020000L
+#define BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                            0x00040000L
+#define BIFP2_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK                                                      0x00080000L
+#define BIFP2_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK                                                       0x00100000L
+//BIFP2_PCIE_RX_CNTL
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT                                                           0x0
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT                                                           0x1
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT                                                          0x2
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT                                                          0x3
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT                                                          0x4
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT                                                          0x5
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT                                                           0x6
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT                                                 0x7
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                                  0x8
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                           0x9
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT                                                           0xa
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT                                                            0xb
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT                                                           0xc
+#define BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT                                                        0xd
+#define BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT                                                        0xf
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT                                                         0x10
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT                                                    0x13
+#define BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                                    0x14
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                                  0x15
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                                    0x16
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT                                                    0x17
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                                 0x18
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                                     0x19
+#define BIFP2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                                 0x1a
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                                     0x1b
+#define BIFP2_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT                                                              0x1c
+#define BIFP2_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT                                                0x1d
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK                                                             0x00000001L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK                                                             0x00000002L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK                                                            0x00000004L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK                                                            0x00000008L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK                                                            0x00000010L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK                                                            0x00000020L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK                                                             0x00000040L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK                                                   0x00000080L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                                    0x00000100L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                             0x00000200L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK                                                             0x00000400L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK                                                              0x00000800L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK                                                             0x00001000L
+#define BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK                                                          0x00002000L
+#define BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK                                                          0x00008000L
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK                                                           0x00070000L
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK                                                      0x00080000L
+#define BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                                      0x00100000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                                    0x00200000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                                      0x00400000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK                                                      0x00800000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                                   0x01000000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                                       0x02000000L
+#define BIFP2_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                                   0x04000000L
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                                       0x08000000L
+#define BIFP2_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK                                                                0x10000000L
+#define BIFP2_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK                                                  0x20000000L
+//BIFP2_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT                                              0x0
+#define BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK                                                0x00000FFFL
+//BIFP2_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT                                                0x18
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK                                                  0x01000000L
+//BIFP2_PCIE_RX_CNTL3
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT                                             0x0
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT                                             0x1
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT                                                0x2
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT                                                    0x3
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT                                               0x4
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK                                               0x00000001L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK                                               0x00000002L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK                                                  0x00000004L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK                                                      0x00000008L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK                                                 0x00000010L
+//BIFP2_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT                                     0x0
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT                                     0x10
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK                                       0x00000FFFL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK                                       0x00FF0000L
+//BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT                                   0x0
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT                                   0x10
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK                                     0x00000FFFL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK                                     0x00FF0000L
+//BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT                                 0x0
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT                                 0x10
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK                                   0x00000FFFL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK                                   0x00FF0000L
+//BIFP2_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT                                    0x0
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT                                 0x2
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT                           0x4
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT                             0x6
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT                              0x8
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT                              0xa
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT                                  0xc
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT                         0xe
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT                            0x10
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT                                0x12
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT                           0x14
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT                             0x16
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK                                      0x00000003L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK                                   0x0000000CL
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK                             0x00000030L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK                               0x000000C0L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK                                0x00000300L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK                                0x00000C00L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK                                    0x00003000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK                           0x0000C000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK                              0x00030000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK                                  0x000C0000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK                             0x00300000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK                               0x00C00000L
+//BIFP2_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT                             0x0
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT                      0x2
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT                                 0x4
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT                                  0x6
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT                          0x8
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT                               0xa
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT                            0xc
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT                         0xe
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT                          0x10
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT                       0x12
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK                               0x00000003L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK                        0x0000000CL
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK                                   0x00000030L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK                                    0x000000C0L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK                            0x00000300L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK                                 0x00000C00L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK                              0x00003000L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK                           0x0000C000L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK                            0x00030000L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK                         0x000C0000L
+//BIFP2_PCIEP_NAK_COUNTER
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT                                              0x0
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT                                             0x10
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK                                                0x0000FFFFL
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK                                               0xFFFF0000L
+//BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT                     0x0
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT                     0xa
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT                      0xf
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT                  0x10
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT                  0x1a
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT                   0x1f
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK                       0x000003FFL
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK                       0x00001C00L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK                        0x00008000L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK                    0x03FF0000L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK                    0x1C000000L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK                     0x80000000L
+//BIFP2_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP2_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT                                    0x5
+#define BIFP2_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK                                      0x00000020L
+//BIFP2_PCIE_AER_PRIV_TRIGGER
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT                          0x0
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT                           0x1
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT                         0x2
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK                            0x00000001L
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK                             0x00000002L
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK                           0x00000004L
+//BIFP2_PCIE_LC_CNTL
+#define BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT                                                    0x1
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT                                                   0x2
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT                                                              0x3
+#define BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT                                                       0x4
+#define BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT                                                          0x8
+#define BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT                                                           0xc
+#define BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT                                                           0x10
+#define BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT                                                            0x11
+#define BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT                                                  0x12
+#define BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT                                                      0x14
+#define BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT                                                     0x15
+#define BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT                                                           0x16
+#define BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT                                                        0x17
+#define BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT                                                          0x18
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT                                                             0x19
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT                                                          0x1b
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT                                                           0x1c
+#define BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT                                                 0x1d
+#define BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT                                                         0x1e
+#define BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT                                                          0x1f
+#define BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK                                                      0x00000002L
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK                                                     0x00000004L
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_LINK_MASK                                                                0x00000008L
+#define BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK                                                         0x000000F0L
+#define BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK                                                            0x00000F00L
+#define BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK                                                             0x0000F000L
+#define BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK                                                             0x00010000L
+#define BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK                                                              0x00020000L
+#define BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK                                                    0x000C0000L
+#define BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK                                                        0x00100000L
+#define BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK                                                       0x00200000L
+#define BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK                                                             0x00400000L
+#define BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK                                                          0x00800000L
+#define BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK                                                            0x01000000L
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK                                                               0x06000000L
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK                                                            0x08000000L
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK                                                             0x10000000L
+#define BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK                                                   0x20000000L
+#define BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK                                                           0x40000000L
+#define BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK                                                            0x80000000L
+//BIFP2_PCIE_LC_TRAINING_CNTL
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT                                                  0x0
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT                                             0x4
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT                                 0x5
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT                                        0x6
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT                                            0x7
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT                                                    0x8
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT                                     0xb
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT                                       0xc
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT                                      0xd
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT                                          0xe
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT                                        0xf
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT                                            0x10
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT                                          0x11
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT                                            0x12
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT                                                 0x13
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT                                                 0x14
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT                                        0x15
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT                                          0x16
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT                                 0x18
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT                                    0x19
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT                                        0x1a
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT                                             0x1b
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT                                            0x1c
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT                                 0x1d
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT                                             0x1e
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK                                                    0x0000000FL
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK                                               0x00000010L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK                                   0x00000020L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK                                          0x00000040L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK                                              0x00000080L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK                                                      0x00000700L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK                                       0x00000800L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK                                         0x00001000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK                                        0x00002000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK                                            0x00004000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK                                          0x00008000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK                                              0x00010000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK                                            0x00020000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK                                              0x00040000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK                                                   0x00080000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK                                                   0x00100000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK                                          0x00200000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK                                            0x00C00000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK                                   0x01000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK                                      0x02000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK                                          0x04000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK                                               0x08000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK                                              0x10000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK                                   0x20000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK                                               0xC0000000L
+//BIFP2_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT                                                   0x0
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT                                                0x4
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT                                  0x7
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT                                                 0x8
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT                                        0x9
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT                                               0xa
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT                                            0xb
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT                                          0xc
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT                                              0xd
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT                                      0xe
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT                                              0xf
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT                                               0x11
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT                                               0x12
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT                                         0x13
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT                                          0x14
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT                                          0x15
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT                                         0x17
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT                                       0x18
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT                                  0x19
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT                                    0x1a
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT                                0x1b
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT                                0x1c
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT                                     0x1d
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT                                        0x1e
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT                                      0x1f
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK                                                     0x00000007L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK                                                  0x00000070L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK                                    0x00000080L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK                                                   0x00000100L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK                                          0x00000200L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK                                                 0x00000400L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK                                              0x00000800L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK                                            0x00001000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK                                                0x00002000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK                                        0x00004000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK                                                0x00008000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK                                                 0x00020000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK                                                 0x00040000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK                                           0x00080000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK                                            0x00100000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK                                            0x00600000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK                                           0x00800000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK                                         0x01000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK                                    0x02000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK                                      0x04000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK                                  0x08000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK                                  0x10000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK                                       0x20000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK                                          0x40000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK                                        0x80000000L
+//BIFP2_PCIE_LC_N_FTS_CNTL
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT                                                        0x0
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT                                            0x8
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT                                          0x9
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT                                                         0xa
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT                                               0xe
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT                                              0xf
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT                                                  0x10
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT                                                             0x18
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK                                                          0x000000FFL
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK                                              0x00000100L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK                                            0x00000200L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK                                                           0x00000400L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK                                                 0x00004000L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK                                                0x00008000L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK                                                    0x00FF0000L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK                                                               0xFF000000L
+//BIFP2_PCIE_LC_SPEED_CNTL
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                                     0x0
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                                     0x1
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                                     0x2
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT                                     0x3
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT                                        0x4
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT                                          0x6
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT                                         0x7
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT                                          0x8
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT                                         0x9
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT                                        0xa
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0xb
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0xd
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT                                                 0xe
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT                                 0x10
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT                                         0x11
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT                                        0x12
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT                                         0x13
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT                                          0x14
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT                                         0x15
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT                                          0x16
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT                                         0x17
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT                                          0x18
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT                                               0x19
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT                                              0x1a
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT                                                   0x1c
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT                                    0x1d
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT                                          0x1e
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT                                           0x1f
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                                       0x00000001L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                                       0x00000002L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                                       0x00000004L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK                                       0x00000008L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK                                          0x00000030L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK                                            0x00000040L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK                                           0x00000080L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK                                            0x00000100L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK                                           0x00000200L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK                                          0x00000400L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x00001800L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00002000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK                                                   0x0000C000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK                                   0x00010000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK                                           0x00020000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK                                          0x00040000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK                                           0x00080000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK                                            0x00100000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK                                           0x00200000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK                                            0x00400000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK                                           0x00800000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK                                            0x01000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK                                                 0x02000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK                                                0x0C000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK                                                     0x10000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK                                      0x20000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK                                            0x40000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK                                             0x80000000L
+//BIFP2_PCIE_LC_STATE0
+#define BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT                                                         0x0
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT                                                           0x8
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT                                                           0x10
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT                                                           0x18
+#define BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK                                                           0x0000003FL
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK                                                             0x00003F00L
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK                                                             0x003F0000L
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK                                                             0x3F000000L
+//BIFP2_PCIE_LC_STATE1
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT                                                           0x0
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT                                                           0x8
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT                                                           0x10
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT                                                           0x18
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK                                                             0x0000003FL
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK                                                             0x00003F00L
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK                                                             0x003F0000L
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK                                                             0x3F000000L
+//BIFP2_PCIE_LC_STATE2
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT                                                           0x0
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT                                                           0x8
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT                                                          0x10
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT                                                          0x18
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK                                                             0x0000003FL
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK                                                             0x00003F00L
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK                                                            0x003F0000L
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK                                                            0x3F000000L
+//BIFP2_PCIE_LC_STATE3
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT                                                          0x0
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT                                                          0x8
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT                                                          0x10
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT                                                          0x18
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK                                                            0x0000003FL
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK                                                            0x00003F00L
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK                                                            0x003F0000L
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK                                                            0x3F000000L
+//BIFP2_PCIE_LC_STATE4
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT                                                          0x0
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT                                                          0x8
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT                                                          0x10
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT                                                          0x18
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK                                                            0x0000003FL
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK                                                            0x00003F00L
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK                                                            0x003F0000L
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK                                                            0x3F000000L
+//BIFP2_PCIE_LC_STATE5
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT                                                          0x0
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT                                                          0x8
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT                                                          0x10
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT                                                          0x18
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK                                                            0x0000003FL
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK                                                            0x00003F00L
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK                                                            0x003F0000L
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK                                                            0x3F000000L
+//BIFP2_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT                                                 0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT                                                 0x1
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT                                                  0x2
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT                                                  0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT                                                 0x4
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT                                                0x5
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT                                                0x6
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT                                          0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT                                         0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT                                          0xf
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT                                         0x13
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT                                          0x17
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT                                         0x1b
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK                                                   0x00000001L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK                                                   0x00000002L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK                                                    0x00000004L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK                                                    0x00000008L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK                                                   0x00000010L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK                                                  0x00000020L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK                                                  0x00000040L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK                                            0x00000780L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK                                           0x00007800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK                                            0x00078000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK                                           0x00780000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK                                            0x07800000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK                                           0x78000000L
+//BIFP2_PCIE_LC_CNTL2
+#define BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT                                                        0x0
+#define BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT                                                        0x6
+#define BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT                                                  0x7
+#define BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT                                                            0x8
+#define BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT                                                    0x9
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT                                                    0xa
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT                                                          0xb
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT                                               0xc
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT                                              0xd
+#define BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT                                                         0xe
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT                                         0x10
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT                                                       0x11
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT                                                      0x12
+#define BIFP2_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT                                              0x13
+#define BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT                                                    0x14
+#define BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT                                                  0x15
+#define BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT                                            0x16
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT                                               0x17
+#define BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT                                                 0x19
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT                                             0x1a
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                               0x1b
+#define BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT                                               0x1c
+#define BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT                                                         0x1d
+#define BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT                                       0x1f
+#define BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK                                                          0x0000003FL
+#define BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK                                                          0x00000040L
+#define BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK                                                    0x00000080L
+#define BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK                                                              0x00000100L
+#define BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK                                                      0x00000200L
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK                                                      0x00000400L
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK                                                            0x00000800L
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK                                                 0x00001000L
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK                                                0x00002000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK                                                           0x0000C000L
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK                                           0x00010000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK                                                         0x00020000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK                                                        0x00040000L
+#define BIFP2_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK                                                0x00080000L
+#define BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK                                                      0x00100000L
+#define BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK                                                    0x00200000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK                                              0x00400000L
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK                                                 0x01800000L
+#define BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK                                                   0x02000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK                                               0x04000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                                 0x08000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK                                                 0x10000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK                                                           0x60000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK                                         0x80000000L
+//BIFP2_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT                                              0x0
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT                                          0x1
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT                                          0x2
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT                                       0x3
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT                                      0x4
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT                                              0x5
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT                                                0x6
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT                                               0x7
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT                                               0x8
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT                                              0x9
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT                              0xa
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT                                        0xb
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK                                                0x00000001L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK                                            0x00000002L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK                                            0x00000004L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK                                         0x00000008L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK                                        0x00000010L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK                                                0x00000020L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK                                                  0x00000040L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK                                                 0x00000080L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK                                                 0x00000100L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK                                                0x00000200L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK                                0x00000400L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK                                          0x00000800L
+//BIFP2_PCIE_LC_CDR_CNTL
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT                                                        0x0
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT                                                       0xc
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT                                                        0x18
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK                                                          0x00000FFFL
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK                                                         0x00FFF000L
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK                                                          0x03000000L
+//BIFP2_PCIE_LC_LANE_CNTL
+#define BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT                                                    0x0
+#define BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK                                                      0x0000FFFFL
+//BIFP2_PCIE_LC_CNTL3
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT                                                      0x0
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT                                                 0x1
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT                                                        0x3
+#define BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT                                                         0x4
+#define BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT                                              0x5
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0x6
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0x8
+#define BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT                                         0x9
+#define BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT                                                   0xa
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT                                                   0xb
+#define BIFP2_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT                                                   0xc
+#define BIFP2_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT                                         0xd
+#define BIFP2_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT                                         0xe
+#define BIFP2_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT                                    0xf
+#define BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT                                                   0x11
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT                                          0x12
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT                                0x13
+#define BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT                                                  0x15
+#define BIFP2_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT                             0x16
+#define BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT                                       0x17
+#define BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT                                                  0x18
+#define BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT                                                      0x1a
+#define BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT                                                         0x1e
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT                                                      0x1f
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK                                                        0x00000001L
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK                                                   0x00000006L
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK                                                          0x00000008L
+#define BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK                                                           0x00000010L
+#define BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK                                                0x00000020L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x000000C0L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00000100L
+#define BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK                                           0x00000200L
+#define BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK                                                     0x00000400L
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK                                                     0x00000800L
+#define BIFP2_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK                                                     0x00001000L
+#define BIFP2_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK                                           0x00002000L
+#define BIFP2_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK                                           0x00004000L
+#define BIFP2_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK                                      0x00008000L
+#define BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK                                                     0x00020000L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK                                            0x00040000L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK                                  0x00180000L
+#define BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK                                                    0x00200000L
+#define BIFP2_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK                               0x00400000L
+#define BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK                                         0x00800000L
+#define BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK                                                    0x03000000L
+#define BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK                                                        0x3C000000L
+#define BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK                                                           0x40000000L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK                                                        0x80000000L
+//BIFP2_PCIE_LC_CNTL4
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT                                                    0x0
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT                                               0x2
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT                                            0x3
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT                                                          0x4
+#define BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT                                                            0x5
+#define BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT                                                           0x6
+#define BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT                                                          0x7
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT                                                     0x8
+#define BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT                                              0xa
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT                                                    0xb
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT                                                       0xc
+#define BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT                                                            0xd
+#define BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT                                                           0xe
+#define BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT                                             0xf
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT                                                0x10
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT                                       0x11
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT                                                 0x12
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT                                                        0x16
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT                                                               0x17
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT                                                  0x18
+#define BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT                                                      0x19
+#define BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT                                              0x1a
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK                                                      0x00000003L
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK                                                 0x00000004L
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK                                              0x00000008L
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK                                                            0x00000010L
+#define BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK                                                              0x00000020L
+#define BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK                                                             0x00000040L
+#define BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK                                                            0x00000080L
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK                                                       0x00000300L
+#define BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK                                                0x00000400L
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK                                                      0x00000800L
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK                                                         0x00001000L
+#define BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK                                                              0x00002000L
+#define BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK                                                             0x00004000L
+#define BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK                                               0x00008000L
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK                                                  0x00010000L
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK                                         0x00020000L
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK                                                   0x003C0000L
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK                                                          0x00400000L
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_SWING_MASK                                                                 0x00800000L
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK                                                    0x01000000L
+#define BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK                                                        0x02000000L
+#define BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK                                                0xFC000000L
+//BIFP2_PCIE_LC_CNTL5
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT                                                 0x0
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT                                                           0x2
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT                                                       0x6
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT                                                           0xa
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT                                                      0x10
+#define BIFP2_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT                                      0x15
+#define BIFP2_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT                                                      0x16
+#define BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT                                        0x18
+#define BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT                                                      0x19
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT                                                     0x1a
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT                                                0x1b
+#define BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT                                                         0x1c
+#define BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT                                                     0x1d
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK                                                   0x00000003L
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK                                                             0x0000003CL
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK                                                         0x000003C0L
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK                                                             0x0000FC00L
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK                                                        0x001F0000L
+#define BIFP2_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK                                        0x00200000L
+#define BIFP2_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK                                                        0x00C00000L
+#define BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK                                          0x01000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK                                                        0x02000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK                                                       0x04000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK                                                  0x08000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK                                                           0x10000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK                                                       0xE0000000L
+//BIFP2_PCIE_LC_FORCE_COEFF
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT                                                  0x0
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT                                             0x1
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT                                                 0x7
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT                                            0xd
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT                                          0x13
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT                                                     0x14
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK                                                    0x00000001L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK                                               0x0000007EL
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK                                                   0x00001F80L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK                                              0x0007E000L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK                                            0x00080000L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK                                                       0x00100000L
+//BIFP2_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT                                                 0x0
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT                                              0x4
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT                                                 0xa
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT                                             0x10
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT                                                    0x16
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT                                          0x1e
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK                                                   0x0000000FL
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK                                                0x000003F0L
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK                                                   0x0000FC00L
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK                                               0x003F0000L
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK                                                      0x3FC00000L
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK                                            0x40000000L
+//BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT                           0x0
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT                                  0x1
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT                                      0x7
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT                                 0xd
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT                                          0x13
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT                                          0x19
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK                             0x00000001L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK                                    0x0000007EL
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK                                        0x00001F80L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK                                   0x0007E000L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK                                            0x01F80000L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK                                            0x7E000000L
+//BIFP2_PCIE_LC_CNTL6
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT                                                         0x0
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT                                                           0x2
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT                                                           0x4
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT                                                          0x6
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT                                                                0x8
+#define BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT                                                      0x9
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT                                                     0xd
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT                                                 0xe
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT                                                   0x10
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT                                           0x12
+#define BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT                                                0x13
+#define BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT                                                     0x14
+#define BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT                                                           0x15
+#define BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT                                                               0x16
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT                                                           0x17
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT                                                      0x18
+#define BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT                                                      0x1f
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK                                                           0x00000003L
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK                                                             0x0000000CL
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK                                                             0x00000030L
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK                                                            0x000000C0L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN_MASK                                                                  0x00000100L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK                                                        0x00001E00L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK                                                       0x00002000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK                                                   0x0000C000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK                                                     0x00030000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK                                             0x00040000L
+#define BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK                                                  0x00080000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK                                                       0x00100000L
+#define BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK                                                             0x00200000L
+#define BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK                                                                 0x00400000L
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK                                                             0x00800000L
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK                                                        0x7F000000L
+#define BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK                                                        0x80000000L
+//BIFP2_PCIE_LC_CNTL7
+#define BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT                                              0x0
+#define BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT                                         0x1
+#define BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT                                             0x2
+#define BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT                                                   0x3
+#define BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT                                                     0x4
+#define BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT                                            0x5
+#define BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT                                                          0x6
+#define BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT                                                0x7
+#define BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT                                                     0x8
+#define BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT                                              0x9
+#define BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT                                               0xa
+#define BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT                                             0xb
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT                                          0xc
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT                                            0xd
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT                                                0x15
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT                                         0x16
+#define BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT                                                     0x17
+#define BIFP2_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT                                              0x18
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT                                                              0x19
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT                                                     0x1b
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT                                                      0x1c
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT                                                          0x1d
+#define BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT                                                          0x1e
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT                                                         0x1f
+#define BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK                                                0x00000001L
+#define BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK                                           0x00000002L
+#define BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK                                               0x00000004L
+#define BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK                                                     0x00000008L
+#define BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK                                                       0x00000010L
+#define BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK                                              0x00000020L
+#define BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK                                                            0x00000040L
+#define BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK                                                  0x00000080L
+#define BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK                                                       0x00000100L
+#define BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK                                                0x00000200L
+#define BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK                                                 0x00000400L
+#define BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK                                               0x00000800L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK                                            0x00001000L
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK                                              0x001FE000L
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK                                                  0x00200000L
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK                                           0x00400000L
+#define BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK                                                       0x00800000L
+#define BIFP2_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK                                                0x01000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_RATES_MASK                                                                0x06000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK                                                       0x08000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK                                                        0x10000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK                                                            0x20000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK                                                            0x40000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK                                                           0x80000000L
+//BIFP2_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT                                           0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                            0x1
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT                           0x2
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT                                           0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT                            0x4
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT                           0x5
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT                                 0x6
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT                                            0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT                                     0x8
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT                                         0x9
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT                                        0xa
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT                                    0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT                                    0xc
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT                                  0xd
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK                                             0x00000001L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK                              0x00000002L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK                             0x00000004L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK                                             0x00000008L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK                              0x00000010L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK                             0x00000020L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK                                   0x00000040L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK                                              0x00000080L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK                                       0x00000100L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK                                           0x00000200L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK                                          0x00000400L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK                                      0x00000800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK                                      0x00001000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK                                    0x00002000L
+//BIFP2_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT                                        0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x1
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT                        0x2
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT                                        0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x4
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT                        0x5
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT                              0x6
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT                                         0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT                                  0x8
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT                                      0x9
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT                                     0xa
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT                                 0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT                                 0xc
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT                               0xd
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK                                          0x00000001L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000002L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK                          0x00000004L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK                                          0x00000008L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000010L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK                          0x00000020L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK                                0x00000040L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK                                           0x00000080L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK                                    0x00000100L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK                                        0x00000200L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK                                       0x00000400L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK                                   0x00000800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK                                   0x00001000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK                                 0x00002000L
+//BIFP2_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT                                         0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT                                              0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT                                         0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT                                                       0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT                                             0xc
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT                                                      0xd
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT                                                    0xf
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT                                                   0x11
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT                                                  0x12
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT                                              0x13
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT                                             0x17
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT                                                 0x1b
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT                                               0x1e
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT                                              0x1f
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK                                           0x00000007L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK                                                0x00000078L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK                                           0x00000780L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK                                                         0x00000800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK                                               0x00001000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK                                                        0x00006000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK                                                      0x00018000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK                                                     0x00020000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK                                                    0x00040000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK                                                0x00780000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK                                               0x07800000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK                                                   0x38000000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK                                                 0x40000000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK                                                0x80000000L
+//BIFP2_PCIEP_STRAP_LC
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT                                                     0x0
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT                                                    0x2
+#define BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT                                                     0x4
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT                                                   0x6
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT                                                      0x8
+#define BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT                                                    0xb
+#define BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT                                                     0xc
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT                                                   0xd
+#define BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT                                                   0xe
+#define BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT                                      0xf
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT                                                   0x10
+#define BIFP2_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                            0x13
+#define BIFP2_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT                                             0x14
+#define BIFP2_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT                                             0x15
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK                                                       0x00000003L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK                                                      0x0000000CL
+#define BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK                                                       0x00000030L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK                                                     0x000000C0L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK                                                        0x00000700L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK                                                      0x00000800L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK                                                       0x00001000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK                                                     0x00002000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK                                                     0x00004000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK                                        0x00008000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK                                                     0x00070000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK                                              0x00080000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK                                               0x00100000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK                                               0x00200000L
+//BIFP2_PCIEP_STRAP_MISC
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT                                                    0x0
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT                                                    0x1
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT                                           0x2
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT                                                   0x3
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT                                                    0x5
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT                                                          0x6
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT                                         0x7
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK                                                      0x00000001L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK                                                      0x00000002L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK                                             0x00000004L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK                                                     0x00000018L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK                                                      0x00000020L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK                                                            0x00000040L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK                                           0x00000080L
+//BIFP2_PCIEP_STRAP_LC2
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT                                                0x0
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT                                             0x1
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT                                                  0x3
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT                                                    0x4
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT                                              0x7
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK                                                  0x00000001L
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK                                               0x00000006L
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK                                                    0x00000008L
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK                                                      0x00000070L
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK                                                0x00000380L
+//BIFP2_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT                                      0x0
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT                                          0x1
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT                                          0x2
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT                                            0x3
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT                                            0x4
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT                                              0x5
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT                                              0x6
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT                                              0x8
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT                                                0x10
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT                                                0x14
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT                                               0x17
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT                                 0x1a
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT                                   0x1b
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT                          0x1c
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK                                        0x00000001L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK                                            0x00000002L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK                                            0x00000004L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK                                              0x00000008L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK                                              0x00000010L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK                                                0x00000020L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK                                                0x000000C0L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK                                                0x00001F00L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK                                                  0x00070000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK                                                  0x00700000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK                                                 0x03800000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK                                   0x04000000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK                                     0x08000000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK                            0x10000000L
+//BIFP2_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT                                              0x0
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT                                          0x8
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK                                                0x000000FFL
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK                                            0x00000700L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+//BIFP2_PCIE_LC_PORT_ORDER
+#define BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT                                                       0x0
+#define BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK                                                         0x0000000FL
+//BIFP2_PCIEP_BCH_ECC_CNTL
+#define BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT                                                     0x0
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT                                              0x8
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT                                                 0x10
+#define BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK                                                       0x00000001L
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK                                                0x0000FF00L
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK                                                   0xFFFF0000L
+//BIFP2_PCIEP_HPGI_PRIVATE
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT                                      0x3
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT                                        0x6
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK                                        0x00000008L
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK                                          0x00000040L
+//BIFP2_PCIEP_HPGI
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT                                                    0x0
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT                                                    0x1
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT                                                  0x2
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT                                                  0x3
+#define BIFP2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT                                                                0x7
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT                                                0x8
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT                                                0x9
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT                                              0xa
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT                                              0xb
+#define BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT                                 0xf
+#define BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT                                     0x10
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK                                                      0x00000001L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK                                                      0x00000002L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK                                                    0x00000004L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK                                                    0x00000008L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_HOOK_MASK                                                                  0x00000080L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK                                                  0x00000100L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK                                                  0x00000200L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK                                                0x00000400L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK                                                0x00000800L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK                                   0x00008000L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK                                       0x00010000L
+//BIFP2_PCIEP_HCNT_DESCRIPTOR
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT                                    0x0
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT                                 0x1f
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK                                      0x00001FFFL
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK                                   0x80000000L
+//BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT                                          0x0
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT                                        0x10
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK                                            0x0000FFFFL
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK                                          0x00FF0000L
+//BIFP2_PCIE_LC_CNTL8
+#define BIFP2_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT                                                    0x0
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT                                                         0x2
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT                                                  0x3
+#define BIFP2_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT                                                           0x7
+#define BIFP2_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT                                                   0x8
+#define BIFP2_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT                                                      0x9
+#define BIFP2_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT                                            0xa
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT                                               0xb
+#define BIFP2_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT                                      0xc
+#define BIFP2_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT                                                0xd
+#define BIFP2_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT                                                        0x11
+#define BIFP2_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT                                                           0x12
+#define BIFP2_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT                                                       0x16
+#define BIFP2_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT                                                               0x17
+#define BIFP2_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT                                                         0x19
+#define BIFP2_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT                                                0x1a
+#define BIFP2_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT                                                 0x1b
+#define BIFP2_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT                                                         0x1c
+#define BIFP2_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT                                                0x1d
+#define BIFP2_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT                                             0x1e
+#define BIFP2_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK                                                      0x00000003L
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK                                                           0x00000004L
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK                                                    0x00000078L
+#define BIFP2_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK                                                             0x00000080L
+#define BIFP2_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK                                                     0x00000100L
+#define BIFP2_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK                                                        0x00000200L
+#define BIFP2_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK                                              0x00000400L
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK                                                 0x00000800L
+#define BIFP2_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK                                        0x00001000L
+#define BIFP2_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK                                                  0x0001E000L
+#define BIFP2_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK                                                          0x00020000L
+#define BIFP2_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK                                                             0x003C0000L
+#define BIFP2_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK                                                         0x00400000L
+#define BIFP2_PCIE_LC_CNTL8__LC_FOM_TIME_MASK                                                                 0x01800000L
+#define BIFP2_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK                                                           0x02000000L
+#define BIFP2_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK                                                  0x04000000L
+#define BIFP2_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK                                                   0x08000000L
+#define BIFP2_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK                                                           0x10000000L
+#define BIFP2_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK                                                  0x20000000L
+#define BIFP2_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK                                               0xC0000000L
+//BIFP2_PCIE_LC_CNTL9
+#define BIFP2_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT                                           0x0
+#define BIFP2_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT                                              0x1
+#define BIFP2_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT                                                0x3
+#define BIFP2_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT                                                       0x4
+#define BIFP2_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT                                                 0x6
+#define BIFP2_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT                                                 0x8
+#define BIFP2_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT                            0xa
+#define BIFP2_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT                                                   0xb
+#define BIFP2_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT                                               0xc
+#define BIFP2_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT                                                    0xd
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT                                                 0xe
+#define BIFP2_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT                                                 0x18
+#define BIFP2_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT                                                0x19
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT                                                  0x1a
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT                                                 0x1b
+#define BIFP2_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT                                              0x1c
+#define BIFP2_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT                               0x1d
+#define BIFP2_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT                                      0x1e
+#define BIFP2_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT                                      0x1f
+#define BIFP2_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK                                             0x00000001L
+#define BIFP2_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK                                                0x00000006L
+#define BIFP2_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK                                                  0x00000008L
+#define BIFP2_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK                                                         0x00000030L
+#define BIFP2_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK                                                   0x000000C0L
+#define BIFP2_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK                                                   0x00000300L
+#define BIFP2_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK                              0x00000400L
+#define BIFP2_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK                                                     0x00000800L
+#define BIFP2_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK                                                 0x00001000L
+#define BIFP2_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK                                                      0x00002000L
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK                                                   0x00FFC000L
+#define BIFP2_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK                                                   0x01000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK                                                  0x02000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK                                                    0x04000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK                                                   0x08000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK                                                0x10000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK                                 0x20000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK                                        0x40000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK                                        0x80000000L
+//BIFP2_PCIE_LC_FORCE_COEFF2
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT                                                0x0
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT                                           0x1
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT                                               0x7
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT                                          0xd
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT                                        0x13
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK                                                  0x00000001L
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK                                             0x0000007EL
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK                                                 0x00001F80L
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK                                            0x0007E000L
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK                                          0x00080000L
+//BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT                         0x0
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT                                0x1
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT                                    0x7
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT                               0xd
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT                                        0x13
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT                                        0x19
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK                           0x00000001L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK                                  0x0000007EL
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK                                      0x00001F80L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK                                 0x0007E000L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK                                          0x01F80000L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK                                          0x7E000000L
+//BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT                                       0x0
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT                                     0x10
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK                                         0x0000FFFFL
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK                                       0x00FF0000L
+//BIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT             0x0
+#define BIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT               0x1
+#define BIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK               0x00000001L
+#define BIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK                 0x00000002L
+//BIFP2_PCIE_LC_CNTL10
+#define BIFP2_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT                      0x0
+#define BIFP2_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT                                         0x1
+#define BIFP2_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT                                             0x2
+#define BIFP2_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT                                            0x4
+#define BIFP2_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT                                                       0x6
+#define BIFP2_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT                                                      0x10
+#define BIFP2_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT                                     0x1a
+#define BIFP2_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT                                                0x1b
+#define BIFP2_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT                                              0x1d
+#define BIFP2_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT                                 0x1e
+#define BIFP2_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT                                 0x1f
+#define BIFP2_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK                        0x00000001L
+#define BIFP2_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK                                           0x00000002L
+#define BIFP2_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK                                               0x0000000CL
+#define BIFP2_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK                                              0x00000030L
+#define BIFP2_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK                                                         0x0000FFC0L
+#define BIFP2_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK                                                        0x03FF0000L
+#define BIFP2_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK                                       0x04000000L
+#define BIFP2_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK                                                  0x18000000L
+#define BIFP2_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK                                                0x20000000L
+#define BIFP2_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK                                   0x40000000L
+#define BIFP2_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK                                   0x80000000L
+//BIFP2_PCIE_LC_CNTL11
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT                                            0x0
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT                                          0x1
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT                                          0x2
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT                                          0x3
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT                                         0x5
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT                                          0x9
+#define BIFP2_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT                                    0xd
+#define BIFP2_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT                                          0xe
+#define BIFP2_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT                                           0xf
+#define BIFP2_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT                                                0x10
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT                       0x11
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT                         0x12
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT                              0x13
+#define BIFP2_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT                        0x14
+#define BIFP2_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT                                   0x15
+#define BIFP2_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT                                        0x16
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT                                                               0x17
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT                                                        0x18
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT                                                             0x1a
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT                                                             0x1b
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT                                                   0x1c
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT                                                     0x1e
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK                                              0x00000001L
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK                                            0x00000002L
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK                                            0x00000004L
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK                                            0x00000018L
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK                                           0x000001E0L
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK                                            0x00001E00L
+#define BIFP2_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK                                      0x00002000L
+#define BIFP2_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK                                            0x00004000L
+#define BIFP2_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK                                             0x00008000L
+#define BIFP2_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK                                                  0x00010000L
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK                         0x00020000L
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK                           0x00040000L
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK                                0x00080000L
+#define BIFP2_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK                          0x00100000L
+#define BIFP2_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK                                     0x00200000L
+#define BIFP2_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK                                          0x00400000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_EN_MASK                                                                 0x00800000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK                                                          0x03000000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK                                                               0x04000000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK                                                               0x08000000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK                                                     0x30000000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK                                                       0xC0000000L
+//BIFP2_PCIE_LC_CNTL12
+#define BIFP2_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT                                         0x0
+#define BIFP2_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT                                0x1
+#define BIFP2_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT                                        0x2
+#define BIFP2_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT                                            0x3
+#define BIFP2_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT                                 0x4
+#define BIFP2_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT                                      0x5
+#define BIFP2_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT                                         0x6
+#define BIFP2_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT                                                     0x7
+#define BIFP2_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT                                           0x8
+#define BIFP2_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT                                       0x9
+#define BIFP2_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT                                              0xa
+#define BIFP2_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT                                   0xb
+#define BIFP2_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT                                                0xc
+#define BIFP2_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT                                             0xd
+#define BIFP2_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT                                            0xe
+#define BIFP2_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT                                                0xf
+#define BIFP2_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT                                0x10
+#define BIFP2_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT                              0x11
+#define BIFP2_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT                            0x12
+#define BIFP2_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT                                          0x13
+#define BIFP2_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT                                                 0x14
+#define BIFP2_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT                                          0x15
+#define BIFP2_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT                                             0x16
+#define BIFP2_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT                                            0x17
+#define BIFP2_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT                                            0x1f
+#define BIFP2_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK                                           0x00000001L
+#define BIFP2_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK                                  0x00000002L
+#define BIFP2_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK                                          0x00000004L
+#define BIFP2_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK                                              0x00000008L
+#define BIFP2_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK                                   0x00000010L
+#define BIFP2_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK                                        0x00000020L
+#define BIFP2_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK                                           0x00000040L
+#define BIFP2_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK                                                       0x00000080L
+#define BIFP2_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK                                             0x00000100L
+#define BIFP2_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK                                         0x00000200L
+#define BIFP2_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK                                                0x00000400L
+#define BIFP2_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK                                     0x00000800L
+#define BIFP2_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK                                                  0x00001000L
+#define BIFP2_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK                                               0x00002000L
+#define BIFP2_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK                                              0x00004000L
+#define BIFP2_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK                                                  0x00008000L
+#define BIFP2_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK                                  0x00010000L
+#define BIFP2_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK                                0x00020000L
+#define BIFP2_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK                              0x00040000L
+#define BIFP2_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK                                            0x00080000L
+#define BIFP2_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK                                                   0x00100000L
+#define BIFP2_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK                                            0x00200000L
+#define BIFP2_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK                                               0x00400000L
+#define BIFP2_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK                                              0x00800000L
+#define BIFP2_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK                                              0x80000000L
+//BIFP2_PCIE_LC_SAVE_RESTORE_1
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT                                               0x0
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT                                        0x1
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT                                            0x2
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT                                      0xa
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT                                             0xb
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT                                  0xc
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT                                    0xd
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT                                           0xe
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT                                          0x10
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK                                                 0x00000001L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK                                          0x00000002L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK                                              0x000003FCL
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK                                        0x00000400L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK                                               0x00000800L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK                                    0x00001000L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK                                      0x00002000L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK                                             0x0000C000L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK                                            0xFFFF0000L
+//BIFP2_PCIE_LC_SAVE_RESTORE_2
+#define BIFP2_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT                                          0x0
+#define BIFP2_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK                                            0xFFFFFFFFL
+//BIFP2_PCIE_LC_SAVE_RESTORE_3
+#define BIFP2_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT                                0x0
+#define BIFP2_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK                                  0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp3_pciedir_p
+//BIFP3_PCIEP_RESERVED
+#define BIFP3_PCIEP_RESERVED__RESERVED__SHIFT                                                                 0x0
+#define BIFP3_PCIEP_RESERVED__RESERVED_MASK                                                                   0xFFFFFFFFL
+//BIFP3_PCIEP_SCRATCH
+#define BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT                                                             0x0
+#define BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK                                                               0xFFFFFFFFL
+//BIFP3_PCIEP_PORT_CNTL
+#define BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT                                                         0x0
+#define BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT                                                       0x1
+#define BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT                                                          0x2
+#define BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT                                                           0x3
+#define BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT                                                            0x4
+#define BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT                                                              0x5
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT                                         0x8
+#define BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT                                            0x12
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT                                             0x18
+#define BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT                                            0x1a
+#define BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK                                                           0x00000001L
+#define BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK                                                         0x00000002L
+#define BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK                                                            0x00000004L
+#define BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK                                                             0x00000008L
+#define BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK                                                              0x00000010L
+#define BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK                                                                0x00000020L
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK                                           0x0003FF00L
+#define BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK                                              0x001C0000L
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK                                               0x03000000L
+#define BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK                                              0x0C000000L
+//BIFP3_PCIE_TX_CNTL
+#define BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                            0xa
+#define BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                             0xc
+#define BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT                                                         0xe
+#define BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT                                                           0xf
+#define BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT                                                              0x14
+#define BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT                                                               0x15
+#define BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT                                                     0x16
+#define BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT                                                   0x17
+#define BIFP3_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT                                              0x1b
+#define BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                              0x00000C00L
+#define BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                               0x00003000L
+#define BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK                                                           0x00004000L
+#define BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK                                                             0x00008000L
+#define BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK                                                                0x00100000L
+#define BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK                                                                 0x00200000L
+#define BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK                                                       0x00400000L
+#define BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK                                                     0x00800000L
+#define BIFP3_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK                                                0x08000000L
+//BIFP3_PCIE_TX_REQUESTER_ID
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                           0x0
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                             0x3
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                                0x8
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                             0x00000007L
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                               0x000000F8L
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                                  0x0000FF00L
+//BIFP3_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT                                                  0x18
+#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK                                                    0x01000000L
+//BIFP3_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT                                          0x18
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT                                   0x1e
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT                                       0x1f
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK                                            0x3F000000L
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK                                     0x40000000L
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK                                         0x80000000L
+//BIFP3_PCIE_TX_SEQ
+#define BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT                                                        0x0
+#define BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT                                                                 0x10
+#define BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK                                                          0x00000FFFL
+#define BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK                                                                   0x0FFF0000L
+//BIFP3_PCIE_TX_REPLAY
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT                                                            0x0
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT                                                      0xe
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT                                                0xf
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT                                                          0x10
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK                                                              0x00000007L
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK                                                        0x00004000L
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK                                                  0x00008000L
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK                                                            0xFFFF0000L
+//BIFP3_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT                                          0x0
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT                                0xc
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK                                            0x00000FFFL
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK                                  0x00001000L
+//BIFP3_PCIE_TX_NOP_DLLP
+#define BIFP3_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT                                                            0x0
+#define BIFP3_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT                                                            0x18
+#define BIFP3_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK                                                              0x00FFFFFFL
+#define BIFP3_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK                                                              0x01000000L
+//BIFP3_PCIE_TX_CNTL_2
+//BIFP3_PCIE_TX_SKID_CTRL
+#define BIFP3_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT                                                  0x0
+#define BIFP3_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT                                            0x4
+#define BIFP3_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK                                                    0x0000000FL
+#define BIFP3_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK                                              0x00000010L
+//BIFP3_PCIE_TX_CREDITS_ADVT_P
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT                                               0x0
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT                                               0x10
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK                                                 0x00003FFFL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK                                                 0x03FF0000L
+//BIFP3_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT                                             0x0
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT                                             0x10
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK                                               0x00003FFFL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK                                               0x03FF0000L
+//BIFP3_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT                                           0x0
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT                                           0x10
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK                                             0x00003FFFL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK                                             0x03FF0000L
+//BIFP3_PCIE_TX_CREDITS_INIT_P
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT                                               0x0
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT                                               0x10
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK                                                 0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK                                                 0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_INIT_NP
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT                                             0x0
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT                                             0x10
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK                                               0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK                                               0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT                                           0x0
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT                                           0x10
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK                                             0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK                                             0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_STATUS
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT                                                0x0
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT                                                0x1
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT                                               0x2
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT                                               0x3
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT                                              0x4
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT                                              0x5
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT                                         0x10
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT                                         0x11
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT                                        0x12
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT                                        0x13
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT                                       0x14
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT                                       0x15
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK                                                  0x00000001L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK                                                  0x00000002L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK                                                 0x00000004L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK                                                 0x00000008L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK                                                0x00000010L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK                                                0x00000020L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK                                           0x00010000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK                                           0x00020000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK                                          0x00040000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK                                          0x00080000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK                                         0x00100000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK                                         0x00200000L
+//BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT                                    0x0
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT                                   0x4
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT                                  0x8
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT                                    0x10
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT                                   0x14
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT                                  0x18
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK                                      0x00000007L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK                                     0x00000070L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK                                    0x00000700L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK                                      0x00070000L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK                                     0x00700000L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK                                    0x07000000L
+//BIFP3_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT                                          0x0
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT                                                  0x3
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT                                           0x6
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT                                                   0x8
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT                                                   0x10
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT                                       0x19
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT                                              0x1c
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK                                            0x00000007L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK                                                    0x00000038L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK                                             0x00000040L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK                                                     0x00003F00L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK                                                     0x003F0000L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK                                         0x02000000L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK                                                0xF0000000L
+//BIFP3_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT                                      0x0
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK                                        0x0000FFFFL
+//BIFP3_PCIE_CCIX_STACKED_BASE
+#define BIFP3_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT                                           0x4
+#define BIFP3_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK                                             0xFFFFFFF0L
+//BIFP3_PCIE_CCIX_STACKED_LIMIT
+#define BIFP3_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT                                         0x4
+#define BIFP3_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK                                           0xFFFFFFF0L
+//BIFP3_PCIE_CCIX_MISC_STATUS
+#define BIFP3_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT                                              0x0
+#define BIFP3_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT                                          0x1
+#define BIFP3_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK                                                0x00000001L
+#define BIFP3_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK                                            0x00000002L
+//BIFP3_PCIE_P_PORT_LANE_STATUS
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT                                              0x0
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT                                                  0x1
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK                                                0x00000001L
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK                                                    0x0000007EL
+//BIFP3_PCIE_FC_P
+#define BIFP3_PCIE_FC_P__PD_CREDITS__SHIFT                                                                    0x0
+#define BIFP3_PCIE_FC_P__PH_CREDITS__SHIFT                                                                    0x10
+#define BIFP3_PCIE_FC_P__PD_CREDITS_MASK                                                                      0x0000FFFFL
+#define BIFP3_PCIE_FC_P__PH_CREDITS_MASK                                                                      0x0FFF0000L
+//BIFP3_PCIE_FC_NP
+#define BIFP3_PCIE_FC_NP__NPD_CREDITS__SHIFT                                                                  0x0
+#define BIFP3_PCIE_FC_NP__NPH_CREDITS__SHIFT                                                                  0x10
+#define BIFP3_PCIE_FC_NP__NPD_CREDITS_MASK                                                                    0x0000FFFFL
+#define BIFP3_PCIE_FC_NP__NPH_CREDITS_MASK                                                                    0x0FFF0000L
+//BIFP3_PCIE_FC_CPL
+#define BIFP3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT                                                                0x0
+#define BIFP3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT                                                                0x10
+#define BIFP3_PCIE_FC_CPL__CPLD_CREDITS_MASK                                                                  0x0000FFFFL
+#define BIFP3_PCIE_FC_CPL__CPLH_CREDITS_MASK                                                                  0x0FFF0000L
+//BIFP3_PCIE_FC_P_VC1
+#define BIFP3_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT                                                    0x0
+#define BIFP3_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT                                                    0x10
+#define BIFP3_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK                                                      0x0000FFFFL
+#define BIFP3_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK                                                      0x0FFF0000L
+//BIFP3_PCIE_FC_NP_VC1
+#define BIFP3_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT                                                  0x0
+#define BIFP3_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT                                                  0x10
+#define BIFP3_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK                                                    0x0000FFFFL
+#define BIFP3_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK                                                    0x0FFF0000L
+//BIFP3_PCIE_FC_CPL_VC1
+#define BIFP3_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT                                                0x0
+#define BIFP3_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT                                                0x10
+#define BIFP3_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK                                                  0x0000FFFFL
+#define BIFP3_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK                                                  0x0FFF0000L
+//BIFP3_PCIE_ERR_CNTL
+#define BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                         0x0
+#define BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT                                                  0x1
+#define BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT                                                     0x2
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT                                                      0x4
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT                                                      0x5
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT                                                      0x6
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT                                                      0x7
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                                       0x8
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                              0xb
+#define BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT                                               0xe
+#define BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT                                              0xf
+#define BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT                                                     0x10
+#define BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                                  0x11
+#define BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                                          0x12
+#define BIFP3_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT                                                    0x13
+#define BIFP3_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT                                                     0x14
+#define BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                           0x00000001L
+#define BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK                                                    0x00000002L
+#define BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK                                                       0x00000004L
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK                                                        0x00000010L
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK                                                        0x00000020L
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK                                                        0x00000040L
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK                                                        0x00000080L
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                         0x00000700L
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                                0x00000800L
+#define BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK                                                 0x00004000L
+#define BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK                                                0x00008000L
+#define BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK                                                       0x00010000L
+#define BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                                    0x00020000L
+#define BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                            0x00040000L
+#define BIFP3_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK                                                      0x00080000L
+#define BIFP3_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK                                                       0x00100000L
+//BIFP3_PCIE_RX_CNTL
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT                                                           0x0
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT                                                           0x1
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT                                                          0x2
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT                                                          0x3
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT                                                          0x4
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT                                                          0x5
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT                                                           0x6
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT                                                 0x7
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                                  0x8
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                           0x9
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT                                                           0xa
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT                                                            0xb
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT                                                           0xc
+#define BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT                                                        0xd
+#define BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT                                                        0xf
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT                                                         0x10
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT                                                    0x13
+#define BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                                    0x14
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                                  0x15
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                                    0x16
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT                                                    0x17
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                                 0x18
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                                     0x19
+#define BIFP3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                                 0x1a
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                                     0x1b
+#define BIFP3_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT                                                              0x1c
+#define BIFP3_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT                                                0x1d
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK                                                             0x00000001L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK                                                             0x00000002L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK                                                            0x00000004L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK                                                            0x00000008L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK                                                            0x00000010L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK                                                            0x00000020L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK                                                             0x00000040L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK                                                   0x00000080L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                                    0x00000100L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                             0x00000200L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK                                                             0x00000400L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK                                                              0x00000800L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK                                                             0x00001000L
+#define BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK                                                          0x00002000L
+#define BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK                                                          0x00008000L
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK                                                           0x00070000L
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK                                                      0x00080000L
+#define BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                                      0x00100000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                                    0x00200000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                                      0x00400000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK                                                      0x00800000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                                   0x01000000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                                       0x02000000L
+#define BIFP3_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                                   0x04000000L
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                                       0x08000000L
+#define BIFP3_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK                                                                0x10000000L
+#define BIFP3_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK                                                  0x20000000L
+//BIFP3_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT                                              0x0
+#define BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK                                                0x00000FFFL
+//BIFP3_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT                                                0x18
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK                                                  0x01000000L
+//BIFP3_PCIE_RX_CNTL3
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT                                             0x0
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT                                             0x1
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT                                                0x2
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT                                                    0x3
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT                                               0x4
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK                                               0x00000001L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK                                               0x00000002L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK                                                  0x00000004L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK                                                      0x00000008L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK                                                 0x00000010L
+//BIFP3_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT                                     0x0
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT                                     0x10
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK                                       0x00000FFFL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK                                       0x00FF0000L
+//BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT                                   0x0
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT                                   0x10
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK                                     0x00000FFFL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK                                     0x00FF0000L
+//BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT                                 0x0
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT                                 0x10
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK                                   0x00000FFFL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK                                   0x00FF0000L
+//BIFP3_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT                                    0x0
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT                                 0x2
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT                           0x4
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT                             0x6
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT                              0x8
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT                              0xa
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT                                  0xc
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT                         0xe
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT                            0x10
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT                                0x12
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT                           0x14
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT                             0x16
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK                                      0x00000003L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK                                   0x0000000CL
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK                             0x00000030L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK                               0x000000C0L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK                                0x00000300L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK                                0x00000C00L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK                                    0x00003000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK                           0x0000C000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK                              0x00030000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK                                  0x000C0000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK                             0x00300000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK                               0x00C00000L
+//BIFP3_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT                             0x0
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT                      0x2
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT                                 0x4
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT                                  0x6
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT                          0x8
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT                               0xa
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT                            0xc
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT                         0xe
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT                          0x10
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT                       0x12
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK                               0x00000003L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK                        0x0000000CL
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK                                   0x00000030L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK                                    0x000000C0L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK                            0x00000300L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK                                 0x00000C00L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK                              0x00003000L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK                           0x0000C000L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK                            0x00030000L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK                         0x000C0000L
+//BIFP3_PCIEP_NAK_COUNTER
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT                                              0x0
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT                                             0x10
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK                                                0x0000FFFFL
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK                                               0xFFFF0000L
+//BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT                     0x0
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT                     0xa
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT                      0xf
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT                  0x10
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT                  0x1a
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT                   0x1f
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK                       0x000003FFL
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK                       0x00001C00L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK                        0x00008000L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK                    0x03FF0000L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK                    0x1C000000L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK                     0x80000000L
+//BIFP3_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP3_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT                                    0x5
+#define BIFP3_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK                                      0x00000020L
+//BIFP3_PCIE_AER_PRIV_TRIGGER
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT                          0x0
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT                           0x1
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT                         0x2
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK                            0x00000001L
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK                             0x00000002L
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK                           0x00000004L
+//BIFP3_PCIE_LC_CNTL
+#define BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT                                                    0x1
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT                                                   0x2
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT                                                              0x3
+#define BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT                                                       0x4
+#define BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT                                                          0x8
+#define BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT                                                           0xc
+#define BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT                                                           0x10
+#define BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT                                                            0x11
+#define BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT                                                  0x12
+#define BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT                                                      0x14
+#define BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT                                                     0x15
+#define BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT                                                           0x16
+#define BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT                                                        0x17
+#define BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT                                                          0x18
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT                                                             0x19
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT                                                          0x1b
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT                                                           0x1c
+#define BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT                                                 0x1d
+#define BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT                                                         0x1e
+#define BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT                                                          0x1f
+#define BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK                                                      0x00000002L
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK                                                     0x00000004L
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_LINK_MASK                                                                0x00000008L
+#define BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK                                                         0x000000F0L
+#define BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK                                                            0x00000F00L
+#define BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK                                                             0x0000F000L
+#define BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK                                                             0x00010000L
+#define BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK                                                              0x00020000L
+#define BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK                                                    0x000C0000L
+#define BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK                                                        0x00100000L
+#define BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK                                                       0x00200000L
+#define BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK                                                             0x00400000L
+#define BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK                                                          0x00800000L
+#define BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK                                                            0x01000000L
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK                                                               0x06000000L
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK                                                            0x08000000L
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK                                                             0x10000000L
+#define BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK                                                   0x20000000L
+#define BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK                                                           0x40000000L
+#define BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK                                                            0x80000000L
+//BIFP3_PCIE_LC_TRAINING_CNTL
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT                                                  0x0
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT                                             0x4
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT                                 0x5
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT                                        0x6
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT                                            0x7
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT                                                    0x8
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT                                     0xb
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT                                       0xc
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT                                      0xd
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT                                          0xe
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT                                        0xf
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT                                            0x10
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT                                          0x11
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT                                            0x12
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT                                                 0x13
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT                                                 0x14
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT                                        0x15
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT                                          0x16
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT                                 0x18
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT                                    0x19
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT                                        0x1a
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT                                             0x1b
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT                                            0x1c
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT                                 0x1d
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT                                             0x1e
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK                                                    0x0000000FL
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK                                               0x00000010L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK                                   0x00000020L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK                                          0x00000040L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK                                              0x00000080L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK                                                      0x00000700L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK                                       0x00000800L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK                                         0x00001000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK                                        0x00002000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK                                            0x00004000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK                                          0x00008000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK                                              0x00010000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK                                            0x00020000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK                                              0x00040000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK                                                   0x00080000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK                                                   0x00100000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK                                          0x00200000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK                                            0x00C00000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK                                   0x01000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK                                      0x02000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK                                          0x04000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK                                               0x08000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK                                              0x10000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK                                   0x20000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK                                               0xC0000000L
+//BIFP3_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT                                                   0x0
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT                                                0x4
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT                                  0x7
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT                                                 0x8
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT                                        0x9
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT                                               0xa
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT                                            0xb
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT                                          0xc
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT                                              0xd
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT                                      0xe
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT                                              0xf
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT                                               0x11
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT                                               0x12
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT                                         0x13
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT                                          0x14
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT                                          0x15
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT                                         0x17
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT                                       0x18
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT                                  0x19
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT                                    0x1a
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT                                0x1b
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT                                0x1c
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT                                     0x1d
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT                                        0x1e
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT                                      0x1f
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK                                                     0x00000007L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK                                                  0x00000070L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK                                    0x00000080L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK                                                   0x00000100L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK                                          0x00000200L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK                                                 0x00000400L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK                                              0x00000800L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK                                            0x00001000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK                                                0x00002000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK                                        0x00004000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK                                                0x00008000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK                                                 0x00020000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK                                                 0x00040000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK                                           0x00080000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK                                            0x00100000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK                                            0x00600000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK                                           0x00800000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK                                         0x01000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK                                    0x02000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK                                      0x04000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK                                  0x08000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK                                  0x10000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK                                       0x20000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK                                          0x40000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK                                        0x80000000L
+//BIFP3_PCIE_LC_N_FTS_CNTL
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT                                                        0x0
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT                                            0x8
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT                                          0x9
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT                                                         0xa
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT                                               0xe
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT                                              0xf
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT                                                  0x10
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT                                                             0x18
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK                                                          0x000000FFL
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK                                              0x00000100L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK                                            0x00000200L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK                                                           0x00000400L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK                                                 0x00004000L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK                                                0x00008000L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK                                                    0x00FF0000L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK                                                               0xFF000000L
+//BIFP3_PCIE_LC_SPEED_CNTL
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                                     0x0
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                                     0x1
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                                     0x2
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT                                     0x3
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT                                        0x4
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT                                          0x6
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT                                         0x7
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT                                          0x8
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT                                         0x9
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT                                        0xa
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0xb
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0xd
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT                                                 0xe
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT                                 0x10
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT                                         0x11
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT                                        0x12
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT                                         0x13
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT                                          0x14
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT                                         0x15
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT                                          0x16
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT                                         0x17
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT                                          0x18
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT                                               0x19
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT                                              0x1a
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT                                                   0x1c
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT                                    0x1d
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT                                          0x1e
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT                                           0x1f
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                                       0x00000001L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                                       0x00000002L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                                       0x00000004L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK                                       0x00000008L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK                                          0x00000030L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK                                            0x00000040L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK                                           0x00000080L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK                                            0x00000100L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK                                           0x00000200L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK                                          0x00000400L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x00001800L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00002000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK                                                   0x0000C000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK                                   0x00010000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK                                           0x00020000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK                                          0x00040000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK                                           0x00080000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK                                            0x00100000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK                                           0x00200000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK                                            0x00400000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK                                           0x00800000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK                                            0x01000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK                                                 0x02000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK                                                0x0C000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK                                                     0x10000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK                                      0x20000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK                                            0x40000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK                                             0x80000000L
+//BIFP3_PCIE_LC_STATE0
+#define BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT                                                         0x0
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT                                                           0x8
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT                                                           0x10
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT                                                           0x18
+#define BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK                                                           0x0000003FL
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK                                                             0x00003F00L
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK                                                             0x003F0000L
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK                                                             0x3F000000L
+//BIFP3_PCIE_LC_STATE1
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT                                                           0x0
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT                                                           0x8
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT                                                           0x10
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT                                                           0x18
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK                                                             0x0000003FL
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK                                                             0x00003F00L
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK                                                             0x003F0000L
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK                                                             0x3F000000L
+//BIFP3_PCIE_LC_STATE2
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT                                                           0x0
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT                                                           0x8
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT                                                          0x10
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT                                                          0x18
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK                                                             0x0000003FL
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK                                                             0x00003F00L
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK                                                            0x003F0000L
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK                                                            0x3F000000L
+//BIFP3_PCIE_LC_STATE3
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT                                                          0x0
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT                                                          0x8
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT                                                          0x10
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT                                                          0x18
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK                                                            0x0000003FL
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK                                                            0x00003F00L
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK                                                            0x003F0000L
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK                                                            0x3F000000L
+//BIFP3_PCIE_LC_STATE4
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT                                                          0x0
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT                                                          0x8
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT                                                          0x10
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT                                                          0x18
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK                                                            0x0000003FL
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK                                                            0x00003F00L
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK                                                            0x003F0000L
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK                                                            0x3F000000L
+//BIFP3_PCIE_LC_STATE5
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT                                                          0x0
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT                                                          0x8
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT                                                          0x10
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT                                                          0x18
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK                                                            0x0000003FL
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK                                                            0x00003F00L
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK                                                            0x003F0000L
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK                                                            0x3F000000L
+//BIFP3_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT                                                 0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT                                                 0x1
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT                                                  0x2
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT                                                  0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT                                                 0x4
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT                                                0x5
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT                                                0x6
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT                                          0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT                                         0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT                                          0xf
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT                                         0x13
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT                                          0x17
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT                                         0x1b
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK                                                   0x00000001L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK                                                   0x00000002L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK                                                    0x00000004L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK                                                    0x00000008L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK                                                   0x00000010L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK                                                  0x00000020L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK                                                  0x00000040L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK                                            0x00000780L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK                                           0x00007800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK                                            0x00078000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK                                           0x00780000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK                                            0x07800000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK                                           0x78000000L
+//BIFP3_PCIE_LC_CNTL2
+#define BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT                                                        0x0
+#define BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT                                                        0x6
+#define BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT                                                  0x7
+#define BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT                                                            0x8
+#define BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT                                                    0x9
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT                                                    0xa
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT                                                          0xb
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT                                               0xc
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT                                              0xd
+#define BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT                                                         0xe
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT                                         0x10
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT                                                       0x11
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT                                                      0x12
+#define BIFP3_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT                                              0x13
+#define BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT                                                    0x14
+#define BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT                                                  0x15
+#define BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT                                            0x16
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT                                               0x17
+#define BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT                                                 0x19
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT                                             0x1a
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                               0x1b
+#define BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT                                               0x1c
+#define BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT                                                         0x1d
+#define BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT                                       0x1f
+#define BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK                                                          0x0000003FL
+#define BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK                                                          0x00000040L
+#define BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK                                                    0x00000080L
+#define BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK                                                              0x00000100L
+#define BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK                                                      0x00000200L
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK                                                      0x00000400L
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK                                                            0x00000800L
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK                                                 0x00001000L
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK                                                0x00002000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK                                                           0x0000C000L
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK                                           0x00010000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK                                                         0x00020000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK                                                        0x00040000L
+#define BIFP3_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK                                                0x00080000L
+#define BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK                                                      0x00100000L
+#define BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK                                                    0x00200000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK                                              0x00400000L
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK                                                 0x01800000L
+#define BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK                                                   0x02000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK                                               0x04000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                                 0x08000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK                                                 0x10000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK                                                           0x60000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK                                         0x80000000L
+//BIFP3_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT                                              0x0
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT                                          0x1
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT                                          0x2
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT                                       0x3
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT                                      0x4
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT                                              0x5
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT                                                0x6
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT                                               0x7
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT                                               0x8
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT                                              0x9
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT                              0xa
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT                                        0xb
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK                                                0x00000001L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK                                            0x00000002L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK                                            0x00000004L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK                                         0x00000008L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK                                        0x00000010L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK                                                0x00000020L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK                                                  0x00000040L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK                                                 0x00000080L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK                                                 0x00000100L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK                                                0x00000200L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK                                0x00000400L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK                                          0x00000800L
+//BIFP3_PCIE_LC_CDR_CNTL
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT                                                        0x0
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT                                                       0xc
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT                                                        0x18
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK                                                          0x00000FFFL
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK                                                         0x00FFF000L
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK                                                          0x03000000L
+//BIFP3_PCIE_LC_LANE_CNTL
+#define BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT                                                    0x0
+#define BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK                                                      0x0000FFFFL
+//BIFP3_PCIE_LC_CNTL3
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT                                                      0x0
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT                                                 0x1
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT                                                        0x3
+#define BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT                                                         0x4
+#define BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT                                              0x5
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0x6
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0x8
+#define BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT                                         0x9
+#define BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT                                                   0xa
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT                                                   0xb
+#define BIFP3_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT                                                   0xc
+#define BIFP3_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT                                         0xd
+#define BIFP3_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT                                         0xe
+#define BIFP3_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT                                    0xf
+#define BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT                                                   0x11
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT                                          0x12
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT                                0x13
+#define BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT                                                  0x15
+#define BIFP3_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT                             0x16
+#define BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT                                       0x17
+#define BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT                                                  0x18
+#define BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT                                                      0x1a
+#define BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT                                                         0x1e
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT                                                      0x1f
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK                                                        0x00000001L
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK                                                   0x00000006L
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK                                                          0x00000008L
+#define BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK                                                           0x00000010L
+#define BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK                                                0x00000020L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x000000C0L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00000100L
+#define BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK                                           0x00000200L
+#define BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK                                                     0x00000400L
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK                                                     0x00000800L
+#define BIFP3_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK                                                     0x00001000L
+#define BIFP3_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK                                           0x00002000L
+#define BIFP3_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK                                           0x00004000L
+#define BIFP3_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK                                      0x00008000L
+#define BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK                                                     0x00020000L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK                                            0x00040000L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK                                  0x00180000L
+#define BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK                                                    0x00200000L
+#define BIFP3_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK                               0x00400000L
+#define BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK                                         0x00800000L
+#define BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK                                                    0x03000000L
+#define BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK                                                        0x3C000000L
+#define BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK                                                           0x40000000L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK                                                        0x80000000L
+//BIFP3_PCIE_LC_CNTL4
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT                                                    0x0
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT                                               0x2
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT                                            0x3
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT                                                          0x4
+#define BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT                                                            0x5
+#define BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT                                                           0x6
+#define BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT                                                          0x7
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT                                                     0x8
+#define BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT                                              0xa
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT                                                    0xb
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT                                                       0xc
+#define BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT                                                            0xd
+#define BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT                                                           0xe
+#define BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT                                             0xf
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT                                                0x10
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT                                       0x11
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT                                                 0x12
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT                                                        0x16
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT                                                               0x17
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT                                                  0x18
+#define BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT                                                      0x19
+#define BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT                                              0x1a
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK                                                      0x00000003L
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK                                                 0x00000004L
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK                                              0x00000008L
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK                                                            0x00000010L
+#define BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK                                                              0x00000020L
+#define BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK                                                             0x00000040L
+#define BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK                                                            0x00000080L
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK                                                       0x00000300L
+#define BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK                                                0x00000400L
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK                                                      0x00000800L
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK                                                         0x00001000L
+#define BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK                                                              0x00002000L
+#define BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK                                                             0x00004000L
+#define BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK                                               0x00008000L
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK                                                  0x00010000L
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK                                         0x00020000L
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK                                                   0x003C0000L
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK                                                          0x00400000L
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_SWING_MASK                                                                 0x00800000L
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK                                                    0x01000000L
+#define BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK                                                        0x02000000L
+#define BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK                                                0xFC000000L
+//BIFP3_PCIE_LC_CNTL5
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT                                                 0x0
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT                                                           0x2
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT                                                       0x6
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT                                                           0xa
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT                                                      0x10
+#define BIFP3_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT                                      0x15
+#define BIFP3_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT                                                      0x16
+#define BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT                                        0x18
+#define BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT                                                      0x19
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT                                                     0x1a
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT                                                0x1b
+#define BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT                                                         0x1c
+#define BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT                                                     0x1d
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK                                                   0x00000003L
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK                                                             0x0000003CL
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK                                                         0x000003C0L
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK                                                             0x0000FC00L
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK                                                        0x001F0000L
+#define BIFP3_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK                                        0x00200000L
+#define BIFP3_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK                                                        0x00C00000L
+#define BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK                                          0x01000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK                                                        0x02000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK                                                       0x04000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK                                                  0x08000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK                                                           0x10000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK                                                       0xE0000000L
+//BIFP3_PCIE_LC_FORCE_COEFF
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT                                                  0x0
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT                                             0x1
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT                                                 0x7
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT                                            0xd
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT                                          0x13
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT                                                     0x14
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK                                                    0x00000001L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK                                               0x0000007EL
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK                                                   0x00001F80L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK                                              0x0007E000L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK                                            0x00080000L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK                                                       0x00100000L
+//BIFP3_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT                                                 0x0
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT                                              0x4
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT                                                 0xa
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT                                             0x10
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT                                                    0x16
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT                                          0x1e
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK                                                   0x0000000FL
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK                                                0x000003F0L
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK                                                   0x0000FC00L
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK                                               0x003F0000L
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK                                                      0x3FC00000L
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK                                            0x40000000L
+//BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT                           0x0
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT                                  0x1
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT                                      0x7
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT                                 0xd
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT                                          0x13
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT                                          0x19
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK                             0x00000001L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK                                    0x0000007EL
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK                                        0x00001F80L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK                                   0x0007E000L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK                                            0x01F80000L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK                                            0x7E000000L
+//BIFP3_PCIE_LC_CNTL6
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT                                                         0x0
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT                                                           0x2
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT                                                           0x4
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT                                                          0x6
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT                                                                0x8
+#define BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT                                                      0x9
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT                                                     0xd
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT                                                 0xe
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT                                                   0x10
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT                                           0x12
+#define BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT                                                0x13
+#define BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT                                                     0x14
+#define BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT                                                           0x15
+#define BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT                                                               0x16
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT                                                           0x17
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT                                                      0x18
+#define BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT                                                      0x1f
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK                                                           0x00000003L
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK                                                             0x0000000CL
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK                                                             0x00000030L
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK                                                            0x000000C0L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN_MASK                                                                  0x00000100L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK                                                        0x00001E00L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK                                                       0x00002000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK                                                   0x0000C000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK                                                     0x00030000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK                                             0x00040000L
+#define BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK                                                  0x00080000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK                                                       0x00100000L
+#define BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK                                                             0x00200000L
+#define BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK                                                                 0x00400000L
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK                                                             0x00800000L
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK                                                        0x7F000000L
+#define BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK                                                        0x80000000L
+//BIFP3_PCIE_LC_CNTL7
+#define BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT                                              0x0
+#define BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT                                         0x1
+#define BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT                                             0x2
+#define BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT                                                   0x3
+#define BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT                                                     0x4
+#define BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT                                            0x5
+#define BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT                                                          0x6
+#define BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT                                                0x7
+#define BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT                                                     0x8
+#define BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT                                              0x9
+#define BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT                                               0xa
+#define BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT                                             0xb
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT                                          0xc
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT                                            0xd
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT                                                0x15
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT                                         0x16
+#define BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT                                                     0x17
+#define BIFP3_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT                                              0x18
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT                                                              0x19
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT                                                     0x1b
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT                                                      0x1c
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT                                                          0x1d
+#define BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT                                                          0x1e
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT                                                         0x1f
+#define BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK                                                0x00000001L
+#define BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK                                           0x00000002L
+#define BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK                                               0x00000004L
+#define BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK                                                     0x00000008L
+#define BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK                                                       0x00000010L
+#define BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK                                              0x00000020L
+#define BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK                                                            0x00000040L
+#define BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK                                                  0x00000080L
+#define BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK                                                       0x00000100L
+#define BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK                                                0x00000200L
+#define BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK                                                 0x00000400L
+#define BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK                                               0x00000800L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK                                            0x00001000L
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK                                              0x001FE000L
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK                                                  0x00200000L
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK                                           0x00400000L
+#define BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK                                                       0x00800000L
+#define BIFP3_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK                                                0x01000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_RATES_MASK                                                                0x06000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK                                                       0x08000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK                                                        0x10000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK                                                            0x20000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK                                                            0x40000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK                                                           0x80000000L
+//BIFP3_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT                                           0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                            0x1
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT                           0x2
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT                                           0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT                            0x4
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT                           0x5
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT                                 0x6
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT                                            0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT                                     0x8
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT                                         0x9
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT                                        0xa
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT                                    0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT                                    0xc
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT                                  0xd
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK                                             0x00000001L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK                              0x00000002L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK                             0x00000004L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK                                             0x00000008L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK                              0x00000010L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK                             0x00000020L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK                                   0x00000040L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK                                              0x00000080L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK                                       0x00000100L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK                                           0x00000200L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK                                          0x00000400L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK                                      0x00000800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK                                      0x00001000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK                                    0x00002000L
+//BIFP3_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT                                        0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x1
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT                        0x2
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT                                        0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x4
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT                        0x5
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT                              0x6
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT                                         0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT                                  0x8
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT                                      0x9
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT                                     0xa
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT                                 0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT                                 0xc
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT                               0xd
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK                                          0x00000001L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000002L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK                          0x00000004L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK                                          0x00000008L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000010L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK                          0x00000020L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK                                0x00000040L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK                                           0x00000080L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK                                    0x00000100L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK                                        0x00000200L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK                                       0x00000400L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK                                   0x00000800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK                                   0x00001000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK                                 0x00002000L
+//BIFP3_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT                                         0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT                                              0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT                                         0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT                                                       0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT                                             0xc
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT                                                      0xd
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT                                                    0xf
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT                                                   0x11
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT                                                  0x12
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT                                              0x13
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT                                             0x17
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT                                                 0x1b
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT                                               0x1e
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT                                              0x1f
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK                                           0x00000007L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK                                                0x00000078L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK                                           0x00000780L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK                                                         0x00000800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK                                               0x00001000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK                                                        0x00006000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK                                                      0x00018000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK                                                     0x00020000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK                                                    0x00040000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK                                                0x00780000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK                                               0x07800000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK                                                   0x38000000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK                                                 0x40000000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK                                                0x80000000L
+//BIFP3_PCIEP_STRAP_LC
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT                                                     0x0
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT                                                    0x2
+#define BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT                                                     0x4
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT                                                   0x6
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT                                                      0x8
+#define BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT                                                    0xb
+#define BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT                                                     0xc
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT                                                   0xd
+#define BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT                                                   0xe
+#define BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT                                      0xf
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT                                                   0x10
+#define BIFP3_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                            0x13
+#define BIFP3_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT                                             0x14
+#define BIFP3_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT                                             0x15
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK                                                       0x00000003L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK                                                      0x0000000CL
+#define BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK                                                       0x00000030L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK                                                     0x000000C0L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK                                                        0x00000700L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK                                                      0x00000800L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK                                                       0x00001000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK                                                     0x00002000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK                                                     0x00004000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK                                        0x00008000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK                                                     0x00070000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK                                              0x00080000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK                                               0x00100000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK                                               0x00200000L
+//BIFP3_PCIEP_STRAP_MISC
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT                                                    0x0
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT                                                    0x1
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT                                           0x2
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT                                                   0x3
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT                                                    0x5
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT                                                          0x6
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT                                         0x7
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK                                                      0x00000001L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK                                                      0x00000002L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK                                             0x00000004L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK                                                     0x00000018L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK                                                      0x00000020L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK                                                            0x00000040L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK                                           0x00000080L
+//BIFP3_PCIEP_STRAP_LC2
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT                                                0x0
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT                                             0x1
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT                                                  0x3
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT                                                    0x4
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT                                              0x7
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK                                                  0x00000001L
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK                                               0x00000006L
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK                                                    0x00000008L
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK                                                      0x00000070L
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK                                                0x00000380L
+//BIFP3_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT                                      0x0
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT                                          0x1
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT                                          0x2
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT                                            0x3
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT                                            0x4
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT                                              0x5
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT                                              0x6
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT                                              0x8
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT                                                0x10
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT                                                0x14
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT                                               0x17
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT                                 0x1a
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT                                   0x1b
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT                          0x1c
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK                                        0x00000001L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK                                            0x00000002L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK                                            0x00000004L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK                                              0x00000008L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK                                              0x00000010L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK                                                0x00000020L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK                                                0x000000C0L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK                                                0x00001F00L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK                                                  0x00070000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK                                                  0x00700000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK                                                 0x03800000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK                                   0x04000000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK                                     0x08000000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK                            0x10000000L
+//BIFP3_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT                                              0x0
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT                                          0x8
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK                                                0x000000FFL
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK                                            0x00000700L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+//BIFP3_PCIE_LC_PORT_ORDER
+#define BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT                                                       0x0
+#define BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK                                                         0x0000000FL
+//BIFP3_PCIEP_BCH_ECC_CNTL
+#define BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT                                                     0x0
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT                                              0x8
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT                                                 0x10
+#define BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK                                                       0x00000001L
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK                                                0x0000FF00L
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK                                                   0xFFFF0000L
+//BIFP3_PCIEP_HPGI_PRIVATE
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT                                      0x3
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT                                        0x6
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK                                        0x00000008L
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK                                          0x00000040L
+//BIFP3_PCIEP_HPGI
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT                                                    0x0
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT                                                    0x1
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT                                                  0x2
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT                                                  0x3
+#define BIFP3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT                                                                0x7
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT                                                0x8
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT                                                0x9
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT                                              0xa
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT                                              0xb
+#define BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT                                 0xf
+#define BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT                                     0x10
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK                                                      0x00000001L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK                                                      0x00000002L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK                                                    0x00000004L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK                                                    0x00000008L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_HOOK_MASK                                                                  0x00000080L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK                                                  0x00000100L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK                                                  0x00000200L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK                                                0x00000400L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK                                                0x00000800L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK                                   0x00008000L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK                                       0x00010000L
+//BIFP3_PCIEP_HCNT_DESCRIPTOR
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT                                    0x0
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT                                 0x1f
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK                                      0x00001FFFL
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK                                   0x80000000L
+//BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT                                          0x0
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT                                        0x10
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK                                            0x0000FFFFL
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK                                          0x00FF0000L
+//BIFP3_PCIE_LC_CNTL8
+#define BIFP3_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT                                                    0x0
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT                                                         0x2
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT                                                  0x3
+#define BIFP3_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT                                                           0x7
+#define BIFP3_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT                                                   0x8
+#define BIFP3_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT                                                      0x9
+#define BIFP3_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT                                            0xa
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT                                               0xb
+#define BIFP3_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT                                      0xc
+#define BIFP3_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT                                                0xd
+#define BIFP3_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT                                                        0x11
+#define BIFP3_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT                                                           0x12
+#define BIFP3_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT                                                       0x16
+#define BIFP3_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT                                                               0x17
+#define BIFP3_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT                                                         0x19
+#define BIFP3_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT                                                0x1a
+#define BIFP3_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT                                                 0x1b
+#define BIFP3_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT                                                         0x1c
+#define BIFP3_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT                                                0x1d
+#define BIFP3_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT                                             0x1e
+#define BIFP3_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK                                                      0x00000003L
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK                                                           0x00000004L
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK                                                    0x00000078L
+#define BIFP3_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK                                                             0x00000080L
+#define BIFP3_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK                                                     0x00000100L
+#define BIFP3_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK                                                        0x00000200L
+#define BIFP3_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK                                              0x00000400L
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK                                                 0x00000800L
+#define BIFP3_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK                                        0x00001000L
+#define BIFP3_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK                                                  0x0001E000L
+#define BIFP3_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK                                                          0x00020000L
+#define BIFP3_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK                                                             0x003C0000L
+#define BIFP3_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK                                                         0x00400000L
+#define BIFP3_PCIE_LC_CNTL8__LC_FOM_TIME_MASK                                                                 0x01800000L
+#define BIFP3_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK                                                           0x02000000L
+#define BIFP3_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK                                                  0x04000000L
+#define BIFP3_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK                                                   0x08000000L
+#define BIFP3_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK                                                           0x10000000L
+#define BIFP3_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK                                                  0x20000000L
+#define BIFP3_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK                                               0xC0000000L
+//BIFP3_PCIE_LC_CNTL9
+#define BIFP3_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT                                           0x0
+#define BIFP3_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT                                              0x1
+#define BIFP3_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT                                                0x3
+#define BIFP3_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT                                                       0x4
+#define BIFP3_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT                                                 0x6
+#define BIFP3_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT                                                 0x8
+#define BIFP3_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT                            0xa
+#define BIFP3_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT                                                   0xb
+#define BIFP3_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT                                               0xc
+#define BIFP3_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT                                                    0xd
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT                                                 0xe
+#define BIFP3_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT                                                 0x18
+#define BIFP3_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT                                                0x19
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT                                                  0x1a
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT                                                 0x1b
+#define BIFP3_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT                                              0x1c
+#define BIFP3_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT                               0x1d
+#define BIFP3_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT                                      0x1e
+#define BIFP3_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT                                      0x1f
+#define BIFP3_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK                                             0x00000001L
+#define BIFP3_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK                                                0x00000006L
+#define BIFP3_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK                                                  0x00000008L
+#define BIFP3_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK                                                         0x00000030L
+#define BIFP3_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK                                                   0x000000C0L
+#define BIFP3_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK                                                   0x00000300L
+#define BIFP3_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK                              0x00000400L
+#define BIFP3_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK                                                     0x00000800L
+#define BIFP3_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK                                                 0x00001000L
+#define BIFP3_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK                                                      0x00002000L
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK                                                   0x00FFC000L
+#define BIFP3_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK                                                   0x01000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK                                                  0x02000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK                                                    0x04000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK                                                   0x08000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK                                                0x10000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK                                 0x20000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK                                        0x40000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK                                        0x80000000L
+//BIFP3_PCIE_LC_FORCE_COEFF2
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT                                                0x0
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT                                           0x1
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT                                               0x7
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT                                          0xd
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT                                        0x13
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK                                                  0x00000001L
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK                                             0x0000007EL
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK                                                 0x00001F80L
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK                                            0x0007E000L
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK                                          0x00080000L
+//BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT                         0x0
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT                                0x1
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT                                    0x7
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT                               0xd
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT                                        0x13
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT                                        0x19
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK                           0x00000001L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK                                  0x0000007EL
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK                                      0x00001F80L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK                                 0x0007E000L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK                                          0x01F80000L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK                                          0x7E000000L
+//BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT                                       0x0
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT                                     0x10
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK                                         0x0000FFFFL
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK                                       0x00FF0000L
+//BIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT             0x0
+#define BIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT               0x1
+#define BIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK               0x00000001L
+#define BIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK                 0x00000002L
+//BIFP3_PCIE_LC_CNTL10
+#define BIFP3_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT                      0x0
+#define BIFP3_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT                                         0x1
+#define BIFP3_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT                                             0x2
+#define BIFP3_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT                                            0x4
+#define BIFP3_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT                                                       0x6
+#define BIFP3_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT                                                      0x10
+#define BIFP3_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT                                     0x1a
+#define BIFP3_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT                                                0x1b
+#define BIFP3_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT                                              0x1d
+#define BIFP3_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT                                 0x1e
+#define BIFP3_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT                                 0x1f
+#define BIFP3_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK                        0x00000001L
+#define BIFP3_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK                                           0x00000002L
+#define BIFP3_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK                                               0x0000000CL
+#define BIFP3_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK                                              0x00000030L
+#define BIFP3_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK                                                         0x0000FFC0L
+#define BIFP3_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK                                                        0x03FF0000L
+#define BIFP3_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK                                       0x04000000L
+#define BIFP3_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK                                                  0x18000000L
+#define BIFP3_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK                                                0x20000000L
+#define BIFP3_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK                                   0x40000000L
+#define BIFP3_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK                                   0x80000000L
+//BIFP3_PCIE_LC_CNTL11
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT                                            0x0
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT                                          0x1
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT                                          0x2
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT                                          0x3
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT                                         0x5
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT                                          0x9
+#define BIFP3_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT                                    0xd
+#define BIFP3_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT                                          0xe
+#define BIFP3_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT                                           0xf
+#define BIFP3_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT                                                0x10
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT                       0x11
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT                         0x12
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT                              0x13
+#define BIFP3_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT                        0x14
+#define BIFP3_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT                                   0x15
+#define BIFP3_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT                                        0x16
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT                                                               0x17
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT                                                        0x18
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT                                                             0x1a
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT                                                             0x1b
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT                                                   0x1c
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT                                                     0x1e
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK                                              0x00000001L
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK                                            0x00000002L
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK                                            0x00000004L
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK                                            0x00000018L
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK                                           0x000001E0L
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK                                            0x00001E00L
+#define BIFP3_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK                                      0x00002000L
+#define BIFP3_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK                                            0x00004000L
+#define BIFP3_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK                                             0x00008000L
+#define BIFP3_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK                                                  0x00010000L
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK                         0x00020000L
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK                           0x00040000L
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK                                0x00080000L
+#define BIFP3_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK                          0x00100000L
+#define BIFP3_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK                                     0x00200000L
+#define BIFP3_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK                                          0x00400000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_EN_MASK                                                                 0x00800000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK                                                          0x03000000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK                                                               0x04000000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK                                                               0x08000000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK                                                     0x30000000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK                                                       0xC0000000L
+//BIFP3_PCIE_LC_CNTL12
+#define BIFP3_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT                                         0x0
+#define BIFP3_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT                                0x1
+#define BIFP3_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT                                        0x2
+#define BIFP3_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT                                            0x3
+#define BIFP3_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT                                 0x4
+#define BIFP3_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT                                      0x5
+#define BIFP3_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT                                         0x6
+#define BIFP3_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT                                                     0x7
+#define BIFP3_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT                                           0x8
+#define BIFP3_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT                                       0x9
+#define BIFP3_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT                                              0xa
+#define BIFP3_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT                                   0xb
+#define BIFP3_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT                                                0xc
+#define BIFP3_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT                                             0xd
+#define BIFP3_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT                                            0xe
+#define BIFP3_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT                                                0xf
+#define BIFP3_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT                                0x10
+#define BIFP3_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT                              0x11
+#define BIFP3_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT                            0x12
+#define BIFP3_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT                                          0x13
+#define BIFP3_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT                                                 0x14
+#define BIFP3_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT                                          0x15
+#define BIFP3_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT                                             0x16
+#define BIFP3_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT                                            0x17
+#define BIFP3_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT                                            0x1f
+#define BIFP3_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK                                           0x00000001L
+#define BIFP3_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK                                  0x00000002L
+#define BIFP3_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK                                          0x00000004L
+#define BIFP3_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK                                              0x00000008L
+#define BIFP3_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK                                   0x00000010L
+#define BIFP3_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK                                        0x00000020L
+#define BIFP3_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK                                           0x00000040L
+#define BIFP3_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK                                                       0x00000080L
+#define BIFP3_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK                                             0x00000100L
+#define BIFP3_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK                                         0x00000200L
+#define BIFP3_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK                                                0x00000400L
+#define BIFP3_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK                                     0x00000800L
+#define BIFP3_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK                                                  0x00001000L
+#define BIFP3_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK                                               0x00002000L
+#define BIFP3_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK                                              0x00004000L
+#define BIFP3_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK                                                  0x00008000L
+#define BIFP3_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK                                  0x00010000L
+#define BIFP3_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK                                0x00020000L
+#define BIFP3_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK                              0x00040000L
+#define BIFP3_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK                                            0x00080000L
+#define BIFP3_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK                                                   0x00100000L
+#define BIFP3_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK                                            0x00200000L
+#define BIFP3_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK                                               0x00400000L
+#define BIFP3_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK                                              0x00800000L
+#define BIFP3_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK                                              0x80000000L
+//BIFP3_PCIE_LC_SAVE_RESTORE_1
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT                                               0x0
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT                                        0x1
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT                                            0x2
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT                                      0xa
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT                                             0xb
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT                                  0xc
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT                                    0xd
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT                                           0xe
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT                                          0x10
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK                                                 0x00000001L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK                                          0x00000002L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK                                              0x000003FCL
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK                                        0x00000400L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK                                               0x00000800L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK                                    0x00001000L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK                                      0x00002000L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK                                             0x0000C000L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK                                            0xFFFF0000L
+//BIFP3_PCIE_LC_SAVE_RESTORE_2
+#define BIFP3_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT                                          0x0
+#define BIFP3_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK                                            0xFFFFFFFFL
+//BIFP3_PCIE_LC_SAVE_RESTORE_3
+#define BIFP3_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT                                0x0
+#define BIFP3_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK                                  0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp4_pciedir_p
+//BIFP4_PCIEP_RESERVED
+#define BIFP4_PCIEP_RESERVED__RESERVED__SHIFT                                                                 0x0
+#define BIFP4_PCIEP_RESERVED__RESERVED_MASK                                                                   0xFFFFFFFFL
+//BIFP4_PCIEP_SCRATCH
+#define BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT                                                             0x0
+#define BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK                                                               0xFFFFFFFFL
+//BIFP4_PCIEP_PORT_CNTL
+#define BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT                                                         0x0
+#define BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT                                                       0x1
+#define BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT                                                          0x2
+#define BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT                                                           0x3
+#define BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT                                                            0x4
+#define BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT                                                              0x5
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT                                         0x8
+#define BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT                                            0x12
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT                                             0x18
+#define BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT                                            0x1a
+#define BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK                                                           0x00000001L
+#define BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK                                                         0x00000002L
+#define BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK                                                            0x00000004L
+#define BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK                                                             0x00000008L
+#define BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK                                                              0x00000010L
+#define BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK                                                                0x00000020L
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK                                           0x0003FF00L
+#define BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK                                              0x001C0000L
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK                                               0x03000000L
+#define BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK                                              0x0C000000L
+//BIFP4_PCIE_TX_CNTL
+#define BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                            0xa
+#define BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                             0xc
+#define BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT                                                         0xe
+#define BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT                                                           0xf
+#define BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT                                                              0x14
+#define BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT                                                               0x15
+#define BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT                                                     0x16
+#define BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT                                                   0x17
+#define BIFP4_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT                                              0x1b
+#define BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                              0x00000C00L
+#define BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                               0x00003000L
+#define BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK                                                           0x00004000L
+#define BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK                                                             0x00008000L
+#define BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK                                                                0x00100000L
+#define BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK                                                                 0x00200000L
+#define BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK                                                       0x00400000L
+#define BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK                                                     0x00800000L
+#define BIFP4_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK                                                0x08000000L
+//BIFP4_PCIE_TX_REQUESTER_ID
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                           0x0
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                             0x3
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                                0x8
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                             0x00000007L
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                               0x000000F8L
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                                  0x0000FF00L
+//BIFP4_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT                                                  0x18
+#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK                                                    0x01000000L
+//BIFP4_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT                                          0x18
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT                                   0x1e
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT                                       0x1f
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK                                            0x3F000000L
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK                                     0x40000000L
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK                                         0x80000000L
+//BIFP4_PCIE_TX_SEQ
+#define BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT                                                        0x0
+#define BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT                                                                 0x10
+#define BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK                                                          0x00000FFFL
+#define BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK                                                                   0x0FFF0000L
+//BIFP4_PCIE_TX_REPLAY
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT                                                            0x0
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT                                                      0xe
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT                                                0xf
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT                                                          0x10
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK                                                              0x00000007L
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK                                                        0x00004000L
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK                                                  0x00008000L
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK                                                            0xFFFF0000L
+//BIFP4_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT                                          0x0
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT                                0xc
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK                                            0x00000FFFL
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK                                  0x00001000L
+//BIFP4_PCIE_TX_NOP_DLLP
+#define BIFP4_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT                                                            0x0
+#define BIFP4_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT                                                            0x18
+#define BIFP4_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK                                                              0x00FFFFFFL
+#define BIFP4_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK                                                              0x01000000L
+//BIFP4_PCIE_TX_CNTL_2
+//BIFP4_PCIE_TX_SKID_CTRL
+#define BIFP4_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT                                                  0x0
+#define BIFP4_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT                                            0x4
+#define BIFP4_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK                                                    0x0000000FL
+#define BIFP4_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK                                              0x00000010L
+//BIFP4_PCIE_TX_CREDITS_ADVT_P
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT                                               0x0
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT                                               0x10
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK                                                 0x00003FFFL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK                                                 0x03FF0000L
+//BIFP4_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT                                             0x0
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT                                             0x10
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK                                               0x00003FFFL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK                                               0x03FF0000L
+//BIFP4_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT                                           0x0
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT                                           0x10
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK                                             0x00003FFFL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK                                             0x03FF0000L
+//BIFP4_PCIE_TX_CREDITS_INIT_P
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT                                               0x0
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT                                               0x10
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK                                                 0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK                                                 0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_INIT_NP
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT                                             0x0
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT                                             0x10
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK                                               0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK                                               0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT                                           0x0
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT                                           0x10
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK                                             0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK                                             0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_STATUS
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT                                                0x0
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT                                                0x1
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT                                               0x2
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT                                               0x3
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT                                              0x4
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT                                              0x5
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT                                         0x10
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT                                         0x11
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT                                        0x12
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT                                        0x13
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT                                       0x14
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT                                       0x15
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK                                                  0x00000001L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK                                                  0x00000002L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK                                                 0x00000004L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK                                                 0x00000008L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK                                                0x00000010L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK                                                0x00000020L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK                                           0x00010000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK                                           0x00020000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK                                          0x00040000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK                                          0x00080000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK                                         0x00100000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK                                         0x00200000L
+//BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT                                    0x0
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT                                   0x4
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT                                  0x8
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT                                    0x10
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT                                   0x14
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT                                  0x18
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK                                      0x00000007L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK                                     0x00000070L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK                                    0x00000700L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK                                      0x00070000L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK                                     0x00700000L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK                                    0x07000000L
+//BIFP4_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT                                          0x0
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT                                                  0x3
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT                                           0x6
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT                                                   0x8
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT                                                   0x10
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT                                       0x19
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT                                              0x1c
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK                                            0x00000007L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK                                                    0x00000038L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK                                             0x00000040L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK                                                     0x00003F00L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK                                                     0x003F0000L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK                                         0x02000000L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK                                                0xF0000000L
+//BIFP4_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT                                      0x0
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK                                        0x0000FFFFL
+//BIFP4_PCIE_CCIX_STACKED_BASE
+#define BIFP4_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT                                           0x4
+#define BIFP4_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK                                             0xFFFFFFF0L
+//BIFP4_PCIE_CCIX_STACKED_LIMIT
+#define BIFP4_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT                                         0x4
+#define BIFP4_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK                                           0xFFFFFFF0L
+//BIFP4_PCIE_CCIX_MISC_STATUS
+#define BIFP4_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT                                              0x0
+#define BIFP4_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT                                          0x1
+#define BIFP4_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK                                                0x00000001L
+#define BIFP4_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK                                            0x00000002L
+//BIFP4_PCIE_P_PORT_LANE_STATUS
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT                                              0x0
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT                                                  0x1
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK                                                0x00000001L
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK                                                    0x0000007EL
+//BIFP4_PCIE_FC_P
+#define BIFP4_PCIE_FC_P__PD_CREDITS__SHIFT                                                                    0x0
+#define BIFP4_PCIE_FC_P__PH_CREDITS__SHIFT                                                                    0x10
+#define BIFP4_PCIE_FC_P__PD_CREDITS_MASK                                                                      0x0000FFFFL
+#define BIFP4_PCIE_FC_P__PH_CREDITS_MASK                                                                      0x0FFF0000L
+//BIFP4_PCIE_FC_NP
+#define BIFP4_PCIE_FC_NP__NPD_CREDITS__SHIFT                                                                  0x0
+#define BIFP4_PCIE_FC_NP__NPH_CREDITS__SHIFT                                                                  0x10
+#define BIFP4_PCIE_FC_NP__NPD_CREDITS_MASK                                                                    0x0000FFFFL
+#define BIFP4_PCIE_FC_NP__NPH_CREDITS_MASK                                                                    0x0FFF0000L
+//BIFP4_PCIE_FC_CPL
+#define BIFP4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT                                                                0x0
+#define BIFP4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT                                                                0x10
+#define BIFP4_PCIE_FC_CPL__CPLD_CREDITS_MASK                                                                  0x0000FFFFL
+#define BIFP4_PCIE_FC_CPL__CPLH_CREDITS_MASK                                                                  0x0FFF0000L
+//BIFP4_PCIE_FC_P_VC1
+#define BIFP4_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT                                                    0x0
+#define BIFP4_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT                                                    0x10
+#define BIFP4_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK                                                      0x0000FFFFL
+#define BIFP4_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK                                                      0x0FFF0000L
+//BIFP4_PCIE_FC_NP_VC1
+#define BIFP4_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT                                                  0x0
+#define BIFP4_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT                                                  0x10
+#define BIFP4_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK                                                    0x0000FFFFL
+#define BIFP4_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK                                                    0x0FFF0000L
+//BIFP4_PCIE_FC_CPL_VC1
+#define BIFP4_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT                                                0x0
+#define BIFP4_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT                                                0x10
+#define BIFP4_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK                                                  0x0000FFFFL
+#define BIFP4_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK                                                  0x0FFF0000L
+//BIFP4_PCIE_ERR_CNTL
+#define BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                         0x0
+#define BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT                                                  0x1
+#define BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT                                                     0x2
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT                                                      0x4
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT                                                      0x5
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT                                                      0x6
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT                                                      0x7
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                                       0x8
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                              0xb
+#define BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT                                               0xe
+#define BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT                                              0xf
+#define BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT                                                     0x10
+#define BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                                  0x11
+#define BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                                          0x12
+#define BIFP4_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT                                                    0x13
+#define BIFP4_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT                                                     0x14
+#define BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                           0x00000001L
+#define BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK                                                    0x00000002L
+#define BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK                                                       0x00000004L
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK                                                        0x00000010L
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK                                                        0x00000020L
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK                                                        0x00000040L
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK                                                        0x00000080L
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                         0x00000700L
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                                0x00000800L
+#define BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK                                                 0x00004000L
+#define BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK                                                0x00008000L
+#define BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK                                                       0x00010000L
+#define BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                                    0x00020000L
+#define BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                            0x00040000L
+#define BIFP4_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK                                                      0x00080000L
+#define BIFP4_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK                                                       0x00100000L
+//BIFP4_PCIE_RX_CNTL
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT                                                           0x0
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT                                                           0x1
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT                                                          0x2
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT                                                          0x3
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT                                                          0x4
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT                                                          0x5
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT                                                           0x6
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT                                                 0x7
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                                  0x8
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                           0x9
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT                                                           0xa
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT                                                            0xb
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT                                                           0xc
+#define BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT                                                        0xd
+#define BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT                                                        0xf
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT                                                         0x10
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT                                                    0x13
+#define BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                                    0x14
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                                  0x15
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                                    0x16
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT                                                    0x17
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                                 0x18
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                                     0x19
+#define BIFP4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                                 0x1a
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                                     0x1b
+#define BIFP4_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT                                                              0x1c
+#define BIFP4_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT                                                0x1d
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK                                                             0x00000001L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK                                                             0x00000002L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK                                                            0x00000004L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK                                                            0x00000008L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK                                                            0x00000010L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK                                                            0x00000020L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK                                                             0x00000040L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK                                                   0x00000080L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                                    0x00000100L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                             0x00000200L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK                                                             0x00000400L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK                                                              0x00000800L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK                                                             0x00001000L
+#define BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK                                                          0x00002000L
+#define BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK                                                          0x00008000L
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK                                                           0x00070000L
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK                                                      0x00080000L
+#define BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                                      0x00100000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                                    0x00200000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                                      0x00400000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK                                                      0x00800000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                                   0x01000000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                                       0x02000000L
+#define BIFP4_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                                   0x04000000L
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                                       0x08000000L
+#define BIFP4_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK                                                                0x10000000L
+#define BIFP4_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK                                                  0x20000000L
+//BIFP4_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT                                              0x0
+#define BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK                                                0x00000FFFL
+//BIFP4_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT                                                0x18
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK                                                  0x01000000L
+//BIFP4_PCIE_RX_CNTL3
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT                                             0x0
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT                                             0x1
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT                                                0x2
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT                                                    0x3
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT                                               0x4
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK                                               0x00000001L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK                                               0x00000002L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK                                                  0x00000004L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK                                                      0x00000008L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK                                                 0x00000010L
+//BIFP4_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT                                     0x0
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT                                     0x10
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK                                       0x00000FFFL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK                                       0x00FF0000L
+//BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT                                   0x0
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT                                   0x10
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK                                     0x00000FFFL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK                                     0x00FF0000L
+//BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT                                 0x0
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT                                 0x10
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK                                   0x00000FFFL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK                                   0x00FF0000L
+//BIFP4_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT                                    0x0
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT                                 0x2
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT                           0x4
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT                             0x6
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT                              0x8
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT                              0xa
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT                                  0xc
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT                         0xe
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT                            0x10
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT                                0x12
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT                           0x14
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT                             0x16
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK                                      0x00000003L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK                                   0x0000000CL
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK                             0x00000030L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK                               0x000000C0L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK                                0x00000300L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK                                0x00000C00L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK                                    0x00003000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK                           0x0000C000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK                              0x00030000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK                                  0x000C0000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK                             0x00300000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK                               0x00C00000L
+//BIFP4_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT                             0x0
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT                      0x2
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT                                 0x4
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT                                  0x6
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT                          0x8
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT                               0xa
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT                            0xc
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT                         0xe
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT                          0x10
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT                       0x12
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK                               0x00000003L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK                        0x0000000CL
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK                                   0x00000030L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK                                    0x000000C0L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK                            0x00000300L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK                                 0x00000C00L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK                              0x00003000L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK                           0x0000C000L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK                            0x00030000L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK                         0x000C0000L
+//BIFP4_PCIEP_NAK_COUNTER
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT                                              0x0
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT                                             0x10
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK                                                0x0000FFFFL
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK                                               0xFFFF0000L
+//BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT                     0x0
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT                     0xa
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT                      0xf
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT                  0x10
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT                  0x1a
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT                   0x1f
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK                       0x000003FFL
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK                       0x00001C00L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK                        0x00008000L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK                    0x03FF0000L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK                    0x1C000000L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK                     0x80000000L
+//BIFP4_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP4_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT                                    0x5
+#define BIFP4_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK                                      0x00000020L
+//BIFP4_PCIE_AER_PRIV_TRIGGER
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT                          0x0
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT                           0x1
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT                         0x2
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK                            0x00000001L
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK                             0x00000002L
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK                           0x00000004L
+//BIFP4_PCIE_LC_CNTL
+#define BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT                                                    0x1
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT                                                   0x2
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT                                                              0x3
+#define BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT                                                       0x4
+#define BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT                                                          0x8
+#define BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT                                                           0xc
+#define BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT                                                           0x10
+#define BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT                                                            0x11
+#define BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT                                                  0x12
+#define BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT                                                      0x14
+#define BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT                                                     0x15
+#define BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT                                                           0x16
+#define BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT                                                        0x17
+#define BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT                                                          0x18
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT                                                             0x19
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT                                                          0x1b
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT                                                           0x1c
+#define BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT                                                 0x1d
+#define BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT                                                         0x1e
+#define BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT                                                          0x1f
+#define BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK                                                      0x00000002L
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK                                                     0x00000004L
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_LINK_MASK                                                                0x00000008L
+#define BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK                                                         0x000000F0L
+#define BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK                                                            0x00000F00L
+#define BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK                                                             0x0000F000L
+#define BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK                                                             0x00010000L
+#define BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK                                                              0x00020000L
+#define BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK                                                    0x000C0000L
+#define BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK                                                        0x00100000L
+#define BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK                                                       0x00200000L
+#define BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK                                                             0x00400000L
+#define BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK                                                          0x00800000L
+#define BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK                                                            0x01000000L
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK                                                               0x06000000L
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK                                                            0x08000000L
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK                                                             0x10000000L
+#define BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK                                                   0x20000000L
+#define BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK                                                           0x40000000L
+#define BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK                                                            0x80000000L
+//BIFP4_PCIE_LC_TRAINING_CNTL
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT                                                  0x0
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT                                             0x4
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT                                 0x5
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT                                        0x6
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT                                            0x7
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT                                                    0x8
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT                                     0xb
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT                                       0xc
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT                                      0xd
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT                                          0xe
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT                                        0xf
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT                                            0x10
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT                                          0x11
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT                                            0x12
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT                                                 0x13
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT                                                 0x14
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT                                        0x15
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT                                          0x16
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT                                 0x18
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT                                    0x19
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT                                        0x1a
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT                                             0x1b
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT                                            0x1c
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT                                 0x1d
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT                                             0x1e
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK                                                    0x0000000FL
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK                                               0x00000010L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK                                   0x00000020L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK                                          0x00000040L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK                                              0x00000080L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK                                                      0x00000700L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK                                       0x00000800L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK                                         0x00001000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK                                        0x00002000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK                                            0x00004000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK                                          0x00008000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK                                              0x00010000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK                                            0x00020000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK                                              0x00040000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK                                                   0x00080000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK                                                   0x00100000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK                                          0x00200000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK                                            0x00C00000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK                                   0x01000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK                                      0x02000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK                                          0x04000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK                                               0x08000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK                                              0x10000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK                                   0x20000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK                                               0xC0000000L
+//BIFP4_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT                                                   0x0
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT                                                0x4
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT                                  0x7
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT                                                 0x8
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT                                        0x9
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT                                               0xa
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT                                            0xb
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT                                          0xc
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT                                              0xd
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT                                      0xe
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT                                              0xf
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT                                               0x11
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT                                               0x12
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT                                         0x13
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT                                          0x14
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT                                          0x15
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT                                         0x17
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT                                       0x18
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT                                  0x19
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT                                    0x1a
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT                                0x1b
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT                                0x1c
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT                                     0x1d
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT                                        0x1e
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT                                      0x1f
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK                                                     0x00000007L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK                                                  0x00000070L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK                                    0x00000080L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK                                                   0x00000100L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK                                          0x00000200L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK                                                 0x00000400L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK                                              0x00000800L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK                                            0x00001000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK                                                0x00002000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK                                        0x00004000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK                                                0x00008000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK                                                 0x00020000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK                                                 0x00040000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK                                           0x00080000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK                                            0x00100000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK                                            0x00600000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK                                           0x00800000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK                                         0x01000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK                                    0x02000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK                                      0x04000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK                                  0x08000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK                                  0x10000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK                                       0x20000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK                                          0x40000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK                                        0x80000000L
+//BIFP4_PCIE_LC_N_FTS_CNTL
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT                                                        0x0
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT                                            0x8
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT                                          0x9
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT                                                         0xa
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT                                               0xe
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT                                              0xf
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT                                                  0x10
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT                                                             0x18
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK                                                          0x000000FFL
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK                                              0x00000100L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK                                            0x00000200L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK                                                           0x00000400L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK                                                 0x00004000L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK                                                0x00008000L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK                                                    0x00FF0000L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK                                                               0xFF000000L
+//BIFP4_PCIE_LC_SPEED_CNTL
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                                     0x0
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                                     0x1
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                                     0x2
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT                                     0x3
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT                                        0x4
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT                                          0x6
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT                                         0x7
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT                                          0x8
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT                                         0x9
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT                                        0xa
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0xb
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0xd
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT                                                 0xe
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT                                 0x10
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT                                         0x11
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT                                        0x12
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT                                         0x13
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT                                          0x14
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT                                         0x15
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT                                          0x16
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT                                         0x17
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT                                          0x18
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT                                               0x19
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT                                              0x1a
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT                                                   0x1c
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT                                    0x1d
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT                                          0x1e
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT                                           0x1f
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                                       0x00000001L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                                       0x00000002L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                                       0x00000004L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK                                       0x00000008L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK                                          0x00000030L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK                                            0x00000040L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK                                           0x00000080L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK                                            0x00000100L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK                                           0x00000200L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK                                          0x00000400L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x00001800L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00002000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK                                                   0x0000C000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK                                   0x00010000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK                                           0x00020000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK                                          0x00040000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK                                           0x00080000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK                                            0x00100000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK                                           0x00200000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK                                            0x00400000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK                                           0x00800000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK                                            0x01000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK                                                 0x02000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK                                                0x0C000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK                                                     0x10000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK                                      0x20000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK                                            0x40000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK                                             0x80000000L
+//BIFP4_PCIE_LC_STATE0
+#define BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT                                                         0x0
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT                                                           0x8
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT                                                           0x10
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT                                                           0x18
+#define BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK                                                           0x0000003FL
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK                                                             0x00003F00L
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK                                                             0x003F0000L
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK                                                             0x3F000000L
+//BIFP4_PCIE_LC_STATE1
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT                                                           0x0
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT                                                           0x8
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT                                                           0x10
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT                                                           0x18
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK                                                             0x0000003FL
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK                                                             0x00003F00L
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK                                                             0x003F0000L
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK                                                             0x3F000000L
+//BIFP4_PCIE_LC_STATE2
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT                                                           0x0
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT                                                           0x8
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT                                                          0x10
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT                                                          0x18
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK                                                             0x0000003FL
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK                                                             0x00003F00L
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK                                                            0x003F0000L
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK                                                            0x3F000000L
+//BIFP4_PCIE_LC_STATE3
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT                                                          0x0
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT                                                          0x8
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT                                                          0x10
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT                                                          0x18
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK                                                            0x0000003FL
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK                                                            0x00003F00L
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK                                                            0x003F0000L
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK                                                            0x3F000000L
+//BIFP4_PCIE_LC_STATE4
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT                                                          0x0
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT                                                          0x8
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT                                                          0x10
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT                                                          0x18
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK                                                            0x0000003FL
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK                                                            0x00003F00L
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK                                                            0x003F0000L
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK                                                            0x3F000000L
+//BIFP4_PCIE_LC_STATE5
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT                                                          0x0
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT                                                          0x8
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT                                                          0x10
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT                                                          0x18
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK                                                            0x0000003FL
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK                                                            0x00003F00L
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK                                                            0x003F0000L
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK                                                            0x3F000000L
+//BIFP4_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT                                                 0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT                                                 0x1
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT                                                  0x2
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT                                                  0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT                                                 0x4
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT                                                0x5
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT                                                0x6
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT                                          0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT                                         0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT                                          0xf
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT                                         0x13
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT                                          0x17
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT                                         0x1b
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK                                                   0x00000001L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK                                                   0x00000002L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK                                                    0x00000004L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK                                                    0x00000008L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK                                                   0x00000010L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK                                                  0x00000020L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK                                                  0x00000040L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK                                            0x00000780L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK                                           0x00007800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK                                            0x00078000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK                                           0x00780000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK                                            0x07800000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK                                           0x78000000L
+//BIFP4_PCIE_LC_CNTL2
+#define BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT                                                        0x0
+#define BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT                                                        0x6
+#define BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT                                                  0x7
+#define BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT                                                            0x8
+#define BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT                                                    0x9
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT                                                    0xa
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT                                                          0xb
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT                                               0xc
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT                                              0xd
+#define BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT                                                         0xe
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT                                         0x10
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT                                                       0x11
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT                                                      0x12
+#define BIFP4_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT                                              0x13
+#define BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT                                                    0x14
+#define BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT                                                  0x15
+#define BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT                                            0x16
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT                                               0x17
+#define BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT                                                 0x19
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT                                             0x1a
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                               0x1b
+#define BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT                                               0x1c
+#define BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT                                                         0x1d
+#define BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT                                       0x1f
+#define BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK                                                          0x0000003FL
+#define BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK                                                          0x00000040L
+#define BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK                                                    0x00000080L
+#define BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK                                                              0x00000100L
+#define BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK                                                      0x00000200L
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK                                                      0x00000400L
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK                                                            0x00000800L
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK                                                 0x00001000L
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK                                                0x00002000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK                                                           0x0000C000L
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK                                           0x00010000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK                                                         0x00020000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK                                                        0x00040000L
+#define BIFP4_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK                                                0x00080000L
+#define BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK                                                      0x00100000L
+#define BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK                                                    0x00200000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK                                              0x00400000L
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK                                                 0x01800000L
+#define BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK                                                   0x02000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK                                               0x04000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                                 0x08000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK                                                 0x10000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK                                                           0x60000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK                                         0x80000000L
+//BIFP4_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT                                              0x0
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT                                          0x1
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT                                          0x2
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT                                       0x3
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT                                      0x4
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT                                              0x5
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT                                                0x6
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT                                               0x7
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT                                               0x8
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT                                              0x9
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT                              0xa
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT                                        0xb
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK                                                0x00000001L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK                                            0x00000002L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK                                            0x00000004L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK                                         0x00000008L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK                                        0x00000010L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK                                                0x00000020L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK                                                  0x00000040L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK                                                 0x00000080L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK                                                 0x00000100L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK                                                0x00000200L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK                                0x00000400L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK                                          0x00000800L
+//BIFP4_PCIE_LC_CDR_CNTL
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT                                                        0x0
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT                                                       0xc
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT                                                        0x18
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK                                                          0x00000FFFL
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK                                                         0x00FFF000L
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK                                                          0x03000000L
+//BIFP4_PCIE_LC_LANE_CNTL
+#define BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT                                                    0x0
+#define BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK                                                      0x0000FFFFL
+//BIFP4_PCIE_LC_CNTL3
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT                                                      0x0
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT                                                 0x1
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT                                                        0x3
+#define BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT                                                         0x4
+#define BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT                                              0x5
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0x6
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0x8
+#define BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT                                         0x9
+#define BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT                                                   0xa
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT                                                   0xb
+#define BIFP4_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT                                                   0xc
+#define BIFP4_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT                                         0xd
+#define BIFP4_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT                                         0xe
+#define BIFP4_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT                                    0xf
+#define BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT                                                   0x11
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT                                          0x12
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT                                0x13
+#define BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT                                                  0x15
+#define BIFP4_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT                             0x16
+#define BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT                                       0x17
+#define BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT                                                  0x18
+#define BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT                                                      0x1a
+#define BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT                                                         0x1e
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT                                                      0x1f
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK                                                        0x00000001L
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK                                                   0x00000006L
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK                                                          0x00000008L
+#define BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK                                                           0x00000010L
+#define BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK                                                0x00000020L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x000000C0L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00000100L
+#define BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK                                           0x00000200L
+#define BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK                                                     0x00000400L
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK                                                     0x00000800L
+#define BIFP4_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK                                                     0x00001000L
+#define BIFP4_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK                                           0x00002000L
+#define BIFP4_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK                                           0x00004000L
+#define BIFP4_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK                                      0x00008000L
+#define BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK                                                     0x00020000L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK                                            0x00040000L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK                                  0x00180000L
+#define BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK                                                    0x00200000L
+#define BIFP4_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK                               0x00400000L
+#define BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK                                         0x00800000L
+#define BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK                                                    0x03000000L
+#define BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK                                                        0x3C000000L
+#define BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK                                                           0x40000000L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK                                                        0x80000000L
+//BIFP4_PCIE_LC_CNTL4
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT                                                    0x0
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT                                               0x2
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT                                            0x3
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT                                                          0x4
+#define BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT                                                            0x5
+#define BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT                                                           0x6
+#define BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT                                                          0x7
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT                                                     0x8
+#define BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT                                              0xa
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT                                                    0xb
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT                                                       0xc
+#define BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT                                                            0xd
+#define BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT                                                           0xe
+#define BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT                                             0xf
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT                                                0x10
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT                                       0x11
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT                                                 0x12
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT                                                        0x16
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT                                                               0x17
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT                                                  0x18
+#define BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT                                                      0x19
+#define BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT                                              0x1a
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK                                                      0x00000003L
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK                                                 0x00000004L
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK                                              0x00000008L
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK                                                            0x00000010L
+#define BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK                                                              0x00000020L
+#define BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK                                                             0x00000040L
+#define BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK                                                            0x00000080L
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK                                                       0x00000300L
+#define BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK                                                0x00000400L
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK                                                      0x00000800L
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK                                                         0x00001000L
+#define BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK                                                              0x00002000L
+#define BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK                                                             0x00004000L
+#define BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK                                               0x00008000L
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK                                                  0x00010000L
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK                                         0x00020000L
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK                                                   0x003C0000L
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK                                                          0x00400000L
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_SWING_MASK                                                                 0x00800000L
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK                                                    0x01000000L
+#define BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK                                                        0x02000000L
+#define BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK                                                0xFC000000L
+//BIFP4_PCIE_LC_CNTL5
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT                                                 0x0
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT                                                           0x2
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT                                                       0x6
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT                                                           0xa
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT                                                      0x10
+#define BIFP4_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT                                      0x15
+#define BIFP4_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT                                                      0x16
+#define BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT                                        0x18
+#define BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT                                                      0x19
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT                                                     0x1a
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT                                                0x1b
+#define BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT                                                         0x1c
+#define BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT                                                     0x1d
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK                                                   0x00000003L
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK                                                             0x0000003CL
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK                                                         0x000003C0L
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK                                                             0x0000FC00L
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK                                                        0x001F0000L
+#define BIFP4_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK                                        0x00200000L
+#define BIFP4_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK                                                        0x00C00000L
+#define BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK                                          0x01000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK                                                        0x02000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK                                                       0x04000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK                                                  0x08000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK                                                           0x10000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK                                                       0xE0000000L
+//BIFP4_PCIE_LC_FORCE_COEFF
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT                                                  0x0
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT                                             0x1
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT                                                 0x7
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT                                            0xd
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT                                          0x13
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT                                                     0x14
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK                                                    0x00000001L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK                                               0x0000007EL
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK                                                   0x00001F80L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK                                              0x0007E000L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK                                            0x00080000L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK                                                       0x00100000L
+//BIFP4_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT                                                 0x0
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT                                              0x4
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT                                                 0xa
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT                                             0x10
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT                                                    0x16
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT                                          0x1e
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK                                                   0x0000000FL
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK                                                0x000003F0L
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK                                                   0x0000FC00L
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK                                               0x003F0000L
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK                                                      0x3FC00000L
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK                                            0x40000000L
+//BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT                           0x0
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT                                  0x1
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT                                      0x7
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT                                 0xd
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT                                          0x13
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT                                          0x19
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK                             0x00000001L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK                                    0x0000007EL
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK                                        0x00001F80L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK                                   0x0007E000L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK                                            0x01F80000L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK                                            0x7E000000L
+//BIFP4_PCIE_LC_CNTL6
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT                                                         0x0
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT                                                           0x2
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT                                                           0x4
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT                                                          0x6
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT                                                                0x8
+#define BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT                                                      0x9
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT                                                     0xd
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT                                                 0xe
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT                                                   0x10
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT                                           0x12
+#define BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT                                                0x13
+#define BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT                                                     0x14
+#define BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT                                                           0x15
+#define BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT                                                               0x16
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT                                                           0x17
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT                                                      0x18
+#define BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT                                                      0x1f
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK                                                           0x00000003L
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK                                                             0x0000000CL
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK                                                             0x00000030L
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK                                                            0x000000C0L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN_MASK                                                                  0x00000100L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK                                                        0x00001E00L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK                                                       0x00002000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK                                                   0x0000C000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK                                                     0x00030000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK                                             0x00040000L
+#define BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK                                                  0x00080000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK                                                       0x00100000L
+#define BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK                                                             0x00200000L
+#define BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK                                                                 0x00400000L
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK                                                             0x00800000L
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK                                                        0x7F000000L
+#define BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK                                                        0x80000000L
+//BIFP4_PCIE_LC_CNTL7
+#define BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT                                              0x0
+#define BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT                                         0x1
+#define BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT                                             0x2
+#define BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT                                                   0x3
+#define BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT                                                     0x4
+#define BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT                                            0x5
+#define BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT                                                          0x6
+#define BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT                                                0x7
+#define BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT                                                     0x8
+#define BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT                                              0x9
+#define BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT                                               0xa
+#define BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT                                             0xb
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT                                          0xc
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT                                            0xd
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT                                                0x15
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT                                         0x16
+#define BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT                                                     0x17
+#define BIFP4_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT                                              0x18
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT                                                              0x19
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT                                                     0x1b
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT                                                      0x1c
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT                                                          0x1d
+#define BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT                                                          0x1e
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT                                                         0x1f
+#define BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK                                                0x00000001L
+#define BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK                                           0x00000002L
+#define BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK                                               0x00000004L
+#define BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK                                                     0x00000008L
+#define BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK                                                       0x00000010L
+#define BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK                                              0x00000020L
+#define BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK                                                            0x00000040L
+#define BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK                                                  0x00000080L
+#define BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK                                                       0x00000100L
+#define BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK                                                0x00000200L
+#define BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK                                                 0x00000400L
+#define BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK                                               0x00000800L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK                                            0x00001000L
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK                                              0x001FE000L
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK                                                  0x00200000L
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK                                           0x00400000L
+#define BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK                                                       0x00800000L
+#define BIFP4_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK                                                0x01000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_RATES_MASK                                                                0x06000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK                                                       0x08000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK                                                        0x10000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK                                                            0x20000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK                                                            0x40000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK                                                           0x80000000L
+//BIFP4_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT                                           0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                            0x1
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT                           0x2
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT                                           0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT                            0x4
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT                           0x5
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT                                 0x6
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT                                            0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT                                     0x8
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT                                         0x9
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT                                        0xa
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT                                    0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT                                    0xc
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT                                  0xd
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK                                             0x00000001L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK                              0x00000002L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK                             0x00000004L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK                                             0x00000008L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK                              0x00000010L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK                             0x00000020L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK                                   0x00000040L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK                                              0x00000080L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK                                       0x00000100L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK                                           0x00000200L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK                                          0x00000400L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK                                      0x00000800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK                                      0x00001000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK                                    0x00002000L
+//BIFP4_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT                                        0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x1
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT                        0x2
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT                                        0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x4
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT                        0x5
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT                              0x6
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT                                         0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT                                  0x8
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT                                      0x9
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT                                     0xa
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT                                 0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT                                 0xc
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT                               0xd
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK                                          0x00000001L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000002L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK                          0x00000004L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK                                          0x00000008L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000010L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK                          0x00000020L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK                                0x00000040L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK                                           0x00000080L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK                                    0x00000100L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK                                        0x00000200L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK                                       0x00000400L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK                                   0x00000800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK                                   0x00001000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK                                 0x00002000L
+//BIFP4_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT                                         0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT                                              0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT                                         0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT                                                       0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT                                             0xc
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT                                                      0xd
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT                                                    0xf
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT                                                   0x11
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT                                                  0x12
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT                                              0x13
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT                                             0x17
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT                                                 0x1b
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT                                               0x1e
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT                                              0x1f
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK                                           0x00000007L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK                                                0x00000078L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK                                           0x00000780L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK                                                         0x00000800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK                                               0x00001000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK                                                        0x00006000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK                                                      0x00018000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK                                                     0x00020000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK                                                    0x00040000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK                                                0x00780000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK                                               0x07800000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK                                                   0x38000000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK                                                 0x40000000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK                                                0x80000000L
+//BIFP4_PCIEP_STRAP_LC
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT                                                     0x0
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT                                                    0x2
+#define BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT                                                     0x4
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT                                                   0x6
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT                                                      0x8
+#define BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT                                                    0xb
+#define BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT                                                     0xc
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT                                                   0xd
+#define BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT                                                   0xe
+#define BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT                                      0xf
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT                                                   0x10
+#define BIFP4_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                            0x13
+#define BIFP4_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT                                             0x14
+#define BIFP4_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT                                             0x15
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK                                                       0x00000003L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK                                                      0x0000000CL
+#define BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK                                                       0x00000030L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK                                                     0x000000C0L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK                                                        0x00000700L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK                                                      0x00000800L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK                                                       0x00001000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK                                                     0x00002000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK                                                     0x00004000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK                                        0x00008000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK                                                     0x00070000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK                                              0x00080000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK                                               0x00100000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK                                               0x00200000L
+//BIFP4_PCIEP_STRAP_MISC
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT                                                    0x0
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT                                                    0x1
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT                                           0x2
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT                                                   0x3
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT                                                    0x5
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT                                                          0x6
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT                                         0x7
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK                                                      0x00000001L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK                                                      0x00000002L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK                                             0x00000004L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK                                                     0x00000018L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK                                                      0x00000020L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK                                                            0x00000040L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK                                           0x00000080L
+//BIFP4_PCIEP_STRAP_LC2
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT                                                0x0
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT                                             0x1
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT                                                  0x3
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT                                                    0x4
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT                                              0x7
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK                                                  0x00000001L
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK                                               0x00000006L
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK                                                    0x00000008L
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK                                                      0x00000070L
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK                                                0x00000380L
+//BIFP4_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT                                      0x0
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT                                          0x1
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT                                          0x2
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT                                            0x3
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT                                            0x4
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT                                              0x5
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT                                              0x6
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT                                              0x8
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT                                                0x10
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT                                                0x14
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT                                               0x17
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT                                 0x1a
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT                                   0x1b
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT                          0x1c
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK                                        0x00000001L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK                                            0x00000002L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK                                            0x00000004L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK                                              0x00000008L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK                                              0x00000010L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK                                                0x00000020L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK                                                0x000000C0L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK                                                0x00001F00L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK                                                  0x00070000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK                                                  0x00700000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK                                                 0x03800000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK                                   0x04000000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK                                     0x08000000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK                            0x10000000L
+//BIFP4_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT                                              0x0
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT                                          0x8
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK                                                0x000000FFL
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK                                            0x00000700L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+//BIFP4_PCIE_LC_PORT_ORDER
+#define BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT                                                       0x0
+#define BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK                                                         0x0000000FL
+//BIFP4_PCIEP_BCH_ECC_CNTL
+#define BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT                                                     0x0
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT                                              0x8
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT                                                 0x10
+#define BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK                                                       0x00000001L
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK                                                0x0000FF00L
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK                                                   0xFFFF0000L
+//BIFP4_PCIEP_HPGI_PRIVATE
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT                                      0x3
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT                                        0x6
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK                                        0x00000008L
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK                                          0x00000040L
+//BIFP4_PCIEP_HPGI
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT                                                    0x0
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT                                                    0x1
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT                                                  0x2
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT                                                  0x3
+#define BIFP4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT                                                                0x7
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT                                                0x8
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT                                                0x9
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT                                              0xa
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT                                              0xb
+#define BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT                                 0xf
+#define BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT                                     0x10
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK                                                      0x00000001L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK                                                      0x00000002L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK                                                    0x00000004L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK                                                    0x00000008L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_HOOK_MASK                                                                  0x00000080L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK                                                  0x00000100L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK                                                  0x00000200L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK                                                0x00000400L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK                                                0x00000800L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK                                   0x00008000L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK                                       0x00010000L
+//BIFP4_PCIEP_HCNT_DESCRIPTOR
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT                                    0x0
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT                                 0x1f
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK                                      0x00001FFFL
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK                                   0x80000000L
+//BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT                                          0x0
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT                                        0x10
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK                                            0x0000FFFFL
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK                                          0x00FF0000L
+//BIFP4_PCIE_LC_CNTL8
+#define BIFP4_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT                                                    0x0
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT                                                         0x2
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT                                                  0x3
+#define BIFP4_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT                                                           0x7
+#define BIFP4_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT                                                   0x8
+#define BIFP4_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT                                                      0x9
+#define BIFP4_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT                                            0xa
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT                                               0xb
+#define BIFP4_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT                                      0xc
+#define BIFP4_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT                                                0xd
+#define BIFP4_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT                                                        0x11
+#define BIFP4_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT                                                           0x12
+#define BIFP4_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT                                                       0x16
+#define BIFP4_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT                                                               0x17
+#define BIFP4_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT                                                         0x19
+#define BIFP4_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT                                                0x1a
+#define BIFP4_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT                                                 0x1b
+#define BIFP4_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT                                                         0x1c
+#define BIFP4_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT                                                0x1d
+#define BIFP4_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT                                             0x1e
+#define BIFP4_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK                                                      0x00000003L
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK                                                           0x00000004L
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK                                                    0x00000078L
+#define BIFP4_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK                                                             0x00000080L
+#define BIFP4_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK                                                     0x00000100L
+#define BIFP4_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK                                                        0x00000200L
+#define BIFP4_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK                                              0x00000400L
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK                                                 0x00000800L
+#define BIFP4_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK                                        0x00001000L
+#define BIFP4_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK                                                  0x0001E000L
+#define BIFP4_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK                                                          0x00020000L
+#define BIFP4_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK                                                             0x003C0000L
+#define BIFP4_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK                                                         0x00400000L
+#define BIFP4_PCIE_LC_CNTL8__LC_FOM_TIME_MASK                                                                 0x01800000L
+#define BIFP4_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK                                                           0x02000000L
+#define BIFP4_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK                                                  0x04000000L
+#define BIFP4_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK                                                   0x08000000L
+#define BIFP4_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK                                                           0x10000000L
+#define BIFP4_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK                                                  0x20000000L
+#define BIFP4_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK                                               0xC0000000L
+//BIFP4_PCIE_LC_CNTL9
+#define BIFP4_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT                                           0x0
+#define BIFP4_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT                                              0x1
+#define BIFP4_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT                                                0x3
+#define BIFP4_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT                                                       0x4
+#define BIFP4_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT                                                 0x6
+#define BIFP4_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT                                                 0x8
+#define BIFP4_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT                            0xa
+#define BIFP4_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT                                                   0xb
+#define BIFP4_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT                                               0xc
+#define BIFP4_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT                                                    0xd
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT                                                 0xe
+#define BIFP4_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT                                                 0x18
+#define BIFP4_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT                                                0x19
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT                                                  0x1a
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT                                                 0x1b
+#define BIFP4_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT                                              0x1c
+#define BIFP4_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT                               0x1d
+#define BIFP4_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT                                      0x1e
+#define BIFP4_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT                                      0x1f
+#define BIFP4_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK                                             0x00000001L
+#define BIFP4_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK                                                0x00000006L
+#define BIFP4_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK                                                  0x00000008L
+#define BIFP4_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK                                                         0x00000030L
+#define BIFP4_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK                                                   0x000000C0L
+#define BIFP4_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK                                                   0x00000300L
+#define BIFP4_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK                              0x00000400L
+#define BIFP4_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK                                                     0x00000800L
+#define BIFP4_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK                                                 0x00001000L
+#define BIFP4_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK                                                      0x00002000L
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK                                                   0x00FFC000L
+#define BIFP4_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK                                                   0x01000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK                                                  0x02000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK                                                    0x04000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK                                                   0x08000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK                                                0x10000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK                                 0x20000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK                                        0x40000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK                                        0x80000000L
+//BIFP4_PCIE_LC_FORCE_COEFF2
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT                                                0x0
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT                                           0x1
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT                                               0x7
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT                                          0xd
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT                                        0x13
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK                                                  0x00000001L
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK                                             0x0000007EL
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK                                                 0x00001F80L
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK                                            0x0007E000L
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK                                          0x00080000L
+//BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT                         0x0
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT                                0x1
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT                                    0x7
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT                               0xd
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT                                        0x13
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT                                        0x19
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK                           0x00000001L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK                                  0x0000007EL
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK                                      0x00001F80L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK                                 0x0007E000L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK                                          0x01F80000L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK                                          0x7E000000L
+//BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT                                       0x0
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT                                     0x10
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK                                         0x0000FFFFL
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK                                       0x00FF0000L
+//BIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT             0x0
+#define BIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT               0x1
+#define BIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK               0x00000001L
+#define BIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK                 0x00000002L
+//BIFP4_PCIE_LC_CNTL10
+#define BIFP4_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT                      0x0
+#define BIFP4_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT                                         0x1
+#define BIFP4_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT                                             0x2
+#define BIFP4_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT                                            0x4
+#define BIFP4_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT                                                       0x6
+#define BIFP4_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT                                                      0x10
+#define BIFP4_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT                                     0x1a
+#define BIFP4_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT                                                0x1b
+#define BIFP4_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT                                              0x1d
+#define BIFP4_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT                                 0x1e
+#define BIFP4_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT                                 0x1f
+#define BIFP4_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK                        0x00000001L
+#define BIFP4_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK                                           0x00000002L
+#define BIFP4_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK                                               0x0000000CL
+#define BIFP4_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK                                              0x00000030L
+#define BIFP4_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK                                                         0x0000FFC0L
+#define BIFP4_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK                                                        0x03FF0000L
+#define BIFP4_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK                                       0x04000000L
+#define BIFP4_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK                                                  0x18000000L
+#define BIFP4_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK                                                0x20000000L
+#define BIFP4_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK                                   0x40000000L
+#define BIFP4_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK                                   0x80000000L
+//BIFP4_PCIE_LC_CNTL11
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT                                            0x0
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT                                          0x1
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT                                          0x2
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT                                          0x3
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT                                         0x5
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT                                          0x9
+#define BIFP4_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT                                    0xd
+#define BIFP4_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT                                          0xe
+#define BIFP4_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT                                           0xf
+#define BIFP4_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT                                                0x10
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT                       0x11
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT                         0x12
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT                              0x13
+#define BIFP4_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT                        0x14
+#define BIFP4_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT                                   0x15
+#define BIFP4_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT                                        0x16
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT                                                               0x17
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT                                                        0x18
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT                                                             0x1a
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT                                                             0x1b
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT                                                   0x1c
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT                                                     0x1e
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK                                              0x00000001L
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK                                            0x00000002L
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK                                            0x00000004L
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK                                            0x00000018L
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK                                           0x000001E0L
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK                                            0x00001E00L
+#define BIFP4_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK                                      0x00002000L
+#define BIFP4_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK                                            0x00004000L
+#define BIFP4_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK                                             0x00008000L
+#define BIFP4_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK                                                  0x00010000L
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK                         0x00020000L
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK                           0x00040000L
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK                                0x00080000L
+#define BIFP4_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK                          0x00100000L
+#define BIFP4_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK                                     0x00200000L
+#define BIFP4_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK                                          0x00400000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_EN_MASK                                                                 0x00800000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK                                                          0x03000000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK                                                               0x04000000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK                                                               0x08000000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK                                                     0x30000000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK                                                       0xC0000000L
+//BIFP4_PCIE_LC_CNTL12
+#define BIFP4_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT                                         0x0
+#define BIFP4_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT                                0x1
+#define BIFP4_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT                                        0x2
+#define BIFP4_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT                                            0x3
+#define BIFP4_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT                                 0x4
+#define BIFP4_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT                                      0x5
+#define BIFP4_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT                                         0x6
+#define BIFP4_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT                                                     0x7
+#define BIFP4_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT                                           0x8
+#define BIFP4_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT                                       0x9
+#define BIFP4_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT                                              0xa
+#define BIFP4_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT                                   0xb
+#define BIFP4_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT                                                0xc
+#define BIFP4_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT                                             0xd
+#define BIFP4_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT                                            0xe
+#define BIFP4_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT                                                0xf
+#define BIFP4_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT                                0x10
+#define BIFP4_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT                              0x11
+#define BIFP4_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT                            0x12
+#define BIFP4_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT                                          0x13
+#define BIFP4_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT                                                 0x14
+#define BIFP4_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT                                          0x15
+#define BIFP4_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT                                             0x16
+#define BIFP4_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT                                            0x17
+#define BIFP4_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT                                            0x1f
+#define BIFP4_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK                                           0x00000001L
+#define BIFP4_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK                                  0x00000002L
+#define BIFP4_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK                                          0x00000004L
+#define BIFP4_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK                                              0x00000008L
+#define BIFP4_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK                                   0x00000010L
+#define BIFP4_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK                                        0x00000020L
+#define BIFP4_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK                                           0x00000040L
+#define BIFP4_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK                                                       0x00000080L
+#define BIFP4_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK                                             0x00000100L
+#define BIFP4_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK                                         0x00000200L
+#define BIFP4_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK                                                0x00000400L
+#define BIFP4_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK                                     0x00000800L
+#define BIFP4_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK                                                  0x00001000L
+#define BIFP4_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK                                               0x00002000L
+#define BIFP4_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK                                              0x00004000L
+#define BIFP4_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK                                                  0x00008000L
+#define BIFP4_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK                                  0x00010000L
+#define BIFP4_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK                                0x00020000L
+#define BIFP4_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK                              0x00040000L
+#define BIFP4_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK                                            0x00080000L
+#define BIFP4_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK                                                   0x00100000L
+#define BIFP4_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK                                            0x00200000L
+#define BIFP4_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK                                               0x00400000L
+#define BIFP4_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK                                              0x00800000L
+#define BIFP4_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK                                              0x80000000L
+//BIFP4_PCIE_LC_SAVE_RESTORE_1
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT                                               0x0
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT                                        0x1
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT                                            0x2
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT                                      0xa
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT                                             0xb
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT                                  0xc
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT                                    0xd
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT                                           0xe
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT                                          0x10
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK                                                 0x00000001L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK                                          0x00000002L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK                                              0x000003FCL
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK                                        0x00000400L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK                                               0x00000800L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK                                    0x00001000L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK                                      0x00002000L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK                                             0x0000C000L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK                                            0xFFFF0000L
+//BIFP4_PCIE_LC_SAVE_RESTORE_2
+#define BIFP4_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT                                          0x0
+#define BIFP4_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK                                            0xFFFFFFFFL
+//BIFP4_PCIE_LC_SAVE_RESTORE_3
+#define BIFP4_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT                                0x0
+#define BIFP4_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK                                  0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp5_pciedir_p
+//BIFP5_PCIEP_RESERVED
+#define BIFP5_PCIEP_RESERVED__RESERVED__SHIFT                                                                 0x0
+#define BIFP5_PCIEP_RESERVED__RESERVED_MASK                                                                   0xFFFFFFFFL
+//BIFP5_PCIEP_SCRATCH
+#define BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT                                                             0x0
+#define BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK                                                               0xFFFFFFFFL
+//BIFP5_PCIEP_PORT_CNTL
+#define BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT                                                         0x0
+#define BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT                                                       0x1
+#define BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT                                                          0x2
+#define BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT                                                           0x3
+#define BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT                                                            0x4
+#define BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT                                                              0x5
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT                                         0x8
+#define BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT                                            0x12
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT                                             0x18
+#define BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT                                            0x1a
+#define BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK                                                           0x00000001L
+#define BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK                                                         0x00000002L
+#define BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK                                                            0x00000004L
+#define BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK                                                             0x00000008L
+#define BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK                                                              0x00000010L
+#define BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK                                                                0x00000020L
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK                                           0x0003FF00L
+#define BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK                                              0x001C0000L
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK                                               0x03000000L
+#define BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK                                              0x0C000000L
+//BIFP5_PCIE_TX_CNTL
+#define BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                            0xa
+#define BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                             0xc
+#define BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT                                                         0xe
+#define BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT                                                           0xf
+#define BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT                                                              0x14
+#define BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT                                                               0x15
+#define BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT                                                     0x16
+#define BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT                                                   0x17
+#define BIFP5_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT                                              0x1b
+#define BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                              0x00000C00L
+#define BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                               0x00003000L
+#define BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK                                                           0x00004000L
+#define BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK                                                             0x00008000L
+#define BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK                                                                0x00100000L
+#define BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK                                                                 0x00200000L
+#define BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK                                                       0x00400000L
+#define BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK                                                     0x00800000L
+#define BIFP5_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK                                                0x08000000L
+//BIFP5_PCIE_TX_REQUESTER_ID
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                           0x0
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                             0x3
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                                0x8
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                             0x00000007L
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                               0x000000F8L
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                                  0x0000FF00L
+//BIFP5_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT                                                  0x18
+#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK                                                    0x01000000L
+//BIFP5_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT                                          0x18
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT                                   0x1e
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT                                       0x1f
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK                                            0x3F000000L
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK                                     0x40000000L
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK                                         0x80000000L
+//BIFP5_PCIE_TX_SEQ
+#define BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT                                                        0x0
+#define BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT                                                                 0x10
+#define BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK                                                          0x00000FFFL
+#define BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK                                                                   0x0FFF0000L
+//BIFP5_PCIE_TX_REPLAY
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT                                                            0x0
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT                                                      0xe
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT                                                0xf
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT                                                          0x10
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK                                                              0x00000007L
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK                                                        0x00004000L
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK                                                  0x00008000L
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK                                                            0xFFFF0000L
+//BIFP5_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT                                          0x0
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT                                0xc
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK                                            0x00000FFFL
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK                                  0x00001000L
+//BIFP5_PCIE_TX_NOP_DLLP
+#define BIFP5_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT                                                            0x0
+#define BIFP5_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT                                                            0x18
+#define BIFP5_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK                                                              0x00FFFFFFL
+#define BIFP5_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK                                                              0x01000000L
+//BIFP5_PCIE_TX_CNTL_2
+//BIFP5_PCIE_TX_SKID_CTRL
+#define BIFP5_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT                                                  0x0
+#define BIFP5_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT                                            0x4
+#define BIFP5_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK                                                    0x0000000FL
+#define BIFP5_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK                                              0x00000010L
+//BIFP5_PCIE_TX_CREDITS_ADVT_P
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT                                               0x0
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT                                               0x10
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK                                                 0x00003FFFL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK                                                 0x03FF0000L
+//BIFP5_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT                                             0x0
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT                                             0x10
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK                                               0x00003FFFL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK                                               0x03FF0000L
+//BIFP5_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT                                           0x0
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT                                           0x10
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK                                             0x00003FFFL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK                                             0x03FF0000L
+//BIFP5_PCIE_TX_CREDITS_INIT_P
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT                                               0x0
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT                                               0x10
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK                                                 0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK                                                 0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_INIT_NP
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT                                             0x0
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT                                             0x10
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK                                               0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK                                               0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT                                           0x0
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT                                           0x10
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK                                             0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK                                             0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_STATUS
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT                                                0x0
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT                                                0x1
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT                                               0x2
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT                                               0x3
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT                                              0x4
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT                                              0x5
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT                                         0x10
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT                                         0x11
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT                                        0x12
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT                                        0x13
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT                                       0x14
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT                                       0x15
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK                                                  0x00000001L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK                                                  0x00000002L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK                                                 0x00000004L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK                                                 0x00000008L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK                                                0x00000010L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK                                                0x00000020L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK                                           0x00010000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK                                           0x00020000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK                                          0x00040000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK                                          0x00080000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK                                         0x00100000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK                                         0x00200000L
+//BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT                                    0x0
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT                                   0x4
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT                                  0x8
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT                                    0x10
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT                                   0x14
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT                                  0x18
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK                                      0x00000007L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK                                     0x00000070L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK                                    0x00000700L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK                                      0x00070000L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK                                     0x00700000L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK                                    0x07000000L
+//BIFP5_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT                                          0x0
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT                                                  0x3
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT                                           0x6
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT                                                   0x8
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT                                                   0x10
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT                                       0x19
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT                                              0x1c
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK                                            0x00000007L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK                                                    0x00000038L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK                                             0x00000040L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK                                                     0x00003F00L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK                                                     0x003F0000L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK                                         0x02000000L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK                                                0xF0000000L
+//BIFP5_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT                                      0x0
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK                                        0x0000FFFFL
+//BIFP5_PCIE_CCIX_STACKED_BASE
+#define BIFP5_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT                                           0x4
+#define BIFP5_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK                                             0xFFFFFFF0L
+//BIFP5_PCIE_CCIX_STACKED_LIMIT
+#define BIFP5_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT                                         0x4
+#define BIFP5_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK                                           0xFFFFFFF0L
+//BIFP5_PCIE_CCIX_MISC_STATUS
+#define BIFP5_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT                                              0x0
+#define BIFP5_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT                                          0x1
+#define BIFP5_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK                                                0x00000001L
+#define BIFP5_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK                                            0x00000002L
+//BIFP5_PCIE_P_PORT_LANE_STATUS
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT                                              0x0
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT                                                  0x1
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK                                                0x00000001L
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK                                                    0x0000007EL
+//BIFP5_PCIE_FC_P
+#define BIFP5_PCIE_FC_P__PD_CREDITS__SHIFT                                                                    0x0
+#define BIFP5_PCIE_FC_P__PH_CREDITS__SHIFT                                                                    0x10
+#define BIFP5_PCIE_FC_P__PD_CREDITS_MASK                                                                      0x0000FFFFL
+#define BIFP5_PCIE_FC_P__PH_CREDITS_MASK                                                                      0x0FFF0000L
+//BIFP5_PCIE_FC_NP
+#define BIFP5_PCIE_FC_NP__NPD_CREDITS__SHIFT                                                                  0x0
+#define BIFP5_PCIE_FC_NP__NPH_CREDITS__SHIFT                                                                  0x10
+#define BIFP5_PCIE_FC_NP__NPD_CREDITS_MASK                                                                    0x0000FFFFL
+#define BIFP5_PCIE_FC_NP__NPH_CREDITS_MASK                                                                    0x0FFF0000L
+//BIFP5_PCIE_FC_CPL
+#define BIFP5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT                                                                0x0
+#define BIFP5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT                                                                0x10
+#define BIFP5_PCIE_FC_CPL__CPLD_CREDITS_MASK                                                                  0x0000FFFFL
+#define BIFP5_PCIE_FC_CPL__CPLH_CREDITS_MASK                                                                  0x0FFF0000L
+//BIFP5_PCIE_FC_P_VC1
+#define BIFP5_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT                                                    0x0
+#define BIFP5_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT                                                    0x10
+#define BIFP5_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK                                                      0x0000FFFFL
+#define BIFP5_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK                                                      0x0FFF0000L
+//BIFP5_PCIE_FC_NP_VC1
+#define BIFP5_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT                                                  0x0
+#define BIFP5_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT                                                  0x10
+#define BIFP5_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK                                                    0x0000FFFFL
+#define BIFP5_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK                                                    0x0FFF0000L
+//BIFP5_PCIE_FC_CPL_VC1
+#define BIFP5_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT                                                0x0
+#define BIFP5_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT                                                0x10
+#define BIFP5_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK                                                  0x0000FFFFL
+#define BIFP5_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK                                                  0x0FFF0000L
+//BIFP5_PCIE_ERR_CNTL
+#define BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                         0x0
+#define BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT                                                  0x1
+#define BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT                                                     0x2
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT                                                      0x4
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT                                                      0x5
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT                                                      0x6
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT                                                      0x7
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                                       0x8
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                              0xb
+#define BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT                                               0xe
+#define BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT                                              0xf
+#define BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT                                                     0x10
+#define BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                                  0x11
+#define BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                                          0x12
+#define BIFP5_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT                                                    0x13
+#define BIFP5_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT                                                     0x14
+#define BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                           0x00000001L
+#define BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK                                                    0x00000002L
+#define BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK                                                       0x00000004L
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK                                                        0x00000010L
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK                                                        0x00000020L
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK                                                        0x00000040L
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK                                                        0x00000080L
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                         0x00000700L
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                                0x00000800L
+#define BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK                                                 0x00004000L
+#define BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK                                                0x00008000L
+#define BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK                                                       0x00010000L
+#define BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                                    0x00020000L
+#define BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                            0x00040000L
+#define BIFP5_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK                                                      0x00080000L
+#define BIFP5_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK                                                       0x00100000L
+//BIFP5_PCIE_RX_CNTL
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT                                                           0x0
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT                                                           0x1
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT                                                          0x2
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT                                                          0x3
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT                                                          0x4
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT                                                          0x5
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT                                                           0x6
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT                                                 0x7
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                                  0x8
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                           0x9
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT                                                           0xa
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT                                                            0xb
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT                                                           0xc
+#define BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT                                                        0xd
+#define BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT                                                        0xf
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT                                                         0x10
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT                                                    0x13
+#define BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                                    0x14
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                                  0x15
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                                    0x16
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT                                                    0x17
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                                 0x18
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                                     0x19
+#define BIFP5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                                 0x1a
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                                     0x1b
+#define BIFP5_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT                                                              0x1c
+#define BIFP5_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT                                                0x1d
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK                                                             0x00000001L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK                                                             0x00000002L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK                                                            0x00000004L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK                                                            0x00000008L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK                                                            0x00000010L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK                                                            0x00000020L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK                                                             0x00000040L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK                                                   0x00000080L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                                    0x00000100L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                             0x00000200L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK                                                             0x00000400L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK                                                              0x00000800L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK                                                             0x00001000L
+#define BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK                                                          0x00002000L
+#define BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK                                                          0x00008000L
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK                                                           0x00070000L
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK                                                      0x00080000L
+#define BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                                      0x00100000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                                    0x00200000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                                      0x00400000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK                                                      0x00800000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                                   0x01000000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                                       0x02000000L
+#define BIFP5_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                                   0x04000000L
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                                       0x08000000L
+#define BIFP5_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK                                                                0x10000000L
+#define BIFP5_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK                                                  0x20000000L
+//BIFP5_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT                                              0x0
+#define BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK                                                0x00000FFFL
+//BIFP5_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT                                                0x18
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK                                                  0x01000000L
+//BIFP5_PCIE_RX_CNTL3
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT                                             0x0
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT                                             0x1
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT                                                0x2
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT                                                    0x3
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT                                               0x4
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK                                               0x00000001L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK                                               0x00000002L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK                                                  0x00000004L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK                                                      0x00000008L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK                                                 0x00000010L
+//BIFP5_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT                                     0x0
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT                                     0x10
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK                                       0x00000FFFL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK                                       0x00FF0000L
+//BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT                                   0x0
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT                                   0x10
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK                                     0x00000FFFL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK                                     0x00FF0000L
+//BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT                                 0x0
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT                                 0x10
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK                                   0x00000FFFL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK                                   0x00FF0000L
+//BIFP5_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT                                    0x0
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT                                 0x2
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT                           0x4
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT                             0x6
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT                              0x8
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT                              0xa
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT                                  0xc
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT                         0xe
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT                            0x10
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT                                0x12
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT                           0x14
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT                             0x16
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK                                      0x00000003L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK                                   0x0000000CL
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK                             0x00000030L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK                               0x000000C0L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK                                0x00000300L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK                                0x00000C00L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK                                    0x00003000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK                           0x0000C000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK                              0x00030000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK                                  0x000C0000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK                             0x00300000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK                               0x00C00000L
+//BIFP5_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT                             0x0
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT                      0x2
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT                                 0x4
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT                                  0x6
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT                          0x8
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT                               0xa
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT                            0xc
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT                         0xe
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT                          0x10
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT                       0x12
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK                               0x00000003L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK                        0x0000000CL
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK                                   0x00000030L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK                                    0x000000C0L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK                            0x00000300L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK                                 0x00000C00L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK                              0x00003000L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK                           0x0000C000L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK                            0x00030000L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK                         0x000C0000L
+//BIFP5_PCIEP_NAK_COUNTER
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT                                              0x0
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT                                             0x10
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK                                                0x0000FFFFL
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK                                               0xFFFF0000L
+//BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT                     0x0
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT                     0xa
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT                      0xf
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT                  0x10
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT                  0x1a
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT                   0x1f
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK                       0x000003FFL
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK                       0x00001C00L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK                        0x00008000L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK                    0x03FF0000L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK                    0x1C000000L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK                     0x80000000L
+//BIFP5_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP5_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT                                    0x5
+#define BIFP5_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK                                      0x00000020L
+//BIFP5_PCIE_AER_PRIV_TRIGGER
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT                          0x0
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT                           0x1
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT                         0x2
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK                            0x00000001L
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK                             0x00000002L
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK                           0x00000004L
+//BIFP5_PCIE_LC_CNTL
+#define BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT                                                    0x1
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT                                                   0x2
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT                                                              0x3
+#define BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT                                                       0x4
+#define BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT                                                          0x8
+#define BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT                                                           0xc
+#define BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT                                                           0x10
+#define BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT                                                            0x11
+#define BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT                                                  0x12
+#define BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT                                                      0x14
+#define BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT                                                     0x15
+#define BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT                                                           0x16
+#define BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT                                                        0x17
+#define BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT                                                          0x18
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT                                                             0x19
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT                                                          0x1b
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT                                                           0x1c
+#define BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT                                                 0x1d
+#define BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT                                                         0x1e
+#define BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT                                                          0x1f
+#define BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK                                                      0x00000002L
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK                                                     0x00000004L
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_LINK_MASK                                                                0x00000008L
+#define BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK                                                         0x000000F0L
+#define BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK                                                            0x00000F00L
+#define BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK                                                             0x0000F000L
+#define BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK                                                             0x00010000L
+#define BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK                                                              0x00020000L
+#define BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK                                                    0x000C0000L
+#define BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK                                                        0x00100000L
+#define BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK                                                       0x00200000L
+#define BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK                                                             0x00400000L
+#define BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK                                                          0x00800000L
+#define BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK                                                            0x01000000L
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK                                                               0x06000000L
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK                                                            0x08000000L
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK                                                             0x10000000L
+#define BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK                                                   0x20000000L
+#define BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK                                                           0x40000000L
+#define BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK                                                            0x80000000L
+//BIFP5_PCIE_LC_TRAINING_CNTL
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT                                                  0x0
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT                                             0x4
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT                                 0x5
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT                                        0x6
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT                                            0x7
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT                                                    0x8
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT                                     0xb
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT                                       0xc
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT                                      0xd
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT                                          0xe
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT                                        0xf
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT                                            0x10
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT                                          0x11
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT                                            0x12
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT                                                 0x13
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT                                                 0x14
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT                                        0x15
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT                                          0x16
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT                                 0x18
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT                                    0x19
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT                                        0x1a
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT                                             0x1b
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT                                            0x1c
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT                                 0x1d
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT                                             0x1e
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK                                                    0x0000000FL
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK                                               0x00000010L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK                                   0x00000020L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK                                          0x00000040L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK                                              0x00000080L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK                                                      0x00000700L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK                                       0x00000800L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK                                         0x00001000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK                                        0x00002000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK                                            0x00004000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK                                          0x00008000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK                                              0x00010000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK                                            0x00020000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK                                              0x00040000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK                                                   0x00080000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK                                                   0x00100000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK                                          0x00200000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK                                            0x00C00000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK                                   0x01000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK                                      0x02000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK                                          0x04000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK                                               0x08000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK                                              0x10000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK                                   0x20000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK                                               0xC0000000L
+//BIFP5_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT                                                   0x0
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT                                                0x4
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT                                  0x7
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT                                                 0x8
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT                                        0x9
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT                                               0xa
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT                                            0xb
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT                                          0xc
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT                                              0xd
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT                                      0xe
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT                                              0xf
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT                                               0x11
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT                                               0x12
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT                                         0x13
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT                                          0x14
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT                                          0x15
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT                                         0x17
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT                                       0x18
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT                                  0x19
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT                                    0x1a
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT                                0x1b
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT                                0x1c
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT                                     0x1d
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT                                        0x1e
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT                                      0x1f
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK                                                     0x00000007L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK                                                  0x00000070L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK                                    0x00000080L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK                                                   0x00000100L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK                                          0x00000200L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK                                                 0x00000400L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK                                              0x00000800L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK                                            0x00001000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK                                                0x00002000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK                                        0x00004000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK                                                0x00008000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK                                                 0x00020000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK                                                 0x00040000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK                                           0x00080000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK                                            0x00100000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK                                            0x00600000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK                                           0x00800000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK                                         0x01000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK                                    0x02000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK                                      0x04000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK                                  0x08000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK                                  0x10000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK                                       0x20000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK                                          0x40000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK                                        0x80000000L
+//BIFP5_PCIE_LC_N_FTS_CNTL
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT                                                        0x0
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT                                            0x8
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT                                          0x9
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT                                                         0xa
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT                                               0xe
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT                                              0xf
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT                                                  0x10
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT                                                             0x18
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK                                                          0x000000FFL
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK                                              0x00000100L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK                                            0x00000200L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK                                                           0x00000400L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK                                                 0x00004000L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK                                                0x00008000L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK                                                    0x00FF0000L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK                                                               0xFF000000L
+//BIFP5_PCIE_LC_SPEED_CNTL
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                                     0x0
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                                     0x1
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                                     0x2
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT                                     0x3
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT                                        0x4
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT                                          0x6
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT                                         0x7
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT                                          0x8
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT                                         0x9
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT                                        0xa
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0xb
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0xd
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT                                                 0xe
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT                                 0x10
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT                                         0x11
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT                                        0x12
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT                                         0x13
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT                                          0x14
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT                                         0x15
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT                                          0x16
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT                                         0x17
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT                                          0x18
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT                                               0x19
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT                                              0x1a
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT                                                   0x1c
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT                                    0x1d
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT                                          0x1e
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT                                           0x1f
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                                       0x00000001L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                                       0x00000002L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                                       0x00000004L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK                                       0x00000008L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK                                          0x00000030L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK                                            0x00000040L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK                                           0x00000080L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK                                            0x00000100L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK                                           0x00000200L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK                                          0x00000400L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x00001800L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00002000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK                                                   0x0000C000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK                                   0x00010000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK                                           0x00020000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK                                          0x00040000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK                                           0x00080000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK                                            0x00100000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK                                           0x00200000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK                                            0x00400000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK                                           0x00800000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK                                            0x01000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK                                                 0x02000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK                                                0x0C000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK                                                     0x10000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK                                      0x20000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK                                            0x40000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK                                             0x80000000L
+//BIFP5_PCIE_LC_STATE0
+#define BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT                                                         0x0
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT                                                           0x8
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT                                                           0x10
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT                                                           0x18
+#define BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK                                                           0x0000003FL
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK                                                             0x00003F00L
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK                                                             0x003F0000L
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK                                                             0x3F000000L
+//BIFP5_PCIE_LC_STATE1
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT                                                           0x0
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT                                                           0x8
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT                                                           0x10
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT                                                           0x18
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK                                                             0x0000003FL
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK                                                             0x00003F00L
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK                                                             0x003F0000L
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK                                                             0x3F000000L
+//BIFP5_PCIE_LC_STATE2
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT                                                           0x0
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT                                                           0x8
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT                                                          0x10
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT                                                          0x18
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK                                                             0x0000003FL
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK                                                             0x00003F00L
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK                                                            0x003F0000L
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK                                                            0x3F000000L
+//BIFP5_PCIE_LC_STATE3
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT                                                          0x0
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT                                                          0x8
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT                                                          0x10
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT                                                          0x18
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK                                                            0x0000003FL
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK                                                            0x00003F00L
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK                                                            0x003F0000L
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK                                                            0x3F000000L
+//BIFP5_PCIE_LC_STATE4
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT                                                          0x0
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT                                                          0x8
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT                                                          0x10
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT                                                          0x18
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK                                                            0x0000003FL
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK                                                            0x00003F00L
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK                                                            0x003F0000L
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK                                                            0x3F000000L
+//BIFP5_PCIE_LC_STATE5
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT                                                          0x0
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT                                                          0x8
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT                                                          0x10
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT                                                          0x18
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK                                                            0x0000003FL
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK                                                            0x00003F00L
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK                                                            0x003F0000L
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK                                                            0x3F000000L
+//BIFP5_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT                                                 0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT                                                 0x1
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT                                                  0x2
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT                                                  0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT                                                 0x4
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT                                                0x5
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT                                                0x6
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT                                          0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT                                         0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT                                          0xf
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT                                         0x13
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT                                          0x17
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT                                         0x1b
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK                                                   0x00000001L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK                                                   0x00000002L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK                                                    0x00000004L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK                                                    0x00000008L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK                                                   0x00000010L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK                                                  0x00000020L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK                                                  0x00000040L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK                                            0x00000780L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK                                           0x00007800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK                                            0x00078000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK                                           0x00780000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK                                            0x07800000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK                                           0x78000000L
+//BIFP5_PCIE_LC_CNTL2
+#define BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT                                                        0x0
+#define BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT                                                        0x6
+#define BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT                                                  0x7
+#define BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT                                                            0x8
+#define BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT                                                    0x9
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT                                                    0xa
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT                                                          0xb
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT                                               0xc
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT                                              0xd
+#define BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT                                                         0xe
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT                                         0x10
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT                                                       0x11
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT                                                      0x12
+#define BIFP5_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT                                              0x13
+#define BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT                                                    0x14
+#define BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT                                                  0x15
+#define BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT                                            0x16
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT                                               0x17
+#define BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT                                                 0x19
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT                                             0x1a
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                               0x1b
+#define BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT                                               0x1c
+#define BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT                                                         0x1d
+#define BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT                                       0x1f
+#define BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK                                                          0x0000003FL
+#define BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK                                                          0x00000040L
+#define BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK                                                    0x00000080L
+#define BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK                                                              0x00000100L
+#define BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK                                                      0x00000200L
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK                                                      0x00000400L
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK                                                            0x00000800L
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK                                                 0x00001000L
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK                                                0x00002000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK                                                           0x0000C000L
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK                                           0x00010000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK                                                         0x00020000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK                                                        0x00040000L
+#define BIFP5_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK                                                0x00080000L
+#define BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK                                                      0x00100000L
+#define BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK                                                    0x00200000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK                                              0x00400000L
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK                                                 0x01800000L
+#define BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK                                                   0x02000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK                                               0x04000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                                 0x08000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK                                                 0x10000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK                                                           0x60000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK                                         0x80000000L
+//BIFP5_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT                                              0x0
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT                                          0x1
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT                                          0x2
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT                                       0x3
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT                                      0x4
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT                                              0x5
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT                                                0x6
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT                                               0x7
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT                                               0x8
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT                                              0x9
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT                              0xa
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT                                        0xb
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK                                                0x00000001L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK                                            0x00000002L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK                                            0x00000004L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK                                         0x00000008L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK                                        0x00000010L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK                                                0x00000020L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK                                                  0x00000040L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK                                                 0x00000080L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK                                                 0x00000100L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK                                                0x00000200L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK                                0x00000400L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK                                          0x00000800L
+//BIFP5_PCIE_LC_CDR_CNTL
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT                                                        0x0
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT                                                       0xc
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT                                                        0x18
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK                                                          0x00000FFFL
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK                                                         0x00FFF000L
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK                                                          0x03000000L
+//BIFP5_PCIE_LC_LANE_CNTL
+#define BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT                                                    0x0
+#define BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK                                                      0x0000FFFFL
+//BIFP5_PCIE_LC_CNTL3
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT                                                      0x0
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT                                                 0x1
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT                                                        0x3
+#define BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT                                                         0x4
+#define BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT                                              0x5
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0x6
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0x8
+#define BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT                                         0x9
+#define BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT                                                   0xa
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT                                                   0xb
+#define BIFP5_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT                                                   0xc
+#define BIFP5_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT                                         0xd
+#define BIFP5_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT                                         0xe
+#define BIFP5_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT                                    0xf
+#define BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT                                                   0x11
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT                                          0x12
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT                                0x13
+#define BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT                                                  0x15
+#define BIFP5_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT                             0x16
+#define BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT                                       0x17
+#define BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT                                                  0x18
+#define BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT                                                      0x1a
+#define BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT                                                         0x1e
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT                                                      0x1f
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK                                                        0x00000001L
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK                                                   0x00000006L
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK                                                          0x00000008L
+#define BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK                                                           0x00000010L
+#define BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK                                                0x00000020L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x000000C0L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00000100L
+#define BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK                                           0x00000200L
+#define BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK                                                     0x00000400L
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK                                                     0x00000800L
+#define BIFP5_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK                                                     0x00001000L
+#define BIFP5_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK                                           0x00002000L
+#define BIFP5_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK                                           0x00004000L
+#define BIFP5_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK                                      0x00008000L
+#define BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK                                                     0x00020000L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK                                            0x00040000L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK                                  0x00180000L
+#define BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK                                                    0x00200000L
+#define BIFP5_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK                               0x00400000L
+#define BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK                                         0x00800000L
+#define BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK                                                    0x03000000L
+#define BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK                                                        0x3C000000L
+#define BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK                                                           0x40000000L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK                                                        0x80000000L
+//BIFP5_PCIE_LC_CNTL4
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT                                                    0x0
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT                                               0x2
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT                                            0x3
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT                                                          0x4
+#define BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT                                                            0x5
+#define BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT                                                           0x6
+#define BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT                                                          0x7
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT                                                     0x8
+#define BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT                                              0xa
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT                                                    0xb
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT                                                       0xc
+#define BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT                                                            0xd
+#define BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT                                                           0xe
+#define BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT                                             0xf
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT                                                0x10
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT                                       0x11
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT                                                 0x12
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT                                                        0x16
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT                                                               0x17
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT                                                  0x18
+#define BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT                                                      0x19
+#define BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT                                              0x1a
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK                                                      0x00000003L
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK                                                 0x00000004L
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK                                              0x00000008L
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK                                                            0x00000010L
+#define BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK                                                              0x00000020L
+#define BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK                                                             0x00000040L
+#define BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK                                                            0x00000080L
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK                                                       0x00000300L
+#define BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK                                                0x00000400L
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK                                                      0x00000800L
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK                                                         0x00001000L
+#define BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK                                                              0x00002000L
+#define BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK                                                             0x00004000L
+#define BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK                                               0x00008000L
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK                                                  0x00010000L
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK                                         0x00020000L
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK                                                   0x003C0000L
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK                                                          0x00400000L
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_SWING_MASK                                                                 0x00800000L
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK                                                    0x01000000L
+#define BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK                                                        0x02000000L
+#define BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK                                                0xFC000000L
+//BIFP5_PCIE_LC_CNTL5
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT                                                 0x0
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT                                                           0x2
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT                                                       0x6
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT                                                           0xa
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT                                                      0x10
+#define BIFP5_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT                                      0x15
+#define BIFP5_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT                                                      0x16
+#define BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT                                        0x18
+#define BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT                                                      0x19
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT                                                     0x1a
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT                                                0x1b
+#define BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT                                                         0x1c
+#define BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT                                                     0x1d
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK                                                   0x00000003L
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK                                                             0x0000003CL
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK                                                         0x000003C0L
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK                                                             0x0000FC00L
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK                                                        0x001F0000L
+#define BIFP5_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK                                        0x00200000L
+#define BIFP5_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK                                                        0x00C00000L
+#define BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK                                          0x01000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK                                                        0x02000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK                                                       0x04000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK                                                  0x08000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK                                                           0x10000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK                                                       0xE0000000L
+//BIFP5_PCIE_LC_FORCE_COEFF
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT                                                  0x0
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT                                             0x1
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT                                                 0x7
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT                                            0xd
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT                                          0x13
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT                                                     0x14
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK                                                    0x00000001L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK                                               0x0000007EL
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK                                                   0x00001F80L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK                                              0x0007E000L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK                                            0x00080000L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK                                                       0x00100000L
+//BIFP5_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT                                                 0x0
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT                                              0x4
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT                                                 0xa
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT                                             0x10
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT                                                    0x16
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT                                          0x1e
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK                                                   0x0000000FL
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK                                                0x000003F0L
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK                                                   0x0000FC00L
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK                                               0x003F0000L
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK                                                      0x3FC00000L
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK                                            0x40000000L
+//BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT                           0x0
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT                                  0x1
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT                                      0x7
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT                                 0xd
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT                                          0x13
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT                                          0x19
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK                             0x00000001L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK                                    0x0000007EL
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK                                        0x00001F80L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK                                   0x0007E000L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK                                            0x01F80000L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK                                            0x7E000000L
+//BIFP5_PCIE_LC_CNTL6
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT                                                         0x0
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT                                                           0x2
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT                                                           0x4
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT                                                          0x6
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT                                                                0x8
+#define BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT                                                      0x9
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT                                                     0xd
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT                                                 0xe
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT                                                   0x10
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT                                           0x12
+#define BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT                                                0x13
+#define BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT                                                     0x14
+#define BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT                                                           0x15
+#define BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT                                                               0x16
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT                                                           0x17
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT                                                      0x18
+#define BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT                                                      0x1f
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK                                                           0x00000003L
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK                                                             0x0000000CL
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK                                                             0x00000030L
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK                                                            0x000000C0L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN_MASK                                                                  0x00000100L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK                                                        0x00001E00L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK                                                       0x00002000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK                                                   0x0000C000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK                                                     0x00030000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK                                             0x00040000L
+#define BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK                                                  0x00080000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK                                                       0x00100000L
+#define BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK                                                             0x00200000L
+#define BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK                                                                 0x00400000L
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK                                                             0x00800000L
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK                                                        0x7F000000L
+#define BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK                                                        0x80000000L
+//BIFP5_PCIE_LC_CNTL7
+#define BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT                                              0x0
+#define BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT                                         0x1
+#define BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT                                             0x2
+#define BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT                                                   0x3
+#define BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT                                                     0x4
+#define BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT                                            0x5
+#define BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT                                                          0x6
+#define BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT                                                0x7
+#define BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT                                                     0x8
+#define BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT                                              0x9
+#define BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT                                               0xa
+#define BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT                                             0xb
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT                                          0xc
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT                                            0xd
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT                                                0x15
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT                                         0x16
+#define BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT                                                     0x17
+#define BIFP5_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT                                              0x18
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT                                                              0x19
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT                                                     0x1b
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT                                                      0x1c
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT                                                          0x1d
+#define BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT                                                          0x1e
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT                                                         0x1f
+#define BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK                                                0x00000001L
+#define BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK                                           0x00000002L
+#define BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK                                               0x00000004L
+#define BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK                                                     0x00000008L
+#define BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK                                                       0x00000010L
+#define BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK                                              0x00000020L
+#define BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK                                                            0x00000040L
+#define BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK                                                  0x00000080L
+#define BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK                                                       0x00000100L
+#define BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK                                                0x00000200L
+#define BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK                                                 0x00000400L
+#define BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK                                               0x00000800L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK                                            0x00001000L
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK                                              0x001FE000L
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK                                                  0x00200000L
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK                                           0x00400000L
+#define BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK                                                       0x00800000L
+#define BIFP5_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK                                                0x01000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_RATES_MASK                                                                0x06000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK                                                       0x08000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK                                                        0x10000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK                                                            0x20000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK                                                            0x40000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK                                                           0x80000000L
+//BIFP5_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT                                           0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                            0x1
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT                           0x2
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT                                           0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT                            0x4
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT                           0x5
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT                                 0x6
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT                                            0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT                                     0x8
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT                                         0x9
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT                                        0xa
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT                                    0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT                                    0xc
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT                                  0xd
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK                                             0x00000001L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK                              0x00000002L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK                             0x00000004L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK                                             0x00000008L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK                              0x00000010L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK                             0x00000020L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK                                   0x00000040L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK                                              0x00000080L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK                                       0x00000100L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK                                           0x00000200L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK                                          0x00000400L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK                                      0x00000800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK                                      0x00001000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK                                    0x00002000L
+//BIFP5_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT                                        0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x1
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT                        0x2
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT                                        0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x4
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT                        0x5
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT                              0x6
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT                                         0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT                                  0x8
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT                                      0x9
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT                                     0xa
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT                                 0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT                                 0xc
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT                               0xd
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK                                          0x00000001L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000002L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK                          0x00000004L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK                                          0x00000008L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000010L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK                          0x00000020L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK                                0x00000040L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK                                           0x00000080L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK                                    0x00000100L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK                                        0x00000200L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK                                       0x00000400L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK                                   0x00000800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK                                   0x00001000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK                                 0x00002000L
+//BIFP5_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT                                         0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT                                              0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT                                         0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT                                                       0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT                                             0xc
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT                                                      0xd
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT                                                    0xf
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT                                                   0x11
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT                                                  0x12
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT                                              0x13
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT                                             0x17
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT                                                 0x1b
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT                                               0x1e
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT                                              0x1f
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK                                           0x00000007L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK                                                0x00000078L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK                                           0x00000780L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK                                                         0x00000800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK                                               0x00001000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK                                                        0x00006000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK                                                      0x00018000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK                                                     0x00020000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK                                                    0x00040000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK                                                0x00780000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK                                               0x07800000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK                                                   0x38000000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK                                                 0x40000000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK                                                0x80000000L
+//BIFP5_PCIEP_STRAP_LC
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT                                                     0x0
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT                                                    0x2
+#define BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT                                                     0x4
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT                                                   0x6
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT                                                      0x8
+#define BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT                                                    0xb
+#define BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT                                                     0xc
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT                                                   0xd
+#define BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT                                                   0xe
+#define BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT                                      0xf
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT                                                   0x10
+#define BIFP5_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                            0x13
+#define BIFP5_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT                                             0x14
+#define BIFP5_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT                                             0x15
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK                                                       0x00000003L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK                                                      0x0000000CL
+#define BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK                                                       0x00000030L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK                                                     0x000000C0L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK                                                        0x00000700L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK                                                      0x00000800L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK                                                       0x00001000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK                                                     0x00002000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK                                                     0x00004000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK                                        0x00008000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK                                                     0x00070000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK                                              0x00080000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK                                               0x00100000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK                                               0x00200000L
+//BIFP5_PCIEP_STRAP_MISC
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT                                                    0x0
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT                                                    0x1
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT                                           0x2
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT                                                   0x3
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT                                                    0x5
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT                                                          0x6
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT                                         0x7
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK                                                      0x00000001L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK                                                      0x00000002L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK                                             0x00000004L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK                                                     0x00000018L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK                                                      0x00000020L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK                                                            0x00000040L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK                                           0x00000080L
+//BIFP5_PCIEP_STRAP_LC2
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT                                                0x0
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT                                             0x1
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT                                                  0x3
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT                                                    0x4
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT                                              0x7
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK                                                  0x00000001L
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK                                               0x00000006L
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK                                                    0x00000008L
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK                                                      0x00000070L
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK                                                0x00000380L
+//BIFP5_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT                                      0x0
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT                                          0x1
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT                                          0x2
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT                                            0x3
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT                                            0x4
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT                                              0x5
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT                                              0x6
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT                                              0x8
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT                                                0x10
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT                                                0x14
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT                                               0x17
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT                                 0x1a
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT                                   0x1b
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT                          0x1c
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK                                        0x00000001L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK                                            0x00000002L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK                                            0x00000004L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK                                              0x00000008L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK                                              0x00000010L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK                                                0x00000020L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK                                                0x000000C0L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK                                                0x00001F00L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK                                                  0x00070000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK                                                  0x00700000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK                                                 0x03800000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK                                   0x04000000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK                                     0x08000000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK                            0x10000000L
+//BIFP5_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT                                              0x0
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT                                          0x8
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK                                                0x000000FFL
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK                                            0x00000700L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+//BIFP5_PCIE_LC_PORT_ORDER
+#define BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT                                                       0x0
+#define BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK                                                         0x0000000FL
+//BIFP5_PCIEP_BCH_ECC_CNTL
+#define BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT                                                     0x0
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT                                              0x8
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT                                                 0x10
+#define BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK                                                       0x00000001L
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK                                                0x0000FF00L
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK                                                   0xFFFF0000L
+//BIFP5_PCIEP_HPGI_PRIVATE
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT                                      0x3
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT                                        0x6
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK                                        0x00000008L
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK                                          0x00000040L
+//BIFP5_PCIEP_HPGI
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT                                                    0x0
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT                                                    0x1
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT                                                  0x2
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT                                                  0x3
+#define BIFP5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT                                                                0x7
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT                                                0x8
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT                                                0x9
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT                                              0xa
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT                                              0xb
+#define BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT                                 0xf
+#define BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT                                     0x10
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK                                                      0x00000001L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK                                                      0x00000002L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK                                                    0x00000004L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK                                                    0x00000008L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_HOOK_MASK                                                                  0x00000080L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK                                                  0x00000100L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK                                                  0x00000200L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK                                                0x00000400L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK                                                0x00000800L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK                                   0x00008000L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK                                       0x00010000L
+//BIFP5_PCIEP_HCNT_DESCRIPTOR
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT                                    0x0
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT                                 0x1f
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK                                      0x00001FFFL
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK                                   0x80000000L
+//BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT                                          0x0
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT                                        0x10
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK                                            0x0000FFFFL
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK                                          0x00FF0000L
+//BIFP5_PCIE_LC_CNTL8
+#define BIFP5_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT                                                    0x0
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT                                                         0x2
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT                                                  0x3
+#define BIFP5_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT                                                           0x7
+#define BIFP5_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT                                                   0x8
+#define BIFP5_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT                                                      0x9
+#define BIFP5_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT                                            0xa
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT                                               0xb
+#define BIFP5_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT                                      0xc
+#define BIFP5_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT                                                0xd
+#define BIFP5_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT                                                        0x11
+#define BIFP5_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT                                                           0x12
+#define BIFP5_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT                                                       0x16
+#define BIFP5_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT                                                               0x17
+#define BIFP5_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT                                                         0x19
+#define BIFP5_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT                                                0x1a
+#define BIFP5_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT                                                 0x1b
+#define BIFP5_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT                                                         0x1c
+#define BIFP5_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT                                                0x1d
+#define BIFP5_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT                                             0x1e
+#define BIFP5_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK                                                      0x00000003L
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK                                                           0x00000004L
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK                                                    0x00000078L
+#define BIFP5_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK                                                             0x00000080L
+#define BIFP5_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK                                                     0x00000100L
+#define BIFP5_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK                                                        0x00000200L
+#define BIFP5_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK                                              0x00000400L
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK                                                 0x00000800L
+#define BIFP5_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK                                        0x00001000L
+#define BIFP5_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK                                                  0x0001E000L
+#define BIFP5_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK                                                          0x00020000L
+#define BIFP5_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK                                                             0x003C0000L
+#define BIFP5_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK                                                         0x00400000L
+#define BIFP5_PCIE_LC_CNTL8__LC_FOM_TIME_MASK                                                                 0x01800000L
+#define BIFP5_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK                                                           0x02000000L
+#define BIFP5_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK                                                  0x04000000L
+#define BIFP5_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK                                                   0x08000000L
+#define BIFP5_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK                                                           0x10000000L
+#define BIFP5_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK                                                  0x20000000L
+#define BIFP5_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK                                               0xC0000000L
+//BIFP5_PCIE_LC_CNTL9
+#define BIFP5_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT                                           0x0
+#define BIFP5_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT                                              0x1
+#define BIFP5_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT                                                0x3
+#define BIFP5_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT                                                       0x4
+#define BIFP5_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT                                                 0x6
+#define BIFP5_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT                                                 0x8
+#define BIFP5_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT                            0xa
+#define BIFP5_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT                                                   0xb
+#define BIFP5_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT                                               0xc
+#define BIFP5_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT                                                    0xd
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT                                                 0xe
+#define BIFP5_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT                                                 0x18
+#define BIFP5_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT                                                0x19
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT                                                  0x1a
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT                                                 0x1b
+#define BIFP5_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT                                              0x1c
+#define BIFP5_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT                               0x1d
+#define BIFP5_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT                                      0x1e
+#define BIFP5_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT                                      0x1f
+#define BIFP5_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK                                             0x00000001L
+#define BIFP5_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK                                                0x00000006L
+#define BIFP5_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK                                                  0x00000008L
+#define BIFP5_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK                                                         0x00000030L
+#define BIFP5_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK                                                   0x000000C0L
+#define BIFP5_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK                                                   0x00000300L
+#define BIFP5_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK                              0x00000400L
+#define BIFP5_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK                                                     0x00000800L
+#define BIFP5_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK                                                 0x00001000L
+#define BIFP5_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK                                                      0x00002000L
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK                                                   0x00FFC000L
+#define BIFP5_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK                                                   0x01000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK                                                  0x02000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK                                                    0x04000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK                                                   0x08000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK                                                0x10000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK                                 0x20000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK                                        0x40000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK                                        0x80000000L
+//BIFP5_PCIE_LC_FORCE_COEFF2
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT                                                0x0
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT                                           0x1
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT                                               0x7
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT                                          0xd
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT                                        0x13
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK                                                  0x00000001L
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK                                             0x0000007EL
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK                                                 0x00001F80L
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK                                            0x0007E000L
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK                                          0x00080000L
+//BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT                         0x0
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT                                0x1
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT                                    0x7
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT                               0xd
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT                                        0x13
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT                                        0x19
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK                           0x00000001L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK                                  0x0000007EL
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK                                      0x00001F80L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK                                 0x0007E000L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK                                          0x01F80000L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK                                          0x7E000000L
+//BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT                                       0x0
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT                                     0x10
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK                                         0x0000FFFFL
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK                                       0x00FF0000L
+//BIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT             0x0
+#define BIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT               0x1
+#define BIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK               0x00000001L
+#define BIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK                 0x00000002L
+//BIFP5_PCIE_LC_CNTL10
+#define BIFP5_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT                      0x0
+#define BIFP5_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT                                         0x1
+#define BIFP5_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT                                             0x2
+#define BIFP5_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT                                            0x4
+#define BIFP5_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT                                                       0x6
+#define BIFP5_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT                                                      0x10
+#define BIFP5_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT                                     0x1a
+#define BIFP5_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT                                                0x1b
+#define BIFP5_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT                                              0x1d
+#define BIFP5_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT                                 0x1e
+#define BIFP5_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT                                 0x1f
+#define BIFP5_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK                        0x00000001L
+#define BIFP5_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK                                           0x00000002L
+#define BIFP5_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK                                               0x0000000CL
+#define BIFP5_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK                                              0x00000030L
+#define BIFP5_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK                                                         0x0000FFC0L
+#define BIFP5_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK                                                        0x03FF0000L
+#define BIFP5_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK                                       0x04000000L
+#define BIFP5_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK                                                  0x18000000L
+#define BIFP5_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK                                                0x20000000L
+#define BIFP5_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK                                   0x40000000L
+#define BIFP5_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK                                   0x80000000L
+//BIFP5_PCIE_LC_CNTL11
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT                                            0x0
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT                                          0x1
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT                                          0x2
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT                                          0x3
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT                                         0x5
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT                                          0x9
+#define BIFP5_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT                                    0xd
+#define BIFP5_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT                                          0xe
+#define BIFP5_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT                                           0xf
+#define BIFP5_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT                                                0x10
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT                       0x11
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT                         0x12
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT                              0x13
+#define BIFP5_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT                        0x14
+#define BIFP5_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT                                   0x15
+#define BIFP5_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT                                        0x16
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT                                                               0x17
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT                                                        0x18
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT                                                             0x1a
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT                                                             0x1b
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT                                                   0x1c
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT                                                     0x1e
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK                                              0x00000001L
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK                                            0x00000002L
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK                                            0x00000004L
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK                                            0x00000018L
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK                                           0x000001E0L
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK                                            0x00001E00L
+#define BIFP5_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK                                      0x00002000L
+#define BIFP5_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK                                            0x00004000L
+#define BIFP5_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK                                             0x00008000L
+#define BIFP5_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK                                                  0x00010000L
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK                         0x00020000L
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK                           0x00040000L
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK                                0x00080000L
+#define BIFP5_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK                          0x00100000L
+#define BIFP5_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK                                     0x00200000L
+#define BIFP5_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK                                          0x00400000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_EN_MASK                                                                 0x00800000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK                                                          0x03000000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK                                                               0x04000000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK                                                               0x08000000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK                                                     0x30000000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK                                                       0xC0000000L
+//BIFP5_PCIE_LC_CNTL12
+#define BIFP5_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT                                         0x0
+#define BIFP5_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT                                0x1
+#define BIFP5_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT                                        0x2
+#define BIFP5_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT                                            0x3
+#define BIFP5_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT                                 0x4
+#define BIFP5_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT                                      0x5
+#define BIFP5_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT                                         0x6
+#define BIFP5_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT                                                     0x7
+#define BIFP5_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT                                           0x8
+#define BIFP5_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT                                       0x9
+#define BIFP5_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT                                              0xa
+#define BIFP5_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT                                   0xb
+#define BIFP5_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT                                                0xc
+#define BIFP5_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT                                             0xd
+#define BIFP5_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT                                            0xe
+#define BIFP5_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT                                                0xf
+#define BIFP5_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT                                0x10
+#define BIFP5_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT                              0x11
+#define BIFP5_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT                            0x12
+#define BIFP5_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT                                          0x13
+#define BIFP5_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT                                                 0x14
+#define BIFP5_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT                                          0x15
+#define BIFP5_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT                                             0x16
+#define BIFP5_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT                                            0x17
+#define BIFP5_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT                                            0x1f
+#define BIFP5_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK                                           0x00000001L
+#define BIFP5_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK                                  0x00000002L
+#define BIFP5_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK                                          0x00000004L
+#define BIFP5_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK                                              0x00000008L
+#define BIFP5_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK                                   0x00000010L
+#define BIFP5_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK                                        0x00000020L
+#define BIFP5_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK                                           0x00000040L
+#define BIFP5_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK                                                       0x00000080L
+#define BIFP5_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK                                             0x00000100L
+#define BIFP5_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK                                         0x00000200L
+#define BIFP5_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK                                                0x00000400L
+#define BIFP5_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK                                     0x00000800L
+#define BIFP5_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK                                                  0x00001000L
+#define BIFP5_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK                                               0x00002000L
+#define BIFP5_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK                                              0x00004000L
+#define BIFP5_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK                                                  0x00008000L
+#define BIFP5_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK                                  0x00010000L
+#define BIFP5_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK                                0x00020000L
+#define BIFP5_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK                              0x00040000L
+#define BIFP5_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK                                            0x00080000L
+#define BIFP5_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK                                                   0x00100000L
+#define BIFP5_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK                                            0x00200000L
+#define BIFP5_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK                                               0x00400000L
+#define BIFP5_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK                                              0x00800000L
+#define BIFP5_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK                                              0x80000000L
+//BIFP5_PCIE_LC_SAVE_RESTORE_1
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT                                               0x0
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT                                        0x1
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT                                            0x2
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT                                      0xa
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT                                             0xb
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT                                  0xc
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT                                    0xd
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT                                           0xe
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT                                          0x10
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK                                                 0x00000001L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK                                          0x00000002L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK                                              0x000003FCL
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK                                        0x00000400L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK                                               0x00000800L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK                                    0x00001000L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK                                      0x00002000L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK                                             0x0000C000L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK                                            0xFFFF0000L
+//BIFP5_PCIE_LC_SAVE_RESTORE_2
+#define BIFP5_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT                                          0x0
+#define BIFP5_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK                                            0xFFFFFFFFL
+//BIFP5_PCIE_LC_SAVE_RESTORE_3
+#define BIFP5_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT                                0x0
+#define BIFP5_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK                                  0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp6_pciedir_p
+//BIFP6_PCIEP_RESERVED
+#define BIFP6_PCIEP_RESERVED__RESERVED__SHIFT                                                                 0x0
+#define BIFP6_PCIEP_RESERVED__RESERVED_MASK                                                                   0xFFFFFFFFL
+//BIFP6_PCIEP_SCRATCH
+#define BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT                                                             0x0
+#define BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK                                                               0xFFFFFFFFL
+//BIFP6_PCIEP_PORT_CNTL
+#define BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT                                                         0x0
+#define BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT                                                       0x1
+#define BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT                                                          0x2
+#define BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT                                                           0x3
+#define BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT                                                            0x4
+#define BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT                                                              0x5
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT                                         0x8
+#define BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT                                            0x12
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT                                             0x18
+#define BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT                                            0x1a
+#define BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK                                                           0x00000001L
+#define BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK                                                         0x00000002L
+#define BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK                                                            0x00000004L
+#define BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK                                                             0x00000008L
+#define BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK                                                              0x00000010L
+#define BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK                                                                0x00000020L
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK                                           0x0003FF00L
+#define BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK                                              0x001C0000L
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK                                               0x03000000L
+#define BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK                                              0x0C000000L
+//BIFP6_PCIE_TX_CNTL
+#define BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                            0xa
+#define BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                             0xc
+#define BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT                                                         0xe
+#define BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT                                                           0xf
+#define BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT                                                              0x14
+#define BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT                                                               0x15
+#define BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT                                                     0x16
+#define BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT                                                   0x17
+#define BIFP6_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT                                              0x1b
+#define BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                              0x00000C00L
+#define BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                               0x00003000L
+#define BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK                                                           0x00004000L
+#define BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK                                                             0x00008000L
+#define BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK                                                                0x00100000L
+#define BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P_MASK                                                                 0x00200000L
+#define BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK                                                       0x00400000L
+#define BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK                                                     0x00800000L
+#define BIFP6_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK                                                0x08000000L
+//BIFP6_PCIE_TX_REQUESTER_ID
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                           0x0
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                             0x3
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                                0x8
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                             0x00000007L
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                               0x000000F8L
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                                  0x0000FF00L
+//BIFP6_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT                                                  0x18
+#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK                                                    0x01000000L
+//BIFP6_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT                                          0x18
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT                                   0x1e
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT                                       0x1f
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK                                            0x3F000000L
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK                                     0x40000000L
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK                                         0x80000000L
+//BIFP6_PCIE_TX_SEQ
+#define BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT                                                        0x0
+#define BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT                                                                 0x10
+#define BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK                                                          0x00000FFFL
+#define BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK                                                                   0x0FFF0000L
+//BIFP6_PCIE_TX_REPLAY
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT                                                            0x0
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT                                                      0xe
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT                                                0xf
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT                                                          0x10
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK                                                              0x00000007L
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK                                                        0x00004000L
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK                                                  0x00008000L
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK                                                            0xFFFF0000L
+//BIFP6_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT                                          0x0
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT                                0xc
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK                                            0x00000FFFL
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK                                  0x00001000L
+//BIFP6_PCIE_TX_NOP_DLLP
+#define BIFP6_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT                                                            0x0
+#define BIFP6_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT                                                            0x18
+#define BIFP6_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK                                                              0x00FFFFFFL
+#define BIFP6_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK                                                              0x01000000L
+//BIFP6_PCIE_TX_CNTL_2
+//BIFP6_PCIE_TX_SKID_CTRL
+#define BIFP6_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT                                                  0x0
+#define BIFP6_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT                                            0x4
+#define BIFP6_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK                                                    0x0000000FL
+#define BIFP6_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK                                              0x00000010L
+//BIFP6_PCIE_TX_CREDITS_ADVT_P
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT                                               0x0
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT                                               0x10
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK                                                 0x00003FFFL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK                                                 0x03FF0000L
+//BIFP6_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT                                             0x0
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT                                             0x10
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK                                               0x00003FFFL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK                                               0x03FF0000L
+//BIFP6_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT                                           0x0
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT                                           0x10
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK                                             0x00003FFFL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK                                             0x03FF0000L
+//BIFP6_PCIE_TX_CREDITS_INIT_P
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT                                               0x0
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT                                               0x10
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK                                                 0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK                                                 0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_INIT_NP
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT                                             0x0
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT                                             0x10
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK                                               0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK                                               0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT                                           0x0
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT                                           0x10
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK                                             0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK                                             0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_STATUS
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT                                                0x0
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT                                                0x1
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT                                               0x2
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT                                               0x3
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT                                              0x4
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT                                              0x5
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT                                         0x10
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT                                         0x11
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT                                        0x12
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT                                        0x13
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT                                       0x14
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT                                       0x15
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK                                                  0x00000001L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK                                                  0x00000002L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK                                                 0x00000004L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK                                                 0x00000008L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK                                                0x00000010L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK                                                0x00000020L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK                                           0x00010000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK                                           0x00020000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK                                          0x00040000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK                                          0x00080000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK                                         0x00100000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK                                         0x00200000L
+//BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT                                    0x0
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT                                   0x4
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT                                  0x8
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT                                    0x10
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT                                   0x14
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT                                  0x18
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK                                      0x00000007L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK                                     0x00000070L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK                                    0x00000700L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK                                      0x00070000L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK                                     0x00700000L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK                                    0x07000000L
+//BIFP6_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT                                          0x0
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT                                                  0x3
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT                                           0x6
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT                                                   0x8
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT                                                   0x10
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT                                       0x19
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT                                              0x1c
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK                                            0x00000007L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK                                                    0x00000038L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK                                             0x00000040L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK                                                     0x00003F00L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK                                                     0x003F0000L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK                                         0x02000000L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK                                                0xF0000000L
+//BIFP6_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT                                      0x0
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK                                        0x0000FFFFL
+//BIFP6_PCIE_CCIX_STACKED_BASE
+#define BIFP6_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT                                           0x4
+#define BIFP6_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK                                             0xFFFFFFF0L
+//BIFP6_PCIE_CCIX_STACKED_LIMIT
+#define BIFP6_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT                                         0x4
+#define BIFP6_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK                                           0xFFFFFFF0L
+//BIFP6_PCIE_CCIX_MISC_STATUS
+#define BIFP6_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT                                              0x0
+#define BIFP6_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT                                          0x1
+#define BIFP6_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK                                                0x00000001L
+#define BIFP6_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK                                            0x00000002L
+//BIFP6_PCIE_P_PORT_LANE_STATUS
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT                                              0x0
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT                                                  0x1
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK                                                0x00000001L
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK                                                    0x0000007EL
+//BIFP6_PCIE_FC_P
+#define BIFP6_PCIE_FC_P__PD_CREDITS__SHIFT                                                                    0x0
+#define BIFP6_PCIE_FC_P__PH_CREDITS__SHIFT                                                                    0x10
+#define BIFP6_PCIE_FC_P__PD_CREDITS_MASK                                                                      0x0000FFFFL
+#define BIFP6_PCIE_FC_P__PH_CREDITS_MASK                                                                      0x0FFF0000L
+//BIFP6_PCIE_FC_NP
+#define BIFP6_PCIE_FC_NP__NPD_CREDITS__SHIFT                                                                  0x0
+#define BIFP6_PCIE_FC_NP__NPH_CREDITS__SHIFT                                                                  0x10
+#define BIFP6_PCIE_FC_NP__NPD_CREDITS_MASK                                                                    0x0000FFFFL
+#define BIFP6_PCIE_FC_NP__NPH_CREDITS_MASK                                                                    0x0FFF0000L
+//BIFP6_PCIE_FC_CPL
+#define BIFP6_PCIE_FC_CPL__CPLD_CREDITS__SHIFT                                                                0x0
+#define BIFP6_PCIE_FC_CPL__CPLH_CREDITS__SHIFT                                                                0x10
+#define BIFP6_PCIE_FC_CPL__CPLD_CREDITS_MASK                                                                  0x0000FFFFL
+#define BIFP6_PCIE_FC_CPL__CPLH_CREDITS_MASK                                                                  0x0FFF0000L
+//BIFP6_PCIE_FC_P_VC1
+#define BIFP6_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT                                                    0x0
+#define BIFP6_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT                                                    0x10
+#define BIFP6_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK                                                      0x0000FFFFL
+#define BIFP6_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK                                                      0x0FFF0000L
+//BIFP6_PCIE_FC_NP_VC1
+#define BIFP6_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT                                                  0x0
+#define BIFP6_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT                                                  0x10
+#define BIFP6_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK                                                    0x0000FFFFL
+#define BIFP6_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK                                                    0x0FFF0000L
+//BIFP6_PCIE_FC_CPL_VC1
+#define BIFP6_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT                                                0x0
+#define BIFP6_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT                                                0x10
+#define BIFP6_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK                                                  0x0000FFFFL
+#define BIFP6_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK                                                  0x0FFF0000L
+//BIFP6_PCIE_ERR_CNTL
+#define BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                         0x0
+#define BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT                                                  0x1
+#define BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT                                                     0x2
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT                                                      0x4
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT                                                      0x5
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT                                                      0x6
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT                                                      0x7
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                                       0x8
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                              0xb
+#define BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT                                               0xe
+#define BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT                                              0xf
+#define BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT                                                     0x10
+#define BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                                  0x11
+#define BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                                          0x12
+#define BIFP6_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT                                                    0x13
+#define BIFP6_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT                                                     0x14
+#define BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                           0x00000001L
+#define BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK                                                    0x00000002L
+#define BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK                                                       0x00000004L
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK                                                        0x00000010L
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK                                                        0x00000020L
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK                                                        0x00000040L
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK                                                        0x00000080L
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                         0x00000700L
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                                0x00000800L
+#define BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK                                                 0x00004000L
+#define BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK                                                0x00008000L
+#define BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK                                                       0x00010000L
+#define BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                                    0x00020000L
+#define BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                            0x00040000L
+#define BIFP6_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK                                                      0x00080000L
+#define BIFP6_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK                                                       0x00100000L
+//BIFP6_PCIE_RX_CNTL
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT                                                           0x0
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT                                                           0x1
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT                                                          0x2
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT                                                          0x3
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT                                                          0x4
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT                                                          0x5
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT                                                           0x6
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT                                                 0x7
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                                  0x8
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                           0x9
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT                                                           0xa
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT                                                            0xb
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT                                                           0xc
+#define BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT                                                        0xd
+#define BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT                                                        0xf
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT                                                         0x10
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT                                                    0x13
+#define BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                                    0x14
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                                  0x15
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                                    0x16
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT                                                    0x17
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                                 0x18
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                                     0x19
+#define BIFP6_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                                 0x1a
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                                     0x1b
+#define BIFP6_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT                                                              0x1c
+#define BIFP6_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT                                                0x1d
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK                                                             0x00000001L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK                                                             0x00000002L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK                                                            0x00000004L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK                                                            0x00000008L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK                                                            0x00000010L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK                                                            0x00000020L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK                                                             0x00000040L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK                                                   0x00000080L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                                    0x00000100L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                             0x00000200L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK                                                             0x00000400L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK                                                              0x00000800L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK                                                             0x00001000L
+#define BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK                                                          0x00002000L
+#define BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK                                                          0x00008000L
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK                                                           0x00070000L
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK                                                      0x00080000L
+#define BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                                      0x00100000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                                    0x00200000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                                      0x00400000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK                                                      0x00800000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                                   0x01000000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                                       0x02000000L
+#define BIFP6_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                                   0x04000000L
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                                       0x08000000L
+#define BIFP6_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK                                                                0x10000000L
+#define BIFP6_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK                                                  0x20000000L
+//BIFP6_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT                                              0x0
+#define BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK                                                0x00000FFFL
+//BIFP6_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT                                                  0x0
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT                                                0x18
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK                                                    0x00FFFFFFL
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK                                                  0x01000000L
+//BIFP6_PCIE_RX_CNTL3
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT                                             0x0
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT                                             0x1
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT                                                0x2
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT                                                    0x3
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT                                               0x4
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK                                               0x00000001L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK                                               0x00000002L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK                                                  0x00000004L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK                                                      0x00000008L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK                                                 0x00000010L
+//BIFP6_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT                                     0x0
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT                                     0x10
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK                                       0x00000FFFL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK                                       0x00FF0000L
+//BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT                                   0x0
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT                                   0x10
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK                                     0x00000FFFL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK                                     0x00FF0000L
+//BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT                                 0x0
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT                                 0x10
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK                                   0x00000FFFL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK                                   0x00FF0000L
+//BIFP6_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT                                    0x0
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT                                 0x2
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT                           0x4
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT                             0x6
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT                              0x8
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT                              0xa
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT                                  0xc
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT                         0xe
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT                            0x10
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT                                0x12
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT                           0x14
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT                             0x16
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK                                      0x00000003L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK                                   0x0000000CL
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK                             0x00000030L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK                               0x000000C0L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK                                0x00000300L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK                                0x00000C00L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK                                    0x00003000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK                           0x0000C000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK                              0x00030000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK                                  0x000C0000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK                             0x00300000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK                               0x00C00000L
+//BIFP6_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT                             0x0
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT                      0x2
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT                                 0x4
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT                                  0x6
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT                          0x8
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT                               0xa
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT                            0xc
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT                         0xe
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT                          0x10
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT                       0x12
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK                               0x00000003L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK                        0x0000000CL
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK                                   0x00000030L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK                                    0x000000C0L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK                            0x00000300L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK                                 0x00000C00L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK                              0x00003000L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK                           0x0000C000L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK                            0x00030000L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK                         0x000C0000L
+//BIFP6_PCIEP_NAK_COUNTER
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT                                              0x0
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT                                             0x10
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK                                                0x0000FFFFL
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK                                               0xFFFF0000L
+//BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT                     0x0
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT                     0xa
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT                      0xf
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT                  0x10
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT                  0x1a
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT                   0x1f
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK                       0x000003FFL
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK                       0x00001C00L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK                        0x00008000L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK                    0x03FF0000L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK                    0x1C000000L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK                     0x80000000L
+//BIFP6_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP6_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT                                    0x5
+#define BIFP6_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK                                      0x00000020L
+//BIFP6_PCIE_AER_PRIV_TRIGGER
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT                          0x0
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT                           0x1
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT                         0x2
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK                            0x00000001L
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK                             0x00000002L
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK                           0x00000004L
+//BIFP6_PCIE_LC_CNTL
+#define BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT                                                    0x1
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT                                                   0x2
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT                                                              0x3
+#define BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT                                                       0x4
+#define BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT                                                          0x8
+#define BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT                                                           0xc
+#define BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT                                                           0x10
+#define BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT                                                            0x11
+#define BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT                                                  0x12
+#define BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT                                                      0x14
+#define BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT                                                     0x15
+#define BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT                                                           0x16
+#define BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT                                                        0x17
+#define BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT                                                          0x18
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT                                                             0x19
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT                                                          0x1b
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT                                                           0x1c
+#define BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT                                                 0x1d
+#define BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT                                                         0x1e
+#define BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT                                                          0x1f
+#define BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK                                                      0x00000002L
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK                                                     0x00000004L
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_LINK_MASK                                                                0x00000008L
+#define BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK                                                         0x000000F0L
+#define BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK                                                            0x00000F00L
+#define BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK                                                             0x0000F000L
+#define BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK                                                             0x00010000L
+#define BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK                                                              0x00020000L
+#define BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK                                                    0x000C0000L
+#define BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK                                                        0x00100000L
+#define BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK                                                       0x00200000L
+#define BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK                                                             0x00400000L
+#define BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK                                                          0x00800000L
+#define BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK                                                            0x01000000L
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK                                                               0x06000000L
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK                                                            0x08000000L
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK                                                             0x10000000L
+#define BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK                                                   0x20000000L
+#define BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK                                                           0x40000000L
+#define BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK                                                            0x80000000L
+//BIFP6_PCIE_LC_TRAINING_CNTL
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT                                                  0x0
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT                                             0x4
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT                                 0x5
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT                                        0x6
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT                                            0x7
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT                                                    0x8
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT                                     0xb
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT                                       0xc
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT                                      0xd
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT                                          0xe
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT                                        0xf
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT                                            0x10
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT                                          0x11
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT                                            0x12
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT                                                 0x13
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT                                                 0x14
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT                                        0x15
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT                                          0x16
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT                                 0x18
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT                                    0x19
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT                                        0x1a
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT                                             0x1b
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT                                            0x1c
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT                                 0x1d
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT                                             0x1e
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK                                                    0x0000000FL
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK                                               0x00000010L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK                                   0x00000020L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK                                          0x00000040L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK                                              0x00000080L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK                                                      0x00000700L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK                                       0x00000800L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK                                         0x00001000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK                                        0x00002000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK                                            0x00004000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK                                          0x00008000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK                                              0x00010000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK                                            0x00020000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK                                              0x00040000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK                                                   0x00080000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK                                                   0x00100000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK                                          0x00200000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK                                            0x00C00000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK                                   0x01000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK                                      0x02000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK                                          0x04000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK                                               0x08000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK                                              0x10000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK                                   0x20000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK                                               0xC0000000L
+//BIFP6_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT                                                   0x0
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT                                                0x4
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT                                  0x7
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT                                                 0x8
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT                                        0x9
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT                                               0xa
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT                                            0xb
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT                                          0xc
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT                                              0xd
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT                                      0xe
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT                                              0xf
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT                                               0x11
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT                                               0x12
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT                                         0x13
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT                                          0x14
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT                                          0x15
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT                                         0x17
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT                                       0x18
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT                                  0x19
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT                                    0x1a
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT                                0x1b
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT                                0x1c
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT                                     0x1d
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT                                        0x1e
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT                                      0x1f
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK                                                     0x00000007L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK                                                  0x00000070L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK                                    0x00000080L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK                                                   0x00000100L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK                                          0x00000200L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK                                                 0x00000400L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK                                              0x00000800L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK                                            0x00001000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK                                                0x00002000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK                                        0x00004000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK                                                0x00008000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK                                                 0x00020000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK                                                 0x00040000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK                                           0x00080000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK                                            0x00100000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK                                            0x00600000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK                                           0x00800000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK                                         0x01000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK                                    0x02000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK                                      0x04000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK                                  0x08000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK                                  0x10000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK                                       0x20000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK                                          0x40000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK                                        0x80000000L
+//BIFP6_PCIE_LC_N_FTS_CNTL
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT                                                        0x0
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT                                            0x8
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT                                          0x9
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT                                                         0xa
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT                                               0xe
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT                                              0xf
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT                                                  0x10
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT                                                             0x18
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK                                                          0x000000FFL
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK                                              0x00000100L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK                                            0x00000200L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK                                                           0x00000400L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK                                                 0x00004000L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK                                                0x00008000L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK                                                    0x00FF0000L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK                                                               0xFF000000L
+//BIFP6_PCIE_LC_SPEED_CNTL
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                                     0x0
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                                     0x1
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                                     0x2
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT                                     0x3
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT                                        0x4
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT                                          0x6
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT                                         0x7
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT                                          0x8
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT                                         0x9
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT                                        0xa
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0xb
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0xd
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT                                                 0xe
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT                                 0x10
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT                                         0x11
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT                                        0x12
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT                                         0x13
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT                                          0x14
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT                                         0x15
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT                                          0x16
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT                                         0x17
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT                                          0x18
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT                                               0x19
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT                                              0x1a
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT                                                   0x1c
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT                                    0x1d
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT                                          0x1e
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT                                           0x1f
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                                       0x00000001L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                                       0x00000002L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                                       0x00000004L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK                                       0x00000008L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK                                          0x00000030L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK                                            0x00000040L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK                                           0x00000080L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK                                            0x00000100L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK                                           0x00000200L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK                                          0x00000400L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x00001800L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00002000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK                                                   0x0000C000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK                                   0x00010000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK                                           0x00020000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK                                          0x00040000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK                                           0x00080000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK                                            0x00100000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK                                           0x00200000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK                                            0x00400000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK                                           0x00800000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK                                            0x01000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK                                                 0x02000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK                                                0x0C000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK                                                     0x10000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK                                      0x20000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK                                            0x40000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK                                             0x80000000L
+//BIFP6_PCIE_LC_STATE0
+#define BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT                                                         0x0
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT                                                           0x8
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT                                                           0x10
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT                                                           0x18
+#define BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK                                                           0x0000003FL
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1_MASK                                                             0x00003F00L
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2_MASK                                                             0x003F0000L
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3_MASK                                                             0x3F000000L
+//BIFP6_PCIE_LC_STATE1
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT                                                           0x0
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT                                                           0x8
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT                                                           0x10
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT                                                           0x18
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4_MASK                                                             0x0000003FL
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5_MASK                                                             0x00003F00L
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6_MASK                                                             0x003F0000L
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7_MASK                                                             0x3F000000L
+//BIFP6_PCIE_LC_STATE2
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT                                                           0x0
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT                                                           0x8
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT                                                          0x10
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT                                                          0x18
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8_MASK                                                             0x0000003FL
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9_MASK                                                             0x00003F00L
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10_MASK                                                            0x003F0000L
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11_MASK                                                            0x3F000000L
+//BIFP6_PCIE_LC_STATE3
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT                                                          0x0
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT                                                          0x8
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT                                                          0x10
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT                                                          0x18
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12_MASK                                                            0x0000003FL
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13_MASK                                                            0x00003F00L
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14_MASK                                                            0x003F0000L
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15_MASK                                                            0x3F000000L
+//BIFP6_PCIE_LC_STATE4
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT                                                          0x0
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT                                                          0x8
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT                                                          0x10
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT                                                          0x18
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16_MASK                                                            0x0000003FL
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17_MASK                                                            0x00003F00L
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18_MASK                                                            0x003F0000L
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19_MASK                                                            0x3F000000L
+//BIFP6_PCIE_LC_STATE5
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT                                                          0x0
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT                                                          0x8
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT                                                          0x10
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT                                                          0x18
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20_MASK                                                            0x0000003FL
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21_MASK                                                            0x00003F00L
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22_MASK                                                            0x003F0000L
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23_MASK                                                            0x3F000000L
+//BIFP6_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT                                                 0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT                                                 0x1
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT                                                  0x2
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT                                                  0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT                                                 0x4
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT                                                0x5
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT                                                0x6
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT                                          0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT                                         0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT                                          0xf
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT                                         0x13
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT                                          0x17
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT                                         0x1b
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK                                                   0x00000001L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK                                                   0x00000002L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK                                                    0x00000004L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK                                                    0x00000008L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK                                                   0x00000010L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK                                                  0x00000020L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK                                                  0x00000040L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK                                            0x00000780L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK                                           0x00007800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK                                            0x00078000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK                                           0x00780000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK                                            0x07800000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK                                           0x78000000L
+//BIFP6_PCIE_LC_CNTL2
+#define BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT                                                        0x0
+#define BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT                                                        0x6
+#define BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT                                                  0x7
+#define BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT                                                            0x8
+#define BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT                                                    0x9
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT                                                    0xa
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT                                                          0xb
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT                                               0xc
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT                                              0xd
+#define BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT                                                         0xe
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT                                         0x10
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT                                                       0x11
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT                                                      0x12
+#define BIFP6_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT                                              0x13
+#define BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT                                                    0x14
+#define BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT                                                  0x15
+#define BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT                                            0x16
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT                                               0x17
+#define BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT                                                 0x19
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT                                             0x1a
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                               0x1b
+#define BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT                                               0x1c
+#define BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT                                                         0x1d
+#define BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT                                       0x1f
+#define BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK                                                          0x0000003FL
+#define BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK                                                          0x00000040L
+#define BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK                                                    0x00000080L
+#define BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK                                                              0x00000100L
+#define BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK                                                      0x00000200L
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK                                                      0x00000400L
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK                                                            0x00000800L
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK                                                 0x00001000L
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK                                                0x00002000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK                                                           0x0000C000L
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK                                           0x00010000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK                                                         0x00020000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK                                                        0x00040000L
+#define BIFP6_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK                                                0x00080000L
+#define BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK                                                      0x00100000L
+#define BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK                                                    0x00200000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK                                              0x00400000L
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK                                                 0x01800000L
+#define BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK                                                   0x02000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK                                               0x04000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                                 0x08000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK                                                 0x10000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK                                                           0x60000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK                                         0x80000000L
+//BIFP6_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT                                              0x0
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT                                          0x1
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT                                          0x2
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT                                       0x3
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT                                      0x4
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT                                              0x5
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT                                                0x6
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT                                               0x7
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT                                               0x8
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT                                              0x9
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT                              0xa
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT                                        0xb
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK                                                0x00000001L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK                                            0x00000002L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK                                            0x00000004L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK                                         0x00000008L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK                                        0x00000010L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK                                                0x00000020L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK                                                  0x00000040L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK                                                 0x00000080L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK                                                 0x00000100L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK                                                0x00000200L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK                                0x00000400L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK                                          0x00000800L
+//BIFP6_PCIE_LC_CDR_CNTL
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT                                                        0x0
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT                                                       0xc
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT                                                        0x18
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK                                                          0x00000FFFL
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK                                                         0x00FFF000L
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK                                                          0x03000000L
+//BIFP6_PCIE_LC_LANE_CNTL
+#define BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT                                                    0x0
+#define BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK                                                      0x0000FFFFL
+//BIFP6_PCIE_LC_CNTL3
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT                                                      0x0
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT                                                 0x1
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT                                                        0x3
+#define BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT                                                         0x4
+#define BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT                                              0x5
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                     0x6
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                       0x8
+#define BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT                                         0x9
+#define BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT                                                   0xa
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT                                                   0xb
+#define BIFP6_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT                                                   0xc
+#define BIFP6_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT                                         0xd
+#define BIFP6_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT                                         0xe
+#define BIFP6_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT                                    0xf
+#define BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT                                                   0x11
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT                                          0x12
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT                                0x13
+#define BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT                                                  0x15
+#define BIFP6_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT                             0x16
+#define BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT                                       0x17
+#define BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT                                                  0x18
+#define BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT                                                      0x1a
+#define BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT                                                         0x1e
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT                                                      0x1f
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK                                                        0x00000001L
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK                                                   0x00000006L
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK                                                          0x00000008L
+#define BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK                                                           0x00000010L
+#define BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK                                                0x00000020L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                       0x000000C0L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                         0x00000100L
+#define BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK                                           0x00000200L
+#define BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK                                                     0x00000400L
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK                                                     0x00000800L
+#define BIFP6_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK                                                     0x00001000L
+#define BIFP6_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK                                           0x00002000L
+#define BIFP6_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK                                           0x00004000L
+#define BIFP6_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK                                      0x00008000L
+#define BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK                                                     0x00020000L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK                                            0x00040000L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK                                  0x00180000L
+#define BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK                                                    0x00200000L
+#define BIFP6_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK                               0x00400000L
+#define BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK                                         0x00800000L
+#define BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK                                                    0x03000000L
+#define BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK                                                        0x3C000000L
+#define BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK                                                           0x40000000L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK                                                        0x80000000L
+//BIFP6_PCIE_LC_CNTL4
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT                                                    0x0
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT                                               0x2
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT                                            0x3
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT                                                          0x4
+#define BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT                                                            0x5
+#define BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT                                                           0x6
+#define BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT                                                          0x7
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT                                                     0x8
+#define BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT                                              0xa
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT                                                    0xb
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT                                                       0xc
+#define BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT                                                            0xd
+#define BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT                                                           0xe
+#define BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT                                             0xf
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT                                                0x10
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT                                       0x11
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT                                                 0x12
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT                                                        0x16
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT                                                               0x17
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT                                                  0x18
+#define BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT                                                      0x19
+#define BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT                                              0x1a
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK                                                      0x00000003L
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK                                                 0x00000004L
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK                                              0x00000008L
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK                                                            0x00000010L
+#define BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK                                                              0x00000020L
+#define BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK                                                             0x00000040L
+#define BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK                                                            0x00000080L
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK                                                       0x00000300L
+#define BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK                                                0x00000400L
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK                                                      0x00000800L
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK                                                         0x00001000L
+#define BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK                                                              0x00002000L
+#define BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK                                                             0x00004000L
+#define BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK                                               0x00008000L
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK                                                  0x00010000L
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK                                         0x00020000L
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK                                                   0x003C0000L
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK                                                          0x00400000L
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_SWING_MASK                                                                 0x00800000L
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK                                                    0x01000000L
+#define BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK                                                        0x02000000L
+#define BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK                                                0xFC000000L
+//BIFP6_PCIE_LC_CNTL5
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT                                                 0x0
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT                                                           0x2
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT                                                       0x6
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT                                                           0xa
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT                                                      0x10
+#define BIFP6_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT                                      0x15
+#define BIFP6_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT                                                      0x16
+#define BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT                                        0x18
+#define BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT                                                      0x19
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT                                                     0x1a
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT                                                0x1b
+#define BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT                                                         0x1c
+#define BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT                                                     0x1d
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK                                                   0x00000003L
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK                                                             0x0000003CL
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK                                                         0x000003C0L
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK                                                             0x0000FC00L
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK                                                        0x001F0000L
+#define BIFP6_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK                                        0x00200000L
+#define BIFP6_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK                                                        0x00C00000L
+#define BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK                                          0x01000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK                                                        0x02000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK                                                       0x04000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK                                                  0x08000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK                                                           0x10000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK                                                       0xE0000000L
+//BIFP6_PCIE_LC_FORCE_COEFF
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT                                                  0x0
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT                                             0x1
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT                                                 0x7
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT                                            0xd
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT                                          0x13
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT                                                     0x14
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK                                                    0x00000001L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK                                               0x0000007EL
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK                                                   0x00001F80L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK                                              0x0007E000L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK                                            0x00080000L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK                                                       0x00100000L
+//BIFP6_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT                                                 0x0
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT                                              0x4
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT                                                 0xa
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT                                             0x10
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT                                                    0x16
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT                                          0x1e
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK                                                   0x0000000FL
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK                                                0x000003F0L
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK                                                   0x0000FC00L
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK                                               0x003F0000L
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK                                                      0x3FC00000L
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK                                            0x40000000L
+//BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT                           0x0
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT                                  0x1
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT                                      0x7
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT                                 0xd
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT                                          0x13
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT                                          0x19
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK                             0x00000001L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK                                    0x0000007EL
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK                                        0x00001F80L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK                                   0x0007E000L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK                                            0x01F80000L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK                                            0x7E000000L
+//BIFP6_PCIE_LC_CNTL6
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT                                                         0x0
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT                                                           0x2
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT                                                           0x4
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT                                                          0x6
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT                                                                0x8
+#define BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT                                                      0x9
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT                                                     0xd
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT                                                 0xe
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT                                                   0x10
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT                                           0x12
+#define BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT                                                0x13
+#define BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT                                                     0x14
+#define BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT                                                           0x15
+#define BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT                                                               0x16
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT                                                           0x17
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT                                                      0x18
+#define BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT                                                      0x1f
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK                                                           0x00000003L
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK                                                             0x0000000CL
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK                                                             0x00000030L
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK                                                            0x000000C0L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN_MASK                                                                  0x00000100L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK                                                        0x00001E00L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK                                                       0x00002000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK                                                   0x0000C000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK                                                     0x00030000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK                                             0x00040000L
+#define BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK                                                  0x00080000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK                                                       0x00100000L
+#define BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK                                                             0x00200000L
+#define BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK                                                                 0x00400000L
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK                                                             0x00800000L
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK                                                        0x7F000000L
+#define BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK                                                        0x80000000L
+//BIFP6_PCIE_LC_CNTL7
+#define BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT                                              0x0
+#define BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT                                         0x1
+#define BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT                                             0x2
+#define BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT                                                   0x3
+#define BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT                                                     0x4
+#define BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT                                            0x5
+#define BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT                                                          0x6
+#define BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT                                                0x7
+#define BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT                                                     0x8
+#define BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT                                              0x9
+#define BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT                                               0xa
+#define BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT                                             0xb
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT                                          0xc
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT                                            0xd
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT                                                0x15
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT                                         0x16
+#define BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT                                                     0x17
+#define BIFP6_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT                                              0x18
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT                                                              0x19
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT                                                     0x1b
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT                                                      0x1c
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT                                                          0x1d
+#define BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT                                                          0x1e
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT                                                         0x1f
+#define BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK                                                0x00000001L
+#define BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK                                           0x00000002L
+#define BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK                                               0x00000004L
+#define BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK                                                     0x00000008L
+#define BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK                                                       0x00000010L
+#define BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK                                              0x00000020L
+#define BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK                                                            0x00000040L
+#define BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK                                                  0x00000080L
+#define BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK                                                       0x00000100L
+#define BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK                                                0x00000200L
+#define BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK                                                 0x00000400L
+#define BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK                                               0x00000800L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK                                            0x00001000L
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK                                              0x001FE000L
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK                                                  0x00200000L
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK                                           0x00400000L
+#define BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK                                                       0x00800000L
+#define BIFP6_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK                                                0x01000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_RATES_MASK                                                                0x06000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK                                                       0x08000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK                                                        0x10000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK                                                            0x20000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK                                                            0x40000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK                                                           0x80000000L
+//BIFP6_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT                                           0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                            0x1
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT                           0x2
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT                                           0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT                            0x4
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT                           0x5
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT                                 0x6
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT                                            0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT                                     0x8
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT                                         0x9
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT                                        0xa
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT                                    0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT                                    0xc
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT                                  0xd
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK                                             0x00000001L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK                              0x00000002L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK                             0x00000004L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK                                             0x00000008L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK                              0x00000010L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK                             0x00000020L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK                                   0x00000040L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK                                              0x00000080L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK                                       0x00000100L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK                                           0x00000200L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK                                          0x00000400L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK                                      0x00000800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK                                      0x00001000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK                                    0x00002000L
+//BIFP6_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT                                        0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x1
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT                        0x2
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT                                        0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                         0x4
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT                        0x5
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT                              0x6
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT                                         0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT                                  0x8
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT                                      0x9
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT                                     0xa
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT                                 0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT                                 0xc
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT                               0xd
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK                                          0x00000001L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000002L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK                          0x00000004L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK                                          0x00000008L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK                           0x00000010L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK                          0x00000020L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK                                0x00000040L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK                                           0x00000080L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK                                    0x00000100L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK                                        0x00000200L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK                                       0x00000400L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK                                   0x00000800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK                                   0x00001000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK                                 0x00002000L
+//BIFP6_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT                                         0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT                                              0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT                                         0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT                                                       0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT                                             0xc
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT                                                      0xd
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT                                                    0xf
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT                                                   0x11
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT                                                  0x12
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT                                              0x13
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT                                             0x17
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT                                                 0x1b
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT                                               0x1e
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT                                              0x1f
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK                                           0x00000007L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK                                                0x00000078L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK                                           0x00000780L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK                                                         0x00000800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK                                               0x00001000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK                                                        0x00006000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK                                                      0x00018000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK                                                     0x00020000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK                                                    0x00040000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK                                                0x00780000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK                                               0x07800000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK                                                   0x38000000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK                                                 0x40000000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK                                                0x80000000L
+//BIFP6_PCIEP_STRAP_LC
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT                                                     0x0
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT                                                    0x2
+#define BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT                                                     0x4
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT                                                   0x6
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT                                                      0x8
+#define BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT                                                    0xb
+#define BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT                                                     0xc
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT                                                   0xd
+#define BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT                                                   0xe
+#define BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT                                      0xf
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT                                                   0x10
+#define BIFP6_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                            0x13
+#define BIFP6_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT                                             0x14
+#define BIFP6_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT                                             0x15
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK                                                       0x00000003L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK                                                      0x0000000CL
+#define BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK                                                       0x00000030L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK                                                     0x000000C0L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK                                                        0x00000700L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK                                                      0x00000800L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK                                                       0x00001000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK                                                     0x00002000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK                                                     0x00004000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK                                        0x00008000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK                                                     0x00070000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK                                              0x00080000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK                                               0x00100000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK                                               0x00200000L
+//BIFP6_PCIEP_STRAP_MISC
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT                                                    0x0
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT                                                    0x1
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT                                           0x2
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT                                                   0x3
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT                                                    0x5
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT                                                          0x6
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT                                         0x7
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK                                                      0x00000001L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK                                                      0x00000002L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK                                             0x00000004L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK                                                     0x00000018L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK                                                      0x00000020L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK                                                            0x00000040L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK                                           0x00000080L
+//BIFP6_PCIEP_STRAP_LC2
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT                                                0x0
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT                                             0x1
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT                                                  0x3
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT                                                    0x4
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT                                              0x7
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK                                                  0x00000001L
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK                                               0x00000006L
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK                                                    0x00000008L
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK                                                      0x00000070L
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK                                                0x00000380L
+//BIFP6_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT                                      0x0
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT                                          0x1
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT                                          0x2
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT                                            0x3
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT                                            0x4
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT                                              0x5
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT                                              0x6
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT                                              0x8
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT                                                0x10
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT                                                0x14
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT                                               0x17
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT                                 0x1a
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT                                   0x1b
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT                          0x1c
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK                                        0x00000001L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK                                            0x00000002L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK                                            0x00000004L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK                                              0x00000008L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK                                              0x00000010L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK                                                0x00000020L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK                                                0x000000C0L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK                                                0x00001F00L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK                                                  0x00070000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK                                                  0x00700000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK                                                 0x03800000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK                                   0x04000000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK                                     0x08000000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK                            0x10000000L
+//BIFP6_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT                                              0x0
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT                                          0x8
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT                                          0x10
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK                                                0x000000FFL
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK                                            0x00000700L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK                                            0x03FF0000L
+//BIFP6_PCIE_LC_PORT_ORDER
+#define BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT                                                       0x0
+#define BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK                                                         0x0000000FL
+//BIFP6_PCIEP_BCH_ECC_CNTL
+#define BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT                                                     0x0
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT                                              0x8
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT                                                 0x10
+#define BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK                                                       0x00000001L
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK                                                0x0000FF00L
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK                                                   0xFFFF0000L
+//BIFP6_PCIEP_HPGI_PRIVATE
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT                                      0x3
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT                                        0x6
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK                                        0x00000008L
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK                                          0x00000040L
+//BIFP6_PCIEP_HPGI
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT                                                    0x0
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT                                                    0x1
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT                                                  0x2
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT                                                  0x3
+#define BIFP6_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT                                                                0x7
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT                                                0x8
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT                                                0x9
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT                                              0xa
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT                                              0xb
+#define BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT                                 0xf
+#define BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT                                     0x10
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK                                                      0x00000001L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK                                                      0x00000002L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK                                                    0x00000004L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK                                                    0x00000008L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_HOOK_MASK                                                                  0x00000080L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK                                                  0x00000100L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK                                                  0x00000200L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK                                                0x00000400L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK                                                0x00000800L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK                                   0x00008000L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK                                       0x00010000L
+//BIFP6_PCIEP_HCNT_DESCRIPTOR
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT                                    0x0
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT                                 0x1f
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK                                      0x00001FFFL
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK                                   0x80000000L
+//BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT                                          0x0
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT                                        0x10
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK                                            0x0000FFFFL
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK                                          0x00FF0000L
+//BIFP6_PCIE_LC_CNTL8
+#define BIFP6_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT                                                    0x0
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT                                                         0x2
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT                                                  0x3
+#define BIFP6_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT                                                           0x7
+#define BIFP6_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT                                                   0x8
+#define BIFP6_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT                                                      0x9
+#define BIFP6_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT                                            0xa
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT                                               0xb
+#define BIFP6_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT                                      0xc
+#define BIFP6_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT                                                0xd
+#define BIFP6_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT                                                        0x11
+#define BIFP6_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT                                                           0x12
+#define BIFP6_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT                                                       0x16
+#define BIFP6_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT                                                               0x17
+#define BIFP6_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT                                                         0x19
+#define BIFP6_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT                                                0x1a
+#define BIFP6_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT                                                 0x1b
+#define BIFP6_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT                                                         0x1c
+#define BIFP6_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT                                                0x1d
+#define BIFP6_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT                                             0x1e
+#define BIFP6_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK                                                      0x00000003L
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK                                                           0x00000004L
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK                                                    0x00000078L
+#define BIFP6_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK                                                             0x00000080L
+#define BIFP6_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK                                                     0x00000100L
+#define BIFP6_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK                                                        0x00000200L
+#define BIFP6_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK                                              0x00000400L
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK                                                 0x00000800L
+#define BIFP6_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK                                        0x00001000L
+#define BIFP6_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK                                                  0x0001E000L
+#define BIFP6_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK                                                          0x00020000L
+#define BIFP6_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK                                                             0x003C0000L
+#define BIFP6_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK                                                         0x00400000L
+#define BIFP6_PCIE_LC_CNTL8__LC_FOM_TIME_MASK                                                                 0x01800000L
+#define BIFP6_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK                                                           0x02000000L
+#define BIFP6_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK                                                  0x04000000L
+#define BIFP6_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK                                                   0x08000000L
+#define BIFP6_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK                                                           0x10000000L
+#define BIFP6_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK                                                  0x20000000L
+#define BIFP6_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK                                               0xC0000000L
+//BIFP6_PCIE_LC_CNTL9
+#define BIFP6_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT                                           0x0
+#define BIFP6_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT                                              0x1
+#define BIFP6_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT                                                0x3
+#define BIFP6_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT                                                       0x4
+#define BIFP6_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT                                                 0x6
+#define BIFP6_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT                                                 0x8
+#define BIFP6_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT                            0xa
+#define BIFP6_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT                                                   0xb
+#define BIFP6_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT                                               0xc
+#define BIFP6_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT                                                    0xd
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT                                                 0xe
+#define BIFP6_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT                                                 0x18
+#define BIFP6_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT                                                0x19
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT                                                  0x1a
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT                                                 0x1b
+#define BIFP6_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT                                              0x1c
+#define BIFP6_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT                               0x1d
+#define BIFP6_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT                                      0x1e
+#define BIFP6_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT                                      0x1f
+#define BIFP6_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK                                             0x00000001L
+#define BIFP6_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK                                                0x00000006L
+#define BIFP6_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK                                                  0x00000008L
+#define BIFP6_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK                                                         0x00000030L
+#define BIFP6_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK                                                   0x000000C0L
+#define BIFP6_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK                                                   0x00000300L
+#define BIFP6_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK                              0x00000400L
+#define BIFP6_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK                                                     0x00000800L
+#define BIFP6_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK                                                 0x00001000L
+#define BIFP6_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK                                                      0x00002000L
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK                                                   0x00FFC000L
+#define BIFP6_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK                                                   0x01000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK                                                  0x02000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK                                                    0x04000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK                                                   0x08000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK                                                0x10000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK                                 0x20000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK                                        0x40000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK                                        0x80000000L
+//BIFP6_PCIE_LC_FORCE_COEFF2
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT                                                0x0
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT                                           0x1
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT                                               0x7
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT                                          0xd
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT                                        0x13
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK                                                  0x00000001L
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK                                             0x0000007EL
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK                                                 0x00001F80L
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK                                            0x0007E000L
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK                                          0x00080000L
+//BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT                         0x0
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT                                0x1
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT                                    0x7
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT                               0xd
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT                                        0x13
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT                                        0x19
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK                           0x00000001L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK                                  0x0000007EL
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK                                      0x00001F80L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK                                 0x0007E000L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK                                          0x01F80000L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK                                          0x7E000000L
+//BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT                                       0x0
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT                                     0x10
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK                                         0x0000FFFFL
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK                                       0x00FF0000L
+//BIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT             0x0
+#define BIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT               0x1
+#define BIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK               0x00000001L
+#define BIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK                 0x00000002L
+//BIFP6_PCIE_LC_CNTL10
+#define BIFP6_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT                      0x0
+#define BIFP6_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT                                         0x1
+#define BIFP6_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT                                             0x2
+#define BIFP6_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT                                            0x4
+#define BIFP6_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT                                                       0x6
+#define BIFP6_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT                                                      0x10
+#define BIFP6_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT                                     0x1a
+#define BIFP6_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT                                                0x1b
+#define BIFP6_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT                                              0x1d
+#define BIFP6_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT                                 0x1e
+#define BIFP6_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT                                 0x1f
+#define BIFP6_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK                        0x00000001L
+#define BIFP6_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK                                           0x00000002L
+#define BIFP6_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK                                               0x0000000CL
+#define BIFP6_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK                                              0x00000030L
+#define BIFP6_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK                                                         0x0000FFC0L
+#define BIFP6_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK                                                        0x03FF0000L
+#define BIFP6_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK                                       0x04000000L
+#define BIFP6_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK                                                  0x18000000L
+#define BIFP6_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK                                                0x20000000L
+#define BIFP6_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK                                   0x40000000L
+#define BIFP6_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK                                   0x80000000L
+//BIFP6_PCIE_LC_CNTL11
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT                                            0x0
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT                                          0x1
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT                                          0x2
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT                                          0x3
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT                                         0x5
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT                                          0x9
+#define BIFP6_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT                                    0xd
+#define BIFP6_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT                                          0xe
+#define BIFP6_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT                                           0xf
+#define BIFP6_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT                                                0x10
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT                       0x11
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT                         0x12
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT                              0x13
+#define BIFP6_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT                        0x14
+#define BIFP6_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT                                   0x15
+#define BIFP6_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT                                        0x16
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT                                                               0x17
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT                                                        0x18
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT                                                             0x1a
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT                                                             0x1b
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT                                                   0x1c
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT                                                     0x1e
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK                                              0x00000001L
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK                                            0x00000002L
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK                                            0x00000004L
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK                                            0x00000018L
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK                                           0x000001E0L
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK                                            0x00001E00L
+#define BIFP6_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK                                      0x00002000L
+#define BIFP6_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK                                            0x00004000L
+#define BIFP6_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK                                             0x00008000L
+#define BIFP6_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK                                                  0x00010000L
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK                         0x00020000L
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK                           0x00040000L
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK                                0x00080000L
+#define BIFP6_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK                          0x00100000L
+#define BIFP6_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK                                     0x00200000L
+#define BIFP6_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK                                          0x00400000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_EN_MASK                                                                 0x00800000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK                                                          0x03000000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK                                                               0x04000000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK                                                               0x08000000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK                                                     0x30000000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK                                                       0xC0000000L
+//BIFP6_PCIE_LC_CNTL12
+#define BIFP6_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT                                         0x0
+#define BIFP6_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT                                0x1
+#define BIFP6_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT                                        0x2
+#define BIFP6_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT                                            0x3
+#define BIFP6_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT                                 0x4
+#define BIFP6_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT                                      0x5
+#define BIFP6_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT                                         0x6
+#define BIFP6_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT                                                     0x7
+#define BIFP6_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT                                           0x8
+#define BIFP6_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT                                       0x9
+#define BIFP6_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT                                              0xa
+#define BIFP6_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT                                   0xb
+#define BIFP6_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT                                                0xc
+#define BIFP6_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT                                             0xd
+#define BIFP6_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT                                            0xe
+#define BIFP6_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT                                                0xf
+#define BIFP6_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT                                0x10
+#define BIFP6_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT                              0x11
+#define BIFP6_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT                            0x12
+#define BIFP6_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT                                          0x13
+#define BIFP6_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT                                                 0x14
+#define BIFP6_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT                                          0x15
+#define BIFP6_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT                                             0x16
+#define BIFP6_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT                                            0x17
+#define BIFP6_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT                                            0x1f
+#define BIFP6_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK                                           0x00000001L
+#define BIFP6_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK                                  0x00000002L
+#define BIFP6_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK                                          0x00000004L
+#define BIFP6_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK                                              0x00000008L
+#define BIFP6_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK                                   0x00000010L
+#define BIFP6_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK                                        0x00000020L
+#define BIFP6_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK                                           0x00000040L
+#define BIFP6_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK                                                       0x00000080L
+#define BIFP6_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK                                             0x00000100L
+#define BIFP6_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK                                         0x00000200L
+#define BIFP6_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK                                                0x00000400L
+#define BIFP6_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK                                     0x00000800L
+#define BIFP6_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK                                                  0x00001000L
+#define BIFP6_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK                                               0x00002000L
+#define BIFP6_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK                                              0x00004000L
+#define BIFP6_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK                                                  0x00008000L
+#define BIFP6_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK                                  0x00010000L
+#define BIFP6_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK                                0x00020000L
+#define BIFP6_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK                              0x00040000L
+#define BIFP6_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK                                            0x00080000L
+#define BIFP6_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK                                                   0x00100000L
+#define BIFP6_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK                                            0x00200000L
+#define BIFP6_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK                                               0x00400000L
+#define BIFP6_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK                                              0x00800000L
+#define BIFP6_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK                                              0x80000000L
+//BIFP6_PCIE_LC_SAVE_RESTORE_1
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT                                               0x0
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT                                        0x1
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT                                            0x2
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT                                      0xa
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT                                             0xb
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT                                  0xc
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT                                    0xd
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT                                           0xe
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT                                          0x10
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK                                                 0x00000001L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK                                          0x00000002L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK                                              0x000003FCL
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK                                        0x00000400L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK                                               0x00000800L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK                                    0x00001000L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK                                      0x00002000L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK                                             0x0000C000L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK                                            0xFFFF0000L
+//BIFP6_PCIE_LC_SAVE_RESTORE_2
+#define BIFP6_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT                                          0x0
+#define BIFP6_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK                                            0xFFFFFFFFL
+//BIFP6_PCIE_LC_SAVE_RESTORE_3
+#define BIFP6_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT                                0x0
+#define BIFP6_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK                                  0x00000001L
+
+
+// addressBlock: nbio_pcie0_pciedir
+//PCIE_RESERVED
+#define PCIE_RESERVED__RESERVED__SHIFT                                                                        0x0
+#define PCIE_RESERVED__RESERVED_MASK                                                                          0xFFFFFFFFL
+//PCIE_SCRATCH
+#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                                     0x0
+#define PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                                       0xFFFFFFFFL
+//PCIE_RX_NUM_NAK
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT                                                                    0x0
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK                                                                      0xFFFFFFFFL
+//PCIE_RX_NUM_NAK_GENERATED
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT                                                0x0
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK                                                  0xFFFFFFFFL
+//PCIE_CNTL
+#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                                      0x0
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT                                                               0x1
+#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                                   0x7
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                                             0x8
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT                                                                0x9
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT                                                              0xa
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT                                                                   0xf
+#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT                                                                   0x10
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT                                                             0x11
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT                                                                0x12
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT                                                        0x13
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT                                                             0x14
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT                                                               0x15
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT                                                            0x16
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT                                                           0x17
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                                0x1e
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT                                                            0x1f
+#define PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                                        0x00000001L
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK                                                                 0x0000000EL
+#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                                     0x00000080L
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                                               0x00000100L
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK                                                                  0x00000200L
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK                                                                0x00001C00L
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK                                                                     0x00008000L
+#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK                                                                     0x00010000L
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK                                                               0x00020000L
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK                                                                  0x00040000L
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK                                                          0x00080000L
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK                                                               0x00100000L
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK                                                                 0x00200000L
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK                                                              0x00400000L
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK                                                             0x00800000L
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                                  0x40000000L
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK                                                              0x80000000L
+//PCIE_CONFIG_CNTL
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT                                                              0x0
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT                                                0x8
+#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                0x9
+#define PCIE_CONFIG_CNTL__CI_10BIT_TAG_EN_OVERRIDE__SHIFT                                                     0xb
+#define PCIE_CONFIG_CNTL__CI_SWUS_10BIT_TAG_EN_OVERRIDE__SHIFT                                                0xd
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT                                                     0x10
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                     0x11
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT                                                0x14
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                                0x15
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT                                                        0x18
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                                  0x19
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT                                           0x1b
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT                                           0x1c
+#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                             0x1e
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK                                                                0x0000000FL
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK                                                  0x00000100L
+#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK                                                  0x00000600L
+#define PCIE_CONFIG_CNTL__CI_10BIT_TAG_EN_OVERRIDE_MASK                                                       0x00001800L
+#define PCIE_CONFIG_CNTL__CI_SWUS_10BIT_TAG_EN_OVERRIDE_MASK                                                  0x00006000L
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK                                                       0x00010000L
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK                                                       0x000E0000L
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK                                                  0x00100000L
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK                                                  0x00E00000L
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK                                                          0x01000000L
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                                    0x06000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK                                             0x08000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK                                             0x30000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK                                               0xC0000000L
+//PCIE_TX_TRACKING_ADDR_LO
+#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT                                                  0x2
+#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK                                                    0xFFFFFFFCL
+//PCIE_TX_TRACKING_ADDR_HI
+#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT                                                  0x0
+#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK                                                    0xFFFFFFFFL
+//PCIE_TX_TRACKING_CTRL_STATUS
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT                                               0x0
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT                                                 0x1
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT                                              0x8
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT                                         0xf
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK                                                 0x00000001L
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK                                                   0x0000000EL
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK                                                0x00007F00L
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK                                           0x00008000L
+//PCIE_TX_CTRL_4
+#define PCIE_TX_CTRL_4__TX_ARB_VC_ROUND_ROBIN_EN__SHIFT                                                       0x0
+#define PCIE_TX_CTRL_4__TX_ARB_VC0_LIMIT__SHIFT                                                               0x1
+#define PCIE_TX_CTRL_4__TX_ARB_VC1_LIMIT__SHIFT                                                               0x6
+#define PCIE_TX_CTRL_4__TX_ARB_VC_ROUND_ROBIN_EN_MASK                                                         0x00000001L
+#define PCIE_TX_CTRL_4__TX_ARB_VC0_LIMIT_MASK                                                                 0x0000003EL
+#define PCIE_TX_CTRL_4__TX_ARB_VC1_LIMIT_MASK                                                                 0x000007C0L
+//PCIE_MST_CTRL_1
+#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_ADVT__SHIFT                                                         0x0
+#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_OVERRIDE_EN__SHIFT                                                  0x8
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_PENDING_RESET_DIS__SHIFT                                            0x9
+#define PCIE_MST_CTRL_1__CI_MSTSDP_ORIG_DISC_FIX_DIS__SHIFT                                                   0xa
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_OVERRIDE_EN__SHIFT                                                  0xf
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_ADVT__SHIFT                                                         0x10
+#define PCIE_MST_CTRL_1__MST_IDLE_HYSTERESIS__SHIFT                                                           0x18
+#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_ADVT_MASK                                                           0x000000FFL
+#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_OVERRIDE_EN_MASK                                                    0x00000100L
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_PENDING_RESET_DIS_MASK                                              0x00000200L
+#define PCIE_MST_CTRL_1__CI_MSTSDP_ORIG_DISC_FIX_DIS_MASK                                                     0x00000400L
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_OVERRIDE_EN_MASK                                                    0x00008000L
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_ADVT_MASK                                                           0x00FF0000L
+#define PCIE_MST_CTRL_1__MST_IDLE_HYSTERESIS_MASK                                                             0xFF000000L
+//PCIE_COMMON_AER_MASK
+#define PCIE_COMMON_AER_MASK__PRIV_SURP_DIS_VEC__SHIFT                                                        0x0
+#define PCIE_COMMON_AER_MASK__PRIV_SURP_DIS_VEC_MASK                                                          0x000000FFL
+//PCIE_CNTL2
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT                                                              0x0
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT                                                                   0x1
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT                                                                   0x6
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT                                                             0xb
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT                                                       0xc
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT                                                              0xd
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT                                                             0xe
+#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT                                                                      0x10
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT                                                           0x11
+#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT                                                                      0x12
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT                                                                   0x13
+#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT                                                                      0x14
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT                                                           0x15
+#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT                                                                      0x16
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT                                                                   0x17
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT                                                           0x18
+#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT                                                                      0x1d
+#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT                                                                      0x1e
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT                                                                   0x1f
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK                                                                0x00000001L
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK                                                                     0x0000003EL
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK                                                                     0x000007C0L
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK                                                               0x00000800L
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK                                                         0x00001000L
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK                                                                0x00002000L
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK                                                               0x00004000L
+#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK                                                                        0x00010000L
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK                                                             0x00020000L
+#define PCIE_CNTL2__MST_MEM_LS_EN_MASK                                                                        0x00040000L
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK                                                                     0x00080000L
+#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK                                                                        0x00100000L
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK                                                             0x00200000L
+#define PCIE_CNTL2__MST_MEM_SD_EN_MASK                                                                        0x00400000L
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK                                                                     0x00800000L
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK                                                             0x1F000000L
+#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK                                                                        0x20000000L
+#define PCIE_CNTL2__MST_MEM_DS_EN_MASK                                                                        0x40000000L
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK                                                                     0x80000000L
+//PCIE_RX_CNTL2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                                    0x0
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT                                                        0x1
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT                                                        0x2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT                                                     0x3
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT                                                      0x4
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT                                                          0x5
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT                                                               0x8
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT                                                            0x9
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT                                                                0xc
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT                                                                0xd
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT                                                                0xe
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT                                                        0x10
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                                                 0x1c
+#define PCIE_RX_CNTL2__RX_PD_OVERFLOW_FIX_DISABLE__SHIFT                                                      0x1f
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                                      0x00000001L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK                                                          0x00000002L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK                                                          0x00000004L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK                                                       0x00000008L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK                                                        0x00000010L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK                                                            0x00000020L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK                                                                 0x00000100L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK                                                              0x00000E00L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK                                                                  0x00001000L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK                                                                  0x00002000L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK                                                                  0x00004000L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK                                                          0x03FF0000L
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                                   0x70000000L
+#define PCIE_RX_CNTL2__RX_PD_OVERFLOW_FIX_DISABLE_MASK                                                        0x80000000L
+//PCIE_TX_F0_ATTR_CNTL
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT                                                     0x0
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT                                                    0x2
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT                                                   0x4
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT                                                      0x6
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT                                                     0x8
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT                                                     0xa
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT                                                    0xc
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK                                                       0x00000003L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK                                                      0x0000000CL
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK                                                     0x00000030L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK                                                        0x000000C0L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK                                                       0x00000300L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK                                                       0x00000C00L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK                                                      0x00003000L
+//PCIE_TX_SWUS_ATTR_CNTL
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT                                                 0x0
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT                                                0x2
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT                                               0x4
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT                                                  0x6
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT                                                 0x8
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT                                                 0xa
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT                                                0xc
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK                                                   0x00000003L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK                                                  0x0000000CL
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK                                                 0x00000030L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK                                                    0x000000C0L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK                                                   0x00000300L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK                                                   0x00000C00L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK                                                  0x00003000L
+//PCIE_CI_CNTL
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT                                                              0x2
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT                                                           0x4
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT                                                            0x6
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT                                                              0x8
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT                                                               0x9
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT                                                             0xa
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT                                                            0xb
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT                                                             0xc
+#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT                                              0x10
+#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS__SHIFT                                                  0x11
+#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS__SHIFT                                         0x12
+#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS__SHIFT                                             0x13
+#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS__SHIFT                                                     0x14
+#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG__SHIFT                                                    0x15
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT                                                           0x16
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT                                                       0x17
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT                                                         0x18
+#define PCIE_CI_CNTL__CI_MSTSPLIT_DIS__SHIFT                                                                  0x19
+#define PCIE_CI_CNTL__CI_MSTSPLIT_REQ_CHAIN_DIS__SHIFT                                                        0x1a
+#define PCIE_CI_CNTL__TX_MWR_SPLIT_QW_PKT_SAFE_MODE__SHIFT                                                    0x1b
+#define PCIE_CI_CNTL__CI_MST_TAG_BORROWING_DIS__SHIFT                                                         0x1c
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN__SHIFT                                              0x1d
+#define PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN__SHIFT                                             0x1e
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN__SHIFT                                         0x1f
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK                                                                0x00000004L
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK                                                             0x00000010L
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK                                                              0x000000C0L
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK                                                                0x00000100L
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK                                                                 0x00000200L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK                                                               0x00000400L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK                                                              0x00000800L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK                                                               0x00001000L
+#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK                                                0x00010000L
+#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS_MASK                                                    0x00020000L
+#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS_MASK                                           0x00040000L
+#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS_MASK                                               0x00080000L
+#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS_MASK                                                       0x00100000L
+#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG_MASK                                                      0x00200000L
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK                                                             0x00400000L
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK                                                         0x00800000L
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK                                                           0x01000000L
+#define PCIE_CI_CNTL__CI_MSTSPLIT_DIS_MASK                                                                    0x02000000L
+#define PCIE_CI_CNTL__CI_MSTSPLIT_REQ_CHAIN_DIS_MASK                                                          0x04000000L
+#define PCIE_CI_CNTL__TX_MWR_SPLIT_QW_PKT_SAFE_MODE_MASK                                                      0x08000000L
+#define PCIE_CI_CNTL__CI_MST_TAG_BORROWING_DIS_MASK                                                           0x10000000L
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN_MASK                                                0x20000000L
+#define PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN_MASK                                               0x40000000L
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN_MASK                                           0x80000000L
+//PCIE_BUS_CNTL
+#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT                                                                     0x6
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                                               0x7
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT                                                               0xc
+#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK                                                                       0x00000040L
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                                 0x00000080L
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK                                                                 0x00001000L
+//PCIE_LC_STATE6
+#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT                                                                0x0
+#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT                                                                0x8
+#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT                                                                0x10
+#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT                                                                0x18
+#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK                                                                  0x0000003FL
+#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK                                                                  0x00003F00L
+#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK                                                                  0x003F0000L
+#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK                                                                  0x3F000000L
+//PCIE_LC_STATE7
+#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT                                                                0x0
+#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT                                                                0x8
+#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT                                                                0x10
+#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT                                                                0x18
+#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK                                                                  0x0000003FL
+#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK                                                                  0x00003F00L
+#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK                                                                  0x003F0000L
+#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK                                                                  0x3F000000L
+//PCIE_LC_STATE8
+#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT                                                                0x0
+#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT                                                                0x8
+#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT                                                                0x10
+#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT                                                                0x18
+#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK                                                                  0x0000003FL
+#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK                                                                  0x00003F00L
+#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK                                                                  0x003F0000L
+#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK                                                                  0x3F000000L
+//PCIE_LC_STATE9
+#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT                                                                0x0
+#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT                                                                0x8
+#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT                                                                0x10
+#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT                                                                0x18
+#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK                                                                  0x0000003FL
+#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK                                                                  0x00003F00L
+#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK                                                                  0x003F0000L
+#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK                                                                  0x3F000000L
+//PCIE_LC_STATE10
+#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT                                                               0x0
+#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT                                                               0x8
+#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT                                                               0x10
+#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT                                                               0x18
+#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK                                                                 0x0000003FL
+#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK                                                                 0x00003F00L
+#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK                                                                 0x003F0000L
+#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK                                                                 0x3F000000L
+//PCIE_LC_STATE11
+#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT                                                               0x0
+#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT                                                               0x8
+#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT                                                               0x10
+#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT                                                               0x18
+#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK                                                                 0x0000003FL
+#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK                                                                 0x00003F00L
+#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK                                                                 0x003F0000L
+#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK                                                                 0x3F000000L
+//PCIE_LC_STATUS1
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT                                                               0x0
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT                                                               0x1
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT                                                       0x2
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT                                                        0x5
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK                                                                 0x00000001L
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK                                                                 0x00000002L
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK                                                         0x0000001CL
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK                                                          0x000000E0L
+//PCIE_LC_STATUS2
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT                                                       0x0
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT                                                               0x10
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK                                                         0x0000FFFFL
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK                                                                 0xFFFF0000L
+//PCIE_TX_CNTL3
+#define PCIE_TX_CNTL3__TX_REGNUM_FROM_ADDR_CFGWR_IOWR_DIS__SHIFT                                              0x0
+#define PCIE_TX_CNTL3__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE__SHIFT                                             0x1
+#define PCIE_TX_CNTL3__TX_STOP_TLP2_IN_REPLAY_DIS__SHIFT                                                      0x4
+#define PCIE_TX_CNTL3__TX_PDAT_CREDIT_RELEASE_FIX_DIS__SHIFT                                                  0x5
+#define PCIE_TX_CNTL3__TX_ARB_P_AFTER_NP_EN__SHIFT                                                            0x6
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_2HDR_MWR_EN__SHIFT                                                       0x7
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_MWR_SIZE__SHIFT                                                          0x8
+#define PCIE_TX_CNTL3__TX_ENCMSG_HDR_FROM_SDP_REQ_EN__SHIFT                                                   0x13
+#define PCIE_TX_CNTL3__TX_DROP_REQ_TARGETING_BAD_PORT_EN__SHIFT                                               0x14
+#define PCIE_TX_CNTL3__MCA_CLKGATE_DIS__SHIFT                                                                 0x15
+#define PCIE_TX_CNTL3__TX_PMFSM_OLD_MODE__SHIFT                                                               0x16
+#define PCIE_TX_CNTL3__TX_MPDAT_EVICT_TAIL_FIX_DIS__SHIFT                                                     0x17
+#define PCIE_TX_CNTL3__TX_CHK_FC_FOR_L1_DIS__SHIFT                                                            0x18
+#define PCIE_TX_CNTL3__TX_8B_CPL_AND_WRITE_EN__SHIFT                                                          0x19
+#define PCIE_TX_CNTL3__TX_B2B_ACK_FIX_DIS__SHIFT                                                              0x1a
+#define PCIE_TX_CNTL3__TXDLLP_B2B_DIS__SHIFT                                                                  0x1b
+#define PCIE_TX_CNTL3__TXDL_TLP_AFTER_DLLP_EN__SHIFT                                                          0x1c
+#define PCIE_TX_CNTL3__TXDL_STP_SDP_AT_DW3_EN__SHIFT                                                          0x1d
+#define PCIE_TX_CNTL3__TX_SILENT_DROP_P_IN_L1SS_DIS__SHIFT                                                    0x1e
+#define PCIE_TX_CNTL3__TX_SILENT_DROP_NP_IN_L1SS_DIS__SHIFT                                                   0x1f
+#define PCIE_TX_CNTL3__TX_REGNUM_FROM_ADDR_CFGWR_IOWR_DIS_MASK                                                0x00000001L
+#define PCIE_TX_CNTL3__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE_MASK                                               0x0000000EL
+#define PCIE_TX_CNTL3__TX_STOP_TLP2_IN_REPLAY_DIS_MASK                                                        0x00000010L
+#define PCIE_TX_CNTL3__TX_PDAT_CREDIT_RELEASE_FIX_DIS_MASK                                                    0x00000020L
+#define PCIE_TX_CNTL3__TX_ARB_P_AFTER_NP_EN_MASK                                                              0x00000040L
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_2HDR_MWR_EN_MASK                                                         0x00000080L
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_MWR_SIZE_MASK                                                            0x0000FF00L
+#define PCIE_TX_CNTL3__TX_ENCMSG_HDR_FROM_SDP_REQ_EN_MASK                                                     0x00080000L
+#define PCIE_TX_CNTL3__TX_DROP_REQ_TARGETING_BAD_PORT_EN_MASK                                                 0x00100000L
+#define PCIE_TX_CNTL3__MCA_CLKGATE_DIS_MASK                                                                   0x00200000L
+#define PCIE_TX_CNTL3__TX_PMFSM_OLD_MODE_MASK                                                                 0x00400000L
+#define PCIE_TX_CNTL3__TX_MPDAT_EVICT_TAIL_FIX_DIS_MASK                                                       0x00800000L
+#define PCIE_TX_CNTL3__TX_CHK_FC_FOR_L1_DIS_MASK                                                              0x01000000L
+#define PCIE_TX_CNTL3__TX_8B_CPL_AND_WRITE_EN_MASK                                                            0x02000000L
+#define PCIE_TX_CNTL3__TX_B2B_ACK_FIX_DIS_MASK                                                                0x04000000L
+#define PCIE_TX_CNTL3__TXDLLP_B2B_DIS_MASK                                                                    0x08000000L
+#define PCIE_TX_CNTL3__TXDL_TLP_AFTER_DLLP_EN_MASK                                                            0x10000000L
+#define PCIE_TX_CNTL3__TXDL_STP_SDP_AT_DW3_EN_MASK                                                            0x20000000L
+#define PCIE_TX_CNTL3__TX_SILENT_DROP_P_IN_L1SS_DIS_MASK                                                      0x40000000L
+#define PCIE_TX_CNTL3__TX_SILENT_DROP_NP_IN_L1SS_DIS_MASK                                                     0x80000000L
+//PCIE_TX_STATUS
+#define PCIE_TX_STATUS__TX_MST_MEM_READY__SHIFT                                                               0x0
+#define PCIE_TX_STATUS__CI_MST_REQ_IDLE__SHIFT                                                                0x1
+#define PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD__SHIFT                                                          0x2
+#define PCIE_TX_STATUS__CI_MST_WRRSP_IDLE__SHIFT                                                              0x3
+#define PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE__SHIFT                                                              0x4
+#define PCIE_TX_STATUS__CI_MST_TX_IDLE__SHIFT                                                                 0x5
+#define PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE__SHIFT                                                             0x6
+#define PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE__SHIFT                                                             0x7
+#define PCIE_TX_STATUS__TX_P_HDR_EMPTY__SHIFT                                                                 0x8
+#define PCIE_TX_STATUS__TX_NP_HDR_EMPTY__SHIFT                                                                0x9
+#define PCIE_TX_STATUS__TX_P_DAT_EMPTY__SHIFT                                                                 0xa
+#define PCIE_TX_STATUS__TX_NP_DAT_EMPTY__SHIFT                                                                0xb
+#define PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS__SHIFT                                                       0xc
+#define PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS__SHIFT                                                      0xd
+#define PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS__SHIFT                                                       0xe
+#define PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS__SHIFT                                                      0xf
+#define PCIE_TX_STATUS__TX_MST_MEM_READY_MASK                                                                 0x00000001L
+#define PCIE_TX_STATUS__CI_MST_REQ_IDLE_MASK                                                                  0x00000002L
+#define PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD_MASK                                                            0x00000004L
+#define PCIE_TX_STATUS__CI_MST_WRRSP_IDLE_MASK                                                                0x00000008L
+#define PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE_MASK                                                                0x00000010L
+#define PCIE_TX_STATUS__CI_MST_TX_IDLE_MASK                                                                   0x00000020L
+#define PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE_MASK                                                               0x00000040L
+#define PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE_MASK                                                               0x00000080L
+#define PCIE_TX_STATUS__TX_P_HDR_EMPTY_MASK                                                                   0x00000100L
+#define PCIE_TX_STATUS__TX_NP_HDR_EMPTY_MASK                                                                  0x00000200L
+#define PCIE_TX_STATUS__TX_P_DAT_EMPTY_MASK                                                                   0x00000400L
+#define PCIE_TX_STATUS__TX_NP_DAT_EMPTY_MASK                                                                  0x00000800L
+#define PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS_MASK                                                         0x00001000L
+#define PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS_MASK                                                        0x00002000L
+#define PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS_MASK                                                         0x00004000L
+#define PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS_MASK                                                        0x00008000L
+//PCIE_WPR_CNTL
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT                                                            0x0
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT                                                            0x1
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT                                                            0x2
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT                                                                0x3
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT                                                                0x4
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT                                                                0x5
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT                                                                0x6
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK                                                              0x00000001L
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK                                                              0x00000002L
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK                                                              0x00000004L
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK                                                                  0x00000008L
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK                                                                  0x00000010L
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK                                                                  0x00000020L
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK                                                                  0x00000040L
+//PCIE_RX_LAST_TLP0
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT                                                                0x0
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK                                                                  0xFFFFFFFFL
+//PCIE_RX_LAST_TLP1
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT                                                                0x0
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK                                                                  0xFFFFFFFFL
+//PCIE_RX_LAST_TLP2
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT                                                                0x0
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK                                                                  0xFFFFFFFFL
+//PCIE_RX_LAST_TLP3
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT                                                                0x0
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK                                                                  0xFFFFFFFFL
+//PCIE_TX_LAST_TLP0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT                                                                0x0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK                                                                  0xFFFFFFFFL
+//PCIE_TX_LAST_TLP1
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT                                                                0x0
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK                                                                  0xFFFFFFFFL
+//PCIE_TX_LAST_TLP2
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT                                                                0x0
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK                                                                  0xFFFFFFFFL
+//PCIE_TX_LAST_TLP3
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT                                                                0x0
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK                                                                  0xFFFFFFFFL
+//PCIE_I2C_REG_ADDR_EXPAND
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT                                                         0x0
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK                                                           0x0001FFFFL
+//PCIE_I2C_REG_DATA
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT                                                                0x0
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK                                                                  0xFFFFFFFFL
+//PCIE_CFG_CNTL
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                                        0x0
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                                   0x1
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                                   0x2
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                                          0x00000001L
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                                     0x00000002L
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                                     0x00000004L
+//PCIE_LC_PM_CNTL
+#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT                                                         0x0
+#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT                                                         0x4
+#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT                                                         0x8
+#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT                                                         0xc
+#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT                                                         0x10
+#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT                                                         0x14
+#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT                                                         0x18
+#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT                                                         0x1c
+#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK                                                           0x0000000FL
+#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK                                                           0x000000F0L
+#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK                                                           0x00000F00L
+#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK                                                           0x0000F000L
+#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK                                                           0x000F0000L
+#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK                                                           0x00F00000L
+#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK                                                           0x0F000000L
+#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK                                                           0xF0000000L
+//PCIE_LC_PORT_ORDER_CNTL
+#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN__SHIFT                                                      0x0
+#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN_MASK                                                        0x00000001L
+//PCIE_P_CNTL
+#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT                                                                        0x0
+#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT                                                                   0x1
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT                                                                  0x4
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT                                                                  0x5
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT                                                                  0x6
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT                                                                  0x7
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT                                                                  0x8
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT                                                                   0xc
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT                                                           0xd
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT                                                                  0xe
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT                                                               0x10
+#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT                                                         0x11
+#define PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT__SHIFT                                                     0x12
+#define PCIE_P_CNTL__MASTER_PLL_LANE_NUM__SHIFT                                                               0x13
+#define PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN__SHIFT                                                      0x17
+#define PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL__SHIFT                                                     0x18
+#define PCIE_P_CNTL__P_PWRDN_EN_MASK                                                                          0x00000001L
+#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK                                                                     0x00000002L
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK                                                                    0x00000010L
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK                                                                    0x00000020L
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK                                                                    0x00000040L
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK                                                                    0x00000080L
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK                                                                    0x00000100L
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK                                                                     0x00001000L
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK                                                             0x00002000L
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK                                                                    0x0000C000L
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK                                                                 0x00010000L
+#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK                                                           0x00020000L
+#define PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT_MASK                                                       0x00040000L
+#define PCIE_P_CNTL__MASTER_PLL_LANE_NUM_MASK                                                                 0x00780000L
+#define PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN_MASK                                                        0x00800000L
+#define PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL_MASK                                                       0x01000000L
+//PCIE_P_BUF_STATUS
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT                                                              0x0
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT                                                             0x10
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK                                                                0x0000FFFFL
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK                                                               0xFFFF0000L
+//PCIE_P_DECODER_STATUS
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT                                                            0x0
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK                                                              0x0000FFFFL
+//PCIE_P_MISC_STATUS
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT                                                               0x0
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT                                                            0x10
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK                                                                 0x000000FFL
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK                                                              0xFFFF0000L
+//PCIE_P_RCV_L0S_FTS_DET
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT                                                  0x0
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT                                                  0x8
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK                                                    0x000000FFL
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK                                                    0x0000FF00L
+//PCIE_TX_CCIX_CNTL0
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_SDP_ENABLE__SHIFT                                                          0x0
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_L1_ON_SDP_DISCONNECT_EN__SHIFT                                             0x1
+#define PCIE_TX_CCIX_CNTL0__CCIX_SYNCFLOOD_DIS__SHIFT                                                         0x2
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_FLUSH_DIS__SHIFT                                                           0x3
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_SDP_ENABLE_MASK                                                            0x00000001L
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_L1_ON_SDP_DISCONNECT_EN_MASK                                               0x00000002L
+#define PCIE_TX_CCIX_CNTL0__CCIX_SYNCFLOOD_DIS_MASK                                                           0x00000004L
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_FLUSH_DIS_MASK                                                             0x00000008L
+//PCIE_TX_CCIX_CNTL1
+#define PCIE_TX_CCIX_CNTL1__TXCCIX_VENDOR_ID__SHIFT                                                           0x0
+#define PCIE_TX_CCIX_CNTL1__TXCCIX_VENDOR_ID_MASK                                                             0x0000FFFFL
+//PCIE_TX_CCIX_PORT_MAP
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_SDP_PORT_NUM_INSERT_EN__SHIFT                                             0x0
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_SDP_PORT_NUM_INSERT_SEL__SHIFT                                            0x1
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_MODE_EN__SHIFT                                                0x4
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_PORT_NUMBER__SHIFT                                                        0x5
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_FIRST_CCIX_PORT_NUM__SHIFT                                                0x8
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_SEL__SHIFT                                               0xa
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_REMOVE0__SHIFT                                           0xe
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_REMOVE1__SHIFT                                           0xf
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_SDP_PORT_NUM_INSERT_EN_MASK                                               0x00000001L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_SDP_PORT_NUM_INSERT_SEL_MASK                                              0x0000000EL
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_MODE_EN_MASK                                                  0x00000010L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_PORT_NUMBER_MASK                                                          0x000000E0L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_FIRST_CCIX_PORT_NUM_MASK                                                  0x00000300L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_SEL_MASK                                                 0x00003C00L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_REMOVE0_MASK                                             0x00004000L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_REMOVE1_MASK                                             0x00008000L
+//PCIE_TX_CCIX_ERR_CTL
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_WRRSP_NONDATAERR_MODE__SHIFT                                            0x0
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_RDRSP_NONDATAERR_MODE__SHIFT                                            0x2
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_RDRSP_DATAERR_MODE__SHIFT                                               0x5
+#define PCIE_TX_CCIX_ERR_CTL__TXCCIX_MASK_POISON_EN__SHIFT                                                    0x8
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_WRRSP_NONDATAERR_MODE_MASK                                              0x00000003L
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_RDRSP_NONDATAERR_MODE_MASK                                              0x0000001CL
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_RDRSP_DATAERR_MODE_MASK                                                 0x000000E0L
+#define PCIE_TX_CCIX_ERR_CTL__TXCCIX_MASK_POISON_EN_MASK                                                      0x00000100L
+//PCIE_RX_CCIX_CTL0
+#define PCIE_RX_CCIX_CTL0__RXCCIX_CTO_VALUE__SHIFT                                                            0x0
+#define PCIE_RX_CCIX_CTL0__RXCCIX_CTO_STATUS__SHIFT                                                           0x3
+#define PCIE_RX_CCIX_CTL0__TXCCIX_REQMUX_MODE__SHIFT                                                          0xe
+#define PCIE_RX_CCIX_CTL0__TXCCIX_REQ_MUXTIME_LIMIT__SHIFT                                                    0x10
+#define PCIE_RX_CCIX_CTL0__RXCCIX_CTO_VALUE_MASK                                                              0x00000007L
+#define PCIE_RX_CCIX_CTL0__RXCCIX_CTO_STATUS_MASK                                                             0x00000038L
+#define PCIE_RX_CCIX_CTL0__TXCCIX_REQMUX_MODE_MASK                                                            0x00004000L
+#define PCIE_RX_CCIX_CTL0__TXCCIX_REQ_MUXTIME_LIMIT_MASK                                                      0x00FF0000L
+//PCIE_RX_AD
+#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT                                                                0x0
+#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT                                                                0x1
+#define PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT                                                                    0x2
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT                                                                  0x3
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT                                                                  0x4
+#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT                                                          0x5
+#define PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT                                                                    0x8
+#define PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT                                                                      0x9
+#define PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT                                                                    0xa
+#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT                                                                  0xb
+#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT                                                                  0xc
+#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT                                                              0xd
+#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT                                                                  0xe
+#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT                                                        0xf
+#define PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN__SHIFT                                                             0x10
+#define PCIE_RX_AD__RX_RC_UR_POIS_ATOP__SHIFT                                                                 0x11
+#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK                                                                  0x00000001L
+#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK                                                                  0x00000002L
+#define PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK                                                                      0x00000004L
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK                                                                    0x00000008L
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK                                                                    0x00000010L
+#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK                                                            0x00000020L
+#define PCIE_RX_AD__RX_RC_DROP_VDM0_MASK                                                                      0x00000100L
+#define PCIE_RX_AD__RX_RC_UR_VDM0_MASK                                                                        0x00000200L
+#define PCIE_RX_AD__RX_RC_DROP_VDM1_MASK                                                                      0x00000400L
+#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK                                                                    0x00000800L
+#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK                                                                    0x00001000L
+#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK                                                                0x00002000L
+#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK                                                                    0x00004000L
+#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK                                                          0x00008000L
+#define PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN_MASK                                                               0x00010000L
+#define PCIE_RX_AD__RX_RC_UR_POIS_ATOP_MASK                                                                   0x00020000L
+//PCIE_SDP_CTRL
+#define PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT                                                                     0x0
+#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT                                                  0x4
+#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT                                                  0x5
+#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE__SHIFT                                               0x6
+#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS__SHIFT                                                              0x7
+#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS__SHIFT                                                            0x8
+#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT                                                       0x9
+#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT                                                        0xa
+#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT                                                         0xb
+#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT                                                     0xc
+#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN__SHIFT                                                    0xd
+#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL__SHIFT                                             0xe
+#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT                                                   0xf
+#define PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN__SHIFT                                                             0x10
+#define PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN__SHIFT                                                0x11
+#define PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN__SHIFT                               0x12
+#define PCIE_SDP_CTRL__TX_ENCMSG_USE_SDP_EP_DIS__SHIFT                                                        0x13
+#define PCIE_SDP_CTRL__TX_IGNORE_POISON_BIT_EN__SHIFT                                                         0x14
+#define PCIE_SDP_CTRL__TX_RBUF_WRITE_2HDR_DIS__SHIFT                                                          0x15
+#define PCIE_SDP_CTRL__TX_RBUF_READ_2HDR_DIS__SHIFT                                                           0x16
+#define PCIE_SDP_CTRL__TX_RBUF_END_TLP2_DIS__SHIFT                                                            0x17
+#define PCIE_SDP_CTRL__TX_MULTICYCLE_DLLP_DIS__SHIFT                                                          0x18
+#define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE__SHIFT                                                            0x19
+#define PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER__SHIFT                                                               0x1a
+#define PCIE_SDP_CTRL__CI_SDP_RECONFIG_EN__SHIFT                                                              0x1d
+#define PCIE_SDP_CTRL__TX_ENCMSG_REQID_FROM_REQSTREAMID_EN__SHIFT                                             0x1e
+#define PCIE_SDP_CTRL__SDP_UNIT_ID_MASK                                                                       0x0000000FL
+#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK                                                    0x00000010L
+#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK                                                    0x00000020L
+#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE_MASK                                                 0x00000040L
+#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS_MASK                                                                0x00000080L
+#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS_MASK                                                              0x00000100L
+#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK                                                         0x00000200L
+#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK                                                          0x00000400L
+#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK                                                           0x00000800L
+#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK                                                       0x00001000L
+#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN_MASK                                                      0x00002000L
+#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL_MASK                                               0x00004000L
+#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK                                                     0x00008000L
+#define PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN_MASK                                                               0x00010000L
+#define PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN_MASK                                                  0x00020000L
+#define PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN_MASK                                 0x00040000L
+#define PCIE_SDP_CTRL__TX_ENCMSG_USE_SDP_EP_DIS_MASK                                                          0x00080000L
+#define PCIE_SDP_CTRL__TX_IGNORE_POISON_BIT_EN_MASK                                                           0x00100000L
+#define PCIE_SDP_CTRL__TX_RBUF_WRITE_2HDR_DIS_MASK                                                            0x00200000L
+#define PCIE_SDP_CTRL__TX_RBUF_READ_2HDR_DIS_MASK                                                             0x00400000L
+#define PCIE_SDP_CTRL__TX_RBUF_END_TLP2_DIS_MASK                                                              0x00800000L
+#define PCIE_SDP_CTRL__TX_MULTICYCLE_DLLP_DIS_MASK                                                            0x01000000L
+#define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE_MASK                                                              0x02000000L
+#define PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER_MASK                                                                 0x1C000000L
+#define PCIE_SDP_CTRL__CI_SDP_RECONFIG_EN_MASK                                                                0x20000000L
+#define PCIE_SDP_CTRL__TX_ENCMSG_REQID_FROM_REQSTREAMID_EN_MASK                                               0x40000000L
+//NBIO_CLKREQb_MAP_CNTL
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_0_MAP__SHIFT                                                      0x0
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_1_MAP__SHIFT                                                      0x4
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_2_MAP__SHIFT                                                      0x8
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_3_MAP__SHIFT                                                      0xc
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_4_MAP__SHIFT                                                      0x10
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_5_MAP__SHIFT                                                      0x14
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_6_MAP__SHIFT                                                      0x18
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_CNTL_MASK__SHIFT                                                  0x1c
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_0_MAP_MASK                                                        0x0000000FL
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_1_MAP_MASK                                                        0x000000F0L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_2_MAP_MASK                                                        0x00000F00L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_3_MAP_MASK                                                        0x0000F000L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_4_MAP_MASK                                                        0x000F0000L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_5_MAP_MASK                                                        0x00F00000L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_6_MAP_MASK                                                        0x0F000000L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_CNTL_MASK_MASK                                                    0x10000000L
+//PCIE_SDP_SWUS_SLV_ATTR_CTRL
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT                                     0x0
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT                                     0x2
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT                                    0x4
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT                                    0x6
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT                                    0x8
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT                                   0xa
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT                                    0xc
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT                                    0xe
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT                                   0x10
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK                                       0x00000003L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK                                       0x0000000CL
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK                                      0x00000030L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK                                      0x000000C0L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK                                      0x00000300L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK                                     0x00000C00L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK                                      0x00003000L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK                                      0x0000C000L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK                                     0x00030000L
+//PCIE_SDP_RC_SLV_ATTR_CTRL
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR__SHIFT                                         0x0
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD__SHIFT                                         0x2
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC__SHIFT                                        0x4
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR__SHIFT                                        0x6
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD__SHIFT                                        0x8
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC__SHIFT                                       0xa
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR__SHIFT                                        0xc
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD__SHIFT                                        0xe
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC__SHIFT                                       0x10
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR_MASK                                           0x00000003L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD_MASK                                           0x0000000CL
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC_MASK                                          0x00000030L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR_MASK                                          0x000000C0L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD_MASK                                          0x00000300L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC_MASK                                         0x00000C00L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR_MASK                                          0x00003000L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD_MASK                                          0x0000C000L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC_MASK                                         0x00030000L
+//PCIE_PERF_COUNT_CNTL
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT                                                          0x0
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT                                                         0x1
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT                                                       0x2
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_SCLK_STATUS__SHIFT                                             0x1f
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK                                                            0x00000001L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK                                                           0x00000002L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK                                                         0x00000004L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_SCLK_STATUS_MASK                                               0x80000000L
+//PCIE_PERF_CNTL_TXCLK1
+#define PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL__SHIFT                                                              0x0
+#define PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL__SHIFT                                                              0x8
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER0_UPPER__SHIFT                                                          0x10
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER1_UPPER__SHIFT                                                          0x18
+#define PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL_MASK                                                                0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL_MASK                                                                0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER0_UPPER_MASK                                                            0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER1_UPPER_MASK                                                            0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK1
+#define PCIE_PERF_COUNT0_TXCLK1__COUNTER0__SHIFT                                                              0x0
+#define PCIE_PERF_COUNT0_TXCLK1__COUNTER0_MASK                                                                0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK1
+#define PCIE_PERF_COUNT1_TXCLK1__COUNTER1__SHIFT                                                              0x0
+#define PCIE_PERF_COUNT1_TXCLK1__COUNTER1_MASK                                                                0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK2
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT                                                              0x0
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT                                                              0x8
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT                                                          0x10
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT                                                          0x18
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK                                                                0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK                                                                0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK                                                            0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK                                                            0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK2
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT                                                              0x0
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK                                                                0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK2
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT                                                              0x0
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK                                                                0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK3
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT                                                              0x0
+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT                                                              0x8
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT                                                          0x10
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT                                                          0x18
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK                                                                0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK                                                                0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK                                                            0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK                                                            0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK3
+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT                                                              0x0
+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK                                                                0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK3
+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT                                                              0x0
+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK                                                                0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK4
+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT                                                              0x0
+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT                                                              0x8
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT                                                          0x10
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT                                                          0x18
+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK                                                                0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK                                                                0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK                                                            0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK                                                            0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK4
+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT                                                              0x0
+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK                                                                0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK4
+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT                                                              0x0
+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK                                                                0xFFFFFFFFL
+//PCIE_PERF_CNTL_SCLK1
+#define PCIE_PERF_CNTL_SCLK1__EVENT0_SEL__SHIFT                                                               0x0
+#define PCIE_PERF_CNTL_SCLK1__EVENT1_SEL__SHIFT                                                               0x8
+#define PCIE_PERF_CNTL_SCLK1__COUNTER0_UPPER__SHIFT                                                           0x10
+#define PCIE_PERF_CNTL_SCLK1__COUNTER1_UPPER__SHIFT                                                           0x18
+#define PCIE_PERF_CNTL_SCLK1__EVENT0_SEL_MASK                                                                 0x000000FFL
+#define PCIE_PERF_CNTL_SCLK1__EVENT1_SEL_MASK                                                                 0x0000FF00L
+#define PCIE_PERF_CNTL_SCLK1__COUNTER0_UPPER_MASK                                                             0x00FF0000L
+#define PCIE_PERF_CNTL_SCLK1__COUNTER1_UPPER_MASK                                                             0xFF000000L
+//PCIE_PERF_COUNT0_SCLK1
+#define PCIE_PERF_COUNT0_SCLK1__COUNTER0__SHIFT                                                               0x0
+#define PCIE_PERF_COUNT0_SCLK1__COUNTER0_MASK                                                                 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SCLK1
+#define PCIE_PERF_COUNT1_SCLK1__COUNTER1__SHIFT                                                               0x0
+#define PCIE_PERF_COUNT1_SCLK1__COUNTER1_MASK                                                                 0xFFFFFFFFL
+//PCIE_PERF_CNTL_SCLK2
+#define PCIE_PERF_CNTL_SCLK2__EVENT0_SEL__SHIFT                                                               0x0
+#define PCIE_PERF_CNTL_SCLK2__EVENT1_SEL__SHIFT                                                               0x8
+#define PCIE_PERF_CNTL_SCLK2__COUNTER0_UPPER__SHIFT                                                           0x10
+#define PCIE_PERF_CNTL_SCLK2__COUNTER1_UPPER__SHIFT                                                           0x18
+#define PCIE_PERF_CNTL_SCLK2__EVENT0_SEL_MASK                                                                 0x000000FFL
+#define PCIE_PERF_CNTL_SCLK2__EVENT1_SEL_MASK                                                                 0x0000FF00L
+#define PCIE_PERF_CNTL_SCLK2__COUNTER0_UPPER_MASK                                                             0x00FF0000L
+#define PCIE_PERF_CNTL_SCLK2__COUNTER1_UPPER_MASK                                                             0xFF000000L
+//PCIE_PERF_COUNT0_SCLK2
+#define PCIE_PERF_COUNT0_SCLK2__COUNTER0__SHIFT                                                               0x0
+#define PCIE_PERF_COUNT0_SCLK2__COUNTER0_MASK                                                                 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SCLK2
+#define PCIE_PERF_COUNT1_SCLK2__COUNTER1__SHIFT                                                               0x0
+#define PCIE_PERF_COUNT1_SCLK2__COUNTER1_MASK                                                                 0xFFFFFFFFL
+//PCIE_PERF_CNTL_EVENT_LC_PORT_SEL
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1__SHIFT                                        0x0
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1__SHIFT                                        0x4
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT                                        0x8
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT                                        0xc
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1_MASK                                          0x0000000FL
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1_MASK                                          0x000000F0L
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK                                          0x00000F00L
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK                                          0x0000F000L
+//PCIE_PERF_CNTL_EVENT_CI_PORT_SEL
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3__SHIFT                                        0x0
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3__SHIFT                                        0x4
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4__SHIFT                                        0x8
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4__SHIFT                                        0xc
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK1__SHIFT                                         0x10
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK1__SHIFT                                         0x14
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK2__SHIFT                                         0x18
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK2__SHIFT                                         0x1c
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3_MASK                                          0x0000000FL
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3_MASK                                          0x000000F0L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4_MASK                                          0x00000F00L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4_MASK                                          0x0000F000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK1_MASK                                           0x000F0000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK1_MASK                                           0x00F00000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK2_MASK                                           0x0F000000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK2_MASK                                           0xF0000000L
+//PCIE_STRAP_F0
+#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT                                                                     0x0
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT                                                  0x1
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT                                                                 0x2
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT                                                                  0x3
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT                                                                 0x4
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT                                                                 0x5
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT                                                                 0x6
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT                                                                 0x7
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT                                                                 0x8
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT                                                                 0x9
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT                                                                 0xa
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT                                                            0xb
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT                                                               0xc
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT                                                          0xd
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT                                                       0xf
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT                                             0x10
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT                                                                  0x11
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT                                                              0x12
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT                                                        0x13
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT                                                      0x14
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT                                                          0x15
+#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT                                                      0x18
+#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT                                                 0x1b
+#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT                                              0x1c
+#define PCIE_STRAP_F0__STRAP_SWUS_ARI_EN__SHIFT                                                               0x1d
+#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT                                                               0x1e
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN__SHIFT                                                             0x1f
+#define PCIE_STRAP_F0__STRAP_F0_EN_MASK                                                                       0x00000001L
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK                                                    0x00000002L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK                                                                   0x00000004L
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK                                                                    0x00000008L
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK                                                                   0x00000010L
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK                                                                   0x00000020L
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK                                                                   0x00000040L
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK                                                                   0x00000080L
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK                                                                   0x00000100L
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK                                                                   0x00000200L
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK                                                                   0x00000400L
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK                                                              0x00000800L
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK                                                                 0x00001000L
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK                                                            0x00002000L
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK                                                         0x00008000L
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK                                               0x00010000L
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK                                                                    0x00020000L
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK                                                                0x00040000L
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK                                                          0x00080000L
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK                                                        0x00100000L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK                                                            0x00E00000L
+#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK                                                        0x07000000L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK                                                   0x08000000L
+#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK                                                0x10000000L
+#define PCIE_STRAP_F0__STRAP_SWUS_ARI_EN_MASK                                                                 0x20000000L
+#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK                                                                 0x40000000L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN_MASK                                                               0x80000000L
+//PCIE_STRAP_NTB
+#define PCIE_STRAP_NTB__STRAP_NTB_MSI_EN__SHIFT                                                               0x2
+#define PCIE_STRAP_NTB__STRAP_NTB_VC_EN__SHIFT                                                                0x3
+#define PCIE_STRAP_NTB__STRAP_NTB_DSN_EN__SHIFT                                                               0x4
+#define PCIE_STRAP_NTB__STRAP_NTB_AER_EN__SHIFT                                                               0x5
+#define PCIE_STRAP_NTB__STRAP_NTB_ECRC_CHECK_EN__SHIFT                                                        0xd
+#define PCIE_STRAP_NTB__STRAP_NTB_CPL_ABORT_ERR_EN__SHIFT                                                     0xf
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_EN__SHIFT                                                            0x12
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_64BIT_EN__SHIFT                                                      0x13
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_ROUTING_EN__SHIFT                                                    0x14
+#define PCIE_STRAP_NTB__STRAP_NTB_LTR_SUPPORTED__SHIFT                                                        0x15
+#define PCIE_STRAP_NTB__STRAP_NTB_OBFF_SUPPORTED__SHIFT                                                       0x16
+#define PCIE_STRAP_NTB__STRAP_NTB_MSI_EN_MASK                                                                 0x00000004L
+#define PCIE_STRAP_NTB__STRAP_NTB_VC_EN_MASK                                                                  0x00000008L
+#define PCIE_STRAP_NTB__STRAP_NTB_DSN_EN_MASK                                                                 0x00000010L
+#define PCIE_STRAP_NTB__STRAP_NTB_AER_EN_MASK                                                                 0x00000020L
+#define PCIE_STRAP_NTB__STRAP_NTB_ECRC_CHECK_EN_MASK                                                          0x00002000L
+#define PCIE_STRAP_NTB__STRAP_NTB_CPL_ABORT_ERR_EN_MASK                                                       0x00008000L
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_EN_MASK                                                              0x00040000L
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_64BIT_EN_MASK                                                        0x00080000L
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_ROUTING_EN_MASK                                                      0x00100000L
+#define PCIE_STRAP_NTB__STRAP_NTB_LTR_SUPPORTED_MASK                                                          0x00200000L
+#define PCIE_STRAP_NTB__STRAP_NTB_OBFF_SUPPORTED_MASK                                                         0x00C00000L
+//PCIE_STRAP_MISC
+#define PCIE_STRAP_MISC__STRAP_DLF_EN__SHIFT                                                                  0x0
+#define PCIE_STRAP_MISC__STRAP_16GT_EN__SHIFT                                                                 0x1
+#define PCIE_STRAP_MISC__STRAP_MARGINING_EN__SHIFT                                                            0x2
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT                                                           0x4
+#define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER__SHIFT                                                        0x6
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT                                                               0x18
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT                                                            0x1a
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT                                                             0x1c
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                                            0x1d
+#define PCIE_STRAP_MISC__STRAP_DLF_EN_MASK                                                                    0x00000001L
+#define PCIE_STRAP_MISC__STRAP_16GT_EN_MASK                                                                   0x00000002L
+#define PCIE_STRAP_MISC__STRAP_MARGINING_EN_MASK                                                              0x00000004L
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK                                                             0x00000010L
+#define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER_MASK                                                          0x00000040L
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK                                                                 0x01000000L
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK                                                              0x04000000L
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK                                                               0x10000000L
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                                              0x20000000L
+//PCIE_STRAP_MISC2
+#define PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT                                            0x0
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT                                                        0x1
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT                                                      0x2
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT                                                        0x3
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT                                                          0x4
+#define PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE__SHIFT                                                        0x5
+#define PCIE_STRAP_MISC2__STRAP_F0_CTO_LOG_CAPABLE__SHIFT                                                     0x6
+#define PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK                                              0x00000001L
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK                                                          0x00000002L
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK                                                        0x00000004L
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK                                                          0x00000008L
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK                                                            0x00000010L
+#define PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE_MASK                                                          0x00000020L
+#define PCIE_STRAP_MISC2__STRAP_F0_CTO_LOG_CAPABLE_MASK                                                       0x00000040L
+//PCIE_STRAP_PI
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT                                                            0x0
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT                                                       0x1c
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT                                                          0x1d
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK                                                              0x00000001L
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK                                                         0x10000000L
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK                                                            0x20000000L
+//PCIE_STRAP_I2C_BD
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT                                                       0x0
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK                                                         0x0000007FL
+//PCIE_PRBS_CLR
+#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT                                                                        0x0
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT                                                                0x18
+#define PCIE_PRBS_CLR__PRBS_CLR_MASK                                                                          0x0000FFFFL
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK                                                                  0x01000000L
+//PCIE_PRBS_STATUS1
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT                                                                0x0
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT                                                                 0x10
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK                                                                  0x0000FFFFL
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK                                                                   0xFFFF0000L
+//PCIE_PRBS_STATUS2
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT                                                            0x0
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK                                                              0x0000FFFFL
+//PCIE_PRBS_FREERUN
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT                                                                0x0
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK                                                                  0x0000FFFFL
+//PCIE_PRBS_MISC
+#define PCIE_PRBS_MISC__PRBS_EN__SHIFT                                                                        0x0
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT                                                                 0x1
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT                                                       0x4
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT                                                                  0x5
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT                                                                 0x6
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT                                                                  0x8
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT                                                                 0xe
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT                                                              0x10
+#define PCIE_PRBS_MISC__PRBS_EN_MASK                                                                          0x00000001L
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK                                                                   0x0000000EL
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK                                                         0x00000010L
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK                                                                    0x00000020L
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK                                                                   0x000000C0L
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK                                                                    0x00001F00L
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK                                                                   0x0000C000L
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK                                                                0xFFFF0000L
+//PCIE_PRBS_USER_PATTERN
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT                                                      0x0
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK                                                        0x3FFFFFFFL
+//PCIE_PRBS_LO_BITCNT
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT                                                            0x0
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK                                                              0xFFFFFFFFL
+//PCIE_PRBS_HI_BITCNT
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT                                                            0x0
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK                                                              0x000000FFL
+//PCIE_PRBS_ERRCNT_0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT                                                              0x0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK                                                                0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_1
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT                                                              0x0
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK                                                                0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_2
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT                                                              0x0
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK                                                                0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_3
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT                                                              0x0
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK                                                                0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_4
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT                                                              0x0
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK                                                                0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_5
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT                                                              0x0
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK                                                                0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_6
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT                                                              0x0
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK                                                                0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_7
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT                                                              0x0
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK                                                                0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_8
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT                                                              0x0
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK                                                                0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_9
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT                                                              0x0
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK                                                                0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_10
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT                                                            0x0
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK                                                              0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_11
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT                                                            0x0
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK                                                              0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_12
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT                                                            0x0
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK                                                              0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_13
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT                                                            0x0
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK                                                              0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_14
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT                                                            0x0
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK                                                              0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_15
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT                                                            0x0
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK                                                              0xFFFFFFFFL
+//SWRST_COMMAND_STATUS
+#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT                                                              0x0
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT                                                             0x1
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT                                                           0x10
+#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT                                                               0x11
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT                                                          0x18
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT                                                 0x19
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT                                                0x1a
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT                                                          0x1b
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT                                                 0x1c
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT                                                0x1d
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT                                             0x1e
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT                                                0x1f
+#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK                                                                0x00000001L
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK                                                               0x00000002L
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK                                                             0x00010000L
+#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK                                                                 0x00020000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK                                                            0x01000000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK                                                   0x02000000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK                                                  0x04000000L
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK                                                            0x08000000L
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK                                                   0x10000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK                                                  0x20000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK                                               0x40000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK                                                  0x80000000L
+//SWRST_GENERAL_CONTROL
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT                                                          0x0
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT                                                         0x1
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT                                                            0x2
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT                                                             0x8
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT                                                           0x9
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT                                                           0xa
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT                                                        0xc
+#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD__SHIFT                                                         0x11
+#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT                                          0x18
+#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT                                                        0x19
+#define SWRST_GENERAL_CONTROL__WAIT_FOR_SDP_CREDITS__SHIFT                                                    0x1a
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK                                                            0x00000001L
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK                                                           0x00000002L
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK                                                              0x0000001CL
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK                                                               0x00000100L
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK                                                             0x00000200L
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK                                                             0x00000400L
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK                                                          0x00001000L
+#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD_MASK                                                           0x00020000L
+#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK                                            0x01000000L
+#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK                                                          0x02000000L
+#define SWRST_GENERAL_CONTROL__WAIT_FOR_SDP_CREDITS_MASK                                                      0x04000000L
+//SWRST_COMMAND_0
+#define SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT                                                               0x0
+#define SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT                                                               0x8
+#define SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT                                                               0x9
+#define SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT                                                               0xa
+#define SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT                                                               0xb
+#define SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT                                                               0xc
+#define SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT                                                               0xd
+#define SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT                                                               0xe
+#define SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT                                                               0xf
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT                                                             0x18
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT                                                              0x19
+#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT                                                               0x1a
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT                                                           0x1b
+#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT                                                                0x1c
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT                                                             0x1d
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT                                                             0x1e
+#define SWRST_COMMAND_0__BIF0_SDP_CREDIT_RESET__SHIFT                                                         0x1f
+#define SWRST_COMMAND_0__PORT0_COR_RESET_MASK                                                                 0x00000001L
+#define SWRST_COMMAND_0__PORT0_CFG_RESET_MASK                                                                 0x00000100L
+#define SWRST_COMMAND_0__PORT1_CFG_RESET_MASK                                                                 0x00000200L
+#define SWRST_COMMAND_0__PORT2_CFG_RESET_MASK                                                                 0x00000400L
+#define SWRST_COMMAND_0__PORT3_CFG_RESET_MASK                                                                 0x00000800L
+#define SWRST_COMMAND_0__PORT4_CFG_RESET_MASK                                                                 0x00001000L
+#define SWRST_COMMAND_0__PORT5_CFG_RESET_MASK                                                                 0x00002000L
+#define SWRST_COMMAND_0__PORT6_CFG_RESET_MASK                                                                 0x00004000L
+#define SWRST_COMMAND_0__PORT7_CFG_RESET_MASK                                                                 0x00008000L
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK                                                               0x01000000L
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK                                                                0x02000000L
+#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK                                                                 0x04000000L
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK                                                             0x08000000L
+#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK                                                                  0x10000000L
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK                                                               0x20000000L
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK                                                               0x40000000L
+#define SWRST_COMMAND_0__BIF0_SDP_CREDIT_RESET_MASK                                                           0x80000000L
+//SWRST_COMMAND_1
+#define SWRST_COMMAND_1__RESETPCS0__SHIFT                                                                     0x0
+#define SWRST_COMMAND_1__RESETPCS1__SHIFT                                                                     0x1
+#define SWRST_COMMAND_1__RESETPCS2__SHIFT                                                                     0x2
+#define SWRST_COMMAND_1__RESETPCS3__SHIFT                                                                     0x3
+#define SWRST_COMMAND_1__RESETPCS4__SHIFT                                                                     0x4
+#define SWRST_COMMAND_1__RESETPCS5__SHIFT                                                                     0x5
+#define SWRST_COMMAND_1__RESETPCS6__SHIFT                                                                     0x6
+#define SWRST_COMMAND_1__RESETPCS7__SHIFT                                                                     0x7
+#define SWRST_COMMAND_1__RESETPCS8__SHIFT                                                                     0x8
+#define SWRST_COMMAND_1__RESETPCS9__SHIFT                                                                     0x9
+#define SWRST_COMMAND_1__RESETPCS10__SHIFT                                                                    0xa
+#define SWRST_COMMAND_1__RESETPCS11__SHIFT                                                                    0xb
+#define SWRST_COMMAND_1__RESETPCS12__SHIFT                                                                    0xc
+#define SWRST_COMMAND_1__RESETPCS13__SHIFT                                                                    0xd
+#define SWRST_COMMAND_1__RESETPCS14__SHIFT                                                                    0xe
+#define SWRST_COMMAND_1__RESETPCS15__SHIFT                                                                    0xf
+#define SWRST_COMMAND_1__SWITCHCLK__SHIFT                                                                     0x15
+#define SWRST_COMMAND_1__RESETPCFG__SHIFT                                                                     0x19
+#define SWRST_COMMAND_1__RESETLNCT__SHIFT                                                                     0x1a
+#define SWRST_COMMAND_1__RESETMNTR__SHIFT                                                                     0x1b
+#define SWRST_COMMAND_1__RESETHLTR__SHIFT                                                                     0x1c
+#define SWRST_COMMAND_1__RESETCPM__SHIFT                                                                      0x1d
+#define SWRST_COMMAND_1__RESETPHY0__SHIFT                                                                     0x1e
+#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT                                                                   0x1f
+#define SWRST_COMMAND_1__RESETPCS0_MASK                                                                       0x00000001L
+#define SWRST_COMMAND_1__RESETPCS1_MASK                                                                       0x00000002L
+#define SWRST_COMMAND_1__RESETPCS2_MASK                                                                       0x00000004L
+#define SWRST_COMMAND_1__RESETPCS3_MASK                                                                       0x00000008L
+#define SWRST_COMMAND_1__RESETPCS4_MASK                                                                       0x00000010L
+#define SWRST_COMMAND_1__RESETPCS5_MASK                                                                       0x00000020L
+#define SWRST_COMMAND_1__RESETPCS6_MASK                                                                       0x00000040L
+#define SWRST_COMMAND_1__RESETPCS7_MASK                                                                       0x00000080L
+#define SWRST_COMMAND_1__RESETPCS8_MASK                                                                       0x00000100L
+#define SWRST_COMMAND_1__RESETPCS9_MASK                                                                       0x00000200L
+#define SWRST_COMMAND_1__RESETPCS10_MASK                                                                      0x00000400L
+#define SWRST_COMMAND_1__RESETPCS11_MASK                                                                      0x00000800L
+#define SWRST_COMMAND_1__RESETPCS12_MASK                                                                      0x00001000L
+#define SWRST_COMMAND_1__RESETPCS13_MASK                                                                      0x00002000L
+#define SWRST_COMMAND_1__RESETPCS14_MASK                                                                      0x00004000L
+#define SWRST_COMMAND_1__RESETPCS15_MASK                                                                      0x00008000L
+#define SWRST_COMMAND_1__SWITCHCLK_MASK                                                                       0x00200000L
+#define SWRST_COMMAND_1__RESETPCFG_MASK                                                                       0x02000000L
+#define SWRST_COMMAND_1__RESETLNCT_MASK                                                                       0x04000000L
+#define SWRST_COMMAND_1__RESETMNTR_MASK                                                                       0x08000000L
+#define SWRST_COMMAND_1__RESETHLTR_MASK                                                                       0x10000000L
+#define SWRST_COMMAND_1__RESETCPM_MASK                                                                        0x20000000L
+#define SWRST_COMMAND_1__RESETPHY0_MASK                                                                       0x40000000L
+#define SWRST_COMMAND_1__TOGGLESTRAP_MASK                                                                     0x80000000L
+//SWRST_CONTROL_0
+#define SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT                                                                0x0
+#define SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT                                                                0x8
+#define SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT                                                                0x9
+#define SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT                                                                0xa
+#define SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT                                                                0xb
+#define SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT                                                                0xc
+#define SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT                                                                0xd
+#define SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT                                                                0xe
+#define SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT                                                                0xf
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT                                                         0x18
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT                                                          0x19
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT                                                           0x1a
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT                                                       0x1b
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT                                                            0x1c
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT                                                         0x1d
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT                                                         0x1e
+#define SWRST_CONTROL_0__BIF0_SDP_CREDIT_RESETRCEN__SHIFT                                                     0x1f
+#define SWRST_CONTROL_0__PORT0_COR_RCEN_MASK                                                                  0x00000001L
+#define SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK                                                                  0x00000100L
+#define SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK                                                                  0x00000200L
+#define SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK                                                                  0x00000400L
+#define SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK                                                                  0x00000800L
+#define SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK                                                                  0x00001000L
+#define SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK                                                                  0x00002000L
+#define SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK                                                                  0x00004000L
+#define SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK                                                                  0x00008000L
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK                                                           0x01000000L
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK                                                            0x02000000L
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK                                                             0x04000000L
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK                                                         0x08000000L
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK                                                              0x10000000L
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK                                                           0x20000000L
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK                                                           0x40000000L
+#define SWRST_CONTROL_0__BIF0_SDP_CREDIT_RESETRCEN_MASK                                                       0x80000000L
+//SWRST_CONTROL_1
+#define SWRST_CONTROL_1__PCSRESET0_RCEN__SHIFT                                                                0x0
+#define SWRST_CONTROL_1__PCSRESET1_RCEN__SHIFT                                                                0x1
+#define SWRST_CONTROL_1__PCSRESET2_RCEN__SHIFT                                                                0x2
+#define SWRST_CONTROL_1__PCSRESET3_RCEN__SHIFT                                                                0x3
+#define SWRST_CONTROL_1__PCSRESET4_RCEN__SHIFT                                                                0x4
+#define SWRST_CONTROL_1__PCSRESET5_RCEN__SHIFT                                                                0x5
+#define SWRST_CONTROL_1__PCSRESET6_RCEN__SHIFT                                                                0x6
+#define SWRST_CONTROL_1__PCSRESET7_RCEN__SHIFT                                                                0x7
+#define SWRST_CONTROL_1__PCSRESET8_RCEN__SHIFT                                                                0x8
+#define SWRST_CONTROL_1__PCSRESET9_RCEN__SHIFT                                                                0x9
+#define SWRST_CONTROL_1__PCSRESET10_RCEN__SHIFT                                                               0xa
+#define SWRST_CONTROL_1__PCSRESET11_RCEN__SHIFT                                                               0xb
+#define SWRST_CONTROL_1__PCSRESET12_RCEN__SHIFT                                                               0xc
+#define SWRST_CONTROL_1__PCSRESET13_RCEN__SHIFT                                                               0xd
+#define SWRST_CONTROL_1__PCSRESET14_RCEN__SHIFT                                                               0xe
+#define SWRST_CONTROL_1__PCSRESET15_RCEN__SHIFT                                                               0xf
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT                                                                0x15
+#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT                                                                0x19
+#define SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT                                                                0x1a
+#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT                                                                0x1b
+#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT                                                                0x1c
+#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT                                                                 0x1d
+#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT                                                                0x1e
+#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT                                                                 0x1f
+#define SWRST_CONTROL_1__PCSRESET0_RCEN_MASK                                                                  0x00000001L
+#define SWRST_CONTROL_1__PCSRESET1_RCEN_MASK                                                                  0x00000002L
+#define SWRST_CONTROL_1__PCSRESET2_RCEN_MASK                                                                  0x00000004L
+#define SWRST_CONTROL_1__PCSRESET3_RCEN_MASK                                                                  0x00000008L
+#define SWRST_CONTROL_1__PCSRESET4_RCEN_MASK                                                                  0x00000010L
+#define SWRST_CONTROL_1__PCSRESET5_RCEN_MASK                                                                  0x00000020L
+#define SWRST_CONTROL_1__PCSRESET6_RCEN_MASK                                                                  0x00000040L
+#define SWRST_CONTROL_1__PCSRESET7_RCEN_MASK                                                                  0x00000080L
+#define SWRST_CONTROL_1__PCSRESET8_RCEN_MASK                                                                  0x00000100L
+#define SWRST_CONTROL_1__PCSRESET9_RCEN_MASK                                                                  0x00000200L
+#define SWRST_CONTROL_1__PCSRESET10_RCEN_MASK                                                                 0x00000400L
+#define SWRST_CONTROL_1__PCSRESET11_RCEN_MASK                                                                 0x00000800L
+#define SWRST_CONTROL_1__PCSRESET12_RCEN_MASK                                                                 0x00001000L
+#define SWRST_CONTROL_1__PCSRESET13_RCEN_MASK                                                                 0x00002000L
+#define SWRST_CONTROL_1__PCSRESET14_RCEN_MASK                                                                 0x00004000L
+#define SWRST_CONTROL_1__PCSRESET15_RCEN_MASK                                                                 0x00008000L
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK                                                                  0x00200000L
+#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK                                                                  0x02000000L
+#define SWRST_CONTROL_1__RESETLNCT_RCEN_MASK                                                                  0x04000000L
+#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK                                                                  0x08000000L
+#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK                                                                  0x10000000L
+#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK                                                                   0x20000000L
+#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK                                                                  0x40000000L
+#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK                                                                   0x80000000L
+//SWRST_CONTROL_2
+#define SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT                                                                0x0
+#define SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT                                                                0x8
+#define SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT                                                                0x9
+#define SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT                                                                0xa
+#define SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT                                                                0xb
+#define SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT                                                                0xc
+#define SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT                                                                0xd
+#define SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT                                                                0xe
+#define SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT                                                                0xf
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT                                                         0x18
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT                                                          0x19
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT                                                           0x1a
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT                                                       0x1b
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT                                                            0x1c
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT                                                         0x1d
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT                                                         0x1e
+#define SWRST_CONTROL_2__BIF0_SDP_CREDIT_RESETATEN__SHIFT                                                     0x1f
+#define SWRST_CONTROL_2__PORT0_COR_ATEN_MASK                                                                  0x00000001L
+#define SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK                                                                  0x00000100L
+#define SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK                                                                  0x00000200L
+#define SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK                                                                  0x00000400L
+#define SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK                                                                  0x00000800L
+#define SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK                                                                  0x00001000L
+#define SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK                                                                  0x00002000L
+#define SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK                                                                  0x00004000L
+#define SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK                                                                  0x00008000L
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK                                                           0x01000000L
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK                                                            0x02000000L
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK                                                             0x04000000L
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK                                                         0x08000000L
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK                                                              0x10000000L
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK                                                           0x20000000L
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK                                                           0x40000000L
+#define SWRST_CONTROL_2__BIF0_SDP_CREDIT_RESETATEN_MASK                                                       0x80000000L
+//SWRST_CONTROL_3
+#define SWRST_CONTROL_3__PCSRESET0_ATEN__SHIFT                                                                0x0
+#define SWRST_CONTROL_3__PCSRESET1_ATEN__SHIFT                                                                0x1
+#define SWRST_CONTROL_3__PCSRESET2_ATEN__SHIFT                                                                0x2
+#define SWRST_CONTROL_3__PCSRESET3_ATEN__SHIFT                                                                0x3
+#define SWRST_CONTROL_3__PCSRESET4_ATEN__SHIFT                                                                0x4
+#define SWRST_CONTROL_3__PCSRESET5_ATEN__SHIFT                                                                0x5
+#define SWRST_CONTROL_3__PCSRESET6_ATEN__SHIFT                                                                0x6
+#define SWRST_CONTROL_3__PCSRESET7_ATEN__SHIFT                                                                0x7
+#define SWRST_CONTROL_3__PCSRESET8_ATEN__SHIFT                                                                0x8
+#define SWRST_CONTROL_3__PCSRESET9_ATEN__SHIFT                                                                0x9
+#define SWRST_CONTROL_3__PCSRESET10_ATEN__SHIFT                                                               0xa
+#define SWRST_CONTROL_3__PCSRESET11_ATEN__SHIFT                                                               0xb
+#define SWRST_CONTROL_3__PCSRESET12_ATEN__SHIFT                                                               0xc
+#define SWRST_CONTROL_3__PCSRESET13_ATEN__SHIFT                                                               0xd
+#define SWRST_CONTROL_3__PCSRESET14_ATEN__SHIFT                                                               0xe
+#define SWRST_CONTROL_3__PCSRESET15_ATEN__SHIFT                                                               0xf
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT                                                                0x15
+#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT                                                                0x19
+#define SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT                                                                0x1a
+#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT                                                                0x1b
+#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT                                                                0x1c
+#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT                                                                 0x1d
+#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT                                                                0x1e
+#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT                                                                 0x1f
+#define SWRST_CONTROL_3__PCSRESET0_ATEN_MASK                                                                  0x00000001L
+#define SWRST_CONTROL_3__PCSRESET1_ATEN_MASK                                                                  0x00000002L
+#define SWRST_CONTROL_3__PCSRESET2_ATEN_MASK                                                                  0x00000004L
+#define SWRST_CONTROL_3__PCSRESET3_ATEN_MASK                                                                  0x00000008L
+#define SWRST_CONTROL_3__PCSRESET4_ATEN_MASK                                                                  0x00000010L
+#define SWRST_CONTROL_3__PCSRESET5_ATEN_MASK                                                                  0x00000020L
+#define SWRST_CONTROL_3__PCSRESET6_ATEN_MASK                                                                  0x00000040L
+#define SWRST_CONTROL_3__PCSRESET7_ATEN_MASK                                                                  0x00000080L
+#define SWRST_CONTROL_3__PCSRESET8_ATEN_MASK                                                                  0x00000100L
+#define SWRST_CONTROL_3__PCSRESET9_ATEN_MASK                                                                  0x00000200L
+#define SWRST_CONTROL_3__PCSRESET10_ATEN_MASK                                                                 0x00000400L
+#define SWRST_CONTROL_3__PCSRESET11_ATEN_MASK                                                                 0x00000800L
+#define SWRST_CONTROL_3__PCSRESET12_ATEN_MASK                                                                 0x00001000L
+#define SWRST_CONTROL_3__PCSRESET13_ATEN_MASK                                                                 0x00002000L
+#define SWRST_CONTROL_3__PCSRESET14_ATEN_MASK                                                                 0x00004000L
+#define SWRST_CONTROL_3__PCSRESET15_ATEN_MASK                                                                 0x00008000L
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK                                                                  0x00200000L
+#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK                                                                  0x02000000L
+#define SWRST_CONTROL_3__RESETLNCT_ATEN_MASK                                                                  0x04000000L
+#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK                                                                  0x08000000L
+#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK                                                                  0x10000000L
+#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK                                                                   0x20000000L
+#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK                                                                  0x40000000L
+#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK                                                                   0x80000000L
+//SWRST_CONTROL_4
+#define SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT                                                                0x0
+#define SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT                                                                0x8
+#define SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT                                                                0x9
+#define SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT                                                                0xa
+#define SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT                                                                0xb
+#define SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT                                                                0xc
+#define SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT                                                                0xd
+#define SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT                                                                0xe
+#define SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT                                                                0xf
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT                                                         0x18
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT                                                          0x19
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT                                                           0x1a
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT                                                       0x1b
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT                                                            0x1c
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT                                                         0x1d
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT                                                         0x1e
+#define SWRST_CONTROL_4__BIF0_SDP_CREDIT_WRRESETEN__SHIFT                                                     0x1f
+#define SWRST_CONTROL_4__PORT0_COR_WREN_MASK                                                                  0x00000001L
+#define SWRST_CONTROL_4__PORT0_CFG_WREN_MASK                                                                  0x00000100L
+#define SWRST_CONTROL_4__PORT1_CFG_WREN_MASK                                                                  0x00000200L
+#define SWRST_CONTROL_4__PORT2_CFG_WREN_MASK                                                                  0x00000400L
+#define SWRST_CONTROL_4__PORT3_CFG_WREN_MASK                                                                  0x00000800L
+#define SWRST_CONTROL_4__PORT4_CFG_WREN_MASK                                                                  0x00001000L
+#define SWRST_CONTROL_4__PORT5_CFG_WREN_MASK                                                                  0x00002000L
+#define SWRST_CONTROL_4__PORT6_CFG_WREN_MASK                                                                  0x00004000L
+#define SWRST_CONTROL_4__PORT7_CFG_WREN_MASK                                                                  0x00008000L
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK                                                           0x01000000L
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK                                                            0x02000000L
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK                                                             0x04000000L
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK                                                         0x08000000L
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK                                                              0x10000000L
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK                                                           0x20000000L
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK                                                           0x40000000L
+#define SWRST_CONTROL_4__BIF0_SDP_CREDIT_WRRESETEN_MASK                                                       0x80000000L
+//SWRST_CONTROL_5
+#define SWRST_CONTROL_5__PCSRESET0_WREN__SHIFT                                                                0x0
+#define SWRST_CONTROL_5__PCSRESET1_WREN__SHIFT                                                                0x1
+#define SWRST_CONTROL_5__PCSRESET2_WREN__SHIFT                                                                0x2
+#define SWRST_CONTROL_5__PCSRESET3_WREN__SHIFT                                                                0x3
+#define SWRST_CONTROL_5__PCSRESET4_WREN__SHIFT                                                                0x4
+#define SWRST_CONTROL_5__PCSRESET5_WREN__SHIFT                                                                0x5
+#define SWRST_CONTROL_5__PCSRESET6_WREN__SHIFT                                                                0x6
+#define SWRST_CONTROL_5__PCSRESET7_WREN__SHIFT                                                                0x7
+#define SWRST_CONTROL_5__PCSRESET8_WREN__SHIFT                                                                0x8
+#define SWRST_CONTROL_5__PCSRESET9_WREN__SHIFT                                                                0x9
+#define SWRST_CONTROL_5__PCSRESET10_WREN__SHIFT                                                               0xa
+#define SWRST_CONTROL_5__PCSRESET11_WREN__SHIFT                                                               0xb
+#define SWRST_CONTROL_5__PCSRESET12_WREN__SHIFT                                                               0xc
+#define SWRST_CONTROL_5__PCSRESET13_WREN__SHIFT                                                               0xd
+#define SWRST_CONTROL_5__PCSRESET14_WREN__SHIFT                                                               0xe
+#define SWRST_CONTROL_5__PCSRESET15_WREN__SHIFT                                                               0xf
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT                                                                0x15
+#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT                                                                0x19
+#define SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT                                                                0x1a
+#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT                                                                0x1b
+#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT                                                                0x1c
+#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT                                                                 0x1d
+#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT                                                                0x1e
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT                                                                 0x1f
+#define SWRST_CONTROL_5__PCSRESET0_WREN_MASK                                                                  0x00000001L
+#define SWRST_CONTROL_5__PCSRESET1_WREN_MASK                                                                  0x00000002L
+#define SWRST_CONTROL_5__PCSRESET2_WREN_MASK                                                                  0x00000004L
+#define SWRST_CONTROL_5__PCSRESET3_WREN_MASK                                                                  0x00000008L
+#define SWRST_CONTROL_5__PCSRESET4_WREN_MASK                                                                  0x00000010L
+#define SWRST_CONTROL_5__PCSRESET5_WREN_MASK                                                                  0x00000020L
+#define SWRST_CONTROL_5__PCSRESET6_WREN_MASK                                                                  0x00000040L
+#define SWRST_CONTROL_5__PCSRESET7_WREN_MASK                                                                  0x00000080L
+#define SWRST_CONTROL_5__PCSRESET8_WREN_MASK                                                                  0x00000100L
+#define SWRST_CONTROL_5__PCSRESET9_WREN_MASK                                                                  0x00000200L
+#define SWRST_CONTROL_5__PCSRESET10_WREN_MASK                                                                 0x00000400L
+#define SWRST_CONTROL_5__PCSRESET11_WREN_MASK                                                                 0x00000800L
+#define SWRST_CONTROL_5__PCSRESET12_WREN_MASK                                                                 0x00001000L
+#define SWRST_CONTROL_5__PCSRESET13_WREN_MASK                                                                 0x00002000L
+#define SWRST_CONTROL_5__PCSRESET14_WREN_MASK                                                                 0x00004000L
+#define SWRST_CONTROL_5__PCSRESET15_WREN_MASK                                                                 0x00008000L
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK                                                                  0x00200000L
+#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK                                                                  0x02000000L
+#define SWRST_CONTROL_5__WRRESETLNCT_EN_MASK                                                                  0x04000000L
+#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK                                                                  0x08000000L
+#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK                                                                  0x10000000L
+#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK                                                                   0x20000000L
+#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK                                                                  0x40000000L
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK                                                                   0x80000000L
+//SWRST_CONTROL_6
+#define SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT                                                               0x0
+#define SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT                                                               0x1
+#define SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT                                                               0x2
+#define SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT                                                               0x3
+#define SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT                                                               0x4
+#define SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT                                                               0x5
+#define SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT                                                               0x6
+#define SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT                                                               0x7
+#define SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT                                                               0x8
+#define SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT                                                               0x9
+#define SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT                                                               0xa
+#define SWRST_CONTROL_6__HOLD_TRAINING_A_MASK                                                                 0x00000001L
+#define SWRST_CONTROL_6__HOLD_TRAINING_B_MASK                                                                 0x00000002L
+#define SWRST_CONTROL_6__HOLD_TRAINING_C_MASK                                                                 0x00000004L
+#define SWRST_CONTROL_6__HOLD_TRAINING_D_MASK                                                                 0x00000008L
+#define SWRST_CONTROL_6__HOLD_TRAINING_E_MASK                                                                 0x00000010L
+#define SWRST_CONTROL_6__HOLD_TRAINING_F_MASK                                                                 0x00000020L
+#define SWRST_CONTROL_6__HOLD_TRAINING_G_MASK                                                                 0x00000040L
+#define SWRST_CONTROL_6__HOLD_TRAINING_H_MASK                                                                 0x00000080L
+#define SWRST_CONTROL_6__HOLD_TRAINING_I_MASK                                                                 0x00000100L
+#define SWRST_CONTROL_6__HOLD_TRAINING_J_MASK                                                                 0x00000200L
+#define SWRST_CONTROL_6__HOLD_TRAINING_K_MASK                                                                 0x00000400L
+//SWRST_EP_COMMAND_0
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT                                                          0x0
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT                                                               0x8
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT                                                            0x9
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT                                                            0xa
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK                                                            0x00000001L
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK                                                                 0x00000100L
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK                                                              0x00000200L
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK                                                              0x00000400L
+//SWRST_EP_CONTROL_0
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT                                                       0x0
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT                                                            0x8
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT                                                         0x9
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT                                                         0xa
+#define SWRST_EP_CONTROL_0__EP_PORT_IGNORE_CHIP_MODE__SHIFT                                                   0x16
+#define SWRST_EP_CONTROL_0__EP_PORT_CONTROL__SHIFT                                                            0x17
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK                                                         0x00000001L
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK                                                              0x00000100L
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK                                                           0x00000200L
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK                                                           0x00000400L
+#define SWRST_EP_CONTROL_0__EP_PORT_IGNORE_CHIP_MODE_MASK                                                     0x00400000L
+#define SWRST_EP_CONTROL_0__EP_PORT_CONTROL_MASK                                                              0xFF800000L
+//CPM_CONTROL
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT                                                              0x0
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT                                                             0x1
+#define CPM_CONTROL__L1_PWR_GATE_ENABLE__SHIFT                                                                0x2
+#define CPM_CONTROL__L1_1_PWR_GATE_ENABLE__SHIFT                                                              0x3
+#define CPM_CONTROL__L1_2_PWR_GATE_ENABLE__SHIFT                                                              0x4
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT                                                            0x5
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT                                                            0x6
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT                                                            0x7
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT                                                           0x8
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT                                                             0x9
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT                                                            0xb
+#define CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE__SHIFT                                               0xd
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT                                                           0xe
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT                                                          0xf
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT                                                              0x10
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT                                                               0x11
+#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT                                                                0x12
+#define CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG__SHIFT                                                            0x15
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT                                                              0x16
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT                                                             0x17
+#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT                                                       0x18
+#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1__SHIFT                                                             0x19
+#define CPM_CONTROL__PG_EARLY_WAKE_ENABLE__SHIFT                                                              0x1a
+#define CPM_CONTROL__PCIE_CORE_IDLE__SHIFT                                                                    0x1b
+#define CPM_CONTROL__PCIE_LINK_IDLE__SHIFT                                                                    0x1c
+#define CPM_CONTROL__PCIE_BUFFER_EMPTY__SHIFT                                                                 0x1d
+#define CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY__SHIFT                                                           0x1e
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK                                                                0x00000001L
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK                                                               0x00000002L
+#define CPM_CONTROL__L1_PWR_GATE_ENABLE_MASK                                                                  0x00000004L
+#define CPM_CONTROL__L1_1_PWR_GATE_ENABLE_MASK                                                                0x00000008L
+#define CPM_CONTROL__L1_2_PWR_GATE_ENABLE_MASK                                                                0x00000010L
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK                                                              0x00000020L
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK                                                              0x00000040L
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK                                                              0x00000080L
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK                                                             0x00000100L
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK                                                               0x00000600L
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK                                                              0x00001800L
+#define CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE_MASK                                                 0x00002000L
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK                                                             0x00004000L
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK                                                            0x00008000L
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK                                                                0x00010000L
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK                                                                 0x00020000L
+#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK                                                                  0x001C0000L
+#define CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG_MASK                                                              0x00200000L
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK                                                                0x00400000L
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK                                                               0x00800000L
+#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK                                                         0x01000000L
+#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1_MASK                                                               0x02000000L
+#define CPM_CONTROL__PG_EARLY_WAKE_ENABLE_MASK                                                                0x04000000L
+#define CPM_CONTROL__PCIE_CORE_IDLE_MASK                                                                      0x08000000L
+#define CPM_CONTROL__PCIE_LINK_IDLE_MASK                                                                      0x10000000L
+#define CPM_CONTROL__PCIE_BUFFER_EMPTY_MASK                                                                   0x20000000L
+#define CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY_MASK                                                             0xC0000000L
+//CPM_SPLIT_CONTROL
+#define CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE__SHIFT                                                  0x0
+#define CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE_MASK                                                    0x00000001L
+//CPM_CONTROL_EXT
+#define CPM_CONTROL_EXT__PWRDOWN_EI_MASK_DISABLE__SHIFT                                                       0x0
+#define CPM_CONTROL_EXT__DELAY_HOLD_TRAINING_ENABLE__SHIFT                                                    0x1
+#define CPM_CONTROL_EXT__LCLK_DS_MODE__SHIFT                                                                  0x2
+#define CPM_CONTROL_EXT__LCLK_DS_ENABLE__SHIFT                                                                0x3
+#define CPM_CONTROL_EXT__PG_STATE__SHIFT                                                                      0x4
+#define CPM_CONTROL_EXT__PWRDOWN_EI_MASK_DISABLE_MASK                                                         0x00000001L
+#define CPM_CONTROL_EXT__DELAY_HOLD_TRAINING_ENABLE_MASK                                                      0x00000002L
+#define CPM_CONTROL_EXT__LCLK_DS_MODE_MASK                                                                    0x00000004L
+#define CPM_CONTROL_EXT__LCLK_DS_ENABLE_MASK                                                                  0x00000008L
+#define CPM_CONTROL_EXT__PG_STATE_MASK                                                                        0x00000070L
+//SMN_APERTURE_ID_A
+#define SMN_APERTURE_ID_A__PCS_APERTURE_ID__SHIFT                                                             0xc
+#define SMN_APERTURE_ID_A__PCS_APERTURE_ID_MASK                                                               0x00FFF000L
+//SMN_APERTURE_ID_B
+#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT                                                           0x0
+#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT                                                            0xc
+#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK                                                             0x00000FFFL
+#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK                                                              0x00FFF000L
+//LNCNT_CONTROL
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN__SHIFT                                                               0x0
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT                                                               0x1
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT                                                              0x2
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN__SHIFT                                                                 0x3
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL__SHIFT                                                                0x4
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN_MASK                                                                 0x00000001L
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK                                                                 0x00000002L
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK                                                                0x00000004L
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN_MASK                                                                   0x00000008L
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL_MASK                                                                  0x00000010L
+//LNCNT_QUAN_THRD
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD__SHIFT                                                          0x0
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD__SHIFT                                                         0x4
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD_MASK                                                            0x00000007L
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD_MASK                                                           0x00000070L
+//LNCNT_WEIGHT
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT__SHIFT                                                                0x0
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT__SHIFT                                                               0x10
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT_MASK                                                                  0x0000FFFFL
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT_MASK                                                                 0xFFFF0000L
+//PCIE_PGMST_CNTL
+#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT                                                             0x0
+#define PCIE_PGMST_CNTL__CFG_PG_EN__SHIFT                                                                     0x8
+#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT                                                         0xa
+#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL__SHIFT                                                           0xe
+#define PCIE_PGMST_CNTL__PG_EXIT_TIMER__SHIFT                                                                 0x10
+#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK                                                               0x000000FFL
+#define PCIE_PGMST_CNTL__CFG_PG_EN_MASK                                                                       0x00000100L
+#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK                                                           0x00003C00L
+#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL_MASK                                                             0x0000C000L
+#define PCIE_PGMST_CNTL__PG_EXIT_TIMER_MASK                                                                   0x00FF0000L
+//PCIE_PGSLV_CNTL
+#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT                                                           0x0
+#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK                                                             0x0000001FL
+//LC_CPM_CONTROL_0
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE__SHIFT                                                 0x0
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE__SHIFT                                                 0x1
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE__SHIFT                                                 0x2
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE__SHIFT                                                 0x3
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE__SHIFT                                                 0x4
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE__SHIFT                                                 0x5
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE__SHIFT                                                 0x6
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE__SHIFT                                                 0x7
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE__SHIFT                                                 0x8
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE__SHIFT                                                 0x9
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE__SHIFT                                                 0xa
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE__SHIFT                                                 0xb
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE__SHIFT                                                 0xc
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE__SHIFT                                                 0xd
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE__SHIFT                                                 0xe
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE__SHIFT                                                 0xf
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE__SHIFT                                              0x10
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE__SHIFT                                              0x11
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE__SHIFT                                              0x12
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE__SHIFT                                              0x13
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE__SHIFT                                              0x14
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE__SHIFT                                              0x15
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE__SHIFT                                              0x16
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE__SHIFT                                              0x17
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE__SHIFT                                              0x18
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE__SHIFT                                              0x19
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE__SHIFT                                              0x1a
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE__SHIFT                                              0x1b
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE__SHIFT                                              0x1c
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE__SHIFT                                              0x1d
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE__SHIFT                                              0x1e
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE__SHIFT                                              0x1f
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE_MASK                                                   0x00000001L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE_MASK                                                   0x00000002L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE_MASK                                                   0x00000004L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE_MASK                                                   0x00000008L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE_MASK                                                   0x00000010L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE_MASK                                                   0x00000020L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE_MASK                                                   0x00000040L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE_MASK                                                   0x00000080L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE_MASK                                                   0x00000100L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE_MASK                                                   0x00000200L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE_MASK                                                   0x00000400L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE_MASK                                                   0x00000800L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE_MASK                                                   0x00001000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE_MASK                                                   0x00002000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE_MASK                                                   0x00004000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE_MASK                                                   0x00008000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE_MASK                                                0x00010000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE_MASK                                                0x00020000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE_MASK                                                0x00040000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE_MASK                                                0x00080000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE_MASK                                                0x00100000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE_MASK                                                0x00200000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE_MASK                                                0x00400000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE_MASK                                                0x00800000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE_MASK                                                0x01000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE_MASK                                                0x02000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE_MASK                                                0x04000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE_MASK                                                0x08000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE_MASK                                                0x10000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE_MASK                                                0x20000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE_MASK                                                0x40000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE_MASK                                                0x80000000L
+//LC_CPM_CONTROL_1
+#define LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY__SHIFT                                                  0x0
+#define LC_CPM_CONTROL_1__TXCLK_PI_CLK_EN_ALL_LANES_GATE_ENABLE__SHIFT                                        0xf
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE__SHIFT                                          0x10
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE__SHIFT                                          0x11
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE__SHIFT                                          0x12
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE__SHIFT                                          0x13
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE__SHIFT                                          0x14
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE__SHIFT                                          0x15
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE__SHIFT                                          0x16
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE__SHIFT                                          0x17
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE__SHIFT                                          0x18
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE__SHIFT                                          0x19
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE__SHIFT                                          0x1a
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE__SHIFT                                          0x1b
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE__SHIFT                                          0x1c
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE__SHIFT                                          0x1d
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE__SHIFT                                          0x1e
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE__SHIFT                                          0x1f
+#define LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY_MASK                                                    0x00000007L
+#define LC_CPM_CONTROL_1__TXCLK_PI_CLK_EN_ALL_LANES_GATE_ENABLE_MASK                                          0x00008000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE_MASK                                            0x00010000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE_MASK                                            0x00020000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE_MASK                                            0x00040000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE_MASK                                            0x00080000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE_MASK                                            0x00100000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE_MASK                                            0x00200000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE_MASK                                            0x00400000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE_MASK                                            0x00800000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE_MASK                                            0x01000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE_MASK                                            0x02000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE_MASK                                            0x04000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE_MASK                                            0x08000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE_MASK                                            0x10000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE_MASK                                            0x20000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE_MASK                                            0x40000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE_MASK                                            0x80000000L
+//PCIE_RXMARGIN_CONTROL_CAPABILITIES
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED__SHIFT                                         0x0
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE__SHIFT                                         0x1
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING__SHIFT                                       0x2
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD__SHIFT                                    0x3
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER__SHIFT                                          0x4
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED_MASK                                           0x00000001L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE_MASK                                           0x00000002L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING_MASK                                         0x00000004L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD_MASK                                      0x00000008L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER_MASK                                            0x00000010L
+//PCIE_RXMARGIN_1_SETTINGS
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS__SHIFT                                                    0x0
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS__SHIFT                                                     0x7
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET__SHIFT                                                    0xd
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET__SHIFT                                                   0x14
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS_MASK                                                      0x0000007FL
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS_MASK                                                       0x00001F80L
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET_MASK                                                      0x000FE000L
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET_MASK                                                     0x07F00000L
+//PCIE_RXMARGIN_2_SETTINGS
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE__SHIFT                                                0x0
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING__SHIFT                                                 0x6
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT__SHIFT                                                        0xc
+#define PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES__SHIFT                                                           0x13
+#define PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT__SHIFT                                                  0x18
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE_MASK                                                  0x0000003FL
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING_MASK                                                   0x00000FC0L
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT_MASK                                                          0x0007F000L
+#define PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES_MASK                                                             0x00F80000L
+#define PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT_MASK                                                    0x3F000000L
+//PCIE_PRESENCE_DETECT_SELECT
+#define PCIE_PRESENCE_DETECT_SELECT__HPGI_BLOCK_DL_ACTIVE_INT__SHIFT                                          0x0
+#define PCIE_PRESENCE_DETECT_SELECT__HPGI_DL_ACTIVE_STATE_PRIVATE__SHIFT                                      0x8
+#define PCIE_PRESENCE_DETECT_SELECT__DL_ACTIVE_INT_STATUS__SHIFT                                              0x10
+#define PCIE_PRESENCE_DETECT_SELECT__PRESENCE_DETECT_SELECT__SHIFT                                            0x18
+#define PCIE_PRESENCE_DETECT_SELECT__HPGI_BLOCK_DL_ACTIVE_INT_MASK                                            0x000000FFL
+#define PCIE_PRESENCE_DETECT_SELECT__HPGI_DL_ACTIVE_STATE_PRIVATE_MASK                                        0x0000FF00L
+#define PCIE_PRESENCE_DETECT_SELECT__DL_ACTIVE_INT_STATUS_MASK                                                0x00FF0000L
+#define PCIE_PRESENCE_DETECT_SELECT__PRESENCE_DETECT_SELECT_MASK                                              0x01000000L
+
+
+// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
+
+
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow0_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow1_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow2_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow3_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow4_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow5_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow6_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec
+//FASTREG_APERTURE
+#define FASTREG_APERTURE__FASTREG_APERTURE_ID__SHIFT                                                          0x0
+#define FASTREG_APERTURE__FASTREG_NODE_ID__SHIFT                                                              0x10
+#define FASTREG_APERTURE__FASTREG_TRAN_POSTED__SHIFT                                                          0x1f
+#define FASTREG_APERTURE__FASTREG_APERTURE_ID_MASK                                                            0x00000FFFL
+#define FASTREG_APERTURE__FASTREG_NODE_ID_MASK                                                                0x000F0000L
+#define FASTREG_APERTURE__FASTREG_TRAN_POSTED_MASK                                                            0x80000000L
+
+
+// addressBlock: nbio_iohub_nb_NBIF1shadow0_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_NBIF1shadow1_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_NBIF1shadow2_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_misc_misc_cfgdec
+//NBIO_LCLK_DS_MASK
+#define NBIO_LCLK_DS_MASK__LCLK_DS_MASK__SHIFT                                                                0x0
+#define NBIO_LCLK_DS_MASK__LCLK_DS_MASK_MASK                                                                  0xFFFFFFFFL
+//SB_LOCATION
+#define SB_LOCATION__SBlocated_Port__SHIFT                                                                    0x0
+#define SB_LOCATION__SBlocated_Core__SHIFT                                                                    0x10
+#define SB_LOCATION__SBlocated_Port_MASK                                                                      0x0000FFFFL
+#define SB_LOCATION__SBlocated_Core_MASK                                                                      0xFFFF0000L
+//SW_US_LOCATION
+#define SW_US_LOCATION__SW_USlocated_Port__SHIFT                                                              0x0
+#define SW_US_LOCATION__SW_USlocated_Core__SHIFT                                                              0x10
+#define SW_US_LOCATION__SW_USlocated_Port_MASK                                                                0x0000FFFFL
+#define SW_US_LOCATION__SW_USlocated_Core_MASK                                                                0xFFFF0000L
+//SW_NMI_CNTL
+#define SW_NMI_CNTL__SW_NMI_Status__SHIFT                                                                     0x0
+#define SW_NMI_CNTL__SW_NMI_Status_MASK                                                                       0xFFFFFFFFL
+//SW_SMI_CNTL
+#define SW_SMI_CNTL__SW_SMI_Status__SHIFT                                                                     0x0
+#define SW_SMI_CNTL__SW_SMI_Status_MASK                                                                       0xFFFFFFFFL
+//SW_SCI_CNTL
+#define SW_SCI_CNTL__SW_SCI_Status__SHIFT                                                                     0x0
+#define SW_SCI_CNTL__SW_SCI_Status_MASK                                                                       0xFFFFFFFFL
+//APML_SW_STATUS
+#define APML_SW_STATUS__APML_NMI_STATUS__SHIFT                                                                0x0
+#define APML_SW_STATUS__APML_NMI_STATUS_MASK                                                                  0x00000001L
+//SW_GIC_SPI_CNTL
+#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector__SHIFT                                                         0x0
+#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector__SHIFT                                                         0x8
+#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector__SHIFT                                                         0x10
+#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector_MASK                                                           0x000000FFL
+#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector_MASK                                                           0x0000FF00L
+#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector_MASK                                                           0x00FF0000L
+//SW_SYNCFLOOD_CNTL
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE__SHIFT                                                        0x0
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML__SHIFT                                                           0x1
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE_MASK                                                          0x00000001L
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML_MASK                                                             0x00000002L
+//CAM_CONTROL
+#define CAM_CONTROL__CAM_En__SHIFT                                                                            0x0
+#define CAM_CONTROL__Op__SHIFT                                                                                0x1
+#define CAM_CONTROL__AccessType__SHIFT                                                                        0x2
+#define CAM_CONTROL__DataMatchEn__SHIFT                                                                       0x3
+#define CAM_CONTROL__VC__SHIFT                                                                                0x4
+#define CAM_CONTROL__CrossTrigger__SHIFT                                                                      0x8
+#define CAM_CONTROL__CAM_En_MASK                                                                              0x00000001L
+#define CAM_CONTROL__Op_MASK                                                                                  0x00000002L
+#define CAM_CONTROL__AccessType_MASK                                                                          0x00000004L
+#define CAM_CONTROL__DataMatchEn_MASK                                                                         0x00000008L
+#define CAM_CONTROL__VC_MASK                                                                                  0x00000070L
+#define CAM_CONTROL__CrossTrigger_MASK                                                                        0x00000F00L
+//CAM_TARGET_INDEX_ADDR_BOTTOM
+#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom__SHIFT                                                  0x0
+#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom_MASK                                                    0xFFFFFFFFL
+//CAM_TARGET_INDEX_ADDR_TOP
+#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop__SHIFT                                                        0x0
+#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop_MASK                                                          0xFFFFFFFFL
+//CAM_TARGET_INDEX_DATA
+#define CAM_TARGET_INDEX_DATA__IndexData__SHIFT                                                               0x0
+#define CAM_TARGET_INDEX_DATA__IndexData_MASK                                                                 0xFFFFFFFFL
+//CAM_TARGET_INDEX_DATA_MASK
+#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask__SHIFT                                                      0x0
+#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask_MASK                                                        0xFFFFFFFFL
+//CAM_TARGET_DATA_ADDR_BOTTOM
+#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom__SHIFT                                                    0x0
+#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom_MASK                                                      0xFFFFFFFFL
+//CAM_TARGET_DATA_ADDR_TOP
+#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop__SHIFT                                                          0x0
+#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop_MASK                                                            0xFFFFFFFFL
+//CAM_TARGET_DATA
+#define CAM_TARGET_DATA__Data__SHIFT                                                                          0x0
+#define CAM_TARGET_DATA__Data_MASK                                                                            0xFFFFFFFFL
+//CAM_TARGET_DATA_MASK
+#define CAM_TARGET_DATA_MASK__DataMask__SHIFT                                                                 0x0
+#define CAM_TARGET_DATA_MASK__DataMask_MASK                                                                   0xFFFFFFFFL
+//P_DMA_DROPPED_LOG_LOWER
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0__SHIFT                                             0x0
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1__SHIFT                                             0x1
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2__SHIFT                                             0x2
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3__SHIFT                                             0x3
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4__SHIFT                                             0x4
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5__SHIFT                                             0x5
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6__SHIFT                                             0x6
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7__SHIFT                                             0x7
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8__SHIFT                                             0x8
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9__SHIFT                                             0x9
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10__SHIFT                                            0xa
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11__SHIFT                                            0xb
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12__SHIFT                                            0xc
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13__SHIFT                                            0xd
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14__SHIFT                                            0xe
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15__SHIFT                                            0xf
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16__SHIFT                                            0x10
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17__SHIFT                                            0x11
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18__SHIFT                                            0x12
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19__SHIFT                                            0x13
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20__SHIFT                                            0x14
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21__SHIFT                                            0x15
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22__SHIFT                                            0x16
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23__SHIFT                                            0x17
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24__SHIFT                                            0x18
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25__SHIFT                                            0x19
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26__SHIFT                                            0x1a
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27__SHIFT                                            0x1b
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28__SHIFT                                            0x1c
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29__SHIFT                                            0x1d
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30__SHIFT                                            0x1e
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31__SHIFT                                            0x1f
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0_MASK                                               0x00000001L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1_MASK                                               0x00000002L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2_MASK                                               0x00000004L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3_MASK                                               0x00000008L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4_MASK                                               0x00000010L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5_MASK                                               0x00000020L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6_MASK                                               0x00000040L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7_MASK                                               0x00000080L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8_MASK                                               0x00000100L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9_MASK                                               0x00000200L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10_MASK                                              0x00000400L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11_MASK                                              0x00000800L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12_MASK                                              0x00001000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13_MASK                                              0x00002000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14_MASK                                              0x00004000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15_MASK                                              0x00008000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16_MASK                                              0x00010000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17_MASK                                              0x00020000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18_MASK                                              0x00040000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19_MASK                                              0x00080000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20_MASK                                              0x00100000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21_MASK                                              0x00200000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22_MASK                                              0x00400000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23_MASK                                              0x00800000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24_MASK                                              0x01000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25_MASK                                              0x02000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26_MASK                                              0x04000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27_MASK                                              0x08000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28_MASK                                              0x10000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29_MASK                                              0x20000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30_MASK                                              0x40000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31_MASK                                              0x80000000L
+//P_DMA_DROPPED_LOG_UPPER
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0__SHIFT                                             0x0
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1__SHIFT                                             0x1
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2__SHIFT                                             0x2
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3__SHIFT                                             0x3
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4__SHIFT                                             0x4
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5__SHIFT                                             0x5
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6__SHIFT                                             0x6
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7__SHIFT                                             0x7
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8__SHIFT                                             0x8
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9__SHIFT                                             0x9
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10__SHIFT                                            0xa
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11__SHIFT                                            0xb
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12__SHIFT                                            0xc
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13__SHIFT                                            0xd
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14__SHIFT                                            0xe
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15__SHIFT                                            0xf
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16__SHIFT                                            0x10
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17__SHIFT                                            0x11
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18__SHIFT                                            0x12
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19__SHIFT                                            0x13
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20__SHIFT                                            0x14
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21__SHIFT                                            0x15
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22__SHIFT                                            0x16
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23__SHIFT                                            0x17
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24__SHIFT                                            0x18
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25__SHIFT                                            0x19
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26__SHIFT                                            0x1a
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27__SHIFT                                            0x1b
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28__SHIFT                                            0x1c
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29__SHIFT                                            0x1d
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30__SHIFT                                            0x1e
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31__SHIFT                                            0x1f
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0_MASK                                               0x00000001L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1_MASK                                               0x00000002L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2_MASK                                               0x00000004L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3_MASK                                               0x00000008L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4_MASK                                               0x00000010L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5_MASK                                               0x00000020L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6_MASK                                               0x00000040L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7_MASK                                               0x00000080L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8_MASK                                               0x00000100L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9_MASK                                               0x00000200L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10_MASK                                              0x00000400L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11_MASK                                              0x00000800L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12_MASK                                              0x00001000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13_MASK                                              0x00002000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14_MASK                                              0x00004000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15_MASK                                              0x00008000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16_MASK                                              0x00010000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17_MASK                                              0x00020000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18_MASK                                              0x00040000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19_MASK                                              0x00080000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20_MASK                                              0x00100000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21_MASK                                              0x00200000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22_MASK                                              0x00400000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23_MASK                                              0x00800000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24_MASK                                              0x01000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25_MASK                                              0x02000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26_MASK                                              0x04000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27_MASK                                              0x08000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28_MASK                                              0x10000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29_MASK                                              0x20000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30_MASK                                              0x40000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31_MASK                                              0x80000000L
+//NP_DMA_DROPPED_LOG_LOWER
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0__SHIFT                                           0x0
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1__SHIFT                                           0x1
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2__SHIFT                                           0x2
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3__SHIFT                                           0x3
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4__SHIFT                                           0x4
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5__SHIFT                                           0x5
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6__SHIFT                                           0x6
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7__SHIFT                                           0x7
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8__SHIFT                                           0x8
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9__SHIFT                                           0x9
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10__SHIFT                                          0xa
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11__SHIFT                                          0xb
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12__SHIFT                                          0xc
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13__SHIFT                                          0xd
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14__SHIFT                                          0xe
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15__SHIFT                                          0xf
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16__SHIFT                                          0x10
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17__SHIFT                                          0x11
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18__SHIFT                                          0x12
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19__SHIFT                                          0x13
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20__SHIFT                                          0x14
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21__SHIFT                                          0x15
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22__SHIFT                                          0x16
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23__SHIFT                                          0x17
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24__SHIFT                                          0x18
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25__SHIFT                                          0x19
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26__SHIFT                                          0x1a
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27__SHIFT                                          0x1b
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28__SHIFT                                          0x1c
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29__SHIFT                                          0x1d
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30__SHIFT                                          0x1e
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31__SHIFT                                          0x1f
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0_MASK                                             0x00000001L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1_MASK                                             0x00000002L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2_MASK                                             0x00000004L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3_MASK                                             0x00000008L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4_MASK                                             0x00000010L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5_MASK                                             0x00000020L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6_MASK                                             0x00000040L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7_MASK                                             0x00000080L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8_MASK                                             0x00000100L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9_MASK                                             0x00000200L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10_MASK                                            0x00000400L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11_MASK                                            0x00000800L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12_MASK                                            0x00001000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13_MASK                                            0x00002000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14_MASK                                            0x00004000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15_MASK                                            0x00008000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16_MASK                                            0x00010000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17_MASK                                            0x00020000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18_MASK                                            0x00040000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19_MASK                                            0x00080000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20_MASK                                            0x00100000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21_MASK                                            0x00200000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22_MASK                                            0x00400000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23_MASK                                            0x00800000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24_MASK                                            0x01000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25_MASK                                            0x02000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26_MASK                                            0x04000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27_MASK                                            0x08000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28_MASK                                            0x10000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29_MASK                                            0x20000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30_MASK                                            0x40000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31_MASK                                            0x80000000L
+//NP_DMA_DROPPED_LOG_UPPER
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0__SHIFT                                           0x0
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1__SHIFT                                           0x1
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2__SHIFT                                           0x2
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3__SHIFT                                           0x3
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4__SHIFT                                           0x4
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5__SHIFT                                           0x5
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6__SHIFT                                           0x6
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7__SHIFT                                           0x7
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8__SHIFT                                           0x8
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9__SHIFT                                           0x9
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10__SHIFT                                          0xa
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11__SHIFT                                          0xb
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12__SHIFT                                          0xc
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13__SHIFT                                          0xd
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14__SHIFT                                          0xe
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15__SHIFT                                          0xf
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16__SHIFT                                          0x10
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17__SHIFT                                          0x11
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18__SHIFT                                          0x12
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19__SHIFT                                          0x13
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20__SHIFT                                          0x14
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21__SHIFT                                          0x15
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22__SHIFT                                          0x16
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23__SHIFT                                          0x17
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24__SHIFT                                          0x18
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25__SHIFT                                          0x19
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26__SHIFT                                          0x1a
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27__SHIFT                                          0x1b
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28__SHIFT                                          0x1c
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29__SHIFT                                          0x1d
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30__SHIFT                                          0x1e
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31__SHIFT                                          0x1f
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0_MASK                                             0x00000001L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1_MASK                                             0x00000002L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2_MASK                                             0x00000004L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3_MASK                                             0x00000008L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4_MASK                                             0x00000010L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5_MASK                                             0x00000020L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6_MASK                                             0x00000040L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7_MASK                                             0x00000080L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8_MASK                                             0x00000100L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9_MASK                                             0x00000200L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10_MASK                                            0x00000400L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11_MASK                                            0x00000800L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12_MASK                                            0x00001000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13_MASK                                            0x00002000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14_MASK                                            0x00004000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15_MASK                                            0x00008000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16_MASK                                            0x00010000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17_MASK                                            0x00020000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18_MASK                                            0x00040000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19_MASK                                            0x00080000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20_MASK                                            0x00100000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21_MASK                                            0x00200000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22_MASK                                            0x00400000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23_MASK                                            0x00800000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24_MASK                                            0x01000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25_MASK                                            0x02000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26_MASK                                            0x04000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27_MASK                                            0x08000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28_MASK                                            0x10000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29_MASK                                            0x20000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30_MASK                                            0x40000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31_MASK                                            0x80000000L
+//PCIE_VDM_NODE0_CTRL4
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT                                                           0x0
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT                                                          0x8
+#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT                                                            0x1f
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK                                                             0x000000FFL
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK                                                            0x0000FF00L
+#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK                                                              0x80000000L
+//PCIE_VDM_CNTL2
+#define PCIE_VDM_CNTL2__VdmP2pMode__SHIFT                                                                     0x0
+#define PCIE_VDM_CNTL2__MCTPMasterValid__SHIFT                                                                0xf
+#define PCIE_VDM_CNTL2__MCTPMasterID__SHIFT                                                                   0x10
+#define PCIE_VDM_CNTL2__VdmP2pMode_MASK                                                                       0x00000003L
+#define PCIE_VDM_CNTL2__MCTPMasterValid_MASK                                                                  0x00008000L
+#define PCIE_VDM_CNTL2__MCTPMasterID_MASK                                                                     0xFFFF0000L
+//PCIE_VDM_CNTL3
+#define PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT                                                               0xf
+#define PCIE_VDM_CNTL3__APMTPMasterID__SHIFT                                                                  0x10
+#define PCIE_VDM_CNTL3__APMTPMasterValid_MASK                                                                 0x00008000L
+#define PCIE_VDM_CNTL3__APMTPMasterID_MASK                                                                    0xFFFF0000L
+//STALL_CONTROL_XBARPORT0_0
+#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT0_1
+#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT1_0
+#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT1_1
+#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT2_0
+#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT2_1
+#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT3_0
+#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT3_1
+#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT4_0
+#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT4_1
+#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT5_0
+#define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT5_1
+#define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT6_0
+#define STALL_CONTROL_XBARPORT6_0__StallVC0ReqEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT6_0__StallVC1ReqEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT6_0__StallVC2ReqEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT6_0__StallVC3ReqEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT6_0__StallVC4ReqEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT6_0__StallVC5ReqEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT6_0__StallVC7ReqEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT6_0__StallVC0ReqEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT6_0__StallVC1ReqEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT6_0__StallVC2ReqEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT6_0__StallVC3ReqEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT6_0__StallVC4ReqEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT6_0__StallVC5ReqEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT6_0__StallVC7ReqEn_MASK                                                         0x30000000L
+//STALL_CONTROL_XBARPORT6_1
+#define STALL_CONTROL_XBARPORT6_1__StallVC0RspEn__SHIFT                                                       0x0
+#define STALL_CONTROL_XBARPORT6_1__StallVC1RspEn__SHIFT                                                       0x4
+#define STALL_CONTROL_XBARPORT6_1__StallVC2RspEn__SHIFT                                                       0x8
+#define STALL_CONTROL_XBARPORT6_1__StallVC3RspEn__SHIFT                                                       0xc
+#define STALL_CONTROL_XBARPORT6_1__StallVC4RspEn__SHIFT                                                       0x10
+#define STALL_CONTROL_XBARPORT6_1__StallVC5RspEn__SHIFT                                                       0x14
+#define STALL_CONTROL_XBARPORT6_1__StallVC7RspEn__SHIFT                                                       0x1c
+#define STALL_CONTROL_XBARPORT6_1__StallVC0RspEn_MASK                                                         0x00000003L
+#define STALL_CONTROL_XBARPORT6_1__StallVC1RspEn_MASK                                                         0x00000030L
+#define STALL_CONTROL_XBARPORT6_1__StallVC2RspEn_MASK                                                         0x00000300L
+#define STALL_CONTROL_XBARPORT6_1__StallVC3RspEn_MASK                                                         0x00003000L
+#define STALL_CONTROL_XBARPORT6_1__StallVC4RspEn_MASK                                                         0x00030000L
+#define STALL_CONTROL_XBARPORT6_1__StallVC5RspEn_MASK                                                         0x00300000L
+#define STALL_CONTROL_XBARPORT6_1__StallVC7RspEn_MASK                                                         0x30000000L
+//FASTREG_BASE_ADDR_LO
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN__SHIFT                                                          0x0
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK__SHIFT                                                        0x1
+#define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO__SHIFT                                                     0x14
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN_MASK                                                            0x00000001L
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK_MASK                                                          0x00000002L
+#define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO_MASK                                                       0xFFF00000L
+//FASTREG_BASE_ADDR_HI
+#define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI__SHIFT                                                     0x0
+#define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI_MASK                                                       0x0000FFFFL
+//FASTREGCNTL_BASE_ADDR_LO
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN__SHIFT                                                  0x0
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK__SHIFT                                                0x1
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO__SHIFT                                             0xc
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN_MASK                                                    0x00000001L
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK_MASK                                                  0x00000002L
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO_MASK                                               0xFFFFF000L
+//FASTREGCNTL_BASE_ADDR_HI
+#define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI__SHIFT                                             0x0
+#define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI_MASK                                               0x0000FFFFL
+//SCRATCH_4
+#define SCRATCH_4__SCRATCH_4__SHIFT                                                                           0x0
+#define SCRATCH_4__SCRATCH_4_MASK                                                                             0xFFFFFFFFL
+//SCRATCH_5
+#define SCRATCH_5__SCRATCH_5__SHIFT                                                                           0x0
+#define SCRATCH_5__SCRATCH_5_MASK                                                                             0xFFFFFFFFL
+//TRAP_STATUS
+#define TRAP_STATUS__TrapReqValid__SHIFT                                                                      0x0
+#define TRAP_STATUS__TrapNumber__SHIFT                                                                        0x8
+#define TRAP_STATUS__TrapReqValid_MASK                                                                        0x00000001L
+#define TRAP_STATUS__TrapNumber_MASK                                                                          0x00000F00L
+//TRAP_REQUEST0
+#define TRAP_REQUEST0__TrapReqAddrLo__SHIFT                                                                   0x2
+#define TRAP_REQUEST0__TrapReqAddrLo_MASK                                                                     0xFFFFFFFCL
+//TRAP_REQUEST1
+#define TRAP_REQUEST1__TrapReqAddrHi__SHIFT                                                                   0x0
+#define TRAP_REQUEST1__TrapReqAddrHi_MASK                                                                     0xFFFFFFFFL
+//TRAP_REQUEST2
+#define TRAP_REQUEST2__TrapReqCmd__SHIFT                                                                      0x0
+#define TRAP_REQUEST2__TrapAttr__SHIFT                                                                        0x8
+#define TRAP_REQUEST2__TrapReqLen__SHIFT                                                                      0x10
+#define TRAP_REQUEST2__TrapReqCmd_MASK                                                                        0x0000003FL
+#define TRAP_REQUEST2__TrapAttr_MASK                                                                          0x0000FF00L
+#define TRAP_REQUEST2__TrapReqLen_MASK                                                                        0x003F0000L
+//TRAP_REQUEST3
+#define TRAP_REQUEST3__TrapReqVC__SHIFT                                                                       0x0
+#define TRAP_REQUEST3__TrapReqBlockLevel__SHIFT                                                               0x4
+#define TRAP_REQUEST3__TrapReqChain__SHIFT                                                                    0x6
+#define TRAP_REQUEST3__TrapReqIO__SHIFT                                                                       0x7
+#define TRAP_REQUEST3__TrapReqPassPW__SHIFT                                                                   0x8
+#define TRAP_REQUEST3__TrapReqRspPassPW__SHIFT                                                                0x9
+#define TRAP_REQUEST3__TrapReqUnitID__SHIFT                                                                   0x10
+#define TRAP_REQUEST3__TrapReqVC_MASK                                                                         0x00000007L
+#define TRAP_REQUEST3__TrapReqBlockLevel_MASK                                                                 0x00000030L
+#define TRAP_REQUEST3__TrapReqChain_MASK                                                                      0x00000040L
+#define TRAP_REQUEST3__TrapReqIO_MASK                                                                         0x00000080L
+#define TRAP_REQUEST3__TrapReqPassPW_MASK                                                                     0x00000100L
+#define TRAP_REQUEST3__TrapReqRspPassPW_MASK                                                                  0x00000200L
+#define TRAP_REQUEST3__TrapReqUnitID_MASK                                                                     0x003F0000L
+//TRAP_REQUEST4
+#define TRAP_REQUEST4__TrapReqSecLevel__SHIFT                                                                 0x0
+#define TRAP_REQUEST4__TrapReqSecLevel_MASK                                                                   0x0000000FL
+//TRAP_REQUEST5
+#define TRAP_REQUEST5__TrapReqDataVC__SHIFT                                                                   0x0
+#define TRAP_REQUEST5__TrapReqDataErr__SHIFT                                                                  0x4
+#define TRAP_REQUEST5__TrapReqDataParity__SHIFT                                                               0x8
+#define TRAP_REQUEST5__TrapReqDataVC_MASK                                                                     0x00000007L
+#define TRAP_REQUEST5__TrapReqDataErr_MASK                                                                    0x00000010L
+#define TRAP_REQUEST5__TrapReqDataParity_MASK                                                                 0x0000FF00L
+//TRAP_REQUEST_DATASTRB0
+#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT                                                      0x0
+#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK                                                        0xFFFFFFFFL
+//TRAP_REQUEST_DATASTRB1
+#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT                                                      0x0
+#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK                                                        0xFFFFFFFFL
+//TRAP_REQUEST_DATA0
+#define TRAP_REQUEST_DATA0__TrapReqData0__SHIFT                                                               0x0
+#define TRAP_REQUEST_DATA0__TrapReqData0_MASK                                                                 0xFFFFFFFFL
+//TRAP_REQUEST_DATA1
+#define TRAP_REQUEST_DATA1__TrapReqData1__SHIFT                                                               0x0
+#define TRAP_REQUEST_DATA1__TrapReqData1_MASK                                                                 0xFFFFFFFFL
+//TRAP_REQUEST_DATA2
+#define TRAP_REQUEST_DATA2__TrapReqData2__SHIFT                                                               0x0
+#define TRAP_REQUEST_DATA2__TrapReqData2_MASK                                                                 0xFFFFFFFFL
+//TRAP_REQUEST_DATA3
+#define TRAP_REQUEST_DATA3__TrapReqData3__SHIFT                                                               0x0
+#define TRAP_REQUEST_DATA3__TrapReqData3_MASK                                                                 0xFFFFFFFFL
+//TRAP_REQUEST_DATA4
+#define TRAP_REQUEST_DATA4__TrapReqData4__SHIFT                                                               0x0
+#define TRAP_REQUEST_DATA4__TrapReqData4_MASK                                                                 0xFFFFFFFFL
+//TRAP_REQUEST_DATA5
+#define TRAP_REQUEST_DATA5__TrapReqData5__SHIFT                                                               0x0
+#define TRAP_REQUEST_DATA5__TrapReqData5_MASK                                                                 0xFFFFFFFFL
+//TRAP_REQUEST_DATA6
+#define TRAP_REQUEST_DATA6__TrapReqData6__SHIFT                                                               0x0
+#define TRAP_REQUEST_DATA6__TrapReqData6_MASK                                                                 0xFFFFFFFFL
+//TRAP_REQUEST_DATA7
+#define TRAP_REQUEST_DATA7__TrapReqData7__SHIFT                                                               0x0
+#define TRAP_REQUEST_DATA7__TrapReqData7_MASK                                                                 0xFFFFFFFFL
+//TRAP_REQUEST_DATA8
+#define TRAP_REQUEST_DATA8__TrapReqData8__SHIFT                                                               0x0
+#define TRAP_REQUEST_DATA8__TrapReqData8_MASK                                                                 0xFFFFFFFFL
+//TRAP_REQUEST_DATA9
+#define TRAP_REQUEST_DATA9__TrapReqData9__SHIFT                                                               0x0
+#define TRAP_REQUEST_DATA9__TrapReqData9_MASK                                                                 0xFFFFFFFFL
+//TRAP_REQUEST_DATA10
+#define TRAP_REQUEST_DATA10__TrapReqData10__SHIFT                                                             0x0
+#define TRAP_REQUEST_DATA10__TrapReqData10_MASK                                                               0xFFFFFFFFL
+//TRAP_REQUEST_DATA11
+#define TRAP_REQUEST_DATA11__TrapReqData11__SHIFT                                                             0x0
+#define TRAP_REQUEST_DATA11__TrapReqData11_MASK                                                               0xFFFFFFFFL
+//TRAP_REQUEST_DATA12
+#define TRAP_REQUEST_DATA12__TrapReqData12__SHIFT                                                             0x0
+#define TRAP_REQUEST_DATA12__TrapReqData12_MASK                                                               0xFFFFFFFFL
+//TRAP_REQUEST_DATA13
+#define TRAP_REQUEST_DATA13__TrapReqData13__SHIFT                                                             0x0
+#define TRAP_REQUEST_DATA13__TrapReqData13_MASK                                                               0xFFFFFFFFL
+//TRAP_REQUEST_DATA14
+#define TRAP_REQUEST_DATA14__TrapReqData14__SHIFT                                                             0x0
+#define TRAP_REQUEST_DATA14__TrapReqData14_MASK                                                               0xFFFFFFFFL
+//TRAP_REQUEST_DATA15
+#define TRAP_REQUEST_DATA15__TrapReqData15__SHIFT                                                             0x0
+#define TRAP_REQUEST_DATA15__TrapReqData15_MASK                                                               0xFFFFFFFFL
+//TRAP_RESPONSE_CONTROL
+#define TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT                                                          0x0
+#define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru__SHIFT                                                      0x1
+#define TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK                                                            0x00000001L
+#define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru_MASK                                                        0x00000002L
+//TRAP_RESPONSE0
+#define TRAP_RESPONSE0__TrapRspPassPW__SHIFT                                                                  0x0
+#define TRAP_RESPONSE0__TrapRspStatus__SHIFT                                                                  0x4
+#define TRAP_RESPONSE0__TrapRspDataStatus__SHIFT                                                              0x10
+#define TRAP_RESPONSE0__TrapRspPassPW_MASK                                                                    0x00000001L
+#define TRAP_RESPONSE0__TrapRspStatus_MASK                                                                    0x000000F0L
+#define TRAP_RESPONSE0__TrapRspDataStatus_MASK                                                                0x00FF0000L
+//TRAP_RESPONSE_DATA0
+#define TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT                                                            0x0
+#define TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK                                                              0xFFFFFFFFL
+//TRAP_RESPONSE_DATA1
+#define TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT                                                            0x0
+#define TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK                                                              0xFFFFFFFFL
+//TRAP_RESPONSE_DATA2
+#define TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT                                                            0x0
+#define TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK                                                              0xFFFFFFFFL
+//TRAP_RESPONSE_DATA3
+#define TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT                                                            0x0
+#define TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK                                                              0xFFFFFFFFL
+//TRAP_RESPONSE_DATA4
+#define TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT                                                            0x0
+#define TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK                                                              0xFFFFFFFFL
+//TRAP_RESPONSE_DATA5
+#define TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT                                                            0x0
+#define TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK                                                              0xFFFFFFFFL
+//TRAP_RESPONSE_DATA6
+#define TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT                                                            0x0
+#define TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK                                                              0xFFFFFFFFL
+//TRAP_RESPONSE_DATA7
+#define TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT                                                            0x0
+#define TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK                                                              0xFFFFFFFFL
+//TRAP_RESPONSE_DATA8
+#define TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT                                                            0x0
+#define TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK                                                              0xFFFFFFFFL
+//TRAP_RESPONSE_DATA9
+#define TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT                                                            0x0
+#define TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK                                                              0xFFFFFFFFL
+//TRAP_RESPONSE_DATA10
+#define TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT                                                          0x0
+#define TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK                                                            0xFFFFFFFFL
+//TRAP_RESPONSE_DATA11
+#define TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT                                                          0x0
+#define TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK                                                            0xFFFFFFFFL
+//TRAP_RESPONSE_DATA12
+#define TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT                                                          0x0
+#define TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK                                                            0xFFFFFFFFL
+//TRAP_RESPONSE_DATA13
+#define TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT                                                          0x0
+#define TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK                                                            0xFFFFFFFFL
+//TRAP_RESPONSE_DATA14
+#define TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT                                                          0x0
+#define TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK                                                            0xFFFFFFFFL
+//TRAP_RESPONSE_DATA15
+#define TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT                                                          0x0
+#define TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK                                                            0xFFFFFFFFL
+//TRAP0_CONTROL0
+#define TRAP0_CONTROL0__Trap0En__SHIFT                                                                        0x0
+#define TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT                                                              0x18
+#define TRAP0_CONTROL0__Trap0En_MASK                                                                          0x00000001L
+#define TRAP0_CONTROL0__Trap0CrossTrigger_MASK                                                                0x0F000000L
+//TRAP0_ADDRESS_LO
+#define TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT                                                                  0x2
+#define TRAP0_ADDRESS_LO__Trap0AddrLo_MASK                                                                    0xFFFFFFFCL
+//TRAP0_ADDRESS_HI
+#define TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT                                                                  0x0
+#define TRAP0_ADDRESS_HI__Trap0AddrHi_MASK                                                                    0xFFFFFFFFL
+//TRAP0_COMMAND
+#define TRAP0_COMMAND__Trap0Cmd0__SHIFT                                                                       0x0
+#define TRAP0_COMMAND__Trap0Cmd1__SHIFT                                                                       0x8
+#define TRAP0_COMMAND__Trap0Cmd0_MASK                                                                         0x0000003FL
+#define TRAP0_COMMAND__Trap0Cmd1_MASK                                                                         0x00003F00L
+//TRAP0_ADDRESS_LO_MASK
+#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT                                                         0x2
+#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK                                                           0xFFFFFFFCL
+//TRAP0_ADDRESS_HI_MASK
+#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT                                                         0x0
+#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK                                                           0xFFFFFFFFL
+//TRAP0_COMMAND_MASK
+#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT                                                              0x0
+#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT                                                              0x8
+#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK                                                                0x0000003FL
+#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK                                                                0x00003F00L
+//TRAP1_CONTROL0
+#define TRAP1_CONTROL0__Trap1En__SHIFT                                                                        0x0
+#define TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT                                                              0x18
+#define TRAP1_CONTROL0__Trap1En_MASK                                                                          0x00000001L
+#define TRAP1_CONTROL0__Trap1CrossTrigger_MASK                                                                0x0F000000L
+//TRAP1_ADDRESS_LO
+#define TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT                                                                  0x2
+#define TRAP1_ADDRESS_LO__Trap1AddrLo_MASK                                                                    0xFFFFFFFCL
+//TRAP1_ADDRESS_HI
+#define TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT                                                                  0x0
+#define TRAP1_ADDRESS_HI__Trap1AddrHi_MASK                                                                    0xFFFFFFFFL
+//TRAP1_COMMAND
+#define TRAP1_COMMAND__Trap1Cmd0__SHIFT                                                                       0x0
+#define TRAP1_COMMAND__Trap1Cmd1__SHIFT                                                                       0x8
+#define TRAP1_COMMAND__Trap1Cmd0_MASK                                                                         0x0000003FL
+#define TRAP1_COMMAND__Trap1Cmd1_MASK                                                                         0x00003F00L
+//TRAP1_ADDRESS_LO_MASK
+#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT                                                         0x2
+#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK                                                           0xFFFFFFFCL
+//TRAP1_ADDRESS_HI_MASK
+#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT                                                         0x0
+#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK                                                           0xFFFFFFFFL
+//TRAP1_COMMAND_MASK
+#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT                                                              0x0
+#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT                                                              0x8
+#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK                                                                0x0000003FL
+#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK                                                                0x00003F00L
+//TRAP2_CONTROL0
+#define TRAP2_CONTROL0__Trap2En__SHIFT                                                                        0x0
+#define TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT                                                              0x18
+#define TRAP2_CONTROL0__Trap2En_MASK                                                                          0x00000001L
+#define TRAP2_CONTROL0__Trap2CrossTrigger_MASK                                                                0x0F000000L
+//TRAP2_ADDRESS_LO
+#define TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT                                                                  0x2
+#define TRAP2_ADDRESS_LO__Trap2AddrLo_MASK                                                                    0xFFFFFFFCL
+//TRAP2_ADDRESS_HI
+#define TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT                                                                  0x0
+#define TRAP2_ADDRESS_HI__Trap2AddrHi_MASK                                                                    0xFFFFFFFFL
+//TRAP2_COMMAND
+#define TRAP2_COMMAND__Trap2Cmd0__SHIFT                                                                       0x0
+#define TRAP2_COMMAND__Trap2Cmd1__SHIFT                                                                       0x8
+#define TRAP2_COMMAND__Trap2Cmd0_MASK                                                                         0x0000003FL
+#define TRAP2_COMMAND__Trap2Cmd1_MASK                                                                         0x00003F00L
+//TRAP2_ADDRESS_LO_MASK
+#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT                                                         0x2
+#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK                                                           0xFFFFFFFCL
+//TRAP2_ADDRESS_HI_MASK
+#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT                                                         0x0
+#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK                                                           0xFFFFFFFFL
+//TRAP2_COMMAND_MASK
+#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT                                                              0x0
+#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT                                                              0x8
+#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK                                                                0x0000003FL
+#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK                                                                0x00003F00L
+//TRAP3_CONTROL0
+#define TRAP3_CONTROL0__Trap3En__SHIFT                                                                        0x0
+#define TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT                                                              0x18
+#define TRAP3_CONTROL0__Trap3En_MASK                                                                          0x00000001L
+#define TRAP3_CONTROL0__Trap3CrossTrigger_MASK                                                                0x0F000000L
+//TRAP3_ADDRESS_LO
+#define TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT                                                                  0x2
+#define TRAP3_ADDRESS_LO__Trap3AddrLo_MASK                                                                    0xFFFFFFFCL
+//TRAP3_ADDRESS_HI
+#define TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT                                                                  0x0
+#define TRAP3_ADDRESS_HI__Trap3AddrHi_MASK                                                                    0xFFFFFFFFL
+//TRAP3_COMMAND
+#define TRAP3_COMMAND__Trap3Cmd0__SHIFT                                                                       0x0
+#define TRAP3_COMMAND__Trap3Cmd1__SHIFT                                                                       0x8
+#define TRAP3_COMMAND__Trap3Cmd0_MASK                                                                         0x0000003FL
+#define TRAP3_COMMAND__Trap3Cmd1_MASK                                                                         0x00003F00L
+//TRAP3_ADDRESS_LO_MASK
+#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT                                                         0x2
+#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK                                                           0xFFFFFFFCL
+//TRAP3_ADDRESS_HI_MASK
+#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT                                                         0x0
+#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK                                                           0xFFFFFFFFL
+//TRAP3_COMMAND_MASK
+#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT                                                              0x0
+#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT                                                              0x8
+#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK                                                                0x0000003FL
+#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK                                                                0x00003F00L
+//TRAP4_CONTROL0
+#define TRAP4_CONTROL0__Trap4En__SHIFT                                                                        0x0
+#define TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT                                                              0x18
+#define TRAP4_CONTROL0__Trap4En_MASK                                                                          0x00000001L
+#define TRAP4_CONTROL0__Trap4CrossTrigger_MASK                                                                0x0F000000L
+//TRAP4_ADDRESS_LO
+#define TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT                                                                  0x2
+#define TRAP4_ADDRESS_LO__Trap4AddrLo_MASK                                                                    0xFFFFFFFCL
+//TRAP4_ADDRESS_HI
+#define TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT                                                                  0x0
+#define TRAP4_ADDRESS_HI__Trap4AddrHi_MASK                                                                    0xFFFFFFFFL
+//TRAP4_COMMAND
+#define TRAP4_COMMAND__Trap4Cmd0__SHIFT                                                                       0x0
+#define TRAP4_COMMAND__Trap4Cmd1__SHIFT                                                                       0x8
+#define TRAP4_COMMAND__Trap4Cmd0_MASK                                                                         0x0000003FL
+#define TRAP4_COMMAND__Trap4Cmd1_MASK                                                                         0x00003F00L
+//TRAP4_ADDRESS_LO_MASK
+#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT                                                         0x2
+#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK                                                           0xFFFFFFFCL
+//TRAP4_ADDRESS_HI_MASK
+#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT                                                         0x0
+#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK                                                           0xFFFFFFFFL
+//TRAP4_COMMAND_MASK
+#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT                                                              0x0
+#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT                                                              0x8
+#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK                                                                0x0000003FL
+#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK                                                                0x00003F00L
+//TRAP5_CONTROL0
+#define TRAP5_CONTROL0__Trap5En__SHIFT                                                                        0x0
+#define TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT                                                              0x18
+#define TRAP5_CONTROL0__Trap5En_MASK                                                                          0x00000001L
+#define TRAP5_CONTROL0__Trap5CrossTrigger_MASK                                                                0x0F000000L
+//TRAP5_ADDRESS_LO
+#define TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT                                                                  0x2
+#define TRAP5_ADDRESS_LO__Trap5AddrLo_MASK                                                                    0xFFFFFFFCL
+//TRAP5_ADDRESS_HI
+#define TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT                                                                  0x0
+#define TRAP5_ADDRESS_HI__Trap5AddrHi_MASK                                                                    0xFFFFFFFFL
+//TRAP5_COMMAND
+#define TRAP5_COMMAND__Trap5Cmd0__SHIFT                                                                       0x0
+#define TRAP5_COMMAND__Trap5Cmd1__SHIFT                                                                       0x8
+#define TRAP5_COMMAND__Trap5Cmd0_MASK                                                                         0x0000003FL
+#define TRAP5_COMMAND__Trap5Cmd1_MASK                                                                         0x00003F00L
+//TRAP5_ADDRESS_LO_MASK
+#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT                                                         0x2
+#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK                                                           0xFFFFFFFCL
+//TRAP5_ADDRESS_HI_MASK
+#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT                                                         0x0
+#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK                                                           0xFFFFFFFFL
+//TRAP5_COMMAND_MASK
+#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT                                                              0x0
+#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT                                                              0x8
+#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK                                                                0x0000003FL
+#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK                                                                0x00003F00L
+//TRAP6_CONTROL0
+#define TRAP6_CONTROL0__Trap6En__SHIFT                                                                        0x0
+#define TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT                                                              0x18
+#define TRAP6_CONTROL0__Trap6En_MASK                                                                          0x00000001L
+#define TRAP6_CONTROL0__Trap6CrossTrigger_MASK                                                                0x0F000000L
+//TRAP6_ADDRESS_LO
+#define TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT                                                                  0x2
+#define TRAP6_ADDRESS_LO__Trap6AddrLo_MASK                                                                    0xFFFFFFFCL
+//TRAP6_ADDRESS_HI
+#define TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT                                                                  0x0
+#define TRAP6_ADDRESS_HI__Trap6AddrHi_MASK                                                                    0xFFFFFFFFL
+//TRAP6_COMMAND
+#define TRAP6_COMMAND__Trap6Cmd0__SHIFT                                                                       0x0
+#define TRAP6_COMMAND__Trap6Cmd1__SHIFT                                                                       0x8
+#define TRAP6_COMMAND__Trap6Cmd0_MASK                                                                         0x0000003FL
+#define TRAP6_COMMAND__Trap6Cmd1_MASK                                                                         0x00003F00L
+//TRAP6_ADDRESS_LO_MASK
+#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT                                                         0x2
+#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK                                                           0xFFFFFFFCL
+//TRAP6_ADDRESS_HI_MASK
+#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT                                                         0x0
+#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK                                                           0xFFFFFFFFL
+//TRAP6_COMMAND_MASK
+#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT                                                              0x0
+#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT                                                              0x8
+#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK                                                                0x0000003FL
+#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK                                                                0x00003F00L
+//TRAP7_CONTROL0
+#define TRAP7_CONTROL0__Trap7En__SHIFT                                                                        0x0
+#define TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT                                                              0x18
+#define TRAP7_CONTROL0__Trap7En_MASK                                                                          0x00000001L
+#define TRAP7_CONTROL0__Trap7CrossTrigger_MASK                                                                0x0F000000L
+//TRAP7_ADDRESS_LO
+#define TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT                                                                  0x2
+#define TRAP7_ADDRESS_LO__Trap7AddrLo_MASK                                                                    0xFFFFFFFCL
+//TRAP7_ADDRESS_HI
+#define TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT                                                                  0x0
+#define TRAP7_ADDRESS_HI__Trap7AddrHi_MASK                                                                    0xFFFFFFFFL
+//TRAP7_COMMAND
+#define TRAP7_COMMAND__Trap7Cmd0__SHIFT                                                                       0x0
+#define TRAP7_COMMAND__Trap7Cmd1__SHIFT                                                                       0x8
+#define TRAP7_COMMAND__Trap7Cmd0_MASK                                                                         0x0000003FL
+#define TRAP7_COMMAND__Trap7Cmd1_MASK                                                                         0x00003F00L
+//TRAP7_ADDRESS_LO_MASK
+#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT                                                         0x2
+#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK                                                           0xFFFFFFFCL
+//TRAP7_ADDRESS_HI_MASK
+#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT                                                         0x0
+#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK                                                           0xFFFFFFFFL
+//TRAP7_COMMAND_MASK
+#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT                                                              0x0
+#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT                                                              0x8
+#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK                                                                0x0000003FL
+#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK                                                                0x00003F00L
+//TRAP8_CONTROL0
+#define TRAP8_CONTROL0__Trap8En__SHIFT                                                                        0x0
+#define TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT                                                              0x18
+#define TRAP8_CONTROL0__Trap8En_MASK                                                                          0x00000001L
+#define TRAP8_CONTROL0__Trap8CrossTrigger_MASK                                                                0x0F000000L
+//TRAP8_ADDRESS_LO
+#define TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT                                                                  0x2
+#define TRAP8_ADDRESS_LO__Trap8AddrLo_MASK                                                                    0xFFFFFFFCL
+//TRAP8_ADDRESS_HI
+#define TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT                                                                  0x0
+#define TRAP8_ADDRESS_HI__Trap8AddrHi_MASK                                                                    0xFFFFFFFFL
+//TRAP8_COMMAND
+#define TRAP8_COMMAND__Trap8Cmd0__SHIFT                                                                       0x0
+#define TRAP8_COMMAND__Trap8Cmd1__SHIFT                                                                       0x8
+#define TRAP8_COMMAND__Trap8Cmd0_MASK                                                                         0x0000003FL
+#define TRAP8_COMMAND__Trap8Cmd1_MASK                                                                         0x00003F00L
+//TRAP8_ADDRESS_LO_MASK
+#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT                                                         0x2
+#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK                                                           0xFFFFFFFCL
+//TRAP8_ADDRESS_HI_MASK
+#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT                                                         0x0
+#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK                                                           0xFFFFFFFFL
+//TRAP8_COMMAND_MASK
+#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT                                                              0x0
+#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT                                                              0x8
+#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK                                                                0x0000003FL
+#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK                                                                0x00003F00L
+//TRAP9_CONTROL0
+#define TRAP9_CONTROL0__Trap9En__SHIFT                                                                        0x0
+#define TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT                                                              0x18
+#define TRAP9_CONTROL0__Trap9En_MASK                                                                          0x00000001L
+#define TRAP9_CONTROL0__Trap9CrossTrigger_MASK                                                                0x0F000000L
+//TRAP9_ADDRESS_LO
+#define TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT                                                                  0x2
+#define TRAP9_ADDRESS_LO__Trap9AddrLo_MASK                                                                    0xFFFFFFFCL
+//TRAP9_ADDRESS_HI
+#define TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT                                                                  0x0
+#define TRAP9_ADDRESS_HI__Trap9AddrHi_MASK                                                                    0xFFFFFFFFL
+//TRAP9_COMMAND
+#define TRAP9_COMMAND__Trap9Cmd0__SHIFT                                                                       0x0
+#define TRAP9_COMMAND__Trap9Cmd1__SHIFT                                                                       0x8
+#define TRAP9_COMMAND__Trap9Cmd0_MASK                                                                         0x0000003FL
+#define TRAP9_COMMAND__Trap9Cmd1_MASK                                                                         0x00003F00L
+//TRAP9_ADDRESS_LO_MASK
+#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT                                                         0x2
+#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK                                                           0xFFFFFFFCL
+//TRAP9_ADDRESS_HI_MASK
+#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT                                                         0x0
+#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK                                                           0xFFFFFFFFL
+//TRAP9_COMMAND_MASK
+#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT                                                              0x0
+#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT                                                              0x8
+#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK                                                                0x0000003FL
+#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK                                                                0x00003F00L
+//TRAP10_CONTROL0
+#define TRAP10_CONTROL0__Trap10En__SHIFT                                                                      0x0
+#define TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT                                                            0x18
+#define TRAP10_CONTROL0__Trap10En_MASK                                                                        0x00000001L
+#define TRAP10_CONTROL0__Trap10CrossTrigger_MASK                                                              0x0F000000L
+//TRAP10_ADDRESS_LO
+#define TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT                                                                0x2
+#define TRAP10_ADDRESS_LO__Trap10AddrLo_MASK                                                                  0xFFFFFFFCL
+//TRAP10_ADDRESS_HI
+#define TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT                                                                0x0
+#define TRAP10_ADDRESS_HI__Trap10AddrHi_MASK                                                                  0xFFFFFFFFL
+//TRAP10_COMMAND
+#define TRAP10_COMMAND__Trap10Cmd0__SHIFT                                                                     0x0
+#define TRAP10_COMMAND__Trap10Cmd1__SHIFT                                                                     0x8
+#define TRAP10_COMMAND__Trap10Cmd0_MASK                                                                       0x0000003FL
+#define TRAP10_COMMAND__Trap10Cmd1_MASK                                                                       0x00003F00L
+//TRAP10_ADDRESS_LO_MASK
+#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT                                                       0x2
+#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK                                                         0xFFFFFFFCL
+//TRAP10_ADDRESS_HI_MASK
+#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT                                                       0x0
+#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK                                                         0xFFFFFFFFL
+//TRAP10_COMMAND_MASK
+#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT                                                            0x0
+#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT                                                            0x8
+#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK                                                              0x0000003FL
+#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK                                                              0x00003F00L
+//TRAP11_CONTROL0
+#define TRAP11_CONTROL0__Trap11En__SHIFT                                                                      0x0
+#define TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT                                                            0x18
+#define TRAP11_CONTROL0__Trap11En_MASK                                                                        0x00000001L
+#define TRAP11_CONTROL0__Trap11CrossTrigger_MASK                                                              0x0F000000L
+//TRAP11_ADDRESS_LO
+#define TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT                                                                0x2
+#define TRAP11_ADDRESS_LO__Trap11AddrLo_MASK                                                                  0xFFFFFFFCL
+//TRAP11_ADDRESS_HI
+#define TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT                                                                0x0
+#define TRAP11_ADDRESS_HI__Trap11AddrHi_MASK                                                                  0xFFFFFFFFL
+//TRAP11_COMMAND
+#define TRAP11_COMMAND__Trap11Cmd0__SHIFT                                                                     0x0
+#define TRAP11_COMMAND__Trap11Cmd1__SHIFT                                                                     0x8
+#define TRAP11_COMMAND__Trap11Cmd0_MASK                                                                       0x0000003FL
+#define TRAP11_COMMAND__Trap11Cmd1_MASK                                                                       0x00003F00L
+//TRAP11_ADDRESS_LO_MASK
+#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT                                                       0x2
+#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK                                                         0xFFFFFFFCL
+//TRAP11_ADDRESS_HI_MASK
+#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT                                                       0x0
+#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK                                                         0xFFFFFFFFL
+//TRAP11_COMMAND_MASK
+#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT                                                            0x0
+#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT                                                            0x8
+#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK                                                              0x0000003FL
+#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK                                                              0x00003F00L
+//TRAP12_CONTROL0
+#define TRAP12_CONTROL0__Trap12En__SHIFT                                                                      0x0
+#define TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT                                                            0x18
+#define TRAP12_CONTROL0__Trap12En_MASK                                                                        0x00000001L
+#define TRAP12_CONTROL0__Trap12CrossTrigger_MASK                                                              0x0F000000L
+//TRAP12_ADDRESS_LO
+#define TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT                                                                0x2
+#define TRAP12_ADDRESS_LO__Trap12AddrLo_MASK                                                                  0xFFFFFFFCL
+//TRAP12_ADDRESS_HI
+#define TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT                                                                0x0
+#define TRAP12_ADDRESS_HI__Trap12AddrHi_MASK                                                                  0xFFFFFFFFL
+//TRAP12_COMMAND
+#define TRAP12_COMMAND__Trap12Cmd0__SHIFT                                                                     0x0
+#define TRAP12_COMMAND__Trap12Cmd1__SHIFT                                                                     0x8
+#define TRAP12_COMMAND__Trap12Cmd0_MASK                                                                       0x0000003FL
+#define TRAP12_COMMAND__Trap12Cmd1_MASK                                                                       0x00003F00L
+//TRAP12_ADDRESS_LO_MASK
+#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT                                                       0x2
+#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK                                                         0xFFFFFFFCL
+//TRAP12_ADDRESS_HI_MASK
+#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT                                                       0x0
+#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK                                                         0xFFFFFFFFL
+//TRAP12_COMMAND_MASK
+#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT                                                            0x0
+#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT                                                            0x8
+#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK                                                              0x0000003FL
+#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK                                                              0x00003F00L
+//TRAP13_CONTROL0
+#define TRAP13_CONTROL0__Trap13En__SHIFT                                                                      0x0
+#define TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT                                                            0x18
+#define TRAP13_CONTROL0__Trap13En_MASK                                                                        0x00000001L
+#define TRAP13_CONTROL0__Trap13CrossTrigger_MASK                                                              0x0F000000L
+//TRAP13_ADDRESS_LO
+#define TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT                                                                0x2
+#define TRAP13_ADDRESS_LO__Trap13AddrLo_MASK                                                                  0xFFFFFFFCL
+//TRAP13_ADDRESS_HI
+#define TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT                                                                0x0
+#define TRAP13_ADDRESS_HI__Trap13AddrHi_MASK                                                                  0xFFFFFFFFL
+//TRAP13_COMMAND
+#define TRAP13_COMMAND__Trap13Cmd0__SHIFT                                                                     0x0
+#define TRAP13_COMMAND__Trap13Cmd1__SHIFT                                                                     0x8
+#define TRAP13_COMMAND__Trap13Cmd0_MASK                                                                       0x0000003FL
+#define TRAP13_COMMAND__Trap13Cmd1_MASK                                                                       0x00003F00L
+//TRAP13_ADDRESS_LO_MASK
+#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT                                                       0x2
+#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK                                                         0xFFFFFFFCL
+//TRAP13_ADDRESS_HI_MASK
+#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT                                                       0x0
+#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK                                                         0xFFFFFFFFL
+//TRAP13_COMMAND_MASK
+#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT                                                            0x0
+#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT                                                            0x8
+#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK                                                              0x0000003FL
+#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK                                                              0x00003F00L
+//TRAP14_CONTROL0
+#define TRAP14_CONTROL0__Trap14En__SHIFT                                                                      0x0
+#define TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT                                                            0x18
+#define TRAP14_CONTROL0__Trap14En_MASK                                                                        0x00000001L
+#define TRAP14_CONTROL0__Trap14CrossTrigger_MASK                                                              0x0F000000L
+//TRAP14_ADDRESS_LO
+#define TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT                                                                0x2
+#define TRAP14_ADDRESS_LO__Trap14AddrLo_MASK                                                                  0xFFFFFFFCL
+//TRAP14_ADDRESS_HI
+#define TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT                                                                0x0
+#define TRAP14_ADDRESS_HI__Trap14AddrHi_MASK                                                                  0xFFFFFFFFL
+//TRAP14_COMMAND
+#define TRAP14_COMMAND__Trap14Cmd0__SHIFT                                                                     0x0
+#define TRAP14_COMMAND__Trap14Cmd1__SHIFT                                                                     0x8
+#define TRAP14_COMMAND__Trap14Cmd0_MASK                                                                       0x0000003FL
+#define TRAP14_COMMAND__Trap14Cmd1_MASK                                                                       0x00003F00L
+//TRAP14_ADDRESS_LO_MASK
+#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT                                                       0x2
+#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK                                                         0xFFFFFFFCL
+//TRAP14_ADDRESS_HI_MASK
+#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT                                                       0x0
+#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK                                                         0xFFFFFFFFL
+//TRAP14_COMMAND_MASK
+#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT                                                            0x0
+#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT                                                            0x8
+#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK                                                              0x0000003FL
+#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK                                                              0x00003F00L
+//TRAP15_CONTROL0
+#define TRAP15_CONTROL0__Trap15En__SHIFT                                                                      0x0
+#define TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT                                                            0x18
+#define TRAP15_CONTROL0__Trap15En_MASK                                                                        0x00000001L
+#define TRAP15_CONTROL0__Trap15CrossTrigger_MASK                                                              0x0F000000L
+//TRAP15_ADDRESS_LO
+#define TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT                                                                0x2
+#define TRAP15_ADDRESS_LO__Trap15AddrLo_MASK                                                                  0xFFFFFFFCL
+//TRAP15_ADDRESS_HI
+#define TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT                                                                0x0
+#define TRAP15_ADDRESS_HI__Trap15AddrHi_MASK                                                                  0xFFFFFFFFL
+//TRAP15_COMMAND
+#define TRAP15_COMMAND__Trap15Cmd0__SHIFT                                                                     0x0
+#define TRAP15_COMMAND__Trap15Cmd1__SHIFT                                                                     0x8
+#define TRAP15_COMMAND__Trap15Cmd0_MASK                                                                       0x0000003FL
+#define TRAP15_COMMAND__Trap15Cmd1_MASK                                                                       0x00003F00L
+//TRAP15_ADDRESS_LO_MASK
+#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT                                                       0x2
+#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK                                                         0xFFFFFFFCL
+//TRAP15_ADDRESS_HI_MASK
+#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT                                                       0x0
+#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK                                                         0xFFFFFFFFL
+//TRAP15_COMMAND_MASK
+#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT                                                            0x0
+#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT                                                            0x8
+#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK                                                              0x0000003FL
+#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK                                                              0x00003F00L
+//SB_COMMAND
+#define SB_COMMAND__IO_ACCESS_EN__SHIFT                                                                       0x0
+#define SB_COMMAND__MEM_ACCESS_EN__SHIFT                                                                      0x1
+#define SB_COMMAND__BUS_MASTER_EN__SHIFT                                                                      0x2
+#define SB_COMMAND__IO_ACCESS_EN_MASK                                                                         0x0001L
+#define SB_COMMAND__MEM_ACCESS_EN_MASK                                                                        0x0002L
+#define SB_COMMAND__BUS_MASTER_EN_MASK                                                                        0x0004L
+//SB_SUB_BUS_NUMBER_LATENCY
+#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                       0x8
+#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                         0x10
+#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                         0x0000FF00L
+#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                           0x00FF0000L
+//SB_IO_BASE_LIMIT
+#define SB_IO_BASE_LIMIT__IO_BASE__SHIFT                                                                      0x4
+#define SB_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                                     0xc
+#define SB_IO_BASE_LIMIT__IO_BASE_MASK                                                                        0x00F0L
+#define SB_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                       0xF000L
+//SB_MEM_BASE_LIMIT
+#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                              0x4
+#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                             0x14
+#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                                0x0000FFF0L
+#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                               0xFFF00000L
+//SB_PREF_BASE_LIMIT
+#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                        0x4
+#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                       0x14
+#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                          0x0000FFF0L
+#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                         0xFFF00000L
+//SB_PREF_BASE_UPPER
+#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                            0x0
+#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                              0xFFFFFFFFL
+//SB_PREF_LIMIT_UPPER
+#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                          0x0
+#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                            0xFFFFFFFFL
+//SB_IO_BASE_LIMIT_HI
+#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                             0x0
+#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                            0x10
+#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                               0x0000FFFFL
+#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                              0xFFFF0000L
+//SB_IRQ_BRIDGE_CNTL
+#define SB_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                                     0x2
+#define SB_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                                     0x3
+#define SB_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                                    0x4
+#define SB_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                       0x0004L
+#define SB_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                       0x0008L
+#define SB_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                                      0x0010L
+//SB_EXT_BRIDGE_CNTL
+#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                              0x0
+#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                                0x01L
+//SB_PMI_STATUS_CNTL
+#define SB_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                                0x0
+#define SB_PMI_STATUS_CNTL__POWER_STATE_MASK                                                                  0x03L
+//SB_SLOT_CAP
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                              0x7
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                              0xf
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                                0x00007F80L
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                                0x00018000L
+//SB_ROOT_CNTL
+#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                       0x4
+#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                         0x0010L
+//SB_DEVICE_CNTL2
+#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                             0x5
+#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                               0x0020L
+//MCA_SMN_INT_REQ_ADDR
+#define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR__SHIFT                                                         0x0
+#define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR_MASK                                                           0x000FFFFFL
+//MCA_SMN_INT_MCM_ADDR
+#define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR__SHIFT                                                         0x0
+#define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR_MASK                                                           0x0000000FL
+//MCA_SMN_INT_APERTUREID
+#define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID__SHIFT                                                     0x0
+#define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID_MASK                                                       0x00000FFFL
+//MCA_SMN_INT_CONTROL
+#define MCA_SMN_INT_CONTROL__MCACrossTrigger__SHIFT                                                           0x0
+#define MCA_SMN_INT_CONTROL__MCACrossTrigger_MASK                                                             0x0000000FL
+
+
+// addressBlock: nbio_iohub_mca_iohc_mca_map
+
+
+// addressBlock: nbio_iohub_nb_security_security_cfgdec
+
+
+// addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec
+//PARITY_CONTROL_0
+#define PARITY_CONTROL_0__ParityCorrThreshold__SHIFT                                                          0x0
+#define PARITY_CONTROL_0__ParityUCPThreshold__SHIFT                                                           0x10
+#define PARITY_CONTROL_0__ParityCorrThreshold_MASK                                                            0x0000FFFFL
+#define PARITY_CONTROL_0__ParityUCPThreshold_MASK                                                             0xFFFF0000L
+//PARITY_CONTROL_1
+#define PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT                                                         0x0
+#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT                                                     0x8
+#define PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT                                                            0xb
+#define PARITY_CONTROL_1__ParityErrGenCmd__SHIFT                                                              0x10
+#define PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT                                                          0x1e
+#define PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT                                                      0x1f
+#define PARITY_CONTROL_1__ParityErrGenGroupSel_MASK                                                           0x000000FFL
+#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK                                                       0x00000100L
+#define PARITY_CONTROL_1__ParityErrGenIdSel_MASK                                                              0x0000F800L
+#define PARITY_CONTROL_1__ParityErrGenCmd_MASK                                                                0x000F0000L
+#define PARITY_CONTROL_1__ParityErrGenTrigger_MASK                                                            0x40000000L
+#define PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK                                                        0x80000000L
+//PARITY_SEVERITY_CONTROL_UNCORR_0
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT                                       0x0
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT                                       0x2
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT                                       0x4
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT                                       0x6
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT                                       0x8
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5__SHIFT                                       0xa
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6__SHIFT                                       0xc
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7__SHIFT                                       0xe
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK                                         0x00000003L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK                                         0x0000000CL
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK                                         0x00000030L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK                                         0x000000C0L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK                                         0x00000300L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5_MASK                                         0x00000C00L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6_MASK                                         0x00003000L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7_MASK                                         0x0000C000L
+//PARITY_SEVERITY_CONTROL_CORR_0
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT                                           0x0
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT                                           0x2
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT                                           0x4
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT                                           0x6
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT                                           0x8
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5__SHIFT                                           0xa
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6__SHIFT                                           0xc
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7__SHIFT                                           0xe
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK                                             0x00000003L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK                                             0x0000000CL
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK                                             0x00000030L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK                                             0x000000C0L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK                                             0x00000300L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5_MASK                                             0x00000C00L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6_MASK                                             0x00003000L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7_MASK                                             0x0000C000L
+//PARITY_SEVERITY_CONTROL_UCP_0
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT                                             0x0
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT                                             0x2
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT                                             0x4
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT                                             0x6
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT                                             0x8
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5__SHIFT                                             0xa
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6__SHIFT                                             0xc
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7__SHIFT                                             0xe
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK                                               0x00000003L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK                                               0x0000000CL
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK                                               0x00000030L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK                                               0x000000C0L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK                                               0x00000300L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5_MASK                                               0x00000C00L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6_MASK                                               0x00003000L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7_MASK                                               0x0000C000L
+//RAS_GLOBAL_STATUS_LO
+#define RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT                                                            0x0
+#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT                                                        0x1
+#define RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT                                                           0x2
+#define RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT                                                            0x3
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT                                                               0x6
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT                                                               0x7
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT                                                               0x8
+#define RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT                                                                   0x9
+#define RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT                                                                   0xa
+#define RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT                                                                   0xb
+#define RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT                                                                 0xc
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT                                                             0xd
+#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT                                                          0xe
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT                                                     0xf
+#define RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK                                                              0x00000001L
+#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK                                                          0x00000002L
+#define RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK                                                             0x00000004L
+#define RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK                                                              0x00000008L
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK                                                                 0x00000040L
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK                                                                 0x00000080L
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK                                                                 0x00000100L
+#define RAS_GLOBAL_STATUS_LO__SW_SMI_MASK                                                                     0x00000200L
+#define RAS_GLOBAL_STATUS_LO__SW_SCI_MASK                                                                     0x00000400L
+#define RAS_GLOBAL_STATUS_LO__SW_NMI_MASK                                                                     0x00000800L
+#define RAS_GLOBAL_STATUS_LO__APML_NMI_MASK                                                                   0x00001000L
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK                                                               0x00002000L
+#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK                                                            0x00004000L
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK                                                       0x00008000L
+//RAS_GLOBAL_STATUS_HI
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT                                                            0x0
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr__SHIFT                                                            0x1
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr__SHIFT                                                            0x2
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr__SHIFT                                                            0x3
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr__SHIFT                                                            0x4
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr__SHIFT                                                            0x5
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr__SHIFT                                                            0x6
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr__SHIFT                                                            0x7
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortBErr__SHIFT                                                            0x8
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortCErr__SHIFT                                                            0x9
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK                                                              0x00000001L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr_MASK                                                              0x00000002L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr_MASK                                                              0x00000004L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr_MASK                                                              0x00000008L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr_MASK                                                              0x00000010L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr_MASK                                                              0x00000020L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr_MASK                                                              0x00000040L
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr_MASK                                                              0x00000080L
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortBErr_MASK                                                              0x00000100L
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortCErr_MASK                                                              0x00000200L
+//PARITY_ERROR_STATUS_UNCORR_GRP0
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT                                         0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT                                         0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT                                         0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT                                         0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT                                         0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT                                         0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT                                         0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT                                         0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT                                         0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT                                         0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT                                        0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT                                        0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT                                        0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT                                        0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT                                        0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT                                        0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT                                        0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT                                        0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT                                        0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT                                        0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT                                        0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT                                        0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT                                        0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT                                        0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT                                        0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT                                        0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT                                        0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT                                        0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT                                        0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT                                        0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT                                        0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT                                        0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK                                           0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK                                           0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK                                           0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK                                           0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK                                           0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK                                           0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK                                           0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK                                           0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK                                           0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK                                           0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK                                          0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK                                          0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK                                          0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK                                          0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK                                          0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK                                          0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK                                          0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK                                          0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK                                          0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK                                          0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK                                          0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK                                          0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK                                          0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK                                          0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK                                          0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK                                          0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK                                          0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK                                          0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK                                          0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK                                          0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK                                          0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK                                          0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP1
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT                                         0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT                                         0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT                                         0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT                                         0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT                                         0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT                                         0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT                                         0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT                                         0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT                                         0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT                                         0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT                                        0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT                                        0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT                                        0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT                                        0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT                                        0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT                                        0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT                                        0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT                                        0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT                                        0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT                                        0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT                                        0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT                                        0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT                                        0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT                                        0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT                                        0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT                                        0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT                                        0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT                                        0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT                                        0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT                                        0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT                                        0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT                                        0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK                                           0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK                                           0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK                                           0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK                                           0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK                                           0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK                                           0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK                                           0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK                                           0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK                                           0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK                                           0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK                                          0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK                                          0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK                                          0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK                                          0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK                                          0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK                                          0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK                                          0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK                                          0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK                                          0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK                                          0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK                                          0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK                                          0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK                                          0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK                                          0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK                                          0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK                                          0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK                                          0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK                                          0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK                                          0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK                                          0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK                                          0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK                                          0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP2
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT                                         0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT                                         0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT                                         0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT                                         0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT                                         0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT                                         0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT                                         0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT                                         0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT                                         0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT                                         0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT                                        0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT                                        0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT                                        0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT                                        0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT                                        0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT                                        0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT                                        0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT                                        0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT                                        0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT                                        0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT                                        0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT                                        0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT                                        0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT                                        0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT                                        0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT                                        0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT                                        0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT                                        0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT                                        0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT                                        0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT                                        0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT                                        0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK                                           0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK                                           0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK                                           0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK                                           0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK                                           0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK                                           0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK                                           0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK                                           0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK                                           0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK                                           0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK                                          0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK                                          0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK                                          0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK                                          0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK                                          0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK                                          0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK                                          0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK                                          0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK                                          0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK                                          0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK                                          0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK                                          0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK                                          0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK                                          0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK                                          0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK                                          0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK                                          0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK                                          0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK                                          0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK                                          0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK                                          0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK                                          0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP3
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT                                         0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT                                         0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT                                         0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT                                         0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT                                         0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT                                         0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT                                         0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT                                         0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT                                         0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT                                         0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT                                        0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT                                        0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT                                        0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT                                        0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT                                        0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT                                        0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT                                        0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT                                        0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT                                        0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT                                        0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT                                        0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT                                        0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT                                        0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT                                        0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT                                        0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT                                        0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT                                        0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT                                        0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT                                        0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT                                        0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT                                        0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT                                        0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK                                           0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK                                           0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK                                           0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK                                           0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK                                           0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK                                           0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK                                           0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK                                           0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK                                           0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK                                           0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK                                          0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK                                          0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK                                          0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK                                          0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK                                          0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK                                          0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK                                          0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK                                          0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK                                          0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK                                          0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK                                          0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK                                          0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK                                          0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK                                          0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK                                          0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK                                          0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK                                          0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK                                          0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK                                          0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK                                          0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK                                          0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK                                          0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP4
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT                                         0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT                                         0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT                                         0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT                                         0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT                                         0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT                                         0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT                                         0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT                                         0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT                                         0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT                                         0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT                                        0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT                                        0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT                                        0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT                                        0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT                                        0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT                                        0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT                                        0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT                                        0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT                                        0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT                                        0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT                                        0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT                                        0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT                                        0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT                                        0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT                                        0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT                                        0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT                                        0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT                                        0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT                                        0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT                                        0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT                                        0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT                                        0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK                                           0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK                                           0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK                                           0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK                                           0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK                                           0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK                                           0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK                                           0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK                                           0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK                                           0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK                                           0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK                                          0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK                                          0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK                                          0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK                                          0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK                                          0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK                                          0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK                                          0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK                                          0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK                                          0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK                                          0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK                                          0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK                                          0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK                                          0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK                                          0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK                                          0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK                                          0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK                                          0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK                                          0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK                                          0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK                                          0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK                                          0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK                                          0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP5
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0__SHIFT                                         0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1__SHIFT                                         0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2__SHIFT                                         0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3__SHIFT                                         0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4__SHIFT                                         0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5__SHIFT                                         0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6__SHIFT                                         0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7__SHIFT                                         0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8__SHIFT                                         0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9__SHIFT                                         0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10__SHIFT                                        0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11__SHIFT                                        0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12__SHIFT                                        0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13__SHIFT                                        0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14__SHIFT                                        0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15__SHIFT                                        0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16__SHIFT                                        0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17__SHIFT                                        0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18__SHIFT                                        0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19__SHIFT                                        0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20__SHIFT                                        0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21__SHIFT                                        0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22__SHIFT                                        0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23__SHIFT                                        0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24__SHIFT                                        0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25__SHIFT                                        0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26__SHIFT                                        0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27__SHIFT                                        0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28__SHIFT                                        0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29__SHIFT                                        0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30__SHIFT                                        0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31__SHIFT                                        0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0_MASK                                           0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1_MASK                                           0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2_MASK                                           0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3_MASK                                           0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4_MASK                                           0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5_MASK                                           0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6_MASK                                           0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7_MASK                                           0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8_MASK                                           0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9_MASK                                           0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10_MASK                                          0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11_MASK                                          0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12_MASK                                          0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13_MASK                                          0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14_MASK                                          0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15_MASK                                          0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16_MASK                                          0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17_MASK                                          0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18_MASK                                          0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19_MASK                                          0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20_MASK                                          0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21_MASK                                          0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22_MASK                                          0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23_MASK                                          0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24_MASK                                          0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25_MASK                                          0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26_MASK                                          0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27_MASK                                          0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28_MASK                                          0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29_MASK                                          0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30_MASK                                          0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31_MASK                                          0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP6
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0__SHIFT                                         0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1__SHIFT                                         0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2__SHIFT                                         0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3__SHIFT                                         0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4__SHIFT                                         0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5__SHIFT                                         0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6__SHIFT                                         0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7__SHIFT                                         0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8__SHIFT                                         0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9__SHIFT                                         0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10__SHIFT                                        0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11__SHIFT                                        0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12__SHIFT                                        0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13__SHIFT                                        0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14__SHIFT                                        0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15__SHIFT                                        0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16__SHIFT                                        0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17__SHIFT                                        0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18__SHIFT                                        0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19__SHIFT                                        0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20__SHIFT                                        0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21__SHIFT                                        0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22__SHIFT                                        0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23__SHIFT                                        0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24__SHIFT                                        0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25__SHIFT                                        0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26__SHIFT                                        0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27__SHIFT                                        0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28__SHIFT                                        0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29__SHIFT                                        0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30__SHIFT                                        0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31__SHIFT                                        0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0_MASK                                           0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1_MASK                                           0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2_MASK                                           0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3_MASK                                           0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4_MASK                                           0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5_MASK                                           0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6_MASK                                           0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7_MASK                                           0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8_MASK                                           0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9_MASK                                           0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10_MASK                                          0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11_MASK                                          0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12_MASK                                          0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13_MASK                                          0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14_MASK                                          0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15_MASK                                          0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16_MASK                                          0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17_MASK                                          0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18_MASK                                          0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19_MASK                                          0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20_MASK                                          0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21_MASK                                          0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22_MASK                                          0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23_MASK                                          0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24_MASK                                          0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25_MASK                                          0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26_MASK                                          0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27_MASK                                          0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28_MASK                                          0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29_MASK                                          0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30_MASK                                          0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31_MASK                                          0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP7
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0__SHIFT                                         0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1__SHIFT                                         0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2__SHIFT                                         0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3__SHIFT                                         0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4__SHIFT                                         0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5__SHIFT                                         0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6__SHIFT                                         0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7__SHIFT                                         0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8__SHIFT                                         0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9__SHIFT                                         0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10__SHIFT                                        0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11__SHIFT                                        0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12__SHIFT                                        0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13__SHIFT                                        0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14__SHIFT                                        0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15__SHIFT                                        0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16__SHIFT                                        0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17__SHIFT                                        0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18__SHIFT                                        0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19__SHIFT                                        0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20__SHIFT                                        0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21__SHIFT                                        0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22__SHIFT                                        0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23__SHIFT                                        0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24__SHIFT                                        0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25__SHIFT                                        0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26__SHIFT                                        0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27__SHIFT                                        0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28__SHIFT                                        0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29__SHIFT                                        0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30__SHIFT                                        0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31__SHIFT                                        0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0_MASK                                           0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1_MASK                                           0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2_MASK                                           0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3_MASK                                           0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4_MASK                                           0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5_MASK                                           0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6_MASK                                           0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7_MASK                                           0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8_MASK                                           0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9_MASK                                           0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10_MASK                                          0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11_MASK                                          0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12_MASK                                          0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13_MASK                                          0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14_MASK                                          0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15_MASK                                          0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16_MASK                                          0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17_MASK                                          0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18_MASK                                          0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19_MASK                                          0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20_MASK                                          0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21_MASK                                          0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22_MASK                                          0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23_MASK                                          0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24_MASK                                          0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25_MASK                                          0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26_MASK                                          0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27_MASK                                          0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28_MASK                                          0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29_MASK                                          0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30_MASK                                          0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31_MASK                                          0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP0
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT                                           0x0
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT                                           0x1
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT                                           0x2
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT                                           0x3
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT                                           0x4
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT                                           0x5
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT                                           0x6
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT                                           0x7
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT                                           0x8
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT                                           0x9
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT                                          0xa
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT                                          0xb
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT                                          0xc
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT                                          0xd
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT                                          0xe
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT                                          0xf
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT                                          0x10
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT                                          0x11
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT                                          0x12
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT                                          0x13
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT                                          0x14
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT                                          0x15
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT                                          0x16
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT                                          0x17
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT                                          0x18
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT                                          0x19
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT                                          0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT                                          0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT                                          0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT                                          0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT                                          0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT                                          0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK                                             0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK                                             0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK                                             0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK                                             0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK                                             0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK                                             0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK                                             0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK                                             0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK                                             0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK                                             0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK                                            0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK                                            0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK                                            0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK                                            0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK                                            0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK                                            0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK                                            0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK                                            0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK                                            0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK                                            0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK                                            0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK                                            0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK                                            0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK                                            0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK                                            0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK                                            0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK                                            0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK                                            0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK                                            0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK                                            0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK                                            0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK                                            0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP1
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT                                           0x0
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT                                           0x1
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT                                           0x2
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT                                           0x3
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT                                           0x4
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT                                           0x5
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT                                           0x6
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT                                           0x7
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT                                           0x8
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT                                           0x9
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT                                          0xa
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT                                          0xb
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT                                          0xc
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT                                          0xd
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT                                          0xe
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT                                          0xf
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT                                          0x10
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT                                          0x11
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT                                          0x12
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT                                          0x13
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT                                          0x14
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT                                          0x15
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT                                          0x16
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT                                          0x17
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT                                          0x18
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT                                          0x19
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT                                          0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT                                          0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT                                          0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT                                          0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT                                          0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT                                          0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK                                             0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK                                             0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK                                             0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK                                             0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK                                             0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK                                             0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK                                             0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK                                             0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK                                             0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK                                             0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK                                            0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK                                            0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK                                            0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK                                            0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK                                            0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK                                            0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK                                            0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK                                            0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK                                            0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK                                            0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK                                            0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK                                            0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK                                            0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK                                            0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK                                            0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK                                            0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK                                            0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK                                            0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK                                            0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK                                            0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK                                            0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK                                            0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP2
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT                                           0x0
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT                                           0x1
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT                                           0x2
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT                                           0x3
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT                                           0x4
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT                                           0x5
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT                                           0x6
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT                                           0x7
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT                                           0x8
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT                                           0x9
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT                                          0xa
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT                                          0xb
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT                                          0xc
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT                                          0xd
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT                                          0xe
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT                                          0xf
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT                                          0x10
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT                                          0x11
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT                                          0x12
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT                                          0x13
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT                                          0x14
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT                                          0x15
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT                                          0x16
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT                                          0x17
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT                                          0x18
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT                                          0x19
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT                                          0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT                                          0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT                                          0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT                                          0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT                                          0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT                                          0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK                                             0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK                                             0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK                                             0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK                                             0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK                                             0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK                                             0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK                                             0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK                                             0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK                                             0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK                                             0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK                                            0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK                                            0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK                                            0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK                                            0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK                                            0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK                                            0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK                                            0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK                                            0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK                                            0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK                                            0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK                                            0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK                                            0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK                                            0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK                                            0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK                                            0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK                                            0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK                                            0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK                                            0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK                                            0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK                                            0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK                                            0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK                                            0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP3
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT                                           0x0
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT                                           0x1
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT                                           0x2
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT                                           0x3
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT                                           0x4
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT                                           0x5
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT                                           0x6
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT                                           0x7
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT                                           0x8
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT                                           0x9
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT                                          0xa
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT                                          0xb
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT                                          0xc
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT                                          0xd
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT                                          0xe
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT                                          0xf
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT                                          0x10
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT                                          0x11
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT                                          0x12
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT                                          0x13
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT                                          0x14
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT                                          0x15
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT                                          0x16
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT                                          0x17
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT                                          0x18
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT                                          0x19
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT                                          0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT                                          0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT                                          0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT                                          0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT                                          0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT                                          0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK                                             0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK                                             0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK                                             0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK                                             0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK                                             0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK                                             0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK                                             0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK                                             0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK                                             0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK                                             0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK                                            0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK                                            0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK                                            0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK                                            0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK                                            0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK                                            0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK                                            0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK                                            0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK                                            0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK                                            0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK                                            0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK                                            0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK                                            0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK                                            0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK                                            0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK                                            0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK                                            0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK                                            0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK                                            0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK                                            0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK                                            0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK                                            0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP4
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT                                           0x0
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT                                           0x1
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT                                           0x2
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT                                           0x3
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT                                           0x4
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT                                           0x5
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT                                           0x6
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT                                           0x7
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT                                           0x8
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT                                           0x9
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT                                          0xa
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT                                          0xb
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT                                          0xc
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT                                          0xd
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT                                          0xe
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT                                          0xf
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT                                          0x10
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT                                          0x11
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT                                          0x12
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT                                          0x13
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT                                          0x14
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT                                          0x15
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT                                          0x16
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT                                          0x17
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT                                          0x18
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT                                          0x19
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT                                          0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT                                          0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT                                          0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT                                          0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT                                          0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT                                          0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK                                             0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK                                             0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK                                             0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK                                             0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK                                             0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK                                             0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK                                             0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK                                             0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK                                             0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK                                             0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK                                            0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK                                            0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK                                            0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK                                            0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK                                            0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK                                            0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK                                            0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK                                            0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK                                            0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK                                            0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK                                            0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK                                            0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK                                            0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK                                            0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK                                            0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK                                            0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK                                            0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK                                            0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK                                            0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK                                            0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK                                            0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK                                            0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP5
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0__SHIFT                                           0x0
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1__SHIFT                                           0x1
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2__SHIFT                                           0x2
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3__SHIFT                                           0x3
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4__SHIFT                                           0x4
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5__SHIFT                                           0x5
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6__SHIFT                                           0x6
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7__SHIFT                                           0x7
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8__SHIFT                                           0x8
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9__SHIFT                                           0x9
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10__SHIFT                                          0xa
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11__SHIFT                                          0xb
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12__SHIFT                                          0xc
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13__SHIFT                                          0xd
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14__SHIFT                                          0xe
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15__SHIFT                                          0xf
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16__SHIFT                                          0x10
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17__SHIFT                                          0x11
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18__SHIFT                                          0x12
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19__SHIFT                                          0x13
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20__SHIFT                                          0x14
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21__SHIFT                                          0x15
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22__SHIFT                                          0x16
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23__SHIFT                                          0x17
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24__SHIFT                                          0x18
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25__SHIFT                                          0x19
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26__SHIFT                                          0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27__SHIFT                                          0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28__SHIFT                                          0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29__SHIFT                                          0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30__SHIFT                                          0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31__SHIFT                                          0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0_MASK                                             0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1_MASK                                             0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2_MASK                                             0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3_MASK                                             0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4_MASK                                             0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5_MASK                                             0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6_MASK                                             0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7_MASK                                             0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8_MASK                                             0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9_MASK                                             0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10_MASK                                            0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11_MASK                                            0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12_MASK                                            0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13_MASK                                            0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14_MASK                                            0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15_MASK                                            0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16_MASK                                            0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17_MASK                                            0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18_MASK                                            0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19_MASK                                            0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20_MASK                                            0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21_MASK                                            0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22_MASK                                            0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23_MASK                                            0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24_MASK                                            0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25_MASK                                            0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26_MASK                                            0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27_MASK                                            0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28_MASK                                            0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29_MASK                                            0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30_MASK                                            0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31_MASK                                            0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP6
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0__SHIFT                                           0x0
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1__SHIFT                                           0x1
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2__SHIFT                                           0x2
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3__SHIFT                                           0x3
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4__SHIFT                                           0x4
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5__SHIFT                                           0x5
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6__SHIFT                                           0x6
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7__SHIFT                                           0x7
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8__SHIFT                                           0x8
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9__SHIFT                                           0x9
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10__SHIFT                                          0xa
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11__SHIFT                                          0xb
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12__SHIFT                                          0xc
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13__SHIFT                                          0xd
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14__SHIFT                                          0xe
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15__SHIFT                                          0xf
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16__SHIFT                                          0x10
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17__SHIFT                                          0x11
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18__SHIFT                                          0x12
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19__SHIFT                                          0x13
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20__SHIFT                                          0x14
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21__SHIFT                                          0x15
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22__SHIFT                                          0x16
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23__SHIFT                                          0x17
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24__SHIFT                                          0x18
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25__SHIFT                                          0x19
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26__SHIFT                                          0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27__SHIFT                                          0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28__SHIFT                                          0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29__SHIFT                                          0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30__SHIFT                                          0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31__SHIFT                                          0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0_MASK                                             0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1_MASK                                             0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2_MASK                                             0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3_MASK                                             0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4_MASK                                             0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5_MASK                                             0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6_MASK                                             0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7_MASK                                             0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8_MASK                                             0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9_MASK                                             0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10_MASK                                            0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11_MASK                                            0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12_MASK                                            0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13_MASK                                            0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14_MASK                                            0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15_MASK                                            0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16_MASK                                            0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17_MASK                                            0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18_MASK                                            0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19_MASK                                            0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20_MASK                                            0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21_MASK                                            0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22_MASK                                            0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23_MASK                                            0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24_MASK                                            0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25_MASK                                            0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26_MASK                                            0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27_MASK                                            0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28_MASK                                            0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29_MASK                                            0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30_MASK                                            0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31_MASK                                            0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP7
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0__SHIFT                                           0x0
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1__SHIFT                                           0x1
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2__SHIFT                                           0x2
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3__SHIFT                                           0x3
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4__SHIFT                                           0x4
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5__SHIFT                                           0x5
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6__SHIFT                                           0x6
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7__SHIFT                                           0x7
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8__SHIFT                                           0x8
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9__SHIFT                                           0x9
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10__SHIFT                                          0xa
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11__SHIFT                                          0xb
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12__SHIFT                                          0xc
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13__SHIFT                                          0xd
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14__SHIFT                                          0xe
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15__SHIFT                                          0xf
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16__SHIFT                                          0x10
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17__SHIFT                                          0x11
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18__SHIFT                                          0x12
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19__SHIFT                                          0x13
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20__SHIFT                                          0x14
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21__SHIFT                                          0x15
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22__SHIFT                                          0x16
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23__SHIFT                                          0x17
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24__SHIFT                                          0x18
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25__SHIFT                                          0x19
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26__SHIFT                                          0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27__SHIFT                                          0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28__SHIFT                                          0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29__SHIFT                                          0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30__SHIFT                                          0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31__SHIFT                                          0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0_MASK                                             0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1_MASK                                             0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2_MASK                                             0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3_MASK                                             0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4_MASK                                             0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5_MASK                                             0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6_MASK                                             0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7_MASK                                             0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8_MASK                                             0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9_MASK                                             0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10_MASK                                            0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11_MASK                                            0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12_MASK                                            0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13_MASK                                            0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14_MASK                                            0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15_MASK                                            0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16_MASK                                            0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17_MASK                                            0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18_MASK                                            0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19_MASK                                            0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20_MASK                                            0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21_MASK                                            0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22_MASK                                            0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23_MASK                                            0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24_MASK                                            0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25_MASK                                            0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26_MASK                                            0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27_MASK                                            0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28_MASK                                            0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29_MASK                                            0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30_MASK                                            0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31_MASK                                            0x80000000L
+//PARITY_COUNTER_CORR_GRP0
+#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT                                                     0x0
+#define PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT                                                              0x1f
+#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK                                                       0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP0__ResetEn_MASK                                                                0x80000000L
+//PARITY_COUNTER_CORR_GRP1
+#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT                                                     0x0
+#define PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT                                                              0x1f
+#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK                                                       0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP1__ResetEn_MASK                                                                0x80000000L
+//PARITY_COUNTER_CORR_GRP2
+#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT                                                     0x0
+#define PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT                                                              0x1f
+#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK                                                       0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP2__ResetEn_MASK                                                                0x80000000L
+//PARITY_COUNTER_CORR_GRP3
+#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT                                                     0x0
+#define PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT                                                              0x1f
+#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK                                                       0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP3__ResetEn_MASK                                                                0x80000000L
+//PARITY_COUNTER_CORR_GRP4
+#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT                                                     0x0
+#define PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT                                                              0x1f
+#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK                                                       0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP4__ResetEn_MASK                                                                0x80000000L
+//PARITY_COUNTER_CORR_GRP5
+#define PARITY_COUNTER_CORR_GRP5__ThresholdCounter__SHIFT                                                     0x0
+#define PARITY_COUNTER_CORR_GRP5__ResetEn__SHIFT                                                              0x1f
+#define PARITY_COUNTER_CORR_GRP5__ThresholdCounter_MASK                                                       0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP5__ResetEn_MASK                                                                0x80000000L
+//PARITY_COUNTER_CORR_GRP6
+#define PARITY_COUNTER_CORR_GRP6__ThresholdCounter__SHIFT                                                     0x0
+#define PARITY_COUNTER_CORR_GRP6__ResetEn__SHIFT                                                              0x1f
+#define PARITY_COUNTER_CORR_GRP6__ThresholdCounter_MASK                                                       0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP6__ResetEn_MASK                                                                0x80000000L
+//PARITY_COUNTER_CORR_GRP7
+#define PARITY_COUNTER_CORR_GRP7__ThresholdCounter__SHIFT                                                     0x0
+#define PARITY_COUNTER_CORR_GRP7__ResetEn__SHIFT                                                              0x1f
+#define PARITY_COUNTER_CORR_GRP7__ThresholdCounter_MASK                                                       0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP7__ResetEn_MASK                                                                0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP0
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT                                            0x0
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT                                            0x1
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT                                            0x2
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT                                            0x3
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT                                            0x4
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT                                            0x5
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT                                            0x6
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT                                            0x7
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT                                            0x8
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT                                            0x9
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT                                           0xa
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT                                           0xb
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT                                           0xc
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT                                           0xd
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT                                           0xe
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT                                           0xf
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT                                           0x10
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT                                           0x11
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT                                           0x12
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT                                           0x13
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT                                           0x14
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT                                           0x15
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT                                           0x16
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT                                           0x17
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT                                           0x18
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT                                           0x19
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT                                           0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT                                           0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT                                           0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT                                           0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT                                           0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT                                           0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK                                              0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK                                              0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK                                              0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK                                              0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK                                              0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK                                              0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK                                              0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK                                              0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK                                              0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK                                              0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK                                             0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK                                             0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK                                             0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK                                             0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK                                             0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK                                             0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK                                             0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK                                             0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK                                             0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK                                             0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK                                             0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK                                             0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK                                             0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK                                             0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK                                             0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK                                             0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK                                             0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK                                             0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK                                             0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK                                             0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK                                             0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK                                             0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP1
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT                                            0x0
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT                                            0x1
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT                                            0x2
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT                                            0x3
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT                                            0x4
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT                                            0x5
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT                                            0x6
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT                                            0x7
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT                                            0x8
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT                                            0x9
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT                                           0xa
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT                                           0xb
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT                                           0xc
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT                                           0xd
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT                                           0xe
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT                                           0xf
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT                                           0x10
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT                                           0x11
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT                                           0x12
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT                                           0x13
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT                                           0x14
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT                                           0x15
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT                                           0x16
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT                                           0x17
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT                                           0x18
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT                                           0x19
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT                                           0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT                                           0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT                                           0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT                                           0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT                                           0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT                                           0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK                                              0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK                                              0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK                                              0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK                                              0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK                                              0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK                                              0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK                                              0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK                                              0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK                                              0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK                                              0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK                                             0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK                                             0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK                                             0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK                                             0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK                                             0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK                                             0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK                                             0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK                                             0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK                                             0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK                                             0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK                                             0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK                                             0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK                                             0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK                                             0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK                                             0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK                                             0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK                                             0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK                                             0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK                                             0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK                                             0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK                                             0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK                                             0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP2
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT                                            0x0
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT                                            0x1
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT                                            0x2
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT                                            0x3
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT                                            0x4
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT                                            0x5
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT                                            0x6
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT                                            0x7
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT                                            0x8
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT                                            0x9
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT                                           0xa
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT                                           0xb
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT                                           0xc
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT                                           0xd
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT                                           0xe
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT                                           0xf
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT                                           0x10
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT                                           0x11
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT                                           0x12
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT                                           0x13
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT                                           0x14
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT                                           0x15
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT                                           0x16
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT                                           0x17
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT                                           0x18
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT                                           0x19
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT                                           0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT                                           0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT                                           0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT                                           0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT                                           0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT                                           0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK                                              0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK                                              0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK                                              0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK                                              0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK                                              0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK                                              0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK                                              0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK                                              0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK                                              0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK                                              0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK                                             0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK                                             0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK                                             0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK                                             0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK                                             0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK                                             0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK                                             0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK                                             0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK                                             0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK                                             0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK                                             0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK                                             0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK                                             0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK                                             0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK                                             0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK                                             0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK                                             0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK                                             0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK                                             0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK                                             0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK                                             0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK                                             0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP3
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT                                            0x0
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT                                            0x1
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT                                            0x2
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT                                            0x3
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT                                            0x4
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT                                            0x5
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT                                            0x6
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT                                            0x7
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT                                            0x8
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT                                            0x9
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT                                           0xa
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT                                           0xb
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT                                           0xc
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT                                           0xd
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT                                           0xe
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT                                           0xf
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT                                           0x10
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT                                           0x11
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT                                           0x12
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT                                           0x13
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT                                           0x14
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT                                           0x15
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT                                           0x16
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT                                           0x17
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT                                           0x18
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT                                           0x19
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT                                           0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT                                           0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT                                           0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT                                           0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT                                           0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT                                           0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK                                              0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK                                              0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK                                              0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK                                              0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK                                              0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK                                              0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK                                              0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK                                              0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK                                              0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK                                              0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK                                             0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK                                             0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK                                             0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK                                             0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK                                             0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK                                             0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK                                             0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK                                             0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK                                             0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK                                             0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK                                             0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK                                             0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK                                             0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK                                             0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK                                             0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK                                             0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK                                             0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK                                             0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK                                             0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK                                             0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK                                             0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK                                             0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP4
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT                                            0x0
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT                                            0x1
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT                                            0x2
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT                                            0x3
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT                                            0x4
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT                                            0x5
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT                                            0x6
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT                                            0x7
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT                                            0x8
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT                                            0x9
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT                                           0xa
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT                                           0xb
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT                                           0xc
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT                                           0xd
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT                                           0xe
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT                                           0xf
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT                                           0x10
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT                                           0x11
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT                                           0x12
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT                                           0x13
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT                                           0x14
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT                                           0x15
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT                                           0x16
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT                                           0x17
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT                                           0x18
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT                                           0x19
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT                                           0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT                                           0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT                                           0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT                                           0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT                                           0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT                                           0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK                                              0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK                                              0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK                                              0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK                                              0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK                                              0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK                                              0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK                                              0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK                                              0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK                                              0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK                                              0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK                                             0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK                                             0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK                                             0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK                                             0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK                                             0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK                                             0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK                                             0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK                                             0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK                                             0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK                                             0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK                                             0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK                                             0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK                                             0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK                                             0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK                                             0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK                                             0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK                                             0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK                                             0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK                                             0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK                                             0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK                                             0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK                                             0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP5
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0__SHIFT                                            0x0
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1__SHIFT                                            0x1
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2__SHIFT                                            0x2
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3__SHIFT                                            0x3
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4__SHIFT                                            0x4
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5__SHIFT                                            0x5
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6__SHIFT                                            0x6
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7__SHIFT                                            0x7
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8__SHIFT                                            0x8
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9__SHIFT                                            0x9
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10__SHIFT                                           0xa
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11__SHIFT                                           0xb
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12__SHIFT                                           0xc
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13__SHIFT                                           0xd
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14__SHIFT                                           0xe
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15__SHIFT                                           0xf
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16__SHIFT                                           0x10
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17__SHIFT                                           0x11
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18__SHIFT                                           0x12
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19__SHIFT                                           0x13
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20__SHIFT                                           0x14
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21__SHIFT                                           0x15
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22__SHIFT                                           0x16
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23__SHIFT                                           0x17
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24__SHIFT                                           0x18
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25__SHIFT                                           0x19
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26__SHIFT                                           0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27__SHIFT                                           0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28__SHIFT                                           0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29__SHIFT                                           0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30__SHIFT                                           0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31__SHIFT                                           0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0_MASK                                              0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1_MASK                                              0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2_MASK                                              0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3_MASK                                              0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4_MASK                                              0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5_MASK                                              0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6_MASK                                              0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7_MASK                                              0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8_MASK                                              0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9_MASK                                              0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10_MASK                                             0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11_MASK                                             0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12_MASK                                             0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13_MASK                                             0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14_MASK                                             0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15_MASK                                             0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16_MASK                                             0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17_MASK                                             0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18_MASK                                             0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19_MASK                                             0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20_MASK                                             0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21_MASK                                             0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22_MASK                                             0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23_MASK                                             0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24_MASK                                             0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25_MASK                                             0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26_MASK                                             0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27_MASK                                             0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28_MASK                                             0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29_MASK                                             0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30_MASK                                             0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31_MASK                                             0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP6
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0__SHIFT                                            0x0
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1__SHIFT                                            0x1
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2__SHIFT                                            0x2
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3__SHIFT                                            0x3
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4__SHIFT                                            0x4
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5__SHIFT                                            0x5
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6__SHIFT                                            0x6
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7__SHIFT                                            0x7
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8__SHIFT                                            0x8
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9__SHIFT                                            0x9
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10__SHIFT                                           0xa
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11__SHIFT                                           0xb
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12__SHIFT                                           0xc
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13__SHIFT                                           0xd
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14__SHIFT                                           0xe
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15__SHIFT                                           0xf
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16__SHIFT                                           0x10
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17__SHIFT                                           0x11
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18__SHIFT                                           0x12
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19__SHIFT                                           0x13
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20__SHIFT                                           0x14
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21__SHIFT                                           0x15
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22__SHIFT                                           0x16
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23__SHIFT                                           0x17
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24__SHIFT                                           0x18
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25__SHIFT                                           0x19
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26__SHIFT                                           0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27__SHIFT                                           0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28__SHIFT                                           0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29__SHIFT                                           0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30__SHIFT                                           0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31__SHIFT                                           0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0_MASK                                              0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1_MASK                                              0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2_MASK                                              0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3_MASK                                              0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4_MASK                                              0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5_MASK                                              0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6_MASK                                              0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7_MASK                                              0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8_MASK                                              0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9_MASK                                              0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10_MASK                                             0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11_MASK                                             0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12_MASK                                             0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13_MASK                                             0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14_MASK                                             0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15_MASK                                             0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16_MASK                                             0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17_MASK                                             0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18_MASK                                             0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19_MASK                                             0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20_MASK                                             0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21_MASK                                             0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22_MASK                                             0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23_MASK                                             0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24_MASK                                             0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25_MASK                                             0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26_MASK                                             0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27_MASK                                             0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28_MASK                                             0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29_MASK                                             0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30_MASK                                             0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31_MASK                                             0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP7
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0__SHIFT                                            0x0
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1__SHIFT                                            0x1
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2__SHIFT                                            0x2
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3__SHIFT                                            0x3
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4__SHIFT                                            0x4
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5__SHIFT                                            0x5
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6__SHIFT                                            0x6
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7__SHIFT                                            0x7
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8__SHIFT                                            0x8
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9__SHIFT                                            0x9
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10__SHIFT                                           0xa
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11__SHIFT                                           0xb
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12__SHIFT                                           0xc
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13__SHIFT                                           0xd
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14__SHIFT                                           0xe
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15__SHIFT                                           0xf
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16__SHIFT                                           0x10
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17__SHIFT                                           0x11
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18__SHIFT                                           0x12
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19__SHIFT                                           0x13
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20__SHIFT                                           0x14
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21__SHIFT                                           0x15
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22__SHIFT                                           0x16
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23__SHIFT                                           0x17
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24__SHIFT                                           0x18
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25__SHIFT                                           0x19
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26__SHIFT                                           0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27__SHIFT                                           0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28__SHIFT                                           0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29__SHIFT                                           0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30__SHIFT                                           0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31__SHIFT                                           0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0_MASK                                              0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1_MASK                                              0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2_MASK                                              0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3_MASK                                              0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4_MASK                                              0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5_MASK                                              0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6_MASK                                              0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7_MASK                                              0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8_MASK                                              0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9_MASK                                              0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10_MASK                                             0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11_MASK                                             0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12_MASK                                             0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13_MASK                                             0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14_MASK                                             0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15_MASK                                             0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16_MASK                                             0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17_MASK                                             0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18_MASK                                             0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19_MASK                                             0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20_MASK                                             0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21_MASK                                             0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22_MASK                                             0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23_MASK                                             0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24_MASK                                             0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25_MASK                                             0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26_MASK                                             0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27_MASK                                             0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28_MASK                                             0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29_MASK                                             0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30_MASK                                             0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31_MASK                                             0x80000000L
+//PARITY_COUNTER_UCP_GRP0
+#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT                                                      0x0
+#define PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT                                                               0x1f
+#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK                                                        0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP0__ResetEn_MASK                                                                 0x80000000L
+//PARITY_COUNTER_UCP_GRP1
+#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT                                                      0x0
+#define PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT                                                               0x1f
+#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK                                                        0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP1__ResetEn_MASK                                                                 0x80000000L
+//PARITY_COUNTER_UCP_GRP2
+#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT                                                      0x0
+#define PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT                                                               0x1f
+#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK                                                        0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP2__ResetEn_MASK                                                                 0x80000000L
+//PARITY_COUNTER_UCP_GRP3
+#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT                                                      0x0
+#define PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT                                                               0x1f
+#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK                                                        0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP3__ResetEn_MASK                                                                 0x80000000L
+//PARITY_COUNTER_UCP_GRP4
+#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT                                                      0x0
+#define PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT                                                               0x1f
+#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK                                                        0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP4__ResetEn_MASK                                                                 0x80000000L
+//PARITY_COUNTER_UCP_GRP5
+#define PARITY_COUNTER_UCP_GRP5__ThresholdCounter__SHIFT                                                      0x0
+#define PARITY_COUNTER_UCP_GRP5__ResetEn__SHIFT                                                               0x1f
+#define PARITY_COUNTER_UCP_GRP5__ThresholdCounter_MASK                                                        0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP5__ResetEn_MASK                                                                 0x80000000L
+//PARITY_COUNTER_UCP_GRP6
+#define PARITY_COUNTER_UCP_GRP6__ThresholdCounter__SHIFT                                                      0x0
+#define PARITY_COUNTER_UCP_GRP6__ResetEn__SHIFT                                                               0x1f
+#define PARITY_COUNTER_UCP_GRP6__ThresholdCounter_MASK                                                        0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP6__ResetEn_MASK                                                                 0x80000000L
+//PARITY_COUNTER_UCP_GRP7
+#define PARITY_COUNTER_UCP_GRP7__ThresholdCounter__SHIFT                                                      0x0
+#define PARITY_COUNTER_UCP_GRP7__ResetEn__SHIFT                                                               0x1f
+#define PARITY_COUNTER_UCP_GRP7__ThresholdCounter_MASK                                                        0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP7__ResetEn_MASK                                                                 0x80000000L
+//MISC_SEVERITY_CONTROL
+#define MISC_SEVERITY_CONTROL__ErrEventErrSev__SHIFT                                                          0x4
+#define MISC_SEVERITY_CONTROL__PcieParityErrSev__SHIFT                                                        0x6
+#define MISC_SEVERITY_CONTROL__ErrEventErrSev_MASK                                                            0x00000030L
+#define MISC_SEVERITY_CONTROL__PcieParityErrSev_MASK                                                          0x000000C0L
+//MISC_RAS_CONTROL
+#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En__SHIFT                                                         0x2
+#define MISC_RAS_CONTROL__InterruptOutputDis__SHIFT                                                           0x9
+#define MISC_RAS_CONTROL__LinkDisOutputDis__SHIFT                                                             0xa
+#define MISC_RAS_CONTROL__SyncFldOutputDis__SHIFT                                                             0xb
+#define MISC_RAS_CONTROL__PCIe_NMI_En__SHIFT                                                                  0xc
+#define MISC_RAS_CONTROL__PCIe_SCI_En__SHIFT                                                                  0xd
+#define MISC_RAS_CONTROL__PCIe_SMI_En__SHIFT                                                                  0xe
+#define MISC_RAS_CONTROL__SW_SCI_En__SHIFT                                                                    0xf
+#define MISC_RAS_CONTROL__SW_SMI_En__SHIFT                                                                    0x10
+#define MISC_RAS_CONTROL__SW_NMI_En__SHIFT                                                                    0x11
+#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En_MASK                                                           0x00000004L
+#define MISC_RAS_CONTROL__InterruptOutputDis_MASK                                                             0x00000200L
+#define MISC_RAS_CONTROL__LinkDisOutputDis_MASK                                                               0x00000400L
+#define MISC_RAS_CONTROL__SyncFldOutputDis_MASK                                                               0x00000800L
+#define MISC_RAS_CONTROL__PCIe_NMI_En_MASK                                                                    0x00001000L
+#define MISC_RAS_CONTROL__PCIe_SCI_En_MASK                                                                    0x00002000L
+#define MISC_RAS_CONTROL__PCIe_SMI_En_MASK                                                                    0x00004000L
+#define MISC_RAS_CONTROL__SW_SCI_En_MASK                                                                      0x00008000L
+#define MISC_RAS_CONTROL__SW_SMI_En_MASK                                                                      0x00010000L
+#define MISC_RAS_CONTROL__SW_NMI_En_MASK                                                                      0x00020000L
+//RAS_SCRATCH_0
+#define RAS_SCRATCH_0__SCRATCH_0__SHIFT                                                                       0x0
+#define RAS_SCRATCH_0__SCRATCH_0_MASK                                                                         0xFFFFFFFFL
+//RAS_SCRATCH_1
+#define RAS_SCRATCH_1__SCRATCH_1__SHIFT                                                                       0x0
+#define RAS_SCRATCH_1__SCRATCH_1_MASK                                                                         0xFFFFFFFFL
+//ErrEvent_ACTION_CONTROL
+#define ErrEvent_ACTION_CONTROL__APML_ERR_En__SHIFT                                                           0x0
+#define ErrEvent_ACTION_CONTROL__IntrGenSel__SHIFT                                                            0x1
+#define ErrEvent_ACTION_CONTROL__LinkDis_En__SHIFT                                                            0x3
+#define ErrEvent_ACTION_CONTROL__SyncFlood_En__SHIFT                                                          0x4
+#define ErrEvent_ACTION_CONTROL__APML_ERR_En_MASK                                                             0x00000001L
+#define ErrEvent_ACTION_CONTROL__IntrGenSel_MASK                                                              0x00000006L
+#define ErrEvent_ACTION_CONTROL__LinkDis_En_MASK                                                              0x00000008L
+#define ErrEvent_ACTION_CONTROL__SyncFlood_En_MASK                                                            0x00000010L
+//ParitySerr_ACTION_CONTROL
+#define ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                         0x0
+#define ParitySerr_ACTION_CONTROL__IntrGenSel__SHIFT                                                          0x1
+#define ParitySerr_ACTION_CONTROL__LinkDis_En__SHIFT                                                          0x3
+#define ParitySerr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                        0x4
+#define ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK                                                           0x00000001L
+#define ParitySerr_ACTION_CONTROL__IntrGenSel_MASK                                                            0x00000006L
+#define ParitySerr_ACTION_CONTROL__LinkDis_En_MASK                                                            0x00000008L
+#define ParitySerr_ACTION_CONTROL__SyncFlood_En_MASK                                                          0x00000010L
+//ParityFatal_ACTION_CONTROL
+#define ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                        0x0
+#define ParityFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                         0x1
+#define ParityFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                         0x3
+#define ParityFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                       0x4
+#define ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                          0x00000001L
+#define ParityFatal_ACTION_CONTROL__IntrGenSel_MASK                                                           0x00000006L
+#define ParityFatal_ACTION_CONTROL__LinkDis_En_MASK                                                           0x00000008L
+#define ParityFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                         0x00000010L
+//ParityNonFatal_ACTION_CONTROL
+#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                     0x0
+#define ParityNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                      0x1
+#define ParityNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                      0x3
+#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                    0x4
+#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                       0x00000001L
+#define ParityNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                        0x00000006L
+#define ParityNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                        0x00000008L
+#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                      0x00000010L
+//ParityCorr_ACTION_CONTROL
+#define ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                         0x0
+#define ParityCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                          0x1
+#define ParityCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                          0x3
+#define ParityCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                        0x4
+#define ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                           0x00000001L
+#define ParityCorr_ACTION_CONTROL__IntrGenSel_MASK                                                            0x00000006L
+#define ParityCorr_ACTION_CONTROL__LinkDis_En_MASK                                                            0x00000008L
+#define ParityCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                          0x00000010L
+//PCIE0PortASerr_ACTION_CONTROL
+#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                     0x0
+#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT                                                      0x1
+#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT                                                      0x3
+#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                    0x4
+#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En_MASK                                                       0x00000001L
+#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel_MASK                                                        0x00000006L
+#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En_MASK                                                        0x00000008L
+#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En_MASK                                                      0x00000010L
+//PCIE0PortAIntFatal_ACTION_CONTROL
+#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortAIntNonFatal_ACTION_CONTROL
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortAIntCorr_ACTION_CONTROL
+#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortAExtFatal_ACTION_CONTROL
+#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortAExtNonFatal_ACTION_CONTROL
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortAExtCorr_ACTION_CONTROL
+#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortAParityErr_ACTION_CONTROL
+#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                0x0
+#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT                                                 0x1
+#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT                                                 0x3
+#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT                                               0x4
+#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK                                                  0x00000001L
+#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK                                                   0x00000006L
+#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK                                                   0x00000008L
+#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK                                                 0x00000010L
+//PCIE0PortBSerr_ACTION_CONTROL
+#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                     0x0
+#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT                                                      0x1
+#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT                                                      0x3
+#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                    0x4
+#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK                                                       0x00000001L
+#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel_MASK                                                        0x00000006L
+#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En_MASK                                                        0x00000008L
+#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK                                                      0x00000010L
+//PCIE0PortBIntFatal_ACTION_CONTROL
+#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortBIntNonFatal_ACTION_CONTROL
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortBIntCorr_ACTION_CONTROL
+#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortBExtFatal_ACTION_CONTROL
+#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortBExtNonFatal_ACTION_CONTROL
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortBExtCorr_ACTION_CONTROL
+#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortBParityErr_ACTION_CONTROL
+#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                0x0
+#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT                                                 0x1
+#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT                                                 0x3
+#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT                                               0x4
+#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK                                                  0x00000001L
+#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK                                                   0x00000006L
+#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK                                                   0x00000008L
+#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK                                                 0x00000010L
+//PCIE0PortCSerr_ACTION_CONTROL
+#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                     0x0
+#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT                                                      0x1
+#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT                                                      0x3
+#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                    0x4
+#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK                                                       0x00000001L
+#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel_MASK                                                        0x00000006L
+#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En_MASK                                                        0x00000008L
+#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK                                                      0x00000010L
+//PCIE0PortCIntFatal_ACTION_CONTROL
+#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortCIntNonFatal_ACTION_CONTROL
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortCIntCorr_ACTION_CONTROL
+#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortCExtFatal_ACTION_CONTROL
+#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortCExtNonFatal_ACTION_CONTROL
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortCExtCorr_ACTION_CONTROL
+#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortCParityErr_ACTION_CONTROL
+#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                0x0
+#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT                                                 0x1
+#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT                                                 0x3
+#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT                                               0x4
+#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK                                                  0x00000001L
+#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK                                                   0x00000006L
+#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK                                                   0x00000008L
+#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK                                                 0x00000010L
+//PCIE0PortDSerr_ACTION_CONTROL
+#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                     0x0
+#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel__SHIFT                                                      0x1
+#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En__SHIFT                                                      0x3
+#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                    0x4
+#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En_MASK                                                       0x00000001L
+#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel_MASK                                                        0x00000006L
+#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En_MASK                                                        0x00000008L
+#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En_MASK                                                      0x00000010L
+//PCIE0PortDIntFatal_ACTION_CONTROL
+#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortDIntNonFatal_ACTION_CONTROL
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortDIntCorr_ACTION_CONTROL
+#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortDExtFatal_ACTION_CONTROL
+#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortDExtNonFatal_ACTION_CONTROL
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortDExtCorr_ACTION_CONTROL
+#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortDParityErr_ACTION_CONTROL
+#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                0x0
+#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel__SHIFT                                                 0x1
+#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En__SHIFT                                                 0x3
+#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT                                               0x4
+#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En_MASK                                                  0x00000001L
+#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel_MASK                                                   0x00000006L
+#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En_MASK                                                   0x00000008L
+#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En_MASK                                                 0x00000010L
+//PCIE0PortESerr_ACTION_CONTROL
+#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                     0x0
+#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel__SHIFT                                                      0x1
+#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En__SHIFT                                                      0x3
+#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                    0x4
+#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En_MASK                                                       0x00000001L
+#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel_MASK                                                        0x00000006L
+#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En_MASK                                                        0x00000008L
+#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En_MASK                                                      0x00000010L
+//PCIE0PortEIntFatal_ACTION_CONTROL
+#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortEIntNonFatal_ACTION_CONTROL
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortEIntCorr_ACTION_CONTROL
+#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortEExtFatal_ACTION_CONTROL
+#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortEExtNonFatal_ACTION_CONTROL
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortEExtCorr_ACTION_CONTROL
+#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortEParityErr_ACTION_CONTROL
+#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                0x0
+#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel__SHIFT                                                 0x1
+#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En__SHIFT                                                 0x3
+#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT                                               0x4
+#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En_MASK                                                  0x00000001L
+#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel_MASK                                                   0x00000006L
+#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En_MASK                                                   0x00000008L
+#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En_MASK                                                 0x00000010L
+//PCIE0PortFSerr_ACTION_CONTROL
+#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                     0x0
+#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel__SHIFT                                                      0x1
+#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En__SHIFT                                                      0x3
+#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                    0x4
+#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En_MASK                                                       0x00000001L
+#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel_MASK                                                        0x00000006L
+#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En_MASK                                                        0x00000008L
+#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En_MASK                                                      0x00000010L
+//PCIE0PortFIntFatal_ACTION_CONTROL
+#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortFIntNonFatal_ACTION_CONTROL
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortFIntCorr_ACTION_CONTROL
+#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortFExtFatal_ACTION_CONTROL
+#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortFExtNonFatal_ACTION_CONTROL
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortFExtCorr_ACTION_CONTROL
+#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortFParityErr_ACTION_CONTROL
+#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                0x0
+#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel__SHIFT                                                 0x1
+#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En__SHIFT                                                 0x3
+#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT                                               0x4
+#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En_MASK                                                  0x00000001L
+#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel_MASK                                                   0x00000006L
+#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En_MASK                                                   0x00000008L
+#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En_MASK                                                 0x00000010L
+//PCIE0PortGSerr_ACTION_CONTROL
+#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                     0x0
+#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel__SHIFT                                                      0x1
+#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En__SHIFT                                                      0x3
+#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                    0x4
+#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En_MASK                                                       0x00000001L
+#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel_MASK                                                        0x00000006L
+#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En_MASK                                                        0x00000008L
+#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En_MASK                                                      0x00000010L
+//PCIE0PortGIntFatal_ACTION_CONTROL
+#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortGIntNonFatal_ACTION_CONTROL
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortGIntCorr_ACTION_CONTROL
+#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortGExtFatal_ACTION_CONTROL
+#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//PCIE0PortGExtNonFatal_ACTION_CONTROL
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//PCIE0PortGExtCorr_ACTION_CONTROL
+#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//PCIE0PortGParityErr_ACTION_CONTROL
+#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                0x0
+#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel__SHIFT                                                 0x1
+#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En__SHIFT                                                 0x3
+#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT                                               0x4
+#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En_MASK                                                  0x00000001L
+#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel_MASK                                                   0x00000006L
+#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En_MASK                                                   0x00000008L
+#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En_MASK                                                 0x00000010L
+//NBIF1PortASerr_ACTION_CONTROL
+#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                     0x0
+#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT                                                      0x1
+#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT                                                      0x3
+#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                    0x4
+#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En_MASK                                                       0x00000001L
+#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel_MASK                                                        0x00000006L
+#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En_MASK                                                        0x00000008L
+#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En_MASK                                                      0x00000010L
+//NBIF1PortAIntFatal_ACTION_CONTROL
+#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//NBIF1PortAIntNonFatal_ACTION_CONTROL
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//NBIF1PortAIntCorr_ACTION_CONTROL
+#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//NBIF1PortAExtFatal_ACTION_CONTROL
+#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//NBIF1PortAExtNonFatal_ACTION_CONTROL
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//NBIF1PortAExtCorr_ACTION_CONTROL
+#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//NBIF1PortAParityErr_ACTION_CONTROL
+#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                0x0
+#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT                                                 0x1
+#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT                                                 0x3
+#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT                                               0x4
+#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK                                                  0x00000001L
+#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK                                                   0x00000006L
+#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK                                                   0x00000008L
+#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK                                                 0x00000010L
+//NBIF1PortBSerr_ACTION_CONTROL
+#define NBIF1PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                     0x0
+#define NBIF1PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT                                                      0x1
+#define NBIF1PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT                                                      0x3
+#define NBIF1PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                    0x4
+#define NBIF1PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK                                                       0x00000001L
+#define NBIF1PortBSerr_ACTION_CONTROL__IntrGenSel_MASK                                                        0x00000006L
+#define NBIF1PortBSerr_ACTION_CONTROL__LinkDis_En_MASK                                                        0x00000008L
+#define NBIF1PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK                                                      0x00000010L
+//NBIF1PortBIntFatal_ACTION_CONTROL
+#define NBIF1PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define NBIF1PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define NBIF1PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define NBIF1PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define NBIF1PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define NBIF1PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define NBIF1PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define NBIF1PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//NBIF1PortBIntNonFatal_ACTION_CONTROL
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//NBIF1PortBIntCorr_ACTION_CONTROL
+#define NBIF1PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define NBIF1PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define NBIF1PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define NBIF1PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define NBIF1PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define NBIF1PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define NBIF1PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define NBIF1PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//NBIF1PortBExtFatal_ACTION_CONTROL
+#define NBIF1PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define NBIF1PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define NBIF1PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define NBIF1PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define NBIF1PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define NBIF1PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define NBIF1PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define NBIF1PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//NBIF1PortBExtNonFatal_ACTION_CONTROL
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//NBIF1PortBExtCorr_ACTION_CONTROL
+#define NBIF1PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define NBIF1PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define NBIF1PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define NBIF1PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define NBIF1PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define NBIF1PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define NBIF1PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define NBIF1PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//NBIF1PortBParityErr_ACTION_CONTROL
+#define NBIF1PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                0x0
+#define NBIF1PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT                                                 0x1
+#define NBIF1PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT                                                 0x3
+#define NBIF1PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT                                               0x4
+#define NBIF1PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK                                                  0x00000001L
+#define NBIF1PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK                                                   0x00000006L
+#define NBIF1PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK                                                   0x00000008L
+#define NBIF1PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK                                                 0x00000010L
+//NBIF1PortCSerr_ACTION_CONTROL
+#define NBIF1PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                     0x0
+#define NBIF1PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT                                                      0x1
+#define NBIF1PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT                                                      0x3
+#define NBIF1PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                    0x4
+#define NBIF1PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK                                                       0x00000001L
+#define NBIF1PortCSerr_ACTION_CONTROL__IntrGenSel_MASK                                                        0x00000006L
+#define NBIF1PortCSerr_ACTION_CONTROL__LinkDis_En_MASK                                                        0x00000008L
+#define NBIF1PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK                                                      0x00000010L
+//NBIF1PortCIntFatal_ACTION_CONTROL
+#define NBIF1PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define NBIF1PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define NBIF1PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define NBIF1PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define NBIF1PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define NBIF1PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define NBIF1PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define NBIF1PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//NBIF1PortCIntNonFatal_ACTION_CONTROL
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//NBIF1PortCIntCorr_ACTION_CONTROL
+#define NBIF1PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define NBIF1PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define NBIF1PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define NBIF1PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define NBIF1PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define NBIF1PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define NBIF1PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define NBIF1PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//NBIF1PortCExtFatal_ACTION_CONTROL
+#define NBIF1PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                                 0x0
+#define NBIF1PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                                  0x1
+#define NBIF1PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                                  0x3
+#define NBIF1PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                                0x4
+#define NBIF1PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                   0x00000001L
+#define NBIF1PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK                                                    0x00000006L
+#define NBIF1PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK                                                    0x00000008L
+#define NBIF1PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK                                                  0x00000010L
+//NBIF1PortCExtNonFatal_ACTION_CONTROL
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT                                              0x0
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT                                               0x1
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT                                               0x3
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT                                             0x4
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK                                                0x00000001L
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK                                                 0x00000006L
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK                                                 0x00000008L
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK                                               0x00000010L
+//NBIF1PortCExtCorr_ACTION_CONTROL
+#define NBIF1PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                  0x0
+#define NBIF1PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT                                                   0x1
+#define NBIF1PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT                                                   0x3
+#define NBIF1PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT                                                 0x4
+#define NBIF1PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK                                                    0x00000001L
+#define NBIF1PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK                                                     0x00000006L
+#define NBIF1PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK                                                     0x00000008L
+#define NBIF1PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK                                                   0x00000010L
+//NBIF1PortCParityErr_ACTION_CONTROL
+#define NBIF1PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT                                                0x0
+#define NBIF1PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT                                                 0x1
+#define NBIF1PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT                                                 0x3
+#define NBIF1PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT                                               0x4
+#define NBIF1PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK                                                  0x00000001L
+#define NBIF1PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK                                                   0x00000006L
+#define NBIF1PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK                                                   0x00000008L
+#define NBIF1PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK                                                 0x00000010L
+//SYNCFLOOD_STATUS
+#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl__SHIFT                                                         0x0
+#define SYNCFLOOD_STATUS__SyncfloodFromAPML__SHIFT                                                            0x1
+#define SYNCFLOOD_STATUS__SyncfloodFromPin__SHIFT                                                             0x2
+#define SYNCFLOOD_STATUS__SyncfloodFromPrivate__SHIFT                                                         0x4
+#define SYNCFLOOD_STATUS__SyncfloodFromMCA__SHIFT                                                             0x5
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8__SHIFT                                                     0x8
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9__SHIFT                                                     0x9
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10__SHIFT                                                    0xa
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11__SHIFT                                                    0xb
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12__SHIFT                                                    0xc
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13__SHIFT                                                    0xd
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14__SHIFT                                                    0xe
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15__SHIFT                                                    0xf
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16__SHIFT                                                    0x10
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17__SHIFT                                                    0x11
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18__SHIFT                                                    0x12
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19__SHIFT                                                    0x13
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20__SHIFT                                                    0x14
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21__SHIFT                                                    0x15
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22__SHIFT                                                    0x16
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23__SHIFT                                                    0x17
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24__SHIFT                                                    0x18
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25__SHIFT                                                    0x19
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26__SHIFT                                                    0x1a
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27__SHIFT                                                    0x1b
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28__SHIFT                                                    0x1c
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29__SHIFT                                                    0x1d
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30__SHIFT                                                    0x1e
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31__SHIFT                                                    0x1f
+#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl_MASK                                                           0x00000001L
+#define SYNCFLOOD_STATUS__SyncfloodFromAPML_MASK                                                              0x00000002L
+#define SYNCFLOOD_STATUS__SyncfloodFromPin_MASK                                                               0x00000004L
+#define SYNCFLOOD_STATUS__SyncfloodFromPrivate_MASK                                                           0x00000010L
+#define SYNCFLOOD_STATUS__SyncfloodFromMCA_MASK                                                               0x00000020L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8_MASK                                                       0x00000100L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9_MASK                                                       0x00000200L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10_MASK                                                      0x00000400L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11_MASK                                                      0x00000800L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12_MASK                                                      0x00001000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13_MASK                                                      0x00002000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14_MASK                                                      0x00004000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15_MASK                                                      0x00008000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16_MASK                                                      0x00010000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17_MASK                                                      0x00020000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18_MASK                                                      0x00040000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19_MASK                                                      0x00080000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20_MASK                                                      0x00100000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21_MASK                                                      0x00200000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22_MASK                                                      0x00400000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23_MASK                                                      0x00800000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24_MASK                                                      0x01000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25_MASK                                                      0x02000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26_MASK                                                      0x04000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27_MASK                                                      0x08000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28_MASK                                                      0x10000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29_MASK                                                      0x20000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30_MASK                                                      0x40000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31_MASK                                                      0x80000000L
+//NMI_STATUS
+#define NMI_STATUS__NMIFromPin__SHIFT                                                                         0x0
+#define NMI_STATUS__NMIFromPin_MASK                                                                           0x00000001L
+//POISON_ACTION_CONTROL
+#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn__SHIFT                                                      0x0
+#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel__SHIFT                                                     0x1
+#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn__SHIFT                                                      0x3
+#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn__SHIFT                                                    0x4
+#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn__SHIFT                                                 0x8
+#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel__SHIFT                                                0x9
+#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn__SHIFT                                                 0xb
+#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn__SHIFT                                               0xc
+#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn__SHIFT                                                 0x10
+#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel__SHIFT                                                0x11
+#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn__SHIFT                                                 0x13
+#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn__SHIFT                                               0x14
+#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn_MASK                                                        0x00000001L
+#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel_MASK                                                       0x00000006L
+#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn_MASK                                                        0x00000008L
+#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn_MASK                                                      0x00000010L
+#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn_MASK                                                   0x00000100L
+#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel_MASK                                                  0x00000600L
+#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn_MASK                                                   0x00000800L
+#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn_MASK                                                 0x00001000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn_MASK                                                   0x00010000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel_MASK                                                  0x00060000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn_MASK                                                   0x00080000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn_MASK                                                 0x00100000L
+//EGRESS_POISON_STATUS_LO
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0__SHIFT                                                0x0
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1__SHIFT                                                0x1
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2__SHIFT                                                0x2
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3__SHIFT                                                0x3
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4__SHIFT                                                0x4
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5__SHIFT                                                0x5
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6__SHIFT                                                0x6
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7__SHIFT                                                0x7
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8__SHIFT                                                0x8
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9__SHIFT                                                0x9
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10__SHIFT                                               0xa
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11__SHIFT                                               0xb
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12__SHIFT                                               0xc
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13__SHIFT                                               0xd
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14__SHIFT                                               0xe
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15__SHIFT                                               0xf
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16__SHIFT                                               0x10
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17__SHIFT                                               0x11
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18__SHIFT                                               0x12
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19__SHIFT                                               0x13
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20__SHIFT                                               0x14
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21__SHIFT                                               0x15
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22__SHIFT                                               0x16
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23__SHIFT                                               0x17
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24__SHIFT                                               0x18
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25__SHIFT                                               0x19
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26__SHIFT                                               0x1a
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27__SHIFT                                               0x1b
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28__SHIFT                                               0x1c
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29__SHIFT                                               0x1d
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30__SHIFT                                               0x1e
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31__SHIFT                                               0x1f
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0_MASK                                                  0x00000001L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1_MASK                                                  0x00000002L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2_MASK                                                  0x00000004L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3_MASK                                                  0x00000008L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4_MASK                                                  0x00000010L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5_MASK                                                  0x00000020L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6_MASK                                                  0x00000040L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7_MASK                                                  0x00000080L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8_MASK                                                  0x00000100L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9_MASK                                                  0x00000200L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10_MASK                                                 0x00000400L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11_MASK                                                 0x00000800L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12_MASK                                                 0x00001000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13_MASK                                                 0x00002000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14_MASK                                                 0x00004000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15_MASK                                                 0x00008000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16_MASK                                                 0x00010000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17_MASK                                                 0x00020000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18_MASK                                                 0x00040000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19_MASK                                                 0x00080000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20_MASK                                                 0x00100000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21_MASK                                                 0x00200000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22_MASK                                                 0x00400000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23_MASK                                                 0x00800000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24_MASK                                                 0x01000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25_MASK                                                 0x02000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26_MASK                                                 0x04000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27_MASK                                                 0x08000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28_MASK                                                 0x10000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29_MASK                                                 0x20000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30_MASK                                                 0x40000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31_MASK                                                 0x80000000L
+//EGRESS_POISON_STATUS_HI
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0__SHIFT                                                0x0
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1__SHIFT                                                0x1
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2__SHIFT                                                0x2
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3__SHIFT                                                0x3
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4__SHIFT                                                0x4
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5__SHIFT                                                0x5
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6__SHIFT                                                0x6
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7__SHIFT                                                0x7
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8__SHIFT                                                0x8
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9__SHIFT                                                0x9
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10__SHIFT                                               0xa
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11__SHIFT                                               0xb
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12__SHIFT                                               0xc
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13__SHIFT                                               0xd
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14__SHIFT                                               0xe
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15__SHIFT                                               0xf
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16__SHIFT                                               0x10
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17__SHIFT                                               0x11
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18__SHIFT                                               0x12
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19__SHIFT                                               0x13
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20__SHIFT                                               0x14
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21__SHIFT                                               0x15
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22__SHIFT                                               0x16
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23__SHIFT                                               0x17
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24__SHIFT                                               0x18
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25__SHIFT                                               0x19
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26__SHIFT                                               0x1a
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27__SHIFT                                               0x1b
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28__SHIFT                                               0x1c
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29__SHIFT                                               0x1d
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30__SHIFT                                               0x1e
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31__SHIFT                                               0x1f
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0_MASK                                                  0x00000001L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1_MASK                                                  0x00000002L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2_MASK                                                  0x00000004L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3_MASK                                                  0x00000008L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4_MASK                                                  0x00000010L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5_MASK                                                  0x00000020L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6_MASK                                                  0x00000040L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7_MASK                                                  0x00000080L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8_MASK                                                  0x00000100L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9_MASK                                                  0x00000200L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10_MASK                                                 0x00000400L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11_MASK                                                 0x00000800L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12_MASK                                                 0x00001000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13_MASK                                                 0x00002000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14_MASK                                                 0x00004000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15_MASK                                                 0x00008000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16_MASK                                                 0x00010000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17_MASK                                                 0x00020000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18_MASK                                                 0x00040000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19_MASK                                                 0x00080000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20_MASK                                                 0x00100000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21_MASK                                                 0x00200000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22_MASK                                                 0x00400000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23_MASK                                                 0x00800000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24_MASK                                                 0x01000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25_MASK                                                 0x02000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26_MASK                                                 0x04000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27_MASK                                                 0x08000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28_MASK                                                 0x10000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29_MASK                                                 0x20000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30_MASK                                                 0x40000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31_MASK                                                 0x80000000L
+//EGRESS_POISON_MASK_LO
+#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo__SHIFT                                                      0x0
+#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo_MASK                                                        0xFFFFFFFFL
+//EGRESS_POISON_MASK_HI
+#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi__SHIFT                                                      0x0
+#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi_MASK                                                        0xFFFFFFFFL
+//EGRESS_POISON_SEVERITY_DOWN
+#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown__SHIFT                                          0x0
+#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown_MASK                                            0xFFFFFFFFL
+//EGRESS_POISON_SEVERITY_UPPER
+#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper__SHIFT                                        0x0
+#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper_MASK                                          0xFFFFFFFFL
+//APML_STATUS
+#define APML_STATUS__APML_Corr__SHIFT                                                                         0x0
+#define APML_STATUS__APML_NonFatal__SHIFT                                                                     0x1
+#define APML_STATUS__APML_Fatal__SHIFT                                                                        0x2
+#define APML_STATUS__APML_Serr__SHIFT                                                                         0x3
+#define APML_STATUS__APML_IntPoisonErr__SHIFT                                                                 0x4
+#define APML_STATUS__APML_EgressPoisonErrLo__SHIFT                                                            0x5
+#define APML_STATUS__APML_EgressPoisonErrHi__SHIFT                                                            0x6
+#define APML_STATUS__APML_Corr_MASK                                                                           0x00000001L
+#define APML_STATUS__APML_NonFatal_MASK                                                                       0x00000002L
+#define APML_STATUS__APML_Fatal_MASK                                                                          0x00000004L
+#define APML_STATUS__APML_Serr_MASK                                                                           0x00000008L
+#define APML_STATUS__APML_IntPoisonErr_MASK                                                                   0x00000010L
+#define APML_STATUS__APML_EgressPoisonErrLo_MASK                                                              0x00000020L
+#define APML_STATUS__APML_EgressPoisonErrHi_MASK                                                              0x00000040L
+//APML_CONTROL
+#define APML_CONTROL__APML_NMI_En__SHIFT                                                                      0x0
+#define APML_CONTROL__APML_SyncFlood_En__SHIFT                                                                0x1
+#define APML_CONTROL__APML_OutputDis__SHIFT                                                                   0x8
+#define APML_CONTROL__APML_NMI_En_MASK                                                                        0x00000001L
+#define APML_CONTROL__APML_SyncFlood_En_MASK                                                                  0x00000002L
+#define APML_CONTROL__APML_OutputDis_MASK                                                                     0x00000100L
+//APML_TRIGGER
+#define APML_TRIGGER__APML_NMI_TRIGGER__SHIFT                                                                 0x0
+#define APML_TRIGGER__APML_NMI_TRIGGER_MASK                                                                   0x00000001L
+
+
+
+
+
+
+
+
+
+
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF2_MM_INDEX
+#define BIF_BX_PF2_MM_INDEX__MM_OFFSET__SHIFT                                                                 0x0
+#define BIF_BX_PF2_MM_INDEX__MM_APER__SHIFT                                                                   0x1f
+#define BIF_BX_PF2_MM_INDEX__MM_OFFSET_MASK                                                                   0x7FFFFFFFL
+#define BIF_BX_PF2_MM_INDEX__MM_APER_MASK                                                                     0x80000000L
+//BIF_BX_PF2_MM_DATA
+#define BIF_BX_PF2_MM_DATA__MM_DATA__SHIFT                                                                    0x0
+#define BIF_BX_PF2_MM_DATA__MM_DATA_MASK                                                                      0xFFFFFFFFL
+//BIF_BX_PF2_MM_INDEX_HI
+#define BIF_BX_PF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                           0x0
+#define BIF_BX_PF2_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+//BIF_BX2_PCIE_INDEX
+#define BIF_BX2_PCIE_INDEX__PCIE_INDEX__SHIFT                                                                 0x0
+#define BIF_BX2_PCIE_INDEX__PCIE_INDEX_MASK                                                                   0xFFFFFFFFL
+//BIF_BX2_PCIE_DATA
+#define BIF_BX2_PCIE_DATA__PCIE_DATA__SHIFT                                                                   0x0
+#define BIF_BX2_PCIE_DATA__PCIE_DATA_MASK                                                                     0xFFFFFFFFL
+//BIF_BX2_PCIE_INDEX2
+#define BIF_BX2_PCIE_INDEX2__PCIE_INDEX2__SHIFT                                                               0x0
+#define BIF_BX2_PCIE_INDEX2__PCIE_INDEX2_MASK                                                                 0xFFFFFFFFL
+//BIF_BX2_PCIE_DATA2
+#define BIF_BX2_PCIE_DATA2__PCIE_DATA2__SHIFT                                                                 0x0
+#define BIF_BX2_PCIE_DATA2__PCIE_DATA2_MASK                                                                   0xFFFFFFFFL
+//BIF_BX2_SBIOS_SCRATCH_0
+#define BIF_BX2_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX2_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX2_SBIOS_SCRATCH_1
+#define BIF_BX2_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX2_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX2_SBIOS_SCRATCH_2
+#define BIF_BX2_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX2_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX2_SBIOS_SCRATCH_3
+#define BIF_BX2_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT                                                      0x0
+#define BIF_BX2_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK                                                        0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_0
+#define BIF_BX2_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT                                                         0x0
+#define BIF_BX2_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK                                                           0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_1
+#define BIF_BX2_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT                                                         0x0
+#define BIF_BX2_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK                                                           0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_2
+#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                         0x0
+#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                           0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_3
+#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                         0x0
+#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                           0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_4
+#define BIF_BX2_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT                                                         0x0
+#define BIF_BX2_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK                                                           0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_5
+#define BIF_BX2_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT                                                         0x0
+#define BIF_BX2_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK                                                           0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_6
+#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                         0x0
+#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                           0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_7
+#define BIF_BX2_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT                                                         0x0
+#define BIF_BX2_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK                                                           0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_8
+#define BIF_BX2_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT                                                         0x0
+#define BIF_BX2_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK                                                           0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_9
+#define BIF_BX2_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT                                                         0x0
+#define BIF_BX2_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK                                                           0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_10
+#define BIF_BX2_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT                                                       0x0
+#define BIF_BX2_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK                                                         0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_11
+#define BIF_BX2_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT                                                       0x0
+#define BIF_BX2_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK                                                         0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_12
+#define BIF_BX2_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT                                                       0x0
+#define BIF_BX2_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK                                                         0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_13
+#define BIF_BX2_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT                                                       0x0
+#define BIF_BX2_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK                                                         0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_14
+#define BIF_BX2_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT                                                       0x0
+#define BIF_BX2_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK                                                         0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_15
+#define BIF_BX2_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT                                                       0x0
+#define BIF_BX2_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK                                                         0xFFFFFFFFL
+//BIF_BX2_BIF_RLC_INTR_CNTL
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT                                                    0x0
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT                                             0x1
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT                                                   0x2
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT                                              0x3
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK                                                      0x00000001L
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK                                               0x00000002L
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK                                                     0x00000004L
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK                                                0x00000008L
+//BIF_BX2_BIF_VCE_INTR_CNTL
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT                                                    0x0
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT                                             0x1
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT                                                   0x2
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT                                              0x3
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK                                                      0x00000001L
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK                                               0x00000002L
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK                                                     0x00000004L
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK                                                0x00000008L
+//BIF_BX2_BIF_UVD_INTR_CNTL
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT                                                    0x0
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT                                             0x1
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT                                                   0x2
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT                                              0x3
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT                                                        0x1c
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK                                                      0x00000001L
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK                                               0x00000002L
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK                                                     0x00000004L
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK                                                0x00000008L
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK                                                          0xF0000000L
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT                                                       0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK                                                         0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT                                           0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK                                             0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT                                                       0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK                                                         0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT                                           0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK                                             0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT                                                       0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK                                                         0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT                                           0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK                                             0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT                                                       0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK                                                         0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT                                           0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK                                             0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT                                                       0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK                                                         0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT                                           0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK                                             0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT                                                       0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK                                                         0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT                                           0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK                                             0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT                                                       0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK                                                         0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT                                           0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK                                             0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT                                                       0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK                                                         0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT                                           0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK                                             0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX2_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT                                                       0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK                                                         0x000000FFL
+//BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT                                                 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK                                                   0xFFFFFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT                                                   0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK                                                     0xFFFFFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT                                 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK                                   0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+//RCC_STRAP3_RCC_BIF_STRAP0
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT                                                  0x0
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT                                                   0x2
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT                                               0x3
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT                                               0x6
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT                                                    0x7
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT                                                 0x8
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT                                  0x9
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT                                         0xa
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT                                     0xb
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT                                              0xc
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT                                             0xd
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                     0xe
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                  0xf
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT                                              0x10
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT                                           0x11
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT                                                      0x18
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT                                                 0x19
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT                                                0x1a
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0x1b
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT                                      0x1d
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT                                                   0x1e
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT                                            0x1f
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK                                                    0x00000001L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK                                                     0x00000004L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK                                                 0x00000038L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK                                                 0x00000040L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK                                                      0x00000080L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK                                                   0x00000100L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK                                    0x00000200L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK                                           0x00000400L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK                                       0x00000800L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK                                                0x00001000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK                                               0x00002000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                       0x00004000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                    0x00008000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK                                                0x00010000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK                                             0x00020000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK                                                        0x01000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK                                                   0x02000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK                                                  0x04000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK                                       0x08000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK                                        0x20000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK                                                     0x40000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK                                              0x80000000L
+//RCC_STRAP3_RCC_BIF_STRAP1
+#define RCC_STRAP3_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT                                                      0x1
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT                                      0x3
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT                                     0x5
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                       0x6
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT                                               0x7
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT                                                  0x8
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT                                                 0x9
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT                                                  0xa
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT                                        0xc
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT                                                    0xd
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT                                                    0xf
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT                                             0x11
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT                                             0x12
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT                                                        0x13
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT                                                   0x14
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT                                                     0x15
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT                                             0x16
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT                                     0x17
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT                                             0x1a
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT                                       0x1b
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT                                                     0x1d
+#define RCC_STRAP3_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK                                                        0x00000002L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK                                        0x00000008L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK                                       0x00000020L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK                                         0x00000040L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK                                                 0x00000080L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK                                                    0x00000100L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK                                                   0x00000200L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK                                                    0x00000C00L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK                                          0x00001000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK                                                      0x00006000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK                                                      0x00018000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK                                               0x00020000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK                                               0x00040000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK                                                          0x00080000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK                                                     0x00100000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK                                                       0x00200000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK                                               0x00400000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK                                       0x00800000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK                                               0x04000000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK                                         0x18000000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK                                                       0x20000000L
+//RCC_STRAP3_RCC_BIF_STRAP2
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT                                     0x0
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT                                            0x3
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT                                            0x4
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT                                        0x5
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT                                      0x6
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT                                 0x8
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT                                        0x9
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT                                   0xa
+#define RCC_STRAP3_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT                                                 0xd
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT                                             0xe
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT                                 0xf
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT                                         0x10
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT                                        0x18
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT                            0x1f
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK                                       0x00000001L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK                                              0x00000008L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK                                              0x00000010L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK                                          0x00000020L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK                                        0x00000040L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK                                   0x00000100L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK                                          0x00000200L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK                                     0x00000C00L
+#define RCC_STRAP3_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK                                                   0x00002000L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK                                               0x00004000L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK                                   0x00008000L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK                                           0x00FF0000L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK                                          0x01000000L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK                              0x80000000L
+//RCC_STRAP3_RCC_BIF_STRAP3
+#define RCC_STRAP3_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT                                         0x0
+#define RCC_STRAP3_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT                                       0x10
+#define RCC_STRAP3_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP3_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK                                         0xFFFF0000L
+//RCC_STRAP3_RCC_BIF_STRAP4
+#define RCC_STRAP3_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT                                          0x0
+#define RCC_STRAP3_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT                                           0x10
+#define RCC_STRAP3_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK                                            0x0000FFFFL
+#define RCC_STRAP3_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK                                             0xFFFF0000L
+//RCC_STRAP3_RCC_BIF_STRAP5
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT                                         0x0
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT                                      0x10
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT                                   0x11
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT                                    0x12
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT                                        0x13
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT                                    0x14
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT                                         0x16
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT                          0x18
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x19
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1b
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT                                           0x1c
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK                                        0x00010000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK                                     0x00020000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK                                      0x00040000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK                                          0x00080000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK                                      0x00100000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK                                           0x00C00000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK                            0x01000000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x06000000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x08000000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK                                             0x70000000L
+//RCC_STRAP3_RCC_BIF_STRAP6
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT                                          0x1
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT                                          0x2
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT                                          0x3
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT                                0x4
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT                                       0x5
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT                                   0x15
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT                            0x18
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT                             0x19
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT                             0x1c
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT                                      0x1f
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK                                            0x00000002L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK                                            0x00000004L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK                                            0x00000008L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK                                  0x00000010L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK                                         0x001FFFE0L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK                                     0x00E00000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK                              0x01000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK                               0x0E000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK                               0x70000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK                                        0x80000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT                                       0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT                                   0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK                                         0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK                                     0xFFFF0000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT                                 0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT                                          0x1
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT                                      0x2
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT                                          0x3
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT                                      0x4
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT                                  0x6
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT                             0x7
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT                                0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT                                    0x9
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT                              0xc
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT                      0xd
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT                                    0xe
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT                                            0xf
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT                                    0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT                                    0x11
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT                                  0x12
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT                             0x14
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT                                   0x17
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT                              0x1a
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT                                    0x1d
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK                                   0x00000001L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK                                            0x00000002L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK                                        0x00000004L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK                                            0x00000008L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK                                        0x00000010L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK                                    0x00000040L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK                               0x00000080L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK                                  0x00000100L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK                                      0x00000E00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK                                0x00001000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK                        0x00002000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK                                      0x00004000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK                                              0x00008000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK                                      0x00010000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK                                      0x00020000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK                                    0x000C0000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK                               0x00700000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK                                     0x03800000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK                                0x1C000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK                                      0xE0000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT                     0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT                                             0x1
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT                                          0x2
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT                                0x3
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT                                          0x6
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT                                  0x7
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT                                   0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT                                     0x9
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0xb
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0xe
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0x12
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0x15
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT                                         0x19
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT                                      0x1b
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT                                       0x1d
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT                                         0x1f
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK                       0x00000001L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK                                               0x00000002L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK                                            0x00000004L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK                                  0x00000038L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK                                            0x00000040L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK                                    0x00000080L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK                                     0x00000100L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK                                       0x00000600L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x00003800L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK  0x0003C000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x001C0000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK  0x01E00000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK                                           0x06000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK                                        0x18000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK                                         0x20000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK                                           0x80000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT                              0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT                              0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT                              0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT                              0x18
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK                                0xFF000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT                              0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT                              0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT                        0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT                                 0x11
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT                                  0x12
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT                                           0x13
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT                                           0x14
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT                                        0x15
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT                                0x16
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT                           0x17
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT                        0x18
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT                        0x19
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT                     0x1a
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT                         0x1b
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT                          0x1c
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT                       0x1d
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT                                         0x1e
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT                                            0x1f
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK                          0x00010000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK                                   0x00020000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK                                    0x00040000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK                                             0x00080000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK                                             0x00100000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK                                          0x00200000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK                                  0x00400000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK                             0x00800000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK                          0x01000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK                          0x02000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK                       0x04000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK                           0x08000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK                            0x10000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK                         0x20000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK                                           0x40000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK                                              0x80000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT                                         0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT                         0x1
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x3
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x4
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT                      0x5
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                      0x6
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                   0x7
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT     0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT     0xc
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT                              0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT                            0x12
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT                     0x13
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK                                           0x00000001L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK                           0x00000002L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000008L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000010L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK                        0x00000020L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                        0x00000040L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                     0x00000080L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK       0x00000F00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK       0x0000F000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK                                0x00030000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK                              0x00040000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK                       0x00080000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT                                        0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT                                    0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT                                    0xc
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT                                          0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT                                          0x18
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT                                          0x1d
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK                                          0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK                                      0x00000F00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK                                      0x0000F000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK                                            0x00FF0000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK                                            0x1F000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK                                            0xE0000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT                              0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT                              0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT                              0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT                              0x18
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK                                0xFF000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT                              0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT                              0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT                                       0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK                                         0xFFFF0000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT                       0x10
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK                                0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK                         0xFFFF0000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT                                 0x8
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT                                0x10
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK                                   0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK                                   0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK                                  0x00FF0000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT                                      0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK                                        0x0000FFFFL
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT                                        0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT                                 0x1
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT                                       0x6
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT                                   0x7
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT                                 0x9
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT                          0xe
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT                                          0xf
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT                                          0x10
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT                                          0x11
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT                                0x14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT                                          0x15
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT                                           0x17
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT                                   0x18
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT                                     0x1b
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT                                        0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT                  0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT               0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT                       0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK                                          0x00000001L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK                                   0x0000003EL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK                                         0x00000040L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK                                     0x00000080L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK                                   0x00003E00L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK                            0x00004000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK                                            0x00008000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK                                            0x00010000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK                                            0x00020000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK                                  0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK                                            0x00200000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK                                             0x00800000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK                                     0x07000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK                                       0x08000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK                                          0x10000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK                    0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK                 0x40000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK                         0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT                      0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT                                          0x1
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT                                       0x2
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT                              0x13
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT                                         0x14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT                                  0x15
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT                                         0x18
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT                        0x1a
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT                       0x1b
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT                                0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT                                       0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT                               0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK                        0x00000001L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK                                            0x00000002L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK                                         0x0003FFFCL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK                                0x00080000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK                                           0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK                                    0x00E00000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK                                           0x01000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK                          0x04000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK                         0x08000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK                                  0x10000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK                                         0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK                                 0x40000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT                                       0x15
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT                                     0x17
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT                                   0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT                                  0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK                                   0x000003FFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK                                         0x00200000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK                                       0x0F800000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK                                     0x70000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK                                    0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT                                   0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT                            0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK                                     0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK                              0x40000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT                                0x3
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT                                     0x4
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT                                      0x7
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT                                     0x9
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT                                     0xd
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                           0x10
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT                                  0x13
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT                                  0x17
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT                                         0x1a
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT                                0x1b
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT                           0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK                                0x00000007L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK                                  0x00000008L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK                                       0x00000070L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK                                        0x00000080L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK                                       0x00001E00L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK                                       0x0000E000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK                             0x00070000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK                                    0x00780000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK                                    0x03800000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK                                           0x04000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK                                  0x38000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK                             0xC0000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT                           0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT                               0x12
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT                        0x13
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT                                    0x15
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT                                 0x16
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT                                 0x18
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK                             0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK                                 0x00040000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK                          0x00080000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK                                      0x00200000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK                                   0x00C00000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK                                   0x0F000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT                                       0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT                                    0x10
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT                                    0x14
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT                                         0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT                           0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT                                      0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT                                      0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK                                         0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK                                      0x000F0000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK                                      0x00F00000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK                                           0x10000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK                             0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK                                        0x40000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK                                        0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP10
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP11
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP12
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT                                 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT                                 0x8
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT                                0x10
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK                                   0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK                                   0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK                                  0x00FF0000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP14
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT                                      0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK                                        0x0000FFFFL
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT                                   0x7
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT                                   0x8
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT                                 0x9
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT                          0xe
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT                                          0x10
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT                                          0x11
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT                                          0x12
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT                                0x14
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT                                          0x15
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT                                          0x16
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT                                           0x17
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT                                   0x18
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT                                        0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT                  0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT               0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT                       0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK                                     0x00000080L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK                                     0x00000100L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK                                   0x00003E00L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK                            0x00004000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK                                            0x00010000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK                                            0x00020000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK                                            0x00040000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK                                  0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK                                            0x00200000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK                                            0x00400000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK                                             0x00800000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK                                     0x07000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK                                          0x10000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK                    0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK                 0x40000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK                         0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT                      0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT                                          0x1
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT                                       0x2
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT                                          0x12
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT                              0x13
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT                                         0x14
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT                                         0x18
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT                        0x1a
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT                       0x1b
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT                                       0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT                               0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK                        0x00000001L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK                                            0x00000002L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK                                         0x0003FFFCL
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK                                            0x00040000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK                                0x00080000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK                                           0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK                                           0x01000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK                          0x04000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK                         0x08000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK                                         0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK                                 0x40000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT                                 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT                                       0x15
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT                                          0x16
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT                                     0x17
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT                                   0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT                                  0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK                                   0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK                                         0x00200000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK                                            0x00400000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK                                       0x0F800000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK                                     0x70000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK                                    0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT                                   0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT                            0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK                                     0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK                              0x40000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT                                        0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x1
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT                                  0x2
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK                                          0x00000001L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00000002L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK                                    0x00000004L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP7
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+//RCC_EP_DEV0_3_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_3_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
+#define RCC_EP_DEV0_3_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
+//RCC_EP_DEV0_3_EP_PCIE_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
+//RCC_EP_DEV0_3_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
+//RCC_EP_DEV0_3_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
+//RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
+//RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
+#define RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
+//RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                  0x3
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                    0x00000008L
+//RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                           0x1d
+#define RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                             0x20000000L
+//RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT                                         0x4
+#define RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK                                           0x00000010L
+//RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
+//RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
+#define RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
+//RCC_EP_DEV0_3_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_3_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
+#define RCC_EP_DEV0_3_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
+//RCC_EP_DEV0_3_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
+//RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
+//RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                            0x8
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                               0x12
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                   0x18
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                   0x19
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                   0x1a
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT                                   0x1b
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT                                   0x1c
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT                                   0x1d
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT                                   0x1e
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT                                   0x1f
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                              0x00000700L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                 0x00040000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                     0x01000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                     0x02000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                     0x04000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK                                     0x08000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK                                     0x10000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK                                     0x20000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK                                     0x40000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK                                     0x80000000L
+//RCC_EP_DEV0_3_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
+//RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                          0x0
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                          0x1
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                          0x2
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                            0x00000001L
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                            0x00000002L
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                            0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+//RCC_DWN_DEV0_3_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_3_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
+#define RCC_DWN_DEV0_3_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
+//RCC_DWN_DEV0_3_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_3_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_3_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
+//RCC_DWN_DEV0_3_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
+//RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
+#define RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
+//RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
+#define RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
+//RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
+#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
+#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
+#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
+//RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                 0x3
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                   0x00000008L
+//RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT                                                0x11
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT                                        0x15
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK                                                     0x00000001L
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK                                                  0x00020000L
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK                                          0x00E00000L
+//RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT                                             0x18
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                          0x1d
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK                                               0x01000000L
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                            0x20000000L
+//RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT                                    0x2
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK                                      0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+//RCC_DWNP_DEV0_3_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                             0x8
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                    0xb
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                               0x00000700L
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                      0x00000800L
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
+//RCC_DWNP_DEV0_3_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
+//RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                           0x0
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                           0x1
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                           0x2
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                             0x00000001L
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                             0x00000002L
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                             0x00000004L
+//RCC_DWNP_DEV0_3_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                               0x0
+#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
+#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                 0x00000001L
+#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
+//RCC_DWNP_DEV0_3_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_3_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT                                          0xa
+#define RCC_DWNP_DEV0_3_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK                                            0x00000400L
+//RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
+#define RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
+//RCC_DEV0_EPF0_1_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                                0x0
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                       0x1
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                  0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                         0x00000002L
+//RCC_DEV0_EPF0_1_RCC_ERR_LOG_1
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_1__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_1__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_1__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_1__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_1_RCC_ERR_LOG_2
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_2__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_2__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_2__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_2__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                       0x00000001L
+//RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_1
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_1__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_1__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_2
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_2__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_2__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_1
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_1__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_1__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_2
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_2__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_2__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_1
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_1__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_1__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_2
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_2__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_2__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                       0x0
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                            0x1f
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                         0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                              0x80000000L
+//RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1__IOV_ENABLE_MASK                                            0x80000000L
+//RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2__IOV_ENABLE_MASK                                            0x80000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+//RCC_DEV0_2_RCC_ERR_INT_CNTL
+#define RCC_DEV0_2_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT                                0x0
+#define RCC_DEV0_2_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK                                  0x00000001L
+//RCC_DEV0_2_RCC_BACO_CNTL_MISC
+#define RCC_DEV0_2_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT                                                 0x0
+#define RCC_DEV0_2_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT                                                  0x1
+#define RCC_DEV0_2_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK                                                   0x00000001L
+#define RCC_DEV0_2_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK                                                    0x00000002L
+//RCC_DEV0_2_RCC_RESET_EN
+#define RCC_DEV0_2_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT                                                      0xf
+#define RCC_DEV0_2_RCC_RESET_EN__DB_APER_RESET_EN_MASK                                                        0x00008000L
+//RCC_DEV0_3_RCC_VDM_SUPPORT
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT                                                       0x0
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT                                                      0x1
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT                                                  0x2
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT                                        0x3
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT                                    0x4
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK                                                         0x00000001L
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK                                                        0x00000002L
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK                                                    0x00000004L
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK                                          0x00000008L
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK                                      0x00000010L
+//RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT                                 0x0
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT                              0x1
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT                                0x2
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT                                 0x3
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT                           0x4
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT                                  0x5
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT                                 0xb
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT                                 0x12
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT                                0x19
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK                                   0x00000001L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK                                0x00000002L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK                                  0x00000004L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK                                   0x00000008L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK                             0x00000010L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK                                    0x000007E0L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK                                   0x0003F800L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK                                   0x01FC0000L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK                                  0xFE000000L
+//RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT                             0x0
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT                              0x6
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT                                         0xc
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT                                      0x11
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK                               0x0000003FL
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK                                0x00000FC0L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK                                           0x0001F000L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK                                        0x00FE0000L
+//RCC_DEV0_2_RCC_GPUIOV_REGION
+#define RCC_DEV0_2_RCC_GPUIOV_REGION__LFB_REGION__SHIFT                                                       0x0
+#define RCC_DEV0_2_RCC_GPUIOV_REGION__MAX_REGION__SHIFT                                                       0x4
+#define RCC_DEV0_2_RCC_GPUIOV_REGION__LFB_REGION_MASK                                                         0x00000007L
+#define RCC_DEV0_2_RCC_GPUIOV_REGION__MAX_REGION_MASK                                                         0x00000070L
+//RCC_DEV0_2_RCC_GPU_HOSTVM_EN
+#define RCC_DEV0_2_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT                                                    0x0
+#define RCC_DEV0_2_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK                                                      0x00000001L
+//RCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT                              0x0
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT                                    0x1
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK                                0x00000001L
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK                                      0x00000002L
+//RCC_DEV0_2_RCC_CONSOLE_IOV_FIRST_VF_OFFSET
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT                        0x0
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK                          0xFFFFL
+//RCC_DEV0_2_RCC_CONSOLE_IOV_VF_STRIDE
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT                                    0x0
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK                                      0xFFFFL
+//RCC_DEV0_2_RCC_PEER_REG_RANGE0
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT                                                     0x0
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT                                                       0x10
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE0__START_ADDR_MASK                                                       0x0000FFFFL
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE0__END_ADDR_MASK                                                         0xFFFF0000L
+//RCC_DEV0_2_RCC_PEER_REG_RANGE1
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT                                                     0x0
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT                                                       0x10
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE1__START_ADDR_MASK                                                       0x0000FFFFL
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE1__END_ADDR_MASK                                                         0xFFFF0000L
+//RCC_DEV0_3_RCC_BUS_CNTL
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT                                                            0x2
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT                                                           0x3
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT                                                            0x4
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT                                                         0x5
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT                                                        0x6
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT                                                         0x7
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT                                                        0x8
+#define RCC_DEV0_3_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT                                                 0xc
+#define RCC_DEV0_3_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT                                           0xd
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x10
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x11
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x12
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x13
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x14
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x15
+#define RCC_DEV0_3_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT                                                 0x18
+#define RCC_DEV0_3_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                 0x19
+#define RCC_DEV0_3_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT                                            0x1c
+#define RCC_DEV0_3_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                            0x1d
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS_MASK                                                              0x00000004L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS_MASK                                                             0x00000008L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_BM_DIS_MASK                                                              0x00000010L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK                                                           0x00000020L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK                                                          0x00000040L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK                                                           0x00000080L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK                                                          0x00000100L
+#define RCC_DEV0_3_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK                                                   0x00001000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK                                             0x00002000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00010000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00020000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00040000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00080000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00100000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00200000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK                                                   0x01000000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK                                                   0x0E000000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK                                              0x10000000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK                                              0xE0000000L
+//RCC_DEV0_2_RCC_CONFIG_CNTL
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT                                                     0x0
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT                                               0x2
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT                                                        0x3
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK                                                       0x00000001L
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK                                                 0x00000004L
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK                                                          0x00000018L
+//RCC_DEV0_2_RCC_CONFIG_F0_BASE
+#define RCC_DEV0_2_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT                                                         0x0
+#define RCC_DEV0_2_RCC_CONFIG_F0_BASE__F0_BASE_MASK                                                           0xFFFFFFFFL
+//RCC_DEV0_2_RCC_CONFIG_APER_SIZE
+#define RCC_DEV0_2_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT                                                     0x0
+#define RCC_DEV0_2_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK                                                       0xFFFFFFFFL
+//RCC_DEV0_2_RCC_CONFIG_REG_APER_SIZE
+#define RCC_DEV0_2_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT                                             0x0
+#define RCC_DEV0_2_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK                                               0x07FFFFFFL
+//RCC_DEV0_2_RCC_XDMA_LO
+#define RCC_DEV0_2_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT                                                   0x0
+#define RCC_DEV0_2_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT                                                       0x1f
+#define RCC_DEV0_2_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK                                                     0x7FFFFFFFL
+#define RCC_DEV0_2_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK                                                         0x80000000L
+//RCC_DEV0_2_RCC_XDMA_HI
+#define RCC_DEV0_2_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT                                                   0x0
+#define RCC_DEV0_2_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK                                                     0x7FFFFFFFL
+//RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT                                   0x7
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT                                 0x8
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT                                    0x9
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT                                    0xa
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT                                 0xb
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT                                  0xc
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT                                      0xd
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT                      0xe
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT                                 0x10
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT                           0x11
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT                               0x12
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT                     0x13
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK                                     0x00000080L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK                                   0x00000100L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK                                      0x00000200L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK                                      0x00000400L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK                                   0x00000800L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK                                    0x00001000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK                                        0x00002000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK                        0x00004000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK                                   0x00010000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK                             0x00020000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK                                 0x00040000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK                       0x00080000L
+//RCC_DEV0_2_RCC_BUSNUM_CNTL1
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT                                                           0x0
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL1__ID_MASK_MASK                                                             0x000000FFL
+//RCC_DEV0_2_RCC_BUSNUM_LIST0
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID0__SHIFT                                                               0x0
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID1__SHIFT                                                               0x8
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID2__SHIFT                                                               0x10
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID3__SHIFT                                                               0x18
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID0_MASK                                                                 0x000000FFL
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID1_MASK                                                                 0x0000FF00L
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID2_MASK                                                                 0x00FF0000L
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID3_MASK                                                                 0xFF000000L
+//RCC_DEV0_2_RCC_BUSNUM_LIST1
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID4__SHIFT                                                               0x0
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID5__SHIFT                                                               0x8
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID6__SHIFT                                                               0x10
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID7__SHIFT                                                               0x18
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID4_MASK                                                                 0x000000FFL
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID5_MASK                                                                 0x0000FF00L
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID6_MASK                                                                 0x00FF0000L
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID7_MASK                                                                 0xFF000000L
+//RCC_DEV0_2_RCC_BUSNUM_CNTL2
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT                                                    0x0
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT                                                     0x8
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT                                                       0x10
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT                                           0x11
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK                                                      0x000000FFL
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK                                                       0x00000100L
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK                                                         0x00010000L
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK                                             0x00020000L
+//RCC_DEV0_2_RCC_CAPTURE_HOST_BUSNUM
+#define RCC_DEV0_2_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT                                                   0x0
+#define RCC_DEV0_2_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK                                                     0x00000001L
+//RCC_DEV0_2_RCC_HOST_BUSNUM
+#define RCC_DEV0_2_RCC_HOST_BUSNUM__HOST_ID__SHIFT                                                            0x0
+#define RCC_DEV0_2_RCC_HOST_BUSNUM__HOST_ID_MASK                                                              0x0000FFFFL
+//RCC_DEV0_2_RCC_PEER0_FB_OFFSET_HI
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_2_RCC_PEER1_FB_OFFSET_HI
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_2_RCC_PEER2_FB_OFFSET_HI
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_2_RCC_PEER3_FB_OFFSET_HI
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT                                                   0x0
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT                                                   0x8
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT                                                   0x10
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT                                                   0x18
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK                                                     0x000000FFL
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK                                                     0x0000FF00L
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK                                                     0x00FF0000L
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK                                                     0xFF000000L
+//RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT                                                   0x0
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT                                                   0x8
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT                                                   0x10
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT                                                   0x18
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK                                                     0x000000FFL
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK                                                     0x0000FF00L
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK                                                     0x00FF0000L
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK                                                     0xFF000000L
+//RCC_DEV0_3_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_3_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT                                                  0x0
+#define RCC_DEV0_3_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT                                                 0x8
+#define RCC_DEV0_3_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK                                                    0x00000001L
+#define RCC_DEV0_3_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK                                                   0x00000100L
+//RCC_DEV0_3_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT                                             0x0
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT                                              0x1
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT                                             0x2
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT                                          0x3
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT                                             0x10
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK                                               0x00000001L
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK                                                0x00000002L
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK                                               0x00000004L
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK                                            0x00000008L
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK                                               0xFFFF0000L
+//RCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT                                            0x0
+#define RCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT                                            0x8
+#define RCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK                                              0x000000FFL
+#define RCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK                                              0x00001F00L
+//RCC_DEV0_3_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_3_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT                                         0x0
+#define RCC_DEV0_3_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK                                           0x000003FFL
+//RCC_DEV0_3_RCC_MH_ARB_CNTL
+#define RCC_DEV0_3_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT                                                        0x0
+#define RCC_DEV0_3_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT                                                0x1
+#define RCC_DEV0_3_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK                                                          0x00000001L
+#define RCC_DEV0_3_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK                                                  0x00007FFEL
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+//BIF_BX2_CC_BIF_BX_STRAP0
+#define BIF_BX2_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT                                                       0x19
+#define BIF_BX2_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK                                                         0xFE000000L
+//BIF_BX2_CC_BIF_BX_PINSTRAP0
+//BIF_BX2_BIF_MM_INDACCESS_CNTL
+#define BIF_BX2_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT                                                0x1
+#define BIF_BX2_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK                                                  0x00000002L
+//BIF_BX2_BUS_CNTL
+#define BIF_BX2_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT                                                        0x6
+#define BIF_BX2_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT                                                        0x7
+#define BIF_BX2_BUS_CNTL__SET_AZ_TC__SHIFT                                                                    0xa
+#define BIF_BX2_BUS_CNTL__SET_MC_TC__SHIFT                                                                    0xd
+#define BIF_BX2_BUS_CNTL__ZERO_BE_WR_EN__SHIFT                                                                0x10
+#define BIF_BX2_BUS_CNTL__ZERO_BE_RD_EN__SHIFT                                                                0x11
+#define BIF_BX2_BUS_CNTL__RD_STALL_IO_WR__SHIFT                                                               0x12
+#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT                                              0x18
+#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT                                          0x19
+#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT                                         0x1a
+#define BIF_BX2_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT                                        0x1b
+#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT                                          0x1c
+#define BIF_BX2_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT                                                     0x1d
+#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT                                                          0x1e
+#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT                                                          0x1f
+#define BIF_BX2_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK                                                          0x00000040L
+#define BIF_BX2_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK                                                          0x00000080L
+#define BIF_BX2_BUS_CNTL__SET_AZ_TC_MASK                                                                      0x00001C00L
+#define BIF_BX2_BUS_CNTL__SET_MC_TC_MASK                                                                      0x0000E000L
+#define BIF_BX2_BUS_CNTL__ZERO_BE_WR_EN_MASK                                                                  0x00010000L
+#define BIF_BX2_BUS_CNTL__ZERO_BE_RD_EN_MASK                                                                  0x00020000L
+#define BIF_BX2_BUS_CNTL__RD_STALL_IO_WR_MASK                                                                 0x00040000L
+#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK                                                0x01000000L
+#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK                                            0x02000000L
+#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK                                           0x04000000L
+#define BIF_BX2_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK                                          0x08000000L
+#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK                                            0x10000000L
+#define BIF_BX2_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK                                                       0x20000000L
+#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK                                                            0x40000000L
+#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK                                                            0x80000000L
+//BIF_BX2_BIF_SCRATCH0
+#define BIF_BX2_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT                                                             0x0
+#define BIF_BX2_BIF_SCRATCH0__BIF_SCRATCH0_MASK                                                               0xFFFFFFFFL
+//BIF_BX2_BIF_SCRATCH1
+#define BIF_BX2_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT                                                             0x0
+#define BIF_BX2_BIF_SCRATCH1__BIF_SCRATCH1_MASK                                                               0xFFFFFFFFL
+//BIF_BX2_BX_RESET_EN
+#define BIF_BX2_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT                                                  0x10
+#define BIF_BX2_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK                                                    0x00010000L
+//BIF_BX2_MM_CFGREGS_CNTL
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT                                                       0x0
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT                                                        0x6
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT                                                       0x1f
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK                                                         0x00000007L
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK                                                          0x000000C0L
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK                                                         0x80000000L
+//BIF_BX2_BX_RESET_CNTL
+#define BIF_BX2_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT                                                           0x0
+#define BIF_BX2_BX_RESET_CNTL__LINK_TRAIN_EN_MASK                                                             0x00000001L
+//BIF_BX2_INTERRUPT_CNTL
+#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT                                                   0x0
+#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT                                                         0x1
+#define BIF_BX2_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT                                                     0x3
+#define BIF_BX2_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT                                                       0x4
+#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT                                                 0xf
+#define BIF_BX2_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT                                               0x10
+#define BIF_BX2_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT                                   0x11
+#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT                                              0x12
+#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK                                                     0x00000001L
+#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK                                                           0x00000002L
+#define BIF_BX2_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK                                                       0x00000008L
+#define BIF_BX2_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK                                                         0x000000F0L
+#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK                                                   0x00008000L
+#define BIF_BX2_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK                                                 0x00010000L
+#define BIF_BX2_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK                                     0x00020000L
+#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK                                                0x00040000L
+//BIF_BX2_INTERRUPT_CNTL2
+#define BIF_BX2_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT                                                      0x0
+#define BIF_BX2_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK                                                        0xFFFFFFFFL
+//BIF_BX2_CLKREQB_PAD_CNTL
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT                                                        0x0
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT                                                      0x1
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT                                                     0x2
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT                                                    0x3
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT                                                      0x5
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT                                                      0x6
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT                                                      0x7
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT                                                      0x8
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT                                                    0x9
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT                                                     0xa
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT                                                   0xb
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT                                                  0xc
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT                                                        0xd
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK                                                          0x00000001L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK                                                        0x00000002L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK                                                       0x00000004L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK                                                      0x00000018L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK                                                        0x00000020L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK                                                        0x00000040L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK                                                        0x00000080L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK                                                        0x00000100L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK                                                      0x00000200L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK                                                       0x00000400L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK                                                     0x00000800L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK                                                    0x00001000L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK                                                          0x00002000L
+//BIF_BX2_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT                                          0x0
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT                                          0x1
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT                                          0x2
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT                                          0x3
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT                             0xb
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT                                      0xc
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT                                          0xd
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT                                           0xf
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT                                           0x10
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT                   0x18
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK                                            0x00000001L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK                                            0x00000002L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK                                            0x00000004L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK                                            0x00000008L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK                               0x00000800L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK                                        0x00001000L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK                                            0x00002000L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK                                             0x00008000L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK                                             0x00FF0000L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK                     0x01000000L
+//BIF_BX2_BIF_DOORBELL_CNTL
+#define BIF_BX2_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT                                                       0x0
+#define BIF_BX2_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT                                                     0x1
+#define BIF_BX2_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT                                                    0x2
+#define BIF_BX2_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT                                         0x3
+#define BIF_BX2_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT                                                 0x4
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT                                                  0x18
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT                                               0x19
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT                                               0x1a
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT                                               0x1b
+#define BIF_BX2_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK                                                         0x00000001L
+#define BIF_BX2_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK                                                       0x00000002L
+#define BIF_BX2_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK                                                      0x00000004L
+#define BIF_BX2_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK                                           0x00000008L
+#define BIF_BX2_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK                                                   0x00000010L
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK                                                    0x01000000L
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK                                                 0x02000000L
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK                                                 0x04000000L
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK                                                 0x08000000L
+//BIF_BX2_BIF_DOORBELL_INT_CNTL
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT                                       0x0
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT                                      0x1
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT                            0x2
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT                                        0x10
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT                                       0x11
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT                             0x12
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT                                      0x18
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT                                     0x19
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT                           0x1a
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                               0x1c
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1d
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1e
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK                                         0x00000001L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK                                        0x00000002L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK                              0x00000004L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK                                          0x00010000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK                                         0x00020000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK                               0x00040000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK                                        0x01000000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK                                       0x02000000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK                             0x04000000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK                                 0x10000000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x20000000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x40000000L
+//BIF_BX2_BIF_FB_EN
+#define BIF_BX2_BIF_FB_EN__FB_READ_EN__SHIFT                                                                  0x0
+#define BIF_BX2_BIF_FB_EN__FB_WRITE_EN__SHIFT                                                                 0x1
+#define BIF_BX2_BIF_FB_EN__FB_READ_EN_MASK                                                                    0x00000001L
+#define BIF_BX2_BIF_FB_EN__FB_WRITE_EN_MASK                                                                   0x00000002L
+//BIF_BX2_BIF_INTR_CNTL
+#define BIF_BX2_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT                                                        0x0
+#define BIF_BX2_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK                                                          0x00000001L
+//BIF_BX2_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX2_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                        0x0
+#define BIF_BX2_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                          0x7FFFFFFFL
+//BIF_BX2_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX2_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT                                        0x0
+#define BIF_BX2_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK                                          0x7FFFFFFFL
+//BIF_BX2_BACO_CNTL
+#define BIF_BX2_BACO_CNTL__BACO_EN__SHIFT                                                                     0x0
+#define BIF_BX2_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT                                                        0x1
+#define BIF_BX2_BACO_CNTL__BACO_DUMMY_EN__SHIFT                                                               0x2
+#define BIF_BX2_BACO_CNTL__BACO_POWER_OFF__SHIFT                                                              0x3
+#define BIF_BX2_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT                                                          0x5
+#define BIF_BX2_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT                                                          0x6
+#define BIF_BX2_BACO_CNTL__BACO_MODE__SHIFT                                                                   0x8
+#define BIF_BX2_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT                                                         0x9
+#define BIF_BX2_BACO_CNTL__BACO_AUTO_EXIT__SHIFT                                                              0x1f
+#define BIF_BX2_BACO_CNTL__BACO_EN_MASK                                                                       0x00000001L
+#define BIF_BX2_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK                                                          0x00000002L
+#define BIF_BX2_BACO_CNTL__BACO_DUMMY_EN_MASK                                                                 0x00000004L
+#define BIF_BX2_BACO_CNTL__BACO_POWER_OFF_MASK                                                                0x00000008L
+#define BIF_BX2_BACO_CNTL__BACO_DSTATE_BYPASS_MASK                                                            0x00000020L
+#define BIF_BX2_BACO_CNTL__BACO_RST_INTR_MASK_MASK                                                            0x00000040L
+#define BIF_BX2_BACO_CNTL__BACO_MODE_MASK                                                                     0x00000100L
+#define BIF_BX2_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK                                                           0x00000200L
+#define BIF_BX2_BACO_CNTL__BACO_AUTO_EXIT_MASK                                                                0x80000000L
+//BIF_BX2_BIF_BACO_EXIT_TIME0
+#define BIF_BX2_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT                                          0x0
+#define BIF_BX2_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK                                            0x000FFFFFL
+//BIF_BX2_BIF_BACO_EXIT_TIMER1
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT                                         0x0
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT                                            0x18
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT                                                 0x1a
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT                                           0x1b
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT                                            0x1c
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT                                                    0x1d
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT                                     0x1f
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK                                           0x000FFFFFL
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK                                              0x01000000L
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK                                                   0x04000000L
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK                                             0x08000000L
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK                                              0x10000000L
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK                                                      0x60000000L
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK                                       0x80000000L
+//BIF_BX2_BIF_BACO_EXIT_TIMER2
+#define BIF_BX2_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT                                         0x0
+#define BIF_BX2_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK                                           0x000FFFFFL
+//BIF_BX2_BIF_BACO_EXIT_TIMER3
+#define BIF_BX2_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT                                     0x0
+#define BIF_BX2_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK                                       0x000FFFFFL
+//BIF_BX2_BIF_BACO_EXIT_TIMER4
+#define BIF_BX2_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT                                      0x0
+#define BIF_BX2_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK                                        0x000FFFFFL
+//BIF_BX2_MEM_TYPE_CNTL
+#define BIF_BX2_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT                                                        0x0
+#define BIF_BX2_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK                                                          0x00000001L
+//BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT                                                     0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT                                                  0x1
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT                                                    0x8
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK                                                       0x00000001L
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK                                                    0x00000002L
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK                                                      0x00000100L
+//BIF_BX2_NBIF_GFX_ADDR_LUT_0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT                                                              0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_0__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_1
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT                                                              0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_1__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_2
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT                                                              0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_2__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_3
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT                                                              0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_3__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_4
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT                                                              0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_4__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_5
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT                                                              0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_5__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_6
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT                                                              0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_6__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_7
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT                                                              0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_7__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_8
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT                                                              0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_8__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_9
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT                                                              0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_9__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_10
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT                                                             0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_10__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_11
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT                                                             0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_11__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_12
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT                                                             0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_12__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_13
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT                                                             0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_13__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_14
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT                                                             0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_14__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_15
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT                                                             0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_15__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX2_VF_REGWR_EN
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT                                                           0x0
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT                                                           0x1
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT                                                           0x2
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT                                                           0x3
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT                                                           0x4
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT                                                           0x5
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT                                                           0x6
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT                                                           0x7
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT                                                           0x8
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT                                                           0x9
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT                                                          0xa
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT                                                          0xb
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT                                                          0xc
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT                                                          0xd
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT                                                          0xe
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT                                                          0xf
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT                                                          0x10
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT                                                          0x11
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT                                                          0x12
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT                                                          0x13
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT                                                          0x14
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT                                                          0x15
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT                                                          0x16
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT                                                          0x17
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT                                                          0x18
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT                                                          0x19
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT                                                          0x1a
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT                                                          0x1b
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT                                                          0x1c
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT                                                          0x1d
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT                                                          0x1e
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK                                                             0x00000001L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK                                                             0x00000002L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK                                                             0x00000004L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK                                                             0x00000008L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK                                                             0x00000010L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK                                                             0x00000020L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK                                                             0x00000040L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK                                                             0x00000080L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK                                                             0x00000100L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK                                                             0x00000200L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK                                                            0x00000400L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK                                                            0x00000800L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK                                                            0x00001000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK                                                            0x00002000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK                                                            0x00004000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK                                                            0x00008000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK                                                            0x00010000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK                                                            0x00020000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK                                                            0x00040000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK                                                            0x00080000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK                                                            0x00100000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK                                                            0x00200000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK                                                            0x00400000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK                                                            0x00800000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK                                                            0x01000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK                                                            0x02000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK                                                            0x04000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK                                                            0x08000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK                                                            0x10000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK                                                            0x20000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK                                                            0x40000000L
+//BIF_BX2_VF_DOORBELL_EN
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT                                                     0x0
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT                                                     0x1
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT                                                     0x2
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT                                                     0x3
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT                                                     0x4
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT                                                     0x5
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT                                                     0x6
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT                                                     0x7
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT                                                     0x8
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT                                                     0x9
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT                                                    0xa
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT                                                    0xb
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT                                                    0xc
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT                                                    0xd
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT                                                    0xe
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT                                                    0xf
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT                                                    0x10
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT                                                    0x11
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT                                                    0x12
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT                                                    0x13
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT                                                    0x14
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT                                                    0x15
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT                                                    0x16
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT                                                    0x17
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT                                                    0x18
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT                                                    0x19
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT                                                    0x1a
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT                                                    0x1b
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT                                                    0x1c
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT                                                    0x1d
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT                                                    0x1e
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT                                                 0x1f
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK                                                       0x00000001L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK                                                       0x00000002L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK                                                       0x00000004L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK                                                       0x00000008L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK                                                       0x00000010L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK                                                       0x00000020L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK                                                       0x00000040L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK                                                       0x00000080L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK                                                       0x00000100L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK                                                       0x00000200L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK                                                      0x00000400L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK                                                      0x00000800L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK                                                      0x00001000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK                                                      0x00002000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK                                                      0x00004000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK                                                      0x00008000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK                                                      0x00010000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK                                                      0x00020000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK                                                      0x00040000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK                                                      0x00080000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK                                                      0x00100000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK                                                      0x00200000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK                                                      0x00400000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK                                                      0x00800000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK                                                      0x01000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK                                                      0x02000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK                                                      0x04000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK                                                      0x08000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK                                                      0x10000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK                                                      0x20000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK                                                      0x40000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK                                                   0x80000000L
+//BIF_BX2_VF_FB_EN
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF0__SHIFT                                                                 0x0
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF1__SHIFT                                                                 0x1
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF2__SHIFT                                                                 0x2
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF3__SHIFT                                                                 0x3
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF4__SHIFT                                                                 0x4
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF5__SHIFT                                                                 0x5
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF6__SHIFT                                                                 0x6
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF7__SHIFT                                                                 0x7
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF8__SHIFT                                                                 0x8
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF9__SHIFT                                                                 0x9
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF10__SHIFT                                                                0xa
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF11__SHIFT                                                                0xb
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF12__SHIFT                                                                0xc
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF13__SHIFT                                                                0xd
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF14__SHIFT                                                                0xe
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF15__SHIFT                                                                0xf
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF16__SHIFT                                                                0x10
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF17__SHIFT                                                                0x11
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF18__SHIFT                                                                0x12
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF19__SHIFT                                                                0x13
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF20__SHIFT                                                                0x14
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF21__SHIFT                                                                0x15
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF22__SHIFT                                                                0x16
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF23__SHIFT                                                                0x17
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF24__SHIFT                                                                0x18
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF25__SHIFT                                                                0x19
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF26__SHIFT                                                                0x1a
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF27__SHIFT                                                                0x1b
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF28__SHIFT                                                                0x1c
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF29__SHIFT                                                                0x1d
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF30__SHIFT                                                                0x1e
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF0_MASK                                                                   0x00000001L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF1_MASK                                                                   0x00000002L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF2_MASK                                                                   0x00000004L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF3_MASK                                                                   0x00000008L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF4_MASK                                                                   0x00000010L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF5_MASK                                                                   0x00000020L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF6_MASK                                                                   0x00000040L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF7_MASK                                                                   0x00000080L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF8_MASK                                                                   0x00000100L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF9_MASK                                                                   0x00000200L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF10_MASK                                                                  0x00000400L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF11_MASK                                                                  0x00000800L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF12_MASK                                                                  0x00001000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF13_MASK                                                                  0x00002000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF14_MASK                                                                  0x00004000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF15_MASK                                                                  0x00008000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF16_MASK                                                                  0x00010000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF17_MASK                                                                  0x00020000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF18_MASK                                                                  0x00040000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF19_MASK                                                                  0x00080000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF20_MASK                                                                  0x00100000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF21_MASK                                                                  0x00200000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF22_MASK                                                                  0x00400000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF23_MASK                                                                  0x00800000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF24_MASK                                                                  0x01000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF25_MASK                                                                  0x02000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF26_MASK                                                                  0x04000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF27_MASK                                                                  0x08000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF28_MASK                                                                  0x10000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF29_MASK                                                                  0x20000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF30_MASK                                                                  0x40000000L
+//BIF_BX2_VF_REGWR_STATUS
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT                                                   0x0
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT                                                   0x1
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT                                                   0x2
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT                                                   0x3
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT                                                   0x4
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT                                                   0x5
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT                                                   0x6
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT                                                   0x7
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT                                                   0x8
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT                                                   0x9
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT                                                  0xa
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT                                                  0xb
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT                                                  0xc
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT                                                  0xd
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT                                                  0xe
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT                                                  0xf
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT                                                  0x10
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT                                                  0x11
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT                                                  0x12
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT                                                  0x13
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT                                                  0x14
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT                                                  0x15
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT                                                  0x16
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT                                                  0x17
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT                                                  0x18
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT                                                  0x19
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT                                                  0x1a
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT                                                  0x1b
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT                                                  0x1c
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT                                                  0x1d
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT                                                  0x1e
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK                                                     0x00000001L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK                                                     0x00000002L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK                                                     0x00000004L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK                                                     0x00000008L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK                                                     0x00000010L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK                                                     0x00000020L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK                                                     0x00000040L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK                                                     0x00000080L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK                                                     0x00000100L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK                                                     0x00000200L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK                                                    0x00000400L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK                                                    0x00000800L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK                                                    0x00001000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK                                                    0x00002000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK                                                    0x00004000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK                                                    0x00008000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK                                                    0x00010000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK                                                    0x00020000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK                                                    0x00040000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK                                                    0x00080000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK                                                    0x00100000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK                                                    0x00200000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK                                                    0x00400000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK                                                    0x00800000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK                                                    0x01000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK                                                    0x02000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK                                                    0x04000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK                                                    0x08000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK                                                    0x10000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK                                                    0x20000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK                                                    0x40000000L
+//BIF_BX2_VF_DOORBELL_STATUS
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT                                             0x0
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT                                             0x1
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT                                             0x2
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT                                             0x3
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT                                             0x4
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT                                             0x5
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT                                             0x6
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT                                             0x7
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT                                             0x8
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT                                             0x9
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT                                            0xa
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT                                            0xb
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT                                            0xc
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT                                            0xd
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT                                            0xe
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT                                            0xf
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT                                            0x10
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT                                            0x11
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT                                            0x12
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT                                            0x13
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT                                            0x14
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT                                            0x15
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT                                            0x16
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT                                            0x17
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT                                            0x18
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT                                            0x19
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT                                            0x1a
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT                                            0x1b
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT                                            0x1c
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT                                            0x1d
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT                                            0x1e
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK                                               0x00000001L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK                                               0x00000002L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK                                               0x00000004L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK                                               0x00000008L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK                                               0x00000010L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK                                               0x00000020L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK                                               0x00000040L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK                                               0x00000080L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK                                               0x00000100L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK                                               0x00000200L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK                                              0x00000400L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK                                              0x00000800L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK                                              0x00001000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK                                              0x00002000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK                                              0x00004000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK                                              0x00008000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK                                              0x00010000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK                                              0x00020000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK                                              0x00040000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK                                              0x00080000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK                                              0x00100000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK                                              0x00200000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK                                              0x00400000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK                                              0x00800000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK                                              0x01000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK                                              0x02000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK                                              0x04000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK                                              0x08000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK                                              0x10000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK                                              0x20000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK                                              0x40000000L
+//BIF_BX2_VF_FB_STATUS
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT                                                         0x0
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT                                                         0x1
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT                                                         0x2
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT                                                         0x3
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT                                                         0x4
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT                                                         0x5
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT                                                         0x6
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT                                                         0x7
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT                                                         0x8
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT                                                         0x9
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT                                                        0xa
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT                                                        0xb
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT                                                        0xc
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT                                                        0xd
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT                                                        0xe
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT                                                        0xf
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT                                                        0x10
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT                                                        0x11
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT                                                        0x12
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT                                                        0x13
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT                                                        0x14
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT                                                        0x15
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT                                                        0x16
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT                                                        0x17
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT                                                        0x18
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT                                                        0x19
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT                                                        0x1a
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT                                                        0x1b
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT                                                        0x1c
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT                                                        0x1d
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT                                                        0x1e
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK                                                           0x00000001L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK                                                           0x00000002L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK                                                           0x00000004L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK                                                           0x00000008L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK                                                           0x00000010L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK                                                           0x00000020L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK                                                           0x00000040L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK                                                           0x00000080L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK                                                           0x00000100L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK                                                           0x00000200L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK                                                          0x00000400L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK                                                          0x00000800L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK                                                          0x00001000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK                                                          0x00002000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK                                                          0x00004000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK                                                          0x00008000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK                                                          0x00010000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK                                                          0x00020000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK                                                          0x00040000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK                                                          0x00080000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK                                                          0x00100000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK                                                          0x00200000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK                                                          0x00400000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK                                                          0x00800000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK                                                          0x01000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK                                                          0x02000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK                                                          0x04000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK                                                          0x08000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK                                                          0x10000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK                                                          0x20000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK                                                          0x40000000L
+//BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
+#define BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
+//BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
+#define BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
+//BIF_BX2_BIF_RB_CNTL
+#define BIF_BX2_BIF_RB_CNTL__RB_ENABLE__SHIFT                                                                 0x0
+#define BIF_BX2_BIF_RB_CNTL__RB_SIZE__SHIFT                                                                   0x1
+#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT                                                     0x8
+#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT                                                      0x9
+#define BIF_BX2_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT                                                               0x11
+#define BIF_BX2_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT                                                      0x1a
+#define BIF_BX2_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT                                                          0x1d
+#define BIF_BX2_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT                                                     0x1e
+#define BIF_BX2_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT                                                       0x1f
+#define BIF_BX2_BIF_RB_CNTL__RB_ENABLE_MASK                                                                   0x00000001L
+#define BIF_BX2_BIF_RB_CNTL__RB_SIZE_MASK                                                                     0x0000003EL
+#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK                                                       0x00000100L
+#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK                                                        0x00003E00L
+#define BIF_BX2_BIF_RB_CNTL__BIF_RB_TRAN_MASK                                                                 0x00020000L
+#define BIF_BX2_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK                                                        0x1C000000L
+#define BIF_BX2_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK                                                            0x20000000L
+#define BIF_BX2_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK                                                       0x40000000L
+#define BIF_BX2_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK                                                         0x80000000L
+//BIF_BX2_BIF_RB_BASE
+#define BIF_BX2_BIF_RB_BASE__ADDR__SHIFT                                                                      0x0
+#define BIF_BX2_BIF_RB_BASE__ADDR_MASK                                                                        0xFFFFFFFFL
+//BIF_BX2_BIF_RB_RPTR
+#define BIF_BX2_BIF_RB_RPTR__OFFSET__SHIFT                                                                    0x2
+#define BIF_BX2_BIF_RB_RPTR__OFFSET_MASK                                                                      0x0003FFFCL
+//BIF_BX2_BIF_RB_WPTR
+#define BIF_BX2_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT                                                           0x0
+#define BIF_BX2_BIF_RB_WPTR__OFFSET__SHIFT                                                                    0x2
+#define BIF_BX2_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK                                                             0x00000001L
+#define BIF_BX2_BIF_RB_WPTR__OFFSET_MASK                                                                      0x0003FFFCL
+//BIF_BX2_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX2_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT                                                              0x0
+#define BIF_BX2_BIF_RB_WPTR_ADDR_HI__ADDR_MASK                                                                0x000000FFL
+//BIF_BX2_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX2_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT                                                              0x2
+#define BIF_BX2_BIF_RB_WPTR_ADDR_LO__ADDR_MASK                                                                0xFFFFFFFCL
+//BIF_BX2_MAILBOX_INDEX
+#define BIF_BX2_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT                                                           0x0
+#define BIF_BX2_MAILBOX_INDEX__MAILBOX_INDEX_MASK                                                             0x0000001FL
+//BIF_BX2_BIF_VCN0_GPUIOV_CFG_SIZE
+#define BIF_BX2_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT                                         0x0
+#define BIF_BX2_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK                                           0x0000000FL
+//BIF_BX2_BIF_VCN1_GPUIOV_CFG_SIZE
+#define BIF_BX2_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT                                         0x0
+#define BIF_BX2_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK                                           0x0000000FL
+//BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT                                 0x0
+#define BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK                                   0x0000000FL
+//BIF_BX2_BIF_PERSTB_PAD_CNTL
+#define BIF_BX2_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT                                                   0x0
+#define BIF_BX2_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK                                                     0x0000FFFFL
+//BIF_BX2_BIF_PX_EN_PAD_CNTL
+#define BIF_BX2_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT                                                     0x0
+#define BIF_BX2_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK                                                       0x000000FFL
+//BIF_BX2_BIF_REFPADKIN_PAD_CNTL
+#define BIF_BX2_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT                                             0x0
+#define BIF_BX2_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK                                               0x000000FFL
+//BIF_BX2_BIF_CLKREQB_PAD_CNTL
+#define BIF_BX2_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT                                                 0x0
+#define BIF_BX2_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK                                                   0x00FFFFFFL
+//BIF_BX2_BIF_PWRBRK_PAD_CNTL
+#define BIF_BX2_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT                                                   0x0
+#define BIF_BX2_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK                                                     0x000000FFL
+//BIF_BX2_BIF_WAKEB_PAD_CNTL
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT                                                   0x0
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT                                                      0x1
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT                                                         0x2
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT                                                         0x3
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT                                                       0x4
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT                                                     0x5
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT                                                     0x6
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT                                                    0x7
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK                                                     0x00000001L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK                                                        0x00000002L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK                                                           0x00000004L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK                                                           0x00000008L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK                                                         0x00000010L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK                                                       0x00000020L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK                                                       0x00000040L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK                                                      0x00000080L
+//BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT                                                    0x0
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT                                                    0x1
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT                                                  0x2
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT                                                0x3
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT                                                0x4
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT                                              0x5
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK                                                      0x00000001L
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK                                                      0x00000002L
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK                                                    0x00000004L
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK                                                  0x00000008L
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK                                                  0x00000010L
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK                                                0x00000020L
+//BIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL
+#define BIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID__SHIFT                                        0x0
+#define BIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH__SHIFT                                      0x1
+#define BIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID_MASK                                          0x00000001L
+#define BIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH_MASK                                        0xFFFFFFFEL
+//BIF_BX2_BIF_S5_MEM_POWER_CTRL0
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0__SHIFT                                         0x0
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0_MASK                                           0xFFFFFFFFL
+//BIF_BX2_BIF_S5_MEM_POWER_CTRL1
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32__SHIFT                                        0x0
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL__SHIFT                                             0xa
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32_MASK                                          0x000003FFL
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL_MASK                                               0x00000400L
+//BIF_BX2_BIF_S5_DUMMY_REGS
+#define BIF_BX2_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS__SHIFT                                                   0x0
+#define BIF_BX2_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF2_BIF_BME_STATUS
+#define BIF_BX_PF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                                      0x0
+#define BIF_BX_PF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                                0x10
+#define BIF_BX_PF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                                        0x00000001L
+#define BIF_BX_PF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                                  0x00010000L
+//BIF_BX_PF2_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                                0x0
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                             0x1
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                                0x2
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                                    0x3
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                          0x10
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                                       0x11
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                          0x12
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                              0x13
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                                  0x00000001L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                               0x00000002L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                                  0x00000004L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                                      0x00000008L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                            0x00010000L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                                         0x00020000L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                            0x00040000L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                                0x00080000L
+//BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT          0x0
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK            0xFFFFFFFFL
+//BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT            0x0
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK              0xFFFFFFFFL
+//BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT                      0x0
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT                    0x1
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT                    0x8
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK                        0x00000001L
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK                      0x00000002L
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK                      0x000FFF00L
+//BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                                    0x0
+#define BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                                      0x00000001L
+//BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                                    0x0
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                                      0x00000001L
+//BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT                          0x0
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                            0x00000001L
+//BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT                0x0
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK                  0x00000001L
+//BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT                                                         0x0
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT                                                         0x1
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT                                                         0x2
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT                                                         0x3
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT                                                         0x4
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT                                                         0x5
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT                                                         0x6
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT                                                         0x7
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT                                                         0x8
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT                                                         0x9
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT                                                       0xa
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT                                                       0xb
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT                                                   0xc
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT                                                   0xd
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT                                                   0xe
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT                                                   0xf
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT                                                   0x10
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT                                                   0x11
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT                                                   0x12
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT                                                   0x13
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT                                                   0x14
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT                                                   0x15
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT                                                  0x16
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT                                                  0x17
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT                                                  0x18
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT                                                  0x19
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT                                                  0x1a
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT                                                  0x1b
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT                                                  0x1c
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT                                                  0x1d
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT                                                  0x1e
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT                                                  0x1f
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK                                                           0x00000001L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK                                                           0x00000002L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK                                                           0x00000004L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK                                                           0x00000008L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK                                                           0x00000010L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK                                                           0x00000020L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK                                                           0x00000040L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK                                                           0x00000080L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK                                                           0x00000100L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK                                                           0x00000200L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK                                                         0x00000400L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK                                                         0x00000800L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK                                                     0x00001000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK                                                     0x00002000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK                                                     0x00004000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK                                                     0x00008000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK                                                     0x00010000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK                                                     0x00020000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK                                                     0x00040000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK                                                     0x00080000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK                                                     0x00100000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK                                                     0x00200000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK                                                    0x00400000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK                                                    0x00800000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK                                                    0x01000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK                                                    0x02000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK                                                    0x04000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK                                                    0x08000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK                                                    0x10000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK                                                    0x20000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK                                                    0x40000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK                                                    0x80000000L
+//BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT                                                    0x0
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT                                                    0x1
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT                                                    0x2
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT                                                    0x3
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT                                                    0x4
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT                                                    0x5
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT                                                    0x6
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT                                                    0x7
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT                                                    0x8
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT                                                    0x9
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT                                                  0xa
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT                                                  0xb
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT                                              0xc
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT                                              0xd
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT                                              0xe
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT                                              0xf
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT                                              0x10
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT                                              0x11
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT                                              0x12
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT                                              0x13
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT                                              0x14
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT                                              0x15
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT                                             0x16
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT                                             0x17
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT                                             0x18
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT                                             0x19
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT                                             0x1a
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT                                             0x1b
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT                                             0x1c
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT                                             0x1d
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT                                             0x1e
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT                                             0x1f
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK                                                      0x00000001L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK                                                      0x00000002L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK                                                      0x00000004L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK                                                      0x00000008L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK                                                      0x00000010L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK                                                      0x00000020L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK                                                      0x00000040L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK                                                      0x00000080L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK                                                      0x00000100L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK                                                      0x00000200L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK                                                    0x00000400L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK                                                    0x00000800L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK                                                0x00001000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK                                                0x00002000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK                                                0x00004000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK                                                0x00008000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK                                                0x00010000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK                                                0x00020000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK                                                0x00040000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK                                                0x00080000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK                                                0x00100000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK                                                0x00200000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK                                               0x00400000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK                                               0x00800000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK                                               0x01000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK                                               0x02000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK                                               0x04000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK                                               0x08000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK                                               0x10000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK                                               0x20000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK                                               0x40000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK                                               0x80000000L
+//BIF_BX_PF2_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                              0x0
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                              0x1
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                              0x2
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                              0x3
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                              0x4
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                              0x5
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                              0x6
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                              0x7
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                              0x8
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                              0x9
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                            0xa
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                            0xb
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                                        0xc
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                                        0xd
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                                        0xe
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                                        0xf
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                                        0x10
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                                        0x11
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                                        0x12
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                                        0x13
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                                        0x14
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                                        0x15
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                                       0x16
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                                       0x17
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                                       0x18
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                                       0x19
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                                       0x1a
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                                       0x1b
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                                       0x1c
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                                       0x1d
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                                       0x1e
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                                       0x1f
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP0_MASK                                                                0x00000001L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP1_MASK                                                                0x00000002L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP2_MASK                                                                0x00000004L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP3_MASK                                                                0x00000008L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP4_MASK                                                                0x00000010L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP5_MASK                                                                0x00000020L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP6_MASK                                                                0x00000040L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP7_MASK                                                                0x00000080L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP8_MASK                                                                0x00000100L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP9_MASK                                                                0x00000200L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                              0x00000400L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                              0x00000800L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                                          0x00001000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                                          0x00002000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                                          0x00004000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                                          0x00008000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                                          0x00010000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                                          0x00020000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                                          0x00040000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                                          0x00080000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                                          0x00100000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                                          0x00200000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                                         0x00400000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                                         0x00800000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                                         0x01000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                                         0x02000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                                         0x04000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                                         0x08000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                                         0x10000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                                         0x20000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                                         0x40000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                                         0x80000000L
+//BIF_BX_PF2_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                             0x0
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                             0x1
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                             0x2
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                             0x3
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                             0x4
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                             0x5
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                             0x6
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                             0x7
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                             0x8
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                             0x9
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                           0xa
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                           0xb
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                                       0xc
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                                       0xd
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                                       0xe
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                                       0xf
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                                       0x10
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                                       0x11
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                                       0x12
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                                       0x13
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                                       0x14
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                                       0x15
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                                      0x16
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                                      0x17
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                                      0x18
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                                      0x19
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                                      0x1a
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                                      0x1b
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                                      0x1c
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                                      0x1d
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                                      0x1e
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                                      0x1f
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP0_MASK                                                               0x00000001L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP1_MASK                                                               0x00000002L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP2_MASK                                                               0x00000004L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP3_MASK                                                               0x00000008L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP4_MASK                                                               0x00000010L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP5_MASK                                                               0x00000020L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP6_MASK                                                               0x00000040L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP7_MASK                                                               0x00000080L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP8_MASK                                                               0x00000100L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP9_MASK                                                               0x00000200L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                             0x00000400L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                             0x00000800L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                                         0x00001000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                                         0x00002000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                                         0x00004000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                                         0x00008000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                                         0x00010000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                                         0x00020000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                                         0x00040000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                                         0x00080000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                                         0x00100000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                                         0x00200000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                                        0x00400000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                                        0x00800000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                                        0x01000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                                        0x02000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                                        0x04000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                                        0x08000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                                        0x10000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                                        0x20000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                                        0x40000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                                        0x80000000L
+//BIF_BX_PF2_BIF_TRANS_PENDING
+#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                            0x0
+#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                            0x1
+#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                              0x00000001L
+#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                              0x00000002L
+//BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                                0x0
+#define BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                                  0x00000001L
+//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_CONTROL
+#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                                      0x0
+#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                                        0x1
+#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                                      0x8
+#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                                        0x9
+#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                                        0x00000001L
+#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                          0x00000002L
+#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                                        0x00000100L
+#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                          0x00000200L
+//BIF_BX_PF2_MAILBOX_INT_CNTL
+#define BIF_BX_PF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                                      0x0
+#define BIF_BX_PF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                                        0x1
+#define BIF_BX_PF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                                        0x00000001L
+#define BIF_BX_PF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                          0x00000002L
+//BIF_BX_PF2_BIF_VMHV_MAILBOX
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                                      0x0
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                                    0x1
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                                         0x8
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                                        0xf
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                                         0x10
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                                        0x17
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                          0x18
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                          0x19
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                                        0x00000001L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                                      0x00000002L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                           0x00000F00L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                          0x00008000L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                           0x000F0000L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                          0x00800000L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                            0x01000000L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                            0x02000000L
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+//GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN0_FAST_WRITE_RESPONSE_EN__SHIFT                             0x0
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN1_FAST_WRITE_RESPONSE_EN__SHIFT                             0x1
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN2_FAST_WRITE_RESPONSE_EN__SHIFT                             0x2
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN3_FAST_WRITE_RESPONSE_EN__SHIFT                             0x3
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__FWR_NORMAL_ARB_MODE__SHIFT                                       0x10
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN0_FAST_WRITE_RESPONSE_EN_MASK                               0x00000001L
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN1_FAST_WRITE_RESPONSE_EN_MASK                               0x00000002L
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN2_FAST_WRITE_RESPONSE_EN_MASK                               0x00000004L
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN3_FAST_WRITE_RESPONSE_EN_MASK                               0x00000008L
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__FWR_NORMAL_ARB_MODE_MASK                                         0x00010000L
+//GDC1_NGDC_SDP_PORT_CTRL
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT                                                 0x0
+#define GDC1_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT                                   0xf
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT                                               0x10
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK                                                   0x000000FFL
+#define GDC1_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN_MASK                                     0x00008000L
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK                                                 0x000F0000L
+//GDC1_SHUB_REGS_IF_CTL
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT                                0x0
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK                                  0x00000001L
+//GDC1_NGDC_MP4SDP_CTRL
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN__SHIFT                                           0x0
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL__SHIFT                                          0x1
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN__SHIFT                                           0x4
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL__SHIFT                                          0x5
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN__SHIFT                                           0x8
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL__SHIFT                                          0x9
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN_MASK                                             0x00000001L
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL_MASK                                            0x00000006L
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN_MASK                                             0x00000010L
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL_MASK                                            0x00000060L
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN_MASK                                             0x00000100L
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL_MASK                                            0x00000600L
+//GDC1_NGDC_MGCG_CTRL
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT                                                              0x0
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT                                                            0x1
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT                                                      0x2
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT                                                         0xa
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT                                                         0xb
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT                                                         0xc
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT                                                         0xd
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK                                                                0x00000001L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK                                                              0x00000002L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK                                                        0x000003FCL
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK                                                           0x00000400L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK                                                           0x00000800L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK                                                           0x00001000L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK                                                           0x00002000L
+//GDC1_NGDC_RESERVED_0
+#define GDC1_NGDC_RESERVED_0__RESERVED__SHIFT                                                                 0x0
+#define GDC1_NGDC_RESERVED_0__RESERVED_MASK                                                                   0xFFFFFFFFL
+//GDC1_NGDC_RESERVED_1
+#define GDC1_NGDC_RESERVED_1__RESERVED__SHIFT                                                                 0x0
+#define GDC1_NGDC_RESERVED_1__RESERVED_MASK                                                                   0xFFFFFFFFL
+//GDC1_NGDC_SDP_PORT_CTRL_SOCCLK
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT                                   0x0
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_POOL_NUM_SOCCLK__SHIFT                                    0x8
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC0_RSV__SHIFT                                       0x10
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC5_RSV__SHIFT                                       0x14
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC6_RSV__SHIFT                                       0x18
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_H__SHIFT                                 0x1c
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK                                     0x000000FFL
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_POOL_NUM_SOCCLK_MASK                                      0x0000FF00L
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC0_RSV_MASK                                         0x000F0000L
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC5_RSV_MASK                                         0x00F00000L
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC6_RSV_MASK                                         0x0F000000L
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_H_MASK                                   0xF0000000L
+//GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC0_RSV__SHIFT                                        0x0
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC1_RSV__SHIFT                                        0x4
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC5_RSV__SHIFT                                        0x8
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC6_RSV__SHIFT                                        0xc
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC0_RSV__SHIFT                                   0x10
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC1_RSV__SHIFT                                   0x14
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC0_RSV_MASK                                          0x0000000FL
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC1_RSV_MASK                                          0x000000F0L
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC5_RSV_MASK                                          0x00000F00L
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC6_RSV_MASK                                          0x0000F000L
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC0_RSV_MASK                                     0x000F0000L
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC1_RSV_MASK                                     0x00F00000L
+//GDC1_NBIF_GFX_DOORBELL_STATUS
+#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT                                          0x0
+#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK                                            0x00000001L
+//GDC1_BIF_SDMA0_DOORBELL_RANGE
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
+//GDC1_BIF_SDMA1_DOORBELL_RANGE
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
+//GDC1_BIF_IH_DOORBELL_RANGE
+#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT                                                             0x2
+#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT                                                               0x10
+#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET_MASK                                                               0x00000FFCL
+#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE_MASK                                                                 0x001F0000L
+//GDC1_BIF_VCN0_DOORBELL_RANGE
+#define GDC1_BIF_VCN0_DOORBELL_RANGE__OFFSET__SHIFT                                                           0x2
+#define GDC1_BIF_VCN0_DOORBELL_RANGE__SIZE__SHIFT                                                             0x10
+#define GDC1_BIF_VCN0_DOORBELL_RANGE__OFFSET_MASK                                                             0x00000FFCL
+#define GDC1_BIF_VCN0_DOORBELL_RANGE__SIZE_MASK                                                               0x001F0000L
+//GDC1_BIF_RLC_DOORBELL_RANGE
+#define GDC1_BIF_RLC_DOORBELL_RANGE__OFFSET__SHIFT                                                            0x2
+#define GDC1_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT                                                              0x10
+#define GDC1_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK                                                              0x00000FFCL
+#define GDC1_BIF_RLC_DOORBELL_RANGE__SIZE_MASK                                                                0x001F0000L
+//GDC1_BIF_SDMA2_DOORBELL_RANGE
+#define GDC1_BIF_SDMA2_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
+#define GDC1_BIF_SDMA2_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
+#define GDC1_BIF_SDMA2_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
+#define GDC1_BIF_SDMA2_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
+//GDC1_BIF_SDMA3_DOORBELL_RANGE
+#define GDC1_BIF_SDMA3_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
+#define GDC1_BIF_SDMA3_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
+#define GDC1_BIF_SDMA3_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
+#define GDC1_BIF_SDMA3_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
+//GDC1_BIF_VCN1_DOORBELL_RANGE
+#define GDC1_BIF_VCN1_DOORBELL_RANGE__OFFSET__SHIFT                                                           0x2
+#define GDC1_BIF_VCN1_DOORBELL_RANGE__SIZE__SHIFT                                                             0x10
+#define GDC1_BIF_VCN1_DOORBELL_RANGE__OFFSET_MASK                                                             0x00000FFCL
+#define GDC1_BIF_VCN1_DOORBELL_RANGE__SIZE_MASK                                                               0x001F0000L
+//GDC1_BIF_SDMA4_DOORBELL_RANGE
+#define GDC1_BIF_SDMA4_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
+#define GDC1_BIF_SDMA4_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
+#define GDC1_BIF_SDMA4_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
+#define GDC1_BIF_SDMA4_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
+//GDC1_BIF_SDMA5_DOORBELL_RANGE
+#define GDC1_BIF_SDMA5_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
+#define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
+#define GDC1_BIF_SDMA5_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
+#define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
+//GDC1_ATDMA_MISC_CNTL
+#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT                                                             0x0
+#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT                                                 0x1
+#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT                                                           0x2
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT                                                           0x8
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT                                                           0x10
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT                                                           0x18
+#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK                                                               0x00000001L
+#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK                                                   0x00000002L
+#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK                                                             0x0000000CL
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK                                                             0x0000FF00L
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK                                                             0x00FF0000L
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK                                                             0xFF000000L
+//GDC1_BIF_DOORBELL_FENCE_CNTL
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT                                         0x0
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT                                      0x1
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT                                      0x2
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE__SHIFT                                        0x4
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE__SHIFT                                      0x5
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE__SHIFT                                      0x6
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE__SHIFT                                      0x7
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE__SHIFT                                      0x8
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT                                  0x10
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK                                           0x00000001L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK                                        0x00000002L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK                                        0x00000004L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE_MASK                                          0x00000010L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE_MASK                                        0x00000020L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE_MASK                                        0x00000040L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE_MASK                                        0x00000080L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE_MASK                                        0x00000100L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK                                    0x00010000L
+//GDC1_S2A_MISC_CNTL
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT                                           0x0
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT                                           0x1
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT                                              0x2
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS__SHIFT                                             0x5
+#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT                                                               0x8
+#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT                                                                0xa
+#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT                                                              0xc
+#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT                                                              0x10
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS__SHIFT                                           0x18
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS__SHIFT                                           0x19
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS__SHIFT                                           0x1a
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS__SHIFT                                           0x1b
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK                                             0x00000001L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK                                             0x00000002L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK                                                0x00000004L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS_MASK                                               0x00000020L
+#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK                                                                 0x00000300L
+#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK                                                                  0x00000C00L
+#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK                                                                0x00003000L
+#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK                                                                0x000F0000L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS_MASK                                             0x01000000L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS_MASK                                             0x02000000L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS_MASK                                             0x04000000L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS_MASK                                             0x08000000L
+//GDC1_NGDC_EARLY_WAKEUP_CTRL
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT                                0x0
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT                               0x1
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT                                0x2
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK                                  0x00000001L
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK                                 0x00000002L
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK                                  0x00000004L
+//GDC1_NGDC_PG_MISC_CTRL
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT                                                   0xa
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT                                                      0xd
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT                                                   0xe
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT                                                      0x10
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT                                        0x18
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT                                              0x1f
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK                                                     0x00000400L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK                                                        0x00002000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK                                                     0x00004000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK                                                        0x00010000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK                                          0x3F000000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK                                                0x80000000L
+//GDC1_NGDC_PGMST_CTRL
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT                                                   0x0
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT                                                           0x8
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT                                               0xa
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT                                                   0xe
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK                                                     0x000000FFL
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK                                                             0x00000100L
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK                                                 0x00003C00L
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK                                                     0x0000C000L
+//GDC1_NGDC_PGSLV_CTRL
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT                                       0x0
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT                                       0x5
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT                                          0xa
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_2_IDLE_HYSTERESIS__SHIFT                                       0xf
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_3_IDLE_HYSTERESIS__SHIFT                                       0x14
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK                                         0x0000001FL
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK                                         0x000003E0L
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK                                            0x00007C00L
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_2_IDLE_HYSTERESIS_MASK                                         0x000F8000L
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_3_IDLE_HYSTERESIS_MASK                                         0x01F00000L
+//GDC1_SHUBCLK_DPM_CTRL
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_MODE__SHIFT                                                        0x0
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_ENABLE__SHIFT                                                      0x1
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMAWR_QUANT__SHIFT                                                 0x2
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMARD_QUANT__SHIFT                                                 0xa
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_CLEAR__SHIFT                                                       0x12
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_MODE_MASK                                                          0x00000001L
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_ENABLE_MASK                                                        0x00000002L
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMAWR_QUANT_MASK                                                   0x000003FCL
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMARD_QUANT_MASK                                                   0x0003FC00L
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_CLEAR_MASK                                                         0x00040000L
+//GDC1_SHUBCLK_DPM_WR_WEIGHT
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_4B__SHIFT                                           0x0
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_8B__SHIFT                                           0x5
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_16B__SHIFT                                          0xa
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_32B__SHIFT                                          0xf
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_64B__SHIFT                                          0x14
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_4B_MASK                                             0x0000001FL
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_8B_MASK                                             0x000003E0L
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_16B_MASK                                            0x00007C00L
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_32B_MASK                                            0x000F8000L
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_64B_MASK                                            0x01F00000L
+//GDC1_SHUBCLK_DPM_RD_WEIGHT
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_4B__SHIFT                                           0x0
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_8B__SHIFT                                           0x5
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_16B__SHIFT                                          0xa
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_32B__SHIFT                                          0xf
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_64B__SHIFT                                          0x14
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_4B_MASK                                             0x0000001FL
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_8B_MASK                                             0x000003E0L
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_16B_MASK                                            0x00007C00L
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_32B_MASK                                            0x000F8000L
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_64B_MASK                                            0x01F00000L
+//GDC1_SHUBCLK_DPM_WR_CNT
+#define GDC1_SHUBCLK_DPM_WR_CNT__SHUBCLK_DPM_WR_COUNTER__SHIFT                                                0x0
+#define GDC1_SHUBCLK_DPM_WR_CNT__SHUBCLK_DPM_WR_COUNTER_MASK                                                  0xFFFFFFFFL
+//GDC1_SHUBCLK_DPM_RD_CNT
+#define GDC1_SHUBCLK_DPM_RD_CNT__SHUBCLK_DPM_RD_COUNTER__SHIFT                                                0x0
+#define GDC1_SHUBCLK_DPM_RD_CNT__SHUBCLK_DPM_RD_COUNTER_MASK                                                  0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_1__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_1__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_2__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_2__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_1__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_1__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_2__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_2__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_1__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_1__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_2__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_2__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                                0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                  0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_1__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_1__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_2__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_2__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_1__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_1__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_2__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_2__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_1__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_1__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_2__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_2__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_1__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_1__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_2__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_2__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                                0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                  0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_1__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_1__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_2__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_2__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_1__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_1__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_2__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_2__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_1__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_1__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_2__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_2__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_1__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_1__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_2__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_2__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                                0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                  0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_1__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_1__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_2__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_2__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_1__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_1__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_2__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_2__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_1__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_1__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_2__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_2__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_1__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_1__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_2__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_2__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                                0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                  0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_1__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_1__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_2__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_2__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                               0x1
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT                                               0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT                                               0x3
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                                 0x00000001L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                                 0x00000002L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK                                                 0x00000004L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK                                                 0x00000008L
+//RCC_DEV0_EPF0_1_GFXMSIX_PBA_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_2__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_3__SHIFT                                             0x3
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_2_MASK                                               0x00000004L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_3_MASK                                               0x00000008L
+//RCC_DEV0_EPF0_1_GFXMSIX_PBA_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_2__SHIFT                                             0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_3__SHIFT                                             0x3
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_2_MASK                                               0x00000004L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_3_MASK                                               0x00000008L
+
+
+// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
+
+
+
+
+
+
+
+
+// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+//BIFPLR0_1_VENDOR_ID
+#define BIFPLR0_1_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR0_1_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR0_1_DEVICE_ID
+#define BIFPLR0_1_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR0_1_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR0_1_COMMAND
+#define BIFPLR0_1_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR0_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR0_1_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR0_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR0_1_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR0_1_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR0_1_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR0_1_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR0_1_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR0_1_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR0_1_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR0_1_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR0_1_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR0_1_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR0_1_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR0_1_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR0_1_STATUS
+#define BIFPLR0_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR0_1_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR0_1_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR0_1_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR0_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR0_1_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR0_1_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR0_1_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR0_1_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR0_1_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR0_1_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR0_1_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR0_1_REVISION_ID
+#define BIFPLR0_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR0_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR0_1_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR0_1_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR0_1_PROG_INTERFACE
+#define BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR0_1_SUB_CLASS
+#define BIFPLR0_1_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR0_1_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR0_1_BASE_CLASS
+#define BIFPLR0_1_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR0_1_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR0_1_CACHE_LINE
+#define BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR0_1_LATENCY
+#define BIFPLR0_1_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR0_1_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR0_1_HEADER
+#define BIFPLR0_1_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR0_1_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR0_1_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR0_1_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR0_1_BIST
+#define BIFPLR0_1_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR0_1_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR0_1_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR0_1_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR0_1_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR0_1_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR0_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR0_1_IO_BASE_LIMIT
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR0_1_SECONDARY_STATUS
+#define BIFPLR0_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR0_1_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR0_1_MEM_BASE_LIMIT
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR0_1_PREF_BASE_LIMIT
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR0_1_PREF_BASE_UPPER
+#define BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_1_PREF_LIMIT_UPPER
+#define BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR0_1_IO_BASE_LIMIT_HI
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR0_1_CAP_PTR
+#define BIFPLR0_1_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR0_1_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR0_1_ROM_BASE_ADDR
+#define BIFPLR0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR0_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR0_1_INTERRUPT_LINE
+#define BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR0_1_INTERRUPT_PIN
+#define BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR0_1_IRQ_BRIDGE_CNTL
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR0_1_EXT_BRIDGE_CNTL
+#define BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR0_1_VENDOR_CAP_LIST
+#define BIFPLR0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR0_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR0_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR0_1_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR0_1_ADAPTER_ID_W
+#define BIFPLR0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR0_1_PMI_CAP_LIST
+#define BIFPLR0_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR0_1_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR0_1_PMI_CAP
+#define BIFPLR0_1_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR0_1_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR0_1_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR0_1_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR0_1_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR0_1_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR0_1_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR0_1_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR0_1_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR0_1_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR0_1_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR0_1_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR0_1_PMI_STATUS_CNTL
+#define BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR0_1_PCIE_CAP_LIST
+#define BIFPLR0_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR0_1_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR0_1_PCIE_CAP
+#define BIFPLR0_1_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR0_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR0_1_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR0_1_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR0_1_DEVICE_CAP
+#define BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR0_1_DEVICE_CNTL
+#define BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR0_1_DEVICE_STATUS
+#define BIFPLR0_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR0_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR0_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR0_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR0_1_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR0_1_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR0_1_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR0_1_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR0_1_LINK_CAP
+#define BIFPLR0_1_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR0_1_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR0_1_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR0_1_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR0_1_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR0_1_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR0_1_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR0_1_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR0_1_LINK_CNTL
+#define BIFPLR0_1_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR0_1_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR0_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR0_1_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR0_1_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR0_1_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR0_1_LINK_STATUS
+#define BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR0_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR0_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR0_1_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR0_1_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR0_1_SLOT_CAP
+#define BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR0_1_SLOT_CNTL
+#define BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR0_1_SLOT_STATUS
+#define BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR0_1_ROOT_CNTL
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR0_1_ROOT_CAP
+#define BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR0_1_ROOT_STATUS
+#define BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR0_1_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR0_1_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR0_1_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR0_1_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR0_1_DEVICE_CAP2
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR0_1_DEVICE_CNTL2
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR0_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR0_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR0_1_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR0_1_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR0_1_DEVICE_STATUS2
+#define BIFPLR0_1_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR0_1_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR0_1_LINK_CAP2
+#define BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR0_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR0_1_LINK_CNTL2
+#define BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR0_1_LINK_STATUS2
+#define BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR0_1_SLOT_CAP2
+#define BIFPLR0_1_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR0_1_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR0_1_SLOT_CNTL2
+#define BIFPLR0_1_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR0_1_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR0_1_SLOT_STATUS2
+#define BIFPLR0_1_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR0_1_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR0_1_MSI_CAP_LIST
+#define BIFPLR0_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR0_1_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR0_1_MSI_MSG_CNTL
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR0_1_MSI_MSG_ADDR_LO
+#define BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR0_1_MSI_MSG_ADDR_HI
+#define BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_1_MSI_MSG_DATA
+#define BIFPLR0_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR0_1_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR0_1_MSI_MSG_DATA_64
+#define BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR0_1_SSID_CAP_LIST
+#define BIFPLR0_1_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR0_1_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR0_1_SSID_CAP
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR0_1_MSI_MAP_CAP_LIST
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR0_1_MSI_MAP_CAP
+#define BIFPLR0_1_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR0_1_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR0_1_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR0_1_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR0_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR0_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR0_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR0_1_PCIE_PORT_VC_CNTL
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR0_1_PCIE_PORT_VC_STATUS
+#define BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR0_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR0_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR0_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR0_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR0_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR0_1_PCIE_CORR_ERR_MASK
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR0_1_PCIE_HDR_LOG0
+#define BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_HDR_LOG1
+#define BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_HDR_LOG2
+#define BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_HDR_LOG3
+#define BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR0_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR0_1_PCIE_ERR_SRC_ID
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR0_1_PCIE_LINK_CNTL3
+#define BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR0_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR0_1_PCIE_ACS_CAP
+#define BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR0_1_PCIE_ACS_CNTL
+#define BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR0_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR0_1_PCIE_MC_CAP
+#define BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR0_1_PCIE_MC_CNTL
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR0_1_PCIE_MC_ADDR0
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR0_1_PCIE_MC_ADDR1
+#define BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_RCV0
+#define BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_RCV1
+#define BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR0_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR0_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR0_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR0_1_PCIE_DPC_CAP_LIST
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR0_1_PCIE_DPC_CNTL
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR0_1_PCIE_DPC_STATUS
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_STATUS
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_MASK
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR0_1_PCIE_ESM_CAP_LIST
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR0_1_PCIE_ESM_HEADER_1
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR0_1_PCIE_ESM_HEADER_2
+#define BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR0_1_PCIE_ESM_STATUS
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR0_1_PCIE_ESM_CTRL
+#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR0_1_PCIE_ESM_CAP_1
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_2
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_3
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR0_1_PCIE_ESM_CAP_4
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_5
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_6
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_7
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR0_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR0_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR0_1_LINK_CAP_16GT
+#define BIFPLR0_1_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR0_1_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR0_1_LINK_CNTL_16GT
+#define BIFPLR0_1_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR0_1_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR0_1_LINK_STATUS_16GT
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR0_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR0_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR0_1_MARGINING_PORT_CAP
+#define BIFPLR0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR0_1_MARGINING_PORT_STATUS
+#define BIFPLR0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR0_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR0_1_PCIE_CCIX_HEADER_1
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR0_1_PCIE_CCIX_HEADER_2
+#define BIFPLR0_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR0_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR0_1_PCIE_CCIX_CAP
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR0_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR0_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR0_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR0_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR0_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR0_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR0_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR0_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR0_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR0_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR0_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR0_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR0_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR0_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR0_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+//BIFPLR1_1_VENDOR_ID
+#define BIFPLR1_1_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR1_1_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR1_1_DEVICE_ID
+#define BIFPLR1_1_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR1_1_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR1_1_COMMAND
+#define BIFPLR1_1_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR1_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR1_1_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR1_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR1_1_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR1_1_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR1_1_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR1_1_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR1_1_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR1_1_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR1_1_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR1_1_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR1_1_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR1_1_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR1_1_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR1_1_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR1_1_STATUS
+#define BIFPLR1_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR1_1_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR1_1_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR1_1_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR1_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR1_1_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR1_1_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR1_1_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR1_1_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR1_1_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR1_1_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR1_1_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR1_1_REVISION_ID
+#define BIFPLR1_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR1_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR1_1_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR1_1_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR1_1_PROG_INTERFACE
+#define BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR1_1_SUB_CLASS
+#define BIFPLR1_1_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR1_1_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR1_1_BASE_CLASS
+#define BIFPLR1_1_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR1_1_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR1_1_CACHE_LINE
+#define BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR1_1_LATENCY
+#define BIFPLR1_1_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR1_1_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR1_1_HEADER
+#define BIFPLR1_1_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR1_1_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR1_1_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR1_1_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR1_1_BIST
+#define BIFPLR1_1_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR1_1_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR1_1_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR1_1_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR1_1_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR1_1_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR1_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR1_1_IO_BASE_LIMIT
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR1_1_SECONDARY_STATUS
+#define BIFPLR1_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR1_1_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR1_1_MEM_BASE_LIMIT
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR1_1_PREF_BASE_LIMIT
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR1_1_PREF_BASE_UPPER
+#define BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_1_PREF_LIMIT_UPPER
+#define BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR1_1_IO_BASE_LIMIT_HI
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR1_1_CAP_PTR
+#define BIFPLR1_1_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR1_1_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR1_1_ROM_BASE_ADDR
+#define BIFPLR1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR1_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR1_1_INTERRUPT_LINE
+#define BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR1_1_INTERRUPT_PIN
+#define BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR1_1_IRQ_BRIDGE_CNTL
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR1_1_EXT_BRIDGE_CNTL
+#define BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR1_1_VENDOR_CAP_LIST
+#define BIFPLR1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR1_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR1_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR1_1_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR1_1_ADAPTER_ID_W
+#define BIFPLR1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR1_1_PMI_CAP_LIST
+#define BIFPLR1_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR1_1_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR1_1_PMI_CAP
+#define BIFPLR1_1_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR1_1_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR1_1_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR1_1_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR1_1_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR1_1_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR1_1_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR1_1_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR1_1_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR1_1_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR1_1_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR1_1_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR1_1_PMI_STATUS_CNTL
+#define BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR1_1_PCIE_CAP_LIST
+#define BIFPLR1_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR1_1_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR1_1_PCIE_CAP
+#define BIFPLR1_1_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR1_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR1_1_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR1_1_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR1_1_DEVICE_CAP
+#define BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR1_1_DEVICE_CNTL
+#define BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR1_1_DEVICE_STATUS
+#define BIFPLR1_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR1_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR1_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR1_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR1_1_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR1_1_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR1_1_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR1_1_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR1_1_LINK_CAP
+#define BIFPLR1_1_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR1_1_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR1_1_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR1_1_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR1_1_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR1_1_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR1_1_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR1_1_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR1_1_LINK_CNTL
+#define BIFPLR1_1_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR1_1_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR1_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR1_1_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR1_1_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR1_1_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR1_1_LINK_STATUS
+#define BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR1_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR1_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR1_1_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR1_1_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR1_1_SLOT_CAP
+#define BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR1_1_SLOT_CNTL
+#define BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR1_1_SLOT_STATUS
+#define BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR1_1_ROOT_CNTL
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR1_1_ROOT_CAP
+#define BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR1_1_ROOT_STATUS
+#define BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR1_1_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR1_1_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR1_1_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR1_1_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR1_1_DEVICE_CAP2
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR1_1_DEVICE_CNTL2
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR1_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR1_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR1_1_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR1_1_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR1_1_DEVICE_STATUS2
+#define BIFPLR1_1_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR1_1_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR1_1_LINK_CAP2
+#define BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR1_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR1_1_LINK_CNTL2
+#define BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR1_1_LINK_STATUS2
+#define BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR1_1_SLOT_CAP2
+#define BIFPLR1_1_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR1_1_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR1_1_SLOT_CNTL2
+#define BIFPLR1_1_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR1_1_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR1_1_SLOT_STATUS2
+#define BIFPLR1_1_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR1_1_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR1_1_MSI_CAP_LIST
+#define BIFPLR1_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR1_1_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR1_1_MSI_MSG_CNTL
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR1_1_MSI_MSG_ADDR_LO
+#define BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR1_1_MSI_MSG_ADDR_HI
+#define BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_1_MSI_MSG_DATA
+#define BIFPLR1_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR1_1_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR1_1_MSI_MSG_DATA_64
+#define BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR1_1_SSID_CAP_LIST
+#define BIFPLR1_1_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR1_1_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR1_1_SSID_CAP
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR1_1_MSI_MAP_CAP_LIST
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR1_1_MSI_MAP_CAP
+#define BIFPLR1_1_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR1_1_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR1_1_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR1_1_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR1_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR1_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR1_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR1_1_PCIE_PORT_VC_CNTL
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR1_1_PCIE_PORT_VC_STATUS
+#define BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR1_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR1_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR1_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR1_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR1_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR1_1_PCIE_CORR_ERR_MASK
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR1_1_PCIE_HDR_LOG0
+#define BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_HDR_LOG1
+#define BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_HDR_LOG2
+#define BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_HDR_LOG3
+#define BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR1_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR1_1_PCIE_ERR_SRC_ID
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR1_1_PCIE_LINK_CNTL3
+#define BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR1_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR1_1_PCIE_ACS_CAP
+#define BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR1_1_PCIE_ACS_CNTL
+#define BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR1_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR1_1_PCIE_MC_CAP
+#define BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR1_1_PCIE_MC_CNTL
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR1_1_PCIE_MC_ADDR0
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR1_1_PCIE_MC_ADDR1
+#define BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_RCV0
+#define BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_RCV1
+#define BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR1_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR1_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR1_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR1_1_PCIE_DPC_CAP_LIST
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR1_1_PCIE_DPC_CNTL
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR1_1_PCIE_DPC_STATUS
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_STATUS
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_MASK
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR1_1_PCIE_ESM_CAP_LIST
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR1_1_PCIE_ESM_HEADER_1
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR1_1_PCIE_ESM_HEADER_2
+#define BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR1_1_PCIE_ESM_STATUS
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR1_1_PCIE_ESM_CTRL
+#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR1_1_PCIE_ESM_CAP_1
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_2
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_3
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR1_1_PCIE_ESM_CAP_4
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_5
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_6
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_7
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR1_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR1_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR1_1_LINK_CAP_16GT
+#define BIFPLR1_1_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR1_1_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR1_1_LINK_CNTL_16GT
+#define BIFPLR1_1_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR1_1_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR1_1_LINK_STATUS_16GT
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR1_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR1_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR1_1_MARGINING_PORT_CAP
+#define BIFPLR1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR1_1_MARGINING_PORT_STATUS
+#define BIFPLR1_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR1_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR1_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR1_1_PCIE_CCIX_HEADER_1
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR1_1_PCIE_CCIX_HEADER_2
+#define BIFPLR1_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR1_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR1_1_PCIE_CCIX_CAP
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR1_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR1_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR1_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR1_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR1_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR1_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR1_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR1_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR1_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR1_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR1_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR1_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR1_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR1_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR1_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+//BIFPLR2_1_VENDOR_ID
+#define BIFPLR2_1_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR2_1_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR2_1_DEVICE_ID
+#define BIFPLR2_1_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR2_1_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR2_1_COMMAND
+#define BIFPLR2_1_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR2_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR2_1_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR2_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR2_1_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR2_1_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR2_1_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR2_1_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR2_1_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR2_1_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR2_1_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR2_1_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR2_1_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR2_1_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR2_1_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR2_1_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR2_1_STATUS
+#define BIFPLR2_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR2_1_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR2_1_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR2_1_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR2_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR2_1_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR2_1_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR2_1_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR2_1_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR2_1_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR2_1_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR2_1_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR2_1_REVISION_ID
+#define BIFPLR2_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR2_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR2_1_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR2_1_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR2_1_PROG_INTERFACE
+#define BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR2_1_SUB_CLASS
+#define BIFPLR2_1_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR2_1_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR2_1_BASE_CLASS
+#define BIFPLR2_1_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR2_1_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR2_1_CACHE_LINE
+#define BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR2_1_LATENCY
+#define BIFPLR2_1_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR2_1_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR2_1_HEADER
+#define BIFPLR2_1_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR2_1_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR2_1_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR2_1_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR2_1_BIST
+#define BIFPLR2_1_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR2_1_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR2_1_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR2_1_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR2_1_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR2_1_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR2_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR2_1_IO_BASE_LIMIT
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR2_1_SECONDARY_STATUS
+#define BIFPLR2_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR2_1_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR2_1_MEM_BASE_LIMIT
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR2_1_PREF_BASE_LIMIT
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR2_1_PREF_BASE_UPPER
+#define BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_1_PREF_LIMIT_UPPER
+#define BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR2_1_IO_BASE_LIMIT_HI
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR2_1_CAP_PTR
+#define BIFPLR2_1_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR2_1_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR2_1_ROM_BASE_ADDR
+#define BIFPLR2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR2_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR2_1_INTERRUPT_LINE
+#define BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR2_1_INTERRUPT_PIN
+#define BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR2_1_IRQ_BRIDGE_CNTL
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR2_1_EXT_BRIDGE_CNTL
+#define BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR2_1_VENDOR_CAP_LIST
+#define BIFPLR2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR2_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR2_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR2_1_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR2_1_ADAPTER_ID_W
+#define BIFPLR2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR2_1_PMI_CAP_LIST
+#define BIFPLR2_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR2_1_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR2_1_PMI_CAP
+#define BIFPLR2_1_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR2_1_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR2_1_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR2_1_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR2_1_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR2_1_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR2_1_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR2_1_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR2_1_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR2_1_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR2_1_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR2_1_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR2_1_PMI_STATUS_CNTL
+#define BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR2_1_PCIE_CAP_LIST
+#define BIFPLR2_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR2_1_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR2_1_PCIE_CAP
+#define BIFPLR2_1_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR2_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR2_1_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR2_1_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR2_1_DEVICE_CAP
+#define BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR2_1_DEVICE_CNTL
+#define BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR2_1_DEVICE_STATUS
+#define BIFPLR2_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR2_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR2_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR2_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR2_1_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR2_1_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR2_1_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR2_1_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR2_1_LINK_CAP
+#define BIFPLR2_1_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR2_1_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR2_1_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR2_1_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR2_1_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR2_1_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR2_1_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR2_1_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR2_1_LINK_CNTL
+#define BIFPLR2_1_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR2_1_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR2_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR2_1_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR2_1_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR2_1_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR2_1_LINK_STATUS
+#define BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR2_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR2_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR2_1_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR2_1_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR2_1_SLOT_CAP
+#define BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR2_1_SLOT_CNTL
+#define BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR2_1_SLOT_STATUS
+#define BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR2_1_ROOT_CNTL
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR2_1_ROOT_CAP
+#define BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR2_1_ROOT_STATUS
+#define BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR2_1_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR2_1_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR2_1_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR2_1_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR2_1_DEVICE_CAP2
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR2_1_DEVICE_CNTL2
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR2_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR2_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR2_1_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR2_1_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR2_1_DEVICE_STATUS2
+#define BIFPLR2_1_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR2_1_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR2_1_LINK_CAP2
+#define BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR2_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR2_1_LINK_CNTL2
+#define BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR2_1_LINK_STATUS2
+#define BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR2_1_SLOT_CAP2
+#define BIFPLR2_1_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR2_1_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR2_1_SLOT_CNTL2
+#define BIFPLR2_1_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR2_1_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR2_1_SLOT_STATUS2
+#define BIFPLR2_1_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR2_1_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR2_1_MSI_CAP_LIST
+#define BIFPLR2_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR2_1_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR2_1_MSI_MSG_CNTL
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR2_1_MSI_MSG_ADDR_LO
+#define BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR2_1_MSI_MSG_ADDR_HI
+#define BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_1_MSI_MSG_DATA
+#define BIFPLR2_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR2_1_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR2_1_MSI_MSG_DATA_64
+#define BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR2_1_SSID_CAP_LIST
+#define BIFPLR2_1_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR2_1_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR2_1_SSID_CAP
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR2_1_MSI_MAP_CAP_LIST
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR2_1_MSI_MAP_CAP
+#define BIFPLR2_1_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR2_1_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR2_1_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR2_1_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR2_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR2_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR2_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR2_1_PCIE_PORT_VC_CNTL
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR2_1_PCIE_PORT_VC_STATUS
+#define BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR2_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR2_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR2_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR2_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR2_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR2_1_PCIE_CORR_ERR_MASK
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR2_1_PCIE_HDR_LOG0
+#define BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_HDR_LOG1
+#define BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_HDR_LOG2
+#define BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_HDR_LOG3
+#define BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR2_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR2_1_PCIE_ERR_SRC_ID
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR2_1_PCIE_LINK_CNTL3
+#define BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR2_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR2_1_PCIE_ACS_CAP
+#define BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR2_1_PCIE_ACS_CNTL
+#define BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR2_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR2_1_PCIE_MC_CAP
+#define BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR2_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR2_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR2_1_PCIE_MC_CNTL
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR2_1_PCIE_MC_ADDR0
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR2_1_PCIE_MC_ADDR1
+#define BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_RCV0
+#define BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_RCV1
+#define BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR2_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR2_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR2_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR2_1_PCIE_DPC_CAP_LIST
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR2_1_PCIE_DPC_CNTL
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR2_1_PCIE_DPC_STATUS
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_STATUS
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_MASK
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR2_1_PCIE_ESM_CAP_LIST
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR2_1_PCIE_ESM_HEADER_1
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR2_1_PCIE_ESM_HEADER_2
+#define BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR2_1_PCIE_ESM_STATUS
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR2_1_PCIE_ESM_CTRL
+#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR2_1_PCIE_ESM_CAP_1
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_2
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_3
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR2_1_PCIE_ESM_CAP_4
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_5
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_6
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_7
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR2_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR2_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR2_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR2_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR2_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR2_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR2_1_LINK_CAP_16GT
+#define BIFPLR2_1_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR2_1_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR2_1_LINK_CNTL_16GT
+#define BIFPLR2_1_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR2_1_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR2_1_LINK_STATUS_16GT
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR2_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR2_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR2_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR2_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR2_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR2_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR2_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR2_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR2_1_MARGINING_PORT_CAP
+#define BIFPLR2_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR2_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR2_1_MARGINING_PORT_STATUS
+#define BIFPLR2_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR2_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR2_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR2_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR2_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR2_1_PCIE_CCIX_HEADER_1
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR2_1_PCIE_CCIX_HEADER_2
+#define BIFPLR2_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR2_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR2_1_PCIE_CCIX_CAP
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR2_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR2_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR2_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR2_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR2_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR2_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR2_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR2_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR2_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR2_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR2_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR2_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR2_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR2_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR2_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+//BIFPLR3_1_VENDOR_ID
+#define BIFPLR3_1_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR3_1_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR3_1_DEVICE_ID
+#define BIFPLR3_1_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR3_1_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR3_1_COMMAND
+#define BIFPLR3_1_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR3_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR3_1_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR3_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR3_1_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR3_1_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR3_1_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR3_1_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR3_1_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR3_1_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR3_1_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR3_1_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR3_1_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR3_1_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR3_1_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR3_1_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR3_1_STATUS
+#define BIFPLR3_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR3_1_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR3_1_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR3_1_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR3_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR3_1_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR3_1_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR3_1_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR3_1_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR3_1_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR3_1_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR3_1_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR3_1_REVISION_ID
+#define BIFPLR3_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR3_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR3_1_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR3_1_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR3_1_PROG_INTERFACE
+#define BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR3_1_SUB_CLASS
+#define BIFPLR3_1_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR3_1_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR3_1_BASE_CLASS
+#define BIFPLR3_1_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR3_1_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR3_1_CACHE_LINE
+#define BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR3_1_LATENCY
+#define BIFPLR3_1_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR3_1_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR3_1_HEADER
+#define BIFPLR3_1_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR3_1_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR3_1_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR3_1_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR3_1_BIST
+#define BIFPLR3_1_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR3_1_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR3_1_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR3_1_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR3_1_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR3_1_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR3_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR3_1_IO_BASE_LIMIT
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR3_1_SECONDARY_STATUS
+#define BIFPLR3_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR3_1_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR3_1_MEM_BASE_LIMIT
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR3_1_PREF_BASE_LIMIT
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR3_1_PREF_BASE_UPPER
+#define BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_1_PREF_LIMIT_UPPER
+#define BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR3_1_IO_BASE_LIMIT_HI
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR3_1_CAP_PTR
+#define BIFPLR3_1_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR3_1_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR3_1_ROM_BASE_ADDR
+#define BIFPLR3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR3_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR3_1_INTERRUPT_LINE
+#define BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR3_1_INTERRUPT_PIN
+#define BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR3_1_IRQ_BRIDGE_CNTL
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR3_1_EXT_BRIDGE_CNTL
+#define BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR3_1_VENDOR_CAP_LIST
+#define BIFPLR3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR3_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR3_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR3_1_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR3_1_ADAPTER_ID_W
+#define BIFPLR3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR3_1_PMI_CAP_LIST
+#define BIFPLR3_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR3_1_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR3_1_PMI_CAP
+#define BIFPLR3_1_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR3_1_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR3_1_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR3_1_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR3_1_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR3_1_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR3_1_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR3_1_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR3_1_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR3_1_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR3_1_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR3_1_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR3_1_PMI_STATUS_CNTL
+#define BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR3_1_PCIE_CAP_LIST
+#define BIFPLR3_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR3_1_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR3_1_PCIE_CAP
+#define BIFPLR3_1_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR3_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR3_1_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR3_1_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR3_1_DEVICE_CAP
+#define BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR3_1_DEVICE_CNTL
+#define BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR3_1_DEVICE_STATUS
+#define BIFPLR3_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR3_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR3_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR3_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR3_1_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR3_1_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR3_1_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR3_1_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR3_1_LINK_CAP
+#define BIFPLR3_1_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR3_1_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR3_1_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR3_1_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR3_1_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR3_1_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR3_1_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR3_1_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR3_1_LINK_CNTL
+#define BIFPLR3_1_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR3_1_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR3_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR3_1_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR3_1_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR3_1_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR3_1_LINK_STATUS
+#define BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR3_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR3_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR3_1_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR3_1_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR3_1_SLOT_CAP
+#define BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR3_1_SLOT_CNTL
+#define BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR3_1_SLOT_STATUS
+#define BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR3_1_ROOT_CNTL
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR3_1_ROOT_CAP
+#define BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR3_1_ROOT_STATUS
+#define BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR3_1_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR3_1_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR3_1_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR3_1_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR3_1_DEVICE_CAP2
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR3_1_DEVICE_CNTL2
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR3_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR3_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR3_1_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR3_1_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR3_1_DEVICE_STATUS2
+#define BIFPLR3_1_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR3_1_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR3_1_LINK_CAP2
+#define BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR3_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR3_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR3_1_LINK_CNTL2
+#define BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR3_1_LINK_STATUS2
+#define BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR3_1_SLOT_CAP2
+#define BIFPLR3_1_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR3_1_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR3_1_SLOT_CNTL2
+#define BIFPLR3_1_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR3_1_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR3_1_SLOT_STATUS2
+#define BIFPLR3_1_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR3_1_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR3_1_MSI_CAP_LIST
+#define BIFPLR3_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR3_1_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR3_1_MSI_MSG_CNTL
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR3_1_MSI_MSG_ADDR_LO
+#define BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR3_1_MSI_MSG_ADDR_HI
+#define BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_1_MSI_MSG_DATA
+#define BIFPLR3_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR3_1_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR3_1_MSI_MSG_DATA_64
+#define BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR3_1_SSID_CAP_LIST
+#define BIFPLR3_1_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR3_1_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR3_1_SSID_CAP
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR3_1_MSI_MAP_CAP_LIST
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR3_1_MSI_MAP_CAP
+#define BIFPLR3_1_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR3_1_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR3_1_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR3_1_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR3_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR3_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR3_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR3_1_PCIE_PORT_VC_CNTL
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR3_1_PCIE_PORT_VC_STATUS
+#define BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR3_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR3_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR3_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR3_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR3_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR3_1_PCIE_CORR_ERR_MASK
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR3_1_PCIE_HDR_LOG0
+#define BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_HDR_LOG1
+#define BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_HDR_LOG2
+#define BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_HDR_LOG3
+#define BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR3_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR3_1_PCIE_ERR_SRC_ID
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR3_1_PCIE_LINK_CNTL3
+#define BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR3_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR3_1_PCIE_ACS_CAP
+#define BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR3_1_PCIE_ACS_CNTL
+#define BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR3_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR3_1_PCIE_MC_CAP
+#define BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR3_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR3_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR3_1_PCIE_MC_CNTL
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR3_1_PCIE_MC_ADDR0
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR3_1_PCIE_MC_ADDR1
+#define BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_RCV0
+#define BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_RCV1
+#define BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR3_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR3_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR3_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR3_1_PCIE_DPC_CAP_LIST
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR3_1_PCIE_DPC_CNTL
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR3_1_PCIE_DPC_STATUS
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_STATUS
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_MASK
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR3_1_PCIE_ESM_CAP_LIST
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR3_1_PCIE_ESM_HEADER_1
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR3_1_PCIE_ESM_HEADER_2
+#define BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR3_1_PCIE_ESM_STATUS
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR3_1_PCIE_ESM_CTRL
+#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR3_1_PCIE_ESM_CAP_1
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_2
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_3
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR3_1_PCIE_ESM_CAP_4
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_5
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_6
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_7
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR3_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR3_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR3_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR3_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR3_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR3_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR3_1_LINK_CAP_16GT
+#define BIFPLR3_1_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR3_1_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR3_1_LINK_CNTL_16GT
+#define BIFPLR3_1_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR3_1_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR3_1_LINK_STATUS_16GT
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR3_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR3_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR3_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR3_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR3_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR3_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR3_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR3_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR3_1_MARGINING_PORT_CAP
+#define BIFPLR3_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR3_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR3_1_MARGINING_PORT_STATUS
+#define BIFPLR3_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR3_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR3_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR3_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR3_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR3_1_PCIE_CCIX_HEADER_1
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR3_1_PCIE_CCIX_HEADER_2
+#define BIFPLR3_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR3_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR3_1_PCIE_CCIX_CAP
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR3_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR3_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR3_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR3_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR3_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR3_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR3_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR3_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR3_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR3_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR3_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR3_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR3_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR3_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR3_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+//BIFPLR4_1_VENDOR_ID
+#define BIFPLR4_1_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR4_1_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR4_1_DEVICE_ID
+#define BIFPLR4_1_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR4_1_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR4_1_COMMAND
+#define BIFPLR4_1_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR4_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR4_1_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR4_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR4_1_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR4_1_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR4_1_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR4_1_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR4_1_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR4_1_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR4_1_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR4_1_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR4_1_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR4_1_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR4_1_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR4_1_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR4_1_STATUS
+#define BIFPLR4_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR4_1_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR4_1_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR4_1_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR4_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR4_1_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR4_1_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR4_1_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR4_1_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR4_1_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR4_1_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR4_1_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR4_1_REVISION_ID
+#define BIFPLR4_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR4_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR4_1_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR4_1_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR4_1_PROG_INTERFACE
+#define BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR4_1_SUB_CLASS
+#define BIFPLR4_1_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR4_1_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR4_1_BASE_CLASS
+#define BIFPLR4_1_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR4_1_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR4_1_CACHE_LINE
+#define BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR4_1_LATENCY
+#define BIFPLR4_1_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR4_1_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR4_1_HEADER
+#define BIFPLR4_1_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR4_1_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR4_1_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR4_1_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR4_1_BIST
+#define BIFPLR4_1_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR4_1_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR4_1_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR4_1_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR4_1_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR4_1_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR4_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR4_1_IO_BASE_LIMIT
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR4_1_SECONDARY_STATUS
+#define BIFPLR4_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR4_1_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR4_1_MEM_BASE_LIMIT
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR4_1_PREF_BASE_LIMIT
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR4_1_PREF_BASE_UPPER
+#define BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_1_PREF_LIMIT_UPPER
+#define BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR4_1_IO_BASE_LIMIT_HI
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR4_1_CAP_PTR
+#define BIFPLR4_1_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR4_1_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR4_1_ROM_BASE_ADDR
+#define BIFPLR4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR4_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR4_1_INTERRUPT_LINE
+#define BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR4_1_INTERRUPT_PIN
+#define BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR4_1_IRQ_BRIDGE_CNTL
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR4_1_EXT_BRIDGE_CNTL
+#define BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR4_1_VENDOR_CAP_LIST
+#define BIFPLR4_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR4_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR4_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR4_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR4_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR4_1_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR4_1_ADAPTER_ID_W
+#define BIFPLR4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR4_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR4_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR4_1_PMI_CAP_LIST
+#define BIFPLR4_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR4_1_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR4_1_PMI_CAP
+#define BIFPLR4_1_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR4_1_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR4_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR4_1_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR4_1_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR4_1_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR4_1_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR4_1_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR4_1_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR4_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR4_1_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR4_1_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR4_1_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR4_1_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR4_1_PMI_STATUS_CNTL
+#define BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR4_1_PCIE_CAP_LIST
+#define BIFPLR4_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR4_1_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR4_1_PCIE_CAP
+#define BIFPLR4_1_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR4_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR4_1_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR4_1_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR4_1_DEVICE_CAP
+#define BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR4_1_DEVICE_CNTL
+#define BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR4_1_DEVICE_STATUS
+#define BIFPLR4_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR4_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR4_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR4_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR4_1_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR4_1_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR4_1_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR4_1_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR4_1_LINK_CAP
+#define BIFPLR4_1_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR4_1_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR4_1_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR4_1_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR4_1_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR4_1_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR4_1_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR4_1_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR4_1_LINK_CNTL
+#define BIFPLR4_1_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR4_1_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR4_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR4_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR4_1_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR4_1_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR4_1_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR4_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR4_1_LINK_STATUS
+#define BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR4_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR4_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR4_1_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR4_1_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR4_1_SLOT_CAP
+#define BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR4_1_SLOT_CNTL
+#define BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR4_1_SLOT_STATUS
+#define BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR4_1_ROOT_CNTL
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR4_1_ROOT_CAP
+#define BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR4_1_ROOT_STATUS
+#define BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR4_1_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR4_1_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR4_1_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR4_1_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR4_1_DEVICE_CAP2
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR4_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR4_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR4_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR4_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR4_1_DEVICE_CNTL2
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR4_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR4_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR4_1_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR4_1_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR4_1_DEVICE_STATUS2
+#define BIFPLR4_1_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR4_1_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR4_1_LINK_CAP2
+#define BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR4_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR4_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR4_1_LINK_CNTL2
+#define BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR4_1_LINK_STATUS2
+#define BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR4_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR4_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR4_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR4_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR4_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR4_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR4_1_SLOT_CAP2
+#define BIFPLR4_1_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR4_1_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR4_1_SLOT_CNTL2
+#define BIFPLR4_1_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR4_1_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR4_1_SLOT_STATUS2
+#define BIFPLR4_1_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR4_1_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR4_1_MSI_CAP_LIST
+#define BIFPLR4_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR4_1_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR4_1_MSI_MSG_CNTL
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR4_1_MSI_MSG_ADDR_LO
+#define BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR4_1_MSI_MSG_ADDR_HI
+#define BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_1_MSI_MSG_DATA
+#define BIFPLR4_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR4_1_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR4_1_MSI_MSG_DATA_64
+#define BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR4_1_SSID_CAP_LIST
+#define BIFPLR4_1_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR4_1_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR4_1_SSID_CAP
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR4_1_MSI_MAP_CAP_LIST
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR4_1_MSI_MAP_CAP
+#define BIFPLR4_1_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR4_1_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR4_1_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR4_1_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR4_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR4_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR4_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR4_1_PCIE_PORT_VC_CNTL
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR4_1_PCIE_PORT_VC_STATUS
+#define BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR4_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR4_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR4_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR4_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR4_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR4_1_PCIE_CORR_ERR_MASK
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR4_1_PCIE_HDR_LOG0
+#define BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_HDR_LOG1
+#define BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_HDR_LOG2
+#define BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_HDR_LOG3
+#define BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR4_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR4_1_PCIE_ERR_SRC_ID
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR4_1_PCIE_LINK_CNTL3
+#define BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR4_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR4_1_PCIE_ACS_CAP
+#define BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR4_1_PCIE_ACS_CNTL
+#define BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR4_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR4_1_PCIE_MC_CAP
+#define BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR4_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR4_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR4_1_PCIE_MC_CNTL
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR4_1_PCIE_MC_ADDR0
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR4_1_PCIE_MC_ADDR1
+#define BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_RCV0
+#define BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_RCV1
+#define BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR4_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR4_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR4_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR4_1_PCIE_DPC_CAP_LIST
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR4_1_PCIE_DPC_CNTL
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR4_1_PCIE_DPC_STATUS
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_STATUS
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_MASK
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR4_1_PCIE_ESM_CAP_LIST
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR4_1_PCIE_ESM_HEADER_1
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR4_1_PCIE_ESM_HEADER_2
+#define BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR4_1_PCIE_ESM_STATUS
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR4_1_PCIE_ESM_CTRL
+#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR4_1_PCIE_ESM_CAP_1
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_2
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_3
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR4_1_PCIE_ESM_CAP_4
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_5
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_6
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_7
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR4_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR4_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR4_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR4_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR4_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR4_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR4_1_LINK_CAP_16GT
+#define BIFPLR4_1_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR4_1_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR4_1_LINK_CNTL_16GT
+#define BIFPLR4_1_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR4_1_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR4_1_LINK_STATUS_16GT
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR4_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR4_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR4_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR4_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR4_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR4_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR4_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR4_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR4_1_MARGINING_PORT_CAP
+#define BIFPLR4_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR4_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR4_1_MARGINING_PORT_STATUS
+#define BIFPLR4_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR4_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR4_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR4_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR4_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR4_1_PCIE_CCIX_HEADER_1
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR4_1_PCIE_CCIX_HEADER_2
+#define BIFPLR4_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR4_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR4_1_PCIE_CCIX_CAP
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR4_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR4_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR4_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR4_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR4_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR4_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR4_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR4_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR4_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR4_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR4_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR4_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR4_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR4_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR4_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+//BIFPLR5_1_VENDOR_ID
+#define BIFPLR5_1_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR5_1_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR5_1_DEVICE_ID
+#define BIFPLR5_1_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR5_1_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR5_1_COMMAND
+#define BIFPLR5_1_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR5_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR5_1_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR5_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR5_1_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR5_1_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR5_1_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR5_1_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR5_1_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR5_1_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR5_1_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR5_1_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR5_1_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR5_1_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR5_1_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR5_1_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR5_1_STATUS
+#define BIFPLR5_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR5_1_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR5_1_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR5_1_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR5_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR5_1_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR5_1_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR5_1_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR5_1_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR5_1_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR5_1_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR5_1_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR5_1_REVISION_ID
+#define BIFPLR5_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR5_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR5_1_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR5_1_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR5_1_PROG_INTERFACE
+#define BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR5_1_SUB_CLASS
+#define BIFPLR5_1_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR5_1_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR5_1_BASE_CLASS
+#define BIFPLR5_1_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR5_1_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR5_1_CACHE_LINE
+#define BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR5_1_LATENCY
+#define BIFPLR5_1_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR5_1_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR5_1_HEADER
+#define BIFPLR5_1_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR5_1_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR5_1_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR5_1_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR5_1_BIST
+#define BIFPLR5_1_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR5_1_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR5_1_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR5_1_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR5_1_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR5_1_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR5_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR5_1_IO_BASE_LIMIT
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR5_1_SECONDARY_STATUS
+#define BIFPLR5_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR5_1_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR5_1_MEM_BASE_LIMIT
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR5_1_PREF_BASE_LIMIT
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR5_1_PREF_BASE_UPPER
+#define BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_1_PREF_LIMIT_UPPER
+#define BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR5_1_IO_BASE_LIMIT_HI
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR5_1_CAP_PTR
+#define BIFPLR5_1_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR5_1_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR5_1_ROM_BASE_ADDR
+#define BIFPLR5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR5_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR5_1_INTERRUPT_LINE
+#define BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR5_1_INTERRUPT_PIN
+#define BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR5_1_IRQ_BRIDGE_CNTL
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR5_1_EXT_BRIDGE_CNTL
+#define BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR5_1_VENDOR_CAP_LIST
+#define BIFPLR5_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR5_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR5_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR5_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR5_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR5_1_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR5_1_ADAPTER_ID_W
+#define BIFPLR5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR5_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR5_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR5_1_PMI_CAP_LIST
+#define BIFPLR5_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR5_1_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR5_1_PMI_CAP
+#define BIFPLR5_1_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR5_1_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR5_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR5_1_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR5_1_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR5_1_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR5_1_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR5_1_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR5_1_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR5_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR5_1_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR5_1_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR5_1_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR5_1_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR5_1_PMI_STATUS_CNTL
+#define BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR5_1_PCIE_CAP_LIST
+#define BIFPLR5_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR5_1_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR5_1_PCIE_CAP
+#define BIFPLR5_1_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR5_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR5_1_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR5_1_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR5_1_DEVICE_CAP
+#define BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR5_1_DEVICE_CNTL
+#define BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR5_1_DEVICE_STATUS
+#define BIFPLR5_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR5_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR5_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR5_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR5_1_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR5_1_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR5_1_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR5_1_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR5_1_LINK_CAP
+#define BIFPLR5_1_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR5_1_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR5_1_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR5_1_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR5_1_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR5_1_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR5_1_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR5_1_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR5_1_LINK_CNTL
+#define BIFPLR5_1_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR5_1_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR5_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR5_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR5_1_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR5_1_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR5_1_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR5_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR5_1_LINK_STATUS
+#define BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR5_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR5_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR5_1_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR5_1_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR5_1_SLOT_CAP
+#define BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR5_1_SLOT_CNTL
+#define BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR5_1_SLOT_STATUS
+#define BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR5_1_ROOT_CNTL
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR5_1_ROOT_CAP
+#define BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR5_1_ROOT_STATUS
+#define BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR5_1_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR5_1_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR5_1_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR5_1_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR5_1_DEVICE_CAP2
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR5_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR5_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR5_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR5_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR5_1_DEVICE_CNTL2
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR5_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR5_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR5_1_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR5_1_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR5_1_DEVICE_STATUS2
+#define BIFPLR5_1_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR5_1_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR5_1_LINK_CAP2
+#define BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR5_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR5_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR5_1_LINK_CNTL2
+#define BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR5_1_LINK_STATUS2
+#define BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR5_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR5_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR5_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR5_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR5_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR5_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR5_1_SLOT_CAP2
+#define BIFPLR5_1_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR5_1_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR5_1_SLOT_CNTL2
+#define BIFPLR5_1_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR5_1_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR5_1_SLOT_STATUS2
+#define BIFPLR5_1_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR5_1_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR5_1_MSI_CAP_LIST
+#define BIFPLR5_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR5_1_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR5_1_MSI_MSG_CNTL
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR5_1_MSI_MSG_ADDR_LO
+#define BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR5_1_MSI_MSG_ADDR_HI
+#define BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_1_MSI_MSG_DATA
+#define BIFPLR5_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR5_1_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR5_1_MSI_MSG_DATA_64
+#define BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR5_1_SSID_CAP_LIST
+#define BIFPLR5_1_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR5_1_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR5_1_SSID_CAP
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR5_1_MSI_MAP_CAP_LIST
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR5_1_MSI_MAP_CAP
+#define BIFPLR5_1_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR5_1_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR5_1_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR5_1_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR5_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR5_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR5_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR5_1_PCIE_PORT_VC_CNTL
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR5_1_PCIE_PORT_VC_STATUS
+#define BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR5_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR5_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR5_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR5_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR5_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR5_1_PCIE_CORR_ERR_MASK
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR5_1_PCIE_HDR_LOG0
+#define BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_HDR_LOG1
+#define BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_HDR_LOG2
+#define BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_HDR_LOG3
+#define BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR5_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR5_1_PCIE_ERR_SRC_ID
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR5_1_PCIE_LINK_CNTL3
+#define BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR5_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR5_1_PCIE_ACS_CAP
+#define BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR5_1_PCIE_ACS_CNTL
+#define BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR5_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR5_1_PCIE_MC_CAP
+#define BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR5_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR5_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR5_1_PCIE_MC_CNTL
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR5_1_PCIE_MC_ADDR0
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR5_1_PCIE_MC_ADDR1
+#define BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_RCV0
+#define BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_RCV1
+#define BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR5_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR5_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR5_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR5_1_PCIE_DPC_CAP_LIST
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR5_1_PCIE_DPC_CNTL
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR5_1_PCIE_DPC_STATUS
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_STATUS
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_MASK
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR5_1_PCIE_ESM_CAP_LIST
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR5_1_PCIE_ESM_HEADER_1
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR5_1_PCIE_ESM_HEADER_2
+#define BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR5_1_PCIE_ESM_STATUS
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR5_1_PCIE_ESM_CTRL
+#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR5_1_PCIE_ESM_CAP_1
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_2
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_3
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR5_1_PCIE_ESM_CAP_4
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_5
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_6
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_7
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR5_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR5_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR5_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR5_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR5_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR5_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR5_1_LINK_CAP_16GT
+#define BIFPLR5_1_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR5_1_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR5_1_LINK_CNTL_16GT
+#define BIFPLR5_1_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR5_1_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR5_1_LINK_STATUS_16GT
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR5_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR5_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR5_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR5_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR5_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR5_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR5_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR5_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR5_1_MARGINING_PORT_CAP
+#define BIFPLR5_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR5_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR5_1_MARGINING_PORT_STATUS
+#define BIFPLR5_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR5_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR5_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR5_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR5_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR5_1_PCIE_CCIX_HEADER_1
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR5_1_PCIE_CCIX_HEADER_2
+#define BIFPLR5_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR5_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR5_1_PCIE_CCIX_CAP
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR5_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR5_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR5_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR5_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR5_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR5_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR5_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR5_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR5_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR5_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR5_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR5_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR5_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR5_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR5_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+//BIFPLR6_1_VENDOR_ID
+#define BIFPLR6_1_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
+#define BIFPLR6_1_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
+//BIFPLR6_1_DEVICE_ID
+#define BIFPLR6_1_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
+#define BIFPLR6_1_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
+//BIFPLR6_1_COMMAND
+#define BIFPLR6_1_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
+#define BIFPLR6_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
+#define BIFPLR6_1_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
+#define BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
+#define BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
+#define BIFPLR6_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
+#define BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
+#define BIFPLR6_1_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
+#define BIFPLR6_1_COMMAND__SERR_EN__SHIFT                                                                     0x8
+#define BIFPLR6_1_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
+#define BIFPLR6_1_COMMAND__INT_DIS__SHIFT                                                                     0xa
+#define BIFPLR6_1_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
+#define BIFPLR6_1_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
+#define BIFPLR6_1_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
+#define BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
+#define BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
+#define BIFPLR6_1_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
+#define BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
+#define BIFPLR6_1_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
+#define BIFPLR6_1_COMMAND__SERR_EN_MASK                                                                       0x0100L
+#define BIFPLR6_1_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
+#define BIFPLR6_1_COMMAND__INT_DIS_MASK                                                                       0x0400L
+//BIFPLR6_1_STATUS
+#define BIFPLR6_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                          0x0
+#define BIFPLR6_1_STATUS__INT_STATUS__SHIFT                                                                   0x3
+#define BIFPLR6_1_STATUS__CAP_LIST__SHIFT                                                                     0x4
+#define BIFPLR6_1_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define BIFPLR6_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define BIFPLR6_1_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define BIFPLR6_1_STATUS__IMMEDIATE_READINESS_MASK                                                            0x0001L
+#define BIFPLR6_1_STATUS__INT_STATUS_MASK                                                                     0x0008L
+#define BIFPLR6_1_STATUS__CAP_LIST_MASK                                                                       0x0010L
+#define BIFPLR6_1_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define BIFPLR6_1_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define BIFPLR6_1_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//BIFPLR6_1_REVISION_ID
+#define BIFPLR6_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
+#define BIFPLR6_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
+#define BIFPLR6_1_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
+#define BIFPLR6_1_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
+//BIFPLR6_1_PROG_INTERFACE
+#define BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
+#define BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
+//BIFPLR6_1_SUB_CLASS
+#define BIFPLR6_1_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
+#define BIFPLR6_1_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
+//BIFPLR6_1_BASE_CLASS
+#define BIFPLR6_1_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
+#define BIFPLR6_1_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
+//BIFPLR6_1_CACHE_LINE
+#define BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
+#define BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
+//BIFPLR6_1_LATENCY
+#define BIFPLR6_1_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
+#define BIFPLR6_1_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
+//BIFPLR6_1_HEADER
+#define BIFPLR6_1_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
+#define BIFPLR6_1_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
+#define BIFPLR6_1_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
+#define BIFPLR6_1_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
+//BIFPLR6_1_BIST
+#define BIFPLR6_1_BIST__BIST_COMP__SHIFT                                                                      0x0
+#define BIFPLR6_1_BIST__BIST_STRT__SHIFT                                                                      0x6
+#define BIFPLR6_1_BIST__BIST_CAP__SHIFT                                                                       0x7
+#define BIFPLR6_1_BIST__BIST_COMP_MASK                                                                        0x0FL
+#define BIFPLR6_1_BIST__BIST_STRT_MASK                                                                        0x40L
+#define BIFPLR6_1_BIST__BIST_CAP_MASK                                                                         0x80L
+//BIFPLR6_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
+//BIFPLR6_1_IO_BASE_LIMIT
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
+//BIFPLR6_1_SECONDARY_STATUS
+#define BIFPLR6_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIFPLR6_1_SECONDARY_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIFPLR6_1_MEM_BASE_LIMIT
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
+//BIFPLR6_1_PREF_BASE_LIMIT
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
+//BIFPLR6_1_PREF_BASE_UPPER
+#define BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
+#define BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_1_PREF_LIMIT_UPPER
+#define BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
+#define BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
+//BIFPLR6_1_IO_BASE_LIMIT_HI
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
+//BIFPLR6_1_CAP_PTR
+#define BIFPLR6_1_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
+#define BIFPLR6_1_CAP_PTR__CAP_PTR_MASK                                                                       0xFFL
+//BIFPLR6_1_ROM_BASE_ADDR
+#define BIFPLR6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                             0x0
+#define BIFPLR6_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                               0xFFFFFFFFL
+//BIFPLR6_1_INTERRUPT_LINE
+#define BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
+#define BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
+//BIFPLR6_1_INTERRUPT_PIN
+#define BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
+#define BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
+//BIFPLR6_1_IRQ_BRIDGE_CNTL
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                               0x8
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                             0x9
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                0xa
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                           0xb
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                 0x0100L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                               0x0200L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                  0x0400L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                             0x0800L
+//BIFPLR6_1_EXT_BRIDGE_CNTL
+#define BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                       0x0
+#define BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                         0x01L
+//BIFPLR6_1_VENDOR_CAP_LIST
+#define BIFPLR6_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
+#define BIFPLR6_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
+#define BIFPLR6_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
+#define BIFPLR6_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
+#define BIFPLR6_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
+#define BIFPLR6_1_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
+//BIFPLR6_1_ADAPTER_ID_W
+#define BIFPLR6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
+#define BIFPLR6_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
+#define BIFPLR6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR6_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
+//BIFPLR6_1_PMI_CAP_LIST
+#define BIFPLR6_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR6_1_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR6_1_PMI_CAP
+#define BIFPLR6_1_PMI_CAP__VERSION__SHIFT                                                                     0x0
+#define BIFPLR6_1_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
+#define BIFPLR6_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                         0x4
+#define BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
+#define BIFPLR6_1_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
+#define BIFPLR6_1_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
+#define BIFPLR6_1_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
+#define BIFPLR6_1_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
+#define BIFPLR6_1_PMI_CAP__VERSION_MASK                                                                       0x0007L
+#define BIFPLR6_1_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
+#define BIFPLR6_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                           0x0010L
+#define BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
+#define BIFPLR6_1_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
+#define BIFPLR6_1_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
+#define BIFPLR6_1_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
+#define BIFPLR6_1_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
+//BIFPLR6_1_PMI_STATUS_CNTL
+#define BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
+#define BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
+#define BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
+#define BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
+#define BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
+#define BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
+#define BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
+//BIFPLR6_1_PCIE_CAP_LIST
+#define BIFPLR6_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR6_1_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR6_1_PCIE_CAP
+#define BIFPLR6_1_PCIE_CAP__VERSION__SHIFT                                                                    0x0
+#define BIFPLR6_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
+#define BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
+#define BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
+#define BIFPLR6_1_PCIE_CAP__VERSION_MASK                                                                      0x000FL
+#define BIFPLR6_1_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
+#define BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
+#define BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
+//BIFPLR6_1_DEVICE_CAP
+#define BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
+#define BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
+#define BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
+#define BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
+#define BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
+#define BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
+#define BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
+#define BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
+#define BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
+#define BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
+#define BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
+#define BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
+#define BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
+#define BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
+//BIFPLR6_1_DEVICE_CNTL
+#define BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
+#define BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
+#define BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
+#define BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
+#define BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
+#define BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
+#define BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
+#define BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
+#define BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
+#define BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
+#define BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
+#define BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
+#define BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
+#define BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
+#define BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
+#define BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
+#define BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
+#define BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
+#define BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
+#define BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
+#define BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
+#define BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
+#define BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
+#define BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
+//BIFPLR6_1_DEVICE_STATUS
+#define BIFPLR6_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
+#define BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
+#define BIFPLR6_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
+#define BIFPLR6_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
+#define BIFPLR6_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
+#define BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
+#define BIFPLR6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                         0x6
+#define BIFPLR6_1_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
+#define BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
+#define BIFPLR6_1_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
+#define BIFPLR6_1_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
+#define BIFPLR6_1_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
+#define BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
+#define BIFPLR6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                           0x0040L
+//BIFPLR6_1_LINK_CAP
+#define BIFPLR6_1_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
+#define BIFPLR6_1_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
+#define BIFPLR6_1_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
+#define BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
+#define BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
+#define BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
+#define BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
+#define BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
+#define BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
+#define BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
+#define BIFPLR6_1_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
+#define BIFPLR6_1_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
+#define BIFPLR6_1_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
+#define BIFPLR6_1_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
+#define BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
+#define BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
+#define BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
+#define BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
+#define BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
+#define BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
+#define BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
+#define BIFPLR6_1_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
+//BIFPLR6_1_LINK_CNTL
+#define BIFPLR6_1_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
+#define BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
+#define BIFPLR6_1_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
+#define BIFPLR6_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
+#define BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
+#define BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
+#define BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
+#define BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
+#define BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
+#define BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
+#define BIFPLR6_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                                     0xe
+#define BIFPLR6_1_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
+#define BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
+#define BIFPLR6_1_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
+#define BIFPLR6_1_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
+#define BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
+#define BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
+#define BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
+#define BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
+#define BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
+#define BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
+#define BIFPLR6_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                       0xC000L
+//BIFPLR6_1_LINK_STATUS
+#define BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
+#define BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
+#define BIFPLR6_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
+#define BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
+#define BIFPLR6_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
+#define BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
+#define BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
+#define BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
+#define BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
+#define BIFPLR6_1_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
+#define BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
+#define BIFPLR6_1_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
+#define BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
+#define BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
+//BIFPLR6_1_SLOT_CAP
+#define BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                        0x0
+#define BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                     0x1
+#define BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                         0x2
+#define BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                     0x3
+#define BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                      0x4
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                           0x5
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                            0x6
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                       0x7
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                       0xf
+#define BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                              0x11
+#define BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                             0x12
+#define BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                          0x13
+#define BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                          0x00000001L
+#define BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                       0x00000002L
+#define BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                           0x00000004L
+#define BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                       0x00000008L
+#define BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                        0x00000010L
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                             0x00000020L
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                              0x00000040L
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                         0x00007F80L
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                         0x00018000L
+#define BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                0x00020000L
+#define BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                               0x00040000L
+#define BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                            0xFFF80000L
+//BIFPLR6_1_SLOT_CNTL
+#define BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                    0x0
+#define BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                     0x1
+#define BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                     0x2
+#define BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                0x3
+#define BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                 0x4
+#define BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                           0x5
+#define BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                       0x6
+#define BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                        0x8
+#define BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                       0xa
+#define BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                0xb
+#define BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                       0xc
+#define BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                               0xd
+#define BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                      0x0001L
+#define BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                       0x0002L
+#define BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                       0x0004L
+#define BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                  0x0008L
+#define BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                   0x0010L
+#define BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                             0x0020L
+#define BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                         0x00C0L
+#define BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                          0x0300L
+#define BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                         0x0400L
+#define BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                  0x0800L
+#define BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                         0x1000L
+#define BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                 0x2000L
+//BIFPLR6_1_SLOT_STATUS
+#define BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                     0x0
+#define BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                      0x1
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                      0x2
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                 0x3
+#define BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                       0x4
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                        0x5
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                   0x6
+#define BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                            0x7
+#define BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                        0x8
+#define BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                       0x0001L
+#define BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                        0x0002L
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                        0x0004L
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                   0x0008L
+#define BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                         0x0010L
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                          0x0020L
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                     0x0040L
+#define BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                              0x0080L
+#define BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                          0x0100L
+//BIFPLR6_1_ROOT_CNTL
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                       0x0
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                   0x1
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                           0x3
+#define BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                0x4
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                         0x0001L
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                     0x0002L
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                             0x0008L
+#define BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                  0x0010L
+//BIFPLR6_1_ROOT_CAP
+#define BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                    0x0
+#define BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                      0x0001L
+//BIFPLR6_1_ROOT_STATUS
+#define BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                        0x0
+#define BIFPLR6_1_ROOT_STATUS__PME_STATUS__SHIFT                                                              0x10
+#define BIFPLR6_1_ROOT_STATUS__PME_PENDING__SHIFT                                                             0x11
+#define BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR6_1_ROOT_STATUS__PME_STATUS_MASK                                                                0x00010000L
+#define BIFPLR6_1_ROOT_STATUS__PME_PENDING_MASK                                                               0x00020000L
+//BIFPLR6_1_DEVICE_CAP2
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
+#define BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
+#define BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
+#define BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
+#define BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
+#define BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
+#define BIFPLR6_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                           0xe
+#define BIFPLR6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                         0x10
+#define BIFPLR6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                         0x11
+#define BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
+#define BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
+#define BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
+#define BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
+#define BIFPLR6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                          0x18
+#define BIFPLR6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                           0x1a
+#define BIFPLR6_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                           0x1f
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
+#define BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
+#define BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
+#define BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
+#define BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
+#define BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
+#define BIFPLR6_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                             0x0000C000L
+#define BIFPLR6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                           0x00010000L
+#define BIFPLR6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                           0x00020000L
+#define BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
+#define BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
+#define BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
+#define BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
+#define BIFPLR6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                            0x03000000L
+#define BIFPLR6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                             0x04000000L
+#define BIFPLR6_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                             0x80000000L
+//BIFPLR6_1_DEVICE_CNTL2
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
+#define BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
+#define BIFPLR6_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
+#define BIFPLR6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                           0xb
+#define BIFPLR6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                           0xc
+#define BIFPLR6_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
+#define BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
+#define BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
+#define BIFPLR6_1_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
+#define BIFPLR6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                             0x0800L
+#define BIFPLR6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                             0x1000L
+#define BIFPLR6_1_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
+#define BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
+//BIFPLR6_1_DEVICE_STATUS2
+#define BIFPLR6_1_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
+#define BIFPLR6_1_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
+//BIFPLR6_1_LINK_CAP2
+#define BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
+#define BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
+#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
+#define BIFPLR6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                                 0x17
+#define BIFPLR6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                                 0x18
+#define BIFPLR6_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                             0x1f
+#define BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
+#define BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
+#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x007F0000L
+#define BIFPLR6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                                   0x00800000L
+#define BIFPLR6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                                   0x01000000L
+#define BIFPLR6_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                               0x80000000L
+//BIFPLR6_1_LINK_CNTL2
+#define BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
+#define BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
+#define BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
+#define BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
+#define BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
+#define BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
+#define BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
+#define BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
+#define BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
+#define BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
+#define BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
+#define BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
+//BIFPLR6_1_LINK_STATUS2
+#define BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                              0x1
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                        0x2
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                        0x3
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                        0x4
+#define BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                          0x5
+#define BIFPLR6_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                      0x6
+#define BIFPLR6_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                      0x7
+#define BIFPLR6_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                                   0x8
+#define BIFPLR6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                          0xc
+#define BIFPLR6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                                   0xf
+#define BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                                0x0002L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                          0x0004L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                          0x0008L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                          0x0010L
+#define BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                            0x0020L
+#define BIFPLR6_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                        0x0040L
+#define BIFPLR6_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                        0x0080L
+#define BIFPLR6_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                                     0x0300L
+#define BIFPLR6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                            0x7000L
+#define BIFPLR6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                                     0x8000L
+//BIFPLR6_1_SLOT_CAP2
+#define BIFPLR6_1_SLOT_CAP2__RESERVED__SHIFT                                                                  0x0
+#define BIFPLR6_1_SLOT_CAP2__RESERVED_MASK                                                                    0xFFFFFFFFL
+//BIFPLR6_1_SLOT_CNTL2
+#define BIFPLR6_1_SLOT_CNTL2__RESERVED__SHIFT                                                                 0x0
+#define BIFPLR6_1_SLOT_CNTL2__RESERVED_MASK                                                                   0xFFFFL
+//BIFPLR6_1_SLOT_STATUS2
+#define BIFPLR6_1_SLOT_STATUS2__RESERVED__SHIFT                                                               0x0
+#define BIFPLR6_1_SLOT_STATUS2__RESERVED_MASK                                                                 0xFFFFL
+//BIFPLR6_1_MSI_CAP_LIST
+#define BIFPLR6_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
+#define BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
+#define BIFPLR6_1_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
+#define BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
+//BIFPLR6_1_MSI_MSG_CNTL
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
+//BIFPLR6_1_MSI_MSG_ADDR_LO
+#define BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
+#define BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
+//BIFPLR6_1_MSI_MSG_ADDR_HI
+#define BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
+#define BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_1_MSI_MSG_DATA
+#define BIFPLR6_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
+#define BIFPLR6_1_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0xFFFFL
+//BIFPLR6_1_MSI_MSG_DATA_64
+#define BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
+#define BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
+//BIFPLR6_1_SSID_CAP_LIST
+#define BIFPLR6_1_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
+#define BIFPLR6_1_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
+#define BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
+//BIFPLR6_1_SSID_CAP
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
+//BIFPLR6_1_MSI_MAP_CAP_LIST
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                           0x8
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                               0x00FFL
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                             0xFF00L
+//BIFPLR6_1_MSI_MAP_CAP
+#define BIFPLR6_1_MSI_MAP_CAP__EN__SHIFT                                                                      0x0
+#define BIFPLR6_1_MSI_MAP_CAP__FIXD__SHIFT                                                                    0x1
+#define BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                0xb
+#define BIFPLR6_1_MSI_MAP_CAP__EN_MASK                                                                        0x0001L
+#define BIFPLR6_1_MSI_MAP_CAP__FIXD_MASK                                                                      0x0002L
+#define BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE_MASK                                                                  0xF800L
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
+//BIFPLR6_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR6_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
+//BIFPLR6_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
+//BIFPLR6_1_PCIE_PORT_VC_CNTL
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
+//BIFPLR6_1_PCIE_PORT_VC_STATUS
+#define BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
+#define BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
+//BIFPLR6_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR6_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x007F0000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
+//BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
+//BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
+//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
+//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
+//BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIFPLR6_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
+//BIFPLR6_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
+//BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
+//BIFPLR6_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
+//BIFPLR6_1_PCIE_CORR_ERR_MASK
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
+//BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                                0xc
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                                  0x00001000L
+//BIFPLR6_1_PCIE_HDR_LOG0
+#define BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_HDR_LOG1
+#define BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_HDR_LOG2
+#define BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_HDR_LOG3
+#define BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
+#define BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                   0x0
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                               0x1
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                  0x2
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                     0x00000001L
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                 0x00000002L
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                    0x00000004L
+//BIFPLR6_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                             0x1
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                        0x2
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                   0x3
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                      0x4
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                        0x5
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                           0x6
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                            0x1b
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                    0x00000001L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                               0x00000002L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                          0x00000004L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                     0x00000008L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                        0x00000010L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                          0x00000020L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                             0x00000040L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                              0xF8000000L
+//BIFPLR6_1_PCIE_ERR_SRC_ID
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                     0x0
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                           0x10
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                             0xFFFF0000L
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR6_1_PCIE_LINK_CNTL3
+#define BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
+#define BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
+#define BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
+#define BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
+//BIFPLR6_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
+#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
+//BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
+//BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
+//BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR6_1_PCIE_ACS_CAP
+#define BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
+#define BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
+#define BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
+#define BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
+#define BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
+#define BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
+#define BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
+#define BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
+#define BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
+#define BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
+//BIFPLR6_1_PCIE_ACS_CNTL
+#define BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
+#define BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
+#define BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
+#define BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
+#define BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
+#define BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
+#define BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
+//BIFPLR6_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
+//BIFPLR6_1_PCIE_MC_CAP
+#define BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
+#define BIFPLR6_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                                         0x8
+#define BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
+#define BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
+#define BIFPLR6_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                           0x3F00L
+#define BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
+//BIFPLR6_1_PCIE_MC_CNTL
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
+//BIFPLR6_1_PCIE_MC_ADDR0
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
+//BIFPLR6_1_PCIE_MC_ADDR1
+#define BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
+#define BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_RCV0
+#define BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
+#define BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_RCV1
+#define BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
+#define BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                0x0
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                               0x6
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                  0x0000003FL
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                 0xFFFFFFC0L
+//BIFPLR6_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                               0x0
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIFPLR6_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                            0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                            0x1
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                              0x2
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                              0x3
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                              0x4
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                             0x8
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                            0x10
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                            0x13
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                              0x00000001L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                              0x00000002L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                0x00000004L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                0x00000008L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                0x00000010L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                               0x0000FF00L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                              0x00030000L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                              0x00F80000L
+//BIFPLR6_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                  0x1
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                    0x2
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                    0x3
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                        0x8
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                        0x10
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                        0x1d
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                    0x00000001L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                    0x00000002L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                      0x00000004L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                      0x00000008L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                          0x0000FF00L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                          0x03FF0000L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                          0xE0000000L
+//BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                               0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                               0x3
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                 0x00000003L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                 0x000000F8L
+//BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR6_1_PCIE_DPC_CAP_LIST
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT                                             0x5
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT                            0x6
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT                                 0x7
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT                                                   0x8
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT                             0xc
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK                                                    0x001FL
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK                                               0x0020L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK                              0x0040L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK                                   0x0080L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK                                                     0x0F00L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK                               0x1000L
+//BIFPLR6_1_PCIE_DPC_CNTL
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT                                                    0x0
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT                                                0x2
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT                                                  0x3
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT                                                    0x4
+#define BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT                                   0x5
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT                                                  0x6
+#define BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT                                              0x7
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK                                                      0x0003L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK                                                  0x0004L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK                                                    0x0008L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK                                                      0x0010L
+#define BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK                                     0x0020L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK                                                    0x0040L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK                                                0x0080L
+//BIFPLR6_1_PCIE_DPC_STATUS
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT                                                  0x1
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT                                                0x3
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT                                                         0x4
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT                                        0x5
+#define BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT                                          0x8
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK                                                    0x0001L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK                                                    0x0006L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK                                                  0x0008L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK                                                           0x0010L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK                                          0x0060L
+#define BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK                                            0x1F00L
+//BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT                                        0x0
+#define BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK                                          0xFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_STATUS
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT                                                       0x0
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT                                                       0x1
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT                                                          0x2
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT                                                        0x8
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT                                                        0x9
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT                                                           0xa
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT                                                       0x10
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT                                                       0x11
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT                                                          0x12
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK                                                         0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK                                                         0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK                                                            0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK                                                          0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK                                                          0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK                                                             0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK                                                         0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK                                                         0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK                                                            0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_MASK
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT                                                         0x0
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT                                                         0x1
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT                                                            0x2
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT                                                          0x8
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT                                                          0x9
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT                                                             0xa
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT                                                         0x10
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT                                                         0x11
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT                                                            0x12
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK                                                           0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK                                                           0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK                                                              0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK                                                            0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK                                                            0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO_MASK                                                               0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK                                                           0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK                                                           0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK                                                              0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT                                                     0x0
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT                                                     0x1
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT                                                        0x2
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT                                                      0x8
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT                                                      0x9
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT                                                         0xa
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT                                                     0x10
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT                                                     0x11
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT                                                        0x12
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK                                                       0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK                                                       0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK                                                          0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK                                                        0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK                                                        0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK                                                           0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK                                                       0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK                                                       0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK                                                          0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT                                                    0x0
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT                                                    0x1
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT                                                       0x2
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT                                                     0x8
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT                                                     0x9
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT                                                        0xa
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT                                                    0x10
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT                                                    0x11
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT                                                       0x12
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK                                                      0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK                                                      0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK                                                         0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK                                                       0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK                                                       0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK                                                          0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK                                                      0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK                                                      0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK                                                         0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK                                                    0xFFFFFFFFL
+//BIFPLR6_1_PCIE_ESM_CAP_LIST
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                           0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                          0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                              0x0000FFFFL
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                             0x000F0000L
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                            0xFFF00000L
+//BIFPLR6_1_PCIE_ESM_HEADER_1
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                     0x0
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                       0x10
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                       0x14
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                       0x0000FFFFL
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                         0x000F0000L
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                         0xFFF00000L
+//BIFPLR6_1_PCIE_ESM_HEADER_2
+#define BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                            0x0
+#define BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID_MASK                                                              0xFFFFL
+//BIFPLR6_1_PCIE_ESM_STATUS
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                0x9
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                    0x01FFL
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                  0x0E00L
+//BIFPLR6_1_PCIE_ESM_CTRL
+#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                           0xf
+#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                             0x8000L
+//BIFPLR6_1_PCIE_ESM_CAP_1
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                             0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                             0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                             0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                             0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                             0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                             0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                             0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                             0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                             0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                             0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                             0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                             0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                             0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                             0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                             0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                             0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                             0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                             0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                             0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                             0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                            0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                            0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                            0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                            0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                            0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                            0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                            0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                            0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                            0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                            0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                               0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                               0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                               0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                               0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                               0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                               0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                               0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                               0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                               0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                               0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                               0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                               0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                               0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                               0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                               0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                               0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                               0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                               0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                               0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                               0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                              0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                              0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                              0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                              0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                              0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                              0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                              0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                              0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                              0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                              0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_2
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                            0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                            0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                            0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                            0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                            0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                            0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                            0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                            0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                            0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                            0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                            0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                            0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                            0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                            0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                            0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                            0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                            0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                            0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                            0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                            0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                            0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                            0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                            0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                            0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                            0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                            0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                            0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                            0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                            0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                            0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                              0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                              0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                              0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                              0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                              0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                              0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                              0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                              0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                              0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                              0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                              0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                              0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                              0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                              0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                              0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                              0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                              0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                              0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                              0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                              0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                              0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                              0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                              0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                              0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                              0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                              0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                              0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                              0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                              0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                              0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_3
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                            0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                            0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                            0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                            0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                            0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                            0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                            0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                            0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                            0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                            0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                            0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                            0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                            0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                            0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                            0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                            0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                            0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                            0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                            0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                            0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                              0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                              0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                              0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                              0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                              0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                              0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                              0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                              0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                              0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                              0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                              0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                              0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                              0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                              0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                              0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                              0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                              0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                              0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                              0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                              0x00080000L
+//BIFPLR6_1_PCIE_ESM_CAP_4
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                            0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                            0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                            0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                            0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                            0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                            0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                            0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                            0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                            0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                            0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                            0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                            0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                            0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                            0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                            0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                            0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                            0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                            0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                            0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                            0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                            0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                            0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                            0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                            0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                            0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                            0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                            0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                            0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                            0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                            0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                              0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                              0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                              0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                              0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                              0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                              0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                              0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                              0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                              0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                              0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                              0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                              0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                              0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                              0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                              0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                              0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                              0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                              0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                              0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                              0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                              0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                              0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                              0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                              0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                              0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                              0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                              0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                              0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                              0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                              0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_5
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                            0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                            0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                            0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                            0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                            0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                            0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                            0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                            0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                            0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                            0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                            0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                            0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                            0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                            0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                            0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                            0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                            0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                            0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                            0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                            0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                            0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                            0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                            0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                            0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                            0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                            0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                            0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                            0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                            0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                            0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                              0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                              0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                              0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                              0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                              0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                              0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                              0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                              0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                              0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                              0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                              0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                              0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                              0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                              0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                              0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                              0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                              0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                              0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                              0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                              0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                              0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                              0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                              0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                              0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                              0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                              0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                              0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                              0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                              0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                              0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_6
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                            0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                            0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                            0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                            0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                            0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                            0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                            0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                            0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                            0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                            0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                            0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                            0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                            0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                            0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                            0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                            0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                            0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                            0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                            0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                            0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                            0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                            0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                            0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                            0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                            0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                            0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                            0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                            0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                            0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                            0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                              0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                              0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                              0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                              0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                              0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                              0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                              0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                              0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                              0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                              0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                              0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                              0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                              0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                              0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                              0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                              0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                              0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                              0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                              0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                              0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                              0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                              0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                              0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                              0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                              0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                              0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                              0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                              0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                              0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                              0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_7
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                            0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                            0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                            0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                            0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                            0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                            0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                            0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                            0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                            0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                            0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                            0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                            0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                            0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                            0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                            0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                            0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                            0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                            0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                            0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                            0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                            0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                            0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                            0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                            0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                            0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                            0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                            0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                            0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                            0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                            0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                            0x1e
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                              0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                              0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                              0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                              0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                              0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                              0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                              0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                              0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                              0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                              0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                              0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                              0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                              0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                              0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                              0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                              0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                              0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                              0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                              0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                              0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                              0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                              0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                              0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                              0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                              0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                              0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                              0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                              0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                              0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                              0x20000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                              0x40000000L
+//BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//BIFPLR6_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT                       0x0
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT                                      0x1
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                           0x1f
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK                         0x00000001L
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK                                        0x007FFFFEL
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                             0x80000000L
+//BIFPLR6_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR6_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                       0x0
+#define BIFPLR6_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                                 0x1f
+#define BIFPLR6_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                         0x007FFFFFL
+#define BIFPLR6_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                                   0x80000000L
+//BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIFPLR6_1_LINK_CAP_16GT
+#define BIFPLR6_1_LINK_CAP_16GT__RESERVED__SHIFT                                                              0x0
+#define BIFPLR6_1_LINK_CAP_16GT__RESERVED_MASK                                                                0xFFFFFFFFL
+//BIFPLR6_1_LINK_CNTL_16GT
+#define BIFPLR6_1_LINK_CNTL_16GT__RESERVED__SHIFT                                                             0x0
+#define BIFPLR6_1_LINK_CNTL_16GT__RESERVED_MASK                                                               0xFFFFFFFFL
+//BIFPLR6_1_LINK_STATUS_16GT
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                         0x0
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                                   0x1
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                                   0x2
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                                   0x3
+#define BIFPLR6_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                                     0x4
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                           0x00000001L
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                                     0x00000002L
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                                     0x00000004L
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                                     0x00000008L
+#define BIFPLR6_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                       0x00000010L
+//BIFPLR6_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT                 0x0
+#define BIFPLR6_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK                   0x0000FFFFL
+//BIFPLR6_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR6_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR6_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT                   0x0
+#define BIFPLR6_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK                     0x0000FFFFL
+//BIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                             0x0
+#define BIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                             0x4
+#define BIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                               0x0FL
+#define BIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                               0xF0L
+//BIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                           0x0
+#define BIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                           0x4
+#define BIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                             0x0FL
+#define BIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                             0xF0L
+//BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIFPLR6_1_MARGINING_PORT_CAP
+#define BIFPLR6_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                          0x0
+#define BIFPLR6_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                            0x0001L
+//BIFPLR6_1_MARGINING_PORT_STATUS
+#define BIFPLR6_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                               0x0
+#define BIFPLR6_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                      0x1
+#define BIFPLR6_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                                 0x0001L
+#define BIFPLR6_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                        0x0002L
+//BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                                   0x0
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                       0x3
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                       0x6
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                                    0x8
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                                     0x0007L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                         0x0038L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                         0x0040L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                      0xFF00L
+//BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                          0x0
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                              0x3
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                              0x6
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                           0x8
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                            0x0007L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                                0x0038L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                                0x0040L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                             0xFF00L
+//BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                                 0x0
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                                     0x3
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                                     0x6
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                                  0x8
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                                   0x0007L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                       0x0038L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                       0x0040L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                                    0xFF00L
+//BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                        0x0
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                            0x3
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                            0x6
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                         0x8
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                          0x0007L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                              0x0038L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                              0x0040L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                           0xFF00L
+//BIFPLR6_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//BIFPLR6_1_PCIE_CCIX_HEADER_1
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT                                                   0x0
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT                                                     0x10
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT                                                     0x14
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK                                                     0x0000FFFFL
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK                                                       0x000F0000L
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK                                                       0xFFF00000L
+//BIFPLR6_1_PCIE_CCIX_HEADER_2
+#define BIFPLR6_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT                                                           0x0
+#define BIFPLR6_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK                                                             0xFFFFL
+//BIFPLR6_1_PCIE_CCIX_CAP
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT                                                    0x0
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT                                       0x1
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT                      0x3
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT                                                  0x4
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT                                        0x8
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK                                                      0x0001L
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK                                         0x0006L
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK                        0x0008L
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK                                                    0x0070L
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK                                          0x0700L
+//BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT                                            0x0
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT                                              0x1
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT                                              0x2
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT                                             0x5
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT                                             0x9
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT                                             0xe
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK                                              0x00000001L
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK                                                0x00000002L
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK                                                0x00000004L
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK                                               0x00000020L
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK                                               0x00000200L
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK                                               0x00004000L
+//BIFPLR6_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR6_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT                                                     0x0
+#define BIFPLR6_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIFPLR6_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR6_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT                                          0x0
+#define BIFPLR6_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT                                       0x7
+#define BIFPLR6_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK                                            0x0000007FL
+#define BIFPLR6_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK                                         0x00000080L
+//BIFPLR6_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT                                                   0x0
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT                                          0x7
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT                                                   0x8
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT                                                       0xf
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT                         0x10
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT                         0x14
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT                                                0x18
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT                                                  0x19
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT                            0x1a
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK                                                     0x0000007FL
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK                                            0x00000080L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK                                                     0x00007F00L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK                                                         0x00008000L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK                           0x00070000L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK                           0x00700000L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK                                                  0x01000000L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK                                                    0x02000000L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK                              0x1C000000L
+//BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT                     0x0
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT                     0x4
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK                       0x0FL
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK                       0xF0L
+//BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT                   0x0
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT                   0x4
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK                     0x0FL
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK                     0xF0L
+//BIFPLR6_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR6_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT                               0x0
+#define BIFPLR6_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK                                 0x00000001L
+//BIFPLR6_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR6_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT                               0x0
+#define BIFPLR6_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK                                 0x00000001L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+//BIF_CFG_DEV0_RC1_VENDOR_ID
+#define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV0_RC1_DEVICE_ID
+#define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV0_RC1_COMMAND
+#define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN__SHIFT                                                             0x1
+#define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN__SHIFT                                                        0x2
+#define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                0x6
+#define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN__SHIFT                                                              0x8
+#define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS__SHIFT                                                              0xa
+#define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN_MASK                                                                0x0001L
+#define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN_MASK                                                               0x0002L
+#define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN_MASK                                                          0x0004L
+#define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING_MASK                                                            0x0080L
+#define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN_MASK                                                                0x0100L
+#define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS_MASK                                                                0x0400L
+//BIF_CFG_DEV0_RC1_STATUS
+#define BIF_CFG_DEV0_RC1_STATUS__IMMEDIATE_READINESS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS__SHIFT                                                            0x3
+#define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST__SHIFT                                                              0x4
+#define BIF_CFG_DEV0_RC1_STATUS__PCI_66_CAP__SHIFT                                                            0x5
+#define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                              0x8
+#define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                 0xd
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_RC1_STATUS__IMMEDIATE_READINESS_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS_MASK                                                              0x0008L
+#define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST_MASK                                                                0x0010L
+#define BIF_CFG_DEV0_RC1_STATUS__PCI_66_CAP_MASK                                                              0x0020L
+#define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                0x0100L
+#define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING_MASK                                                           0x0600L
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                   0x2000L
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                   0x4000L
+#define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED_MASK                                                   0x8000L
+//BIF_CFG_DEV0_RC1_REVISION_ID
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID_MASK                                                       0x0FL
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID_MASK                                                       0xF0L
+//BIF_CFG_DEV0_RC1_PROG_INTERFACE
+#define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_RC1_SUB_CLASS
+#define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS_MASK                                                            0xFFL
+//BIF_CFG_DEV0_RC1_BASE_CLASS
+#define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS_MASK                                                          0xFFL
+//BIF_CFG_DEV0_RC1_CACHE_LINE
+#define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                     0xFFL
+//BIF_CFG_DEV0_RC1_LATENCY
+#define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER_MASK                                                          0xFFL
+//BIF_CFG_DEV0_RC1_HEADER
+#define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE_MASK                                                             0x7FL
+#define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE_MASK                                                             0x80L
+//BIF_CFG_DEV0_RC1_BIST
+#define BIF_CFG_DEV0_RC1_BIST__BIST_COMP__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC1_BIST__BIST_STRT__SHIFT                                                               0x6
+#define BIF_CFG_DEV0_RC1_BIST__BIST_CAP__SHIFT                                                                0x7
+#define BIF_CFG_DEV0_RC1_BIST__BIST_COMP_MASK                                                                 0x0FL
+#define BIF_CFG_DEV0_RC1_BIST__BIST_STRT_MASK                                                                 0x40L
+#define BIF_CFG_DEV0_RC1_BIST__BIST_CAP_MASK                                                                  0x80L
+//BIF_CFG_DEV0_RC1_BASE_ADDR_1
+#define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_BASE_ADDR_2
+#define BIF_CFG_DEV0_RC1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC1_BASE_ADDR_2__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                               0x18
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                           0x0000FF00L
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                             0x00FF0000L
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_RC1_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                       0xc
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                     0x000FL
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                    0x0F00L
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                         0xF000L
+//BIF_CFG_DEV0_RC1_SECONDARY_STATUS
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                           0x7
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                    0x8
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                               0x9
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                         0xb
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                       0xc
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                       0xd
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                       0xe
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_CAP_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                             0x0080L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                      0x0100L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                 0x0600L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                           0x0800L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                         0x1000L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                         0x2000L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                         0x4000L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                         0x8000L
+//BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                0x4
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                0x10
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                               0x14
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                   0x0000000FL
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                  0x0000FFF0L
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                          0x4
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                             0x0000000FL
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                            0x0000FFF0L
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC1_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                              0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                              0x10
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                0xFFFF0000L
+//BIF_CFG_DEV0_RC1_CAP_PTR
+#define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR_MASK                                                                0xFFL
+//BIF_CFG_DEV0_RC1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_RC1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                    0xFFL
+//BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                      0x1
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                        0x8
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                      0x9
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                         0xa
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                    0xb
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                        0x0002L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                              0x0020L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                          0x0100L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                        0x0200L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                           0x0400L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                      0x0800L
+//BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                  0x01L
+//BIF_CFG_DEV0_RC1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV0_RC1_PMI_CAP
+#define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK__SHIFT                                                            0x3
+#define BIF_CFG_DEV0_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                  0x4
+#define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT__SHIFT                                                           0x9
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT__SHIFT                                                          0xb
+#define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION_MASK                                                                0x0007L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK_MASK                                                              0x0008L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                    0x0010L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT_MASK                                                            0x01C0L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT_MASK                                                             0x0200L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT_MASK                                                             0x0400L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT_MASK                                                            0xF800L
+//BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                0x16
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                   0x17
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                     0x18
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                    0x00000003L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                  0x00000008L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN_MASK                                                         0x00000100L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                    0x00001E00L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                     0x00006000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                     0x00008000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                  0x00400000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                     0x00800000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                       0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_RC1_PCIE_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION_MASK                                                               0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE_MASK                                                           0x00F0L
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                      0x0100L
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                       0x3E00L
+//BIF_CFG_DEV0_RC1_DEVICE_CAP
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                      0x3
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                            0x6
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                             0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                          0xf
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                       0x1c
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                        0x00000018L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG_MASK                                                        0x00000020L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                              0x000001C0L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                               0x00000E00L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                            0x00008000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE_MASK                                                         0x10000000L
+//BIF_CFG_DEV0_RC1_DEVICE_CNTL
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                  0xa
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                      0xb
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                            0xc
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                              0xf
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                   0x00E0L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                    0x0100L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                    0x0200L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                    0x0400L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                        0x0800L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                              0x7000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                0x8000L
+//BIF_CFG_DEV0_RC1_DEVICE_STATUS
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                      0x2
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                              0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                    0x0002L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR_MASK                                                        0x0004L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                0x0020L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                    0x0040L
+//BIF_CFG_DEV0_RC1_LINK_CAP
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                    0xc
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                              0x12
+#define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                         0x13
+#define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                            0x15
+#define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                         0x16
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER__SHIFT                                                         0x18
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED_MASK                                                            0x0000000FL
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH_MASK                                                            0x000003F0L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT_MASK                                                            0x00000C00L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                      0x00007000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                       0x00038000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                0x00040000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                           0x00080000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                           0x00100000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                              0x00200000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                           0x00400000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER_MASK                                                           0xFF000000L
+//BIF_CFG_DEV0_RC1_LINK_CNTL
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                   0x6
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                          0xb
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                              0xe
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL_MASK                                                           0x0003L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                     0x0040L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                            0x0100L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                            0x0400L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                            0x0800L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                0xC000L
+//BIF_CFG_DEV0_RC1_LINK_STATUS
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                            0x4
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING__SHIFT                                                    0xb
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                        0xe
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                        0xf
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                 0x000FL
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                              0x03F0L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING_MASK                                                      0x0800L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                     0x1000L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE_MASK                                                          0x2000L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                          0x4000L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                          0x8000L
+//BIF_CFG_DEV0_RC1_SLOT_CAP
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                              0x1
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                              0x3
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                               0x4
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                     0x6
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                0xf
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                      0x12
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                   0x13
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                   0x00000001L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                0x00000002L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                    0x00000004L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                0x00000008L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                 0x00000010L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                      0x00000020L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                       0x00000040L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                  0x00007F80L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                  0x00018000L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                         0x00020000L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                        0x00040000L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                     0xFFF80000L
+//BIF_CFG_DEV0_RC1_SLOT_CNTL
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                              0x2
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                         0x3
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                0x6
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                0xa
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                         0xb
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                0xc
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                        0xd
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                               0x0001L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                0x0004L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                           0x0008L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                            0x0010L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                  0x00C0L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                   0x0300L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                  0x0400L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                           0x0800L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                          0x2000L
+//BIF_CFG_DEV0_RC1_SLOT_STATUS
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                               0x1
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                               0x2
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                          0x3
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                0x4
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                            0x6
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                     0x7
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                0x0001L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                 0x0004L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                            0x0008L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                              0x0040L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                       0x0080L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                   0x0100L
+//BIF_CFG_DEV0_RC1_ROOT_CNTL
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                               0x2
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                 0x0004L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                           0x0010L
+//BIF_CFG_DEV0_RC1_ROOT_CAP
+#define BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                               0x0001L
+//BIF_CFG_DEV0_RC1_ROOT_STATUS
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS__SHIFT                                                       0x10
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING__SHIFT                                                      0x11
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS_MASK                                                         0x00010000L
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING_MASK                                                        0x00020000L
+//BIF_CFG_DEV0_RC1_DEVICE_CAP2
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                        0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                         0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                       0x6
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                       0x7
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                           0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                        0xa
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                    0xb
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                               0xc
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                    0xe
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                  0x10
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                  0x11
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                   0x12
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                     0x14
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                     0x15
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                         0x16
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                   0x18
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                    0x1f
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                        0x0000000FL
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                          0x00000010L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                           0x00000020L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                         0x00000080L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                             0x00000200L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                          0x00000400L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                      0x00000800L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                 0x00003000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                      0x0000C000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                     0x000C0000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                       0x00100000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                           0x00C00000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                     0x03000000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                      0x04000000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                      0x80000000L
+//BIF_CFG_DEV0_RC1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                               0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                             0x6
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                        0x7
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                              0x8
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                           0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                    0xb
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                    0xc
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                         0xd
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                 0x000FL
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                 0x0020L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                               0x0040L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                          0x0080L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                0x0100L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                             0x0200L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                      0x0800L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                      0x1000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN_MASK                                                           0x6000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                       0x8000L
+//BIF_CFG_DEV0_RC1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED_MASK                                                        0xFFFFL
+//BIF_CFG_DEV0_RC1_LINK_CAP2
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                               0x1
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                0x8
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                          0x17
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                          0x18
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                      0x1f
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                 0x000000FEL
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                  0x00000100L
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                             0x007F0000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                            0x00800000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                            0x01000000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__DRS_SUPPORTED_MASK                                                        0x80000000L
+//BIF_CFG_DEV0_RC1_LINK_CNTL2
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                       0x5
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                             0x6
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                              0xa
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                    0xb
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                             0xc
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                   0x000FL
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                         0x0020L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                               0x0040L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN_MASK                                                         0x0380L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                0x0400L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                      0x0800L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                               0xF000L
+//BIF_CFG_DEV0_RC1_LINK_STATUS2
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                       0x1
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                 0x2
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                 0x4
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                   0x5
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                               0x6
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                               0x7
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                            0x8
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                              0x0001L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                         0x0002L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                   0x0004L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                   0x0008L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                   0x0010L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                     0x0020L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                 0x0080L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                              0x0300L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                     0x7000L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                              0x8000L
+//BIF_CFG_DEV0_RC1_SLOT_CAP2
+#define BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_SLOT_CNTL2
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED_MASK                                                            0xFFFFL
+//BIF_CFG_DEV0_RC1_SLOT_STATUS2
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED_MASK                                                          0xFFFFL
+//BIF_CFG_DEV0_RC1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV0_RC1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                            0x9
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN_MASK                                                            0x0001L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                     0x000EL
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                      0x0070L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                         0x0100L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                              0x0200L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                               0x0400L
+//BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                              0x2
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                0xFFFFFFFCL
+//BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA_MASK                                                          0xFFFFL
+//BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                  0xFFFFL
+//BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                    0xFFFFL
+//BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                            0xFFFFL
+//BIF_CFG_DEV0_RC1_SSID_CAP_LIST
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_RC1_SSID_CAP
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                        0x10
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID_MASK                                                          0xFFFF0000L
+//BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_RC1_MSI_MAP_CAP
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD__SHIFT                                                             0x1
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                         0xb
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN_MASK                                                                 0x0001L
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD_MASK                                                               0x0002L
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE_MASK                                                           0xF800L
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                            0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                               0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                              0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                              0x4
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                0x8
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                              0xa
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                             0x00000007L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                0x00000070L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                  0x00000300L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                0x00000C00L
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                    0x18
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                               0x000000FFL
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                      0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                              0x1
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                            0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                0x000EL
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                        0x0001L
+//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x007F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x003F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                        0x4
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                     0x5
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                         0xd
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                        0x12
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                       0x13
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                  0x15
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                 0x16
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                 0x17
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                        0x18
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                         0x19
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                    0x1a
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                          0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                       0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                          0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                           0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                        0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                         0x00020000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                          0x00040000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                         0x00080000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                   0x00100000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                   0x00400000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                   0x00800000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                          0x01000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                           0x02000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                      0x04000000L
+//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                            0x4
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                         0x5
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                            0xc
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                             0xd
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                           0x11
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                            0x12
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                           0x13
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                     0x14
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                      0x15
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                     0x16
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                     0x17
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                            0x18
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                             0x19
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                        0x1a
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                              0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                           0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                              0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                               0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                        0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                            0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                             0x00020000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                              0x00040000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                             0x00080000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                       0x00100000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                        0x00200000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                       0x00400000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                              0x01000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                               0x02000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                          0x04000000L
+//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                    0x4
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                    0xc
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                     0xd
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                              0xf
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                  0x10
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                   0x11
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                    0x12
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                   0x13
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                             0x14
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                              0x15
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                             0x16
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                             0x17
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                    0x18
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                     0x19
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                0x1a
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                      0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                   0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                      0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                       0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                     0x00020000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                      0x00040000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                     0x00080000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                               0x00100000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                0x00200000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                               0x00400000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                               0x00800000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                      0x01000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                       0x02000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                  0x04000000L
+//BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                         0x7
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                             0xc
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                            0xd
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                            0x00000040L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                           0x00000080L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                0x00000100L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                               0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                              0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                       0x00008000L
+//BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                              0x6
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                             0x7
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                0xd
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                         0xe
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                         0xf
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                0x00000040L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                               0x00000080L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                           0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                           0x00008000L
+//BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                         0x7
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                     0x9
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                      0xa
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                 0xb
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                         0xc
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                            0x0000001FL
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                           0x00000080L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                            0x00000100L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                       0x00000200L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                        0x00000400L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                   0x00000800L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                           0x00001000L
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                           0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                             0x00000004L
+//BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                      0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                 0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                            0x3
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                               0x4
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                    0x6
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                     0x1b
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                        0x00000002L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                   0x00000004L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                              0x00000008L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                   0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                       0xF8000000L
+//BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                    0x10
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                      0xFFFF0000L
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                   0x00000002L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                  0x0000FFFFL
+//BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                            0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                            0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                         0x3
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                             0x4
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                              0x5
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                           0x6
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                              0x0002L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                              0x0004L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                           0x0008L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                               0x0010L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                0x0020L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                             0x0040L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                        0xFF00L
+//BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                        0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                     0x3
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                          0x0004L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                       0x0008L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                         0x0040L
+//BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                    0x0
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                    0x1f
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                      0x007FFFFFL
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                      0x80000000L
+//BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                  0x007FFFFFL
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_RC1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_RC1_LINK_CAP_16GT__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC1_LINK_CAP_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LINK_CNTL_16GT__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC1_LINK_CNTL_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                            0x1
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                    0x00000001L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                              0x00000002L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                              0x00000004L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                              0x00000008L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                0x00000010L
+//BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT          0x0
+#define BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK            0x0000FFFFL
+//BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                   0x0
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                     0x0001L
+//BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                        0x0
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                               0x1
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                          0x0001L
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                 0x0002L
+//BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+//BIF_CFG_DEV1_RC1_VENDOR_ID
+#define BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV1_RC1_DEVICE_ID
+#define BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV1_RC1_COMMAND
+#define BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN__SHIFT                                                              0x0
+#define BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN__SHIFT                                                             0x1
+#define BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN__SHIFT                                                        0x2
+#define BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN__SHIFT                                                         0x5
+#define BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                0x6
+#define BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING__SHIFT                                                          0x7
+#define BIF_CFG_DEV1_RC1_COMMAND__SERR_EN__SHIFT                                                              0x8
+#define BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN__SHIFT                                                          0x9
+#define BIF_CFG_DEV1_RC1_COMMAND__INT_DIS__SHIFT                                                              0xa
+#define BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN_MASK                                                                0x0001L
+#define BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN_MASK                                                               0x0002L
+#define BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN_MASK                                                          0x0004L
+#define BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN_MASK                                                           0x0020L
+#define BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                  0x0040L
+#define BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING_MASK                                                            0x0080L
+#define BIF_CFG_DEV1_RC1_COMMAND__SERR_EN_MASK                                                                0x0100L
+#define BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN_MASK                                                            0x0200L
+#define BIF_CFG_DEV1_RC1_COMMAND__INT_DIS_MASK                                                                0x0400L
+//BIF_CFG_DEV1_RC1_STATUS
+#define BIF_CFG_DEV1_RC1_STATUS__IMMEDIATE_READINESS__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_RC1_STATUS__INT_STATUS__SHIFT                                                            0x3
+#define BIF_CFG_DEV1_RC1_STATUS__CAP_LIST__SHIFT                                                              0x4
+#define BIF_CFG_DEV1_RC1_STATUS__PCI_66_CAP__SHIFT                                                            0x5
+#define BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                     0x7
+#define BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                              0x8
+#define BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING__SHIFT                                                         0x9
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                   0xb
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                 0xc
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                 0xd
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                 0xe
+#define BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                 0xf
+#define BIF_CFG_DEV1_RC1_STATUS__IMMEDIATE_READINESS_MASK                                                     0x0001L
+#define BIF_CFG_DEV1_RC1_STATUS__INT_STATUS_MASK                                                              0x0008L
+#define BIF_CFG_DEV1_RC1_STATUS__CAP_LIST_MASK                                                                0x0010L
+#define BIF_CFG_DEV1_RC1_STATUS__PCI_66_CAP_MASK                                                              0x0020L
+#define BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE_MASK                                                       0x0080L
+#define BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                0x0100L
+#define BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING_MASK                                                           0x0600L
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                     0x0800L
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                   0x1000L
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                   0x2000L
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                   0x4000L
+#define BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED_MASK                                                   0x8000L
+//BIF_CFG_DEV1_RC1_REVISION_ID
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                     0x4
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID_MASK                                                       0x0FL
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID_MASK                                                       0xF0L
+//BIF_CFG_DEV1_RC1_PROG_INTERFACE
+#define BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                  0xFFL
+//BIF_CFG_DEV1_RC1_SUB_CLASS
+#define BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS_MASK                                                            0xFFL
+//BIF_CFG_DEV1_RC1_BASE_CLASS
+#define BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS_MASK                                                          0xFFL
+//BIF_CFG_DEV1_RC1_CACHE_LINE
+#define BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                     0xFFL
+//BIF_CFG_DEV1_RC1_LATENCY
+#define BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER_MASK                                                          0xFFL
+//BIF_CFG_DEV1_RC1_HEADER
+#define BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE__SHIFT                                                           0x7
+#define BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE_MASK                                                             0x7FL
+#define BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE_MASK                                                             0x80L
+//BIF_CFG_DEV1_RC1_BIST
+#define BIF_CFG_DEV1_RC1_BIST__BIST_COMP__SHIFT                                                               0x0
+#define BIF_CFG_DEV1_RC1_BIST__BIST_STRT__SHIFT                                                               0x6
+#define BIF_CFG_DEV1_RC1_BIST__BIST_CAP__SHIFT                                                                0x7
+#define BIF_CFG_DEV1_RC1_BIST__BIST_COMP_MASK                                                                 0x0FL
+#define BIF_CFG_DEV1_RC1_BIST__BIST_STRT_MASK                                                                 0x40L
+#define BIF_CFG_DEV1_RC1_BIST__BIST_CAP_MASK                                                                  0x80L
+//BIF_CFG_DEV1_RC1_BASE_ADDR_1
+#define BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_BASE_ADDR_2
+#define BIF_CFG_DEV1_RC1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC1_BASE_ADDR_2__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                         0x8
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                           0x10
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                               0x18
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                             0x000000FFL
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                           0x0000FF00L
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                             0x00FF0000L
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                 0xFF000000L
+//BIF_CFG_DEV1_RC1_IO_BASE_LIMIT
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                        0x4
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                  0x8
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                       0xc
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                     0x000FL
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                    0x0F00L
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                         0xF000L
+//BIF_CFG_DEV1_RC1_SECONDARY_STATUS
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                  0x5
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                           0x7
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                    0x8
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                               0x9
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                         0xb
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                       0xc
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                       0xd
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                       0xe
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                       0xf
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_CAP_MASK                                                    0x0020L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                             0x0080L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                      0x0100L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                 0x0600L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                           0x0800L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                         0x1000L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                         0x2000L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                         0x4000L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                         0x8000L
+//BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                0x4
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                0x10
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                               0x14
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                   0x0000000FL
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                  0x0000FFF0L
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                          0x4
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                          0x10
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                         0x14
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                             0x0000000FL
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                            0x0000FFF0L
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                            0x000F0000L
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                           0xFFF00000L
+//BIF_CFG_DEV1_RC1_PREF_BASE_UPPER
+#define BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                              0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                              0x10
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                0xFFFF0000L
+//BIF_CFG_DEV1_RC1_CAP_PTR
+#define BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR__SHIFT                                                              0x0
+#define BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR_MASK                                                                0xFFL
+//BIF_CFG_DEV1_RC1_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_RC1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_RC1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_INTERRUPT_LINE
+#define BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                  0xFFL
+//BIF_CFG_DEV1_RC1_INTERRUPT_PIN
+#define BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                    0xFFL
+//BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                      0x1
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                       0x3
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                      0x4
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                            0x5
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                          0x6
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                  0x7
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                        0x8
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                      0x9
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                         0xa
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                    0xb
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                        0x0002L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                         0x0008L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                        0x0010L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                              0x0020L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                            0x0040L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                    0x0080L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                          0x0100L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                        0x0200L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                           0x0400L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                      0x0800L
+//BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                  0x01L
+//BIF_CFG_DEV1_RC1_PMI_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV1_RC1_PMI_CAP
+#define BIF_CFG_DEV1_RC1_PMI_CAP__VERSION__SHIFT                                                              0x0
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK__SHIFT                                                            0x3
+#define BIF_CFG_DEV1_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                  0x4
+#define BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                    0x5
+#define BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT__SHIFT                                                          0x6
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT__SHIFT                                                           0x9
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT__SHIFT                                                           0xa
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT__SHIFT                                                          0xb
+#define BIF_CFG_DEV1_RC1_PMI_CAP__VERSION_MASK                                                                0x0007L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK_MASK                                                              0x0008L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                    0x0010L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                      0x0020L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT_MASK                                                            0x01C0L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT_MASK                                                             0x0200L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT_MASK                                                             0x0400L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT_MASK                                                            0xF800L
+//BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                0x3
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                       0x8
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                  0x9
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                   0xd
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                   0xf
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                0x16
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                   0x17
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                     0x18
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                    0x00000003L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                  0x00000008L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN_MASK                                                         0x00000100L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                    0x00001E00L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                     0x00006000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                     0x00008000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                  0x00400000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                     0x00800000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                       0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV1_RC1_PCIE_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                         0x4
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                     0x9
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION_MASK                                                               0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE_MASK                                                           0x00F0L
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                      0x0100L
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                       0x3E00L
+//BIF_CFG_DEV1_RC1_DEVICE_CAP
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                      0x3
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                      0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                            0x6
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                             0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                          0xf
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                       0x1c
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                 0x00000007L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                        0x00000018L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG_MASK                                                        0x00000020L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                              0x000001C0L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                               0x00000E00L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                            0x00008000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE_MASK                                                         0x10000000L
+//BIF_CFG_DEV1_RC1_DEVICE_CNTL
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                 0x1
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                 0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                  0x8
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                  0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                  0xa
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                      0xb
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                            0xc
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                              0xf
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                   0x0002L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                     0x0010L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                   0x00E0L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                    0x0100L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                    0x0200L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                    0x0400L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                        0x0800L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                              0x7000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                0x8000L
+//BIF_CFG_DEV1_RC1_DEVICE_STATUS
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                  0x1
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                      0x2
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                   0x3
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR__SHIFT                                                        0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                              0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                  0x6
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR_MASK                                                         0x0001L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                    0x0002L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR_MASK                                                        0x0004L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED_MASK                                                     0x0008L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR_MASK                                                          0x0010L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                0x0020L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                    0x0040L
+//BIF_CFG_DEV1_RC1_LINK_CAP
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH__SHIFT                                                          0x4
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                    0xc
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                     0xf
+#define BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                              0x12
+#define BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                         0x13
+#define BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                         0x14
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                            0x15
+#define BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                         0x16
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER__SHIFT                                                         0x18
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED_MASK                                                            0x0000000FL
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH_MASK                                                            0x000003F0L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT_MASK                                                            0x00000C00L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                      0x00007000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                       0x00038000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                0x00040000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                           0x00080000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                           0x00100000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                              0x00200000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                           0x00400000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER_MASK                                                           0xFF000000L
+//BIF_CFG_DEV1_RC1_LINK_CNTL
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                  0x3
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS__SHIFT                                                           0x4
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                       0x5
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                   0x6
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                      0x7
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                          0xb
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                              0xe
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL_MASK                                                           0x0003L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                    0x0008L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS_MASK                                                             0x0010L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK_MASK                                                         0x0020L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                     0x0040L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC_MASK                                                        0x0080L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                            0x0100L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                            0x0400L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                            0x0800L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                0xC000L
+//BIF_CFG_DEV1_RC1_LINK_STATUS
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                            0x4
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING__SHIFT                                                    0xb
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                   0xc
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE__SHIFT                                                        0xd
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                        0xe
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                        0xf
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                 0x000FL
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                              0x03F0L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING_MASK                                                      0x0800L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                     0x1000L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE_MASK                                                          0x2000L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                          0x4000L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                          0x8000L
+//BIF_CFG_DEV1_RC1_SLOT_CAP
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                              0x1
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                  0x2
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                              0x3
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                               0x4
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                    0x5
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                     0x6
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                0x7
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                0xf
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                       0x11
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                      0x12
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                   0x13
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                   0x00000001L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                0x00000002L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                    0x00000004L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                0x00000008L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                 0x00000010L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                      0x00000020L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                       0x00000040L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                  0x00007F80L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                  0x00018000L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                         0x00020000L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                        0x00040000L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                     0xFFF80000L
+//BIF_CFG_DEV1_RC1_SLOT_CNTL
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                              0x2
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                         0x3
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                0x6
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                 0x8
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                0xa
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                         0xb
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                0xc
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                        0xd
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                               0x0001L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                0x0004L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                           0x0008L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                            0x0010L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                  0x00C0L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                   0x0300L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                  0x0400L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                           0x0800L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                  0x1000L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                          0x2000L
+//BIF_CFG_DEV1_RC1_SLOT_STATUS
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                               0x1
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                               0x2
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                          0x3
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                0x4
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                 0x5
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                            0x6
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                     0x7
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                 0x8
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                0x0001L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                 0x0002L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                 0x0004L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                            0x0008L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                  0x0010L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                   0x0020L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                              0x0040L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                       0x0080L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                   0x0100L
+//BIF_CFG_DEV1_RC1_ROOT_CNTL
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                               0x2
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                  0x0001L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                 0x0004L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                           0x0010L
+//BIF_CFG_DEV1_RC1_ROOT_CAP
+#define BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                               0x0001L
+//BIF_CFG_DEV1_RC1_ROOT_STATUS
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS__SHIFT                                                       0x10
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING__SHIFT                                                      0x11
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS_MASK                                                         0x00010000L
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING_MASK                                                        0x00020000L
+//BIF_CFG_DEV1_RC1_DEVICE_CAP2
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                      0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                        0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                         0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                       0x6
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                       0x7
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                       0x8
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                           0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                        0xa
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                    0xb
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                               0xc
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                    0xe
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                  0x10
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                  0x11
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                   0x12
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                     0x14
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                     0x15
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                         0x16
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                   0x18
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                    0x1a
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                    0x1f
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                        0x0000000FL
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                          0x00000010L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                           0x00000020L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                         0x00000040L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                         0x00000080L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                         0x00000100L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                             0x00000200L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                          0x00000400L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                      0x00000800L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                 0x00003000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                      0x0000C000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                    0x00010000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                    0x00020000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                     0x000C0000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                       0x00100000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                       0x00200000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                           0x00C00000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                     0x03000000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                      0x04000000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                      0x80000000L
+//BIF_CFG_DEV1_RC1_DEVICE_CNTL2
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                 0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                               0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                             0x6
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                        0x7
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                              0x8
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                           0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN__SHIFT                                                          0xa
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                    0xb
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                    0xc
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                         0xd
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                     0xf
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                 0x000FL
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                   0x0010L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                 0x0020L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                               0x0040L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                          0x0080L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                0x0100L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                             0x0200L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN_MASK                                                            0x0400L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                      0x0800L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                      0x1000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN_MASK                                                           0x6000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                       0x8000L
+//BIF_CFG_DEV1_RC1_DEVICE_STATUS2
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED_MASK                                                        0xFFFFL
+//BIF_CFG_DEV1_RC1_LINK_CAP2
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                               0x1
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                0x8
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                           0x10
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                          0x17
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                          0x18
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                      0x1f
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                 0x000000FEL
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                  0x00000100L
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                             0x007F0000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                            0x00800000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                            0x01000000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__DRS_SUPPORTED_MASK                                                        0x80000000L
+//BIF_CFG_DEV1_RC1_LINK_CNTL2
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                  0x4
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                       0x5
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                             0x6
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                       0x7
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                              0xa
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                    0xb
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                             0xc
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                   0x000FL
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                    0x0010L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                         0x0020L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                               0x0040L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN_MASK                                                         0x0380L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                0x0400L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                      0x0800L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                               0xF000L
+//BIF_CFG_DEV1_RC1_LINK_STATUS2
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                       0x1
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                 0x2
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                 0x3
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                 0x4
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                   0x5
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                               0x6
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                               0x7
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                            0x8
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                   0xc
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                            0xf
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                              0x0001L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                         0x0002L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                   0x0004L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                   0x0008L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                   0x0010L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                     0x0020L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                 0x0040L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                 0x0080L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                              0x0300L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                     0x7000L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                              0x8000L
+//BIF_CFG_DEV1_RC1_SLOT_CAP2
+#define BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_SLOT_CNTL2
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED_MASK                                                            0xFFFFL
+//BIF_CFG_DEV1_RC1_SLOT_STATUS2
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED_MASK                                                          0xFFFFL
+//BIF_CFG_DEV1_RC1_MSI_CAP_LIST
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV1_RC1_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                   0x1
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                    0x4
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                       0x7
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                       0x8
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                            0x9
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN_MASK                                                            0x0001L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                     0x000EL
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                      0x0070L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                         0x0080L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                         0x0100L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                              0x0200L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                               0x0400L
+//BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                              0x2
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                0xFFFFFFFCL
+//BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_MSI_MSG_DATA
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA_MASK                                                          0xFFFFL
+//BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                  0xFFFFL
+//BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                    0xFFFFL
+//BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                            0xFFFFL
+//BIF_CFG_DEV1_RC1_SSID_CAP_LIST
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV1_RC1_SSID_CAP
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                        0x10
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID_MASK                                                          0xFFFF0000L
+//BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV1_RC1_MSI_MAP_CAP
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN__SHIFT                                                               0x0
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD__SHIFT                                                             0x1
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                         0xb
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN_MASK                                                                 0x0001L
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD_MASK                                                               0x0002L
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE_MASK                                                           0xF800L
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                            0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                         0x14
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                               0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                              0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                           0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                              0x4
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                0x8
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                              0xa
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                             0x00000007L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                0x00000070L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                  0x00000300L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                0x00000C00L
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                             0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                    0x18
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                               0x000000FFL
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                      0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                              0x1
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                            0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                0x000EL
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                        0x0001L
+//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x007F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x003F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                     0x0
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                     0x0
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                        0x4
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                     0x5
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                        0xc
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                         0xd
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                      0x10
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                       0x11
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                        0x12
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                       0x13
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                  0x15
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                 0x16
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                 0x17
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                        0x18
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                         0x19
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                    0x1a
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                          0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                       0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                          0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                           0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                    0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                        0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                         0x00020000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                          0x00040000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                         0x00080000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                   0x00100000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                    0x00200000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                   0x00400000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                   0x00800000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                          0x01000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                           0x02000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                      0x04000000L
+//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                            0x4
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                         0x5
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                            0xc
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                             0xd
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                          0x10
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                           0x11
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                            0x12
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                           0x13
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                     0x14
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                      0x15
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                     0x16
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                     0x17
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                            0x18
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                             0x19
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                        0x1a
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                              0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                           0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                              0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                               0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                        0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                            0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                             0x00020000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                              0x00040000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                             0x00080000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                       0x00100000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                        0x00200000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                       0x00400000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                       0x00800000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                              0x01000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                               0x02000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                          0x04000000L
+//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                    0x4
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                    0xc
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                     0xd
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                0xe
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                              0xf
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                  0x10
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                   0x11
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                    0x12
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                   0x13
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                             0x14
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                              0x15
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                             0x16
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                             0x17
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                    0x18
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                     0x19
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                0x1a
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                      0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                   0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                      0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                       0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                  0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                    0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                     0x00020000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                      0x00040000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                     0x00080000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                               0x00100000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                0x00200000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                               0x00400000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                               0x00800000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                      0x01000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                       0x02000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                  0x04000000L
+//BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                          0x6
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                         0x7
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                              0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                             0xc
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                            0xd
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                            0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                            0x00000040L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                           0x00000080L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                0x00000100L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                               0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                              0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                       0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                       0x00008000L
+//BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                              0x6
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                             0x7
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                  0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                0xd
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                         0xe
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                         0xf
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                0x00000040L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                               0x00000080L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                    0x00000100L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                   0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                  0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                           0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                           0x00008000L
+//BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                          0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                         0x7
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                     0x9
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                      0xa
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                 0xb
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                         0xc
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                            0x0000001FL
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                           0x00000080L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                            0x00000100L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                       0x00000200L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                        0x00000400L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                   0x00000800L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                           0x00001000L
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                           0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                              0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                          0x00000002L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                             0x00000004L
+//BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                      0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                 0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                            0x3
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                               0x4
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                    0x6
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                     0x1b
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                             0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                        0x00000002L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                   0x00000004L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                              0x00000008L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                 0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                   0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                      0x00000040L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                       0xF8000000L
+//BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                    0x10
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                      0xFFFF0000L
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                         0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                           0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                   0x00000002L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                  0x0000FFFFL
+//BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                               0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                            0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                            0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                         0x3
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                             0x4
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                              0x5
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                           0x6
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                              0x0002L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                              0x0004L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                           0x0008L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                               0x0010L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                0x0020L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                             0x0040L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                        0xFF00L
+//BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                        0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                     0x3
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                          0x0004L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                       0x0008L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                         0x0040L
+//BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                    0x0
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                    0x1f
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                      0x007FFFFFL
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                      0x80000000L
+//BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                0x0
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                          0x1f
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                  0x007FFFFFL
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                            0x80000000L
+//BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV1_RC1_LINK_CAP_16GT
+#define BIF_CFG_DEV1_RC1_LINK_CAP_16GT__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_RC1_LINK_CAP_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_LINK_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LINK_CNTL_16GT__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_RC1_LINK_CNTL_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_LINK_STATUS_16GT
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                  0x0
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                            0x1
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                            0x2
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                            0x3
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                              0x4
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                    0x00000001L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                              0x00000002L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                              0x00000004L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                              0x00000008L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                0x00000010L
+//BIF_CFG_DEV1_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT          0x0
+#define BIF_CFG_DEV1_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK            0x0000FFFFL
+//BIF_CFG_DEV1_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV1_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV1_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV1_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV1_RC1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                   0x0
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                     0x0001L
+//BIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                        0x0
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                               0x1
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                          0x0001L
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                 0x0002L
+//BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp
+//BIF_CFG_DEV2_RC1_VENDOR_ID
+#define BIF_CFG_DEV2_RC1_VENDOR_ID__VENDOR_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC1_VENDOR_ID__VENDOR_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV2_RC1_DEVICE_ID
+#define BIF_CFG_DEV2_RC1_DEVICE_ID__DEVICE_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_ID__DEVICE_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV2_RC1_COMMAND
+#define BIF_CFG_DEV2_RC1_COMMAND__IOEN_DN__SHIFT                                                              0x0
+#define BIF_CFG_DEV2_RC1_COMMAND__MEMEN_DN__SHIFT                                                             0x1
+#define BIF_CFG_DEV2_RC1_COMMAND__BUS_MASTER_EN__SHIFT                                                        0x2
+#define BIF_CFG_DEV2_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV2_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV2_RC1_COMMAND__PAL_SNOOP_EN__SHIFT                                                         0x5
+#define BIF_CFG_DEV2_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                0x6
+#define BIF_CFG_DEV2_RC1_COMMAND__AD_STEPPING__SHIFT                                                          0x7
+#define BIF_CFG_DEV2_RC1_COMMAND__SERR_EN__SHIFT                                                              0x8
+#define BIF_CFG_DEV2_RC1_COMMAND__FAST_B2B_EN__SHIFT                                                          0x9
+#define BIF_CFG_DEV2_RC1_COMMAND__INT_DIS__SHIFT                                                              0xa
+#define BIF_CFG_DEV2_RC1_COMMAND__IOEN_DN_MASK                                                                0x0001L
+#define BIF_CFG_DEV2_RC1_COMMAND__MEMEN_DN_MASK                                                               0x0002L
+#define BIF_CFG_DEV2_RC1_COMMAND__BUS_MASTER_EN_MASK                                                          0x0004L
+#define BIF_CFG_DEV2_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV2_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV2_RC1_COMMAND__PAL_SNOOP_EN_MASK                                                           0x0020L
+#define BIF_CFG_DEV2_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                  0x0040L
+#define BIF_CFG_DEV2_RC1_COMMAND__AD_STEPPING_MASK                                                            0x0080L
+#define BIF_CFG_DEV2_RC1_COMMAND__SERR_EN_MASK                                                                0x0100L
+#define BIF_CFG_DEV2_RC1_COMMAND__FAST_B2B_EN_MASK                                                            0x0200L
+#define BIF_CFG_DEV2_RC1_COMMAND__INT_DIS_MASK                                                                0x0400L
+//BIF_CFG_DEV2_RC1_STATUS
+#define BIF_CFG_DEV2_RC1_STATUS__IMMEDIATE_READINESS__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_RC1_STATUS__INT_STATUS__SHIFT                                                            0x3
+#define BIF_CFG_DEV2_RC1_STATUS__CAP_LIST__SHIFT                                                              0x4
+#define BIF_CFG_DEV2_RC1_STATUS__PCI_66_CAP__SHIFT                                                            0x5
+#define BIF_CFG_DEV2_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                     0x7
+#define BIF_CFG_DEV2_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                              0x8
+#define BIF_CFG_DEV2_RC1_STATUS__DEVSEL_TIMING__SHIFT                                                         0x9
+#define BIF_CFG_DEV2_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                   0xb
+#define BIF_CFG_DEV2_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                 0xc
+#define BIF_CFG_DEV2_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                 0xd
+#define BIF_CFG_DEV2_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                 0xe
+#define BIF_CFG_DEV2_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                 0xf
+#define BIF_CFG_DEV2_RC1_STATUS__IMMEDIATE_READINESS_MASK                                                     0x0001L
+#define BIF_CFG_DEV2_RC1_STATUS__INT_STATUS_MASK                                                              0x0008L
+#define BIF_CFG_DEV2_RC1_STATUS__CAP_LIST_MASK                                                                0x0010L
+#define BIF_CFG_DEV2_RC1_STATUS__PCI_66_CAP_MASK                                                              0x0020L
+#define BIF_CFG_DEV2_RC1_STATUS__FAST_BACK_CAPABLE_MASK                                                       0x0080L
+#define BIF_CFG_DEV2_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                0x0100L
+#define BIF_CFG_DEV2_RC1_STATUS__DEVSEL_TIMING_MASK                                                           0x0600L
+#define BIF_CFG_DEV2_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                     0x0800L
+#define BIF_CFG_DEV2_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                   0x1000L
+#define BIF_CFG_DEV2_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                   0x2000L
+#define BIF_CFG_DEV2_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                   0x4000L
+#define BIF_CFG_DEV2_RC1_STATUS__PARITY_ERROR_DETECTED_MASK                                                   0x8000L
+//BIF_CFG_DEV2_RC1_REVISION_ID
+#define BIF_CFG_DEV2_RC1_REVISION_ID__MINOR_REV_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                     0x4
+#define BIF_CFG_DEV2_RC1_REVISION_ID__MINOR_REV_ID_MASK                                                       0x0FL
+#define BIF_CFG_DEV2_RC1_REVISION_ID__MAJOR_REV_ID_MASK                                                       0xF0L
+//BIF_CFG_DEV2_RC1_PROG_INTERFACE
+#define BIF_CFG_DEV2_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                  0xFFL
+//BIF_CFG_DEV2_RC1_SUB_CLASS
+#define BIF_CFG_DEV2_RC1_SUB_CLASS__SUB_CLASS__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC1_SUB_CLASS__SUB_CLASS_MASK                                                            0xFFL
+//BIF_CFG_DEV2_RC1_BASE_CLASS
+#define BIF_CFG_DEV2_RC1_BASE_CLASS__BASE_CLASS__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC1_BASE_CLASS__BASE_CLASS_MASK                                                          0xFFL
+//BIF_CFG_DEV2_RC1_CACHE_LINE
+#define BIF_CFG_DEV2_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                     0xFFL
+//BIF_CFG_DEV2_RC1_LATENCY
+#define BIF_CFG_DEV2_RC1_LATENCY__LATENCY_TIMER__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC1_LATENCY__LATENCY_TIMER_MASK                                                          0xFFL
+//BIF_CFG_DEV2_RC1_HEADER
+#define BIF_CFG_DEV2_RC1_HEADER__HEADER_TYPE__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_RC1_HEADER__DEVICE_TYPE__SHIFT                                                           0x7
+#define BIF_CFG_DEV2_RC1_HEADER__HEADER_TYPE_MASK                                                             0x7FL
+#define BIF_CFG_DEV2_RC1_HEADER__DEVICE_TYPE_MASK                                                             0x80L
+//BIF_CFG_DEV2_RC1_BIST
+#define BIF_CFG_DEV2_RC1_BIST__BIST_COMP__SHIFT                                                               0x0
+#define BIF_CFG_DEV2_RC1_BIST__BIST_STRT__SHIFT                                                               0x6
+#define BIF_CFG_DEV2_RC1_BIST__BIST_CAP__SHIFT                                                                0x7
+#define BIF_CFG_DEV2_RC1_BIST__BIST_COMP_MASK                                                                 0x0FL
+#define BIF_CFG_DEV2_RC1_BIST__BIST_STRT_MASK                                                                 0x40L
+#define BIF_CFG_DEV2_RC1_BIST__BIST_CAP_MASK                                                                  0x80L
+//BIF_CFG_DEV2_RC1_BASE_ADDR_1
+#define BIF_CFG_DEV2_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC1_BASE_ADDR_1__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_BASE_ADDR_2
+#define BIF_CFG_DEV2_RC1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC1_BASE_ADDR_2__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                         0x8
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                           0x10
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                               0x18
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                           0x0000FF00L
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                             0x00FF0000L
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                 0xFF000000L
+//BIF_CFG_DEV2_RC1_IO_BASE_LIMIT
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                        0x4
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                  0x8
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                       0xc
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                     0x000FL
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_BASE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                    0x0F00L
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                         0xF000L
+//BIF_CFG_DEV2_RC1_SECONDARY_STATUS
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                  0x5
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                           0x7
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                    0x8
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                               0x9
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                         0xb
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                       0xc
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                       0xd
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                       0xe
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                       0xf
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__PCI_66_CAP_MASK                                                    0x0020L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                             0x0080L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                      0x0100L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                 0x0600L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                           0x0800L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                         0x1000L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                         0x2000L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                         0x4000L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                         0x8000L
+//BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                0x4
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                0x10
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                               0x14
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                   0x0000000FL
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                  0x0000FFF0L
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                          0x4
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                          0x10
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                         0x14
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                             0x0000000FL
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                            0x0000FFF0L
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                            0x000F0000L
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                           0xFFF00000L
+//BIF_CFG_DEV2_RC1_PREF_BASE_UPPER
+#define BIF_CFG_DEV2_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV2_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                            0x0
+#define BIF_CFG_DEV2_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                              0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                               0x0
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                              0x10
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                0xFFFF0000L
+//BIF_CFG_DEV2_RC1_CAP_PTR
+#define BIF_CFG_DEV2_RC1_CAP_PTR__CAP_PTR__SHIFT                                                              0x0
+#define BIF_CFG_DEV2_RC1_CAP_PTR__CAP_PTR_MASK                                                                0xFFL
+//BIF_CFG_DEV2_RC1_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_RC1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_RC1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_INTERRUPT_LINE
+#define BIF_CFG_DEV2_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                  0xFFL
+//BIF_CFG_DEV2_RC1_INTERRUPT_PIN
+#define BIF_CFG_DEV2_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                    0xFFL
+//BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                      0x1
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                       0x3
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                      0x4
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                            0x5
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                          0x6
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                  0x7
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                        0x8
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                      0x9
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                         0xa
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                    0xb
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                        0x0002L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                         0x0008L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                        0x0010L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                              0x0020L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                            0x0040L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                    0x0080L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                          0x0100L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                        0x0200L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                           0x0400L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                      0x0800L
+//BIF_CFG_DEV2_RC1_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV2_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                  0x01L
+//BIF_CFG_DEV2_RC1_PMI_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PMI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV2_RC1_PMI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV2_RC1_PMI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV2_RC1_PMI_CAP
+#define BIF_CFG_DEV2_RC1_PMI_CAP__VERSION__SHIFT                                                              0x0
+#define BIF_CFG_DEV2_RC1_PMI_CAP__PME_CLOCK__SHIFT                                                            0x3
+#define BIF_CFG_DEV2_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                  0x4
+#define BIF_CFG_DEV2_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_RC1_PMI_CAP__AUX_CURRENT__SHIFT                                                          0x6
+#define BIF_CFG_DEV2_RC1_PMI_CAP__D1_SUPPORT__SHIFT                                                           0x9
+#define BIF_CFG_DEV2_RC1_PMI_CAP__D2_SUPPORT__SHIFT                                                           0xa
+#define BIF_CFG_DEV2_RC1_PMI_CAP__PME_SUPPORT__SHIFT                                                          0xb
+#define BIF_CFG_DEV2_RC1_PMI_CAP__VERSION_MASK                                                                0x0007L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__PME_CLOCK_MASK                                                              0x0008L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                    0x0010L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                      0x0020L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__AUX_CURRENT_MASK                                                            0x01C0L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__D1_SUPPORT_MASK                                                             0x0200L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__D2_SUPPORT_MASK                                                             0x0400L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__PME_SUPPORT_MASK                                                            0xF800L
+//BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                0x3
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                       0x8
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                  0x9
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                   0xd
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                   0xf
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                0x16
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                   0x17
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                     0x18
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                    0x00000003L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                  0x00000008L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PME_EN_MASK                                                         0x00000100L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                    0x00001E00L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                     0x00006000L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                     0x00008000L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                  0x00400000L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                     0x00800000L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                       0xFF000000L
+//BIF_CFG_DEV2_RC1_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV2_RC1_PCIE_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV2_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV2_RC1_PCIE_CAP
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                         0x4
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                     0x9
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__VERSION_MASK                                                               0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__DEVICE_TYPE_MASK                                                           0x00F0L
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                      0x0100L
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                       0x3E00L
+//BIF_CFG_DEV2_RC1_DEVICE_CAP
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                               0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                      0x3
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                      0x5
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                            0x6
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                             0x9
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                          0xf
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                       0x1c
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                 0x00000007L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                        0x00000018L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__EXTENDED_TAG_MASK                                                        0x00000020L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                              0x000001C0L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                               0x00000E00L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                            0x00008000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__FLR_CAPABLE_MASK                                                         0x10000000L
+//BIF_CFG_DEV2_RC1_DEVICE_CNTL
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                 0x1
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                 0x5
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                  0x8
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                  0x9
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                  0xa
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                      0xb
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                            0xc
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                              0xf
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                   0x0002L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                     0x0010L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                   0x00E0L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                    0x0100L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                    0x0200L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                    0x0400L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                        0x0800L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                              0x7000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                0x8000L
+//BIF_CFG_DEV2_RC1_DEVICE_STATUS
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__CORR_ERR__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                  0x1
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                      0x2
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                   0x3
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__AUX_PWR__SHIFT                                                        0x4
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                              0x5
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                  0x6
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__CORR_ERR_MASK                                                         0x0001L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                    0x0002L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__FATAL_ERR_MASK                                                        0x0004L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__USR_DETECTED_MASK                                                     0x0008L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__AUX_PWR_MASK                                                          0x0010L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                0x0020L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                    0x0040L
+//BIF_CFG_DEV2_RC1_LINK_CAP
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_SPEED__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_WIDTH__SHIFT                                                          0x4
+#define BIF_CFG_DEV2_RC1_LINK_CAP__PM_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV2_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                    0xc
+#define BIF_CFG_DEV2_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                     0xf
+#define BIF_CFG_DEV2_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                              0x12
+#define BIF_CFG_DEV2_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                         0x13
+#define BIF_CFG_DEV2_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                         0x14
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                            0x15
+#define BIF_CFG_DEV2_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                         0x16
+#define BIF_CFG_DEV2_RC1_LINK_CAP__PORT_NUMBER__SHIFT                                                         0x18
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_SPEED_MASK                                                            0x0000000FL
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_WIDTH_MASK                                                            0x000003F0L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__PM_SUPPORT_MASK                                                            0x00000C00L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                      0x00007000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                       0x00038000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                0x00040000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                           0x00080000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                           0x00100000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                              0x00200000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                           0x00400000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__PORT_NUMBER_MASK                                                           0xFF000000L
+//BIF_CFG_DEV2_RC1_LINK_CNTL
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__PM_CONTROL__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_DIS__SHIFT                                                           0x4
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                       0x5
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                   0x6
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                      0x7
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                          0xb
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                              0xe
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__PM_CONTROL_MASK                                                           0x0003L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                    0x0008L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_DIS_MASK                                                             0x0010L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__RETRAIN_LINK_MASK                                                         0x0020L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                     0x0040L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__EXTENDED_SYNC_MASK                                                        0x0080L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                            0x0100L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                            0x0400L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                            0x0800L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                0xC000L
+//BIF_CFG_DEV2_RC1_LINK_STATUS
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                               0x0
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                            0x4
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_TRAINING__SHIFT                                                    0xb
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                   0xc
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__DL_ACTIVE__SHIFT                                                        0xd
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                        0xe
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                        0xf
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                 0x000FL
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                              0x03F0L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_TRAINING_MASK                                                      0x0800L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                     0x1000L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__DL_ACTIVE_MASK                                                          0x2000L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                          0x4000L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                          0x8000L
+//BIF_CFG_DEV2_RC1_SLOT_CAP
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                              0x1
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                  0x2
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                              0x3
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                               0x4
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                     0x6
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                0x7
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                0xf
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                       0x11
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                      0x12
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                   0x13
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                   0x00000001L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                0x00000002L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                    0x00000004L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                0x00000008L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                 0x00000010L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                      0x00000020L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                       0x00000040L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                  0x00007F80L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                  0x00018000L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                         0x00020000L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                        0x00040000L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                     0xFFF80000L
+//BIF_CFG_DEV2_RC1_SLOT_CNTL
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                             0x0
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                              0x2
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                         0x3
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                0x6
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                 0x8
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                0xa
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                         0xb
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                0xc
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                        0xd
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                               0x0001L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                0x0004L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                           0x0008L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                            0x0010L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                  0x00C0L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                   0x0300L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                  0x0400L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                           0x0800L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                  0x1000L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                          0x2000L
+//BIF_CFG_DEV2_RC1_SLOT_STATUS
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                               0x1
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                               0x2
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                          0x3
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                0x4
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                 0x5
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                            0x6
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                     0x7
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                 0x8
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                0x0001L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                 0x0002L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                 0x0004L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                            0x0008L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                  0x0010L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                   0x0020L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                              0x0040L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                       0x0080L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                   0x0100L
+//BIF_CFG_DEV2_RC1_ROOT_CNTL
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                               0x2
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                  0x0001L
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                 0x0004L
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                           0x0010L
+//BIF_CFG_DEV2_RC1_ROOT_CAP
+#define BIF_CFG_DEV2_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                             0x0
+#define BIF_CFG_DEV2_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                               0x0001L
+//BIF_CFG_DEV2_RC1_ROOT_STATUS
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_STATUS__SHIFT                                                       0x10
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_PENDING__SHIFT                                                      0x11
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_STATUS_MASK                                                         0x00010000L
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_PENDING_MASK                                                        0x00020000L
+//BIF_CFG_DEV2_RC1_DEVICE_CAP2
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                      0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                        0x4
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                         0x5
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                       0x6
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                       0x7
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                       0x8
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                           0x9
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                        0xa
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                    0xb
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                               0xc
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                    0xe
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                  0x10
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                  0x11
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                   0x12
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                     0x14
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                     0x15
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                         0x16
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                   0x18
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                    0x1a
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                    0x1f
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                        0x0000000FL
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                          0x00000010L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                           0x00000020L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                         0x00000040L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                         0x00000080L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                         0x00000100L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                             0x00000200L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                          0x00000400L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                      0x00000800L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                 0x00003000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                      0x0000C000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                    0x00010000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                    0x00020000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                     0x000C0000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                       0x00100000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                       0x00200000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                           0x00C00000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                     0x03000000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                      0x04000000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                      0x80000000L
+//BIF_CFG_DEV2_RC1_DEVICE_CNTL2
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                               0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                 0x4
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                               0x5
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                             0x6
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                        0x7
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                              0x8
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                           0x9
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__LTR_EN__SHIFT                                                          0xa
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                    0xb
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                    0xc
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                         0xd
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                     0xf
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                 0x000FL
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                   0x0010L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                 0x0020L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                               0x0040L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                          0x0080L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                0x0100L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                             0x0200L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__LTR_EN_MASK                                                            0x0400L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                      0x0800L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                      0x1000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__OBFF_EN_MASK                                                           0x6000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                       0x8000L
+//BIF_CFG_DEV2_RC1_DEVICE_STATUS2
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS2__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS2__RESERVED_MASK                                                        0xFFFFL
+//BIF_CFG_DEV2_RC1_LINK_CAP2
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                               0x1
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                0x8
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                           0x10
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                          0x17
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                          0x18
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                      0x1f
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                 0x000000FEL
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                  0x00000100L
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                             0x007F0000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                            0x00800000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                            0x01000000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__DRS_SUPPORTED_MASK                                                        0x80000000L
+//BIF_CFG_DEV2_RC1_LINK_CNTL2
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                  0x4
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                       0x5
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                             0x6
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                       0x7
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                              0xa
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                    0xb
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                             0xc
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                   0x000FL
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                    0x0010L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                         0x0020L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                               0x0040L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__XMIT_MARGIN_MASK                                                         0x0380L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                0x0400L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                      0x0800L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                               0xF000L
+//BIF_CFG_DEV2_RC1_LINK_STATUS2
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                            0x0
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                       0x1
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                 0x2
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                 0x3
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                 0x4
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                   0x5
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                               0x6
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                               0x7
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                            0x8
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                   0xc
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                            0xf
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                              0x0001L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                         0x0002L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                   0x0004L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                   0x0008L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                   0x0010L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                     0x0020L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                 0x0040L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                 0x0080L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                              0x0300L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                     0x7000L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                              0x8000L
+//BIF_CFG_DEV2_RC1_SLOT_CAP2
+#define BIF_CFG_DEV2_RC1_SLOT_CAP2__RESERVED__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_RC1_SLOT_CAP2__RESERVED_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_SLOT_CNTL2
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL2__RESERVED__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL2__RESERVED_MASK                                                            0xFFFFL
+//BIF_CFG_DEV2_RC1_SLOT_STATUS2
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS2__RESERVED__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS2__RESERVED_MASK                                                          0xFFFFL
+//BIF_CFG_DEV2_RC1_MSI_CAP_LIST
+#define BIF_CFG_DEV2_RC1_MSI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV2_RC1_MSI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV2_RC1_MSI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV2_RC1_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                   0x1
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                    0x4
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                       0x7
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                       0x8
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                            0x9
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EN_MASK                                                            0x0001L
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                     0x000EL
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                      0x0070L
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                         0x0080L
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                         0x0100L
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                              0x0200L
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                               0x0400L
+//BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                              0x2
+#define BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                0xFFFFFFFCL
+//BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_MSI_MSG_DATA
+#define BIF_CFG_DEV2_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC1_MSI_MSG_DATA__MSI_DATA_MASK                                                          0xFFFFL
+//BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                  0xFFFFL
+//BIF_CFG_DEV2_RC1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                    0xFFFFL
+//BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                          0x0
+#define BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                            0xFFFFL
+//BIF_CFG_DEV2_RC1_SSID_CAP_LIST
+#define BIF_CFG_DEV2_RC1_SSID_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV2_RC1_SSID_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV2_RC1_SSID_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV2_RC1_SSID_CAP
+#define BIF_CFG_DEV2_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                        0x10
+#define BIF_CFG_DEV2_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_SSID_CAP__SUBSYSTEM_ID_MASK                                                          0xFFFF0000L
+//BIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_RC1_MSI_MAP_CAP
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__EN__SHIFT                                                               0x0
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__FIXD__SHIFT                                                             0x1
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT                                                         0xb
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__EN_MASK                                                                 0x0001L
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__FIXD_MASK                                                               0x0002L
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__CAP_TYPE_MASK                                                           0xF800L
+//BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                             0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                            0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                         0x14
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                               0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                              0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                           0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                              0x4
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                0x8
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                              0xa
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                             0x00000007L
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                0x00000070L
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                  0x00000300L
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                0x00000C00L
+//BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                             0x0
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                    0x18
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                               0x000000FFL
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                      0xFF000000L
+//BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                          0x0
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                              0x1
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                            0x0001L
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                0x000EL
+//BIF_CFG_DEV2_RC1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                        0x0001L
+//BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x007F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x003F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                     0x0
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                     0x0
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                        0x4
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                     0x5
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                        0xc
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                         0xd
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                      0x10
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                       0x11
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                        0x12
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                       0x13
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                  0x15
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                 0x16
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                 0x17
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                        0x18
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                         0x19
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                    0x1a
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                          0x00000010L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                       0x00000020L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                          0x00001000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                           0x00002000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                    0x00008000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                        0x00010000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                         0x00020000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                          0x00040000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                         0x00080000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                   0x00100000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                    0x00200000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                   0x00400000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                   0x00800000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                          0x01000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                           0x02000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                      0x04000000L
+//BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                            0x4
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                         0x5
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                            0xc
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                             0xd
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                          0x10
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                           0x11
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                            0x12
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                           0x13
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                     0x14
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                      0x15
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                     0x16
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                     0x17
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                            0x18
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                             0x19
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                        0x1a
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                              0x00000010L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                           0x00000020L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                              0x00001000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                               0x00002000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                        0x00008000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                            0x00010000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                             0x00020000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                              0x00040000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                             0x00080000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                       0x00100000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                        0x00200000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                       0x00400000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                       0x00800000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                              0x01000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                               0x02000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                          0x04000000L
+//BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                    0x4
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                 0x5
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                    0xc
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                     0xd
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                0xe
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                              0xf
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                  0x10
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                   0x11
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                    0x12
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                   0x13
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                             0x14
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                              0x15
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                             0x16
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                             0x17
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                    0x18
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                     0x19
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                0x1a
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                      0x00000010L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                   0x00000020L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                      0x00001000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                       0x00002000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                  0x00004000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                0x00008000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                    0x00010000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                     0x00020000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                      0x00040000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                     0x00080000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                               0x00100000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                0x00200000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                               0x00400000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                               0x00800000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                      0x01000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                       0x02000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                  0x04000000L
+//BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                          0x0
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                          0x6
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                         0x7
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                              0x8
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                             0xc
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                            0xd
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                            0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                            0x00000040L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                           0x00000080L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                0x00000100L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                               0x00001000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                              0x00002000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                       0x00004000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                       0x00008000L
+//BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                              0x6
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                             0x7
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                  0x8
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                0xd
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                         0xe
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                         0xf
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                0x00000040L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                               0x00000080L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                    0x00000100L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                   0x00001000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                  0x00002000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                           0x00004000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                           0x00008000L
+//BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                          0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                         0x7
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                     0x9
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                      0xa
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                 0xb
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                         0xc
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                            0x0000001FL
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                           0x00000080L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                            0x00000100L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                       0x00000200L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                        0x00000400L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                   0x00000800L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                           0x00001000L
+//BIF_CFG_DEV2_RC1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                           0x2
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                              0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                          0x00000002L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                             0x00000004L
+//BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                      0x1
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                 0x2
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                            0x3
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                               0x4
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                 0x5
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                    0x6
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                     0x1b
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                             0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                        0x00000002L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                   0x00000004L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                              0x00000008L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                 0x00000010L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                   0x00000020L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                      0x00000040L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                       0xF8000000L
+//BIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                    0x10
+#define BIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                      0xFFFF0000L
+//BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                         0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                 0x1
+#define BIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                           0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                   0x00000002L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                  0x0000FFFFL
+//BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                               0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                            0x1
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                            0x2
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                         0x3
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                             0x4
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                              0x5
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                           0x6
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                 0x0001L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                              0x0002L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                              0x0004L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                           0x0008L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                               0x0010L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                0x0020L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                             0x0040L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                        0xFF00L
+//BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                        0x2
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                     0x3
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                          0x0004L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                       0x0008L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                         0x0040L
+//BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                    0x0
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                    0x1f
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                      0x007FFFFFL
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                      0x80000000L
+//BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                0x0
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                          0x1f
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                  0x007FFFFFL
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                            0x80000000L
+//BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV2_RC1_LINK_CAP_16GT
+#define BIF_CFG_DEV2_RC1_LINK_CAP_16GT__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_RC1_LINK_CAP_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_LINK_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LINK_CNTL_16GT__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_RC1_LINK_CNTL_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_LINK_STATUS_16GT
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                  0x0
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                            0x1
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                            0x2
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                            0x3
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                              0x4
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                    0x00000001L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                              0x00000002L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                              0x00000004L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                              0x00000008L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                0x00000010L
+//BIF_CFG_DEV2_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT          0x0
+#define BIF_CFG_DEV2_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK            0x0000FFFFL
+//BIF_CFG_DEV2_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV2_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV2_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV2_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV2_RC1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                   0x0
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                     0x0001L
+//BIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                        0x0
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                               0x1
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                          0x0001L
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                 0x0002L
+//BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF0_1_STATUS
+#define BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF0_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_1_HEADER
+#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF0_1_BIST
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF0_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF0_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF0_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF0_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF0_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF0_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                    0x0040L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU_MASK                                                           0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                               0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                        0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                          0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                          0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                0x0100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                            0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                    0x003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                 0x3F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                   0x003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                  0x0000003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                            0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                              0xFFE00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                  0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                           0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                    0x0020L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                 0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT   0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK     0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
+//BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
+#define BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
+//BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
+//BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                          0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                         0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                            0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                           0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                     0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                    0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                       0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                         0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT     0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT      0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT     0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT     0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT    0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT     0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK        0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK       0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK        0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK       0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK       0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK      0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK        0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK       0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK    0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK    0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK    0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK   0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK    0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK   0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                   0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT               0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                      0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                  0x00000F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                  0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                   0x01000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT               0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT               0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT               0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT               0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT               0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT               0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT               0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT               0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT               0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT               0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT              0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT              0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT              0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT              0x1b
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                0x1c
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT              0x1d
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                0x1e
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT              0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                   0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                   0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                   0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                   0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                   0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                   0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                   0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                   0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                   0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                  0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                  0x04000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                0x08000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                  0x10000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                0x20000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                  0x40000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT              0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT                0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT              0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT                0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT              0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT                0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT              0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT              0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT                0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT              0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT                0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT              0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT                0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT              0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT              0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT                0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT              0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT                0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT              0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT                0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT              0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT                0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT              0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT                0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT              0x1b
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT                0x1c
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT              0x1d
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                  0x1e
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK                0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK                  0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK                0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK                  0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK                0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK                  0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK                0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK                  0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK                0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK                  0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK                0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK                  0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK                0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK                  0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK                0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK                  0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK                0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK                  0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK                0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK                0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK                0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK                  0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK                0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK                  0x04000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK                0x08000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK                  0x10000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK                0x20000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                    0x40000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                  0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT                               0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT                    0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK                        0x0000007FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK                                 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK                      0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                  0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT                     0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT                    0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK                      0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK                       0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT                         0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK                           0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK                           0x00000070L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK  0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_COMMAND
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF1_1_STATUS
+#define BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF1_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF1_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF1_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF1_1_LATENCY
+#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF1_1_HEADER
+#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF1_1_BIST
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF1_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF1_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF1_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                    0x0040L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU_MASK                                                           0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                               0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                        0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                          0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                          0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                0x0100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                            0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                    0x003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                 0x3F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                   0x003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                  0x0000003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                            0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                              0xFFE00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                  0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                           0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                    0x0020L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT   0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK     0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
+//BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
+//BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
+#define BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
+//BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
+//BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                          0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                         0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                            0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                           0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                     0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                    0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                       0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                          0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                         0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT     0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT      0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT     0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT     0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT    0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT     0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK        0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK       0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK        0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK       0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK       0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK      0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK        0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK       0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK    0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK    0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK    0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK   0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK    0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK   0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                   0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT               0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                      0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                  0x00000F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                  0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                   0x01000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT               0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT               0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT               0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT               0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT               0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT               0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT               0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT               0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT               0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT               0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT              0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT              0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT              0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT              0x1b
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                0x1c
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT              0x1d
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                0x1e
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT              0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                   0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                   0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                   0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                   0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                   0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                   0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                   0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                   0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                   0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                   0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                  0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                  0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                  0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                  0x04000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                0x08000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                  0x10000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                0x20000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                  0x40000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT              0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT                0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT              0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT                0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT              0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT                0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT              0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT              0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT                0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT              0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT                0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT              0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT                0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT              0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT              0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT                0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT              0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT                0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT              0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT                0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT              0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT                0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT              0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT                0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT              0x1b
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT                0x1c
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT              0x1d
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                  0x1e
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK                  0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK                0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK                  0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK                0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK                  0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK                0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK                  0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK                0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK                  0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK                0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK                  0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK                0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK                  0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK                0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK                  0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK                0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK                  0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK                0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK                  0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK                0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK                  0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK                0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK                  0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK                0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK                  0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK                0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK                  0x04000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK                0x08000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK                  0x10000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK                0x20000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                    0x40000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                  0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT                               0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT                    0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK                        0x0000007FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK                                 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK                      0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                  0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT                     0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT                    0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK                      0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK                       0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK                      0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT                         0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK                           0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK                           0x00000070L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK  0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK                              0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_COMMAND
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF2_1_STATUS
+#define BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF2_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF2_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF2_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF2_1_LATENCY
+#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF2_1_HEADER
+#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF2_1_BIST
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF2_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF2_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_SBRN
+#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF2_1_FLADJ
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF2_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF2_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF2_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF2_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF2_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_COMMAND
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF3_1_STATUS
+#define BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF3_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF3_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF3_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF3_1_LATENCY
+#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF3_1_HEADER
+#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF3_1_BIST
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF3_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF3_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_SBRN
+#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF3_1_FLADJ
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF3_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF3_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF3_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF3_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF3_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF4_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_COMMAND
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF4_1_STATUS
+#define BIF_CFG_DEV0_EPF4_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF4_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF4_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF4_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF4_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF4_1_LATENCY
+#define BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF4_1_HEADER
+#define BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF4_1_BIST
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF4_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF4_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF4_1_SBRN
+#define BIF_CFG_DEV0_EPF4_1_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF4_1_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF4_1_FLADJ
+#define BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF4_1_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF4_1_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF4_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF4_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF4_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF4_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF4_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF4_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF5_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_COMMAND
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF5_1_STATUS
+#define BIF_CFG_DEV0_EPF5_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF5_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF5_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF5_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF5_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF5_1_LATENCY
+#define BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF5_1_HEADER
+#define BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF5_1_BIST
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF5_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF5_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF5_1_SBRN
+#define BIF_CFG_DEV0_EPF5_1_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF5_1_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF5_1_FLADJ
+#define BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF5_1_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF5_1_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF5_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF5_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF5_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF5_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF5_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF5_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF6_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_COMMAND
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF6_1_STATUS
+#define BIF_CFG_DEV0_EPF6_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF6_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF6_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF6_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF6_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF6_1_LATENCY
+#define BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF6_1_HEADER
+#define BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF6_1_BIST
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF6_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF6_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF6_1_SBRN
+#define BIF_CFG_DEV0_EPF6_1_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF6_1_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF6_1_FLADJ
+#define BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF6_1_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF6_1_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF6_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF6_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF6_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF6_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF6_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF6_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF7_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_COMMAND
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF7_1_STATUS
+#define BIF_CFG_DEV0_EPF7_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF7_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF7_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF7_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF7_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF7_1_LATENCY
+#define BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF7_1_HEADER
+#define BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF7_1_BIST
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF7_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF7_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF7_1_SBRN
+#define BIF_CFG_DEV0_EPF7_1_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_EPF7_1_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV0_EPF7_1_FLADJ
+#define BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_EPF7_1_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV0_EPF7_1_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF7_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF7_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF7_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF7_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF7_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF7_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp
+//BIF_CFG_DEV1_EPF0_1_VENDOR_ID
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_DEVICE_ID
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_COMMAND
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV1_EPF0_1_STATUS
+#define BIF_CFG_DEV1_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV1_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV1_EPF0_1_REVISION_ID
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV1_EPF0_1_SUB_CLASS
+#define BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_CLASS
+#define BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV1_EPF0_1_CACHE_LINE
+#define BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV1_EPF0_1_LATENCY
+#define BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV1_EPF0_1_HEADER
+#define BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV1_EPF0_1_BIST
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV1_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_CAP_PTR
+#define BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV1_EPF0_1_MIN_GRANT
+#define BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV1_EPF0_1_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PMI_CAP
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_SBRN
+#define BIF_CFG_DEV1_EPF0_1_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV1_EPF0_1_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV1_EPF0_1_FLADJ
+#define BIF_CFG_DEV1_EPF0_1_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV1_EPF0_1_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV1_EPF0_1_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV1_EPF0_1_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV1_EPF0_1_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF0_1_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_EPF0_1_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV1_EPF0_1_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV1_EPF0_1_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV1_EPF0_1_LINK_CAP
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_LINK_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV1_EPF0_1_LINK_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_LINK_CAP2
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV1_EPF0_1_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV1_EPF0_1_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MASK
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_PENDING
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV1_EPF0_1_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_1_MSIX_PBA
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
+//BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_LINK_CAP_16GT
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_LINK_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
+//BIF_CFG_DEV1_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
+#define BIF_CFG_DEV1_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV1_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV1_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
+//BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
+//BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp
+//BIF_CFG_DEV1_EPF1_1_VENDOR_ID
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_DEVICE_ID
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_COMMAND
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV1_EPF1_1_STATUS
+#define BIF_CFG_DEV1_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV1_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV1_EPF1_1_REVISION_ID
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV1_EPF1_1_SUB_CLASS
+#define BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_CLASS
+#define BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV1_EPF1_1_CACHE_LINE
+#define BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV1_EPF1_1_LATENCY
+#define BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV1_EPF1_1_HEADER
+#define BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV1_EPF1_1_BIST
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV1_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_CAP_PTR
+#define BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV1_EPF1_1_MIN_GRANT
+#define BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV1_EPF1_1_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PMI_CAP
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV1_EPF1_1_SBRN
+#define BIF_CFG_DEV1_EPF1_1_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV1_EPF1_1_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV1_EPF1_1_FLADJ
+#define BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV1_EPF1_1_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV1_EPF1_1_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV1_EPF1_1_LINK_CAP
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV1_EPF1_1_LINK_CNTL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV1_EPF1_1_LINK_STATUS
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_LINK_CAP2
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV1_EPF1_1_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV1_EPF1_1_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MASK
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_PENDING
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV1_EPF1_1_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_1_MSIX_PBA
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp
+//BIF_CFG_DEV2_EPF0_1_VENDOR_ID
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_DEVICE_ID
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_COMMAND
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV2_EPF0_1_STATUS
+#define BIF_CFG_DEV2_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF0_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF0_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV2_EPF0_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV2_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV2_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV2_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV2_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV2_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV2_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV2_EPF0_1_REVISION_ID
+#define BIF_CFG_DEV2_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV2_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV2_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV2_EPF0_1_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF0_1_SUB_CLASS
+#define BIF_CFG_DEV2_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_CLASS
+#define BIF_CFG_DEV2_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF0_1_CACHE_LINE
+#define BIF_CFG_DEV2_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV2_EPF0_1_LATENCY
+#define BIF_CFG_DEV2_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF0_1_HEADER
+#define BIF_CFG_DEV2_EPF0_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF0_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV2_EPF0_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV2_EPF0_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV2_EPF0_1_BIST
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_CAP_PTR
+#define BIF_CFG_DEV2_EPF0_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF0_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV2_EPF0_1_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF0_1_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV2_EPF0_1_MIN_GRANT
+#define BIF_CFG_DEV2_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF0_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV2_EPF0_1_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PMI_CAP
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_SBRN
+#define BIF_CFG_DEV2_EPF0_1_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV2_EPF0_1_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV2_EPF0_1_FLADJ
+#define BIF_CFG_DEV2_EPF0_1_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV2_EPF0_1_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV2_EPF0_1_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV2_EPF0_1_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV2_EPF0_1_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF0_1_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF0_1_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF0_1_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV2_EPF0_1_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV2_EPF0_1_LINK_CAP
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_LINK_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV2_EPF0_1_LINK_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_LINK_CAP2
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV2_EPF0_1_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV2_EPF0_1_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_MASK
+#define BIF_CFG_DEV2_EPF0_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_PENDING
+#define BIF_CFG_DEV2_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV2_EPF0_1_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV2_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF0_1_MSIX_PBA
+#define BIF_CFG_DEV2_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
+//BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
+//BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_LINK_CAP_16GT
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_LINK_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
+//BIF_CFG_DEV2_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
+#define BIF_CFG_DEV2_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV2_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV2_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
+//BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
+//BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf1_bifcfgdecp
+//BIF_CFG_DEV2_EPF1_1_VENDOR_ID
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_DEVICE_ID
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_COMMAND
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV2_EPF1_1_STATUS
+#define BIF_CFG_DEV2_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF1_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF1_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV2_EPF1_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV2_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV2_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV2_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV2_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV2_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV2_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV2_EPF1_1_REVISION_ID
+#define BIF_CFG_DEV2_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV2_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV2_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV2_EPF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF1_1_SUB_CLASS
+#define BIF_CFG_DEV2_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_CLASS
+#define BIF_CFG_DEV2_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF1_1_CACHE_LINE
+#define BIF_CFG_DEV2_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV2_EPF1_1_LATENCY
+#define BIF_CFG_DEV2_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF1_1_HEADER
+#define BIF_CFG_DEV2_EPF1_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF1_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV2_EPF1_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV2_EPF1_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV2_EPF1_1_BIST
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_CAP_PTR
+#define BIF_CFG_DEV2_EPF1_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF1_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV2_EPF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV2_EPF1_1_MIN_GRANT
+#define BIF_CFG_DEV2_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF1_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV2_EPF1_1_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PMI_CAP
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV2_EPF1_1_SBRN
+#define BIF_CFG_DEV2_EPF1_1_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV2_EPF1_1_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV2_EPF1_1_FLADJ
+#define BIF_CFG_DEV2_EPF1_1_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV2_EPF1_1_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV2_EPF1_1_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV2_EPF1_1_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV2_EPF1_1_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF1_1_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF1_1_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF1_1_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV2_EPF1_1_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV2_EPF1_1_LINK_CAP
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV2_EPF1_1_LINK_CNTL
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV2_EPF1_1_LINK_STATUS
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_LINK_CAP2
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV2_EPF1_1_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV2_EPF1_1_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_MASK
+#define BIF_CFG_DEV2_EPF1_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_PENDING
+#define BIF_CFG_DEV2_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV2_EPF1_1_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV2_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF1_1_MSIX_PBA
+#define BIF_CFG_DEV2_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf2_bifcfgdecp
+//BIF_CFG_DEV2_EPF2_1_VENDOR_ID
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_DEVICE_ID
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_COMMAND
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV2_EPF2_1_STATUS
+#define BIF_CFG_DEV2_EPF2_1_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF2_1_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF2_1_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV2_EPF2_1_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV2_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV2_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV2_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV2_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV2_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV2_EPF2_1_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV2_EPF2_1_REVISION_ID
+#define BIF_CFG_DEV2_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV2_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV2_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV2_EPF2_1_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF2_1_SUB_CLASS
+#define BIF_CFG_DEV2_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_CLASS
+#define BIF_CFG_DEV2_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF2_1_CACHE_LINE
+#define BIF_CFG_DEV2_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV2_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV2_EPF2_1_LATENCY
+#define BIF_CFG_DEV2_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV2_EPF2_1_HEADER
+#define BIF_CFG_DEV2_EPF2_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF2_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV2_EPF2_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV2_EPF2_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV2_EPF2_1_BIST
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_CAP_PTR
+#define BIF_CFG_DEV2_EPF2_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF2_1_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV2_EPF2_1_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV2_EPF2_1_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV2_EPF2_1_MIN_GRANT
+#define BIF_CFG_DEV2_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF2_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV2_EPF2_1_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PMI_CAP
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV2_EPF2_1_SBRN
+#define BIF_CFG_DEV2_EPF2_1_SBRN__SBRN__SHIFT                                                                 0x0
+#define BIF_CFG_DEV2_EPF2_1_SBRN__SBRN_MASK                                                                   0xFFL
+//BIF_CFG_DEV2_EPF2_1_FLADJ
+#define BIF_CFG_DEV2_EPF2_1_FLADJ__FLADJ__SHIFT                                                               0x0
+#define BIF_CFG_DEV2_EPF2_1_FLADJ__NFC__SHIFT                                                                 0x6
+#define BIF_CFG_DEV2_EPF2_1_FLADJ__FLADJ_MASK                                                                 0x3FL
+#define BIF_CFG_DEV2_EPF2_1_FLADJ__NFC_MASK                                                                   0x40L
+//BIF_CFG_DEV2_EPF2_1_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF2_1_DBESL_DBESLD__DBESL__SHIFT                                                        0x0
+#define BIF_CFG_DEV2_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF2_1_DBESL_DBESLD__DBESL_MASK                                                          0x0FL
+#define BIF_CFG_DEV2_EPF2_1_DBESL_DBESLD__DBESLD_MASK                                                         0xF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV2_EPF2_1_LINK_CAP
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV2_EPF2_1_LINK_CNTL
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV2_EPF2_1_LINK_STATUS
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_LINK_CAP2
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV2_EPF2_1_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV2_EPF2_1_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_MASK
+#define BIF_CFG_DEV2_EPF2_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_PENDING
+#define BIF_CFG_DEV2_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV2_EPF2_1_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV2_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF2_1_MSIX_PBA
+#define BIF_CFG_DEV2_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV2_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT                                    0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT                                    0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK                                      0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK                                      0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT                                   0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT                                   0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK                                     0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK                                     0xFF00L
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h
index 8ba21747b40a..c1d7b1d0b952 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -5636,7 +5636,9 @@ typedef struct  _ATOM_SMU_INFO_V2_1
 {
   ATOM_COMMON_TABLE_HEADER         asHeader;
   UCHAR ucSclkEntryNum;            // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1
-  UCHAR ucReserved[3];
+  UCHAR ucSMUVer;
+  UCHAR ucSharePowerSource;
+  UCHAR ucReserved;
   ATOM_SCLK_FCW_RANGE_ENTRY_V1     asSclkFcwRangeEntry[8];
 }ATOM_SMU_INFO_V2_1;
 
@@ -5655,6 +5657,22 @@ typedef struct  _ATOM_GFX_INFO_V2_1
   UCHAR max_texture_channel_caches;
 }ATOM_GFX_INFO_V2_1;
 
+typedef struct  _ATOM_GFX_INFO_V2_3
+{
+  ATOM_COMMON_TABLE_HEADER asHeader;
+  UCHAR GfxIpMinVer;
+  UCHAR GfxIpMajVer;
+  UCHAR max_shader_engines;
+  UCHAR max_tile_pipes;
+  UCHAR max_cu_per_sh;
+  UCHAR max_sh_per_se;
+  UCHAR max_backends_per_se;
+  UCHAR max_texture_channel_caches;
+  USHORT usHiLoLeakageThreshold;
+  USHORT usEdcDidtLoDpm7TableOffset; //offset of DPM7 low leakage table _ATOM_EDC_DIDT_TABLE_V1
+  USHORT usEdcDidtHiDpm7TableOffset; //offset of DPM7 high leakage table _ATOM_EDC_DIDT_TABLE_V1
+  USHORT usReserverd[3];
+}ATOM_GFX_INFO_V2_3;
 
 typedef struct _ATOM_POWER_SOURCE_OBJECT
 {
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 3e526c394f6c..6139d10f4289 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1304,11 +1304,67 @@ struct atom_integrated_system_info_v1_12
   struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
   struct atom_DCN_dpphy_dp_tuningset hbr_tuningset;    //hbr 2.7G dp tuning set
   struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset;   //hbr2 5.4G dp turnig set
-  struct atom_DCN_dpphy_dp_tuningset edp_tunings;       //edp tuning set  
+  struct atom_DCN_dpphy_dp_tuningset edp_tunings;       //edp tuning set
   struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK6_tuningset;
   uint32_t  reserved[63];
 };
 
+struct edp_info_table
+{
+        uint16_t edp_backlight_pwm_hz;
+        uint16_t edp_ss_percentage;
+        uint16_t edp_ss_rate_10hz;
+        uint16_t reserved1;
+        uint32_t reserved2;
+        uint8_t  edp_pwr_on_off_delay;
+        uint8_t  edp_pwr_on_vary_bl_to_blon;
+        uint8_t  edp_pwr_down_bloff_to_vary_bloff;
+        uint8_t  edp_panel_bpc;
+        uint8_t  edp_bootup_bl_level;
+        uint8_t  reserved3[3];
+        uint32_t reserved4[3];
+};
+
+struct atom_integrated_system_info_v2_1
+{
+        struct  atom_common_table_header  table_header;
+        uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
+        uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
+        uint32_t  system_config;
+        uint32_t  cpucapinfo;
+        uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
+        uint16_t  gpuclk_ss_type;
+        uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
+        uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
+        uint8_t   umachannelnumber;                 // number of memory channels
+        uint8_t   htc_hyst_limit;
+        uint8_t   htc_tmp_limit;
+        uint8_t   reserved1;
+        uint8_t   reserved2;
+        struct edp_info_table edp1_info;
+        struct edp_info_table edp2_info;
+        uint32_t  reserved3[8];
+        struct atom_external_display_connection_info extdispconninfo;
+        struct atom_DCN_dpphy_dvihdmi_tuningset  TMDS_tuningset;
+        struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK5_tuningset; //add clk6
+        struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK6_tuningset;
+        struct atom_DCN_dpphy_dvihdmi_tuningset  hdmiCLK8_tuningset;
+        uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset)
+        struct atom_DCN_dpphy_dp_tuningset rbr_tuningset;        // rbr 1.62G dp tuning set
+        struct atom_DCN_dpphy_dp_tuningset hbr_tuningset;    //hbr 2.7G dp tuning set
+        struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset;   //hbr2 5.4G dp turnig set
+        struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset;   // HBR3 dp tuning set
+        struct atom_DCN_dpphy_dp_tuningset edp_tunings;       //edp tuning set
+        uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset)
+        struct atom_hdmi_retimer_redriver_set dp0_retimer_set;   //for DP0
+        struct atom_hdmi_retimer_redriver_set dp1_retimer_set;   //for DP1
+        struct atom_hdmi_retimer_redriver_set dp2_retimer_set;   //for DP2
+        struct atom_hdmi_retimer_redriver_set dp3_retimer_set;   //for DP3
+        uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info
+        uint32_t reserved7[32];
+
+};
+
 // system_config
 enum atom_system_vbiosmisc_def{
   INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
@@ -1367,6 +1423,11 @@ enum atom_dmi_t17_mem_type_def{
   LpDdr2MemType,                                        ///< Assign 28 to LPDDR2
   LpDdr3MemType,                                        ///< Assign 29 to LPDDR3
   LpDdr4MemType,                                        ///< Assign 30 to LPDDR4
+  GDdr6MemType,                                         ///< Assign 31 to GDDR6
+  HbmMemType,                                           ///< Assign 32 to HBM
+  Hbm2MemType,                                          ///< Assign 33 to HBM2
+  Ddr5MemType,                                          ///< Assign 34 to DDR5
+  LpDdr5MemType,                                        ///< Assign 35 to LPDDR5
 };
 
 
diff --git a/drivers/gpu/drm/amd/include/dimgrey_cavefish_ip_offset.h b/drivers/gpu/drm/amd/include/dimgrey_cavefish_ip_offset.h
new file mode 100644
index 000000000000..b41263de8a9b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/dimgrey_cavefish_ip_offset.h
@@ -0,0 +1,1049 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dimgrey_cavefish_ip_offset_HEADER
+#define _dimgrey_cavefish_ip_offset_HEADER
+
+#define MAX_INSTANCE                                        7
+#define MAX_SEGMENT                                         6
+
+
+struct IP_BASE_INSTANCE
+{
+    unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
+                                        { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
+                                        { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
+                                        { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
+                                        { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
+                                        { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
+                                        { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } },
+                                        { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016200, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
+                                        { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
+                                        { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
+                                        { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCN0_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+
+
+#define ATHUB_BASE__INST0_SEG0                     0x00000C00
+#define ATHUB_BASE__INST0_SEG1                     0x02408C00
+#define ATHUB_BASE__INST0_SEG2                     0
+#define ATHUB_BASE__INST0_SEG3                     0
+#define ATHUB_BASE__INST0_SEG4                     0
+#define ATHUB_BASE__INST0_SEG5                     0
+
+#define ATHUB_BASE__INST1_SEG0                     0
+#define ATHUB_BASE__INST1_SEG1                     0
+#define ATHUB_BASE__INST1_SEG2                     0
+#define ATHUB_BASE__INST1_SEG3                     0
+#define ATHUB_BASE__INST1_SEG4                     0
+#define ATHUB_BASE__INST1_SEG5                     0
+
+#define ATHUB_BASE__INST2_SEG0                     0
+#define ATHUB_BASE__INST2_SEG1                     0
+#define ATHUB_BASE__INST2_SEG2                     0
+#define ATHUB_BASE__INST2_SEG3                     0
+#define ATHUB_BASE__INST2_SEG4                     0
+#define ATHUB_BASE__INST2_SEG5                     0
+
+#define ATHUB_BASE__INST3_SEG0                     0
+#define ATHUB_BASE__INST3_SEG1                     0
+#define ATHUB_BASE__INST3_SEG2                     0
+#define ATHUB_BASE__INST3_SEG3                     0
+#define ATHUB_BASE__INST3_SEG4                     0
+#define ATHUB_BASE__INST3_SEG5                     0
+
+#define ATHUB_BASE__INST4_SEG0                     0
+#define ATHUB_BASE__INST4_SEG1                     0
+#define ATHUB_BASE__INST4_SEG2                     0
+#define ATHUB_BASE__INST4_SEG3                     0
+#define ATHUB_BASE__INST4_SEG4                     0
+#define ATHUB_BASE__INST4_SEG5                     0
+
+#define ATHUB_BASE__INST5_SEG0                     0
+#define ATHUB_BASE__INST5_SEG1                     0
+#define ATHUB_BASE__INST5_SEG2                     0
+#define ATHUB_BASE__INST5_SEG3                     0
+#define ATHUB_BASE__INST5_SEG4                     0
+#define ATHUB_BASE__INST5_SEG5                     0
+
+#define ATHUB_BASE__INST6_SEG0                     0
+#define ATHUB_BASE__INST6_SEG1                     0
+#define ATHUB_BASE__INST6_SEG2                     0
+#define ATHUB_BASE__INST6_SEG3                     0
+#define ATHUB_BASE__INST6_SEG4                     0
+#define ATHUB_BASE__INST6_SEG5                     0
+
+#define CLK_BASE__INST0_SEG0                       0x00016C00
+#define CLK_BASE__INST0_SEG1                       0x02401800
+#define CLK_BASE__INST0_SEG2                       0
+#define CLK_BASE__INST0_SEG3                       0
+#define CLK_BASE__INST0_SEG4                       0
+#define CLK_BASE__INST0_SEG5                       0
+
+#define CLK_BASE__INST1_SEG0                       0x00016E00
+#define CLK_BASE__INST1_SEG1                       0x02401C00
+#define CLK_BASE__INST1_SEG2                       0
+#define CLK_BASE__INST1_SEG3                       0
+#define CLK_BASE__INST1_SEG4                       0
+#define CLK_BASE__INST1_SEG5                       0
+
+#define CLK_BASE__INST2_SEG0                       0x00017000
+#define CLK_BASE__INST2_SEG1                       0x02402000
+#define CLK_BASE__INST2_SEG2                       0
+#define CLK_BASE__INST2_SEG3                       0
+#define CLK_BASE__INST2_SEG4                       0
+#define CLK_BASE__INST2_SEG5                       0
+
+#define CLK_BASE__INST3_SEG0                       0x00017200
+#define CLK_BASE__INST3_SEG1                       0x02402400
+#define CLK_BASE__INST3_SEG2                       0
+#define CLK_BASE__INST3_SEG3                       0
+#define CLK_BASE__INST3_SEG4                       0
+#define CLK_BASE__INST3_SEG5                       0
+
+#define CLK_BASE__INST4_SEG0                       0x0001B000
+#define CLK_BASE__INST4_SEG1                       0x0242D800
+#define CLK_BASE__INST4_SEG2                       0
+#define CLK_BASE__INST4_SEG3                       0
+#define CLK_BASE__INST4_SEG4                       0
+#define CLK_BASE__INST4_SEG5                       0
+
+#define CLK_BASE__INST5_SEG0                       0x0001B200
+#define CLK_BASE__INST5_SEG1                       0x0242DC00
+#define CLK_BASE__INST5_SEG2                       0
+#define CLK_BASE__INST5_SEG3                       0
+#define CLK_BASE__INST5_SEG4                       0
+#define CLK_BASE__INST5_SEG5                       0
+
+#define CLK_BASE__INST6_SEG0                       0x0001B400
+#define CLK_BASE__INST6_SEG1                       0x0242E000
+#define CLK_BASE__INST6_SEG2                       0
+#define CLK_BASE__INST6_SEG3                       0
+#define CLK_BASE__INST6_SEG4                       0
+#define CLK_BASE__INST6_SEG5                       0
+
+#define DBGU_IO0_BASE__INST0_SEG0                  0x000001E0
+#define DBGU_IO0_BASE__INST0_SEG1                  0x0240B400
+#define DBGU_IO0_BASE__INST0_SEG2                  0
+#define DBGU_IO0_BASE__INST0_SEG3                  0
+#define DBGU_IO0_BASE__INST0_SEG4                  0
+#define DBGU_IO0_BASE__INST0_SEG5                  0
+
+#define DBGU_IO0_BASE__INST1_SEG0                  0x00000260
+#define DBGU_IO0_BASE__INST1_SEG1                  0x02413C00
+#define DBGU_IO0_BASE__INST1_SEG2                  0
+#define DBGU_IO0_BASE__INST1_SEG3                  0
+#define DBGU_IO0_BASE__INST1_SEG4                  0
+#define DBGU_IO0_BASE__INST1_SEG5                  0
+
+#define DBGU_IO0_BASE__INST2_SEG0                  0
+#define DBGU_IO0_BASE__INST2_SEG1                  0
+#define DBGU_IO0_BASE__INST2_SEG2                  0
+#define DBGU_IO0_BASE__INST2_SEG3                  0
+#define DBGU_IO0_BASE__INST2_SEG4                  0
+#define DBGU_IO0_BASE__INST2_SEG5                  0
+
+#define DBGU_IO0_BASE__INST3_SEG0                  0
+#define DBGU_IO0_BASE__INST3_SEG1                  0
+#define DBGU_IO0_BASE__INST3_SEG2                  0
+#define DBGU_IO0_BASE__INST3_SEG3                  0
+#define DBGU_IO0_BASE__INST3_SEG4                  0
+#define DBGU_IO0_BASE__INST3_SEG5                  0
+
+#define DBGU_IO0_BASE__INST4_SEG0                  0
+#define DBGU_IO0_BASE__INST4_SEG1                  0
+#define DBGU_IO0_BASE__INST4_SEG2                  0
+#define DBGU_IO0_BASE__INST4_SEG3                  0
+#define DBGU_IO0_BASE__INST4_SEG4                  0
+#define DBGU_IO0_BASE__INST4_SEG5                  0
+
+#define DBGU_IO0_BASE__INST5_SEG0                  0
+#define DBGU_IO0_BASE__INST5_SEG1                  0
+#define DBGU_IO0_BASE__INST5_SEG2                  0
+#define DBGU_IO0_BASE__INST5_SEG3                  0
+#define DBGU_IO0_BASE__INST5_SEG4                  0
+#define DBGU_IO0_BASE__INST5_SEG5                  0
+
+#define DBGU_IO0_BASE__INST6_SEG0                  0
+#define DBGU_IO0_BASE__INST6_SEG1                  0
+#define DBGU_IO0_BASE__INST6_SEG2                  0
+#define DBGU_IO0_BASE__INST6_SEG3                  0
+#define DBGU_IO0_BASE__INST6_SEG4                  0
+#define DBGU_IO0_BASE__INST6_SEG5                  0
+
+#define DF_BASE__INST0_SEG0                        0x00007000
+#define DF_BASE__INST0_SEG1                        0x0240B800
+#define DF_BASE__INST0_SEG2                        0
+#define DF_BASE__INST0_SEG3                        0
+#define DF_BASE__INST0_SEG4                        0
+#define DF_BASE__INST0_SEG5                        0
+
+#define DF_BASE__INST1_SEG0                        0
+#define DF_BASE__INST1_SEG1                        0
+#define DF_BASE__INST1_SEG2                        0
+#define DF_BASE__INST1_SEG3                        0
+#define DF_BASE__INST1_SEG4                        0
+#define DF_BASE__INST1_SEG5                        0
+
+#define DF_BASE__INST2_SEG0                        0
+#define DF_BASE__INST2_SEG1                        0
+#define DF_BASE__INST2_SEG2                        0
+#define DF_BASE__INST2_SEG3                        0
+#define DF_BASE__INST2_SEG4                        0
+#define DF_BASE__INST2_SEG5                        0
+
+#define DF_BASE__INST3_SEG0                        0
+#define DF_BASE__INST3_SEG1                        0
+#define DF_BASE__INST3_SEG2                        0
+#define DF_BASE__INST3_SEG3                        0
+#define DF_BASE__INST3_SEG4                        0
+#define DF_BASE__INST3_SEG5                        0
+
+#define DF_BASE__INST4_SEG0                        0
+#define DF_BASE__INST4_SEG1                        0
+#define DF_BASE__INST4_SEG2                        0
+#define DF_BASE__INST4_SEG3                        0
+#define DF_BASE__INST4_SEG4                        0
+#define DF_BASE__INST4_SEG5                        0
+
+#define DF_BASE__INST5_SEG0                        0
+#define DF_BASE__INST5_SEG1                        0
+#define DF_BASE__INST5_SEG2                        0
+#define DF_BASE__INST5_SEG3                        0
+#define DF_BASE__INST5_SEG4                        0
+#define DF_BASE__INST5_SEG5                        0
+
+#define DF_BASE__INST6_SEG0                        0
+#define DF_BASE__INST6_SEG1                        0
+#define DF_BASE__INST6_SEG2                        0
+#define DF_BASE__INST6_SEG3                        0
+#define DF_BASE__INST6_SEG4                        0
+#define DF_BASE__INST6_SEG5                        0
+
+#define DCN_BASE__INST0_SEG0                       0x00000012
+#define DCN_BASE__INST0_SEG1                       0x000000C0
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+#define DCN_BASE__INST0_SEG3                       0x00009000
+#define DCN_BASE__INST0_SEG4                       0x02403C00
+#define DCN_BASE__INST0_SEG5                       0
+
+#define DCN_BASE__INST1_SEG0                       0
+#define DCN_BASE__INST1_SEG1                       0
+#define DCN_BASE__INST1_SEG2                       0
+#define DCN_BASE__INST1_SEG3                       0
+#define DCN_BASE__INST1_SEG4                       0
+#define DCN_BASE__INST1_SEG5                       0
+
+#define DCN_BASE__INST2_SEG0                       0
+#define DCN_BASE__INST2_SEG1                       0
+#define DCN_BASE__INST2_SEG2                       0
+#define DCN_BASE__INST2_SEG3                       0
+#define DCN_BASE__INST2_SEG4                       0
+#define DCN_BASE__INST2_SEG5                       0
+
+#define DCN_BASE__INST3_SEG0                       0
+#define DCN_BASE__INST3_SEG1                       0
+#define DCN_BASE__INST3_SEG2                       0
+#define DCN_BASE__INST3_SEG3                       0
+#define DCN_BASE__INST3_SEG4                       0
+#define DCN_BASE__INST3_SEG5                       0
+
+#define DCN_BASE__INST4_SEG0                       0
+#define DCN_BASE__INST4_SEG1                       0
+#define DCN_BASE__INST4_SEG2                       0
+#define DCN_BASE__INST4_SEG3                       0
+#define DCN_BASE__INST4_SEG4                       0
+#define DCN_BASE__INST4_SEG5                       0
+
+#define DCN_BASE__INST5_SEG0                       0
+#define DCN_BASE__INST5_SEG1                       0
+#define DCN_BASE__INST5_SEG2                       0
+#define DCN_BASE__INST5_SEG3                       0
+#define DCN_BASE__INST5_SEG4                       0
+#define DCN_BASE__INST5_SEG5                       0
+
+#define DCN_BASE__INST6_SEG0                       0
+#define DCN_BASE__INST6_SEG1                       0
+#define DCN_BASE__INST6_SEG2                       0
+#define DCN_BASE__INST6_SEG3                       0
+#define DCN_BASE__INST6_SEG4                       0
+#define DCN_BASE__INST6_SEG5                       0
+
+#define DPCS_BASE__INST0_SEG0                      0x00000012
+#define DPCS_BASE__INST0_SEG1                      0x000000C0
+#define DPCS_BASE__INST0_SEG2                      0x000034C0
+#define DPCS_BASE__INST0_SEG3                      0x00009000
+#define DPCS_BASE__INST0_SEG4                      0x02403C00
+#define DPCS_BASE__INST0_SEG5                      0
+
+#define DPCS_BASE__INST1_SEG0                      0
+#define DPCS_BASE__INST1_SEG1                      0
+#define DPCS_BASE__INST1_SEG2                      0
+#define DPCS_BASE__INST1_SEG3                      0
+#define DPCS_BASE__INST1_SEG4                      0
+#define DPCS_BASE__INST1_SEG5                      0
+
+#define DPCS_BASE__INST2_SEG0                      0
+#define DPCS_BASE__INST2_SEG1                      0
+#define DPCS_BASE__INST2_SEG2                      0
+#define DPCS_BASE__INST2_SEG3                      0
+#define DPCS_BASE__INST2_SEG4                      0
+#define DPCS_BASE__INST2_SEG5                      0
+
+#define DPCS_BASE__INST3_SEG0                      0
+#define DPCS_BASE__INST3_SEG1                      0
+#define DPCS_BASE__INST3_SEG2                      0
+#define DPCS_BASE__INST3_SEG3                      0
+#define DPCS_BASE__INST3_SEG4                      0
+#define DPCS_BASE__INST3_SEG5                      0
+
+#define DPCS_BASE__INST4_SEG0                      0
+#define DPCS_BASE__INST4_SEG1                      0
+#define DPCS_BASE__INST4_SEG2                      0
+#define DPCS_BASE__INST4_SEG3                      0
+#define DPCS_BASE__INST4_SEG4                      0
+#define DPCS_BASE__INST4_SEG5                      0
+
+#define DPCS_BASE__INST5_SEG0                      0
+#define DPCS_BASE__INST5_SEG1                      0
+#define DPCS_BASE__INST5_SEG2                      0
+#define DPCS_BASE__INST5_SEG3                      0
+#define DPCS_BASE__INST5_SEG4                      0
+#define DPCS_BASE__INST5_SEG5                      0
+
+#define DPCS_BASE__INST6_SEG0                      0
+#define DPCS_BASE__INST6_SEG1                      0
+#define DPCS_BASE__INST6_SEG2                      0
+#define DPCS_BASE__INST6_SEG3                      0
+#define DPCS_BASE__INST6_SEG4                      0
+#define DPCS_BASE__INST6_SEG5                      0
+
+#define FUSE_BASE__INST0_SEG0                      0x00017400
+#define FUSE_BASE__INST0_SEG1                      0x02401400
+#define FUSE_BASE__INST0_SEG2                      0
+#define FUSE_BASE__INST0_SEG3                      0
+#define FUSE_BASE__INST0_SEG4                      0
+#define FUSE_BASE__INST0_SEG5                      0
+
+#define FUSE_BASE__INST1_SEG0                      0
+#define FUSE_BASE__INST1_SEG1                      0
+#define FUSE_BASE__INST1_SEG2                      0
+#define FUSE_BASE__INST1_SEG3                      0
+#define FUSE_BASE__INST1_SEG4                      0
+#define FUSE_BASE__INST1_SEG5                      0
+
+#define FUSE_BASE__INST2_SEG0                      0
+#define FUSE_BASE__INST2_SEG1                      0
+#define FUSE_BASE__INST2_SEG2                      0
+#define FUSE_BASE__INST2_SEG3                      0
+#define FUSE_BASE__INST2_SEG4                      0
+#define FUSE_BASE__INST2_SEG5                      0
+
+#define FUSE_BASE__INST3_SEG0                      0
+#define FUSE_BASE__INST3_SEG1                      0
+#define FUSE_BASE__INST3_SEG2                      0
+#define FUSE_BASE__INST3_SEG3                      0
+#define FUSE_BASE__INST3_SEG4                      0
+#define FUSE_BASE__INST3_SEG5                      0
+
+#define FUSE_BASE__INST4_SEG0                      0
+#define FUSE_BASE__INST4_SEG1                      0
+#define FUSE_BASE__INST4_SEG2                      0
+#define FUSE_BASE__INST4_SEG3                      0
+#define FUSE_BASE__INST4_SEG4                      0
+#define FUSE_BASE__INST4_SEG5                      0
+
+#define FUSE_BASE__INST5_SEG0                      0
+#define FUSE_BASE__INST5_SEG1                      0
+#define FUSE_BASE__INST5_SEG2                      0
+#define FUSE_BASE__INST5_SEG3                      0
+#define FUSE_BASE__INST5_SEG4                      0
+#define FUSE_BASE__INST5_SEG5                      0
+
+#define FUSE_BASE__INST6_SEG0                      0
+#define FUSE_BASE__INST6_SEG1                      0
+#define FUSE_BASE__INST6_SEG2                      0
+#define FUSE_BASE__INST6_SEG3                      0
+#define FUSE_BASE__INST6_SEG4                      0
+#define FUSE_BASE__INST6_SEG5                      0
+
+#define GC_BASE__INST0_SEG0                        0x00001260
+#define GC_BASE__INST0_SEG1                        0x0000A000
+#define GC_BASE__INST0_SEG2                        0x0001C000
+#define GC_BASE__INST0_SEG3                        0x02402C00
+#define GC_BASE__INST0_SEG4                        0
+#define GC_BASE__INST0_SEG5                        0
+
+#define GC_BASE__INST1_SEG0                        0
+#define GC_BASE__INST1_SEG1                        0
+#define GC_BASE__INST1_SEG2                        0
+#define GC_BASE__INST1_SEG3                        0
+#define GC_BASE__INST1_SEG4                        0
+#define GC_BASE__INST1_SEG5                        0
+
+#define GC_BASE__INST2_SEG0                        0
+#define GC_BASE__INST2_SEG1                        0
+#define GC_BASE__INST2_SEG2                        0
+#define GC_BASE__INST2_SEG3                        0
+#define GC_BASE__INST2_SEG4                        0
+#define GC_BASE__INST2_SEG5                        0
+
+#define GC_BASE__INST3_SEG0                        0
+#define GC_BASE__INST3_SEG1                        0
+#define GC_BASE__INST3_SEG2                        0
+#define GC_BASE__INST3_SEG3                        0
+#define GC_BASE__INST3_SEG4                        0
+#define GC_BASE__INST3_SEG5                        0
+
+#define GC_BASE__INST4_SEG0                        0
+#define GC_BASE__INST4_SEG1                        0
+#define GC_BASE__INST4_SEG2                        0
+#define GC_BASE__INST4_SEG3                        0
+#define GC_BASE__INST4_SEG4                        0
+#define GC_BASE__INST4_SEG5                        0
+
+#define GC_BASE__INST5_SEG0                        0
+#define GC_BASE__INST5_SEG1                        0
+#define GC_BASE__INST5_SEG2                        0
+#define GC_BASE__INST5_SEG3                        0
+#define GC_BASE__INST5_SEG4                        0
+#define GC_BASE__INST5_SEG5                        0
+
+#define GC_BASE__INST6_SEG0                        0
+#define GC_BASE__INST6_SEG1                        0
+#define GC_BASE__INST6_SEG2                        0
+#define GC_BASE__INST6_SEG3                        0
+#define GC_BASE__INST6_SEG4                        0
+#define GC_BASE__INST6_SEG5                        0
+
+#define HDP_BASE__INST0_SEG0                       0x00000F20
+#define HDP_BASE__INST0_SEG1                       0x0240A400
+#define HDP_BASE__INST0_SEG2                       0
+#define HDP_BASE__INST0_SEG3                       0
+#define HDP_BASE__INST0_SEG4                       0
+#define HDP_BASE__INST0_SEG5                       0
+
+#define HDP_BASE__INST1_SEG0                       0
+#define HDP_BASE__INST1_SEG1                       0
+#define HDP_BASE__INST1_SEG2                       0
+#define HDP_BASE__INST1_SEG3                       0
+#define HDP_BASE__INST1_SEG4                       0
+#define HDP_BASE__INST1_SEG5                       0
+
+#define HDP_BASE__INST2_SEG0                       0
+#define HDP_BASE__INST2_SEG1                       0
+#define HDP_BASE__INST2_SEG2                       0
+#define HDP_BASE__INST2_SEG3                       0
+#define HDP_BASE__INST2_SEG4                       0
+#define HDP_BASE__INST2_SEG5                       0
+
+#define HDP_BASE__INST3_SEG0                       0
+#define HDP_BASE__INST3_SEG1                       0
+#define HDP_BASE__INST3_SEG2                       0
+#define HDP_BASE__INST3_SEG3                       0
+#define HDP_BASE__INST3_SEG4                       0
+#define HDP_BASE__INST3_SEG5                       0
+
+#define HDP_BASE__INST4_SEG0                       0
+#define HDP_BASE__INST4_SEG1                       0
+#define HDP_BASE__INST4_SEG2                       0
+#define HDP_BASE__INST4_SEG3                       0
+#define HDP_BASE__INST4_SEG4                       0
+#define HDP_BASE__INST4_SEG5                       0
+
+#define HDP_BASE__INST5_SEG0                       0
+#define HDP_BASE__INST5_SEG1                       0
+#define HDP_BASE__INST5_SEG2                       0
+#define HDP_BASE__INST5_SEG3                       0
+#define HDP_BASE__INST5_SEG4                       0
+#define HDP_BASE__INST5_SEG5                       0
+
+#define HDP_BASE__INST6_SEG0                       0
+#define HDP_BASE__INST6_SEG1                       0
+#define HDP_BASE__INST6_SEG2                       0
+#define HDP_BASE__INST6_SEG3                       0
+#define HDP_BASE__INST6_SEG4                       0
+#define HDP_BASE__INST6_SEG5                       0
+
+#define MMHUB_BASE__INST0_SEG0                     0x0001A000
+#define MMHUB_BASE__INST0_SEG1                     0x02408800
+#define MMHUB_BASE__INST0_SEG2                     0
+#define MMHUB_BASE__INST0_SEG3                     0
+#define MMHUB_BASE__INST0_SEG4                     0
+#define MMHUB_BASE__INST0_SEG5                     0
+
+#define MMHUB_BASE__INST1_SEG0                     0
+#define MMHUB_BASE__INST1_SEG1                     0
+#define MMHUB_BASE__INST1_SEG2                     0
+#define MMHUB_BASE__INST1_SEG3                     0
+#define MMHUB_BASE__INST1_SEG4                     0
+#define MMHUB_BASE__INST1_SEG5                     0
+
+#define MMHUB_BASE__INST2_SEG0                     0
+#define MMHUB_BASE__INST2_SEG1                     0
+#define MMHUB_BASE__INST2_SEG2                     0
+#define MMHUB_BASE__INST2_SEG3                     0
+#define MMHUB_BASE__INST2_SEG4                     0
+#define MMHUB_BASE__INST2_SEG5                     0
+
+#define MMHUB_BASE__INST3_SEG0                     0
+#define MMHUB_BASE__INST3_SEG1                     0
+#define MMHUB_BASE__INST3_SEG2                     0
+#define MMHUB_BASE__INST3_SEG3                     0
+#define MMHUB_BASE__INST3_SEG4                     0
+#define MMHUB_BASE__INST3_SEG5                     0
+
+#define MMHUB_BASE__INST4_SEG0                     0
+#define MMHUB_BASE__INST4_SEG1                     0
+#define MMHUB_BASE__INST4_SEG2                     0
+#define MMHUB_BASE__INST4_SEG3                     0
+#define MMHUB_BASE__INST4_SEG4                     0
+#define MMHUB_BASE__INST4_SEG5                     0
+
+#define MMHUB_BASE__INST5_SEG0                     0
+#define MMHUB_BASE__INST5_SEG1                     0
+#define MMHUB_BASE__INST5_SEG2                     0
+#define MMHUB_BASE__INST5_SEG3                     0
+#define MMHUB_BASE__INST5_SEG4                     0
+#define MMHUB_BASE__INST5_SEG5                     0
+
+#define MMHUB_BASE__INST6_SEG0                     0
+#define MMHUB_BASE__INST6_SEG1                     0
+#define MMHUB_BASE__INST6_SEG2                     0
+#define MMHUB_BASE__INST6_SEG3                     0
+#define MMHUB_BASE__INST6_SEG4                     0
+#define MMHUB_BASE__INST6_SEG5                     0
+
+#define MP0_BASE__INST0_SEG0                       0x00016000
+#define MP0_BASE__INST0_SEG1                       0x00DC0000
+#define MP0_BASE__INST0_SEG2                       0x00E00000
+#define MP0_BASE__INST0_SEG3                       0x00E40000
+#define MP0_BASE__INST0_SEG4                       0x0243FC00
+#define MP0_BASE__INST0_SEG5                       0
+
+#define MP0_BASE__INST1_SEG0                       0
+#define MP0_BASE__INST1_SEG1                       0
+#define MP0_BASE__INST1_SEG2                       0
+#define MP0_BASE__INST1_SEG3                       0
+#define MP0_BASE__INST1_SEG4                       0
+#define MP0_BASE__INST1_SEG5                       0
+
+#define MP0_BASE__INST2_SEG0                       0
+#define MP0_BASE__INST2_SEG1                       0
+#define MP0_BASE__INST2_SEG2                       0
+#define MP0_BASE__INST2_SEG3                       0
+#define MP0_BASE__INST2_SEG4                       0
+#define MP0_BASE__INST2_SEG5                       0
+
+#define MP0_BASE__INST3_SEG0                       0
+#define MP0_BASE__INST3_SEG1                       0
+#define MP0_BASE__INST3_SEG2                       0
+#define MP0_BASE__INST3_SEG3                       0
+#define MP0_BASE__INST3_SEG4                       0
+#define MP0_BASE__INST3_SEG5                       0
+
+#define MP0_BASE__INST4_SEG0                       0
+#define MP0_BASE__INST4_SEG1                       0
+#define MP0_BASE__INST4_SEG2                       0
+#define MP0_BASE__INST4_SEG3                       0
+#define MP0_BASE__INST4_SEG4                       0
+#define MP0_BASE__INST4_SEG5                       0
+
+#define MP0_BASE__INST5_SEG0                       0
+#define MP0_BASE__INST5_SEG1                       0
+#define MP0_BASE__INST5_SEG2                       0
+#define MP0_BASE__INST5_SEG3                       0
+#define MP0_BASE__INST5_SEG4                       0
+#define MP0_BASE__INST5_SEG5                       0
+
+#define MP0_BASE__INST6_SEG0                       0
+#define MP0_BASE__INST6_SEG1                       0
+#define MP0_BASE__INST6_SEG2                       0
+#define MP0_BASE__INST6_SEG3                       0
+#define MP0_BASE__INST6_SEG4                       0
+#define MP0_BASE__INST6_SEG5                       0
+
+#define MP1_BASE__INST0_SEG0                       0x00016200
+#define MP1_BASE__INST0_SEG1                       0x00E80000
+#define MP1_BASE__INST0_SEG2                       0x00EC0000
+#define MP1_BASE__INST0_SEG3                       0x00F00000
+#define MP1_BASE__INST0_SEG4                       0x02400400
+#define MP1_BASE__INST0_SEG5                       0
+
+#define MP1_BASE__INST1_SEG0                       0
+#define MP1_BASE__INST1_SEG1                       0
+#define MP1_BASE__INST1_SEG2                       0
+#define MP1_BASE__INST1_SEG3                       0
+#define MP1_BASE__INST1_SEG4                       0
+#define MP1_BASE__INST1_SEG5                       0
+
+#define MP1_BASE__INST2_SEG0                       0
+#define MP1_BASE__INST2_SEG1                       0
+#define MP1_BASE__INST2_SEG2                       0
+#define MP1_BASE__INST2_SEG3                       0
+#define MP1_BASE__INST2_SEG4                       0
+#define MP1_BASE__INST2_SEG5                       0
+
+#define MP1_BASE__INST3_SEG0                       0
+#define MP1_BASE__INST3_SEG1                       0
+#define MP1_BASE__INST3_SEG2                       0
+#define MP1_BASE__INST3_SEG3                       0
+#define MP1_BASE__INST3_SEG4                       0
+#define MP1_BASE__INST3_SEG5                       0
+
+#define MP1_BASE__INST4_SEG0                       0
+#define MP1_BASE__INST4_SEG1                       0
+#define MP1_BASE__INST4_SEG2                       0
+#define MP1_BASE__INST4_SEG3                       0
+#define MP1_BASE__INST4_SEG4                       0
+#define MP1_BASE__INST4_SEG5                       0
+
+#define MP1_BASE__INST5_SEG0                       0
+#define MP1_BASE__INST5_SEG1                       0
+#define MP1_BASE__INST5_SEG2                       0
+#define MP1_BASE__INST5_SEG3                       0
+#define MP1_BASE__INST5_SEG4                       0
+#define MP1_BASE__INST5_SEG5                       0
+
+#define MP1_BASE__INST6_SEG0                       0
+#define MP1_BASE__INST6_SEG1                       0
+#define MP1_BASE__INST6_SEG2                       0
+#define MP1_BASE__INST6_SEG3                       0
+#define MP1_BASE__INST6_SEG4                       0
+#define MP1_BASE__INST6_SEG5                       0
+
+#define NBIO_BASE__INST0_SEG0                      0x00000000
+#define NBIO_BASE__INST0_SEG1                      0x00000014
+#define NBIO_BASE__INST0_SEG2                      0x00000D20
+#define NBIO_BASE__INST0_SEG3                      0x00010400
+#define NBIO_BASE__INST0_SEG4                      0x0241B000
+#define NBIO_BASE__INST0_SEG5                      0x04040000
+
+#define NBIO_BASE__INST1_SEG0                      0
+#define NBIO_BASE__INST1_SEG1                      0
+#define NBIO_BASE__INST1_SEG2                      0
+#define NBIO_BASE__INST1_SEG3                      0
+#define NBIO_BASE__INST1_SEG4                      0
+#define NBIO_BASE__INST1_SEG5                      0
+
+#define NBIO_BASE__INST2_SEG0                      0
+#define NBIO_BASE__INST2_SEG1                      0
+#define NBIO_BASE__INST2_SEG2                      0
+#define NBIO_BASE__INST2_SEG3                      0
+#define NBIO_BASE__INST2_SEG4                      0
+#define NBIO_BASE__INST2_SEG5                      0
+
+#define NBIO_BASE__INST3_SEG0                      0
+#define NBIO_BASE__INST3_SEG1                      0
+#define NBIO_BASE__INST3_SEG2                      0
+#define NBIO_BASE__INST3_SEG3                      0
+#define NBIO_BASE__INST3_SEG4                      0
+#define NBIO_BASE__INST3_SEG5                      0
+
+#define NBIO_BASE__INST4_SEG0                      0
+#define NBIO_BASE__INST4_SEG1                      0
+#define NBIO_BASE__INST4_SEG2                      0
+#define NBIO_BASE__INST4_SEG3                      0
+#define NBIO_BASE__INST4_SEG4                      0
+#define NBIO_BASE__INST4_SEG5                      0
+
+#define NBIO_BASE__INST5_SEG0                      0
+#define NBIO_BASE__INST5_SEG1                      0
+#define NBIO_BASE__INST5_SEG2                      0
+#define NBIO_BASE__INST5_SEG3                      0
+#define NBIO_BASE__INST5_SEG4                      0
+#define NBIO_BASE__INST5_SEG5                      0
+
+#define NBIO_BASE__INST6_SEG0                      0
+#define NBIO_BASE__INST6_SEG1                      0
+#define NBIO_BASE__INST6_SEG2                      0
+#define NBIO_BASE__INST6_SEG3                      0
+#define NBIO_BASE__INST6_SEG4                      0
+#define NBIO_BASE__INST6_SEG5                      0
+
+#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
+#define OSSSYS_BASE__INST0_SEG1                    0x0240A000
+#define OSSSYS_BASE__INST0_SEG2                    0
+#define OSSSYS_BASE__INST0_SEG3                    0
+#define OSSSYS_BASE__INST0_SEG4                    0
+#define OSSSYS_BASE__INST0_SEG5                    0
+
+#define OSSSYS_BASE__INST1_SEG0                    0
+#define OSSSYS_BASE__INST1_SEG1                    0
+#define OSSSYS_BASE__INST1_SEG2                    0
+#define OSSSYS_BASE__INST1_SEG3                    0
+#define OSSSYS_BASE__INST1_SEG4                    0
+#define OSSSYS_BASE__INST1_SEG5                    0
+
+#define OSSSYS_BASE__INST2_SEG0                    0
+#define OSSSYS_BASE__INST2_SEG1                    0
+#define OSSSYS_BASE__INST2_SEG2                    0
+#define OSSSYS_BASE__INST2_SEG3                    0
+#define OSSSYS_BASE__INST2_SEG4                    0
+#define OSSSYS_BASE__INST2_SEG5                    0
+
+#define OSSSYS_BASE__INST3_SEG0                    0
+#define OSSSYS_BASE__INST3_SEG1                    0
+#define OSSSYS_BASE__INST3_SEG2                    0
+#define OSSSYS_BASE__INST3_SEG3                    0
+#define OSSSYS_BASE__INST3_SEG4                    0
+#define OSSSYS_BASE__INST3_SEG5                    0
+
+#define OSSSYS_BASE__INST4_SEG0                    0
+#define OSSSYS_BASE__INST4_SEG1                    0
+#define OSSSYS_BASE__INST4_SEG2                    0
+#define OSSSYS_BASE__INST4_SEG3                    0
+#define OSSSYS_BASE__INST4_SEG4                    0
+#define OSSSYS_BASE__INST4_SEG5                    0
+
+#define OSSSYS_BASE__INST5_SEG0                    0
+#define OSSSYS_BASE__INST5_SEG1                    0
+#define OSSSYS_BASE__INST5_SEG2                    0
+#define OSSSYS_BASE__INST5_SEG3                    0
+#define OSSSYS_BASE__INST5_SEG4                    0
+#define OSSSYS_BASE__INST5_SEG5                    0
+
+#define OSSSYS_BASE__INST6_SEG0                    0
+#define OSSSYS_BASE__INST6_SEG1                    0
+#define OSSSYS_BASE__INST6_SEG2                    0
+#define OSSSYS_BASE__INST6_SEG3                    0
+#define OSSSYS_BASE__INST6_SEG4                    0
+#define OSSSYS_BASE__INST6_SEG5                    0
+
+#define SMUIO_BASE__INST0_SEG0                     0x00016800
+#define SMUIO_BASE__INST0_SEG1                     0x00016A00
+#define SMUIO_BASE__INST0_SEG2                     0x00440000
+#define SMUIO_BASE__INST0_SEG3                     0x02401000
+#define SMUIO_BASE__INST0_SEG4                     0
+#define SMUIO_BASE__INST0_SEG5                     0
+
+#define SMUIO_BASE__INST1_SEG0                     0
+#define SMUIO_BASE__INST1_SEG1                     0
+#define SMUIO_BASE__INST1_SEG2                     0
+#define SMUIO_BASE__INST1_SEG3                     0
+#define SMUIO_BASE__INST1_SEG4                     0
+#define SMUIO_BASE__INST1_SEG5                     0
+
+#define SMUIO_BASE__INST2_SEG0                     0
+#define SMUIO_BASE__INST2_SEG1                     0
+#define SMUIO_BASE__INST2_SEG2                     0
+#define SMUIO_BASE__INST2_SEG3                     0
+#define SMUIO_BASE__INST2_SEG4                     0
+#define SMUIO_BASE__INST2_SEG5                     0
+
+#define SMUIO_BASE__INST3_SEG0                     0
+#define SMUIO_BASE__INST3_SEG1                     0
+#define SMUIO_BASE__INST3_SEG2                     0
+#define SMUIO_BASE__INST3_SEG3                     0
+#define SMUIO_BASE__INST3_SEG4                     0
+#define SMUIO_BASE__INST3_SEG5                     0
+
+#define SMUIO_BASE__INST4_SEG0                     0
+#define SMUIO_BASE__INST4_SEG1                     0
+#define SMUIO_BASE__INST4_SEG2                     0
+#define SMUIO_BASE__INST4_SEG3                     0
+#define SMUIO_BASE__INST4_SEG4                     0
+#define SMUIO_BASE__INST4_SEG5                     0
+
+#define SMUIO_BASE__INST5_SEG0                     0
+#define SMUIO_BASE__INST5_SEG1                     0
+#define SMUIO_BASE__INST5_SEG2                     0
+#define SMUIO_BASE__INST5_SEG3                     0
+#define SMUIO_BASE__INST5_SEG4                     0
+#define SMUIO_BASE__INST5_SEG5                     0
+
+#define SMUIO_BASE__INST6_SEG0                     0
+#define SMUIO_BASE__INST6_SEG1                     0
+#define SMUIO_BASE__INST6_SEG2                     0
+#define SMUIO_BASE__INST6_SEG3                     0
+#define SMUIO_BASE__INST6_SEG4                     0
+#define SMUIO_BASE__INST6_SEG5                     0
+
+#define THM_BASE__INST0_SEG0                       0x00016600
+#define THM_BASE__INST0_SEG1                       0x02400C00
+#define THM_BASE__INST0_SEG2                       0
+#define THM_BASE__INST0_SEG3                       0
+#define THM_BASE__INST0_SEG4                       0
+#define THM_BASE__INST0_SEG5                       0
+
+#define THM_BASE__INST1_SEG0                       0
+#define THM_BASE__INST1_SEG1                       0
+#define THM_BASE__INST1_SEG2                       0
+#define THM_BASE__INST1_SEG3                       0
+#define THM_BASE__INST1_SEG4                       0
+#define THM_BASE__INST1_SEG5                       0
+
+#define THM_BASE__INST2_SEG0                       0
+#define THM_BASE__INST2_SEG1                       0
+#define THM_BASE__INST2_SEG2                       0
+#define THM_BASE__INST2_SEG3                       0
+#define THM_BASE__INST2_SEG4                       0
+#define THM_BASE__INST2_SEG5                       0
+
+#define THM_BASE__INST3_SEG0                       0
+#define THM_BASE__INST3_SEG1                       0
+#define THM_BASE__INST3_SEG2                       0
+#define THM_BASE__INST3_SEG3                       0
+#define THM_BASE__INST3_SEG4                       0
+#define THM_BASE__INST3_SEG5                       0
+
+#define THM_BASE__INST4_SEG0                       0
+#define THM_BASE__INST4_SEG1                       0
+#define THM_BASE__INST4_SEG2                       0
+#define THM_BASE__INST4_SEG3                       0
+#define THM_BASE__INST4_SEG4                       0
+#define THM_BASE__INST4_SEG5                       0
+
+#define THM_BASE__INST5_SEG0                       0
+#define THM_BASE__INST5_SEG1                       0
+#define THM_BASE__INST5_SEG2                       0
+#define THM_BASE__INST5_SEG3                       0
+#define THM_BASE__INST5_SEG4                       0
+#define THM_BASE__INST5_SEG5                       0
+
+#define THM_BASE__INST6_SEG0                       0
+#define THM_BASE__INST6_SEG1                       0
+#define THM_BASE__INST6_SEG2                       0
+#define THM_BASE__INST6_SEG3                       0
+#define THM_BASE__INST6_SEG4                       0
+#define THM_BASE__INST6_SEG5                       0
+
+#define UMC_BASE__INST0_SEG0                       0x00014000
+#define UMC_BASE__INST0_SEG1                       0x02425800
+#define UMC_BASE__INST0_SEG2                       0
+#define UMC_BASE__INST0_SEG3                       0
+#define UMC_BASE__INST0_SEG4                       0
+#define UMC_BASE__INST0_SEG5                       0
+
+#define UMC_BASE__INST1_SEG0                       0x00054000
+#define UMC_BASE__INST1_SEG1                       0x02425C00
+#define UMC_BASE__INST1_SEG2                       0
+#define UMC_BASE__INST1_SEG3                       0
+#define UMC_BASE__INST1_SEG4                       0
+#define UMC_BASE__INST1_SEG5                       0
+
+#define UMC_BASE__INST2_SEG0                       0x00094000
+#define UMC_BASE__INST2_SEG1                       0x02426000
+#define UMC_BASE__INST2_SEG2                       0
+#define UMC_BASE__INST2_SEG3                       0
+#define UMC_BASE__INST2_SEG4                       0
+#define UMC_BASE__INST2_SEG5                       0
+
+#define UMC_BASE__INST3_SEG0                       0x000D4000
+#define UMC_BASE__INST3_SEG1                       0x02426400
+#define UMC_BASE__INST3_SEG2                       0
+#define UMC_BASE__INST3_SEG3                       0
+#define UMC_BASE__INST3_SEG4                       0
+#define UMC_BASE__INST3_SEG5                       0
+
+#define UMC_BASE__INST4_SEG0                       0
+#define UMC_BASE__INST4_SEG1                       0
+#define UMC_BASE__INST4_SEG2                       0
+#define UMC_BASE__INST4_SEG3                       0
+#define UMC_BASE__INST4_SEG4                       0
+#define UMC_BASE__INST4_SEG5                       0
+
+#define UMC_BASE__INST5_SEG0                       0
+#define UMC_BASE__INST5_SEG1                       0
+#define UMC_BASE__INST5_SEG2                       0
+#define UMC_BASE__INST5_SEG3                       0
+#define UMC_BASE__INST5_SEG4                       0
+#define UMC_BASE__INST5_SEG5                       0
+
+#define UMC_BASE__INST6_SEG0                       0
+#define UMC_BASE__INST6_SEG1                       0
+#define UMC_BASE__INST6_SEG2                       0
+#define UMC_BASE__INST6_SEG3                       0
+#define UMC_BASE__INST6_SEG4                       0
+#define UMC_BASE__INST6_SEG5                       0
+
+#define VCN0_BASE__INST0_SEG0                      0x00007800
+#define VCN0_BASE__INST0_SEG1                      0x00007E00
+#define VCN0_BASE__INST0_SEG2                      0x02403000
+#define VCN0_BASE__INST0_SEG3                      0
+#define VCN0_BASE__INST0_SEG4                      0
+#define VCN0_BASE__INST0_SEG5                      0
+
+#define VCN0_BASE__INST1_SEG0                      0
+#define VCN0_BASE__INST1_SEG1                      0
+#define VCN0_BASE__INST1_SEG2                      0
+#define VCN0_BASE__INST1_SEG3                      0
+#define VCN0_BASE__INST1_SEG4                      0
+#define VCN0_BASE__INST1_SEG5                      0
+
+#define VCN0_BASE__INST2_SEG0                      0
+#define VCN0_BASE__INST2_SEG1                      0
+#define VCN0_BASE__INST2_SEG2                      0
+#define VCN0_BASE__INST2_SEG3                      0
+#define VCN0_BASE__INST2_SEG4                      0
+#define VCN0_BASE__INST2_SEG5                      0
+
+#define VCN0_BASE__INST3_SEG0                      0
+#define VCN0_BASE__INST3_SEG1                      0
+#define VCN0_BASE__INST3_SEG2                      0
+#define VCN0_BASE__INST3_SEG3                      0
+#define VCN0_BASE__INST3_SEG4                      0
+#define VCN0_BASE__INST3_SEG5                      0
+
+#define VCN0_BASE__INST4_SEG0                      0
+#define VCN0_BASE__INST4_SEG1                      0
+#define VCN0_BASE__INST4_SEG2                      0
+#define VCN0_BASE__INST4_SEG3                      0
+#define VCN0_BASE__INST4_SEG4                      0
+#define VCN0_BASE__INST4_SEG5                      0
+
+#define VCN0_BASE__INST5_SEG0                      0
+#define VCN0_BASE__INST5_SEG1                      0
+#define VCN0_BASE__INST5_SEG2                      0
+#define VCN0_BASE__INST5_SEG3                      0
+#define VCN0_BASE__INST5_SEG4                      0
+#define VCN0_BASE__INST5_SEG5                      0
+
+#define VCN0_BASE__INST6_SEG0                      0
+#define VCN0_BASE__INST6_SEG1                      0
+#define VCN0_BASE__INST6_SEG2                      0
+#define VCN0_BASE__INST6_SEG3                      0
+#define VCN0_BASE__INST6_SEG4                      0
+#define VCN0_BASE__INST6_SEG5                      0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/vangogh_ip_offset.h b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
new file mode 100644
index 000000000000..2875574b060e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/vangogh_ip_offset.h
@@ -0,0 +1,1516 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __VANGOGH_IP_OFFSET_H__
+#define __VANGOGH_IP_OFFSET_H__
+
+#define MAX_INSTANCE                                        8
+#define MAX_SEGMENT                                         6
+
+
+struct IP_BASE_INSTANCE
+{
+    unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
+                                        { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
+                                        { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
+                                        { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
+                                        { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
+                                        { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
+                                        { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } },
+                                        { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ISP_BASE = { { { { 0x00018000, 0x0240B000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP2_BASE = { { { { 0x00016400, 0x02400800, 0x00F40000, 0x00F80000, 0x00FC0000, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } },
+                                        { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
+                                        { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
+                                        { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
+                                        { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE USB_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0, 0 } },
+                                        { { 0x0242AC00, 0x05B80000, 0, 0, 0, 0 } },
+                                        { { 0x0242B000, 0x05C00000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+
+
+#define ACP_BASE__INST0_SEG0                       0x02403800
+#define ACP_BASE__INST0_SEG1                       0x00480000
+#define ACP_BASE__INST0_SEG2                       0
+#define ACP_BASE__INST0_SEG3                       0
+#define ACP_BASE__INST0_SEG4                       0
+#define ACP_BASE__INST0_SEG5                       0
+
+#define ACP_BASE__INST1_SEG0                       0
+#define ACP_BASE__INST1_SEG1                       0
+#define ACP_BASE__INST1_SEG2                       0
+#define ACP_BASE__INST1_SEG3                       0
+#define ACP_BASE__INST1_SEG4                       0
+#define ACP_BASE__INST1_SEG5                       0
+
+#define ACP_BASE__INST2_SEG0                       0
+#define ACP_BASE__INST2_SEG1                       0
+#define ACP_BASE__INST2_SEG2                       0
+#define ACP_BASE__INST2_SEG3                       0
+#define ACP_BASE__INST2_SEG4                       0
+#define ACP_BASE__INST2_SEG5                       0
+
+#define ACP_BASE__INST3_SEG0                       0
+#define ACP_BASE__INST3_SEG1                       0
+#define ACP_BASE__INST3_SEG2                       0
+#define ACP_BASE__INST3_SEG3                       0
+#define ACP_BASE__INST3_SEG4                       0
+#define ACP_BASE__INST3_SEG5                       0
+
+#define ACP_BASE__INST4_SEG0                       0
+#define ACP_BASE__INST4_SEG1                       0
+#define ACP_BASE__INST4_SEG2                       0
+#define ACP_BASE__INST4_SEG3                       0
+#define ACP_BASE__INST4_SEG4                       0
+#define ACP_BASE__INST4_SEG5                       0
+
+#define ACP_BASE__INST5_SEG0                       0
+#define ACP_BASE__INST5_SEG1                       0
+#define ACP_BASE__INST5_SEG2                       0
+#define ACP_BASE__INST5_SEG3                       0
+#define ACP_BASE__INST5_SEG4                       0
+#define ACP_BASE__INST5_SEG5                       0
+
+#define ACP_BASE__INST6_SEG0                       0
+#define ACP_BASE__INST6_SEG1                       0
+#define ACP_BASE__INST6_SEG2                       0
+#define ACP_BASE__INST6_SEG3                       0
+#define ACP_BASE__INST6_SEG4                       0
+#define ACP_BASE__INST6_SEG5                       0
+
+#define ACP_BASE__INST7_SEG0                       0
+#define ACP_BASE__INST7_SEG1                       0
+#define ACP_BASE__INST7_SEG2                       0
+#define ACP_BASE__INST7_SEG3                       0
+#define ACP_BASE__INST7_SEG4                       0
+#define ACP_BASE__INST7_SEG5                       0
+
+#define ATHUB_BASE__INST0_SEG0                     0x00000C00
+#define ATHUB_BASE__INST0_SEG1                     0x00013300
+#define ATHUB_BASE__INST0_SEG2                     0x02408C00
+#define ATHUB_BASE__INST0_SEG3                     0
+#define ATHUB_BASE__INST0_SEG4                     0
+#define ATHUB_BASE__INST0_SEG5                     0
+
+#define ATHUB_BASE__INST1_SEG0                     0
+#define ATHUB_BASE__INST1_SEG1                     0
+#define ATHUB_BASE__INST1_SEG2                     0
+#define ATHUB_BASE__INST1_SEG3                     0
+#define ATHUB_BASE__INST1_SEG4                     0
+#define ATHUB_BASE__INST1_SEG5                     0
+
+#define ATHUB_BASE__INST2_SEG0                     0
+#define ATHUB_BASE__INST2_SEG1                     0
+#define ATHUB_BASE__INST2_SEG2                     0
+#define ATHUB_BASE__INST2_SEG3                     0
+#define ATHUB_BASE__INST2_SEG4                     0
+#define ATHUB_BASE__INST2_SEG5                     0
+
+#define ATHUB_BASE__INST3_SEG0                     0
+#define ATHUB_BASE__INST3_SEG1                     0
+#define ATHUB_BASE__INST3_SEG2                     0
+#define ATHUB_BASE__INST3_SEG3                     0
+#define ATHUB_BASE__INST3_SEG4                     0
+#define ATHUB_BASE__INST3_SEG5                     0
+
+#define ATHUB_BASE__INST4_SEG0                     0
+#define ATHUB_BASE__INST4_SEG1                     0
+#define ATHUB_BASE__INST4_SEG2                     0
+#define ATHUB_BASE__INST4_SEG3                     0
+#define ATHUB_BASE__INST4_SEG4                     0
+#define ATHUB_BASE__INST4_SEG5                     0
+
+#define ATHUB_BASE__INST5_SEG0                     0
+#define ATHUB_BASE__INST5_SEG1                     0
+#define ATHUB_BASE__INST5_SEG2                     0
+#define ATHUB_BASE__INST5_SEG3                     0
+#define ATHUB_BASE__INST5_SEG4                     0
+#define ATHUB_BASE__INST5_SEG5                     0
+
+#define ATHUB_BASE__INST6_SEG0                     0
+#define ATHUB_BASE__INST6_SEG1                     0
+#define ATHUB_BASE__INST6_SEG2                     0
+#define ATHUB_BASE__INST6_SEG3                     0
+#define ATHUB_BASE__INST6_SEG4                     0
+#define ATHUB_BASE__INST6_SEG5                     0
+
+#define ATHUB_BASE__INST7_SEG0                     0
+#define ATHUB_BASE__INST7_SEG1                     0
+#define ATHUB_BASE__INST7_SEG2                     0
+#define ATHUB_BASE__INST7_SEG3                     0
+#define ATHUB_BASE__INST7_SEG4                     0
+#define ATHUB_BASE__INST7_SEG5                     0
+
+#define CLK_BASE__INST0_SEG0                       0x00016C00
+#define CLK_BASE__INST0_SEG1                       0x02401800
+#define CLK_BASE__INST0_SEG2                       0
+#define CLK_BASE__INST0_SEG3                       0
+#define CLK_BASE__INST0_SEG4                       0
+#define CLK_BASE__INST0_SEG5                       0
+
+#define CLK_BASE__INST1_SEG0                       0x00016E00
+#define CLK_BASE__INST1_SEG1                       0x02401C00
+#define CLK_BASE__INST1_SEG2                       0
+#define CLK_BASE__INST1_SEG3                       0
+#define CLK_BASE__INST1_SEG4                       0
+#define CLK_BASE__INST1_SEG5                       0
+
+#define CLK_BASE__INST2_SEG0                       0x00017000
+#define CLK_BASE__INST2_SEG1                       0x02402000
+#define CLK_BASE__INST2_SEG2                       0
+#define CLK_BASE__INST2_SEG3                       0
+#define CLK_BASE__INST2_SEG4                       0
+#define CLK_BASE__INST2_SEG5                       0
+
+#define CLK_BASE__INST3_SEG0                       0x00017200
+#define CLK_BASE__INST3_SEG1                       0x02402400
+#define CLK_BASE__INST3_SEG2                       0
+#define CLK_BASE__INST3_SEG3                       0
+#define CLK_BASE__INST3_SEG4                       0
+#define CLK_BASE__INST3_SEG5                       0
+
+#define CLK_BASE__INST4_SEG0                       0x0001B000
+#define CLK_BASE__INST4_SEG1                       0x0242D800
+#define CLK_BASE__INST4_SEG2                       0
+#define CLK_BASE__INST4_SEG3                       0
+#define CLK_BASE__INST4_SEG4                       0
+#define CLK_BASE__INST4_SEG5                       0
+
+#define CLK_BASE__INST5_SEG0                       0x0001B200
+#define CLK_BASE__INST5_SEG1                       0x0242DC00
+#define CLK_BASE__INST5_SEG2                       0
+#define CLK_BASE__INST5_SEG3                       0
+#define CLK_BASE__INST5_SEG4                       0
+#define CLK_BASE__INST5_SEG5                       0
+
+#define CLK_BASE__INST6_SEG0                       0x0001B400
+#define CLK_BASE__INST6_SEG1                       0x0242E000
+#define CLK_BASE__INST6_SEG2                       0
+#define CLK_BASE__INST6_SEG3                       0
+#define CLK_BASE__INST6_SEG4                       0
+#define CLK_BASE__INST6_SEG5                       0
+
+#define CLK_BASE__INST7_SEG0                       0x00017E00
+#define CLK_BASE__INST7_SEG1                       0x0240BC00
+#define CLK_BASE__INST7_SEG2                       0
+#define CLK_BASE__INST7_SEG3                       0
+#define CLK_BASE__INST7_SEG4                       0
+#define CLK_BASE__INST7_SEG5                       0
+
+#define DF_BASE__INST0_SEG0                        0x00007000
+#define DF_BASE__INST0_SEG1                        0x0240B800
+#define DF_BASE__INST0_SEG2                        0
+#define DF_BASE__INST0_SEG3                        0
+#define DF_BASE__INST0_SEG4                        0
+#define DF_BASE__INST0_SEG5                        0
+
+#define DF_BASE__INST1_SEG0                        0
+#define DF_BASE__INST1_SEG1                        0
+#define DF_BASE__INST1_SEG2                        0
+#define DF_BASE__INST1_SEG3                        0
+#define DF_BASE__INST1_SEG4                        0
+#define DF_BASE__INST1_SEG5                        0
+
+#define DF_BASE__INST2_SEG0                        0
+#define DF_BASE__INST2_SEG1                        0
+#define DF_BASE__INST2_SEG2                        0
+#define DF_BASE__INST2_SEG3                        0
+#define DF_BASE__INST2_SEG4                        0
+#define DF_BASE__INST2_SEG5                        0
+
+#define DF_BASE__INST3_SEG0                        0
+#define DF_BASE__INST3_SEG1                        0
+#define DF_BASE__INST3_SEG2                        0
+#define DF_BASE__INST3_SEG3                        0
+#define DF_BASE__INST3_SEG4                        0
+#define DF_BASE__INST3_SEG5                        0
+
+#define DF_BASE__INST4_SEG0                        0
+#define DF_BASE__INST4_SEG1                        0
+#define DF_BASE__INST4_SEG2                        0
+#define DF_BASE__INST4_SEG3                        0
+#define DF_BASE__INST4_SEG4                        0
+#define DF_BASE__INST4_SEG5                        0
+
+#define DF_BASE__INST5_SEG0                        0
+#define DF_BASE__INST5_SEG1                        0
+#define DF_BASE__INST5_SEG2                        0
+#define DF_BASE__INST5_SEG3                        0
+#define DF_BASE__INST5_SEG4                        0
+#define DF_BASE__INST5_SEG5                        0
+
+#define DF_BASE__INST6_SEG0                        0
+#define DF_BASE__INST6_SEG1                        0
+#define DF_BASE__INST6_SEG2                        0
+#define DF_BASE__INST6_SEG3                        0
+#define DF_BASE__INST6_SEG4                        0
+#define DF_BASE__INST6_SEG5                        0
+
+#define DF_BASE__INST7_SEG0                        0
+#define DF_BASE__INST7_SEG1                        0
+#define DF_BASE__INST7_SEG2                        0
+#define DF_BASE__INST7_SEG3                        0
+#define DF_BASE__INST7_SEG4                        0
+#define DF_BASE__INST7_SEG5                        0
+
+#define DCN_BASE__INST0_SEG0                       0x00000012
+#define DCN_BASE__INST0_SEG1                       0x000000C0
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+#define DCN_BASE__INST0_SEG3                       0x00009000
+#define DCN_BASE__INST0_SEG4                       0x02403C00
+#define DCN_BASE__INST0_SEG5                       0
+
+#define DCN_BASE__INST1_SEG0                       0
+#define DCN_BASE__INST1_SEG1                       0
+#define DCN_BASE__INST1_SEG2                       0
+#define DCN_BASE__INST1_SEG3                       0
+#define DCN_BASE__INST1_SEG4                       0
+#define DCN_BASE__INST1_SEG5                       0
+
+#define DCN_BASE__INST2_SEG0                       0
+#define DCN_BASE__INST2_SEG1                       0
+#define DCN_BASE__INST2_SEG2                       0
+#define DCN_BASE__INST2_SEG3                       0
+#define DCN_BASE__INST2_SEG4                       0
+#define DCN_BASE__INST2_SEG5                       0
+
+#define DCN_BASE__INST3_SEG0                       0
+#define DCN_BASE__INST3_SEG1                       0
+#define DCN_BASE__INST3_SEG2                       0
+#define DCN_BASE__INST3_SEG3                       0
+#define DCN_BASE__INST3_SEG4                       0
+#define DCN_BASE__INST3_SEG5                       0
+
+#define DCN_BASE__INST4_SEG0                       0
+#define DCN_BASE__INST4_SEG1                       0
+#define DCN_BASE__INST4_SEG2                       0
+#define DCN_BASE__INST4_SEG3                       0
+#define DCN_BASE__INST4_SEG4                       0
+#define DCN_BASE__INST4_SEG5                       0
+
+#define DCN_BASE__INST5_SEG0                       0
+#define DCN_BASE__INST5_SEG1                       0
+#define DCN_BASE__INST5_SEG2                       0
+#define DCN_BASE__INST5_SEG3                       0
+#define DCN_BASE__INST5_SEG4                       0
+#define DCN_BASE__INST5_SEG5                       0
+
+#define DCN_BASE__INST6_SEG0                       0
+#define DCN_BASE__INST6_SEG1                       0
+#define DCN_BASE__INST6_SEG2                       0
+#define DCN_BASE__INST6_SEG3                       0
+#define DCN_BASE__INST6_SEG4                       0
+#define DCN_BASE__INST6_SEG5                       0
+
+#define DCN_BASE__INST7_SEG0                       0
+#define DCN_BASE__INST7_SEG1                       0
+#define DCN_BASE__INST7_SEG2                       0
+#define DCN_BASE__INST7_SEG3                       0
+#define DCN_BASE__INST7_SEG4                       0
+#define DCN_BASE__INST7_SEG5                       0
+
+#define DPCS_BASE__INST0_SEG0                      0x00000012
+#define DPCS_BASE__INST0_SEG1                      0x000000C0
+#define DPCS_BASE__INST0_SEG2                      0x000034C0
+#define DPCS_BASE__INST0_SEG3                      0x00009000
+#define DPCS_BASE__INST0_SEG4                      0x02403C00
+#define DPCS_BASE__INST0_SEG5                      0
+
+#define DPCS_BASE__INST1_SEG0                      0
+#define DPCS_BASE__INST1_SEG1                      0
+#define DPCS_BASE__INST1_SEG2                      0
+#define DPCS_BASE__INST1_SEG3                      0
+#define DPCS_BASE__INST1_SEG4                      0
+#define DPCS_BASE__INST1_SEG5                      0
+
+#define DPCS_BASE__INST2_SEG0                      0
+#define DPCS_BASE__INST2_SEG1                      0
+#define DPCS_BASE__INST2_SEG2                      0
+#define DPCS_BASE__INST2_SEG3                      0
+#define DPCS_BASE__INST2_SEG4                      0
+#define DPCS_BASE__INST2_SEG5                      0
+
+#define DPCS_BASE__INST3_SEG0                      0
+#define DPCS_BASE__INST3_SEG1                      0
+#define DPCS_BASE__INST3_SEG2                      0
+#define DPCS_BASE__INST3_SEG3                      0
+#define DPCS_BASE__INST3_SEG4                      0
+#define DPCS_BASE__INST3_SEG5                      0
+
+#define DPCS_BASE__INST4_SEG0                      0
+#define DPCS_BASE__INST4_SEG1                      0
+#define DPCS_BASE__INST4_SEG2                      0
+#define DPCS_BASE__INST4_SEG3                      0
+#define DPCS_BASE__INST4_SEG4                      0
+#define DPCS_BASE__INST4_SEG5                      0
+
+#define DPCS_BASE__INST5_SEG0                      0
+#define DPCS_BASE__INST5_SEG1                      0
+#define DPCS_BASE__INST5_SEG2                      0
+#define DPCS_BASE__INST5_SEG3                      0
+#define DPCS_BASE__INST5_SEG4                      0
+#define DPCS_BASE__INST5_SEG5                      0
+
+#define DPCS_BASE__INST6_SEG0                      0
+#define DPCS_BASE__INST6_SEG1                      0
+#define DPCS_BASE__INST6_SEG2                      0
+#define DPCS_BASE__INST6_SEG3                      0
+#define DPCS_BASE__INST6_SEG4                      0
+#define DPCS_BASE__INST6_SEG5                      0
+
+#define DPCS_BASE__INST7_SEG0                      0
+#define DPCS_BASE__INST7_SEG1                      0
+#define DPCS_BASE__INST7_SEG2                      0
+#define DPCS_BASE__INST7_SEG3                      0
+#define DPCS_BASE__INST7_SEG4                      0
+#define DPCS_BASE__INST7_SEG5                      0
+
+#define FCH_BASE__INST0_SEG0                       0x0240C000
+#define FCH_BASE__INST0_SEG1                       0x00B40000
+#define FCH_BASE__INST0_SEG2                       0x11000000
+#define FCH_BASE__INST0_SEG3                       0
+#define FCH_BASE__INST0_SEG4                       0
+#define FCH_BASE__INST0_SEG5                       0
+
+#define FCH_BASE__INST1_SEG0                       0
+#define FCH_BASE__INST1_SEG1                       0
+#define FCH_BASE__INST1_SEG2                       0
+#define FCH_BASE__INST1_SEG3                       0
+#define FCH_BASE__INST1_SEG4                       0
+#define FCH_BASE__INST1_SEG5                       0
+
+#define FCH_BASE__INST2_SEG0                       0
+#define FCH_BASE__INST2_SEG1                       0
+#define FCH_BASE__INST2_SEG2                       0
+#define FCH_BASE__INST2_SEG3                       0
+#define FCH_BASE__INST2_SEG4                       0
+#define FCH_BASE__INST2_SEG5                       0
+
+#define FCH_BASE__INST3_SEG0                       0
+#define FCH_BASE__INST3_SEG1                       0
+#define FCH_BASE__INST3_SEG2                       0
+#define FCH_BASE__INST3_SEG3                       0
+#define FCH_BASE__INST3_SEG4                       0
+#define FCH_BASE__INST3_SEG5                       0
+
+#define FCH_BASE__INST4_SEG0                       0
+#define FCH_BASE__INST4_SEG1                       0
+#define FCH_BASE__INST4_SEG2                       0
+#define FCH_BASE__INST4_SEG3                       0
+#define FCH_BASE__INST4_SEG4                       0
+#define FCH_BASE__INST4_SEG5                       0
+
+#define FCH_BASE__INST5_SEG0                       0
+#define FCH_BASE__INST5_SEG1                       0
+#define FCH_BASE__INST5_SEG2                       0
+#define FCH_BASE__INST5_SEG3                       0
+#define FCH_BASE__INST5_SEG4                       0
+#define FCH_BASE__INST5_SEG5                       0
+
+#define FCH_BASE__INST6_SEG0                       0
+#define FCH_BASE__INST6_SEG1                       0
+#define FCH_BASE__INST6_SEG2                       0
+#define FCH_BASE__INST6_SEG3                       0
+#define FCH_BASE__INST6_SEG4                       0
+#define FCH_BASE__INST6_SEG5                       0
+
+#define FCH_BASE__INST7_SEG0                       0
+#define FCH_BASE__INST7_SEG1                       0
+#define FCH_BASE__INST7_SEG2                       0
+#define FCH_BASE__INST7_SEG3                       0
+#define FCH_BASE__INST7_SEG4                       0
+#define FCH_BASE__INST7_SEG5                       0
+
+#define FUSE_BASE__INST0_SEG0                      0x00017400
+#define FUSE_BASE__INST0_SEG1                      0x02401400
+#define FUSE_BASE__INST0_SEG2                      0
+#define FUSE_BASE__INST0_SEG3                      0
+#define FUSE_BASE__INST0_SEG4                      0
+#define FUSE_BASE__INST0_SEG5                      0
+
+#define FUSE_BASE__INST1_SEG0                      0
+#define FUSE_BASE__INST1_SEG1                      0
+#define FUSE_BASE__INST1_SEG2                      0
+#define FUSE_BASE__INST1_SEG3                      0
+#define FUSE_BASE__INST1_SEG4                      0
+#define FUSE_BASE__INST1_SEG5                      0
+
+#define FUSE_BASE__INST2_SEG0                      0
+#define FUSE_BASE__INST2_SEG1                      0
+#define FUSE_BASE__INST2_SEG2                      0
+#define FUSE_BASE__INST2_SEG3                      0
+#define FUSE_BASE__INST2_SEG4                      0
+#define FUSE_BASE__INST2_SEG5                      0
+
+#define FUSE_BASE__INST3_SEG0                      0
+#define FUSE_BASE__INST3_SEG1                      0
+#define FUSE_BASE__INST3_SEG2                      0
+#define FUSE_BASE__INST3_SEG3                      0
+#define FUSE_BASE__INST3_SEG4                      0
+#define FUSE_BASE__INST3_SEG5                      0
+
+#define FUSE_BASE__INST4_SEG0                      0
+#define FUSE_BASE__INST4_SEG1                      0
+#define FUSE_BASE__INST4_SEG2                      0
+#define FUSE_BASE__INST4_SEG3                      0
+#define FUSE_BASE__INST4_SEG4                      0
+#define FUSE_BASE__INST4_SEG5                      0
+
+#define FUSE_BASE__INST5_SEG0                      0
+#define FUSE_BASE__INST5_SEG1                      0
+#define FUSE_BASE__INST5_SEG2                      0
+#define FUSE_BASE__INST5_SEG3                      0
+#define FUSE_BASE__INST5_SEG4                      0
+#define FUSE_BASE__INST5_SEG5                      0
+
+#define FUSE_BASE__INST6_SEG0                      0
+#define FUSE_BASE__INST6_SEG1                      0
+#define FUSE_BASE__INST6_SEG2                      0
+#define FUSE_BASE__INST6_SEG3                      0
+#define FUSE_BASE__INST6_SEG4                      0
+#define FUSE_BASE__INST6_SEG5                      0
+
+#define FUSE_BASE__INST7_SEG0                      0
+#define FUSE_BASE__INST7_SEG1                      0
+#define FUSE_BASE__INST7_SEG2                      0
+#define FUSE_BASE__INST7_SEG3                      0
+#define FUSE_BASE__INST7_SEG4                      0
+#define FUSE_BASE__INST7_SEG5                      0
+
+#define GC_BASE__INST0_SEG0                        0x00001260
+#define GC_BASE__INST0_SEG1                        0x0000A000
+#define GC_BASE__INST0_SEG2                        0x02402C00
+#define GC_BASE__INST0_SEG3                        0
+#define GC_BASE__INST0_SEG4                        0
+#define GC_BASE__INST0_SEG5                        0
+
+#define GC_BASE__INST1_SEG0                        0
+#define GC_BASE__INST1_SEG1                        0
+#define GC_BASE__INST1_SEG2                        0
+#define GC_BASE__INST1_SEG3                        0
+#define GC_BASE__INST1_SEG4                        0
+#define GC_BASE__INST1_SEG5                        0
+
+#define GC_BASE__INST2_SEG0                        0
+#define GC_BASE__INST2_SEG1                        0
+#define GC_BASE__INST2_SEG2                        0
+#define GC_BASE__INST2_SEG3                        0
+#define GC_BASE__INST2_SEG4                        0
+#define GC_BASE__INST2_SEG5                        0
+
+#define GC_BASE__INST3_SEG0                        0
+#define GC_BASE__INST3_SEG1                        0
+#define GC_BASE__INST3_SEG2                        0
+#define GC_BASE__INST3_SEG3                        0
+#define GC_BASE__INST3_SEG4                        0
+#define GC_BASE__INST3_SEG5                        0
+
+#define GC_BASE__INST4_SEG0                        0
+#define GC_BASE__INST4_SEG1                        0
+#define GC_BASE__INST4_SEG2                        0
+#define GC_BASE__INST4_SEG3                        0
+#define GC_BASE__INST4_SEG4                        0
+#define GC_BASE__INST4_SEG5                        0
+
+#define GC_BASE__INST5_SEG0                        0
+#define GC_BASE__INST5_SEG1                        0
+#define GC_BASE__INST5_SEG2                        0
+#define GC_BASE__INST5_SEG3                        0
+#define GC_BASE__INST5_SEG4                        0
+#define GC_BASE__INST5_SEG5                        0
+
+#define GC_BASE__INST6_SEG0                        0
+#define GC_BASE__INST6_SEG1                        0
+#define GC_BASE__INST6_SEG2                        0
+#define GC_BASE__INST6_SEG3                        0
+#define GC_BASE__INST6_SEG4                        0
+#define GC_BASE__INST6_SEG5                        0
+
+#define GC_BASE__INST7_SEG0                        0
+#define GC_BASE__INST7_SEG1                        0
+#define GC_BASE__INST7_SEG2                        0
+#define GC_BASE__INST7_SEG3                        0
+#define GC_BASE__INST7_SEG4                        0
+#define GC_BASE__INST7_SEG5                        0
+
+#define HDP_BASE__INST0_SEG0                       0x00000F20
+#define HDP_BASE__INST0_SEG1                       0x0240A400
+#define HDP_BASE__INST0_SEG2                       0
+#define HDP_BASE__INST0_SEG3                       0
+#define HDP_BASE__INST0_SEG4                       0
+#define HDP_BASE__INST0_SEG5                       0
+
+#define HDP_BASE__INST1_SEG0                       0
+#define HDP_BASE__INST1_SEG1                       0
+#define HDP_BASE__INST1_SEG2                       0
+#define HDP_BASE__INST1_SEG3                       0
+#define HDP_BASE__INST1_SEG4                       0
+#define HDP_BASE__INST1_SEG5                       0
+
+#define HDP_BASE__INST2_SEG0                       0
+#define HDP_BASE__INST2_SEG1                       0
+#define HDP_BASE__INST2_SEG2                       0
+#define HDP_BASE__INST2_SEG3                       0
+#define HDP_BASE__INST2_SEG4                       0
+#define HDP_BASE__INST2_SEG5                       0
+
+#define HDP_BASE__INST3_SEG0                       0
+#define HDP_BASE__INST3_SEG1                       0
+#define HDP_BASE__INST3_SEG2                       0
+#define HDP_BASE__INST3_SEG3                       0
+#define HDP_BASE__INST3_SEG4                       0
+#define HDP_BASE__INST3_SEG5                       0
+
+#define HDP_BASE__INST4_SEG0                       0
+#define HDP_BASE__INST4_SEG1                       0
+#define HDP_BASE__INST4_SEG2                       0
+#define HDP_BASE__INST4_SEG3                       0
+#define HDP_BASE__INST4_SEG4                       0
+#define HDP_BASE__INST4_SEG5                       0
+
+#define HDP_BASE__INST5_SEG0                       0
+#define HDP_BASE__INST5_SEG1                       0
+#define HDP_BASE__INST5_SEG2                       0
+#define HDP_BASE__INST5_SEG3                       0
+#define HDP_BASE__INST5_SEG4                       0
+#define HDP_BASE__INST5_SEG5                       0
+
+#define HDP_BASE__INST6_SEG0                       0
+#define HDP_BASE__INST6_SEG1                       0
+#define HDP_BASE__INST6_SEG2                       0
+#define HDP_BASE__INST6_SEG3                       0
+#define HDP_BASE__INST6_SEG4                       0
+#define HDP_BASE__INST6_SEG5                       0
+
+#define HDP_BASE__INST7_SEG0                       0
+#define HDP_BASE__INST7_SEG1                       0
+#define HDP_BASE__INST7_SEG2                       0
+#define HDP_BASE__INST7_SEG3                       0
+#define HDP_BASE__INST7_SEG4                       0
+#define HDP_BASE__INST7_SEG5                       0
+
+#define ISP_BASE__INST0_SEG0                       0x00018000
+#define ISP_BASE__INST0_SEG1                       0x0240B000
+#define ISP_BASE__INST0_SEG2                       0
+#define ISP_BASE__INST0_SEG3                       0
+#define ISP_BASE__INST0_SEG4                       0
+#define ISP_BASE__INST0_SEG5                       0
+
+#define ISP_BASE__INST1_SEG0                       0
+#define ISP_BASE__INST1_SEG1                       0
+#define ISP_BASE__INST1_SEG2                       0
+#define ISP_BASE__INST1_SEG3                       0
+#define ISP_BASE__INST1_SEG4                       0
+#define ISP_BASE__INST1_SEG5                       0
+
+#define ISP_BASE__INST2_SEG0                       0
+#define ISP_BASE__INST2_SEG1                       0
+#define ISP_BASE__INST2_SEG2                       0
+#define ISP_BASE__INST2_SEG3                       0
+#define ISP_BASE__INST2_SEG4                       0
+#define ISP_BASE__INST2_SEG5                       0
+
+#define ISP_BASE__INST3_SEG0                       0
+#define ISP_BASE__INST3_SEG1                       0
+#define ISP_BASE__INST3_SEG2                       0
+#define ISP_BASE__INST3_SEG3                       0
+#define ISP_BASE__INST3_SEG4                       0
+#define ISP_BASE__INST3_SEG5                       0
+
+#define ISP_BASE__INST4_SEG0                       0
+#define ISP_BASE__INST4_SEG1                       0
+#define ISP_BASE__INST4_SEG2                       0
+#define ISP_BASE__INST4_SEG3                       0
+#define ISP_BASE__INST4_SEG4                       0
+#define ISP_BASE__INST4_SEG5                       0
+
+#define ISP_BASE__INST5_SEG0                       0
+#define ISP_BASE__INST5_SEG1                       0
+#define ISP_BASE__INST5_SEG2                       0
+#define ISP_BASE__INST5_SEG3                       0
+#define ISP_BASE__INST5_SEG4                       0
+#define ISP_BASE__INST5_SEG5                       0
+
+#define ISP_BASE__INST6_SEG0                       0
+#define ISP_BASE__INST6_SEG1                       0
+#define ISP_BASE__INST6_SEG2                       0
+#define ISP_BASE__INST6_SEG3                       0
+#define ISP_BASE__INST6_SEG4                       0
+#define ISP_BASE__INST6_SEG5                       0
+
+#define ISP_BASE__INST7_SEG0                       0
+#define ISP_BASE__INST7_SEG1                       0
+#define ISP_BASE__INST7_SEG2                       0
+#define ISP_BASE__INST7_SEG3                       0
+#define ISP_BASE__INST7_SEG4                       0
+#define ISP_BASE__INST7_SEG5                       0
+
+#define MMHUB_BASE__INST0_SEG0                     0x00013200
+#define MMHUB_BASE__INST0_SEG1                     0x0001A000
+#define MMHUB_BASE__INST0_SEG2                     0x02408800
+#define MMHUB_BASE__INST0_SEG3                     0
+#define MMHUB_BASE__INST0_SEG4                     0
+#define MMHUB_BASE__INST0_SEG5                     0
+
+#define MMHUB_BASE__INST1_SEG0                     0
+#define MMHUB_BASE__INST1_SEG1                     0
+#define MMHUB_BASE__INST1_SEG2                     0
+#define MMHUB_BASE__INST1_SEG3                     0
+#define MMHUB_BASE__INST1_SEG4                     0
+#define MMHUB_BASE__INST1_SEG5                     0
+
+#define MMHUB_BASE__INST2_SEG0                     0
+#define MMHUB_BASE__INST2_SEG1                     0
+#define MMHUB_BASE__INST2_SEG2                     0
+#define MMHUB_BASE__INST2_SEG3                     0
+#define MMHUB_BASE__INST2_SEG4                     0
+#define MMHUB_BASE__INST2_SEG5                     0
+
+#define MMHUB_BASE__INST3_SEG0                     0
+#define MMHUB_BASE__INST3_SEG1                     0
+#define MMHUB_BASE__INST3_SEG2                     0
+#define MMHUB_BASE__INST3_SEG3                     0
+#define MMHUB_BASE__INST3_SEG4                     0
+#define MMHUB_BASE__INST3_SEG5                     0
+
+#define MMHUB_BASE__INST4_SEG0                     0
+#define MMHUB_BASE__INST4_SEG1                     0
+#define MMHUB_BASE__INST4_SEG2                     0
+#define MMHUB_BASE__INST4_SEG3                     0
+#define MMHUB_BASE__INST4_SEG4                     0
+#define MMHUB_BASE__INST4_SEG5                     0
+
+#define MMHUB_BASE__INST5_SEG0                     0
+#define MMHUB_BASE__INST5_SEG1                     0
+#define MMHUB_BASE__INST5_SEG2                     0
+#define MMHUB_BASE__INST5_SEG3                     0
+#define MMHUB_BASE__INST5_SEG4                     0
+#define MMHUB_BASE__INST5_SEG5                     0
+
+#define MMHUB_BASE__INST6_SEG0                     0
+#define MMHUB_BASE__INST6_SEG1                     0
+#define MMHUB_BASE__INST6_SEG2                     0
+#define MMHUB_BASE__INST6_SEG3                     0
+#define MMHUB_BASE__INST6_SEG4                     0
+#define MMHUB_BASE__INST6_SEG5                     0
+
+#define MMHUB_BASE__INST7_SEG0                     0
+#define MMHUB_BASE__INST7_SEG1                     0
+#define MMHUB_BASE__INST7_SEG2                     0
+#define MMHUB_BASE__INST7_SEG3                     0
+#define MMHUB_BASE__INST7_SEG4                     0
+#define MMHUB_BASE__INST7_SEG5                     0
+
+#define MP0_BASE__INST0_SEG0                       0x00016000
+#define MP0_BASE__INST0_SEG1                       0x0243FC00
+#define MP0_BASE__INST0_SEG2                       0x00DC0000
+#define MP0_BASE__INST0_SEG3                       0x00E00000
+#define MP0_BASE__INST0_SEG4                       0x00E40000
+#define MP0_BASE__INST0_SEG5                       0
+
+#define MP0_BASE__INST1_SEG0                       0
+#define MP0_BASE__INST1_SEG1                       0
+#define MP0_BASE__INST1_SEG2                       0
+#define MP0_BASE__INST1_SEG3                       0
+#define MP0_BASE__INST1_SEG4                       0
+#define MP0_BASE__INST1_SEG5                       0
+
+#define MP0_BASE__INST2_SEG0                       0
+#define MP0_BASE__INST2_SEG1                       0
+#define MP0_BASE__INST2_SEG2                       0
+#define MP0_BASE__INST2_SEG3                       0
+#define MP0_BASE__INST2_SEG4                       0
+#define MP0_BASE__INST2_SEG5                       0
+
+#define MP0_BASE__INST3_SEG0                       0
+#define MP0_BASE__INST3_SEG1                       0
+#define MP0_BASE__INST3_SEG2                       0
+#define MP0_BASE__INST3_SEG3                       0
+#define MP0_BASE__INST3_SEG4                       0
+#define MP0_BASE__INST3_SEG5                       0
+
+#define MP0_BASE__INST4_SEG0                       0
+#define MP0_BASE__INST4_SEG1                       0
+#define MP0_BASE__INST4_SEG2                       0
+#define MP0_BASE__INST4_SEG3                       0
+#define MP0_BASE__INST4_SEG4                       0
+#define MP0_BASE__INST4_SEG5                       0
+
+#define MP0_BASE__INST5_SEG0                       0
+#define MP0_BASE__INST5_SEG1                       0
+#define MP0_BASE__INST5_SEG2                       0
+#define MP0_BASE__INST5_SEG3                       0
+#define MP0_BASE__INST5_SEG4                       0
+#define MP0_BASE__INST5_SEG5                       0
+
+#define MP0_BASE__INST6_SEG0                       0
+#define MP0_BASE__INST6_SEG1                       0
+#define MP0_BASE__INST6_SEG2                       0
+#define MP0_BASE__INST6_SEG3                       0
+#define MP0_BASE__INST6_SEG4                       0
+#define MP0_BASE__INST6_SEG5                       0
+
+#define MP0_BASE__INST7_SEG0                       0
+#define MP0_BASE__INST7_SEG1                       0
+#define MP0_BASE__INST7_SEG2                       0
+#define MP0_BASE__INST7_SEG3                       0
+#define MP0_BASE__INST7_SEG4                       0
+#define MP0_BASE__INST7_SEG5                       0
+
+#define MP1_BASE__INST0_SEG0                       0x00016000
+#define MP1_BASE__INST0_SEG1                       0x0243FC00
+#define MP1_BASE__INST0_SEG2                       0x00DC0000
+#define MP1_BASE__INST0_SEG3                       0x00E00000
+#define MP1_BASE__INST0_SEG4                       0x00E40000
+#define MP1_BASE__INST0_SEG5                       0
+
+#define MP1_BASE__INST1_SEG0                       0
+#define MP1_BASE__INST1_SEG1                       0
+#define MP1_BASE__INST1_SEG2                       0
+#define MP1_BASE__INST1_SEG3                       0
+#define MP1_BASE__INST1_SEG4                       0
+#define MP1_BASE__INST1_SEG5                       0
+
+#define MP1_BASE__INST2_SEG0                       0
+#define MP1_BASE__INST2_SEG1                       0
+#define MP1_BASE__INST2_SEG2                       0
+#define MP1_BASE__INST2_SEG3                       0
+#define MP1_BASE__INST2_SEG4                       0
+#define MP1_BASE__INST2_SEG5                       0
+
+#define MP1_BASE__INST3_SEG0                       0
+#define MP1_BASE__INST3_SEG1                       0
+#define MP1_BASE__INST3_SEG2                       0
+#define MP1_BASE__INST3_SEG3                       0
+#define MP1_BASE__INST3_SEG4                       0
+#define MP1_BASE__INST3_SEG5                       0
+
+#define MP1_BASE__INST4_SEG0                       0
+#define MP1_BASE__INST4_SEG1                       0
+#define MP1_BASE__INST4_SEG2                       0
+#define MP1_BASE__INST4_SEG3                       0
+#define MP1_BASE__INST4_SEG4                       0
+#define MP1_BASE__INST4_SEG5                       0
+
+#define MP1_BASE__INST5_SEG0                       0
+#define MP1_BASE__INST5_SEG1                       0
+#define MP1_BASE__INST5_SEG2                       0
+#define MP1_BASE__INST5_SEG3                       0
+#define MP1_BASE__INST5_SEG4                       0
+#define MP1_BASE__INST5_SEG5                       0
+
+#define MP1_BASE__INST6_SEG0                       0
+#define MP1_BASE__INST6_SEG1                       0
+#define MP1_BASE__INST6_SEG2                       0
+#define MP1_BASE__INST6_SEG3                       0
+#define MP1_BASE__INST6_SEG4                       0
+#define MP1_BASE__INST6_SEG5                       0
+
+#define MP1_BASE__INST7_SEG0                       0
+#define MP1_BASE__INST7_SEG1                       0
+#define MP1_BASE__INST7_SEG2                       0
+#define MP1_BASE__INST7_SEG3                       0
+#define MP1_BASE__INST7_SEG4                       0
+#define MP1_BASE__INST7_SEG5                       0
+
+#define MP2_BASE__INST0_SEG0                       0x00016400
+#define MP2_BASE__INST0_SEG1                       0x02400800
+#define MP2_BASE__INST0_SEG2                       0x00F40000
+#define MP2_BASE__INST0_SEG3                       0x00F80000
+#define MP2_BASE__INST0_SEG4                       0x00FC0000
+#define MP2_BASE__INST0_SEG5                       0
+
+#define MP2_BASE__INST1_SEG0                       0
+#define MP2_BASE__INST1_SEG1                       0
+#define MP2_BASE__INST1_SEG2                       0
+#define MP2_BASE__INST1_SEG3                       0
+#define MP2_BASE__INST1_SEG4                       0
+#define MP2_BASE__INST1_SEG5                       0
+
+#define MP2_BASE__INST2_SEG0                       0
+#define MP2_BASE__INST2_SEG1                       0
+#define MP2_BASE__INST2_SEG2                       0
+#define MP2_BASE__INST2_SEG3                       0
+#define MP2_BASE__INST2_SEG4                       0
+#define MP2_BASE__INST2_SEG5                       0
+
+#define MP2_BASE__INST3_SEG0                       0
+#define MP2_BASE__INST3_SEG1                       0
+#define MP2_BASE__INST3_SEG2                       0
+#define MP2_BASE__INST3_SEG3                       0
+#define MP2_BASE__INST3_SEG4                       0
+#define MP2_BASE__INST3_SEG5                       0
+
+#define MP2_BASE__INST4_SEG0                       0
+#define MP2_BASE__INST4_SEG1                       0
+#define MP2_BASE__INST4_SEG2                       0
+#define MP2_BASE__INST4_SEG3                       0
+#define MP2_BASE__INST4_SEG4                       0
+#define MP2_BASE__INST4_SEG5                       0
+
+#define MP2_BASE__INST5_SEG0                       0
+#define MP2_BASE__INST5_SEG1                       0
+#define MP2_BASE__INST5_SEG2                       0
+#define MP2_BASE__INST5_SEG3                       0
+#define MP2_BASE__INST5_SEG4                       0
+#define MP2_BASE__INST5_SEG5                       0
+
+#define MP2_BASE__INST6_SEG0                       0
+#define MP2_BASE__INST6_SEG1                       0
+#define MP2_BASE__INST6_SEG2                       0
+#define MP2_BASE__INST6_SEG3                       0
+#define MP2_BASE__INST6_SEG4                       0
+#define MP2_BASE__INST6_SEG5                       0
+
+#define MP2_BASE__INST7_SEG0                       0
+#define MP2_BASE__INST7_SEG1                       0
+#define MP2_BASE__INST7_SEG2                       0
+#define MP2_BASE__INST7_SEG3                       0
+#define MP2_BASE__INST7_SEG4                       0
+#define MP2_BASE__INST7_SEG5                       0
+
+#define NBIO_BASE__INST0_SEG0                      0x00000000
+#define NBIO_BASE__INST0_SEG1                      0x00000014
+#define NBIO_BASE__INST0_SEG2                      0x00000D20
+#define NBIO_BASE__INST0_SEG3                      0x00010400
+#define NBIO_BASE__INST0_SEG4                      0x0241B000
+#define NBIO_BASE__INST0_SEG5                      0x04040000
+
+#define NBIO_BASE__INST1_SEG0                      0
+#define NBIO_BASE__INST1_SEG1                      0
+#define NBIO_BASE__INST1_SEG2                      0
+#define NBIO_BASE__INST1_SEG3                      0
+#define NBIO_BASE__INST1_SEG4                      0
+#define NBIO_BASE__INST1_SEG5                      0
+
+#define NBIO_BASE__INST2_SEG0                      0
+#define NBIO_BASE__INST2_SEG1                      0
+#define NBIO_BASE__INST2_SEG2                      0
+#define NBIO_BASE__INST2_SEG3                      0
+#define NBIO_BASE__INST2_SEG4                      0
+#define NBIO_BASE__INST2_SEG5                      0
+
+#define NBIO_BASE__INST3_SEG0                      0
+#define NBIO_BASE__INST3_SEG1                      0
+#define NBIO_BASE__INST3_SEG2                      0
+#define NBIO_BASE__INST3_SEG3                      0
+#define NBIO_BASE__INST3_SEG4                      0
+#define NBIO_BASE__INST3_SEG5                      0
+
+#define NBIO_BASE__INST4_SEG0                      0
+#define NBIO_BASE__INST4_SEG1                      0
+#define NBIO_BASE__INST4_SEG2                      0
+#define NBIO_BASE__INST4_SEG3                      0
+#define NBIO_BASE__INST4_SEG4                      0
+#define NBIO_BASE__INST4_SEG5                      0
+
+#define NBIO_BASE__INST5_SEG0                      0
+#define NBIO_BASE__INST5_SEG1                      0
+#define NBIO_BASE__INST5_SEG2                      0
+#define NBIO_BASE__INST5_SEG3                      0
+#define NBIO_BASE__INST5_SEG4                      0
+#define NBIO_BASE__INST5_SEG5                      0
+
+#define NBIO_BASE__INST6_SEG0                      0
+#define NBIO_BASE__INST6_SEG1                      0
+#define NBIO_BASE__INST6_SEG2                      0
+#define NBIO_BASE__INST6_SEG3                      0
+#define NBIO_BASE__INST6_SEG4                      0
+#define NBIO_BASE__INST6_SEG5                      0
+
+#define NBIO_BASE__INST7_SEG0                      0
+#define NBIO_BASE__INST7_SEG1                      0
+#define NBIO_BASE__INST7_SEG2                      0
+#define NBIO_BASE__INST7_SEG3                      0
+#define NBIO_BASE__INST7_SEG4                      0
+#define NBIO_BASE__INST7_SEG5                      0
+
+#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
+#define OSSSYS_BASE__INST0_SEG1                    0x0240A000
+#define OSSSYS_BASE__INST0_SEG2                    0
+#define OSSSYS_BASE__INST0_SEG3                    0
+#define OSSSYS_BASE__INST0_SEG4                    0
+#define OSSSYS_BASE__INST0_SEG5                    0
+
+#define OSSSYS_BASE__INST1_SEG0                    0
+#define OSSSYS_BASE__INST1_SEG1                    0
+#define OSSSYS_BASE__INST1_SEG2                    0
+#define OSSSYS_BASE__INST1_SEG3                    0
+#define OSSSYS_BASE__INST1_SEG4                    0
+#define OSSSYS_BASE__INST1_SEG5                    0
+
+#define OSSSYS_BASE__INST2_SEG0                    0
+#define OSSSYS_BASE__INST2_SEG1                    0
+#define OSSSYS_BASE__INST2_SEG2                    0
+#define OSSSYS_BASE__INST2_SEG3                    0
+#define OSSSYS_BASE__INST2_SEG4                    0
+#define OSSSYS_BASE__INST2_SEG5                    0
+
+#define OSSSYS_BASE__INST3_SEG0                    0
+#define OSSSYS_BASE__INST3_SEG1                    0
+#define OSSSYS_BASE__INST3_SEG2                    0
+#define OSSSYS_BASE__INST3_SEG3                    0
+#define OSSSYS_BASE__INST3_SEG4                    0
+#define OSSSYS_BASE__INST3_SEG5                    0
+
+#define OSSSYS_BASE__INST4_SEG0                    0
+#define OSSSYS_BASE__INST4_SEG1                    0
+#define OSSSYS_BASE__INST4_SEG2                    0
+#define OSSSYS_BASE__INST4_SEG3                    0
+#define OSSSYS_BASE__INST4_SEG4                    0
+#define OSSSYS_BASE__INST4_SEG5                    0
+
+#define OSSSYS_BASE__INST5_SEG0                    0
+#define OSSSYS_BASE__INST5_SEG1                    0
+#define OSSSYS_BASE__INST5_SEG2                    0
+#define OSSSYS_BASE__INST5_SEG3                    0
+#define OSSSYS_BASE__INST5_SEG4                    0
+#define OSSSYS_BASE__INST5_SEG5                    0
+
+#define OSSSYS_BASE__INST6_SEG0                    0
+#define OSSSYS_BASE__INST6_SEG1                    0
+#define OSSSYS_BASE__INST6_SEG2                    0
+#define OSSSYS_BASE__INST6_SEG3                    0
+#define OSSSYS_BASE__INST6_SEG4                    0
+#define OSSSYS_BASE__INST6_SEG5                    0
+
+#define OSSSYS_BASE__INST7_SEG0                    0
+#define OSSSYS_BASE__INST7_SEG1                    0
+#define OSSSYS_BASE__INST7_SEG2                    0
+#define OSSSYS_BASE__INST7_SEG3                    0
+#define OSSSYS_BASE__INST7_SEG4                    0
+#define OSSSYS_BASE__INST7_SEG5                    0
+
+#define PCIE0_BASE__INST0_SEG0                     0x00000000
+#define PCIE0_BASE__INST0_SEG1                     0x00000014
+#define PCIE0_BASE__INST0_SEG2                     0x00000D20
+#define PCIE0_BASE__INST0_SEG3                     0x00010400
+#define PCIE0_BASE__INST0_SEG4                     0x0241B000
+#define PCIE0_BASE__INST0_SEG5                     0x04040000
+
+#define PCIE0_BASE__INST1_SEG0                     0
+#define PCIE0_BASE__INST1_SEG1                     0
+#define PCIE0_BASE__INST1_SEG2                     0
+#define PCIE0_BASE__INST1_SEG3                     0
+#define PCIE0_BASE__INST1_SEG4                     0
+#define PCIE0_BASE__INST1_SEG5                     0
+
+#define PCIE0_BASE__INST2_SEG0                     0
+#define PCIE0_BASE__INST2_SEG1                     0
+#define PCIE0_BASE__INST2_SEG2                     0
+#define PCIE0_BASE__INST2_SEG3                     0
+#define PCIE0_BASE__INST2_SEG4                     0
+#define PCIE0_BASE__INST2_SEG5                     0
+
+#define PCIE0_BASE__INST3_SEG0                     0
+#define PCIE0_BASE__INST3_SEG1                     0
+#define PCIE0_BASE__INST3_SEG2                     0
+#define PCIE0_BASE__INST3_SEG3                     0
+#define PCIE0_BASE__INST3_SEG4                     0
+#define PCIE0_BASE__INST3_SEG5                     0
+
+#define PCIE0_BASE__INST4_SEG0                     0
+#define PCIE0_BASE__INST4_SEG1                     0
+#define PCIE0_BASE__INST4_SEG2                     0
+#define PCIE0_BASE__INST4_SEG3                     0
+#define PCIE0_BASE__INST4_SEG4                     0
+#define PCIE0_BASE__INST4_SEG5                     0
+
+#define PCIE0_BASE__INST5_SEG0                     0
+#define PCIE0_BASE__INST5_SEG1                     0
+#define PCIE0_BASE__INST5_SEG2                     0
+#define PCIE0_BASE__INST5_SEG3                     0
+#define PCIE0_BASE__INST5_SEG4                     0
+#define PCIE0_BASE__INST5_SEG5                     0
+
+#define PCIE0_BASE__INST6_SEG0                     0
+#define PCIE0_BASE__INST6_SEG1                     0
+#define PCIE0_BASE__INST6_SEG2                     0
+#define PCIE0_BASE__INST6_SEG3                     0
+#define PCIE0_BASE__INST6_SEG4                     0
+#define PCIE0_BASE__INST6_SEG5                     0
+
+#define PCIE0_BASE__INST7_SEG0                     0
+#define PCIE0_BASE__INST7_SEG1                     0
+#define PCIE0_BASE__INST7_SEG2                     0
+#define PCIE0_BASE__INST7_SEG3                     0
+#define PCIE0_BASE__INST7_SEG4                     0
+#define PCIE0_BASE__INST7_SEG5                     0
+
+#define SMUIO_BASE__INST0_SEG0                      0x00016800
+#define SMUIO_BASE__INST0_SEG1                      0x00016A00
+#define SMUIO_BASE__INST0_SEG2                      0x02401000
+#define SMUIO_BASE__INST0_SEG3                      0x00440000
+#define SMUIO_BASE__INST0_SEG4                      0
+#define SMUIO_BASE__INST0_SEG5                      0
+
+#define SMUIO_BASE__INST1_SEG0                      0x0001BC00
+#define SMUIO_BASE__INST1_SEG1                      0x0242D400
+#define SMUIO_BASE__INST1_SEG2                      0
+#define SMUIO_BASE__INST1_SEG3                      0
+#define SMUIO_BASE__INST1_SEG4                      0
+#define SMUIO_BASE__INST1_SEG5                      0
+
+#define SMUIO_BASE__INST2_SEG0                      0
+#define SMUIO_BASE__INST2_SEG1                      0
+#define SMUIO_BASE__INST2_SEG2                      0
+#define SMUIO_BASE__INST2_SEG3                      0
+#define SMUIO_BASE__INST2_SEG4                      0
+#define SMUIO_BASE__INST2_SEG5                      0
+
+#define SMUIO_BASE__INST3_SEG0                      0
+#define SMUIO_BASE__INST3_SEG1                      0
+#define SMUIO_BASE__INST3_SEG2                      0
+#define SMUIO_BASE__INST3_SEG3                      0
+#define SMUIO_BASE__INST3_SEG4                      0
+#define SMUIO_BASE__INST3_SEG5                      0
+
+#define SMUIO_BASE__INST4_SEG0                      0
+#define SMUIO_BASE__INST4_SEG1                      0
+#define SMUIO_BASE__INST4_SEG2                      0
+#define SMUIO_BASE__INST4_SEG3                      0
+#define SMUIO_BASE__INST4_SEG4                      0
+#define SMUIO_BASE__INST4_SEG5                      0
+
+#define SMUIO_BASE__INST5_SEG0                      0
+#define SMUIO_BASE__INST5_SEG1                      0
+#define SMUIO_BASE__INST5_SEG2                      0
+#define SMUIO_BASE__INST5_SEG3                      0
+#define SMUIO_BASE__INST5_SEG4                      0
+#define SMUIO_BASE__INST5_SEG5                      0
+
+#define SMUIO_BASE__INST6_SEG0                      0
+#define SMUIO_BASE__INST6_SEG1                      0
+#define SMUIO_BASE__INST6_SEG2                      0
+#define SMUIO_BASE__INST6_SEG3                      0
+#define SMUIO_BASE__INST6_SEG4                      0
+#define SMUIO_BASE__INST6_SEG5                      0
+
+#define SMUIO_BASE__INST7_SEG0                      0
+#define SMUIO_BASE__INST7_SEG1                      0
+#define SMUIO_BASE__INST7_SEG2                      0
+#define SMUIO_BASE__INST7_SEG3                      0
+#define SMUIO_BASE__INST7_SEG4                      0
+#define SMUIO_BASE__INST7_SEG5                      0
+
+#define THM_BASE__INST0_SEG0                       0x00016600
+#define THM_BASE__INST0_SEG1                       0x02400C00
+#define THM_BASE__INST0_SEG2                       0
+#define THM_BASE__INST0_SEG3                       0
+#define THM_BASE__INST0_SEG4                       0
+#define THM_BASE__INST0_SEG5                       0
+
+#define THM_BASE__INST1_SEG0                       0
+#define THM_BASE__INST1_SEG1                       0
+#define THM_BASE__INST1_SEG2                       0
+#define THM_BASE__INST1_SEG3                       0
+#define THM_BASE__INST1_SEG4                       0
+#define THM_BASE__INST1_SEG5                       0
+
+#define THM_BASE__INST2_SEG0                       0
+#define THM_BASE__INST2_SEG1                       0
+#define THM_BASE__INST2_SEG2                       0
+#define THM_BASE__INST2_SEG3                       0
+#define THM_BASE__INST2_SEG4                       0
+#define THM_BASE__INST2_SEG5                       0
+
+#define THM_BASE__INST3_SEG0                       0
+#define THM_BASE__INST3_SEG1                       0
+#define THM_BASE__INST3_SEG2                       0
+#define THM_BASE__INST3_SEG3                       0
+#define THM_BASE__INST3_SEG4                       0
+#define THM_BASE__INST3_SEG5                       0
+
+#define THM_BASE__INST4_SEG0                       0
+#define THM_BASE__INST4_SEG1                       0
+#define THM_BASE__INST4_SEG2                       0
+#define THM_BASE__INST4_SEG3                       0
+#define THM_BASE__INST4_SEG4                       0
+#define THM_BASE__INST4_SEG5                       0
+
+#define THM_BASE__INST5_SEG0                       0
+#define THM_BASE__INST5_SEG1                       0
+#define THM_BASE__INST5_SEG2                       0
+#define THM_BASE__INST5_SEG3                       0
+#define THM_BASE__INST5_SEG4                       0
+#define THM_BASE__INST5_SEG5                       0
+
+#define THM_BASE__INST6_SEG0                       0
+#define THM_BASE__INST6_SEG1                       0
+#define THM_BASE__INST6_SEG2                       0
+#define THM_BASE__INST6_SEG3                       0
+#define THM_BASE__INST6_SEG4                       0
+#define THM_BASE__INST6_SEG5                       0
+
+#define THM_BASE__INST7_SEG0                       0
+#define THM_BASE__INST7_SEG1                       0
+#define THM_BASE__INST7_SEG2                       0
+#define THM_BASE__INST7_SEG3                       0
+#define THM_BASE__INST7_SEG4                       0
+#define THM_BASE__INST7_SEG5                       0
+
+#define UMC_BASE__INST0_SEG0                       0x00014000
+#define UMC_BASE__INST0_SEG1                       0x02425800
+#define UMC_BASE__INST0_SEG2                       0
+#define UMC_BASE__INST0_SEG3                       0
+#define UMC_BASE__INST0_SEG4                       0
+#define UMC_BASE__INST0_SEG5                       0
+
+#define UMC_BASE__INST1_SEG0                       0x00054000
+#define UMC_BASE__INST1_SEG1                       0x02425C00
+#define UMC_BASE__INST1_SEG2                       0
+#define UMC_BASE__INST1_SEG3                       0
+#define UMC_BASE__INST1_SEG4                       0
+#define UMC_BASE__INST1_SEG5                       0
+
+#define UMC_BASE__INST2_SEG0                       0x00094000
+#define UMC_BASE__INST2_SEG1                       0x02426000
+#define UMC_BASE__INST2_SEG2                       0
+#define UMC_BASE__INST2_SEG3                       0
+#define UMC_BASE__INST2_SEG4                       0
+#define UMC_BASE__INST2_SEG5                       0
+
+#define UMC_BASE__INST3_SEG0                       0x000D4000
+#define UMC_BASE__INST3_SEG1                       0x02426400
+#define UMC_BASE__INST3_SEG2                       0
+#define UMC_BASE__INST3_SEG3                       0
+#define UMC_BASE__INST3_SEG4                       0
+#define UMC_BASE__INST3_SEG5                       0
+
+#define UMC_BASE__INST4_SEG0                       0
+#define UMC_BASE__INST4_SEG1                       0
+#define UMC_BASE__INST4_SEG2                       0
+#define UMC_BASE__INST4_SEG3                       0
+#define UMC_BASE__INST4_SEG4                       0
+#define UMC_BASE__INST4_SEG5                       0
+
+#define UMC_BASE__INST5_SEG0                       0
+#define UMC_BASE__INST5_SEG1                       0
+#define UMC_BASE__INST5_SEG2                       0
+#define UMC_BASE__INST5_SEG3                       0
+#define UMC_BASE__INST5_SEG4                       0
+#define UMC_BASE__INST5_SEG5                       0
+
+#define UMC_BASE__INST6_SEG0                       0
+#define UMC_BASE__INST6_SEG1                       0
+#define UMC_BASE__INST6_SEG2                       0
+#define UMC_BASE__INST6_SEG3                       0
+#define UMC_BASE__INST6_SEG4                       0
+#define UMC_BASE__INST6_SEG5                       0
+
+#define UMC_BASE__INST7_SEG0                       0
+#define UMC_BASE__INST7_SEG1                       0
+#define UMC_BASE__INST7_SEG2                       0
+#define UMC_BASE__INST7_SEG3                       0
+#define UMC_BASE__INST7_SEG4                       0
+#define UMC_BASE__INST7_SEG5                       0
+
+#define USB_BASE__INST0_SEG0                       0x0242A800
+#define USB_BASE__INST0_SEG1                       0x05B00000
+#define USB_BASE__INST0_SEG2                       0
+#define USB_BASE__INST0_SEG3                       0
+#define USB_BASE__INST0_SEG4                       0
+#define USB_BASE__INST0_SEG5                       0
+
+#define USB_BASE__INST1_SEG0                       0x0242AC00
+#define USB_BASE__INST1_SEG1                       0x05B80000
+#define USB_BASE__INST1_SEG2                       0
+#define USB_BASE__INST1_SEG3                       0
+#define USB_BASE__INST1_SEG4                       0
+#define USB_BASE__INST1_SEG5                       0
+
+#define USB_BASE__INST2_SEG0                       0x0242B000
+#define USB_BASE__INST2_SEG1                       0x05C00000
+#define USB_BASE__INST2_SEG2                       0
+#define USB_BASE__INST2_SEG3                       0
+#define USB_BASE__INST2_SEG4                       0
+#define USB_BASE__INST2_SEG5                       0
+
+#define USB_BASE__INST3_SEG0                       0
+#define USB_BASE__INST3_SEG1                       0
+#define USB_BASE__INST3_SEG2                       0
+#define USB_BASE__INST3_SEG3                       0
+#define USB_BASE__INST3_SEG4                       0
+#define USB_BASE__INST3_SEG5                       0
+
+#define USB_BASE__INST4_SEG0                       0
+#define USB_BASE__INST4_SEG1                       0
+#define USB_BASE__INST4_SEG2                       0
+#define USB_BASE__INST4_SEG3                       0
+#define USB_BASE__INST4_SEG4                       0
+#define USB_BASE__INST4_SEG5                       0
+
+#define USB_BASE__INST5_SEG0                       0
+#define USB_BASE__INST5_SEG1                       0
+#define USB_BASE__INST5_SEG2                       0
+#define USB_BASE__INST5_SEG3                       0
+#define USB_BASE__INST5_SEG4                       0
+#define USB_BASE__INST5_SEG5                       0
+
+#define USB_BASE__INST6_SEG0                       0
+#define USB_BASE__INST6_SEG1                       0
+#define USB_BASE__INST6_SEG2                       0
+#define USB_BASE__INST6_SEG3                       0
+#define USB_BASE__INST6_SEG4                       0
+#define USB_BASE__INST6_SEG5                       0
+
+#define USB_BASE__INST7_SEG0                       0
+#define USB_BASE__INST7_SEG1                       0
+#define USB_BASE__INST7_SEG2                       0
+#define USB_BASE__INST7_SEG3                       0
+#define USB_BASE__INST7_SEG4                       0
+#define USB_BASE__INST7_SEG5                       0
+
+#define VCN_BASE__INST0_SEG0                      0x00007800
+#define VCN_BASE__INST0_SEG1                      0x00007E00
+#define VCN_BASE__INST0_SEG2                      0x02403000
+#define VCN_BASE__INST0_SEG3                      0
+#define VCN_BASE__INST0_SEG4                      0
+#define VCN_BASE__INST0_SEG5                      0
+
+#define VCN_BASE__INST1_SEG0                      0
+#define VCN_BASE__INST1_SEG1                      0
+#define VCN_BASE__INST1_SEG2                      0
+#define VCN_BASE__INST1_SEG3                      0
+#define VCN_BASE__INST1_SEG4                      0
+#define VCN_BASE__INST1_SEG5                      0
+
+#define VCN_BASE__INST2_SEG0                      0
+#define VCN_BASE__INST2_SEG1                      0
+#define VCN_BASE__INST2_SEG2                      0
+#define VCN_BASE__INST2_SEG3                      0
+#define VCN_BASE__INST2_SEG4                      0
+#define VCN_BASE__INST2_SEG5                      0
+
+#define VCN_BASE__INST3_SEG0                      0
+#define VCN_BASE__INST3_SEG1                      0
+#define VCN_BASE__INST3_SEG2                      0
+#define VCN_BASE__INST3_SEG3                      0
+#define VCN_BASE__INST3_SEG4                      0
+#define VCN_BASE__INST3_SEG5                      0
+
+#define VCN_BASE__INST4_SEG0                      0
+#define VCN_BASE__INST4_SEG1                      0
+#define VCN_BASE__INST4_SEG2                      0
+#define VCN_BASE__INST4_SEG3                      0
+#define VCN_BASE__INST4_SEG4                      0
+#define VCN_BASE__INST4_SEG5                      0
+
+#define VCN_BASE__INST5_SEG0                      0
+#define VCN_BASE__INST5_SEG1                      0
+#define VCN_BASE__INST5_SEG2                      0
+#define VCN_BASE__INST5_SEG3                      0
+#define VCN_BASE__INST5_SEG4                      0
+#define VCN_BASE__INST5_SEG5                      0
+
+#define VCN_BASE__INST6_SEG0                      0
+#define VCN_BASE__INST6_SEG1                      0
+#define VCN_BASE__INST6_SEG2                      0
+#define VCN_BASE__INST6_SEG3                      0
+#define VCN_BASE__INST6_SEG4                      0
+#define VCN_BASE__INST6_SEG5                      0
+
+#define VCN_BASE__INST7_SEG0                      0
+#define VCN_BASE__INST7_SEG1                      0
+#define VCN_BASE__INST7_SEG2                      0
+#define VCN_BASE__INST7_SEG3                      0
+#define VCN_BASE__INST7_SEG4                      0
+#define VCN_BASE__INST7_SEG5                      0
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 529816637c73..7b6ef05a1d35 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -39,6 +39,7 @@
 #include "hwmgr.h"
 
 static const struct cg_flag_name clocks[] = {
+	{AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
 	{AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
 	{AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
 	{AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
@@ -63,6 +64,11 @@ static const struct cg_flag_name clocks[] = {
 	{AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
 	{AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
 	{AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
+	{AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
+	{AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
+	{AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
+	{AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
+	{AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
 
 	{AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
 	{AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
@@ -940,8 +946,6 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
 	if (ret)
 		return -EINVAL;
 
-	pr_debug("featuremask = 0x%llx\n", featuremask);
-
 	ret = pm_runtime_get_sync(ddev->dev);
 	if (ret < 0) {
 		pm_runtime_put_autosuspend(ddev->dev);
@@ -1501,7 +1505,7 @@ static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 	}
 
 	if (is_support_sw_smu(adev))
-		value = smu_get_od_percentage(&(adev->smu), SMU_OD_SCLK);
+		value = 0;
 	else if (adev->powerplay.pp_funcs->get_sclk_od)
 		value = amdgpu_dpm_get_sclk_od(adev);
 
@@ -1536,7 +1540,7 @@ static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 	}
 
 	if (is_support_sw_smu(adev)) {
-		value = smu_set_od_percentage(&(adev->smu), SMU_OD_SCLK, (uint32_t)value);
+		value = 0;
 	} else {
 		if (adev->powerplay.pp_funcs->set_sclk_od)
 			amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
@@ -1574,7 +1578,7 @@ static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 	}
 
 	if (is_support_sw_smu(adev))
-		value = smu_get_od_percentage(&(adev->smu), SMU_OD_MCLK);
+		value = 0;
 	else if (adev->powerplay.pp_funcs->get_mclk_od)
 		value = amdgpu_dpm_get_mclk_od(adev);
 
@@ -1609,7 +1613,7 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 	}
 
 	if (is_support_sw_smu(adev)) {
-		value = smu_set_od_percentage(&(adev->smu), SMU_OD_MCLK, (uint32_t)value);
+		value = 0;
 	} else {
 		if (adev->powerplay.pp_funcs->set_mclk_od)
 			amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
@@ -2060,9 +2064,6 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
 	} else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
 		if (asic_type < CHIP_VEGA20)
 			*states = ATTR_STATE_UNSUPPORTED;
-	} else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
-		if (asic_type == CHIP_ARCTURUS)
-			*states = ATTR_STATE_UNSUPPORTED;
 	} else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
 		*states = ATTR_STATE_UNSUPPORTED;
 		if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
@@ -3467,7 +3468,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
 {
 	uint32_t value;
-	uint64_t value64;
+	uint64_t value64 = 0;
 	uint32_t query = 0;
 	int size;
 
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 44fd0cd069de..9724d6fd82f4 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -31,6 +31,7 @@
 #define SMU_THERMAL_MINIMUM_ALERT_TEMP		0
 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP		255
 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES	1000
+#define SMU_FW_NAME_LEN			0x24
 
 struct smu_hw_power_state {
 	unsigned int magic;
@@ -225,6 +226,7 @@ struct smu_bios_boot_up_values
 	uint32_t			format_revision;
 	uint32_t			content_revision;
 	uint32_t			fclk;
+	uint32_t			lclk;
 };
 
 enum smu_table_id
@@ -470,11 +472,6 @@ struct pptable_funcs {
 	int (*populate_umd_state_clk)(struct smu_context *smu);
 	int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
 	int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
-	int (*set_default_od8_settings)(struct smu_context *smu);
-	int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type);
-	int (*set_od_percentage)(struct smu_context *smu,
-				 enum smu_clk_type clk_type,
-				 uint32_t value);
 	int (*od_edit_dpm_table)(struct smu_context *smu,
 				 enum PP_OD_DPM_TABLE_COMMAND type,
 				 long *input, uint32_t size);
@@ -483,11 +480,6 @@ struct pptable_funcs {
 					      struct
 					      pp_clock_levels_with_latency
 					      *clocks);
-	int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
-					      enum amd_pp_clock_type type,
-					      struct
-					      pp_clock_levels_with_voltage
-					      *clocks);
 	int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
 	int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
 	int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
@@ -498,7 +490,6 @@ struct pptable_funcs {
 	int (*display_config_changed)(struct smu_context *smu);
 	int (*apply_clocks_adjust_rules)(struct smu_context *smu);
 	int (*notify_smc_display_config)(struct smu_context *smu);
-	int (*set_cpu_power_state)(struct smu_context *smu);
 	bool (*is_dpm_running)(struct smu_context *smu);
 	int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
 	int (*set_watermarks_table)(struct smu_context *smu,
@@ -534,7 +525,6 @@ struct pptable_funcs {
 	int (*set_driver_table_location)(struct smu_context *smu);
 	int (*set_tool_table_location)(struct smu_context *smu);
 	int (*notify_memory_pool_location)(struct smu_context *smu);
-	int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
 	int (*system_features_control)(struct smu_context *smu, bool en);
 	int (*send_smc_msg_with_param)(struct smu_context *smu,
 				       enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
@@ -552,27 +542,9 @@ struct pptable_funcs {
 	int (*enable_thermal_alert)(struct smu_context *smu);
 	int (*disable_thermal_alert)(struct smu_context *smu);
 	int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);
-	int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
-	int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
-			      bool cc6_disable, bool pstate_disable,
-			      bool pstate_switch_disable);
-	int (*get_clock_by_type)(struct smu_context *smu,
-				 enum amd_pp_clock_type type,
-				 struct amd_pp_clocks *clocks);
-	int (*get_max_high_clocks)(struct smu_context *smu,
-				   struct amd_pp_simple_clock_info *clocks);
 	int (*display_clock_voltage_request)(struct smu_context *smu, struct
 					     pp_display_clock_request
 					     *clock_req);
-	int (*get_dal_power_level)(struct smu_context *smu,
-				   struct amd_pp_simple_clock_info *clocks);
-	int (*get_perf_level)(struct smu_context *smu,
-			      enum smu_perf_level_designation designation,
-			      struct smu_performance_level *level);
-	int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
-						struct smu_clock_info *clocks);
-	int (*notify_smu_enable_pwe)(struct smu_context *smu);
-	int (*conv_power_profile_to_pplib_workload)(int power_profile);
 	uint32_t (*get_fan_control_mode)(struct smu_context *smu);
 	int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
 	int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
@@ -603,6 +575,7 @@ struct pptable_funcs {
 	int (*get_fan_parameters)(struct smu_context *smu);
 	int (*post_init)(struct smu_context *smu);
 	void (*interrupt_work)(struct smu_context *smu);
+	int (*gpo_control)(struct smu_context *smu, bool enablement);
 };
 
 typedef enum {
@@ -683,8 +656,6 @@ int smu_get_power_limit(struct smu_context *smu,
 
 int smu_set_power_limit(struct smu_context *smu, uint32_t limit);
 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
-int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type);
-int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value);
 
 int smu_od_edit_dpm_table(struct smu_context *smu,
 			  enum PP_OD_DPM_TABLE_COMMAND type,
@@ -707,25 +678,13 @@ int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed);
 
 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk);
 
-int smu_get_clock_by_type(struct smu_context *smu,
-			  enum amd_pp_clock_type type,
-			  struct amd_pp_clocks *clocks);
-
-int smu_get_max_high_clocks(struct smu_context *smu,
-			    struct amd_pp_simple_clock_info *clocks);
-
 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
 				       enum smu_clk_type clk_type,
 				       struct pp_clock_levels_with_latency *clocks);
 
-int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
-				       enum amd_pp_clock_type type,
-				       struct pp_clock_levels_with_voltage *clocks);
-
 int smu_display_clock_voltage_request(struct smu_context *smu,
 				      struct pp_display_clock_request *clock_req);
 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
-int smu_notify_smu_enable_pwe(struct smu_context *smu);
 
 int smu_set_xgmi_pstate(struct smu_context *smu,
 			uint32_t pstate);
@@ -763,8 +722,6 @@ int smu_set_watermarks_for_clock_ranges(
 extern int smu_display_configuration_change(struct smu_context *smu, const
 					    struct amd_pp_display_configuration
 					    *display_config);
-extern int smu_get_current_clocks(struct smu_context *smu,
-				  struct amd_pp_clock_info *clocks);
 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
 extern int smu_handle_task(struct smu_context *smu,
 			   enum amd_dpm_forced_level level,
diff --git a/drivers/gpu/drm/amd/pm/inc/hwmgr.h b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
index 3898a95ec28b..7e29ec2902dc 100644
--- a/drivers/gpu/drm/amd/pm/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
@@ -60,7 +60,7 @@ struct vi_dpm_level {
 
 struct vi_dpm_table {
 	uint32_t count;
-	struct vi_dpm_level dpm_level[1];
+	struct vi_dpm_level dpm_level[];
 };
 
 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
@@ -91,7 +91,7 @@ struct phm_set_power_state_input {
 
 struct phm_clock_array {
 	uint32_t count;
-	uint32_t values[1];
+	uint32_t values[];
 };
 
 struct phm_clock_voltage_dependency_record {
@@ -122,8 +122,8 @@ struct phm_acpclock_voltage_dependency_record {
 };
 
 struct phm_clock_voltage_dependency_table {
-	uint32_t count;										/* Number of entries. */
-	struct phm_clock_voltage_dependency_record entries[1];		/* Dynamically allocate count entries. */
+	uint32_t count;							/* Number of entries. */
+	struct phm_clock_voltage_dependency_record entries[];		/* Dynamically allocate count entries. */
 };
 
 struct phm_phase_shedding_limits_record {
@@ -140,7 +140,7 @@ struct phm_uvd_clock_voltage_dependency_record {
 
 struct phm_uvd_clock_voltage_dependency_table {
 	uint8_t count;
-	struct phm_uvd_clock_voltage_dependency_record entries[1];
+	struct phm_uvd_clock_voltage_dependency_record entries[];
 };
 
 struct phm_acp_clock_voltage_dependency_record {
@@ -150,7 +150,7 @@ struct phm_acp_clock_voltage_dependency_record {
 
 struct phm_acp_clock_voltage_dependency_table {
 	uint32_t count;
-	struct phm_acp_clock_voltage_dependency_record entries[1];
+	struct phm_acp_clock_voltage_dependency_record entries[];
 };
 
 struct phm_vce_clock_voltage_dependency_record {
@@ -161,7 +161,7 @@ struct phm_vce_clock_voltage_dependency_record {
 
 struct phm_phase_shedding_limits_table {
 	uint32_t                           count;
-	struct phm_phase_shedding_limits_record  entries[1];
+	struct phm_phase_shedding_limits_record  entries[];
 };
 
 struct phm_vceclock_voltage_dependency_table {
@@ -186,7 +186,7 @@ struct phm_acpclock_voltage_dependency_table {
 
 struct phm_vce_clock_voltage_dependency_table {
 	uint8_t count;
-	struct phm_vce_clock_voltage_dependency_record entries[1];
+	struct phm_vce_clock_voltage_dependency_record entries[];
 };
 
 
@@ -229,6 +229,7 @@ struct pp_smumgr_func {
 	bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);
 	int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
 	int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
+	int (*stop_smc)(struct pp_hwmgr *hwmgr);
 };
 
 struct pp_hwmgr_func {
@@ -393,7 +394,7 @@ union phm_cac_leakage_record {
 
 struct phm_cac_leakage_table {
 	uint32_t count;
-	union phm_cac_leakage_record entries[1];
+	union phm_cac_leakage_record entries[];
 };
 
 struct phm_samu_clock_voltage_dependency_record {
@@ -404,7 +405,7 @@ struct phm_samu_clock_voltage_dependency_record {
 
 struct phm_samu_clock_voltage_dependency_table {
 	uint8_t count;
-	struct phm_samu_clock_voltage_dependency_record entries[1];
+	struct phm_samu_clock_voltage_dependency_record entries[];
 };
 
 struct phm_cac_tdp_table {
@@ -441,6 +442,7 @@ struct phm_cac_tdp_table {
 	uint8_t  ucPlx_I2C_Line;
 	uint32_t usBoostPowerLimit;
 	uint8_t  ucCKS_LDO_REFSEL;
+	uint8_t  ucHotSpotOnly;
 };
 
 struct phm_tdp_table {
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index 1275246769d9..e418a46603c8 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if 
 // any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x39
+#define SMU11_DRIVER_IF_VERSION 0x3A
 
 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 6
 
@@ -226,6 +226,8 @@ typedef enum {
 #define FW_DSTATE_MEM_PLL_PWRDN_BIT         9   
 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10
 #define FW_DSTATE_MEM_PSI_BIT               11
+#define FW_DSTATE_HSR_NON_STROBE_BIT        12
+#define FW_DSTATE_MP0_ENTER_WFI_BIT         13
 
 #define FW_DSTATE_SOC_ULV_MASK                    (1 << FW_DSTATE_SOC_ULV_BIT          )
 #define FW_DSTATE_G6_HSR_MASK                     (1 << FW_DSTATE_G6_HSR_BIT           )
@@ -239,6 +241,8 @@ typedef enum {
 #define FW_DSTATE_MEM_PLL_PWRDN_MASK              (1 << FW_DSTATE_MEM_PLL_PWRDN_BIT    )
 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK      (1 << FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT    )
 #define FW_DSTATE_MEM_PSI_MASK                    (1 << FW_DSTATE_MEM_PSI_BIT    )
+#define FW_DSTATE_HSR_NON_STROBE_MASK             (1 << FW_DSTATE_HSR_NON_STROBE_BIT    )
+#define FW_DSTATE_MP0_ENTER_WFI_MASK              (1 << FW_DSTATE_MP0_ENTER_WFI_BIT    )
 
 // GFX GPO Feature Contains PACE and DEM sub features
 #define GFX_GPO_PACE_BIT                   0
@@ -804,7 +808,11 @@ typedef struct {
   uint32_t         VcBtcVminA;                  // A_VMIN
   uint32_t         VcBtcVminB;                  // B_VMIN  
   
-  uint32_t         SkuReserved[9];
+  //GPIO Board feature
+  uint16_t         LedGpio;            //GeneriA GPIO flag used to control the radeon LEDs
+  uint16_t         GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 
+  
+  uint32_t         SkuReserved[8];
 
 
   // MAJOR SECTION: BOARD PARAMETERS
@@ -1026,6 +1034,8 @@ typedef struct {
   uint16_t VcnActivityPercentage  ; //place holder, David N. to provide full sequence
   uint8_t  PcieRate               ;
   uint8_t  PcieWidth              ;
+  uint16_t AverageGfxclkFrequencyTarget;
+  uint16_t Padding16_2;
 
 } SmuMetrics_t;
 
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
new file mode 100644
index 000000000000..8f438c80132e
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU11_DRIVER_IF_VANGOGH_H__
+#define __SMU11_DRIVER_IF_VANGOGH_H__
+
+// *** IMPORTANT ***
+// SMU TEAM: Always increment the interface version if
+// any structure is changed in this file
+#define SMU13_DRIVER_IF_VERSION 2
+
+typedef struct {
+  int32_t value;
+  uint32_t numFractionalBits;
+} FloatInIntFormat_t;
+
+typedef enum {
+  DSPCLK_DCFCLK = 0,
+  DSPCLK_DISPCLK,
+  DSPCLK_PIXCLK,
+  DSPCLK_PHYCLK,
+  DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+  uint16_t Freq; // in MHz
+  uint16_t Vid;  // min voltage in SVI2 VID
+} DisplayClockTable_t;
+
+typedef struct {
+  uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
+  uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
+  uint16_t MinMclk;
+  uint16_t MaxMclk;
+
+  uint8_t  WmSetting;
+  uint8_t  WmType;  // Used for normal pstate change or memory retraining
+  uint8_t  Padding[2];
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+#define WM_PSTATE_CHG 0
+#define WM_RETRAINING 1
+
+typedef enum {
+  WM_SOCCLK = 0,
+  WM_DCFCLK,
+  WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+  // Watermarks
+  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+  uint32_t     MmHubPadding[7]; // SMU internal use
+} Watermarks_t;
+
+typedef enum {
+  CUSTOM_DPM_SETTING_GFXCLK,
+  CUSTOM_DPM_SETTING_CCLK,
+  CUSTOM_DPM_SETTING_FCLK_CCX,
+  CUSTOM_DPM_SETTING_FCLK_GFX,
+  CUSTOM_DPM_SETTING_FCLK_STALLS,
+  CUSTOM_DPM_SETTING_LCLK,
+  CUSTOM_DPM_SETTING_COUNT,
+} CUSTOM_DPM_SETTING_e;
+
+typedef struct {
+  uint8_t             ActiveHystLimit;
+  uint8_t             IdleHystLimit;
+  uint8_t             FPS;
+  uint8_t             MinActiveFreqType;
+  FloatInIntFormat_t  MinActiveFreq;
+  FloatInIntFormat_t  PD_Data_limit;
+  FloatInIntFormat_t  PD_Data_time_constant;
+  FloatInIntFormat_t  PD_Data_error_coeff;
+  FloatInIntFormat_t  PD_Data_error_rate_coeff;
+} DpmActivityMonitorCoeffExt_t;
+
+typedef struct {
+  DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
+} CustomDpmSettings_t;
+
+#define NUM_DCFCLK_DPM_LEVELS 7
+#define NUM_DISPCLK_DPM_LEVELS 7
+#define NUM_DPPCLK_DPM_LEVELS 7
+#define NUM_SOCCLK_DPM_LEVELS 7
+#define NUM_ISPICLK_DPM_LEVELS 7
+#define NUM_ISPXCLK_DPM_LEVELS 7
+#define NUM_VCN_DPM_LEVELS 5
+#define NUM_FCLK_DPM_LEVELS 4
+#define NUM_SOC_VOLTAGE_LEVELS 8
+
+typedef struct {
+  uint32_t fclk;
+  uint32_t memclk;
+  uint32_t voltage;
+} df_pstate_t;
+
+typedef struct {
+  uint32_t vclk;
+  uint32_t dclk;
+} vcn_clk_t;
+
+//Freq in MHz
+//Voltage in milli volts with 2 fractional bits
+
+typedef struct {
+  uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
+  uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
+  uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
+  uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
+  uint32_t IspiClocks[NUM_ISPICLK_DPM_LEVELS];
+  uint32_t IspxClocks[NUM_ISPXCLK_DPM_LEVELS];
+  vcn_clk_t VcnClocks[NUM_VCN_DPM_LEVELS];
+
+  uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
+
+  df_pstate_t DfPstateTable[NUM_FCLK_DPM_LEVELS];
+
+  uint32_t MinGfxClk;
+  uint32_t MaxGfxClk;
+
+  uint8_t NumDfPstatesEnabled;
+  uint8_t NumDpmLevelsEnabled;
+  uint8_t spare[2];
+} DpmClocks_t;
+
+
+// Throttler Status Bitmask
+#define THROTTLER_STATUS_BIT_SPL 0
+#define THROTTLER_STATUS_BIT_FPPT 1
+#define THROTTLER_STATUS_BIT_SPPT 2
+#define THROTTLER_STATUS_BIT_SPPT_APU 3
+#define THROTTLER_STATUS_BIT_THM_CORE 4
+#define THROTTLER_STATUS_BIT_THM_GFX 5
+#define THROTTLER_STATUS_BIT_THM_SOC 6
+#define THROTTLER_STATUS_BIT_TDC_VDD 7
+#define THROTTLER_STATUS_BIT_TDC_SOC 8
+#define THROTTLER_STATUS_BIT_TDC_GFX 9
+#define THROTTLER_STATUS_BIT_TDC_CVIP 10
+
+typedef struct {
+  uint16_t GfxclkFrequency;      //[MHz]
+  uint16_t SocclkFrequency;      //[MHz]
+  uint16_t VclkFrequency;        //[MHz]
+  uint16_t DclkFrequency;        //[MHz]
+  uint16_t MemclkFrequency;      //[MHz]
+  uint16_t spare;
+
+  uint16_t GfxActivity;          //[centi]
+  uint16_t UvdActivity;          //[centi]
+
+  uint16_t Voltage[3];           //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
+  uint16_t Current[3];           //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
+  uint16_t Power[3];             //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
+  uint16_t CurrentSocketPower;   //[mW]
+
+  //3rd party tools in Windows need info in the case of APUs
+  uint16_t CoreFrequency[8];     //[MHz]
+  uint16_t CorePower[8];         //[mW]
+  uint16_t CoreTemperature[8];   //[centi-Celsius]
+  uint16_t L3Frequency[2];       //[MHz]
+  uint16_t L3Temperature[2];     //[centi-Celsius]
+
+  uint16_t GfxTemperature;       //[centi-Celsius]
+  uint16_t SocTemperature;       //[centi-Celsius]
+  uint16_t EdgeTemperature;
+  uint16_t ThrottlerStatus;
+} SmuMetrics_t;
+
+
+// Workload bits
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
+#define WORKLOAD_PPLIB_VIDEO_BIT 2
+#define WORKLOAD_PPLIB_VR_BIT 3
+#define WORKLOAD_PPLIB_COMPUTE_BIT 4
+#define WORKLOAD_PPLIB_CUSTOM_BIT 5
+#define WORKLOAD_PPLIB_COUNT 6
+
+#define TABLE_BIOS_IF            0 // Called by BIOS
+#define TABLE_WATERMARKS         1 // Called by DAL through VBIOS
+#define TABLE_CUSTOM_DPM         2 // Called by Driver
+#define TABLE_SPARE1             3
+#define TABLE_DPMCLOCKS          4 // Called by Driver
+#define TABLE_SPARE2             5 // Called by Tools
+#define TABLE_MODERN_STDBY       6 // Called by Tools for Modern Standby Log
+#define TABLE_SMU_METRICS        7 // Called by Driver
+#define TABLE_COUNT              8
+
+//ISP tile definitions
+typedef enum {
+  TILE_ISPX = 0, // ISPX
+  TILE_ISPM,     // ISPM
+  TILE_ISPC,  // ISPCORE
+  TILE_ISPPRE,   // ISPPRE
+  TILE_ISPPOST,  // ISPPOST
+  TILE_MAX
+} TILE_NUM_e;
+
+// Tile Selection (Based on arguments)
+#define TILE_SEL_ISPX       (1<<(TILE_ISPX))
+#define TILE_SEL_ISPM       (1<<(TILE_ISPM))
+#define TILE_SEL_ISPC       (1<<(TILE_ISPC))
+#define TILE_SEL_ISPPRE     (1<<(TILE_ISPPRE))
+#define TILE_SEL_ISPPOST    (1<<(TILE_ISPPOST))
+
+// Mask for ISP tiles in PGFSM PWR Status Registers
+//Bit[1:0] maps to ISPX, (ISPX)
+//Bit[3:2] maps to ISPM, (ISPM)
+//Bit[5:4] maps to ISPCORE, (ISPCORE)
+//Bit[7:6] maps to ISPPRE, (ISPPRE)
+//Bit[9:8] maps to POST, (ISPPOST
+#define TILE_ISPX_MASK      ((1<<0) | (1<<1))
+#define TILE_ISPM_MASK      ((1<<2) | (1<<3))
+#define TILE_ISPC_MASK      ((1<<4) | (1<<5))
+#define TILE_ISPPRE_MASK    ((1<<6) | (1<<7))
+#define TILE_ISPPOST_MASK   ((1<<8) | (1<<9))
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/inc/smu74_discrete.h b/drivers/gpu/drm/amd/pm/inc/smu74_discrete.h
index 899d6d8108c2..350889e408d2 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu74_discrete.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu74_discrete.h
@@ -271,7 +271,8 @@ struct SMU74_Discrete_DpmTable {
 
 	uint8_t                             VRHotLevel;
 	uint8_t                             LdoRefSel;
-	uint8_t                             Reserved1[2];
+	uint8_t                             SharedRails;
+	uint8_t                             Reserved1;
 	uint16_t                            FanStartTemperature;
 	uint16_t                            FanStopTemperature;
 	uint16_t                            MaxVoltage;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu7_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu7_ppsmc.h
index 6e19f4c7cf8f..a0a38b8a4b1b 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu7_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu7_ppsmc.h
@@ -394,6 +394,7 @@ typedef uint16_t PPSMC_Result;
 
 #define PPSMC_MSG_SetGpuPllDfsForSclk         ((uint16_t) 0x300)
 #define PPSMC_MSG_Didt_Block_Function		  ((uint16_t) 0x301)
+#define PPSMC_MSG_EnableZeroRpm               ((uint16_t) 0x302)
 
 #define PPSMC_MSG_SetVBITimeout               ((uint16_t) 0x306)
 
@@ -402,6 +403,11 @@ typedef uint16_t PPSMC_Result;
 
 #define PPSMC_MSG_EnableDpmDidt               ((uint16_t) 0x309)
 #define PPSMC_MSG_DisableDpmDidt              ((uint16_t) 0x30A)
+#define PPSMC_MSG_EnableDpmMcBlackout         ((uint16_t) 0x30B)
+#define PPSMC_MSG_DisableDpmMcBlackout        ((uint16_t) 0x30C)
+
+#define PPSMC_MSG_EnableEDCController         ((uint16_t) 0x316)
+#define PPSMC_MSG_DisableEDCController        ((uint16_t) 0x317)
 
 #define PPSMC_MSG_SecureSRBMWrite             ((uint16_t) 0x600)
 #define PPSMC_MSG_SecureSRBMRead              ((uint16_t) 0x601)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index cbf4a58b77d9..4a6d1381df16 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -35,6 +35,7 @@
        __SMU_DUMMY_MAP(EnableSmuFeaturesHigh),        \
        __SMU_DUMMY_MAP(DisableSmuFeaturesLow),        \
        __SMU_DUMMY_MAP(DisableSmuFeaturesHigh),       \
+       __SMU_DUMMY_MAP(GetEnabledSmuFeatures),	      \
        __SMU_DUMMY_MAP(GetEnabledSmuFeaturesLow),     \
        __SMU_DUMMY_MAP(GetEnabledSmuFeaturesHigh),    \
        __SMU_DUMMY_MAP(SetWorkloadMask),              \
@@ -122,7 +123,7 @@
        __SMU_DUMMY_MAP(GetVoltageByDpm),              \
        __SMU_DUMMY_MAP(GetVoltageByDpmOverdrive),     \
        __SMU_DUMMY_MAP(PowerUpVcn0),                  \
-       __SMU_DUMMY_MAP(PowerDownVcn0),               \
+       __SMU_DUMMY_MAP(PowerDownVcn0),                \
        __SMU_DUMMY_MAP(PowerUpVcn1),                  \
        __SMU_DUMMY_MAP(PowerDownVcn1),                \
        __SMU_DUMMY_MAP(PowerUpGfx),                   \
@@ -165,18 +166,49 @@
 	__SMU_DUMMY_MAP(GpuChangeState),              \
 	__SMU_DUMMY_MAP(SetPowerLimitPercentage),     \
 	__SMU_DUMMY_MAP(ForceGfxContentSave),         \
-	__SMU_DUMMY_MAP(EnableTmdp48MHzRefclkPwrDown), \
+	__SMU_DUMMY_MAP(EnableTmdp48MHzRefclkPwrDown),\
 	__SMU_DUMMY_MAP(PowerGateAtHub),              \
 	__SMU_DUMMY_MAP(SetSoftMinJpeg),              \
 	__SMU_DUMMY_MAP(SetHardMinFclkByFreq),        \
-	__SMU_DUMMY_MAP(DFCstateControl), \
-	__SMU_DUMMY_MAP(GmiPwrDnControl), \
-	__SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE), \
+	__SMU_DUMMY_MAP(DFCstateControl),             \
+	__SMU_DUMMY_MAP(GmiPwrDnControl),              \
+	__SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE),\
 	__SMU_DUMMY_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE), \
 	__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH), \
 	__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW), \
 	__SMU_DUMMY_MAP(GET_UMC_FW_WA), \
 	__SMU_DUMMY_MAP(Mode1Reset), \
+	__SMU_DUMMY_MAP(Spare),                          \
+	__SMU_DUMMY_MAP(SetHardMinIspiclkByFreq),        \
+	__SMU_DUMMY_MAP(SetHardMinIspxclkByFreq),        \
+	__SMU_DUMMY_MAP(SetSoftMinSocclkByFreq),         \
+	__SMU_DUMMY_MAP(PowerUpCvip),                    \
+	__SMU_DUMMY_MAP(PowerDownCvip),                  \
+       __SMU_DUMMY_MAP(EnableGfxOff),                   \
+       __SMU_DUMMY_MAP(SetSoftMinGfxclk),               \
+       __SMU_DUMMY_MAP(SetSoftMinFclk),                 \
+       __SMU_DUMMY_MAP(GetThermalLimit),                \
+       __SMU_DUMMY_MAP(GetCurrentTemperature),          \
+       __SMU_DUMMY_MAP(GetCurrentPower),                \
+       __SMU_DUMMY_MAP(GetCurrentVoltage),              \
+       __SMU_DUMMY_MAP(GetCurrentCurrent),              \
+       __SMU_DUMMY_MAP(GetAverageCpuActivity),          \
+       __SMU_DUMMY_MAP(GetAverageGfxActivity),          \
+       __SMU_DUMMY_MAP(GetAveragePower),                \
+       __SMU_DUMMY_MAP(GetAverageTemperature),          \
+       __SMU_DUMMY_MAP(SetAveragePowerTimeConstant),        \
+       __SMU_DUMMY_MAP(SetAverageActivityTimeConstant),     \
+       __SMU_DUMMY_MAP(SetAverageTemperatureTimeConstant),  \
+       __SMU_DUMMY_MAP(SetMitigationEndHysteresis),         \
+       __SMU_DUMMY_MAP(GetCurrentFreq),                     \
+       __SMU_DUMMY_MAP(SetReducedPptLimit),                 \
+       __SMU_DUMMY_MAP(SetReducedThermalLimit),             \
+       __SMU_DUMMY_MAP(DramLogSetDramAddr),                 \
+       __SMU_DUMMY_MAP(StartDramLogging),                   \
+       __SMU_DUMMY_MAP(StopDramLogging),                    \
+       __SMU_DUMMY_MAP(SetSoftMinCclk),                     \
+       __SMU_DUMMY_MAP(SetSoftMaxCclk),                     \
+	__SMU_DUMMY_MAP(SetGpoFeaturePMask),             \
 
 #undef __SMU_DUMMY_MAP
 #define __SMU_DUMMY_MAP(type)	SMU_MSG_##type
@@ -266,7 +298,37 @@ enum smu_clk_type {
        __SMU_DUMMY_MAP(ATHUB_PG),                      	\
        __SMU_DUMMY_MAP(APCC_DFLL),                     	\
        __SMU_DUMMY_MAP(DPM_GFX_GPO),                    \
-       __SMU_DUMMY_MAP(WAFL_CG),
+       __SMU_DUMMY_MAP(WAFL_CG),                        \
+       __SMU_DUMMY_MAP(CCLK_DPM),                     	\
+       __SMU_DUMMY_MAP(FAN_CONTROLLER),                 \
+       __SMU_DUMMY_MAP(VCN_DPM),                     	\
+       __SMU_DUMMY_MAP(LCLK_DPM),                     	\
+       __SMU_DUMMY_MAP(SHUBCLK_DPM),                    \
+       __SMU_DUMMY_MAP(DCFCLK_DPM),                     \
+       __SMU_DUMMY_MAP(DS_DCFCLK),                     	\
+       __SMU_DUMMY_MAP(S0I2),                     	\
+       __SMU_DUMMY_MAP(SMU_LOW_POWER),                  \
+       __SMU_DUMMY_MAP(GFX_DEM),                        \
+       __SMU_DUMMY_MAP(PSI),                     	\
+       __SMU_DUMMY_MAP(PROCHOT),                        \
+       __SMU_DUMMY_MAP(CPUOFF),                     	\
+       __SMU_DUMMY_MAP(STAPM),                          \
+       __SMU_DUMMY_MAP(S0I3),                     	\
+       __SMU_DUMMY_MAP(DF_CSTATES),                     \
+       __SMU_DUMMY_MAP(PERF_LIMIT),                     \
+       __SMU_DUMMY_MAP(CORE_DLDO),                     	\
+       __SMU_DUMMY_MAP(RSMU_LOW_POWER),                 \
+       __SMU_DUMMY_MAP(SMN_LOW_POWER),                  \
+       __SMU_DUMMY_MAP(THM_LOW_POWER),                  \
+       __SMU_DUMMY_MAP(SMUIO_LOW_POWER),                \
+       __SMU_DUMMY_MAP(MP1_LOW_POWER),                  \
+       __SMU_DUMMY_MAP(DS_VCN),                         \
+       __SMU_DUMMY_MAP(CPPC),                           \
+       __SMU_DUMMY_MAP(OS_CSTATES),                     \
+       __SMU_DUMMY_MAP(ISP_DPM),                        \
+       __SMU_DUMMY_MAP(A55_DPM),                        \
+       __SMU_DUMMY_MAP(CVIP_DSP_DPM),                   \
+       __SMU_DUMMY_MAP(MSMU_LOW_POWER),
 
 #undef __SMU_DUMMY_MAP
 #define __SMU_DUMMY_MAP(feature)	SMU_FEATURE_##feature##_BIT
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 2d1c3babaa3a..dc06459af91c 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -30,8 +30,10 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36
 #define SMU11_DRIVER_IF_VERSION_NV12 0x36
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3A
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
+#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02
+#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xB
 
 /* MP Apertures */
 #define MP0_Public			0x03800000
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
new file mode 100644
index 000000000000..99a406984135
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SMU_V11_5_0_PMFW_H__
+#define __SMU_V11_5_0_PMFW_H__
+
+#include "smu11_driver_if_vangogh.h"
+
+#pragma pack(push, 1)
+
+#define ENABLE_DEBUG_FEATURES
+
+// Feature Control Defines
+#define FEATURE_CCLK_DPM_BIT           0
+#define FEATURE_FAN_CONTROLLER_BIT     1
+#define FEATURE_DATA_CALCULATION_BIT   2
+#define FEATURE_PPT_BIT                3
+#define FEATURE_TDC_BIT                4
+#define FEATURE_THERMAL_BIT            5
+#define FEATURE_FIT_BIT                6
+#define FEATURE_EDC_BIT                7
+#define FEATURE_PLL_POWER_DOWN_BIT     8
+#define FEATURE_ULV_BIT                9
+#define FEATURE_VDDOFF_BIT            10
+#define FEATURE_VCN_DPM_BIT           11
+#define FEATURE_CSTATE_BOOST_BIT      12
+#define FEATURE_FCLK_DPM_BIT          13
+#define FEATURE_SOCCLK_DPM_BIT        14
+#define FEATURE_MP0CLK_DPM_BIT        15
+#define FEATURE_LCLK_DPM_BIT          16
+#define FEATURE_SHUBCLK_DPM_BIT       17
+#define FEATURE_DCFCLK_DPM_BIT        18
+#define FEATURE_GFX_DPM_BIT           19
+#define FEATURE_DS_GFXCLK_BIT         20
+#define FEATURE_DS_SOCCLK_BIT         21
+#define FEATURE_DS_LCLK_BIT           22
+#define FEATURE_DS_DCFCLK_BIT         23
+#define FEATURE_DS_SHUBCLK_BIT        24
+#define FEATURE_GFX_TEMP_VMIN_BIT     25
+#define FEATURE_S0I2_BIT              26
+#define FEATURE_WHISPER_MODE_BIT      27
+#define FEATURE_DS_FCLK_BIT           28
+#define FEATURE_DS_SMNCLK_BIT         29
+#define FEATURE_DS_MP1CLK_BIT         30
+#define FEATURE_DS_MP0CLK_BIT         31
+#define FEATURE_SMU_LOW_POWER_BIT     32
+#define FEATURE_FUSE_PG_BIT           33
+#define FEATURE_GFX_DEM_BIT           34
+#define FEATURE_PSI_BIT               35
+#define FEATURE_PROCHOT_BIT           36
+#define FEATURE_CPUOFF_BIT            37
+#define FEATURE_STAPM_BIT             38
+#define FEATURE_S0I3_BIT              39
+#define FEATURE_DF_CSTATES_BIT        40
+#define FEATURE_PERF_LIMIT_BIT        41
+#define FEATURE_CORE_DLDO_BIT         42
+#define FEATURE_RSMU_LOW_POWER_BIT    43
+#define FEATURE_SMN_LOW_POWER_BIT     44
+#define FEATURE_THM_LOW_POWER_BIT     45
+#define FEATURE_SMUIO_LOW_POWER_BIT   46
+#define FEATURE_MP1_LOW_POWER_BIT     47
+#define FEATURE_DS_VCN_BIT            48
+#define FEATURE_CPPC_BIT              49
+#define FEATURE_OS_CSTATES_BIT        50
+#define FEATURE_ISP_DPM_BIT           51
+#define FEATURE_A55_DPM_BIT           52
+#define FEATURE_CVIP_DSP_DPM_BIT      53
+#define FEATURE_MSMU_LOW_POWER_BIT    54
+#define FEATURE_SOC_VOLTAGE_MON_BIT   55
+#define FEATURE_ATHUB_PG_BIT          56
+#define FEATURE_ECO_DEEPCSTATE_BIT    57
+#define FEATURE_CC6_BIT               58
+#define NUM_FEATURES                  59
+
+typedef struct {
+  // MP1_EXT_SCRATCH0
+  uint32_t DpmHandlerID         : 8;
+  uint32_t ActivityMonitorID    : 8;
+  uint32_t DpmTimerID           : 8;
+  uint32_t spare0               : 8;
+  // MP1_EXT_SCRATCH1
+  uint32_t GfxStatus            : 2;
+  uint32_t GfxoffStatus         : 8;
+  uint32_t CpuOff               : 1;
+  uint32_t VddOff               : 1;
+  uint32_t InUlv                : 1;
+  uint32_t InS0i2               : 2;
+  uint32_t InWhisperMode        : 1;
+  uint32_t spare1               : 16;
+  // MP1_EXT_SCRATCH2
+  uint32_t P2JobHandler			: 32;
+  // MP1_EXT_SCRATCH3
+//  uint32_t spare2               : 32;
+  // MP1_EXT_SCRATCH4:6 are used by Kernel
+} FwStatus_t;
+
+
+#pragma pack(pop)
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
new file mode 100644
index 000000000000..1ada0eb64663
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU_11_5_0_PPSMC_H
+#define SMU_11_5_0_PPSMC_H
+
+// SMU Response Codes:
+#define PPSMC_Result_OK 0x1
+#define PPSMC_Result_Failed 0xFF
+#define PPSMC_Result_UnknownCmd 0xFE
+#define PPSMC_Result_CmdRejectedPrereq 0xFD
+#define PPSMC_Result_CmdRejectedBusy 0xFC
+
+// Message Definitions:
+#define PPSMC_MSG_TestMessage                          0x1
+#define PPSMC_MSG_GetSmuVersion                        0x2
+#define PPSMC_MSG_GetDriverIfVersion                   0x3
+#define PPSMC_MSG_EnableGfxOff                         0x4
+#define PPSMC_MSG_DisableGfxOff                        0x5
+#define PPSMC_MSG_PowerDownIspByTile                   0x6 // ISP is power gated by default
+#define PPSMC_MSG_PowerUpIspByTile                     0x7
+#define PPSMC_MSG_PowerDownVcn                         0x8 // VCN is power gated by default
+#define PPSMC_MSG_PowerUpVcn                           0x9
+#define PPSMC_MSG_spare                                0xA
+#define PPSMC_MSG_SetHardMinVcn                        0xB // For wireless display
+#define PPSMC_MSG_SetSoftMinGfxclk                     0xC //Sets SoftMin for GFXCLK. Arg is in MHz
+#define PPSMC_MSG_ActiveProcessNotify                  0xD
+#define PPSMC_MSG_SetHardMinIspiclkByFreq              0xE
+#define PPSMC_MSG_SetHardMinIspxclkByFreq              0xF
+#define PPSMC_MSG_SetDriverDramAddrHigh                0x10
+#define PPSMC_MSG_SetDriverDramAddrLow                 0x11
+#define PPSMC_MSG_TransferTableSmu2Dram                0x12
+#define PPSMC_MSG_TransferTableDram2Smu                0x13
+#define PPSMC_MSG_GfxDeviceDriverReset                 0x14 //mode 2 reset during TDR
+#define PPSMC_MSG_GetEnabledSmuFeatures                0x15
+#define PPSMC_MSG_spare1                               0x16
+#define PPSMC_MSG_SetHardMinSocclkByFreq               0x17
+#define PPSMC_MSG_SetSoftMinFclk                       0x18 //Used to be PPSMC_MSG_SetMinVideoFclkFreq
+#define PPSMC_MSG_SetSoftMinVcn                        0x19
+#define PPSMC_MSG_EnablePostCode                       0x1A
+#define PPSMC_MSG_GetGfxclkFrequency                   0x1B
+#define PPSMC_MSG_GetFclkFrequency                     0x1C
+#define PPSMC_MSG_AllowGfxOff                          0x1D
+#define PPSMC_MSG_DisallowGfxOff                       0x1E
+#define PPSMC_MSG_SetSoftMaxGfxClk                     0x1F
+#define PPSMC_MSG_SetHardMinGfxClk                     0x20
+#define PPSMC_MSG_SetSoftMaxSocclkByFreq               0x21
+#define PPSMC_MSG_SetSoftMaxFclkByFreq                 0x22
+#define PPSMC_MSG_SetSoftMaxVcn                        0x23
+#define PPSMC_MSG_spare2                               0x24
+#define PPSMC_MSG_SetPowerLimitPercentage              0x25
+#define PPSMC_MSG_PowerDownJpeg                        0x26
+#define PPSMC_MSG_PowerUpJpeg                          0x27
+#define PPSMC_MSG_SetHardMinFclkByFreq                 0x28
+#define PPSMC_MSG_SetSoftMinSocclkByFreq               0x29
+#define PPSMC_MSG_PowerUpCvip                          0x2A
+#define PPSMC_MSG_PowerDownCvip                        0x2B
+#define PPSMC_MSG_GetPptLimit                          0x2C
+#define PPSMC_MSG_GetThermalLimit                      0x2D
+#define PPSMC_MSG_GetCurrentTemperature                0x2E
+#define PPSMC_MSG_GetCurrentPower                      0x2F
+#define PPSMC_MSG_GetCurrentVoltage                    0x30
+#define PPSMC_MSG_GetCurrentCurrent                    0x31
+#define PPSMC_MSG_GetAverageCpuActivity                0x32
+#define PPSMC_MSG_GetAverageGfxActivity                0x33
+#define PPSMC_MSG_GetAveragePower                      0x34
+#define PPSMC_MSG_GetAverageTemperature                0x35
+#define PPSMC_MSG_SetAveragePowerTimeConstant          0x36
+#define PPSMC_MSG_SetAverageActivityTimeConstant       0x37
+#define PPSMC_MSG_SetAverageTemperatureTimeConstant    0x38
+#define PPSMC_MSG_SetMitigationEndHysteresis           0x39
+#define PPSMC_MSG_GetCurrentFreq                       0x3A
+#define PPSMC_MSG_SetReducedPptLimit                   0x3B
+#define PPSMC_MSG_SetReducedThermalLimit               0x3C
+#define PPSMC_MSG_DramLogSetDramAddr                   0x3D
+#define PPSMC_MSG_StartDramLogging                     0x3E
+#define PPSMC_MSG_StopDramLogging                      0x3F
+#define PPSMC_MSG_SetSoftMinCclk                       0x40
+#define PPSMC_MSG_SetSoftMaxCclk                       0x41
+#define PPSMC_Message_Count                            0x42
+
+//Argument for  PPSMC_MSG_GpuChangeState
+enum {
+  MODE1_RESET = 1,
+  MODE2_RESET = 2
+};
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/inc/smumgr.h b/drivers/gpu/drm/amd/pm/inc/smumgr.h
index ad100b533d04..5f46f1a4f38e 100644
--- a/drivers/gpu/drm/amd/pm/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/pm/inc/smumgr.h
@@ -113,4 +113,6 @@ extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_settin
 
 extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);
 
+extern int smum_stop_smc(struct pp_hwmgr *hwmgr);
+
 #endif
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
index 3be40114e63d..45f608838f6e 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ci_baco.c
@@ -142,12 +142,12 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
 	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_BCLK_OFF_MASK,           BACO_CNTL__BACO_BCLK_OFF__SHIFT, 0, 0x00 },
 	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_POWER_OFF_MASK,          BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0x00 },
 	{ CMD_DELAY_MS, 0, 0, 0, 20, 0 },
-	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x20 },
+	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_BF_MASK, 0, 0xffffffff, 0x200 },
 	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ISO_DIS_MASK, BACO_CNTL__BACO_ISO_DIS__SHIFT, 0, 0x01 },
-	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c },
+	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__PWRGOOD_MASK, 0, 5, 0x1c00 },
 	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_ANA_ISO_DIS_MASK, BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT, 0, 0x01 },
 	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_RESET_EN_MASK, BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0x00 },
-	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x10 },
+	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK, 0, 5, 0x100 },
 	{ CMD_READMODIFYWRITE, mmBACO_CNTL, BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 0x00 },
 	{ CMD_WAITFOR, mmBACO_CNTL, BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0x00 }
 };
@@ -155,6 +155,7 @@ static const struct baco_cmd_entry exit_baco_tbl[] =
 static const struct baco_cmd_entry clean_baco_tbl[] =
 {
 	{ CMD_WRITE, mmBIOS_SCRATCH_6, 0, 0, 0, 0 },
+	{ CMD_WRITE, mmBIOS_SCRATCH_7, 0, 0, 0, 0 },
 	{ CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
 };
 
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c
index f48fdc7f0382..739e215ec8b7 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c
@@ -479,11 +479,17 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 						PHM_PlatformCaps_RegulatorHot);
 
 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+			PHM_PlatformCaps_MemorySpreadSpectrumSupport);
+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+			PHM_PlatformCaps_EngineSpreadSpectrumSupport);
+
+	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 					PHM_PlatformCaps_AutomaticDCTransition);
 
-	if (hwmgr->chip_id != CHIP_POLARIS10)
+	if (((hwmgr->chip_id == CHIP_POLARIS11) && !hwmgr->is_kicker) ||
+	    (hwmgr->chip_id == CHIP_POLARIS12))
 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-					PHM_PlatformCaps_SPLLShutdownSupport);
+				PHM_PlatformCaps_SPLLShutdownSupport);
 
 	if (hwmgr->chip_id != CHIP_POLARIS11) {
 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h
index c0193e09d58a..729615aff126 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr_ppt.h
@@ -48,7 +48,7 @@ typedef struct phm_ppt_v1_clock_voltage_dependency_record phm_ppt_v1_clock_volta
 
 struct phm_ppt_v1_clock_voltage_dependency_table {
 	uint32_t count;                                            /* Number of entries. */
-	phm_ppt_v1_clock_voltage_dependency_record entries[1];     /* Dynamically allocate count entries. */
+	phm_ppt_v1_clock_voltage_dependency_record entries[];	   /* Dynamically allocate count entries. */
 };
 
 typedef struct phm_ppt_v1_clock_voltage_dependency_table phm_ppt_v1_clock_voltage_dependency_table;
@@ -71,7 +71,7 @@ typedef struct phm_ppt_v1_mm_clock_voltage_dependency_record phm_ppt_v1_mm_clock
 
 struct phm_ppt_v1_mm_clock_voltage_dependency_table {
 	uint32_t count;													/* Number of entries. */
-	phm_ppt_v1_mm_clock_voltage_dependency_record entries[1];		/* Dynamically allocate count entries. */
+	phm_ppt_v1_mm_clock_voltage_dependency_record entries[];		/* Dynamically allocate count entries. */
 };
 typedef struct phm_ppt_v1_mm_clock_voltage_dependency_table phm_ppt_v1_mm_clock_voltage_dependency_table;
 
@@ -86,7 +86,7 @@ typedef struct phm_ppt_v1_voltage_lookup_record phm_ppt_v1_voltage_lookup_record
 
 struct phm_ppt_v1_voltage_lookup_table {
 	uint32_t count;
-	phm_ppt_v1_voltage_lookup_record entries[1];    /* Dynamically allocate count entries. */
+	phm_ppt_v1_voltage_lookup_record entries[];    /* Dynamically allocate count entries. */
 };
 typedef struct phm_ppt_v1_voltage_lookup_table phm_ppt_v1_voltage_lookup_table;
 
@@ -103,7 +103,7 @@ typedef struct phm_ppt_v1_pcie_record phm_ppt_v1_pcie_record;
 
 struct phm_ppt_v1_pcie_table {
 	uint32_t count;                                            /* Number of entries. */
-	phm_ppt_v1_pcie_record entries[1];                         /* Dynamically allocate count entries. */
+	phm_ppt_v1_pcie_record entries[];			   /* Dynamically allocate count entries. */
 };
 typedef struct phm_ppt_v1_pcie_table phm_ppt_v1_pcie_table;
 
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
index 01dc46dc9c8a..c2fee6796bd9 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
@@ -166,6 +166,43 @@ int atomctrl_initialize_mc_reg_table(
 	return result;
 }
 
+int atomctrl_initialize_mc_reg_table_v2_2(
+		struct pp_hwmgr *hwmgr,
+		uint8_t module_index,
+		pp_atomctrl_mc_reg_table *table)
+{
+	ATOM_VRAM_INFO_HEADER_V2_2 *vram_info;
+	ATOM_INIT_REG_BLOCK *reg_block;
+	int result = 0;
+	u8 frev, crev;
+	u16 size;
+
+	vram_info = (ATOM_VRAM_INFO_HEADER_V2_2 *)
+		smu_atom_get_data_table(hwmgr->adev,
+				GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev);
+
+	if (module_index >= vram_info->ucNumOfVRAMModule) {
+		pr_err("Invalid VramInfo table.");
+		result = -1;
+	} else if (vram_info->sHeader.ucTableFormatRevision < 2) {
+		pr_err("Invalid VramInfo table.");
+		result = -1;
+	}
+
+	if (0 == result) {
+		reg_block = (ATOM_INIT_REG_BLOCK *)
+			((uint8_t *)vram_info + le16_to_cpu(vram_info->usMemClkPatchTblOffset));
+		result = atomctrl_set_mc_reg_address_table(reg_block, table);
+	}
+
+	if (0 == result) {
+		result = atomctrl_retrieve_ac_timing(module_index,
+					reg_block, table);
+	}
+
+	return result;
+}
+
 /**
  * Set DRAM timings based on engine clock and memory clock.
  */
@@ -1208,6 +1245,17 @@ static ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
 	return table;
 }
 
+bool atomctrl_is_asic_internal_ss_supported(struct pp_hwmgr *hwmgr)
+{
+	ATOM_ASIC_INTERNAL_SS_INFO *table =
+		asic_internal_ss_get_ss_table(hwmgr->adev);
+
+	if (table)
+		return true;
+	else
+		return false;
+}
+
 /**
  * Get the asic internal spread spectrum assignment
  */
@@ -1295,12 +1343,18 @@ int atomctrl_get_engine_clock_spread_spectrum(
 }
 
 int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
-		uint16_t end_index, uint32_t mask, uint32_t *efuse)
+		uint16_t end_index, uint32_t *efuse)
 {
 	struct amdgpu_device *adev = hwmgr->adev;
+	uint32_t mask;
 	int result;
 	READ_EFUSE_VALUE_PARAMETER efuse_param;
 
+	if ((end_index - start_index)  == 31)
+		mask = 0xFFFFFFFF;
+	else
+		mask = (1 << ((end_index - start_index) + 1)) - 1;
+
 	efuse_param.sEfuse.usEfuseIndex = cpu_to_le16((start_index / 32) * 4);
 	efuse_param.sEfuse.ucBitShift = (uint8_t)
 			(start_index - ((start_index / 32) * 32));
@@ -1384,6 +1438,20 @@ int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctr
 	return 0;
 }
 
+int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t *shared_rail)
+{
+	ATOM_SMU_INFO_V2_1 *psmu_info =
+		(ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev,
+			GetIndexIntoMasterTable(DATA, SMU_Info),
+			NULL, NULL, NULL);
+	if (!psmu_info)
+		return -1;
+
+	*shared_rail = psmu_info->ucSharePowerSource;
+
+	return 0;
+}
+
 int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
 				  struct pp_atom_ctrl__avfs_parameters *param)
 {
@@ -1560,3 +1628,56 @@ void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
 	*max_vddc = 0;
 	*min_vddc = 0;
 }
+
+int atomctrl_get_edc_hilo_leakage_offset_table(struct pp_hwmgr *hwmgr,
+					       AtomCtrl_HiLoLeakageOffsetTable *table)
+{
+	ATOM_GFX_INFO_V2_3 *gfxinfo = smu_atom_get_data_table(hwmgr->adev,
+					GetIndexIntoMasterTable(DATA, GFX_Info),
+					NULL, NULL, NULL);
+	if (!gfxinfo)
+		return -ENOENT;
+
+	table->usHiLoLeakageThreshold = gfxinfo->usHiLoLeakageThreshold;
+	table->usEdcDidtLoDpm7TableOffset = gfxinfo->usEdcDidtLoDpm7TableOffset;
+	table->usEdcDidtHiDpm7TableOffset = gfxinfo->usEdcDidtHiDpm7TableOffset;
+
+	return 0;
+}
+
+static AtomCtrl_EDCLeakgeTable *get_edc_leakage_table(struct pp_hwmgr *hwmgr,
+						      uint16_t offset)
+{
+	void *table_address;
+	char *temp;
+
+	table_address = smu_atom_get_data_table(hwmgr->adev,
+			GetIndexIntoMasterTable(DATA, GFX_Info),
+			NULL, NULL, NULL);
+	if (!table_address)
+		return NULL;
+
+	temp = (char *)table_address;
+	table_address += offset;
+
+	return (AtomCtrl_EDCLeakgeTable *)temp;
+}
+
+int atomctrl_get_edc_leakage_table(struct pp_hwmgr *hwmgr,
+				   AtomCtrl_EDCLeakgeTable *table,
+				   uint16_t offset)
+{
+	uint32_t length, i;
+	AtomCtrl_EDCLeakgeTable *leakage_table =
+		get_edc_leakage_table(hwmgr, offset);
+
+	if (!leakage_table)
+		return -ENOENT;
+
+	length = sizeof(leakage_table->DIDT_REG) /
+		 sizeof(leakage_table->DIDT_REG[0]);
+	for (i = 0; i < length; i++)
+		table->DIDT_REG[i] = leakage_table->DIDT_REG[i];
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
index 76ed2e413594..b3103bd4be42 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h
@@ -278,13 +278,30 @@ struct pp_atom_ctrl__avfs_parameters {
 	uint8_t  ucReserved;
 };
 
+struct _AtomCtrl_HiLoLeakageOffsetTable
+{
+    USHORT usHiLoLeakageThreshold;
+    USHORT usEdcDidtLoDpm7TableOffset;
+    USHORT usEdcDidtHiDpm7TableOffset;
+};
+typedef struct _AtomCtrl_HiLoLeakageOffsetTable AtomCtrl_HiLoLeakageOffsetTable;
+
+struct _AtomCtrl_EDCLeakgeTable
+{
+    ULONG DIDT_REG[24];
+};
+typedef struct _AtomCtrl_EDCLeakgeTable AtomCtrl_EDCLeakgeTable;
+
 extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
 extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
 extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage);
 extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
+
+bool atomctrl_is_asic_internal_ss_supported(struct pp_hwmgr *hwmgr);
 extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
 extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
 extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
+extern int atomctrl_initialize_mc_reg_table_v2_2(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
 extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
 extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
@@ -300,7 +317,7 @@ extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
 						 uint32_t clock_value,
 						 pp_atomctrl_clock_dividers_kong *dividers);
 extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
-		uint16_t end_index, uint32_t mask, uint32_t *efuse);
+		uint16_t end_index, uint32_t *efuse);
 extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
 		uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
 extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
@@ -324,5 +341,14 @@ extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *
 
 extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
 							uint32_t *min_vddc);
+
+extern int atomctrl_get_edc_hilo_leakage_offset_table(struct pp_hwmgr *hwmgr,
+						      AtomCtrl_HiLoLeakageOffsetTable *table);
+
+extern int atomctrl_get_edc_leakage_table(struct pp_hwmgr *hwmgr,
+					  AtomCtrl_EDCLeakgeTable *table,
+					  uint16_t offset);
+
+extern int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t *shared_rail);
 #endif
 
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h
index 1e870f58dd12..b0ac4d121adc 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h
@@ -315,6 +315,36 @@ typedef struct _ATOM_Fiji_Fan_Table {
 	USHORT  usReserved;
 } ATOM_Fiji_Fan_Table;
 
+typedef struct _ATOM_Polaris_Fan_Table {
+	UCHAR   ucRevId;						 /* Change this if the table format changes or version changes so that the other fields are not the same. */
+	UCHAR   ucTHyst;						 /* Temperature hysteresis. Integer. */
+	USHORT  usTMin; 						 /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
+	USHORT  usTMed; 						 /* The middle temperature where we change slopes. */
+	USHORT  usTHigh;						 /* The high point above TMed for adjusting the second slope. */
+	USHORT  usPWMMin;						 /* The minimum PWM value in percent (0.01% increments). */
+	USHORT  usPWMMed;						 /* The PWM value (in percent) at TMed. */
+	USHORT  usPWMHigh;						 /* The PWM value at THigh. */
+	USHORT  usTMax; 						 /* The max temperature */
+	UCHAR   ucFanControlMode;				  /* Legacy or Fuzzy Fan mode */
+	USHORT  usFanPWMMax;					  /* Maximum allowed fan power in percent */
+	USHORT  usFanOutputSensitivity;		  /* Sensitivity of fan reaction to temepature changes */
+	USHORT  usFanRPMMax;					  /* The default value in RPM */
+	ULONG  ulMinFanSCLKAcousticLimit;		/* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
+	UCHAR   ucTargetTemperature;			 /* Advanced fan controller target temperature. */
+	UCHAR   ucMinimumPWMLimit; 			  /* The minimum PWM that the advanced fan controller can set.	This should be set to the highest PWM that will run the fan at its lowest RPM. */
+	USHORT  usFanGainEdge;
+	USHORT  usFanGainHotspot;
+	USHORT  usFanGainLiquid;
+	USHORT  usFanGainVrVddc;
+	USHORT  usFanGainVrMvdd;
+	USHORT  usFanGainPlx;
+	USHORT  usFanGainHbm;
+	UCHAR   ucEnableZeroRPM;
+	UCHAR   ucFanStopTemperature;
+	UCHAR   ucFanStartTemperature;
+	USHORT  usReserved;
+} ATOM_Polaris_Fan_Table;
+
 typedef struct _ATOM_Tonga_Thermal_Controller {
 	UCHAR ucRevId;
 	UCHAR ucType;		   /* one of ATOM_TONGA_PP_THERMALCONTROLLER_* */
@@ -389,6 +419,42 @@ typedef struct _ATOM_Fiji_PowerTune_Table {
 	USHORT usReserved;
 } ATOM_Fiji_PowerTune_Table;
 
+typedef struct _ATOM_Polaris_PowerTune_Table
+{
+    UCHAR  ucRevId;
+    USHORT usTDP;
+    USHORT usConfigurableTDP;
+    USHORT usTDC;
+    USHORT usBatteryPowerLimit;
+    USHORT usSmallPowerLimit;
+    USHORT usLowCACLeakage;
+    USHORT usHighCACLeakage;
+    USHORT usMaximumPowerDeliveryLimit;
+    USHORT usTjMax;  // For Fiji, this is also usTemperatureLimitEdge;
+    USHORT usPowerTuneDataSetID;
+    USHORT usEDCLimit;
+    USHORT usSoftwareShutdownTemp;
+    USHORT usClockStretchAmount;
+    USHORT usTemperatureLimitHotspot;  //The following are added for Fiji
+    USHORT usTemperatureLimitLiquid1;
+    USHORT usTemperatureLimitLiquid2;
+    USHORT usTemperatureLimitVrVddc;
+    USHORT usTemperatureLimitVrMvdd;
+    USHORT usTemperatureLimitPlx;
+    UCHAR  ucLiquid1_I2C_address;  //Liquid
+    UCHAR  ucLiquid2_I2C_address;
+    UCHAR  ucLiquid_I2C_Line;
+    UCHAR  ucVr_I2C_address;  //VR
+    UCHAR  ucVr_I2C_Line;
+    UCHAR  ucPlx_I2C_address;  //PLX
+    UCHAR  ucPlx_I2C_Line;
+    USHORT usBoostPowerLimit;
+    UCHAR  ucCKS_LDO_REFSEL;
+    UCHAR  ucHotSpotOnly;
+    UCHAR  ucReserve;
+    USHORT usReserve;
+} ATOM_Polaris_PowerTune_Table;
+
 #define ATOM_PPM_A_A    1
 #define ATOM_PPM_A_I    2
 typedef struct _ATOM_Tonga_PPM_Table {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c
index b760f95e7fa7..801a56502670 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/process_pptables_v1_0.c
@@ -157,7 +157,7 @@ static int get_vddc_lookup_table(
 		uint32_t max_levels
 		)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	phm_ppt_v1_voltage_lookup_table *table;
 	phm_ppt_v1_voltage_lookup_record *record;
 	ATOM_Tonga_Voltage_Lookup_Record *atom_record;
@@ -165,12 +165,8 @@ static int get_vddc_lookup_table(
 	PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries),
 		"Invalid CAC Leakage PowerPlay Table!", return 1);
 
-	table_size = sizeof(uint32_t) +
-		sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels;
-
-	table = kzalloc(table_size, GFP_KERNEL);
-
-	if (NULL == table)
+	table = kzalloc(struct_size(table, entries, max_levels), GFP_KERNEL);
+	if (!table)
 		return -ENOMEM;
 
 	table->count = vddc_lookup_pp_tables->ucNumEntries;
@@ -318,19 +314,16 @@ static int get_valid_clk(
 		phm_ppt_v1_clock_voltage_dependency_table const *clk_volt_pp_table
 		)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	struct phm_clock_array *table;
 	phm_ppt_v1_clock_voltage_dependency_record *dep_record;
 
 	PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count),
 		"Invalid PowerPlay Table!", return -1);
 
-	table_size = sizeof(uint32_t) +
-		sizeof(uint32_t) * clk_volt_pp_table->count;
-
-	table = kzalloc(table_size, GFP_KERNEL);
-
-	if (NULL == table)
+	table = kzalloc(struct_size(table, values, clk_volt_pp_table->count),
+			GFP_KERNEL);
+	if (!table)
 		return -ENOMEM;
 
 	table->count = (uint32_t)clk_volt_pp_table->count;
@@ -370,7 +363,7 @@ static int get_mclk_voltage_dependency_table(
 		ATOM_Tonga_MCLK_Dependency_Table const *mclk_dep_table
 		)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	phm_ppt_v1_clock_voltage_dependency_table *mclk_table;
 	phm_ppt_v1_clock_voltage_dependency_record *mclk_table_record;
 	ATOM_Tonga_MCLK_Dependency_Record *mclk_dep_record;
@@ -378,12 +371,9 @@ static int get_mclk_voltage_dependency_table(
 	PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries),
 		"Invalid PowerPlay Table!", return -1);
 
-	table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
-		* mclk_dep_table->ucNumEntries;
-
-	mclk_table = kzalloc(table_size, GFP_KERNEL);
-
-	if (NULL == mclk_table)
+	mclk_table = kzalloc(struct_size(mclk_table, entries, mclk_dep_table->ucNumEntries),
+			     GFP_KERNEL);
+	if (!mclk_table)
 		return -ENOMEM;
 
 	mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
@@ -413,7 +403,7 @@ static int get_sclk_voltage_dependency_table(
 		PPTable_Generic_SubTable_Header const  *sclk_dep_table
 		)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	phm_ppt_v1_clock_voltage_dependency_table *sclk_table;
 	phm_ppt_v1_clock_voltage_dependency_record *sclk_table_record;
 
@@ -425,12 +415,9 @@ static int get_sclk_voltage_dependency_table(
 		PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries),
 			"Invalid PowerPlay Table!", return -1);
 
-		table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
-			* tonga_table->ucNumEntries;
-
-		sclk_table = kzalloc(table_size, GFP_KERNEL);
-
-		if (NULL == sclk_table)
+		sclk_table = kzalloc(struct_size(sclk_table, entries, tonga_table->ucNumEntries),
+				     GFP_KERNEL);
+		if (!sclk_table)
 			return -ENOMEM;
 
 		sclk_table->count = (uint32_t)tonga_table->ucNumEntries;
@@ -457,12 +444,9 @@ static int get_sclk_voltage_dependency_table(
 		PP_ASSERT_WITH_CODE((0 != polaris_table->ucNumEntries),
 			"Invalid PowerPlay Table!", return -1);
 
-		table_size = sizeof(uint32_t) + sizeof(phm_ppt_v1_clock_voltage_dependency_record)
-			* polaris_table->ucNumEntries;
-
-		sclk_table = kzalloc(table_size, GFP_KERNEL);
-
-		if (NULL == sclk_table)
+		sclk_table = kzalloc(struct_size(sclk_table, entries, polaris_table->ucNumEntries),
+				     GFP_KERNEL);
+		if (!sclk_table)
 			return -ENOMEM;
 
 		sclk_table->count = (uint32_t)polaris_table->ucNumEntries;
@@ -494,7 +478,7 @@ static int get_pcie_table(
 		PPTable_Generic_SubTable_Header const *ptable
 		)
 {
-	uint32_t table_size, i, pcie_count;
+	uint32_t i, pcie_count;
 	phm_ppt_v1_pcie_table *pcie_table;
 	struct phm_ppt_v1_information *pp_table_information =
 		(struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -507,12 +491,10 @@ static int get_pcie_table(
 		PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
 			"Invalid PowerPlay Table!", return -1);
 
-		table_size = sizeof(uint32_t) +
-			sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;
-
-		pcie_table = kzalloc(table_size, GFP_KERNEL);
-
-		if (pcie_table == NULL)
+		pcie_table = kzalloc(struct_size(pcie_table, entries,
+						 atom_pcie_table->ucNumEntries),
+				     GFP_KERNEL);
+		if (!pcie_table)
 			return -ENOMEM;
 
 		/*
@@ -546,12 +528,10 @@ static int get_pcie_table(
 		PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
 			"Invalid PowerPlay Table!", return -1);
 
-		table_size = sizeof(uint32_t) +
-			sizeof(phm_ppt_v1_pcie_record) * atom_pcie_table->ucNumEntries;
-
-		pcie_table = kzalloc(table_size, GFP_KERNEL);
-
-		if (pcie_table == NULL)
+		pcie_table = kzalloc(struct_size(pcie_table, entries,
+						 atom_pcie_table->ucNumEntries),
+				     GFP_KERNEL);
+		if (!pcie_table)
 			return -ENOMEM;
 
 		/*
@@ -633,7 +613,7 @@ static int get_cac_tdp_table(
 			le16_to_cpu(tonga_table->usSoftwareShutdownTemp);
 		tdp_table->usClockStretchAmount =
 			le16_to_cpu(tonga_table->usClockStretchAmount);
-	} else {   /* Fiji and newer */
+	} else if (table->ucRevId < 4) {   /* Fiji and newer */
 		const ATOM_Fiji_PowerTune_Table *fijitable =
 			(ATOM_Fiji_PowerTune_Table *)table;
 		tdp_table->usTDP = le16_to_cpu(fijitable->usTDP);
@@ -677,6 +657,53 @@ static int get_cac_tdp_table(
 		tdp_table->ucVr_I2C_Line = fijitable->ucVr_I2C_Line;
 		tdp_table->ucPlx_I2C_address = fijitable->ucPlx_I2C_address;
 		tdp_table->ucPlx_I2C_Line = fijitable->ucPlx_I2C_Line;
+	} else {
+		const ATOM_Polaris_PowerTune_Table *polaristable =
+			(ATOM_Polaris_PowerTune_Table *)table;
+		tdp_table->usTDP = le16_to_cpu(polaristable->usTDP);
+		tdp_table->usConfigurableTDP = le16_to_cpu(polaristable->usConfigurableTDP);
+		tdp_table->usTDC = le16_to_cpu(polaristable->usTDC);
+		tdp_table->usBatteryPowerLimit = le16_to_cpu(polaristable->usBatteryPowerLimit);
+		tdp_table->usSmallPowerLimit = le16_to_cpu(polaristable->usSmallPowerLimit);
+		tdp_table->usLowCACLeakage = le16_to_cpu(polaristable->usLowCACLeakage);
+		tdp_table->usHighCACLeakage = le16_to_cpu(polaristable->usHighCACLeakage);
+		tdp_table->usMaximumPowerDeliveryLimit =
+			le16_to_cpu(polaristable->usMaximumPowerDeliveryLimit);
+		tdp_table->usDefaultTargetOperatingTemp =
+			le16_to_cpu(polaristable->usTjMax);
+		tdp_table->usTargetOperatingTemp =
+			le16_to_cpu(polaristable->usTjMax); /*Set the initial temp to the same as default */
+		tdp_table->usPowerTuneDataSetID =
+			le16_to_cpu(polaristable->usPowerTuneDataSetID);
+		tdp_table->usSoftwareShutdownTemp =
+			le16_to_cpu(polaristable->usSoftwareShutdownTemp);
+		tdp_table->usClockStretchAmount =
+			le16_to_cpu(polaristable->usClockStretchAmount);
+		tdp_table->usTemperatureLimitHotspot =
+			le16_to_cpu(polaristable->usTemperatureLimitHotspot);
+		tdp_table->usTemperatureLimitLiquid1 =
+			le16_to_cpu(polaristable->usTemperatureLimitLiquid1);
+		tdp_table->usTemperatureLimitLiquid2 =
+			le16_to_cpu(polaristable->usTemperatureLimitLiquid2);
+		tdp_table->usTemperatureLimitVrVddc =
+			le16_to_cpu(polaristable->usTemperatureLimitVrVddc);
+		tdp_table->usTemperatureLimitVrMvdd =
+			le16_to_cpu(polaristable->usTemperatureLimitVrMvdd);
+		tdp_table->usTemperatureLimitPlx =
+			le16_to_cpu(polaristable->usTemperatureLimitPlx);
+		tdp_table->ucLiquid1_I2C_address =
+			polaristable->ucLiquid1_I2C_address;
+		tdp_table->ucLiquid2_I2C_address =
+			polaristable->ucLiquid2_I2C_address;
+		tdp_table->ucLiquid_I2C_Line =
+			polaristable->ucLiquid_I2C_Line;
+		tdp_table->ucVr_I2C_address = polaristable->ucVr_I2C_address;
+		tdp_table->ucVr_I2C_Line = polaristable->ucVr_I2C_Line;
+		tdp_table->ucPlx_I2C_address = polaristable->ucPlx_I2C_address;
+		tdp_table->ucPlx_I2C_Line = polaristable->ucPlx_I2C_Line;
+		tdp_table->usBoostPowerLimit = polaristable->usBoostPowerLimit;
+		tdp_table->ucCKS_LDO_REFSEL = polaristable->ucCKS_LDO_REFSEL;
+		tdp_table->ucHotSpotOnly = polaristable->ucHotSpotOnly;
 	}
 
 	*cac_tdp_table = tdp_table;
@@ -690,19 +717,16 @@ static int get_mm_clock_voltage_table(
 		const ATOM_Tonga_MM_Dependency_Table * mm_dependency_table
 		)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	const ATOM_Tonga_MM_Dependency_Record *mm_dependency_record;
 	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table;
 	phm_ppt_v1_mm_clock_voltage_dependency_record *mm_table_record;
 
 	PP_ASSERT_WITH_CODE((0 != mm_dependency_table->ucNumEntries),
 		"Invalid PowerPlay Table!", return -1);
-	table_size = sizeof(uint32_t) +
-		sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record)
-		* mm_dependency_table->ucNumEntries;
-	mm_table = kzalloc(table_size, GFP_KERNEL);
-
-	if (NULL == mm_table)
+	mm_table = kzalloc(struct_size(mm_table, entries, mm_dependency_table->ucNumEntries),
+			   GFP_KERNEL);
+	if (!mm_table)
 		return -ENOMEM;
 
 	mm_table->count = mm_dependency_table->ucNumEntries;
@@ -972,7 +996,7 @@ static int init_thermal_controller(
 			= tonga_fan_table->ucTargetTemperature;
 		hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
 			= tonga_fan_table->ucMinimumPWMLimit;
-	} else {
+	} else if (fan_table->ucRevId == 8) {
 		const ATOM_Fiji_Fan_Table *fiji_fan_table =
 			(ATOM_Fiji_Fan_Table *)fan_table;
 		hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
@@ -1022,6 +1046,62 @@ static int init_thermal_controller(
 			= le16_to_cpu(fiji_fan_table->usFanGainPlx);
 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm
 			= le16_to_cpu(fiji_fan_table->usFanGainHbm);
+	} else if (fan_table->ucRevId >= 9) {
+		const ATOM_Polaris_Fan_Table *polaris_fan_table =
+			(ATOM_Polaris_Fan_Table *)fan_table;
+		hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
+			= polaris_fan_table->ucTHyst;
+		hwmgr->thermal_controller.advanceFanControlParameters.usTMin
+			= le16_to_cpu(polaris_fan_table->usTMin);
+		hwmgr->thermal_controller.advanceFanControlParameters.usTMed
+			= le16_to_cpu(polaris_fan_table->usTMed);
+		hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
+			= le16_to_cpu(polaris_fan_table->usTHigh);
+		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
+			= le16_to_cpu(polaris_fan_table->usPWMMin);
+		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
+			= le16_to_cpu(polaris_fan_table->usPWMMed);
+		hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
+			= le16_to_cpu(polaris_fan_table->usPWMHigh);
+		hwmgr->thermal_controller.advanceFanControlParameters.usTMax
+			= le16_to_cpu(polaris_fan_table->usTMax);
+		hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
+			= polaris_fan_table->ucFanControlMode;
+		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
+			= le16_to_cpu(polaris_fan_table->usFanPWMMax);
+		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
+			= 4836;
+		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
+			= le16_to_cpu(polaris_fan_table->usFanOutputSensitivity);
+		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
+			= le16_to_cpu(polaris_fan_table->usFanRPMMax);
+		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
+			= (le32_to_cpu(polaris_fan_table->ulMinFanSCLKAcousticLimit) / 100); /* PPTable stores it in 10Khz unit for 2 decimal places.  SMC wants MHz. */
+		hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
+			= polaris_fan_table->ucTargetTemperature;
+		hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
+			= polaris_fan_table->ucMinimumPWMLimit;
+
+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge
+			= le16_to_cpu(polaris_fan_table->usFanGainEdge);
+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot
+			= le16_to_cpu(polaris_fan_table->usFanGainHotspot);
+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid
+			= le16_to_cpu(polaris_fan_table->usFanGainLiquid);
+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc
+			= le16_to_cpu(polaris_fan_table->usFanGainVrVddc);
+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd
+			= le16_to_cpu(polaris_fan_table->usFanGainVrMvdd);
+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx
+			= le16_to_cpu(polaris_fan_table->usFanGainPlx);
+		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm
+			= le16_to_cpu(polaris_fan_table->usFanGainHbm);
+		hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM
+			= le16_to_cpu(polaris_fan_table->ucEnableZeroRPM);
+		hwmgr->thermal_controller.advanceFanControlParameters.ucFanStopTemperature
+			= le16_to_cpu(polaris_fan_table->ucFanStopTemperature);
+		hwmgr->thermal_controller.advanceFanControlParameters.ucFanStartTemperature
+			= le16_to_cpu(polaris_fan_table->ucFanStartTemperature);
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
index 719597c5d27d..48d550d26c6a 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c
@@ -377,14 +377,11 @@ static int get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
 		const ATOM_PPLIB_Clock_Voltage_Dependency_Table *table)
 {
 
-	unsigned long table_size, i;
+	unsigned long i;
 	struct phm_clock_voltage_dependency_table *dep_table;
 
-	table_size = sizeof(unsigned long) +
-		sizeof(struct phm_clock_voltage_dependency_table)
-		* table->ucNumEntries;
-
-	dep_table = kzalloc(table_size, GFP_KERNEL);
+	dep_table = kzalloc(struct_size(dep_table, entries, table->ucNumEntries),
+			    GFP_KERNEL);
 	if (NULL == dep_table)
 		return -ENOMEM;
 
@@ -407,12 +404,11 @@ static int get_valid_clk(struct pp_hwmgr *hwmgr,
 			struct phm_clock_array **ptable,
 			const struct phm_clock_voltage_dependency_table *table)
 {
-	unsigned long table_size, i;
+	unsigned long i;
 	struct phm_clock_array *clock_table;
 
-	table_size = sizeof(unsigned long) + sizeof(unsigned long) * table->count;
-	clock_table = kzalloc(table_size, GFP_KERNEL);
-	if (NULL == clock_table)
+	clock_table = kzalloc(struct_size(clock_table, values, table->count), GFP_KERNEL);
+	if (!clock_table)
 		return -ENOMEM;
 
 	clock_table->count = (unsigned long)table->count;
@@ -1109,15 +1105,12 @@ static int get_uvd_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
 		const ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *table,
 		const UVDClockInfoArray *array)
 {
-	unsigned long table_size, i;
+	unsigned long i;
 	struct phm_uvd_clock_voltage_dependency_table *uvd_table;
 
-	table_size = sizeof(unsigned long) +
-		 sizeof(struct phm_uvd_clock_voltage_dependency_table) *
-		 table->numEntries;
-
-	uvd_table = kzalloc(table_size, GFP_KERNEL);
-	if (NULL == uvd_table)
+	uvd_table = kzalloc(struct_size(uvd_table, entries, table->numEntries),
+			    GFP_KERNEL);
+	if (!uvd_table)
 		return -ENOMEM;
 
 	uvd_table->count = table->numEntries;
@@ -1142,15 +1135,12 @@ static int get_vce_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
 		const ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *table,
 		const VCEClockInfoArray    *array)
 {
-	unsigned long table_size, i;
+	unsigned long i;
 	struct phm_vce_clock_voltage_dependency_table *vce_table = NULL;
 
-	table_size = sizeof(unsigned long) +
-			sizeof(struct phm_vce_clock_voltage_dependency_table)
-			* table->numEntries;
-
-	vce_table = kzalloc(table_size, GFP_KERNEL);
-	if (NULL == vce_table)
+	vce_table = kzalloc(struct_size(vce_table, entries, table->numEntries),
+			    GFP_KERNEL);
+	if (!vce_table)
 		return -ENOMEM;
 
 	vce_table->count = table->numEntries;
@@ -1173,15 +1163,12 @@ static int get_samu_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
 		 struct phm_samu_clock_voltage_dependency_table **ptable,
 		 const ATOM_PPLIB_SAMClk_Voltage_Limit_Table *table)
 {
-	unsigned long table_size, i;
+	unsigned long i;
 	struct phm_samu_clock_voltage_dependency_table *samu_table;
 
-	table_size = sizeof(unsigned long) +
-		sizeof(struct phm_samu_clock_voltage_dependency_table) *
-		table->numEntries;
-
-	samu_table = kzalloc(table_size, GFP_KERNEL);
-	if (NULL == samu_table)
+	samu_table = kzalloc(struct_size(samu_table, entries, table->numEntries),
+			     GFP_KERNEL);
+	if (!samu_table)
 		return -ENOMEM;
 
 	samu_table->count = table->numEntries;
@@ -1201,15 +1188,12 @@ static int get_acp_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
 		struct phm_acp_clock_voltage_dependency_table **ptable,
 		const ATOM_PPLIB_ACPClk_Voltage_Limit_Table *table)
 {
-	unsigned table_size, i;
+	unsigned long i;
 	struct phm_acp_clock_voltage_dependency_table *acp_table;
 
-	table_size = sizeof(unsigned long) +
-		sizeof(struct phm_acp_clock_voltage_dependency_table) *
-		table->numEntries;
-
-	acp_table = kzalloc(table_size, GFP_KERNEL);
-	if (NULL == acp_table)
+	acp_table = kzalloc(struct_size(acp_table, entries, table->numEntries),
+			    GFP_KERNEL);
+	if (!acp_table)
 		return -ENOMEM;
 
 	acp_table->count = (unsigned long)table->numEntries;
@@ -1397,17 +1381,14 @@ static int get_cac_leakage_table(struct pp_hwmgr *hwmgr,
 				const ATOM_PPLIB_CAC_Leakage_Table *table)
 {
 	struct phm_cac_leakage_table  *cac_leakage_table;
-	unsigned long            table_size, i;
+	unsigned long i;
 
-	if (hwmgr == NULL || table == NULL || ptable == NULL)
+	if (!hwmgr || !table || !ptable)
 		return -EINVAL;
 
-	table_size = sizeof(ULONG) +
-		(sizeof(struct phm_cac_leakage_table) * table->ucNumEntries);
-
-	cac_leakage_table = kzalloc(table_size, GFP_KERNEL);
-
-	if (cac_leakage_table == NULL)
+	cac_leakage_table = kzalloc(struct_size(cac_leakage_table, entries, table->ucNumEntries),
+				    GFP_KERNEL);
+	if (!cac_leakage_table)
 		return -ENOMEM;
 
 	cac_leakage_table->count = (ULONG)table->ucNumEntries;
@@ -1540,16 +1521,12 @@ static int init_phase_shedding_table(struct pp_hwmgr *hwmgr,
 				(((unsigned long)powerplay_table4) +
 				le16_to_cpu(powerplay_table4->usVddcPhaseShedLimitsTableOffset));
 			struct phm_phase_shedding_limits_table *table;
-			unsigned long size, i;
-
-
-			size = sizeof(unsigned long) +
-				(sizeof(struct phm_phase_shedding_limits_table) *
-				ptable->ucNumEntries);
+			unsigned long i;
 
-			table = kzalloc(size, GFP_KERNEL);
 
-			if (table == NULL)
+			table = kzalloc(struct_size(table, entries, ptable->ucNumEntries),
+					GFP_KERNEL);
+			if (!table)
 				return -ENOMEM;
 
 			table->count = (unsigned long)ptable->ucNumEntries;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 1e8919b0acdb..53111c6bbcc9 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -49,6 +49,8 @@
 #include "processpptables.h"
 #include "pp_thermal.h"
 #include "smu7_baco.h"
+#include "smu7_smumgr.h"
+#include "polaris10_smumgr.h"
 
 #include "ivsrcid/ivsrcid_vislands30.h"
 
@@ -97,6 +99,9 @@ static struct profile_mode_setting smu7_profiling[7] =
 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT                  0x00000005
 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT               0x00000006
 
+#define STRAP_EVV_REVISION_MSB		2211
+#define STRAP_EVV_REVISION_LSB		2208
+
 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 enum DPM_EVENT_SRC {
 	DPM_EVENT_SRC_ANALOG = 0,
@@ -106,9 +111,66 @@ enum DPM_EVENT_SRC {
 	DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 };
 
+#define ixDIDT_SQ_EDC_CTRL                         0x0013
+#define ixDIDT_SQ_EDC_THRESHOLD                    0x0014
+#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2            0x0015
+#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4            0x0016
+#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6            0x0017
+#define ixDIDT_SQ_EDC_STALL_PATTERN_7              0x0018
+
+#define ixDIDT_TD_EDC_CTRL                         0x0053
+#define ixDIDT_TD_EDC_THRESHOLD                    0x0054
+#define ixDIDT_TD_EDC_STALL_PATTERN_1_2            0x0055
+#define ixDIDT_TD_EDC_STALL_PATTERN_3_4            0x0056
+#define ixDIDT_TD_EDC_STALL_PATTERN_5_6            0x0057
+#define ixDIDT_TD_EDC_STALL_PATTERN_7              0x0058
+
+#define ixDIDT_TCP_EDC_CTRL                        0x0073
+#define ixDIDT_TCP_EDC_THRESHOLD                   0x0074
+#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2           0x0075
+#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4           0x0076
+#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6           0x0077
+#define ixDIDT_TCP_EDC_STALL_PATTERN_7             0x0078
+
+#define ixDIDT_DB_EDC_CTRL                         0x0033
+#define ixDIDT_DB_EDC_THRESHOLD                    0x0034
+#define ixDIDT_DB_EDC_STALL_PATTERN_1_2            0x0035
+#define ixDIDT_DB_EDC_STALL_PATTERN_3_4            0x0036
+#define ixDIDT_DB_EDC_STALL_PATTERN_5_6            0x0037
+#define ixDIDT_DB_EDC_STALL_PATTERN_7              0x0038
+
+uint32_t DIDTEDCConfig_P12[] = {
+    ixDIDT_SQ_EDC_STALL_PATTERN_1_2,
+    ixDIDT_SQ_EDC_STALL_PATTERN_3_4,
+    ixDIDT_SQ_EDC_STALL_PATTERN_5_6,
+    ixDIDT_SQ_EDC_STALL_PATTERN_7,
+    ixDIDT_SQ_EDC_THRESHOLD,
+    ixDIDT_SQ_EDC_CTRL,
+    ixDIDT_TD_EDC_STALL_PATTERN_1_2,
+    ixDIDT_TD_EDC_STALL_PATTERN_3_4,
+    ixDIDT_TD_EDC_STALL_PATTERN_5_6,
+    ixDIDT_TD_EDC_STALL_PATTERN_7,
+    ixDIDT_TD_EDC_THRESHOLD,
+    ixDIDT_TD_EDC_CTRL,
+    ixDIDT_TCP_EDC_STALL_PATTERN_1_2,
+    ixDIDT_TCP_EDC_STALL_PATTERN_3_4,
+    ixDIDT_TCP_EDC_STALL_PATTERN_5_6,
+    ixDIDT_TCP_EDC_STALL_PATTERN_7,
+    ixDIDT_TCP_EDC_THRESHOLD,
+    ixDIDT_TCP_EDC_CTRL,
+    ixDIDT_DB_EDC_STALL_PATTERN_1_2,
+    ixDIDT_DB_EDC_STALL_PATTERN_3_4,
+    ixDIDT_DB_EDC_STALL_PATTERN_5_6,
+    ixDIDT_DB_EDC_STALL_PATTERN_7,
+    ixDIDT_DB_EDC_THRESHOLD,
+    ixDIDT_DB_EDC_CTRL,
+    0xFFFFFFFF // End of list
+};
+
 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
 		enum pp_clock_type type, uint32_t mask);
+static int smu7_notify_has_display(struct pp_hwmgr *hwmgr);
 
 static struct smu7_power_state *cast_phw_smu7_power_state(
 				  struct pp_hw_power_state *hw_ps)
@@ -178,7 +240,8 @@ static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 */
 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 {
-	if (hwmgr->chip_id == CHIP_VEGAM) {
+	if (hwmgr->chip_id >= CHIP_POLARIS10 &&
+	    hwmgr->chip_id <= CHIP_VEGAM) {
 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
 				CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0);
 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
@@ -1088,7 +1151,8 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 
 	/* enable SCLK dpm */
 	if (!data->sclk_dpm_key_disabled) {
-		if (hwmgr->chip_id == CHIP_VEGAM)
+		if (hwmgr->chip_id >= CHIP_POLARIS10 &&
+		    hwmgr->chip_id <= CHIP_VEGAM)
 			smu7_disable_sclk_vce_handshake(hwmgr);
 
 		PP_ASSERT_WITH_CODE(
@@ -1109,7 +1173,11 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 				"Failed to enable MCLK DPM during DPM Start Function!",
 				return -EINVAL);
 
-		if (hwmgr->chip_family != CHIP_VEGAM)
+		if ((hwmgr->chip_family == AMDGPU_FAMILY_CI) ||
+		    (hwmgr->chip_id == CHIP_POLARIS10) ||
+		    (hwmgr->chip_id == CHIP_POLARIS11) ||
+		    (hwmgr->chip_id == CHIP_POLARIS12) ||
+		    (hwmgr->chip_id == CHIP_TONGA))
 			PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
 
 
@@ -1331,6 +1399,50 @@ static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
+static int smu7_program_edc_didt_registers(struct pp_hwmgr *hwmgr,
+					   uint32_t *cac_config_regs,
+					   AtomCtrl_EDCLeakgeTable *edc_leakage_table)
+{
+	uint32_t data, i = 0;
+
+	while (cac_config_regs[i] != 0xFFFFFFFF) {
+		data = edc_leakage_table->DIDT_REG[i];
+		cgs_write_ind_register(hwmgr->device,
+				       CGS_IND_REG__DIDT,
+				       cac_config_regs[i],
+				       data);
+		i++;
+	}
+
+	return 0;
+}
+
+static int smu7_populate_edc_leakage_registers(struct pp_hwmgr *hwmgr)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	int ret = 0;
+
+	if (!data->disable_edc_leakage_controller &&
+	    data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset &&
+	    data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) {
+		ret = smu7_program_edc_didt_registers(hwmgr,
+						      DIDTEDCConfig_P12,
+						      &data->edc_leakage_table);
+		if (ret)
+			return ret;
+
+		ret = smum_send_msg_to_smc(hwmgr,
+					   (PPSMC_Msg)PPSMC_MSG_EnableEDCController,
+					   NULL);
+	} else {
+		ret = smum_send_msg_to_smc(hwmgr,
+					   (PPSMC_Msg)PPSMC_MSG_DisableEDCController,
+					   NULL);
+	}
+
+	return ret;
+}
+
 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
 	int tmp_result = 0;
@@ -1395,7 +1507,21 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 	PP_ASSERT_WITH_CODE((0 == tmp_result),
 			"Failed to enable VR hot GPIO interrupt!", result = tmp_result);
 
-	smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL);
+	if (hwmgr->chip_id >= CHIP_POLARIS10 &&
+	    hwmgr->chip_id <= CHIP_VEGAM) {
+		tmp_result = smu7_notify_has_display(hwmgr);
+		PP_ASSERT_WITH_CODE((0 == tmp_result),
+				"Failed to enable display setting!", result = tmp_result);
+	} else {
+		smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL);
+	}
+
+	if (hwmgr->chip_id >= CHIP_POLARIS10 &&
+	    hwmgr->chip_id <= CHIP_VEGAM) {
+		tmp_result = smu7_populate_edc_leakage_registers(hwmgr);
+		PP_ASSERT_WITH_CODE((0 == tmp_result),
+				"Failed to populate edc leakage registers!", result = tmp_result);
+	}
 
 	tmp_result = smu7_enable_sclk_control(hwmgr);
 	PP_ASSERT_WITH_CODE((0 == tmp_result),
@@ -1541,6 +1667,10 @@ static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
 	PP_ASSERT_WITH_CODE((tmp_result == 0),
 			"Failed to reset to default!", result = tmp_result);
 
+	tmp_result = smum_stop_smc(hwmgr);
+	PP_ASSERT_WITH_CODE((tmp_result == 0),
+			"Failed to stop smc!", result = tmp_result);
+
 	tmp_result = smu7_force_switch_to_arbf0(hwmgr);
 	PP_ASSERT_WITH_CODE((tmp_result == 0),
 			"Failed to force to switch arbf0!", result = tmp_result);
@@ -1554,6 +1684,8 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 	struct phm_ppt_v1_information *table_info =
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
 	struct amdgpu_device *adev = hwmgr->adev;
+	uint8_t tmp1, tmp2;
+	uint16_t tmp3 = 0;
 
 	data->dll_default_on = false;
 	data->mclk_dpm0_activity_target = 0xa;
@@ -1585,36 +1717,29 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 	data->current_profile_setting.sclk_down_hyst = 100;
 	data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
 	data->current_profile_setting.bupdate_mclk = 1;
-	if (adev->gmc.vram_width == 256) {
-		data->current_profile_setting.mclk_up_hyst = 10;
-		data->current_profile_setting.mclk_down_hyst = 60;
-		data->current_profile_setting.mclk_activity = 25;
-	} else if (adev->gmc.vram_width == 128) {
-		data->current_profile_setting.mclk_up_hyst = 5;
-		data->current_profile_setting.mclk_down_hyst = 16;
-		data->current_profile_setting.mclk_activity = 20;
-	} else if (adev->gmc.vram_width == 64) {
-		data->current_profile_setting.mclk_up_hyst = 3;
-		data->current_profile_setting.mclk_down_hyst = 16;
-		data->current_profile_setting.mclk_activity = 20;
+	if (hwmgr->chip_id >= CHIP_POLARIS10) {
+		if (adev->gmc.vram_width == 256) {
+			data->current_profile_setting.mclk_up_hyst = 10;
+			data->current_profile_setting.mclk_down_hyst = 60;
+			data->current_profile_setting.mclk_activity = 25;
+		} else if (adev->gmc.vram_width == 128) {
+			data->current_profile_setting.mclk_up_hyst = 5;
+			data->current_profile_setting.mclk_down_hyst = 16;
+			data->current_profile_setting.mclk_activity = 20;
+		} else if (adev->gmc.vram_width == 64) {
+			data->current_profile_setting.mclk_up_hyst = 3;
+			data->current_profile_setting.mclk_down_hyst = 16;
+			data->current_profile_setting.mclk_activity = 20;
+		}
+	} else {
+		data->current_profile_setting.mclk_up_hyst = 0;
+		data->current_profile_setting.mclk_down_hyst = 100;
+		data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
 	}
 	hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
 	hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 	hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 
-	if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
-		uint8_t tmp1, tmp2;
-		uint16_t tmp3 = 0;
-		atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
-						&tmp3);
-		tmp3 = (tmp3 >> 5) & 0x3;
-		data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
-	} else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
-		data->vddc_phase_shed_control = 1;
-	} else {
-		data->vddc_phase_shed_control = 0;
-	}
-
 	if (hwmgr->chip_id  == CHIP_HAWAII) {
 		data->thermal_temp_setting.temperature_low = 94500;
 		data->thermal_temp_setting.temperature_high = 95000;
@@ -1673,6 +1798,22 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 				PHM_PlatformCaps_ControlVDDCI);
 
+	data->vddc_phase_shed_control = 1;
+	if ((hwmgr->chip_id == CHIP_POLARIS12) ||
+	    ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
+	    ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
+	    ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) ||
+	    ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
+		if (data->voltage_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
+			atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
+							&tmp3);
+			tmp3 = (tmp3 >> 5) & 0x3;
+			data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
+		}
+	} else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
+		data->vddc_phase_shed_control = 1;
+	}
+
 	if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
 		&& (table_info->cac_dtp_table->usClockStretchAmount != 0))
 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
@@ -1694,6 +1835,85 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 	if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 			      PHM_PlatformCaps_VCEPowerGating);
+
+	data->disable_edc_leakage_controller = true;
+	if (((adev->asic_type == CHIP_POLARIS10) && hwmgr->is_kicker) ||
+	    ((adev->asic_type == CHIP_POLARIS11) && hwmgr->is_kicker) ||
+	    (adev->asic_type == CHIP_POLARIS12) ||
+	    (adev->asic_type == CHIP_VEGAM))
+		data->disable_edc_leakage_controller = false;
+
+	if (!atomctrl_is_asic_internal_ss_supported(hwmgr)) {
+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+			PHM_PlatformCaps_MemorySpreadSpectrumSupport);
+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+			PHM_PlatformCaps_EngineSpreadSpectrumSupport);
+	}
+
+	if ((adev->pdev->device == 0x699F) &&
+	    (adev->pdev->revision == 0xCF)) {
+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+				PHM_PlatformCaps_PowerContainment);
+		data->enable_tdc_limit_feature = false;
+		data->enable_pkg_pwr_tracking_feature = false;
+		data->disable_edc_leakage_controller = true;
+		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
+					PHM_PlatformCaps_ClockStretcher);
+	}
+}
+
+static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	struct amdgpu_device *adev = hwmgr->adev;
+	uint32_t asicrev1, evv_revision, max = 0, min = 0;
+
+	atomctrl_read_efuse(hwmgr, STRAP_EVV_REVISION_LSB, STRAP_EVV_REVISION_MSB,
+			&evv_revision);
+
+	atomctrl_read_efuse(hwmgr, 568, 579, &asicrev1);
+
+	if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
+	    ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) {
+		min = 1200;
+		max = 2500;
+	} else if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
+		   ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
+		min = 900;
+		max= 2100;
+	} else if (hwmgr->chip_id == CHIP_POLARIS10) {
+		if (adev->pdev->subsystem_vendor == 0x106B) {
+			min = 1000;
+			max = 2300;
+		} else {
+			if (evv_revision == 0) {
+				min = 1000;
+				max = 2300;
+			} else if (evv_revision == 1) {
+				if (asicrev1 == 326) {
+					min = 1200;
+					max = 2500;
+					/* TODO: PATCH RO in VBIOS */
+				} else {
+					min = 1200;
+					max = 2000;
+				}
+			} else if (evv_revision == 2) {
+				min = 1200;
+				max = 2500;
+			}
+		}
+	} else {
+		min = 1100;
+		max = 2100;
+	}
+
+	data->ro_range_minimum = min;
+	data->ro_range_maximum = max;
+
+	/* TODO: PATCH RO in VBIOS here */
+
+	return 0;
 }
 
 /**
@@ -1714,6 +1934,10 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
 			(struct phm_ppt_v1_information *)hwmgr->pptable;
 	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
 
+	if (hwmgr->chip_id == CHIP_POLARIS10 ||
+	    hwmgr->chip_id == CHIP_POLARIS11 ||
+	    hwmgr->chip_id == CHIP_POLARIS12)
+		smu7_calculate_ro_range(hwmgr);
 
 	for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
 		vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
@@ -2077,6 +2301,28 @@ static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
 	return result;
 }
 
+static int smu7_find_highest_vddc(struct pp_hwmgr *hwmgr)
+{
+	struct phm_ppt_v1_information *table_info =
+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
+	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
+						table_info->vdd_dep_on_sclk;
+	struct phm_ppt_v1_voltage_lookup_table *lookup_table =
+						table_info->vddc_lookup_table;
+	uint16_t highest_voltage;
+	uint32_t i;
+
+	highest_voltage = allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
+
+	for (i = 0; i < lookup_table->count; i++) {
+		if (lookup_table->entries[i].us_vdd < ATOM_VIRTUAL_VOLTAGE_ID0 &&
+		    lookup_table->entries[i].us_vdd > highest_voltage)
+			highest_voltage = lookup_table->entries[i].us_vdd;
+	}
+
+	return highest_voltage;
+}
+
 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
 {
 	struct phm_ppt_v1_information *table_info =
@@ -2105,8 +2351,12 @@ static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
 		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
 	table_info->max_clock_voltage_on_ac.mclk =
 		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
-	table_info->max_clock_voltage_on_ac.vddc =
-		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
+	if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM)
+		table_info->max_clock_voltage_on_ac.vddc =
+			smu7_find_highest_vddc(hwmgr);
+	else
+		table_info->max_clock_voltage_on_ac.vddc =
+			allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
 	table_info->max_clock_voltage_on_ac.vddci =
 		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
 
@@ -2138,10 +2388,17 @@ static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
 	sub_sys_id = adev->pdev->subsystem_device;
 	sub_vendor_id = adev->pdev->subsystem_vendor;
 
-	if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
-			((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
-		    (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
-		    (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
+	if (adev->pdev->device == 0x67DF && hw_revision == 0xC7 &&
+	    ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
+	     (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
+	     (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
+
+		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
+					      CGS_IND_REG__SMC,
+					      PWR_CKS_CNTL,
+					      CKS_STRETCH_AMOUNT,
+					      0x3);
+
 		if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
 			return 0;
 
@@ -2542,6 +2799,42 @@ static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
+#define LEAKAGE_ID_MSB			463
+#define LEAKAGE_ID_LSB			454
+
+static int smu7_update_edc_leakage_table(struct pp_hwmgr *hwmgr)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	uint32_t efuse;
+	uint16_t offset;
+	int ret = 0;
+
+	if (data->disable_edc_leakage_controller)
+		return 0;
+
+	ret = atomctrl_get_edc_hilo_leakage_offset_table(hwmgr,
+							 &data->edc_hilo_leakage_offset_from_vbios);
+	if (ret)
+		return ret;
+
+	if (data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset &&
+	    data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) {
+		atomctrl_read_efuse(hwmgr, LEAKAGE_ID_LSB, LEAKAGE_ID_MSB, &efuse);
+		if (efuse < data->edc_hilo_leakage_offset_from_vbios.usHiLoLeakageThreshold)
+			offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset;
+		else
+			offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset;
+
+		ret = atomctrl_get_edc_leakage_table(hwmgr,
+						     &data->edc_leakage_table,
+						     offset);
+		if (ret)
+			return ret;
+	}
+
+	return ret;
+}
+
 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data;
@@ -2591,6 +2884,8 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 		data->pcie_gen_cap = adev->pm.pcie_gen_mask;
 		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 			data->pcie_spc_cap = 20;
+		else
+			data->pcie_spc_cap = 16;
 		data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
 
 		hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
@@ -2603,6 +2898,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 		smu7_hwmgr_backend_fini(hwmgr);
 	}
 
+	result = smu7_update_edc_leakage_table(hwmgr);
+	if (result)
+		return result;
+
 	return 0;
 }
 
@@ -2880,7 +3179,7 @@ static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
 	case CHIP_POLARIS10:
 	case CHIP_POLARIS11:
 	case CHIP_POLARIS12:
-		if (hwmgr->is_kicker)
+		if (hwmgr->is_kicker || (hwmgr->chip_id == CHIP_POLARIS12))
 			switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
 		else
 			switch_limit_us = data->is_memory_gddr5 ? 200 : 150;
@@ -2911,6 +3210,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 	struct PP_Clocks minimum_clocks = {0};
 	bool disable_mclk_switching;
 	bool disable_mclk_switching_for_frame_lock;
+	bool disable_mclk_switching_for_display;
 	const struct phm_clock_and_voltage_limits *max_limits;
 	uint32_t i;
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -2918,9 +3218,12 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
 	int32_t count;
 	int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
+	uint32_t latency;
+	bool latency_allowed = false;
 
 	data->battery_state = (PP_StateUILabel_Battery ==
 			request_ps->classification.ui_label);
+	data->mclk_ignore_signal = false;
 
 	PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2,
 				 "VI should always have 2 performance levels",
@@ -2971,19 +3274,26 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 				    hwmgr->platform_descriptor.platformCaps,
 				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
 
+	disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) &&
+						!hwmgr->display_config->multi_monitor_in_sync) ||
+						smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time);
 
-	if (hwmgr->display_config->num_display == 0)
-		disable_mclk_switching = false;
-	else
-		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
-					  !hwmgr->display_config->multi_monitor_in_sync) ||
-			disable_mclk_switching_for_frame_lock ||
-			smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time);
+	disable_mclk_switching = disable_mclk_switching_for_frame_lock ||
+					 disable_mclk_switching_for_display;
+
+	if (hwmgr->display_config->num_display == 0) {
+		if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM)
+			data->mclk_ignore_signal = true;
+		else
+			disable_mclk_switching = false;
+	}
 
 	sclk = smu7_ps->performance_levels[0].engine_clock;
 	mclk = smu7_ps->performance_levels[0].memory_clock;
 
-	if (disable_mclk_switching)
+	if (disable_mclk_switching &&
+	    (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
+	    hwmgr->chip_id <= CHIP_VEGAM)))
 		mclk = smu7_ps->performance_levels
 		[smu7_ps->performance_level_count - 1].memory_clock;
 
@@ -3008,8 +3318,41 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 		if (mclk < smu7_ps->performance_levels[1].memory_clock)
 			mclk = smu7_ps->performance_levels[1].memory_clock;
 
+		if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) {
+			if (disable_mclk_switching_for_display) {
+				/* Find the lowest MCLK frequency that is within
+				 * the tolerable latency defined in DAL
+				 */
+				latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
+				for (i = 0; i < data->mclk_latency_table.count; i++) {
+					if (data->mclk_latency_table.entries[i].latency <= latency) {
+						latency_allowed = true;
+
+						if ((data->mclk_latency_table.entries[i].frequency >=
+								smu7_ps->performance_levels[0].memory_clock) &&
+						    (data->mclk_latency_table.entries[i].frequency <=
+								smu7_ps->performance_levels[1].memory_clock)) {
+							mclk = data->mclk_latency_table.entries[i].frequency;
+							break;
+						}
+					}
+				}
+				if ((i >= data->mclk_latency_table.count - 1) && !latency_allowed) {
+					data->mclk_ignore_signal = true;
+				} else {
+					data->mclk_ignore_signal = false;
+				}
+			}
+
+			if (disable_mclk_switching_for_frame_lock)
+				mclk = smu7_ps->performance_levels[1].memory_clock;
+		}
+
 		smu7_ps->performance_levels[0].memory_clock = mclk;
-		smu7_ps->performance_levels[1].memory_clock = mclk;
+
+		if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
+		      hwmgr->chip_id <= CHIP_VEGAM))
+			smu7_ps->performance_levels[1].memory_clock = mclk;
 	} else {
 		if (smu7_ps->performance_levels[1].memory_clock <
 				smu7_ps->performance_levels[0].memory_clock)
@@ -3755,6 +4098,7 @@ static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 	}
 
 	if ((0 == data->mclk_dpm_key_disabled) &&
+		!data->mclk_ignore_signal &&
 		(data->need_update_smu7_dpm_table &
 		 DPMTABLE_OD_UPDATE_MCLK)) {
 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
@@ -3911,6 +4255,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 	}
 
 	if ((0 == data->mclk_dpm_key_disabled) &&
+		!data->mclk_ignore_signal &&
 		(data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
 
 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
@@ -3964,7 +4309,12 @@ static int smu7_notify_link_speed_change_after_state_change(
 	return 0;
 }
 
-static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
+static int smu7_notify_no_display(struct pp_hwmgr *hwmgr)
+{
+	return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL) == 0) ?  0 : -EINVAL;
+}
+
+static int smu7_notify_has_display(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 
@@ -3977,10 +4327,25 @@ static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
 			smum_send_msg_to_smc_with_parameter(hwmgr,
 					(PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2,
 					NULL);
+		data->last_sent_vbi_timeout = data->frame_time_x2;
 	}
+
 	return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay, NULL) == 0) ?  0 : -EINVAL;
 }
 
+static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	int result = 0;
+
+	if (data->mclk_ignore_signal)
+		result = smu7_notify_no_display(hwmgr);
+	else
+		result = smu7_notify_has_display(hwmgr);
+
+	return result;
+}
+
 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
 {
 	int tmp_result, result = 0;
@@ -4031,11 +4396,6 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
 			"Failed to update SCLK threshold!",
 			result = tmp_result);
 
-	tmp_result = smu7_notify_smc_display(hwmgr);
-	PP_ASSERT_WITH_CODE((0 == tmp_result),
-			"Failed to notify smc display settings!",
-			result = tmp_result);
-
 	tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
 	PP_ASSERT_WITH_CODE((0 == tmp_result),
 			"Failed to unfreeze SCLK MCLK DPM!",
@@ -4046,6 +4406,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
 			"Failed to upload DPM level enabled mask!",
 			result = tmp_result);
 
+	tmp_result = smu7_notify_smc_display(hwmgr);
+	PP_ASSERT_WITH_CODE((0 == tmp_result),
+			"Failed to notify smc display settings!",
+			result = tmp_result);
+
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_PCIEPerformanceRequest)) {
 		tmp_result =
@@ -4069,20 +4434,8 @@ static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f
 }
 
 static int
-smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
-{
-	PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
-
-	return (smum_send_msg_to_smc(hwmgr, msg, NULL) == 0) ?  0 : -1;
-}
-
-static int
 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
 {
-	if (hwmgr->display_config->num_display > 1 &&
-			!hwmgr->display_config->multi_monitor_in_sync)
-		smu7_notify_smc_display_change(hwmgr, false);
-
 	return 0;
 }
 
@@ -4205,6 +4558,11 @@ smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
 	if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh)
 		is_update_required = true;
 
+	if (hwmgr->chip_id >= CHIP_POLARIS10 &&
+	    hwmgr->chip_id <= CHIP_VEGAM &&
+	    data->last_sent_vbi_timeout != data->frame_time_x2)
+		is_update_required = true;
+
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
 		if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
 			(data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
@@ -4761,6 +5119,125 @@ static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type
 	return 0;
 }
 
+static int smu7_get_sclks_with_latency(struct pp_hwmgr *hwmgr,
+				       struct pp_clock_levels_with_latency *clocks)
+{
+	struct phm_ppt_v1_information *table_info =
+			(struct phm_ppt_v1_information *)hwmgr->pptable;
+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
+			table_info->vdd_dep_on_sclk;
+	int i;
+
+	clocks->num_levels = 0;
+	for (i = 0; i < dep_sclk_table->count; i++) {
+		if (dep_sclk_table->entries[i].clk) {
+			clocks->data[clocks->num_levels].clocks_in_khz =
+				dep_sclk_table->entries[i].clk * 10;
+			clocks->num_levels++;
+		}
+	}
+
+	return 0;
+}
+
+static int smu7_get_mclks_with_latency(struct pp_hwmgr *hwmgr,
+				       struct pp_clock_levels_with_latency *clocks)
+{
+	struct phm_ppt_v1_information *table_info =
+			(struct phm_ppt_v1_information *)hwmgr->pptable;
+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
+			table_info->vdd_dep_on_mclk;
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	int i;
+
+	clocks->num_levels = 0;
+	data->mclk_latency_table.count = 0;
+	for (i = 0; i < dep_mclk_table->count; i++) {
+		if (dep_mclk_table->entries[i].clk) {
+			clocks->data[clocks->num_levels].clocks_in_khz =
+					dep_mclk_table->entries[i].clk * 10;
+			data->mclk_latency_table.entries[data->mclk_latency_table.count].frequency =
+					dep_mclk_table->entries[i].clk;
+			clocks->data[clocks->num_levels].latency_in_us =
+				data->mclk_latency_table.entries[data->mclk_latency_table.count].latency =
+					smu7_get_mem_latency(hwmgr, dep_mclk_table->entries[i].clk);
+			clocks->num_levels++;
+			data->mclk_latency_table.count++;
+		}
+	}
+
+	return 0;
+}
+
+static int smu7_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
+					       enum amd_pp_clock_type type,
+					       struct pp_clock_levels_with_latency *clocks)
+{
+	if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
+	      hwmgr->chip_id <= CHIP_VEGAM))
+		return -EINVAL;
+
+	switch (type) {
+	case amd_pp_sys_clock:
+		smu7_get_sclks_with_latency(hwmgr, clocks);
+		break;
+	case amd_pp_mem_clock:
+		smu7_get_mclks_with_latency(hwmgr, clocks);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int smu7_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+						 void *clock_range)
+{
+	struct phm_ppt_v1_information *table_info =
+			(struct phm_ppt_v1_information *)hwmgr->pptable;
+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
+			table_info->vdd_dep_on_mclk;
+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
+			table_info->vdd_dep_on_sclk;
+	struct polaris10_smumgr *smu_data =
+			(struct polaris10_smumgr *)(hwmgr->smu_backend);
+	SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
+	struct dm_pp_wm_sets_with_clock_ranges *watermarks =
+			(struct dm_pp_wm_sets_with_clock_ranges *)clock_range;
+	uint32_t i, j, k;
+	bool valid_entry;
+
+	if (!(hwmgr->chip_id >= CHIP_POLARIS10 &&
+	      hwmgr->chip_id <= CHIP_VEGAM))
+		return -EINVAL;
+
+	for (i = 0; i < dep_mclk_table->count; i++) {
+		for (j = 0; j < dep_sclk_table->count; j++) {
+			valid_entry = false;
+			for (k = 0; k < watermarks->num_wm_sets; k++) {
+				if (dep_sclk_table->entries[i].clk / 10 >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz &&
+				    dep_sclk_table->entries[i].clk / 10 < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz &&
+				    dep_mclk_table->entries[i].clk / 10 >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz &&
+				    dep_mclk_table->entries[i].clk / 10 < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz) {
+					valid_entry = true;
+					table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id;
+					break;
+				}
+			}
+			PP_ASSERT_WITH_CODE(valid_entry,
+					"Clock is not in range of specified clock range for watermark from DAL!  Using highest water mark set.",
+					table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id);
+		}
+	}
+
+	return smu7_copy_bytes_to_smc(hwmgr,
+				      smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, DisplayWatermark),
+				      (uint8_t *)table->DisplayWatermark,
+				      sizeof(uint8_t) * SMU74_MAX_LEVELS_MEMORY * SMU74_MAX_LEVELS_GRAPHICS,
+				      SMC_RAM_END);
+}
+
 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
 					uint32_t virtual_addr_low,
 					uint32_t virtual_addr_hi,
@@ -5178,6 +5655,8 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
 	.get_mclk_od = smu7_get_mclk_od,
 	.set_mclk_od = smu7_set_mclk_od,
 	.get_clock_by_type = smu7_get_clock_by_type,
+	.get_clock_by_type_with_latency = smu7_get_clock_by_type_with_latency,
+	.set_watermarks_for_clocks_ranges = smu7_set_watermarks_for_clocks_ranges,
 	.read_sensor = smu7_read_sensor,
 	.dynamic_state_management_disable = smu7_disable_dpm_tasks,
 	.avfs_control = smu7_avfs_control,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
index 69d361f8dfca..d9e8b386bd4d 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.h
@@ -200,10 +200,21 @@ struct profile_mode_setting {
 	uint16_t mclk_activity;
 };
 
+struct smu7_mclk_latency_entries {
+	uint32_t  frequency;
+	uint32_t  latency;
+};
+
+struct smu7_mclk_latency_table {
+	uint32_t  count;
+	struct smu7_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
+};
+
 struct smu7_hwmgr {
 	struct smu7_dpm_table			dpm_table;
 	struct smu7_dpm_table			golden_dpm_table;
 	struct smu7_odn_dpm_table		odn_dpm_table;
+	struct smu7_mclk_latency_table		mclk_latency_table;
 
 	uint32_t						voting_rights_clients[8];
 	uint32_t						static_screen_threshold_unit;
@@ -239,6 +250,7 @@ struct smu7_hwmgr {
 
 	bool                           pcie_performance_request;
 	bool                           battery_state;
+	bool                           mclk_ignore_signal;
 	bool                           is_tlu_enabled;
 	bool                           disable_handshake;
 	bool                           smc_voltage_control_enabled;
@@ -324,10 +336,18 @@ struct smu7_hwmgr {
 	uint32_t                              avfs_vdroop_override_setting;
 	bool                                  apply_avfs_cks_off_voltage;
 	uint32_t                              frame_time_x2;
+	uint32_t                              last_sent_vbi_timeout;
 	uint16_t                              mem_latency_high;
 	uint16_t                              mem_latency_low;
 	uint32_t                              vr_config;
 	struct profile_mode_setting           current_profile_setting;
+
+	uint32_t                              ro_range_minimum;
+	uint32_t                              ro_range_maximum;
+
+	bool                                  disable_edc_leakage_controller;
+	AtomCtrl_HiLoLeakageOffsetTable       edc_hilo_leakage_offset_from_vbios;
+	AtomCtrl_EDCLeakgeTable               edc_leakage_table;
 };
 
 /* To convert to Q8.8 format for firmware */
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
index 5d4971576111..32a5a00fd8ae 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
@@ -852,12 +852,14 @@ static const struct gpu_pt_config_reg DIDTConfig_VegaM[] =
 };
 static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
 {
+	struct amdgpu_device *adev = hwmgr->adev;
 	uint32_t en = enable ? 1 : 0;
 	uint32_t block_en = 0;
 	int32_t result = 0;
 	uint32_t didt_block;
 
-	if (hwmgr->chip_id == CHIP_POLARIS11)
+	if ((hwmgr->chip_id == CHIP_POLARIS11) &&
+	    (adev->pdev->subsystem_vendor != 0x106B))
 		didt_block = Polaris11_DIDTBlock_Info;
 	else
 		didt_block = DIDTBlock_Info;
@@ -962,6 +964,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
 	uint32_t num_se = 0;
 	uint32_t count, value, value2;
 	struct amdgpu_device *adev = hwmgr->adev;
+	uint32_t efuse;
 
 	num_se = adev->gfx.config.max_shader_engines;
 
@@ -988,7 +991,9 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
 			} else if (hwmgr->chip_id == CHIP_POLARIS11) {
 				result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
 				PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
-				if (hwmgr->is_kicker)
+
+				if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
+				    ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
 					result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);
 				else
 					result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
@@ -1016,7 +1021,32 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
 						NULL);
 			PP_ASSERT_WITH_CODE((0 == result),
 					"Failed to enable DPM DIDT.", goto error);
+
+			if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
+			    ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) {
+				result = smum_send_msg_to_smc(hwmgr,
+							(uint16_t)(PPSMC_MSG_EnableDpmMcBlackout),
+							NULL);
+				PP_ASSERT_WITH_CODE((0 == result),
+						"Failed to enable workaround for CRC issue.", goto error);
+			} else {
+				atomctrl_read_efuse(hwmgr, 547, 547, &efuse);
+				if (efuse == 1) {
+					result = smum_send_msg_to_smc(hwmgr,
+								(uint16_t)(PPSMC_MSG_EnableDpmMcBlackout),
+								NULL);
+					PP_ASSERT_WITH_CODE((0 == result),
+							"Failed to enable workaround for CRC issue.", goto error);
+				} else {
+					result = smum_send_msg_to_smc(hwmgr,
+								(uint16_t)(PPSMC_MSG_DisableDpmMcBlackout),
+								NULL);
+					PP_ASSERT_WITH_CODE((0 == result),
+							"Failed to enable workaround for CRC issue.", goto error);
+				}
+			}
 		}
+
 		mutex_unlock(&adev->grbm_idx_mutex);
 		amdgpu_gfx_rlc_exit_safe_mode(adev);
 	}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
index 0b30f73649a8..e3d9d969d86a 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
@@ -175,6 +175,17 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
 				hwmgr->thermal_controller.
 				advanceFanControlParameters.ucTargetTemperature,
 				NULL);
+
+	if (!result &&
+	    (hwmgr->chip_id == CHIP_POLARIS10 ||
+	    hwmgr->chip_id == CHIP_POLARIS11 ||
+	    hwmgr->chip_id == CHIP_POLARIS12) &&
+	    hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM &&
+	    !PP_CAP(PHM_PlatformCaps_customThermalManagement))
+		result = smum_send_msg_to_smc(hwmgr,
+				PPSMC_MSG_EnableZeroRpm,
+				NULL);
+
 	hwmgr->fan_ctrl_enabled = true;
 
 	return result;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
index 35ed47ebaf09..ed9b89980184 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
@@ -276,7 +276,7 @@ static int smu8_init_dynamic_state_adjustment_rule_settings(
 {
 	struct phm_clock_voltage_dependency_table *table_clk_vlt;
 
-	table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 7),
+	table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 8),
 				GFP_KERNEL);
 
 	if (NULL == table_clk_vlt) {
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
index 60b5ca974356..2a0ca5194bbe 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
@@ -492,13 +492,12 @@ int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
  */
 int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
 {
-	uint32_t table_size;
 	struct phm_clock_voltage_dependency_table *table_clk_vlt;
 	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
 
 	/* initialize vddc_dep_on_dal_pwrl table */
-	table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
-	table_clk_vlt = kzalloc(table_size, GFP_KERNEL);
+	table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 4),
+				GFP_KERNEL);
 
 	if (NULL == table_clk_vlt) {
 		pr_err("Can not allocate space for vddc_dep_on_dal_pwrl! \n");
@@ -506,11 +505,23 @@ int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr
 	} else {
 		table_clk_vlt->count = 4;
 		table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
-		table_clk_vlt->entries[0].v = 0;
+		if (hwmgr->chip_id >= CHIP_POLARIS10 &&
+		    hwmgr->chip_id <= CHIP_VEGAM)
+			table_clk_vlt->entries[0].v = 700;
+		else
+			table_clk_vlt->entries[0].v = 0;
 		table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
-		table_clk_vlt->entries[1].v = 720;
+		if (hwmgr->chip_id >= CHIP_POLARIS10 &&
+		    hwmgr->chip_id <= CHIP_VEGAM)
+			table_clk_vlt->entries[1].v = 740;
+		else
+			table_clk_vlt->entries[1].v = 720;
 		table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
-		table_clk_vlt->entries[2].v = 810;
+		if (hwmgr->chip_id >= CHIP_POLARIS10 &&
+		    hwmgr->chip_id <= CHIP_VEGAM)
+			table_clk_vlt->entries[2].v = 800;
+		else
+			table_clk_vlt->entries[2].v = 810;
 		table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
 		table_clk_vlt->entries[3].v = 900;
 		if (pptable_info != NULL)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c
index f29af5ca0aa0..535404de78a2 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_processpptables.c
@@ -344,18 +344,15 @@ static int get_mm_clock_voltage_table(
 		phm_ppt_v1_mm_clock_voltage_dependency_table **vega10_mm_table,
 		const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	const ATOM_Vega10_MM_Dependency_Record *mm_dependency_record;
 	phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table;
 
 	PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0),
 			"Invalid PowerPlay Table!", return -1);
 
-	table_size = sizeof(uint32_t) +
-			sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record) *
-			mm_dependency_table->ucNumEntries;
-	mm_table = kzalloc(table_size, GFP_KERNEL);
-
+	mm_table = kzalloc(struct_size(mm_table, entries, mm_dependency_table->ucNumEntries),
+			   GFP_KERNEL);
 	if (!mm_table)
 		return -ENOMEM;
 
@@ -571,18 +568,14 @@ static int get_socclk_voltage_dependency_table(
 		phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_clk_dep_table,
 		const ATOM_Vega10_SOCCLK_Dependency_Table *clk_dep_table)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	phm_ppt_v1_clock_voltage_dependency_table *clk_table;
 
 	PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries,
 		"Invalid PowerPlay Table!", return -1);
 
-	table_size = sizeof(uint32_t) +
-			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
-			clk_dep_table->ucNumEntries;
-
-	clk_table = kzalloc(table_size, GFP_KERNEL);
-
+	clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries),
+			    GFP_KERNEL);
 	if (!clk_table)
 		return -ENOMEM;
 
@@ -605,18 +598,14 @@ static int get_mclk_voltage_dependency_table(
 		phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_mclk_dep_table,
 		const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	phm_ppt_v1_clock_voltage_dependency_table *mclk_table;
 
 	PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries,
 		"Invalid PowerPlay Table!", return -1);
 
-	table_size = sizeof(uint32_t) +
-			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
-			mclk_dep_table->ucNumEntries;
-
-	mclk_table = kzalloc(table_size, GFP_KERNEL);
-
+	mclk_table = kzalloc(struct_size(mclk_table, entries, mclk_dep_table->ucNumEntries),
+			    GFP_KERNEL);
 	if (!mclk_table)
 		return -ENOMEM;
 
@@ -644,7 +633,7 @@ static int get_gfxclk_voltage_dependency_table(
 			**pp_vega10_clk_dep_table,
 		const ATOM_Vega10_GFXCLK_Dependency_Table *clk_dep_table)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	struct phm_ppt_v1_clock_voltage_dependency_table
 				*clk_table;
 	ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;
@@ -652,12 +641,8 @@ static int get_gfxclk_voltage_dependency_table(
 	PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
 			"Invalid PowerPlay Table!", return -1);
 
-	table_size = sizeof(uint32_t) +
-			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
-			clk_dep_table->ucNumEntries;
-
-	clk_table = kzalloc(table_size, GFP_KERNEL);
-
+	clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries),
+			    GFP_KERNEL);
 	if (!clk_table)
 		return -ENOMEM;
 
@@ -711,19 +696,15 @@ static int get_pix_clk_voltage_dependency_table(
 			**pp_vega10_clk_dep_table,
 		const  ATOM_Vega10_PIXCLK_Dependency_Table *clk_dep_table)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	struct phm_ppt_v1_clock_voltage_dependency_table
 				*clk_table;
 
 	PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
 			"Invalid PowerPlay Table!", return -1);
 
-	table_size = sizeof(uint32_t) +
-			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
-			clk_dep_table->ucNumEntries;
-
-	clk_table = kzalloc(table_size, GFP_KERNEL);
-
+	clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries),
+			    GFP_KERNEL);
 	if (!clk_table)
 		return -ENOMEM;
 
@@ -747,7 +728,7 @@ static int get_dcefclk_voltage_dependency_table(
 			**pp_vega10_clk_dep_table,
 		const ATOM_Vega10_DCEFCLK_Dependency_Table *clk_dep_table)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	uint8_t num_entries;
 	struct phm_ppt_v1_clock_voltage_dependency_table
 				*clk_table;
@@ -775,12 +756,8 @@ static int get_dcefclk_voltage_dependency_table(
 		num_entries = clk_dep_table->ucNumEntries;
 
 
-	table_size = sizeof(uint32_t) +
-			sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
-			num_entries;
-
-	clk_table = kzalloc(table_size, GFP_KERNEL);
-
+	clk_table = kzalloc(struct_size(clk_table, entries, num_entries),
+			    GFP_KERNEL);
 	if (!clk_table)
 		return -ENOMEM;
 
@@ -807,7 +784,7 @@ static int get_pcie_table(struct pp_hwmgr *hwmgr,
 		struct phm_ppt_v1_pcie_table **vega10_pcie_table,
 		const Vega10_PPTable_Generic_SubTable_Header *table)
 {
-	uint32_t table_size, i, pcie_count;
+	uint32_t i, pcie_count;
 	struct phm_ppt_v1_pcie_table *pcie_table;
 	struct phm_ppt_v2_information *table_info =
 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -818,12 +795,8 @@ static int get_pcie_table(struct pp_hwmgr *hwmgr,
 			"Invalid PowerPlay Table!",
 			return 0);
 
-	table_size = sizeof(uint32_t) +
-			sizeof(struct phm_ppt_v1_pcie_record) *
-			atom_pcie_table->ucNumEntries;
-
-	pcie_table = kzalloc(table_size, GFP_KERNEL);
-
+	pcie_table = kzalloc(struct_size(pcie_table, entries, atom_pcie_table->ucNumEntries),
+			     GFP_KERNEL);
 	if (!pcie_table)
 		return -ENOMEM;
 
@@ -875,17 +848,14 @@ static int get_valid_clk(
 		struct phm_clock_array **clk_table,
 		const phm_ppt_v1_clock_voltage_dependency_table *clk_volt_pp_table)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	struct phm_clock_array *table;
 
 	PP_ASSERT_WITH_CODE(clk_volt_pp_table->count,
 			"Invalid PowerPlay Table!", return -1);
 
-	table_size = sizeof(uint32_t) +
-			sizeof(uint32_t) * clk_volt_pp_table->count;
-
-	table = kzalloc(table_size, GFP_KERNEL);
-
+	table = kzalloc(struct_size(table, values, clk_volt_pp_table->count),
+			GFP_KERNEL);
 	if (!table)
 		return -ENOMEM;
 
@@ -1066,18 +1036,14 @@ static int get_vddc_lookup_table(
 		const ATOM_Vega10_Voltage_Lookup_Table *vddc_lookup_pp_tables,
 		uint32_t max_levels)
 {
-	uint32_t table_size, i;
+	uint32_t i;
 	phm_ppt_v1_voltage_lookup_table *table;
 
 	PP_ASSERT_WITH_CODE((vddc_lookup_pp_tables->ucNumEntries != 0),
 			"Invalid SOC_VDDD Lookup Table!", return 1);
 
-	table_size = sizeof(uint32_t) +
-			sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels;
-
-	table = kzalloc(table_size, GFP_KERNEL);
-
-	if (table == NULL)
+	table = kzalloc(struct_size(table, entries, max_levels), GFP_KERNEL);
+	if (!table)
 		return -ENOMEM;
 
 	table->count = vddc_lookup_pp_tables->ucNumEntries;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
index e4d1f3d66ef4..329bf4d44bbc 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
@@ -2726,10 +2726,7 @@ static int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
 
 static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
 {
-	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
-					     CGS_IND_REG__SMC, FEATURE_STATUS,
-					     VOLTAGE_CONTROLLER_ON))
-		? true : false;
+	return ci_is_smc_ram_running(hwmgr);
 }
 
 static int ci_smu_init(struct pp_hwmgr *hwmgr)
@@ -2939,6 +2936,29 @@ static int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
 	return 0;
 }
 
+static void ci_reset_smc(struct pp_hwmgr *hwmgr)
+{
+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+				  SMC_SYSCON_RESET_CNTL,
+				  rst_reg, 1);
+}
+
+
+static void ci_stop_smc_clock(struct pp_hwmgr *hwmgr)
+{
+	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+				  SMC_SYSCON_CLOCK_CNTL_0,
+				  ck_disable, 1);
+}
+
+static int ci_stop_smc(struct pp_hwmgr *hwmgr)
+{
+	ci_reset_smc(hwmgr);
+	ci_stop_smc_clock(hwmgr);
+
+	return 0;
+}
+
 const struct pp_smumgr_func ci_smu_funcs = {
 	.name = "ci_smu",
 	.smu_init = ci_smu_init,
@@ -2964,4 +2984,5 @@ const struct pp_smumgr_func ci_smu_funcs = {
 	.is_dpm_running = ci_is_dpm_running,
 	.update_dpm_settings = ci_update_dpm_settings,
 	.update_smc_table = ci_update_smc_table,
+	.stop_smc = ci_stop_smc,
 };
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
index ecb9ee46d6b3..fef9d3906fcc 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
@@ -318,13 +318,12 @@ static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
 {
 
 	uint32_t efuse = 0;
-	uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
 
 	if (!hwmgr->not_vf)
 		return false;
 
 	if (!atomctrl_read_efuse(hwmgr, AVFS_EN_LSB, AVFS_EN_MSB,
-			mask, &efuse)) {
+			&efuse)) {
 		if (efuse)
 			return true;
 	}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
index c3d2e6dcf62a..d4253b1116c2 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
@@ -401,6 +401,8 @@ static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
 		*voltage |= (data->vbios_boot_state.vddci_bootup_value *
 				VOLTAGE_SCALE) << VDDCI_SHIFT;
 	else if (dep_table->entries[i-1].vddci) {
+		*voltage |= (dep_table->entries[i - 1].vddci * VOLTAGE_SCALE) << VDDC_SHIFT;
+	} else {
 		vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
 				(dep_table->entries[i].vddc -
 						(uint16_t)VDDC_VDDCI_DELTA));
@@ -470,6 +472,21 @@ static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmg
 	return 0;
 }
 
+static void polaris10_populate_zero_rpm_parameters(struct pp_hwmgr *hwmgr)
+{
+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+	SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
+	uint16_t fan_stop_temp =
+		((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStopTemperature) << 8;
+	uint16_t fan_start_temp =
+		((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStartTemperature) << 8;
+
+	if (hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM) {
+		table->FanStartTemperature = PP_HOST_TO_SMC_US(fan_start_temp);
+		table->FanStopTemperature = PP_HOST_TO_SMC_US(fan_stop_temp);
+	}
+}
+
 static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
 {
 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
@@ -671,6 +688,31 @@ static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
+static int polaris10_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
+					struct SMU74_Discrete_DpmTable *table)
+{
+	uint32_t count, level;
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+	count = data->vddc_voltage_table.count;
+
+	if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
+		if (count > SMU_MAX_SMIO_LEVELS)
+			count = SMU_MAX_SMIO_LEVELS;
+		for (level = 0; level < count; ++level) {
+			table->SmioTable1.Pattern[level].Voltage =
+				PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[level].value * VOLTAGE_SCALE);
+			table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
+
+			table->Smio[level] |= data->vddc_voltage_table.entries[level].smio_low;
+		}
+
+		table->SmioMask1 = data->vddc_voltage_table.mask_low;
+	}
+
+	return 0;
+}
+
 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 					struct SMU74_Discrete_DpmTable *table)
 {
@@ -689,9 +731,9 @@ static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 
 			table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 		}
-	}
 
-	table->SmioMask1 = data->vddci_voltage_table.mask_low;
+		table->SmioMask1 = data->vddci_voltage_table.mask_low;
+	}
 
 	return 0;
 }
@@ -725,6 +767,7 @@ static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 		struct SMU74_Discrete_DpmTable *table)
 {
+	polaris10_populate_smc_vddc_table(hwmgr, table);
 	polaris10_populate_smc_vddci_table(hwmgr, table);
 	polaris10_populate_smc_mvdd_table(hwmgr, table);
 	polaris10_populate_cac_table(hwmgr, table);
@@ -738,6 +781,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 	struct phm_ppt_v1_information *table_info =
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
+	struct amdgpu_device *adev = hwmgr->adev;
 
 	state->CcPwrDynRm = 0;
 	state->CcPwrDynRm1 = 0;
@@ -746,7 +790,11 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 	state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 			VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 
-	if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker)
+	if ((hwmgr->chip_id == CHIP_POLARIS12) ||
+	    ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
+	    ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
+	    ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) ||
+	    ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
 		state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
 	else
 		state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
@@ -975,6 +1023,16 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
+static void polaris10_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr)
+{
+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+	SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
+	uint8_t shared_rail;
+
+	if (!atomctrl_get_vddc_shared_railinfo(hwmgr, &shared_rail))
+		table->SharedRails = shared_rail;
+}
+
 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -996,6 +1054,13 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
 		lowest_pcie_level_enabled = 0,
 		mid_pcie_level_enabled = 0,
 		count = 0;
+	struct amdgpu_device *adev = hwmgr->adev;
+	pp_atomctrl_clock_dividers_vi dividers;
+	uint32_t dpm0_sclkfrequency = levels[0].SclkSetting.SclkFrequency;
+
+	if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
+	    ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
+		polaris10_get_vddc_shared_railinfo(hwmgr);
 
 	polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
 
@@ -1012,15 +1077,31 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
 			levels[i].DeepSleepDivId = 0;
 	}
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-					PHM_PlatformCaps_SPLLShutdownSupport))
+					PHM_PlatformCaps_SPLLShutdownSupport)) {
 		smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
+		if (dpm0_sclkfrequency != levels[0].SclkSetting.SclkFrequency) {
+			result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+					dpm_table->sclk_table.dpm_levels[0].value,
+					&dividers);
+			PP_ASSERT_WITH_CODE((0 == result),
+					"can not find divide id for sclk",
+					return result);
+			smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_SetGpuPllDfsForSclk,
+					dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ?
+					dividers.pll_post_divider - 1 : dividers.pll_post_divider,
+					NULL);
+		}
+	}
 
-	smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
 	smu_data->smc_state_table.GraphicsDpmLevelCount =
 			(uint8_t)dpm_table->sclk_table.count;
 	hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
 			phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
 
+	for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++)
+		smu_data->smc_state_table.GraphicsLevel[i].EnabledForActivity =
+			(hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask & (1 << i)) >> i;
 
 	if (pcie_table != NULL) {
 		PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
@@ -1110,7 +1191,9 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
 	if (mclk_stutter_mode_threshold &&
 		(clock <= mclk_stutter_mode_threshold) &&
 		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
-				STUTTER_ENABLE) & 0x1))
+				STUTTER_ENABLE) & 0x1) &&
+		(data->display_timing.num_existing_displays <= 2) &&
+		data->display_timing.num_existing_displays)
 		mem_level->StutterEnable = true;
 
 	if (!result) {
@@ -1144,27 +1227,21 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
 		result = polaris10_populate_single_memory_level(hwmgr,
 				dpm_table->mclk_table.dpm_levels[i].value,
 				&levels[i]);
-		if (i == dpm_table->mclk_table.count - 1) {
+		if (i == dpm_table->mclk_table.count - 1)
 			levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
-			levels[i].EnabledForActivity = 1;
-		}
 		if (result)
 			return result;
 	}
 
-	/* In order to prevent MC activity from stutter mode to push DPM up,
-	 * the UVD change complements this by putting the MCLK in
-	 * a higher state by default such that we are not affected by
-	 * up threshold or and MCLK DPM latency.
-	 */
-	levels[0].ActivityLevel = 0x1f;
-	CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
-
 	smu_data->smc_state_table.MemoryDpmLevelCount =
 			(uint8_t)dpm_table->mclk_table.count;
 	hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
 			phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
 
+	for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++)
+		smu_data->smc_state_table.MemoryLevel[i].EnabledForActivity =
+			(hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask & (1 << i)) >> i;
+
 	/* level count will send to smc once at init smc table and never change */
 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
 			(uint32_t)array_size, SMC_RAM_END);
@@ -1275,8 +1352,9 @@ static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
 	table->MemoryACPILevel.UpHyst = 0;
 	table->MemoryACPILevel.DownHyst = 100;
 	table->MemoryACPILevel.VoltageDownHyst = 0;
+	/* To align with the settings from other OSes */
 	table->MemoryACPILevel.ActivityLevel =
-			PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
+			PP_HOST_TO_SMC_US(data->current_profile_setting.sclk_activity);
 
 	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
 	CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
@@ -1334,6 +1412,55 @@ static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
 	return result;
 }
 
+static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
+		SMU74_Discrete_DpmTable *table)
+{
+	int result = -EINVAL;
+	uint8_t count;
+	struct pp_atomctrl_clock_dividers_vi dividers;
+	struct phm_ppt_v1_information *table_info =
+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
+	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
+			table_info->mm_dep_table;
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	uint32_t vddci;
+
+	table->SamuLevelCount = (uint8_t)(mm_table->count);
+	table->SamuBootLevel = 0;
+
+	for (count = 0; count < table->SamuLevelCount; count++) {
+		table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
+		table->SamuLevel[count].MinVoltage |=
+				(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
+
+		if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
+			vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
+						mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
+		else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
+			vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
+		else
+			vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
+
+
+		table->SamuLevel[count].MinVoltage |=
+				(vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
+		table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
+
+		/*retrieve divider value for VBIOS */
+		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
+				table->SamuLevel[count].Frequency, &dividers);
+		PP_ASSERT_WITH_CODE((0 == result),
+				"can not find divide id for VCE engine clock",
+				return result);
+
+		table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
+
+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
+		CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
+	}
+	return result;
+}
+
 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
 		int32_t eng_clock, int32_t mem_clock,
 		SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
@@ -1374,7 +1501,7 @@ static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
 					hw_data->dpm_table.sclk_table.dpm_levels[i].value,
 					hw_data->dpm_table.mclk_table.dpm_levels[j].value,
 					&arb_regs.entries[i][j]);
-			if (result == 0)
+			if (result == 0 && i == 0)
 				result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
 			if (result != 0)
 				return result;
@@ -1460,10 +1587,18 @@ static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
 	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
 			data->vbios_boot_state.sclk_bootup_value,
 			(uint32_t *)&(table->GraphicsBootLevel));
+	if (result) {
+		table->GraphicsBootLevel = 0;
+		result = 0;
+	}
 
 	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
 			data->vbios_boot_state.mclk_bootup_value,
 			(uint32_t *)&(table->MemoryBootLevel));
+	if (result) {
+		table->MemoryBootLevel = 0;
+		result = 0;
+	}
 
 	table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
 			VOLTAGE_SCALE;
@@ -1509,49 +1644,28 @@ static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
+#define STRAP_ASIC_RO_LSB    2168
+#define STRAP_ASIC_RO_MSB    2175
+
 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
 {
-	uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-
-	uint8_t i, stretch_amount, volt_offset = 0;
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 	struct phm_ppt_v1_information *table_info =
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
 	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
 			table_info->vdd_dep_on_sclk;
+	uint32_t ro, efuse, volt_without_cks, volt_with_cks, value;
+	uint8_t i, stretch_amount, volt_offset = 0;
 
 	stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
 
 	/* Read SMU_Eefuse to read and calculate RO and determine
 	 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
 	 */
-	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
-			ixSMU_EFUSE_0 + (67 * 4));
-	efuse &= 0xFF000000;
-	efuse = efuse >> 24;
-
-	if (hwmgr->chip_id == CHIP_POLARIS10) {
-		if (hwmgr->is_kicker) {
-			min = 1200;
-			max = 2500;
-		} else {
-			min = 1000;
-			max = 2300;
-		}
-	} else if (hwmgr->chip_id == CHIP_POLARIS11) {
-		if (hwmgr->is_kicker) {
-			min = 900;
-			max = 2100;
-		} else {
-			min = 1100;
-			max = 2100;
-		}
-	} else {
-		min = 1100;
-		max = 2100;
-	}
-
-	ro = efuse * (max - min) / 255 + min;
+	atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB, &efuse);
+	ro = ((efuse * (data->ro_range_maximum - data->ro_range_minimum)) / 255) +
+		data->ro_range_minimum;
 
 	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
 	for (i = 0; i < sclk_table->count; i++) {
@@ -1576,7 +1690,8 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
 		smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
 	}
 
-	smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
+	smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
+
 	/* Populate CKS Lookup Table */
 	if (stretch_amount == 0 || stretch_amount > 5) {
 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
@@ -1607,6 +1722,9 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
 	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 		config = VR_SVI2_PLANE_1;
 		table->VRConfig |= config;
+	} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
+		config = VR_SMIO_PATTERN_1;
+		table->VRConfig |= config;
 	} else {
 		PP_ASSERT_WITH_CODE(false,
 				"VDDC should be on SVI2 control in merged mode!",
@@ -1625,7 +1743,17 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
 	}
 	/* Set Mvdd Voltage Controller */
 	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
-		config = VR_SVI2_PLANE_2;
+		if (config != VR_SVI2_PLANE_2) {
+			config = VR_SVI2_PLANE_2;
+			table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
+				offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
+		} else {
+			config = VR_STATIC_VOLTAGE;
+			table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
+		}
+	} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
+		config = VR_SMIO_PATTERN_2;
 		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
 			offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
@@ -1660,16 +1788,18 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
 	if (!hwmgr->avfs_supported)
 		return 0;
 
+
+	if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
+		hwmgr->avfs_supported = 0;
+		return 0;
+	}
+
 	result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
 
 	if (0 == result) {
-		if (((adev->pdev->device == 0x67ef) &&
-		     ((adev->pdev->revision == 0xe0) ||
-		      (adev->pdev->revision == 0xe5))) ||
-		    ((adev->pdev->device == 0x67ff) &&
-		     ((adev->pdev->revision == 0xcf) ||
-		      (adev->pdev->revision == 0xef) ||
-		      (adev->pdev->revision == 0xff)))) {
+		if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
+		    ((hwmgr->chip_id == CHIP_POLARIS12) && !ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) ||
+		    ASICID_IS_P21(adev->pdev->device, adev->pdev->revision)) {
 			avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
 			if ((adev->pdev->device == 0x67ef && adev->pdev->revision == 0xe5) ||
 			    (adev->pdev->device == 0x67ff && adev->pdev->revision == 0xef)) {
@@ -1686,32 +1816,21 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
 					avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0;
 					avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b  = 0x23;
 				}
+			} else if (hwmgr->chip_id == CHIP_POLARIS12 && !ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
+				avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0   = 0xF6B024DD;
+				avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1   = 0x3005E;
+				avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2   = 0x18A5F;
+				avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0x315;
+				avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFED1;
+				avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b  = 0x3B;
+			} else if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision)) {
+				avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0   = 0xF843B66B;
+				avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1   = 0x59CB5;
+				avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2   = 0xFFFF287F;
+				avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
+				avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFF23;
+				avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b  = 0x58;
 			}
-		} else if (hwmgr->chip_id == CHIP_POLARIS12 && !hwmgr->is_kicker) {
-			avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
-			avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0   = 0xF6B024DD;
-			avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1   = 0x3005E;
-			avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2   = 0x18A5F;
-			avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0x315;
-			avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFED1;
-			avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b  = 0x3B;
-		} else if (((adev->pdev->device == 0x67df) &&
-			    ((adev->pdev->revision == 0xe0) ||
-			     (adev->pdev->revision == 0xe3) ||
-			     (adev->pdev->revision == 0xe4) ||
-			     (adev->pdev->revision == 0xe5) ||
-			     (adev->pdev->revision == 0xe7) ||
-			     (adev->pdev->revision == 0xef))) ||
-			   ((adev->pdev->device == 0x6fdf) &&
-			    ((adev->pdev->revision == 0xef) ||
-			     (adev->pdev->revision == 0xff)))) {
-			avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
-			avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0   = 0xF843B66B;
-			avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1   = 0x59CB5;
-			avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2   = 0xFFFF287F;
-			avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
-			avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFF23;
-			avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b  = 0x58;
 		}
 	}
 
@@ -1774,33 +1893,6 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
 	return result;
 }
 
-static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
-{
-	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
-	uint32_t tmp;
-	int result;
-
-	/* This is a read-modify-write on the first byte of the ARB table.
-	 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
-	 * is the field 'current'.
-	 * This solution is ugly, but we never write the whole table only
-	 * individual fields in it.
-	 * In reality this field should not be in that structure
-	 * but in a soft register.
-	 */
-	result = smu7_read_smc_sram_dword(hwmgr,
-			smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
-
-	if (result)
-		return result;
-
-	tmp &= 0x00FFFFFF;
-	tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
-
-	return smu7_write_smc_sram_dword(hwmgr,
-			smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
-}
-
 static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
 {
 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
@@ -1830,6 +1922,7 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
 	uint8_t i;
 	struct pp_atomctrl_gpio_pin_assignment gpio_pin;
 	pp_atomctrl_clock_dividers_vi dividers;
+	struct phm_ppt_v1_gpio_table *gpio_table = table_info->gpio_table;
 
 	polaris10_initialize_power_tune_defaults(hwmgr);
 
@@ -1876,6 +1969,10 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
 	PP_ASSERT_WITH_CODE(0 == result,
 			"Failed to initialize VCE Level!", return result);
 
+	result = polaris10_populate_smc_samu_level(hwmgr, table);
+	PP_ASSERT_WITH_CODE(0 == result,
+			"Failed to initialize SAMU Level!", return result);
+
 	/* Since only the initial state is completely set up at this point
 	 * (the other states are just copies of the boot state) we only
 	 * need to populate the  ARB settings for the initial state.
@@ -1900,6 +1997,8 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
 	PP_ASSERT_WITH_CODE(0 == result,
 			"Failed to populate BAPM Parameters!", return result);
 
+	polaris10_populate_zero_rpm_parameters(hwmgr);
+
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_ClockStretcher)) {
 		result = polaris10_populate_clock_stretcher_data_table(hwmgr);
@@ -1928,7 +2027,7 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
 	table->VoltageResponseTime = 0;
 	table->PhaseResponseTime = 0;
 	table->MemoryThermThrottleEnable = 1;
-	table->PCIeBootLinkLevel = 0;
+	table->PCIeBootLinkLevel = hw_data->dpm_table.pcie_speed_table.count;
 	table->PCIeGenInterval = 1;
 	table->VRConfig = 0;
 
@@ -1941,6 +2040,8 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
 
 	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
 		table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
+		if (gpio_table)
+			table->VRHotLevel = gpio_table->vrhot_triggered_sclk_dpm_index;
 	} else {
 		table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
@@ -1950,8 +2051,11 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
 	if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
 			&gpio_pin)) {
 		table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
-		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-				PHM_PlatformCaps_AutomaticDCTransition);
+		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+				PHM_PlatformCaps_AutomaticDCTransition) &&
+		    !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme, NULL))
+			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+					PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 	} else {
 		table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
@@ -2020,10 +2124,6 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
 	PP_ASSERT_WITH_CODE(0 == result,
 			"Failed to upload dpm data to SMC memory!", return result);
 
-	result = polaris10_init_arb_table_index(hwmgr);
-	PP_ASSERT_WITH_CODE(0 == result,
-			"Failed to upload arb data to SMC memory!", return result);
-
 	result = polaris10_populate_pm_fuses(hwmgr);
 	PP_ASSERT_WITH_CODE(0 == result,
 			"Failed to  populate PM fuses to SMC memory!", return result);
@@ -2380,7 +2480,8 @@ static uint32_t polaris10_get_mac_definition(uint32_t value)
 	case SMU_MAX_LEVELS_MVDD:
 		return SMU74_MAX_LEVELS_MVDD;
 	case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
-		return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
+		return SMU7_UVD_MCLK_HANDSHAKE_DISABLE |
+				SMU7_VCE_MCLK_HANDSHAKE_DISABLE;
 	}
 
 	pr_warn("can't get the mac of %x\n", value);
@@ -2458,6 +2559,24 @@ static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
 	return error ? -1 : 0;
 }
 
+static uint8_t polaris10_get_memory_modile_index(struct pp_hwmgr *hwmgr)
+{
+	return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
+}
+
+static int polaris10_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
+{
+	int result;
+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
+	pp_atomctrl_mc_reg_table *mc_reg_table = &smu_data->mc_reg_table;
+	uint8_t module_index = polaris10_get_memory_modile_index(hwmgr);
+
+	memset(mc_reg_table, 0, sizeof(pp_atomctrl_mc_reg_table));
+	result = atomctrl_initialize_mc_reg_table_v2_2(hwmgr, module_index, mc_reg_table);
+
+	return result;
+}
+
 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
 {
 	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
@@ -2584,6 +2703,7 @@ const struct pp_smumgr_func polaris10_smu_funcs = {
 	.populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
 	.populate_all_memory_levels = polaris10_populate_all_memory_levels,
 	.get_mac_definition = polaris10_get_mac_definition,
+	.initialize_mc_reg_table = polaris10_initialize_mc_reg_table,
 	.is_dpm_running = polaris10_is_dpm_running,
 	.is_hw_avfs_present = polaris10_is_hw_avfs_present,
 	.update_dpm_settings = polaris10_update_dpm_settings,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h
index 1ec425df9eda..6f4c48ac34b8 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.h
@@ -60,6 +60,7 @@ struct polaris10_smumgr {
 	struct polaris10_range_table                range_table[NUM_SCLK_RANGE];
 	const struct polaris10_pt_defaults       *power_tune_defaults;
 	uint32_t               bif_sclk_table[SMU74_MAX_LEVELS_LINK];
+	pp_atomctrl_mc_reg_table             mc_reg_table;
 };
 
 
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c
index b6fb48066841..b6921db3c130 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c
@@ -245,3 +245,11 @@ int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t tabl
 
 	return -EINVAL;
 }
+
+int smum_stop_smc(struct pp_hwmgr *hwmgr)
+{
+	if (hwmgr->smumgr_funcs->stop_smc)
+		return hwmgr->smumgr_funcs->stop_smc(hwmgr);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
index 0ecc18b55ffb..38a5cdcf5896 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c
@@ -1495,12 +1495,11 @@ static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
 	struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
 			table_info->vdd_dep_on_sclk;
-	uint32_t mask = (1 << ((STRAP_ASIC_RO_MSB - STRAP_ASIC_RO_LSB) + 1)) - 1;
 
 	stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
 
 	atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB,
-			mask, &efuse);
+			&efuse);
 
 	min = 1200;
 	max = 2500;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index fc4f95fa87cf..39990790ed67 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -33,6 +33,7 @@
 #include "navi10_ppt.h"
 #include "sienna_cichlid_ppt.h"
 #include "renoir_ppt.h"
+#include "vangogh_ppt.h"
 #include "amd_pcie.h"
 
 /*
@@ -396,11 +397,15 @@ static int smu_set_funcs(struct amdgpu_device *adev)
 		break;
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		sienna_cichlid_set_ppt_funcs(smu);
 		break;
 	case CHIP_RENOIR:
 		renoir_set_ppt_funcs(smu);
 		break;
+	case CHIP_VANGOGH:
+		vangogh_set_ppt_funcs(smu);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -469,6 +474,9 @@ static int smu_late_init(void *handle)
 	struct smu_context *smu = &adev->smu;
 	int ret = 0;
 
+	if (adev->asic_type == CHIP_VANGOGH)
+		return 0;
+
 	if (!smu->pm_enabled)
 		return 0;
 
@@ -1029,17 +1037,6 @@ static int smu_smc_hw_setup(struct smu_context *smu)
 		return ret;
 	}
 
-	/*
-	 * Set initialized values (get from vbios) to dpm tables context such as
-	 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
-	 * type of clks.
-	 */
-	ret = smu_set_default_dpm_table(smu);
-	if (ret) {
-		dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
-		return ret;
-	}
-
 	ret = smu_notify_display_change(smu);
 	if (ret)
 		return ret;
@@ -1370,96 +1367,11 @@ int smu_display_configuration_change(struct smu_context *smu,
 			num_of_active_display++;
 	}
 
-	smu_set_active_display_count(smu, num_of_active_display);
-
-	smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
-			   display_config->cpu_cc6_disable,
-			   display_config->cpu_pstate_disable,
-			   display_config->nb_pstate_switch_disable);
-
 	mutex_unlock(&smu->mutex);
 
 	return 0;
 }
 
-static int smu_get_clock_info(struct smu_context *smu,
-			      struct smu_clock_info *clk_info,
-			      enum smu_perf_level_designation designation)
-{
-	int ret;
-	struct smu_performance_level level = {0};
-
-	if (!clk_info)
-		return -EINVAL;
-
-	ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
-	if (ret)
-		return -EINVAL;
-
-	clk_info->min_mem_clk = level.memory_clock;
-	clk_info->min_eng_clk = level.core_clock;
-	clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
-
-	ret = smu_get_perf_level(smu, designation, &level);
-	if (ret)
-		return -EINVAL;
-
-	clk_info->min_mem_clk = level.memory_clock;
-	clk_info->min_eng_clk = level.core_clock;
-	clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
-
-	return 0;
-}
-
-int smu_get_current_clocks(struct smu_context *smu,
-			   struct amd_pp_clock_info *clocks)
-{
-	struct amd_pp_simple_clock_info simple_clocks = {0};
-	struct smu_clock_info hw_clocks;
-	int ret = 0;
-
-	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
-		return -EOPNOTSUPP;
-
-	mutex_lock(&smu->mutex);
-
-	smu_get_dal_power_level(smu, &simple_clocks);
-
-	if (smu->support_power_containment)
-		ret = smu_get_clock_info(smu, &hw_clocks,
-					 PERF_LEVEL_POWER_CONTAINMENT);
-	else
-		ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
-
-	if (ret) {
-		dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
-		goto failed;
-	}
-
-	clocks->min_engine_clock = hw_clocks.min_eng_clk;
-	clocks->max_engine_clock = hw_clocks.max_eng_clk;
-	clocks->min_memory_clock = hw_clocks.min_mem_clk;
-	clocks->max_memory_clock = hw_clocks.max_mem_clk;
-	clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
-	clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
-	clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
-	clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
-
-        if (simple_clocks.level == 0)
-                clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
-        else
-                clocks->max_clocks_state = simple_clocks.level;
-
-        if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
-                clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
-                clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
-        }
-
-failed:
-	mutex_unlock(&smu->mutex);
-	return ret;
-}
-
 static int smu_set_clockgating_state(void *handle,
 				     enum amd_clockgating_state state)
 {
@@ -1491,6 +1403,7 @@ static int smu_enable_umd_pstate(void *handle,
 		if (*level & profile_mode_mask) {
 			smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
 			smu_dpm_ctx->enable_umd_pstate = true;
+			smu_gpo_control(smu, false);
 			amdgpu_device_ip_set_powergating_state(smu->adev,
 							       AMD_IP_BLOCK_TYPE_GFX,
 							       AMD_PG_STATE_UNGATE);
@@ -1499,6 +1412,7 @@ static int smu_enable_umd_pstate(void *handle,
 							       AMD_CG_STATE_UNGATE);
 			smu_gfx_ulv_control(smu, false);
 			smu_deep_sleep_control(smu, false);
+			amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
 		}
 	} else {
 		/* exit umd pstate, restore level, enable gfx cg*/
@@ -1506,6 +1420,7 @@ static int smu_enable_umd_pstate(void *handle,
 			if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
 				*level = smu_dpm_ctx->saved_dpm_level;
 			smu_dpm_ctx->enable_umd_pstate = false;
+			amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
 			smu_deep_sleep_control(smu, true);
 			smu_gfx_ulv_control(smu, true);
 			amdgpu_device_ip_set_clockgating_state(smu->adev,
@@ -1514,6 +1429,7 @@ static int smu_enable_umd_pstate(void *handle,
 			amdgpu_device_ip_set_powergating_state(smu->adev,
 							       AMD_IP_BLOCK_TYPE_GFX,
 							       AMD_PG_STATE_GATE);
+			smu_gpo_control(smu, true);
 		}
 	}
 
@@ -1592,9 +1508,6 @@ int smu_handle_task(struct smu_context *smu,
 		ret = smu_pre_display_config_changed(smu);
 		if (ret)
 			goto out;
-		ret = smu_set_cpu_power_state(smu);
-		if (ret)
-			goto out;
 		ret = smu_adjust_power_state_dynamic(smu, level, false);
 		break;
 	case AMD_PP_TASK_COMPLETE_INIT:
@@ -2044,40 +1957,6 @@ int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, ch
 	return ret;
 }
 
-int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
-{
-	int ret = 0;
-
-	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
-		return -EOPNOTSUPP;
-
-	mutex_lock(&smu->mutex);
-
-	if (smu->ppt_funcs->get_od_percentage)
-		ret = smu->ppt_funcs->get_od_percentage(smu, type);
-
-	mutex_unlock(&smu->mutex);
-
-	return ret;
-}
-
-int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
-{
-	int ret = 0;
-
-	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
-		return -EOPNOTSUPP;
-
-	mutex_lock(&smu->mutex);
-
-	if (smu->ppt_funcs->set_od_percentage)
-		ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
-
-	mutex_unlock(&smu->mutex);
-
-	return ret;
-}
-
 int smu_od_edit_dpm_table(struct smu_context *smu,
 			  enum PP_OD_DPM_TABLE_COMMAND type,
 			  long *input, uint32_t size)
@@ -2318,43 +2197,6 @@ int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
 	return ret;
 }
 
-int smu_get_clock_by_type(struct smu_context *smu,
-			  enum amd_pp_clock_type type,
-			  struct amd_pp_clocks *clocks)
-{
-	int ret = 0;
-
-	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
-		return -EOPNOTSUPP;
-
-	mutex_lock(&smu->mutex);
-
-	if (smu->ppt_funcs->get_clock_by_type)
-		ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
-
-	mutex_unlock(&smu->mutex);
-
-	return ret;
-}
-
-int smu_get_max_high_clocks(struct smu_context *smu,
-			    struct amd_pp_simple_clock_info *clocks)
-{
-	int ret = 0;
-
-	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
-		return -EOPNOTSUPP;
-
-	mutex_lock(&smu->mutex);
-
-	if (smu->ppt_funcs->get_max_high_clocks)
-		ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
-
-	mutex_unlock(&smu->mutex);
-
-	return ret;
-}
-
 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
 				       enum smu_clk_type clk_type,
 				       struct pp_clock_levels_with_latency *clocks)
@@ -2374,26 +2216,6 @@ int smu_get_clock_by_type_with_latency(struct smu_context *smu,
 	return ret;
 }
 
-int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
-				       enum amd_pp_clock_type type,
-				       struct pp_clock_levels_with_voltage *clocks)
-{
-	int ret = 0;
-
-	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
-		return -EOPNOTSUPP;
-
-	mutex_lock(&smu->mutex);
-
-	if (smu->ppt_funcs->get_clock_by_type_with_voltage)
-		ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
-
-	mutex_unlock(&smu->mutex);
-
-	return ret;
-}
-
-
 int smu_display_clock_voltage_request(struct smu_context *smu,
 				      struct pp_display_clock_request *clock_req)
 {
@@ -2430,23 +2252,6 @@ int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disabl
 	return ret;
 }
 
-int smu_notify_smu_enable_pwe(struct smu_context *smu)
-{
-	int ret = 0;
-
-	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
-		return -EOPNOTSUPP;
-
-	mutex_lock(&smu->mutex);
-
-	if (smu->ppt_funcs->notify_smu_enable_pwe)
-		ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
-
-	mutex_unlock(&smu->mutex);
-
-	return ret;
-}
-
 int smu_set_xgmi_pstate(struct smu_context *smu,
 			uint32_t pstate)
 {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile b/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile
index f98d97192635..0138c982dfd3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/Makefile
@@ -26,6 +26,7 @@
 SMU11_MGR = arcturus_ppt.o \
 	    navi10_ppt.o \
 	    sienna_cichlid_ppt.o \
+	    vangogh_ppt.o \
 	    smu_v11_0.o
 
 AMD_SWSMU_SMU11MGR = $(addprefix $(AMD_SWSMU_PATH)/smu11/,$(SMU11_MGR))
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index fc376281e629..4fd850e58004 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -717,6 +717,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
 	struct smu_11_0_dpm_table *single_dpm_table;
 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 	struct smu_11_0_dpm_context *dpm_context = NULL;
+	uint32_t gen_speed, lane_width;
 
 	if (amdgpu_ras_intr_triggered())
 		return snprintf(buf, PAGE_SIZE, "unavailable\n");
@@ -820,6 +821,23 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
 				now) ? "*" : ""));
 		break;
 
+	case SMU_PCIE:
+		gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
+		lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
+		size += sprintf(buf + size, "0: %s %s %dMhz *\n",
+				(gen_speed == 0) ? "2.5GT/s," :
+				(gen_speed == 1) ? "5.0GT/s," :
+				(gen_speed == 2) ? "8.0GT/s," :
+				(gen_speed == 3) ? "16.0GT/s," : "",
+				(lane_width == 1) ? "x1" :
+				(lane_width == 2) ? "x2" :
+				(lane_width == 3) ? "x4" :
+				(lane_width == 4) ? "x8" :
+				(lane_width == 5) ? "x12" :
+				(lane_width == 6) ? "x16" : "",
+				smu->smu_table.boot_values.lclk / 100);
+		break;
+
 	default:
 		break;
 	}
@@ -1121,14 +1139,9 @@ static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
 	if (!speed)
 		return -EINVAL;
 
-	switch (smu_v11_0_get_fan_control_mode(smu)) {
-	case AMD_FAN_CTRL_AUTO:
-		return arcturus_get_smu_metrics_data(smu,
-						     METRICS_CURR_FANSPEED,
-						     speed);
-	default:
-		return smu_v11_0_get_fan_speed_rpm(smu, speed);
-	}
+	return arcturus_get_smu_metrics_data(smu,
+					     METRICS_CURR_FANSPEED,
+					     speed);
 }
 
 static int arcturus_get_fan_parameters(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 895d89bea7fa..0600befc6e4c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -127,6 +127,7 @@ static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT]
 	MSG_MAP(ArmD3,				PPSMC_MSG_ArmD3,                       0),
 	MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,		       0),
 	MSG_MAP(SetMGpuFanBoostLimitRpm,	PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
+	MSG_MAP(SetGpoFeaturePMask,		PPSMC_MSG_SetGpoFeaturePMask,          0),
 };
 
 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
@@ -2278,7 +2279,6 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
 	dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
 	dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
 	dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
-	dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
 
 	dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
 	dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
@@ -2719,6 +2719,26 @@ static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
 					       NULL);
 }
 
+static int sienna_cichlid_gpo_control(struct smu_context *smu,
+				      bool enablement)
+{
+	int ret = 0;
+
+	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
+		if (enablement)
+			ret = smu_cmn_send_smc_msg_with_param(smu,
+							SMU_MSG_SetGpoFeaturePMask,
+							GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
+							NULL);
+		else
+			ret = smu_cmn_send_smc_msg_with_param(smu,
+							SMU_MSG_SetGpoFeaturePMask,
+							0,
+							NULL);
+	}
+
+	return ret;
+}
 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
 	.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
 	.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
@@ -2800,6 +2820,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
 	.deep_sleep_control = smu_v11_0_deep_sleep_control,
 	.get_fan_parameters = sienna_cichlid_get_fan_parameters,
 	.interrupt_work = smu_v11_0_interrupt_work,
+	.gpo_control = sienna_cichlid_gpo_control,
 };
 
 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 2380759ddf48..b6453ee6f8e6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -62,6 +62,7 @@ MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
+MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
 
 #define SMU11_VOLTAGE_SCALE 4
 
@@ -84,7 +85,7 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
 {
 	struct amdgpu_device *adev = smu->adev;
 	const char *chip_name;
-	char fw_name[30];
+	char fw_name[SMU_FW_NAME_LEN];
 	int err = 0;
 	const struct smc_firmware_header_v1_0 *hdr;
 	const struct common_firmware_header *header;
@@ -109,6 +110,9 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
 	case CHIP_NAVY_FLOUNDER:
 		chip_name = "navy_flounder";
 		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		chip_name = "dimgrey_cavefish";
+		break;
 	default:
 		dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
 		return -EINVAL;
@@ -244,6 +248,12 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
 	case CHIP_NAVY_FLOUNDER:
 		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
 		break;
+	case CHIP_VANGOGH:
+		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
+		break;
+	case CHIP_DIMGREY_CAVEFISH:
+		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
+		break;
 	default:
 		dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
 		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
@@ -327,7 +337,7 @@ int smu_v11_0_setup_pptable(struct smu_context *smu)
 		version_major = le16_to_cpu(hdr->header.header_version_major);
 		version_minor = le16_to_cpu(hdr->header.header_version_minor);
 		if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) ||
-			adev->asic_type == CHIP_NAVY_FLOUNDER) {
+		    adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
 			dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 			switch (version_minor) {
 			case 0:
@@ -592,6 +602,11 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 						 (uint8_t)SMU11_SYSPLL1_2_ID,
 						 &smu->smu_table.boot_values.fclk);
 
+	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
+					 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
+					 (uint8_t)SMU11_SYSPLL3_1_ID,
+					 &smu->smu_table.boot_values.lclk);
+
 	return 0;
 }
 
@@ -699,8 +714,11 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 {
 	struct amdgpu_device *adev = smu->adev;
 
-	/* Navy_Flounder do not support to change display num currently */
-	if (adev->asic_type == CHIP_NAVY_FLOUNDER)
+	/* Navy_Flounder/Dimgrey_Cavefish do not support to change
+	 * display num currently
+	 */
+	if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
+	    adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
 		return 0;
 
 	return smu_cmn_send_smc_msg_with_param(smu,
@@ -1068,6 +1086,7 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
 	case CHIP_NAVI12:
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+	case CHIP_DIMGREY_CAVEFISH:
 		if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 			return 0;
 		if (enable)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
new file mode 100644
index 000000000000..83a1b0a04eb1
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -0,0 +1,619 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#define SWSMU_CODE_LAYER_L2
+
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "smu_v11_0.h"
+#include "smu11_driver_if_vangogh.h"
+#include "vangogh_ppt.h"
+#include "smu_v11_5_ppsmc.h"
+#include "smu_v11_5_pmfw.h"
+#include "smu_cmn.h"
+
+/*
+ * DO NOT use these for err/warn/info/debug messages.
+ * Use dev_err, dev_warn, dev_info and dev_dbg instead.
+ * They are more MGPU friendly.
+ */
+#undef pr_err
+#undef pr_warn
+#undef pr_info
+#undef pr_debug
+
+#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMC_DPM_FEATURE ( \
+	FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
+	FEATURE_MASK(FEATURE_VCN_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_FCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_LCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
+	FEATURE_MASK(FEATURE_GFX_DPM_BIT))
+
+static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
+	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,			0),
+	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,		0),
+	MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,	0),
+	MSG_MAP(EnableGfxOff,                   PPSMC_MSG_EnableGfxOff,			0),
+	MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisableGfxOff,		0),
+	MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile,	0),
+	MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile,		0),
+	MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,			0),
+	MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,			0),
+	MSG_MAP(Spare,                          PPSMC_MSG_spare,				0),
+	MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,		0),
+	MSG_MAP(SetSoftMinGfxclk,               PPSMC_MSG_SetSoftMinGfxclk,		0),
+	MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify,		0),
+	MSG_MAP(SetHardMinIspiclkByFreq,        PPSMC_MSG_SetHardMinIspiclkByFreq,	0),
+	MSG_MAP(SetHardMinIspxclkByFreq,        PPSMC_MSG_SetHardMinIspxclkByFreq,	0),
+	MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,	0),
+	MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,		0),
+	MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,	0),
+	MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,	0),
+	MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,		0),
+	MSG_MAP(GetEnabledSmuFeatures,          PPSMC_MSG_GetEnabledSmuFeatures,	0),
+	MSG_MAP(Spare1,                         PPSMC_MSG_spare1,					0),
+	MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,	0),
+	MSG_MAP(SetSoftMinFclk,                 PPSMC_MSG_SetSoftMinFclk,		0),
+	MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,		0),
+	MSG_MAP(EnablePostCode,                 PPSMC_MSG_EnablePostCode,		0),
+	MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency,	0),
+	MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency,		0),
+	MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,		0),
+	MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,		0),
+	MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,	0),
+	MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,		0),
+	MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,			0),
+	MSG_MAP(Spare2,                         PPSMC_MSG_spare2,					0),
+	MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage,	0),
+	MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,			0),
+	MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,				0),
+	MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,		0),
+	MSG_MAP(SetSoftMinSocclkByFreq,         PPSMC_MSG_SetSoftMinSocclkByFreq,	0),
+	MSG_MAP(PowerUpCvip,                    PPSMC_MSG_PowerUpCvip,				0),
+	MSG_MAP(PowerDownCvip,                  PPSMC_MSG_PowerDownCvip,			0),
+	MSG_MAP(GetPptLimit,                        PPSMC_MSG_GetPptLimit,			0),
+	MSG_MAP(GetThermalLimit,                    PPSMC_MSG_GetThermalLimit,		0),
+	MSG_MAP(GetCurrentTemperature,              PPSMC_MSG_GetCurrentTemperature, 0),
+	MSG_MAP(GetCurrentPower,                    PPSMC_MSG_GetCurrentPower,		 0),
+	MSG_MAP(GetCurrentVoltage,                  PPSMC_MSG_GetCurrentVoltage,	 0),
+	MSG_MAP(GetCurrentCurrent,                  PPSMC_MSG_GetCurrentCurrent,	 0),
+	MSG_MAP(GetAverageCpuActivity,              PPSMC_MSG_GetAverageCpuActivity, 0),
+	MSG_MAP(GetAverageGfxActivity,              PPSMC_MSG_GetAverageGfxActivity, 0),
+	MSG_MAP(GetAveragePower,                    PPSMC_MSG_GetAveragePower,		 0),
+	MSG_MAP(GetAverageTemperature,              PPSMC_MSG_GetAverageTemperature, 0),
+	MSG_MAP(SetAveragePowerTimeConstant,        PPSMC_MSG_SetAveragePowerTimeConstant,			0),
+	MSG_MAP(SetAverageActivityTimeConstant,     PPSMC_MSG_SetAverageActivityTimeConstant,		0),
+	MSG_MAP(SetAverageTemperatureTimeConstant,  PPSMC_MSG_SetAverageTemperatureTimeConstant,	0),
+	MSG_MAP(SetMitigationEndHysteresis,         PPSMC_MSG_SetMitigationEndHysteresis,			0),
+	MSG_MAP(GetCurrentFreq,                     PPSMC_MSG_GetCurrentFreq,						0),
+	MSG_MAP(SetReducedPptLimit,                 PPSMC_MSG_SetReducedPptLimit,					0),
+	MSG_MAP(SetReducedThermalLimit,             PPSMC_MSG_SetReducedThermalLimit,				0),
+	MSG_MAP(DramLogSetDramAddr,                 PPSMC_MSG_DramLogSetDramAddr,					0),
+	MSG_MAP(StartDramLogging,                   PPSMC_MSG_StartDramLogging,						0),
+	MSG_MAP(StopDramLogging,                    PPSMC_MSG_StopDramLogging,						0),
+	MSG_MAP(SetSoftMinCclk,                     PPSMC_MSG_SetSoftMinCclk,						0),
+	MSG_MAP(SetSoftMaxCclk,                     PPSMC_MSG_SetSoftMaxCclk,						0),
+};
+
+static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
+	FEA_MAP(PPT),
+	FEA_MAP(TDC),
+	FEA_MAP(THERMAL),
+	FEA_MAP(DS_GFXCLK),
+	FEA_MAP(DS_SOCCLK),
+	FEA_MAP(DS_LCLK),
+	FEA_MAP(DS_FCLK),
+	FEA_MAP(DS_MP1CLK),
+	FEA_MAP(DS_MP0CLK),
+	FEA_MAP(ATHUB_PG),
+	FEA_MAP(CCLK_DPM),
+	FEA_MAP(FAN_CONTROLLER),
+	FEA_MAP(ULV),
+	FEA_MAP(VCN_DPM),
+	FEA_MAP(LCLK_DPM),
+	FEA_MAP(SHUBCLK_DPM),
+	FEA_MAP(DCFCLK_DPM),
+	FEA_MAP(DS_DCFCLK),
+	FEA_MAP(S0I2),
+	FEA_MAP(SMU_LOW_POWER),
+	FEA_MAP(GFX_DEM),
+	FEA_MAP(PSI),
+	FEA_MAP(PROCHOT),
+	FEA_MAP(CPUOFF),
+	FEA_MAP(STAPM),
+	FEA_MAP(S0I3),
+	FEA_MAP(DF_CSTATES),
+	FEA_MAP(PERF_LIMIT),
+	FEA_MAP(CORE_DLDO),
+	FEA_MAP(RSMU_LOW_POWER),
+	FEA_MAP(SMN_LOW_POWER),
+	FEA_MAP(THM_LOW_POWER),
+	FEA_MAP(SMUIO_LOW_POWER),
+	FEA_MAP(MP1_LOW_POWER),
+	FEA_MAP(DS_VCN),
+	FEA_MAP(CPPC),
+	FEA_MAP(OS_CSTATES),
+	FEA_MAP(ISP_DPM),
+	FEA_MAP(A55_DPM),
+	FEA_MAP(CVIP_DSP_DPM),
+	FEA_MAP(MSMU_LOW_POWER),
+};
+
+static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
+	TAB_MAP_VALID(WATERMARKS),
+	TAB_MAP_VALID(SMU_METRICS),
+	TAB_MAP_VALID(CUSTOM_DPM),
+	TAB_MAP_VALID(DPMCLOCKS),
+};
+
+static int vangogh_tables_init(struct smu_context *smu)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+	struct smu_table *tables = smu_table->tables;
+
+	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
+		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+	SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
+		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+	SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
+		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+	SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
+		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+	if (!smu_table->metrics_table)
+		goto err0_out;
+	smu_table->metrics_time = 0;
+
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0);
+	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
+	if (!smu_table->gpu_metrics_table)
+		goto err1_out;
+
+	smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
+	if (!smu_table->watermarks_table)
+		goto err2_out;
+
+	return 0;
+
+err2_out:
+	kfree(smu_table->gpu_metrics_table);
+err1_out:
+	kfree(smu_table->metrics_table);
+err0_out:
+	return -ENOMEM;
+}
+
+static int vangogh_get_smu_metrics_data(struct smu_context *smu,
+				       MetricsMember_t member,
+				       uint32_t *value)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+
+	SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
+	int ret = 0;
+
+	mutex_lock(&smu->metrics_lock);
+
+	ret = smu_cmn_get_metrics_table_locked(smu,
+					       NULL,
+					       false);
+	if (ret) {
+		mutex_unlock(&smu->metrics_lock);
+		return ret;
+	}
+
+	switch (member) {
+	case METRICS_AVERAGE_GFXCLK:
+		*value = metrics->GfxclkFrequency;
+		break;
+	case METRICS_AVERAGE_SOCCLK:
+		*value = metrics->SocclkFrequency;
+		break;
+	case METRICS_AVERAGE_UCLK:
+		*value = metrics->MemclkFrequency;
+		break;
+	case METRICS_AVERAGE_GFXACTIVITY:
+		*value = metrics->GfxActivity / 100;
+		break;
+	case METRICS_AVERAGE_VCNACTIVITY:
+		*value = metrics->UvdActivity;
+		break;
+	case METRICS_AVERAGE_SOCKETPOWER:
+		*value = metrics->CurrentSocketPower;
+		break;
+	case METRICS_TEMPERATURE_EDGE:
+		*value = metrics->GfxTemperature / 100 *
+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+		break;
+	case METRICS_TEMPERATURE_HOTSPOT:
+		*value = metrics->SocTemperature / 100 *
+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+		break;
+	case METRICS_THROTTLER_STATUS:
+		*value = metrics->ThrottlerStatus;
+		break;
+	default:
+		*value = UINT_MAX;
+		break;
+	}
+
+	mutex_unlock(&smu->metrics_lock);
+
+	return ret;
+}
+
+static int vangogh_allocate_dpm_context(struct smu_context *smu)
+{
+	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
+
+	smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
+				       GFP_KERNEL);
+	if (!smu_dpm->dpm_context)
+		return -ENOMEM;
+
+	smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
+
+	return 0;
+}
+
+static int vangogh_init_smc_tables(struct smu_context *smu)
+{
+	int ret = 0;
+
+	ret = vangogh_tables_init(smu);
+	if (ret)
+		return ret;
+
+	ret = vangogh_allocate_dpm_context(smu);
+	if (ret)
+		return ret;
+
+	return smu_v11_0_init_smc_tables(smu);
+}
+
+static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+{
+	int ret = 0;
+
+	if (enable) {
+		/* vcn dpm on is a prerequisite for vcn power gate messages */
+		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
+			if (ret)
+				return ret;
+		}
+	} else {
+		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return ret;
+}
+
+static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
+{
+	int ret = 0;
+
+	if (enable) {
+		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
+			if (ret)
+				return ret;
+		}
+	} else {
+		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return ret;
+}
+
+static int vangogh_get_allowed_feature_mask(struct smu_context *smu,
+					    uint32_t *feature_mask,
+					    uint32_t num)
+{
+	struct amdgpu_device *adev = smu->adev;
+
+	if (num > 2)
+		return -EINVAL;
+
+	memset(feature_mask, 0, sizeof(uint32_t) * num);
+
+	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DPM_BIT)
+				| FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)
+				| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
+				| FEATURE_MASK(FEATURE_PPT_BIT)
+				| FEATURE_MASK(FEATURE_TDC_BIT)
+				| FEATURE_MASK(FEATURE_FAN_CONTROLLER_BIT)
+				| FEATURE_MASK(FEATURE_DS_LCLK_BIT)
+				| FEATURE_MASK(FEATURE_DS_DCFCLK_BIT);
+
+	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
+		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT);
+
+	if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
+		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT);
+
+	if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
+		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
+
+	return 0;
+}
+
+static bool vangogh_is_dpm_running(struct smu_context *smu)
+{
+	int ret = 0;
+	uint32_t feature_mask[2];
+	uint64_t feature_enabled;
+
+	ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+
+	if (ret)
+		return false;
+
+	feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+				((uint64_t)feature_mask[1] << 32));
+
+	return !!(feature_enabled & SMC_DPM_FEATURE);
+}
+
+static int vangogh_get_current_activity_percent(struct smu_context *smu,
+					       enum amd_pp_sensors sensor,
+					       uint32_t *value)
+{
+	int ret = 0;
+
+	if (!value)
+		return -EINVAL;
+
+	switch (sensor) {
+	case AMDGPU_PP_SENSOR_GPU_LOAD:
+		ret = vangogh_get_smu_metrics_data(smu,
+						  METRICS_AVERAGE_GFXACTIVITY,
+						  value);
+		break;
+	default:
+		dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int vangogh_get_gpu_power(struct smu_context *smu, uint32_t *value)
+{
+	if (!value)
+		return -EINVAL;
+
+	return vangogh_get_smu_metrics_data(smu,
+					   METRICS_AVERAGE_SOCKETPOWER,
+					   value);
+}
+
+static int vangogh_thermal_get_temperature(struct smu_context *smu,
+					     enum amd_pp_sensors sensor,
+					     uint32_t *value)
+{
+	int ret = 0;
+
+	if (!value)
+		return -EINVAL;
+
+	switch (sensor) {
+	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+		ret = vangogh_get_smu_metrics_data(smu,
+						  METRICS_TEMPERATURE_HOTSPOT,
+						  value);
+		break;
+	case AMDGPU_PP_SENSOR_EDGE_TEMP:
+		ret = vangogh_get_smu_metrics_data(smu,
+						  METRICS_TEMPERATURE_EDGE,
+						  value);
+		break;
+	default:
+		dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static int vangogh_get_current_clk_freq_by_table(struct smu_context *smu,
+				       enum smu_clk_type clk_type,
+				       uint32_t *value)
+{
+	MetricsMember_t member_type;
+
+	switch (clk_type) {
+	case SMU_GFXCLK:
+		member_type = METRICS_AVERAGE_GFXCLK;
+		break;
+	case SMU_MCLK:
+	case SMU_UCLK:
+		member_type = METRICS_AVERAGE_UCLK;
+		break;
+	case SMU_SOCCLK:
+		member_type = METRICS_AVERAGE_SOCCLK;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return vangogh_get_smu_metrics_data(smu,
+					   member_type,
+					   value);
+}
+
+static int vangogh_read_sensor(struct smu_context *smu,
+				 enum amd_pp_sensors sensor,
+				 void *data, uint32_t *size)
+{
+	int ret = 0;
+
+	if (!data || !size)
+		return -EINVAL;
+
+	mutex_lock(&smu->sensor_lock);
+	switch (sensor) {
+	case AMDGPU_PP_SENSOR_GPU_LOAD:
+		ret = vangogh_get_current_activity_percent(smu, sensor, (uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_GPU_POWER:
+		ret = vangogh_get_gpu_power(smu, (uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_EDGE_TEMP:
+	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+		ret = vangogh_thermal_get_temperature(smu, sensor, (uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_GFX_MCLK:
+		ret = vangogh_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
+		*(uint32_t *)data *= 100;
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_GFX_SCLK:
+		ret = vangogh_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
+		*(uint32_t *)data *= 100;
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_VDDGFX:
+		ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
+		*size = 4;
+		break;
+	default:
+		ret = -EOPNOTSUPP;
+		break;
+	}
+	mutex_unlock(&smu->sensor_lock);
+
+	return ret;
+}
+
+static int vangogh_set_watermarks_table(struct smu_context *smu,
+				       struct pp_smu_wm_range_sets *clock_ranges)
+{
+	int i;
+	int ret = 0;
+	Watermarks_t *table = smu->smu_table.watermarks_table;
+
+	if (!table || !clock_ranges)
+		return -EINVAL;
+
+	if (clock_ranges) {
+		if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
+		    clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
+			return -EINVAL;
+
+		for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
+			table->WatermarkRow[WM_DCFCLK][i].MinClock =
+				clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
+			table->WatermarkRow[WM_DCFCLK][i].MaxClock =
+				clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
+			table->WatermarkRow[WM_DCFCLK][i].MinMclk =
+				clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
+			table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
+				clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
+
+			table->WatermarkRow[WM_DCFCLK][i].WmSetting =
+				clock_ranges->reader_wm_sets[i].wm_inst;
+		}
+
+		for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
+			table->WatermarkRow[WM_SOCCLK][i].MinClock =
+				clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
+			table->WatermarkRow[WM_SOCCLK][i].MaxClock =
+				clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
+			table->WatermarkRow[WM_SOCCLK][i].MinMclk =
+				clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
+			table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
+				clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
+
+			table->WatermarkRow[WM_SOCCLK][i].WmSetting =
+				clock_ranges->writer_wm_sets[i].wm_inst;
+		}
+
+		smu->watermarks_bitmap |= WATERMARKS_EXIST;
+	}
+
+	/* pass data to smu controller */
+	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+		ret = smu_cmn_write_watermarks_table(smu);
+		if (ret) {
+			dev_err(smu->adev->dev, "Failed to update WMTABLE!");
+			return ret;
+		}
+		smu->watermarks_bitmap |= WATERMARKS_LOADED;
+	}
+
+	return 0;
+}
+
+static const struct pptable_funcs vangogh_ppt_funcs = {
+
+	.check_fw_status = smu_v11_0_check_fw_status,
+	.check_fw_version = smu_v11_0_check_fw_version,
+	.init_smc_tables = vangogh_init_smc_tables,
+	.fini_smc_tables = smu_v11_0_fini_smc_tables,
+	.init_power = smu_v11_0_init_power,
+	.fini_power = smu_v11_0_fini_power,
+	.register_irq_handler = smu_v11_0_register_irq_handler,
+	.get_allowed_feature_mask = vangogh_get_allowed_feature_mask,
+	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
+	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
+	.send_smc_msg = smu_cmn_send_smc_msg,
+	.dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
+	.dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
+	.is_dpm_running = vangogh_is_dpm_running,
+	.read_sensor = vangogh_read_sensor,
+	.get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,
+	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
+	.set_watermarks_table = vangogh_set_watermarks_table,
+	.set_driver_table_location = smu_v11_0_set_driver_table_location,
+	.disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
+	.interrupt_work = smu_v11_0_interrupt_work,
+};
+
+void vangogh_set_ppt_funcs(struct smu_context *smu)
+{
+	smu->ppt_funcs = &vangogh_ppt_funcs;
+	smu->message_map = vangogh_message_map;
+	smu->feature_map = vangogh_feature_mask_map;
+	smu->table_map = vangogh_table_map;
+	smu->is_apu = true;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
new file mode 100644
index 000000000000..8756766296cd
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __VANGOGH_PPT_H__
+#define __VANGOGH_PPT_H__
+
+
+extern void vangogh_set_ppt_funcs(struct smu_context *smu);
+
+/* UMD PState Vangogh Msg Parameters in MHz */
+#define VANGOGH_UMD_PSTATE_GFXCLK       700
+#define VANGOGH_UMD_PSTATE_SOCCLK       678
+#define VANGOGH_UMD_PSTATE_FCLK         800
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 92b2ea4c197b..dc28f22aeb38 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -346,6 +346,43 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
 	return ret;
 }
 
+int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
+					uint32_t *feature_mask,
+					uint32_t num)
+{
+	uint32_t feature_mask_en_low = 0;
+	uint32_t feature_mask_en_high = 0;
+	struct smu_feature *feature = &smu->smu_feature;
+	int ret = 0;
+
+	if (!feature_mask || num < 2)
+		return -EINVAL;
+
+	if (bitmap_empty(feature->enabled, feature->feature_num)) {
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetEnabledSmuFeatures, 0,
+										 &feature_mask_en_low);
+
+		if (ret)
+			return ret;
+
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetEnabledSmuFeatures, 1,
+										 &feature_mask_en_high);
+
+		if (ret)
+			return ret;
+
+		feature_mask[0] = feature_mask_en_low;
+		feature_mask[1] = feature_mask_en_high;
+
+	} else {
+		bitmap_copy((unsigned long *)feature_mask, feature->enabled,
+				 feature->feature_num);
+	}
+
+	return ret;
+
+}
+
 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
 					uint64_t feature_mask,
 					bool enabled)
@@ -437,11 +474,19 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
 	size_t size = 0;
 	int ret = 0, i;
 
-	ret = smu_cmn_get_enabled_mask(smu,
-				       feature_mask,
-				       2);
-	if (ret)
-		return 0;
+	if (!smu->is_apu) {
+		ret = smu_cmn_get_enabled_mask(smu,
+						feature_mask,
+						2);
+		if (ret)
+			return 0;
+	} else {
+		ret = smu_cmn_get_enabled_32_bits_mask(smu,
+					feature_mask,
+					2);
+		if (ret)
+			return 0;
+	}
 
 	size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
 			feature_mask[1], feature_mask[0]);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index ab577be23c15..01e825d83d8d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -52,6 +52,10 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
 			     uint32_t *feature_mask,
 			     uint32_t num);
 
+int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
+					uint32_t *feature_mask,
+					uint32_t num);
+
 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
 					uint64_t feature_mask,
 					bool enabled);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
index c5adbe46ba0d..f7be2d1a0ff2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
@@ -42,7 +42,6 @@
 #define smu_check_fw_version(smu)					smu_ppt_funcs(check_fw_version, 0, smu)
 #define smu_write_pptable(smu)						smu_ppt_funcs(write_pptable, 0, smu)
 #define smu_set_min_dcef_deep_sleep(smu, clk)				smu_ppt_funcs(set_min_dcef_deep_sleep, 0, smu, clk)
-#define smu_set_active_display_count(smu, count)			smu_ppt_funcs(set_active_display_count, 0, smu, count)
 #define smu_set_driver_table_location(smu)				smu_ppt_funcs(set_driver_table_location, 0, smu)
 #define smu_set_tool_table_location(smu)				smu_ppt_funcs(set_tool_table_location, 0, smu)
 #define smu_notify_memory_pool_location(smu)				smu_ppt_funcs(notify_memory_pool_location, 0, smu)
@@ -62,7 +61,6 @@
 #define smu_is_dpm_running(smu)						smu_ppt_funcs(is_dpm_running, 0 , smu)
 #define smu_notify_display_change(smu)					smu_ppt_funcs(notify_display_change, 0, smu)
 #define smu_populate_umd_state_clk(smu)					smu_ppt_funcs(populate_umd_state_clk, 0, smu)
-#define smu_set_default_od8_settings(smu)				smu_ppt_funcs(set_default_od8_settings, 0, smu)
 #define smu_enable_thermal_alert(smu)					smu_ppt_funcs(enable_thermal_alert, 0, smu)
 #define smu_disable_thermal_alert(smu)					smu_ppt_funcs(disable_thermal_alert, 0, smu)
 #define smu_smc_read_sensor(smu, sensor, data, size)			smu_ppt_funcs(read_sensor, -EINVAL, smu, sensor, data, size)
@@ -70,13 +68,8 @@
 #define smu_display_config_changed(smu)					smu_ppt_funcs(display_config_changed, 0 , smu)
 #define smu_apply_clocks_adjust_rules(smu)				smu_ppt_funcs(apply_clocks_adjust_rules, 0, smu)
 #define smu_notify_smc_display_config(smu)				smu_ppt_funcs(notify_smc_display_config, 0, smu)
-#define smu_set_cpu_power_state(smu)					smu_ppt_funcs(set_cpu_power_state, 0, smu)
 #define smu_run_btc(smu)						smu_ppt_funcs(run_btc, 0, smu)
 #define smu_get_allowed_feature_mask(smu, feature_mask, num)		smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num)
-#define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis)	smu_ppt_funcs(store_cc6_data, 0, smu, st, cc6_dis, pst_dis, pst_sw_dis)
-#define smu_get_dal_power_level(smu, clocks)				smu_ppt_funcs(get_dal_power_level, 0, smu, clocks)
-#define smu_get_perf_level(smu, designation, level)			smu_ppt_funcs(get_perf_level, 0, smu, designation, level)
-#define smu_get_current_shallow_sleep_clocks(smu, clocks)		smu_ppt_funcs(get_current_shallow_sleep_clocks, 0, smu, clocks)
 #define smu_set_watermarks_table(smu, clock_ranges)			smu_ppt_funcs(set_watermarks_table, 0, smu, clock_ranges)
 #define smu_thermal_temperature_range_update(smu, range, rw)		smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw)
 #define smu_register_irq_handler(smu)					smu_ppt_funcs(register_irq_handler, 0, smu)
@@ -96,6 +89,7 @@
 #define smu_deep_sleep_control(smu, enablement)				smu_ppt_funcs(deep_sleep_control, 0, smu, enablement)
 #define smu_get_fan_parameters(smu)					smu_ppt_funcs(get_fan_parameters, 0, smu)
 #define smu_post_init(smu)						smu_ppt_funcs(post_init, 0, smu)
+#define smu_gpo_control(smu, enablement)				smu_ppt_funcs(gpo_control, 0, smu, enablement)
 
 #endif
 #endif
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index 25c269bc4681..ef82009035e6 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -469,6 +469,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
 			return -EFAULT;
 
 		set_out_fence_for_crtc(state->state, crtc, fence_ptr);
+	} else if (property == crtc->scaling_filter_property) {
+		state->scaling_filter = val;
 	} else if (crtc->funcs->atomic_set_property) {
 		return crtc->funcs->atomic_set_property(crtc, state, property, val);
 	} else {
@@ -503,6 +505,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
 		*val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
 	else if (property == config->prop_out_fence_ptr)
 		*val = 0;
+	else if (property == crtc->scaling_filter_property)
+		*val = state->scaling_filter;
 	else if (crtc->funcs->atomic_get_property)
 		return crtc->funcs->atomic_get_property(crtc, state, property, val);
 	else
@@ -585,6 +589,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane,
 					sizeof(struct drm_rect),
 					&replaced);
 		return ret;
+	} else if (property == plane->scaling_filter_property) {
+		state->scaling_filter = val;
 	} else if (plane->funcs->atomic_set_property) {
 		return plane->funcs->atomic_set_property(plane, state,
 				property, val);
@@ -643,6 +649,8 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
 	} else if (property == config->prop_fb_damage_clips) {
 		*val = (state->fb_damage_clips) ?
 			state->fb_damage_clips->base.id : 0;
+	} else if (property == plane->scaling_filter_property) {
+		*val = state->scaling_filter;
 	} else if (plane->funcs->atomic_get_property) {
 		return plane->funcs->atomic_get_property(plane, state, property, val);
 	} else {
diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c
index f1dcad96f341..ae2234aae93d 100644
--- a/drivers/gpu/drm/drm_blend.c
+++ b/drivers/gpu/drm/drm_blend.c
@@ -194,6 +194,19 @@
  * Note that all the property extensions described here apply either to the
  * plane or the CRTC (e.g. for the background color, which currently is not
  * exposed and assumed to be black).
+ *
+ * SCALING_FILTER:
+ *
+ *     Indicates scaling filter to be used for plane scaler
+ *
+ *     The value of this property can be one of the following:
+ *     Default:
+ *             Driver's default scaling filter
+ *     Nearest Neighbor:
+ *             Nearest Neighbor scaling filter
+ *
+ * Drivers can set up this property for a plane by calling
+ * drm_plane_create_scaling_filter_property
  */
 
 /**
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index aecdd7ea26dc..f927976eca50 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -229,6 +229,15 @@ struct dma_fence *drm_crtc_create_fence(struct drm_crtc *crtc)
  * 	user-space must set this property to 0.
  *
  * 	Setting MODE_ID to 0 will release reserved resources for the CRTC.
+ * SCALING_FILTER:
+ *	Atomic property for setting the scaling filter for CRTC scaler
+ *
+ *	The value of this property can be one of the following:
+ *	Default:
+ *		Driver's default scaling filter
+ *	Nearest Neighbor:
+ *		Nearest Neighbor scaling filter
+ *
  */
 
 /**
@@ -774,3 +783,34 @@ int drm_mode_crtc_set_obj_prop(struct drm_mode_object *obj,
 
 	return ret;
 }
+
+/**
+ * drm_crtc_create_scaling_filter_property - create a new scaling filter
+ * property
+ *
+ * @crtc: drm CRTC
+ * @supported_filters: bitmask of supported scaling filters, must include
+ *		       BIT(DRM_SCALING_FILTER_DEFAULT).
+ *
+ * This function lets driver to enable the scaling filter property on a given
+ * CRTC.
+ *
+ * RETURNS:
+ * Zero for success or -errno
+ */
+int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc,
+					    unsigned int supported_filters)
+{
+	struct drm_property *prop =
+		drm_create_scaling_filter_prop(crtc->dev, supported_filters);
+
+	if (IS_ERR(prop))
+		return PTR_ERR(prop);
+
+	drm_object_attach_property(&crtc->base, prop,
+				   DRM_SCALING_FILTER_DEFAULT);
+	crtc->scaling_filter_property = prop;
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property);
diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h
index da96b2f64d7e..54d4cf1233e9 100644
--- a/drivers/gpu/drm/drm_crtc_internal.h
+++ b/drivers/gpu/drm/drm_crtc_internal.h
@@ -72,6 +72,9 @@ int drm_crtc_force_disable(struct drm_crtc *crtc);
 
 struct dma_fence *drm_crtc_create_fence(struct drm_crtc *crtc);
 
+struct drm_property *
+drm_create_scaling_filter_prop(struct drm_device *dev,
+			       unsigned int supported_filters);
 /* IOCTLs */
 int drm_mode_getcrtc(struct drm_device *dev,
 		     void *data, struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index deeed73f4ed6..37ec3b94389c 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -150,11 +150,8 @@ void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 }
 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
 
-void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval)
 {
-	unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
-					 DP_TRAINING_AUX_RD_MASK;
-
 	if (rd_interval > 4)
 		DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
 			      rd_interval);
@@ -166,8 +163,35 @@ void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 
 	usleep_range(rd_interval, rd_interval * 2);
 }
+
+void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+	__drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+					     DP_TRAINING_AUX_RD_MASK);
+}
 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
 
+void drm_dp_lttpr_link_train_clock_recovery_delay(void)
+{
+	usleep_range(100, 200);
+}
+EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
+
+static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
+{
+	return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
+}
+
+void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
+{
+	u8 interval = dp_lttpr_phy_cap(phy_cap,
+				       DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
+		      DP_TRAINING_AUX_RD_MASK;
+
+	__drm_dp_link_train_channel_eq_delay(interval);
+}
+EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
+
 u8 drm_dp_link_rate_to_bw_code(int link_rate)
 {
 	/* Spec says link_bw = link_rate / 0.27Gbps */
@@ -363,6 +387,59 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
 }
 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
 
+/**
+ * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
+ * @aux: DisplayPort AUX channel
+ * @dp_phy: the DP PHY to get the link status for
+ * @link_status: buffer to return the status in
+ *
+ * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
+ * layout of the returned @link_status matches the DPCD register layout of the
+ * DPRX PHY link status.
+ *
+ * Returns 0 if the information was read successfully or a negative error code
+ * on failure.
+ */
+int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
+				     enum drm_dp_phy dp_phy,
+				     u8 link_status[DP_LINK_STATUS_SIZE])
+{
+	int ret;
+
+	if (dp_phy == DP_PHY_DPRX) {
+		ret = drm_dp_dpcd_read(aux,
+				       DP_LANE0_1_STATUS,
+				       link_status,
+				       DP_LINK_STATUS_SIZE);
+
+		if (ret < 0)
+			return ret;
+
+		WARN_ON(ret != DP_LINK_STATUS_SIZE);
+
+		return 0;
+	}
+
+	ret = drm_dp_dpcd_read(aux,
+			       DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
+			       link_status,
+			       DP_LINK_STATUS_SIZE - 1);
+
+	if (ret < 0)
+		return ret;
+
+	WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
+
+	/* Convert the LTTPR to the sink PHY link status layout */
+	memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
+		&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
+		DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
+	link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
+
 static bool is_edid_digital_input_dp(const struct edid *edid)
 {
 	return edid && edid->revision >= 4 &&
@@ -1882,6 +1959,7 @@ static const struct edid_quirk edid_quirk_list[] = {
 	{ MFG(0x4d, 0x10), PROD_ID(0xc7, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
 	{ MFG(0x4d, 0x10), PROD_ID(0xe6, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
 	{ MFG(0x4c, 0x83), PROD_ID(0x47, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
+	{ MFG(0x09, 0xe5), PROD_ID(0xde, 0x08), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
 };
 
 #undef MFG
@@ -2104,6 +2182,153 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
 
 /**
+ * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
+ * @aux: DisplayPort AUX channel
+ * @caps: buffer to return the capability info in
+ *
+ * Read capabilities common to all LTTPRs.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+				  u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
+{
+	int ret;
+
+	ret = drm_dp_dpcd_read(aux,
+			       DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+			       caps, DP_LTTPR_COMMON_CAP_SIZE);
+	if (ret < 0)
+		return ret;
+
+	WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
+
+/**
+ * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
+ * @aux: DisplayPort AUX channel
+ * @dp_phy: LTTPR PHY to read the capabilities for
+ * @caps: buffer to return the capability info in
+ *
+ * Read the capabilities for the given LTTPR PHY.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+			       enum drm_dp_phy dp_phy,
+			       u8 caps[DP_LTTPR_PHY_CAP_SIZE])
+{
+	int ret;
+
+	ret = drm_dp_dpcd_read(aux,
+			       DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
+			       caps, DP_LTTPR_PHY_CAP_SIZE);
+	if (ret < 0)
+		return ret;
+
+	WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
+
+static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
+{
+	return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+}
+
+/**
+ * drm_dp_lttpr_count - get the number of detected LTTPRs
+ * @caps: LTTPR common capabilities
+ *
+ * Get the number of detected LTTPRs from the LTTPR common capabilities info.
+ *
+ * Returns:
+ *   -ERANGE if more than supported number (8) of LTTPRs are detected
+ *   -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
+ *   otherwise the number of detected LTTPRs
+ */
+int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
+{
+	u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
+
+	switch (hweight8(count)) {
+	case 0:
+		return 0;
+	case 1:
+		return 8 - ilog2(count);
+	case 8:
+		return -ERANGE;
+	default:
+		return -EINVAL;
+	}
+}
+EXPORT_SYMBOL(drm_dp_lttpr_count);
+
+/**
+ * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
+ * @caps: LTTPR common capabilities
+ *
+ * Returns the maximum link rate supported by all detected LTTPRs.
+ */
+int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
+{
+	u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
+
+	return drm_dp_bw_code_to_link_rate(rate);
+}
+EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
+
+/**
+ * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
+ * @caps: LTTPR common capabilities
+ *
+ * Returns the maximum lane count supported by all detected LTTPRs.
+ */
+int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
+{
+	u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
+
+	return max_lanes & DP_MAX_LANE_COUNT_MASK;
+}
+EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
+
+/**
+ * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
+ * @caps: LTTPR PHY capabilities
+ *
+ * Returns true if the @caps for an LTTPR TX PHY indicate support for
+ * voltage swing level 3.
+ */
+bool
+drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
+{
+	u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
+
+	return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
+}
+EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
+
+/**
+ * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
+ * @caps: LTTPR PHY capabilities
+ *
+ * Returns true if the @caps for an LTTPR TX PHY indicate support for
+ * pre-emphasis level 3.
+ */
+bool
+drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
+{
+	u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
+
+	return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
+}
+EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
+
+/**
  * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
  * @aux: DisplayPort AUX channel
  * @data: DP phy compliance test parameters.
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index affe1cfed009..e6231947f987 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -1231,3 +1231,76 @@ out:
 
 	return ret;
 }
+
+struct drm_property *
+drm_create_scaling_filter_prop(struct drm_device *dev,
+			       unsigned int supported_filters)
+{
+	struct drm_property *prop;
+	static const struct drm_prop_enum_list props[] = {
+		{ DRM_SCALING_FILTER_DEFAULT, "Default" },
+		{ DRM_SCALING_FILTER_NEAREST_NEIGHBOR, "Nearest Neighbor" },
+	};
+	unsigned int valid_mode_mask = BIT(DRM_SCALING_FILTER_DEFAULT) |
+				       BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR);
+	int i;
+
+	if (WARN_ON((supported_filters & ~valid_mode_mask) ||
+		    ((supported_filters & BIT(DRM_SCALING_FILTER_DEFAULT)) == 0)))
+		return ERR_PTR(-EINVAL);
+
+	prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
+				   "SCALING_FILTER",
+				   hweight32(supported_filters));
+	if (!prop)
+		return ERR_PTR(-ENOMEM);
+
+	for (i = 0; i < ARRAY_SIZE(props); i++) {
+		int ret;
+
+		if (!(BIT(props[i].type) & supported_filters))
+			continue;
+
+		ret = drm_property_add_enum(prop, props[i].type,
+					    props[i].name);
+
+		if (ret) {
+			drm_property_destroy(dev, prop);
+
+			return ERR_PTR(ret);
+		}
+	}
+
+	return prop;
+}
+
+/**
+ * drm_plane_create_scaling_filter_property - create a new scaling filter
+ * property
+ *
+ * @plane: drm plane
+ * @supported_filters: bitmask of supported scaling filters, must include
+ *		       BIT(DRM_SCALING_FILTER_DEFAULT).
+ *
+ * This function lets driver to enable the scaling filter property on a given
+ * plane.
+ *
+ * RETURNS:
+ * Zero for success or -errno
+ */
+int drm_plane_create_scaling_filter_property(struct drm_plane *plane,
+					     unsigned int supported_filters)
+{
+	struct drm_property *prop =
+		drm_create_scaling_filter_prop(plane->dev, supported_filters);
+
+	if (IS_ERR(prop))
+		return PTR_ERR(prop);
+
+	drm_object_attach_property(&plane->base, prop,
+				   DRM_SCALING_FILTER_DEFAULT);
+	plane->scaling_filter_property = prop;
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_plane_create_scaling_filter_property);
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 520715b7d5b5..096652921453 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -205,6 +205,32 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 	return 0;
 }
 
+void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 tmp, mode_flags;
+	enum port port;
+
+	mode_flags = crtc_state->mode_flags;
+
+	/*
+	 * case 1 also covers dual link
+	 * In case of dual link, frame update should be set on
+	 * DSI_0
+	 */
+	if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0)
+		port = PORT_A;
+	else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
+		port = PORT_B;
+	else
+		return;
+
+	tmp = intel_de_read(dev_priv, DSI_CMD_FRMCTL(port));
+	tmp |= DSI_FRAME_UPDATE_REQUEST;
+	intel_de_write(dev_priv, DSI_CMD_FRMCTL(port), tmp);
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -429,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 
 		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
-		if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
+		if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
 			tmp = intel_de_read(dev_priv,
 					    ICL_PORT_PCS_DW1_AUX(phy));
 			tmp &= ~LATENCY_OPTIM_MASK;
@@ -586,7 +612,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
 		}
 	}
 
-	if (IS_ELKHARTLAKE(dev_priv)) {
+	if (IS_JSL_EHL(dev_priv)) {
 		for_each_dsi_phy(phy, intel_dsi->phys) {
 			tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy));
 			tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
@@ -1447,6 +1473,18 @@ static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
 	return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
 }
 
+static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
+					  struct intel_crtc_state *pipe_config)
+{
+	if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
+		pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
+					    I915_MODE_FLAG_DSI_USE_TE0;
+	else if (intel_dsi->ports == BIT(PORT_B))
+		pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
+	else
+		pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
+}
+
 static void gen11_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
@@ -1468,6 +1506,10 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
 
+	/* Get the details on which TE should be enabled */
+	if (is_cmd_mode(intel_dsi))
+		gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
+
 	if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
 		pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
 }
@@ -1562,18 +1604,8 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	 * receive TE from the slave if
 	 * dual link is enabled
 	 */
-	if (is_cmd_mode(intel_dsi)) {
-		if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
-			pipe_config->mode_flags |=
-						I915_MODE_FLAG_DSI_USE_TE1 |
-						I915_MODE_FLAG_DSI_USE_TE0;
-		else if (intel_dsi->ports == BIT(PORT_B))
-			pipe_config->mode_flags |=
-						I915_MODE_FLAG_DSI_USE_TE1;
-		else
-			pipe_config->mode_flags |=
-						I915_MODE_FLAG_DSI_USE_TE0;
-	}
+	if (is_cmd_mode(intel_dsi))
+		gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
 
 	return 0;
 }
@@ -1636,6 +1668,19 @@ out:
 	return ret;
 }
 
+static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
+					    struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->dsc.compression_enable) {
+		drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
+		crtc_state->uapi.mode_changed = true;
+
+		return false;
+	}
+
+	return true;
+}
+
 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
 {
 	intel_encoder_destroy(encoder);
@@ -1891,6 +1936,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	encoder->update_pipe = intel_panel_update_backlight;
 	encoder->compute_config = gen11_dsi_compute_config;
 	encoder->get_hw_state = gen11_dsi_get_hw_state;
+	encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
 	encoder->type = INTEL_OUTPUT_DSI;
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 79032701873a..3334ff253600 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -262,6 +262,7 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 	plane_state->hw.rotation = from_plane_state->uapi.rotation;
 	plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
 	plane_state->hw.color_range = from_plane_state->uapi.color_range;
+	plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
 }
 
 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
@@ -408,7 +409,11 @@ void intel_update_plane(struct intel_plane *plane,
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	trace_intel_update_plane(&plane->base, crtc);
-	plane->update_plane(plane, crtc_state, plane_state);
+
+	if (crtc_state->uapi.async_flip && plane->async_flip)
+		plane->async_flip(plane, crtc_state, plane_state);
+	else
+		plane->update_plane(plane, crtc_state, plane_state);
 }
 
 void intel_disable_plane(struct intel_plane *plane,
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 4716484af62d..4cc949b228f2 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -425,6 +425,7 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
 	const struct bdb_lfp_backlight_data *backlight_data;
 	const struct lfp_backlight_data_entry *entry;
 	int panel_type = dev_priv->vbt.panel_type;
+	u16 level;
 
 	backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
 	if (!backlight_data)
@@ -459,14 +460,39 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
 
 	dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
 	dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
-	dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
+
+	if (bdb->version >= 234) {
+		u16 min_level;
+		bool scale;
+
+		level = backlight_data->brightness_level[panel_type].level;
+		min_level = backlight_data->brightness_min_level[panel_type].level;
+
+		if (bdb->version >= 236)
+			scale = backlight_data->brightness_precision_bits[panel_type] == 16;
+		else
+			scale = level > 255;
+
+		if (scale)
+			min_level = min_level / 255;
+
+		if (min_level > 255) {
+			drm_warn(&dev_priv->drm, "Brightness min level > 255\n");
+			level = 255;
+		}
+		dev_priv->vbt.backlight.min_brightness = min_level;
+	} else {
+		level = backlight_data->level[panel_type];
+		dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
+	}
+
 	drm_dbg_kms(&dev_priv->drm,
 		    "VBT backlight PWM modulation frequency %u Hz, "
 		    "active %s, min brightness %u, level %u, controller %u\n",
 		    dev_priv->vbt.backlight.pwm_freq_hz,
 		    dev_priv->vbt.backlight.active_low_pwm ? "low" : "high",
 		    dev_priv->vbt.backlight.min_brightness,
-		    backlight_data->level[panel_type],
+		    level,
 		    dev_priv->vbt.backlight.controller);
 }
 
@@ -1602,7 +1628,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 	const u8 *ddc_pin_map;
 	int n_entries;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+		return vbt_pin;
+	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
 		ddc_pin_map = icp_ddc_pin_map;
 		n_entries = ARRAY_SIZE(icp_ddc_pin_map);
 	} else if (HAS_PCH_CNP(dev_priv)) {
@@ -1660,20 +1688,18 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
 		[PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
 	};
 	/*
-	 * Bspec lists the ports as A, B, C, D - however internally in our
-	 * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
-	 * registers in Display Engine match the right offsets. Apply the
-	 * mapping here to translate from VBT to internal convention.
+	 * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D
+	 * map to DDI A,B,TC1,TC2 respectively.
 	 */
 	static const int rkl_port_mapping[][3] = {
 		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
 		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
 		[PORT_C] = { -1 },
-		[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
-		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+		[PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+		[PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
 	};
 
-	if (IS_ROCKETLAKE(dev_priv))
+	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
 					  ARRAY_SIZE(rkl_port_mapping[0]),
 					  rkl_port_mapping,
@@ -1889,7 +1915,7 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
 		expected_size = 37;
 	} else if (bdb->version <= 215) {
 		expected_size = 38;
-	} else if (bdb->version <= 229) {
+	} else if (bdb->version <= 237) {
 		expected_size = 39;
 	} else {
 		expected_size = sizeof(*child);
@@ -2638,10 +2664,16 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
 		aux_ch = AUX_CH_B;
 		break;
 	case DP_AUX_C:
-		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
+		/*
+		 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
+		 * map to DDI A,B,TC1,TC2 respectively.
+		 */
+		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+			AUX_CH_USBC1 : AUX_CH_C;
 		break;
 	case DP_AUX_D:
-		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
+		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+			AUX_CH_USBC2 : AUX_CH_D;
 		break;
 	case DP_AUX_E:
 		aux_ch = AUX_CH_E;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index cb93f6cf6d37..c449d28d0560 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1233,6 +1233,30 @@ static const struct intel_cdclk_vals icl_cdclk_table[] = {
 	{}
 };
 
+static const struct intel_cdclk_vals rkl_cdclk_table[] = {
+	{ .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio =  36 },
+	{ .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio =  40 },
+	{ .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio =  64 },
+	{ .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
+	{ .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
+	{ .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
+
+	{ .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio =  30 },
+	{ .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio =  32 },
+	{ .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio =  52 },
+	{ .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
+	{ .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio =  92 },
+	{ .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
+
+	{ .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
+	{ .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
+	{ .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
+	{ .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
+	{ .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
+	{ .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
+	{}
+};
+
 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 {
 	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
@@ -2588,7 +2612,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
 {
-	if (IS_ELKHARTLAKE(dev_priv)) {
+	if (IS_JSL_EHL(dev_priv)) {
 		if (dev_priv->cdclk.hw.ref == 24000)
 			dev_priv->max_cdclk_freq = 552000;
 		else
@@ -2680,6 +2704,18 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
 			       DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
 }
 
+static int dg1_rawclk(struct drm_i915_private *dev_priv)
+{
+	/*
+	 * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
+	 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
+	 */
+	I915_WRITE(PCH_RAWCLK_FREQ,
+		   CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
+
+	return 38400;
+}
+
 static int cnp_rawclk(struct drm_i915_private *dev_priv)
 {
 	u32 rawclk;
@@ -2788,7 +2824,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 {
 	u32 freq;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+		freq = dg1_rawclk(dev_priv);
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 		freq = cnp_rawclk(dev_priv);
 	else if (HAS_PCH_SPLIT(dev_priv))
 		freq = pch_rawclk(dev_priv);
@@ -2809,13 +2847,19 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
  */
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 12) {
+	if (IS_ROCKETLAKE(dev_priv)) {
+		dev_priv->display.set_cdclk = bxt_set_cdclk;
+		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+		dev_priv->cdclk.table = rkl_cdclk_table;
+	} else if (INTEL_GEN(dev_priv) >= 12) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
-	} else if (IS_ELKHARTLAKE(dev_priv)) {
+	} else if (IS_JSL_EHL(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 945bb03bdd4d..172d398081ee 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -638,10 +638,17 @@ static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
 		ilk_load_lut_8(crtc, gamma_lut);
-	else
+		break;
+	case GAMMA_MODE_MODE_10BIT:
 		ilk_load_lut_10(crtc, gamma_lut);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
+	}
 }
 
 static int ivb_lut_10_size(u32 prec_index)
@@ -745,21 +752,27 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
+	const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		ilk_load_lut_8(crtc, gamma_lut);
-	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
+		ilk_load_lut_8(crtc, blob);
+		break;
+	case GAMMA_MODE_MODE_SPLIT:
 		ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
 		ivb_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(512));
-	} else {
-		const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
-
+		break;
+	case GAMMA_MODE_MODE_10BIT:
 		ivb_load_lut_10(crtc, blob,
 				PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
 	}
 }
 
@@ -768,21 +781,28 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
+	const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		ilk_load_lut_8(crtc, gamma_lut);
-	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
+		ilk_load_lut_8(crtc, blob);
+		break;
+	case GAMMA_MODE_MODE_SPLIT:
 		bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(512));
-	} else {
-		const struct drm_property_blob *blob = gamma_lut ?: degamma_lut;
+		break;
+	case GAMMA_MODE_MODE_10BIT:
 
 		bdw_load_lut_10(crtc, blob,
 				PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
 	}
 }
 
@@ -818,12 +838,14 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 		 * as compared to just 16 to achieve this.
 		 */
 		intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe),
-		               lut[i].green);
+			       lut[i].green);
 	}
 
 	/* Clamp values > 1.0. */
 	while (i++ < 35)
 		intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
+
+	intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
 }
 
 static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state)
@@ -851,6 +873,8 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
 	/* Clamp values > 1.0. */
 	while (i++ < 35)
 		intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
+
+	intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
 }
 
 static void glk_load_luts(const struct intel_crtc_state *crtc_state)
@@ -871,11 +895,17 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 	else
 		glk_load_degamma_lut_linear(crtc_state);
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
 		ilk_load_lut_8(crtc, gamma_lut);
-	} else {
+		break;
+	case GAMMA_MODE_MODE_10BIT:
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
 	}
 }
 
@@ -1007,9 +1037,13 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 		icl_program_gamma_superfine_segment(crtc_state);
 		icl_program_gamma_multi_segment(crtc_state);
 		break;
-	default:
+	case GAMMA_MODE_MODE_10BIT:
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc_state);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
 	}
 
 	intel_dsb_commit(crtc_state);
@@ -1026,13 +1060,6 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
 	return drm_color_lut_extract(color->red, 14);
 }
 
-static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
-{
-	entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
-	entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
-	entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
-}
-
 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
 				 const struct drm_property_blob *blob)
 {
@@ -1060,6 +1087,13 @@ static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color)
 	return drm_color_lut_extract(color->red, 10);
 }
 
+static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+{
+	entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
+	entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
+	entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
+}
+
 static void chv_load_cgm_gamma(struct intel_crtc *crtc,
 			       const struct drm_property_blob *blob)
 {
@@ -1733,7 +1767,7 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 		break;
 	default:
 		MISSING_CASE(gamma_mode);
-			return false;
+		return false;
 	}
 
 	return true;
@@ -1913,23 +1947,34 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 	if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
 		return;
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
 		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
-	else
+		break;
+	case GAMMA_MODE_MODE_10BIT:
 		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
+	}
 }
 
-static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc,
+/* On BDW+ the index auto increment mode actually works */
+static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
 						 u32 prec_index)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, hw_lut_size = ivb_lut_10_size(prec_index);
+	int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
 
+	drm_WARN_ON(&dev_priv->drm, lut_size != hw_lut_size);
+
 	blob = drm_property_create_blob(&dev_priv->drm,
-					sizeof(struct drm_color_lut) * hw_lut_size,
+					sizeof(struct drm_color_lut) * lut_size,
 					NULL);
 	if (IS_ERR(blob))
 		return NULL;
@@ -1939,7 +1984,7 @@ static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc,
 	intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
 		       prec_index | PAL_PREC_AUTO_INCREMENT);
 
-	for (i = 0; i < hw_lut_size; i++) {
+	for (i = 0; i < lut_size; i++) {
 		u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
 
 		ilk_lut_10_pack(&lut[i], val);
@@ -1957,10 +2002,17 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
 	if (!crtc_state->gamma_enable)
 		return;
 
-	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
+	switch (crtc_state->gamma_mode) {
+	case GAMMA_MODE_MODE_8BIT:
 		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
-	else
-		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
+		break;
+	case GAMMA_MODE_MODE_10BIT:
+		crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
+		break;
+	default:
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
+	}
 }
 
 static struct drm_property_blob *
@@ -2012,11 +2064,15 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
 	case GAMMA_MODE_MODE_8BIT:
 		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
 		break;
+	case GAMMA_MODE_MODE_10BIT:
+		crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
+		break;
 	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 		crtc_state->hw.gamma_lut = icl_read_lut_multi_segment(crtc);
 		break;
 	default:
-		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
+		MISSING_CASE(crtc_state->gamma_mode);
+		break;
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 157d8c8c605a..d5ad61e4083e 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -188,8 +188,9 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
 	 * PHY-B and may not even have instances of the register for the
 	 * other combo PHY's.
 	 */
-	if (IS_ELKHARTLAKE(i915) ||
-	    IS_ROCKETLAKE(i915))
+	if (IS_JSL_EHL(i915) ||
+	    IS_ROCKETLAKE(i915) ||
+	    IS_DG1(i915))
 		return phy < PHY_C;
 
 	return true;
@@ -242,14 +243,14 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
 	 *
 	 * ICL,TGL:
 	 *   A(master) -> B(slave), C(slave)
-	 * RKL:
+	 * RKL,DG1:
 	 *   A(master) -> B(slave)
 	 *   C(master) -> D(slave)
 	 *
 	 * We must set the IREFGEN bit for any PHY acting as a master
 	 * to another PHY.
 	 */
-	if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
+	if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C)
 		return true;
 
 	return phy == PHY_A;
@@ -282,7 +283,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 				     IREFGEN, IREFGEN);
 
-		if (IS_ELKHARTLAKE(dev_priv)) {
+		if (IS_JSL_EHL(dev_priv)) {
 			if (ehl_vbt_ddi_d_present(dev_priv))
 				expected_val = ICL_PHY_MISC_MUX_DDID;
 
@@ -376,7 +377,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		 * "internal" child devices.
 		 */
 		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
-		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) {
+		if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
 			val &= ~ICL_PHY_MISC_MUX_DDID;
 
 			if (ehl_vbt_ddi_d_present(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index d5db16764619..67dc64df78a5 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,13 +40,16 @@
 
 #define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
 
+#define DG1_CSR_PATH			"i915/dg1_dmc_ver2_02.bin"
+#define DG1_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)
+MODULE_FIRMWARE(DG1_CSR_PATH);
+
 #define RKL_CSR_PATH			"i915/rkl_dmc_ver2_02.bin"
 #define RKL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)
 MODULE_FIRMWARE(RKL_CSR_PATH);
 
 #define TGL_CSR_PATH			"i915/tgl_dmc_ver2_08.bin"
 #define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 8)
-#define TGL_CSR_MAX_FW_SIZE		0x6000
 MODULE_FIRMWARE(TGL_CSR_PATH);
 
 #define ICL_CSR_PATH			"i915/icl_dmc_ver1_09.bin"
@@ -686,14 +689,17 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_csr_runtime_pm_get(dev_priv);
 
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		csr->fw_path = DG1_CSR_PATH;
+		csr->required_version = DG1_CSR_VERSION_REQUIRED;
+		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		csr->fw_path = RKL_CSR_PATH;
 		csr->required_version = RKL_CSR_VERSION_REQUIRED;
 		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 	} else if (INTEL_GEN(dev_priv) >= 12) {
 		csr->fw_path = TGL_CSR_PATH;
 		csr->required_version = TGL_CSR_VERSION_REQUIRED;
-		/* Allow to load fw via parameter using the last known size */
 		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 	} else if (IS_GEN(dev_priv, 11)) {
 		csr->fw_path = ICL_CSR_PATH;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index cdcb7b1034ae..19b16517a502 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1034,133 +1034,235 @@ cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
-			int *n_entries)
+icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
+			     int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+	return icl_combo_phy_ddi_translations_hdmi;
+}
+
+static const struct cnl_ddi_buf_trans *
+icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
+			   int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
+	return icl_combo_phy_ddi_translations_dp_hbr2;
+}
+
+static const struct cnl_ddi_buf_trans *
+icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
+			    int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	if (type == INTEL_OUTPUT_HDMI) {
-		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
-		return icl_combo_phy_ddi_translations_hdmi;
-	} else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
+	if (crtc_state->port_clock > 540000) {
 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
 		return icl_combo_phy_ddi_translations_edp_hbr3;
-	} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
+	} else if (dev_priv->vbt.edp.low_vswing) {
 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 		return icl_combo_phy_ddi_translations_edp_hbr2;
 	}
 
-	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
-	return icl_combo_phy_ddi_translations_dp_hbr2;
+	return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
+static const struct cnl_ddi_buf_trans *
+icl_get_combo_buf_trans(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
+			int *n_entries)
+{
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
+	else
+		return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct icl_mg_phy_ddi_buf_trans *
-icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
-		     int *n_entries)
+icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state,
+			  int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
+	return icl_mg_phy_ddi_translations_hdmi;
+}
+
+static const struct icl_mg_phy_ddi_buf_trans *
+icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
+			int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI) {
-		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
-		return icl_mg_phy_ddi_translations_hdmi;
-	} else if (rate > 270000) {
+	if (crtc_state->port_clock > 270000) {
 		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
 		return icl_mg_phy_ddi_translations_hbr2_hbr3;
+	} else {
+		*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
+		return icl_mg_phy_ddi_translations_rbr_hbr;
 	}
+}
 
-	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
-	return icl_mg_phy_ddi_translations_rbr_hbr;
+static const struct icl_mg_phy_ddi_buf_trans *
+icl_get_mg_buf_trans(struct intel_encoder *encoder,
+		     const struct intel_crtc_state *crtc_state,
+		     int *n_entries)
+{
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else
+		return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
-			int *n_entries)
+ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
+			     int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+	return icl_combo_phy_ddi_translations_hdmi;
+}
+
+static const struct cnl_ddi_buf_trans *
+ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
+			   int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
+	return ehl_combo_phy_ddi_translations_dp;
+}
+
+static const struct cnl_ddi_buf_trans *
+ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
+			    int *n_entries)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
-	switch (type) {
-	case INTEL_OUTPUT_HDMI:
-		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
-		return icl_combo_phy_ddi_translations_hdmi;
-	case INTEL_OUTPUT_EDP:
-		if (dev_priv->vbt.edp.low_vswing) {
-			if (rate > 540000) {
-				*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
-				return icl_combo_phy_ddi_translations_edp_hbr3;
-			} else {
-				*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
-				return icl_combo_phy_ddi_translations_edp_hbr2;
-			}
-		}
-		/* fall through */
-	default:
-		/* All combo DP and eDP ports that do not support low_vswing */
-		*n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
-		return ehl_combo_phy_ddi_translations_dp;
+	if (dev_priv->vbt.edp.low_vswing) {
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+		return icl_combo_phy_ddi_translations_edp_hbr2;
 	}
+
+	return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
 static const struct cnl_ddi_buf_trans *
-tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+ehl_get_combo_buf_trans(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
 			int *n_entries)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
+	else
+		return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
+}
 
-	switch (type) {
-	case INTEL_OUTPUT_HDMI:
-		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
-		return icl_combo_phy_ddi_translations_hdmi;
-	case INTEL_OUTPUT_EDP:
-		if (dev_priv->vbt.edp.hobl) {
-			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-			if (!intel_dp->hobl_failed && rate <= 540000) {
-				/* Same table applies to TGL, RKL and DG1 */
-				*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
-				return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
-			}
-		}
+static const struct cnl_ddi_buf_trans *
+tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
+			     int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+	return icl_combo_phy_ddi_translations_hdmi;
+}
 
-		if (rate > 540000) {
-			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
-			return icl_combo_phy_ddi_translations_edp_hbr3;
-		} else if (dev_priv->vbt.edp.low_vswing) {
-			*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
-			return icl_combo_phy_ddi_translations_edp_hbr2;
-		}
-		/* fall through */
-	default:
-		/* All combo DP and eDP ports that do not support low_vswing */
-		if (rate > 270000) {
-			if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
-				*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
-				return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
-			}
+static const struct cnl_ddi_buf_trans *
+tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
+			   int *n_entries)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
+	if (crtc_state->port_clock > 270000) {
+		if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
+			*n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
+			return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
+		} else {
 			*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
 			return tgl_combo_phy_ddi_translations_dp_hbr2;
 		}
-
+	} else {
 		*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
 		return tgl_combo_phy_ddi_translations_dp_hbr;
 	}
 }
 
+static const struct cnl_ddi_buf_trans *
+tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
+			    int *n_entries)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+	if (crtc_state->port_clock > 540000) {
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+		return icl_combo_phy_ddi_translations_edp_hbr3;
+	} else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
+		*n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
+		return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
+	} else if (dev_priv->vbt.edp.low_vswing) {
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+		return icl_combo_phy_ddi_translations_edp_hbr2;
+	}
+
+	return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
+static const struct cnl_ddi_buf_trans *
+tgl_get_combo_buf_trans(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state,
+			int *n_entries)
+{
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
+	else
+		return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
 static const struct tgl_dkl_phy_ddi_buf_trans *
-tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
-		      int *n_entries)
+tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state,
+			   int *n_entries)
+{
+	*n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
+	return tgl_dkl_phy_hdmi_ddi_trans;
+}
+
+static const struct tgl_dkl_phy_ddi_buf_trans *
+tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state,
+			 int *n_entries)
 {
-	if (type == INTEL_OUTPUT_HDMI) {
-		*n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
-		return tgl_dkl_phy_hdmi_ddi_trans;
-	} else if (rate > 270000) {
+	if (crtc_state->port_clock > 270000) {
 		*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
 		return tgl_dkl_phy_dp_ddi_trans_hbr2;
+	} else {
+		*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
+		return tgl_dkl_phy_dp_ddi_trans;
 	}
+}
 
-	*n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
-	return tgl_dkl_phy_dp_ddi_trans;
+static const struct tgl_dkl_phy_ddi_buf_trans *
+tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
+		      const struct intel_crtc_state *crtc_state,
+		      int *n_entries)
+{
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else
+		return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
-static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
+static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	int n_entries, level, default_entry;
@@ -1168,19 +1270,15 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		if (intel_phy_is_combo(dev_priv, phy))
-			tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
-						0, &n_entries);
+			tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		else
-			tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
-					      &n_entries);
+			tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		default_entry = n_entries - 1;
 	} else if (INTEL_GEN(dev_priv) == 11) {
 		if (intel_phy_is_combo(dev_priv, phy))
-			icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
-						0, &n_entries);
+			icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		else
-			icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
-					     &n_entries);
+			icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries);
 		default_entry = n_entries - 1;
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		cnl_get_buf_trans_hdmi(encoder, &n_entries);
@@ -1507,14 +1605,15 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 		       DP_TP_CTL_ENABLE);
 }
 
-static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
+static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
+				      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	intel_dp->DP = dig_port->saved_port_bits |
 		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
-	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
+	intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
 }
 
 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
@@ -2178,13 +2277,14 @@ static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
 }
 
 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
-			       int level, enum intel_output_type type)
+			       const struct intel_crtc_state *crtc_state,
+			       int level)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	u8 iboost;
 
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		iboost = intel_bios_hdmi_boost_level(encoder);
 	else
 		iboost = intel_bios_dp_boost_level(encoder);
@@ -2193,14 +2293,12 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 		const struct ddi_buf_trans *ddi_translations;
 		int n_entries;
 
-		if (type == INTEL_OUTPUT_HDMI)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 			ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
-		else if (type == INTEL_OUTPUT_EDP)
-			ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
-								       &n_entries);
+		else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+			ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries);
 		else
-			ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
-								      &n_entries);
+			ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries);
 
 		if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 			return;
@@ -2223,16 +2321,17 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 }
 
 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int level, enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct bxt_ddi_buf_trans *ddi_translations;
 	enum port port = encoder->port;
 	int n_entries;
 
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
 	else
 		ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
@@ -2249,7 +2348,8 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
 				     ddi_translations[level].deemphasis);
 }
 
-static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
+static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
+				   const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2259,33 +2359,28 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		if (intel_phy_is_combo(dev_priv, phy))
-			tgl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+			tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 		else
-			tgl_get_dkl_buf_trans(encoder, encoder->type,
-					      intel_dp->link_rate, &n_entries);
+			tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
 	} else if (INTEL_GEN(dev_priv) == 11) {
-		if (IS_ELKHARTLAKE(dev_priv))
-			ehl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+		if (IS_JSL_EHL(dev_priv))
+			ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 		else if (intel_phy_is_combo(dev_priv, phy))
-			icl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+			icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 		else
-			icl_get_mg_buf_trans(encoder, encoder->type,
-					     intel_dp->link_rate, &n_entries);
+			icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
 	} else if (IS_CANNONLAKE(dev_priv)) {
-		if (encoder->type == INTEL_OUTPUT_EDP)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 			cnl_get_buf_trans_edp(encoder, &n_entries);
 		else
 			cnl_get_buf_trans_dp(encoder, &n_entries);
 	} else if (IS_GEN9_LP(dev_priv)) {
-		if (encoder->type == INTEL_OUTPUT_EDP)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 			bxt_get_buf_trans_edp(encoder, &n_entries);
 		else
 			bxt_get_buf_trans_dp(encoder, &n_entries);
 	} else {
-		if (encoder->type == INTEL_OUTPUT_EDP)
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 			intel_ddi_get_buf_trans_edp(encoder, &n_entries);
 		else
 			intel_ddi_get_buf_trans_dp(encoder, &n_entries);
@@ -2312,7 +2407,8 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
 }
 
 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
-				   int level, enum intel_output_type type)
+				   const struct intel_crtc_state *crtc_state,
+				   int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct cnl_ddi_buf_trans *ddi_translations;
@@ -2320,9 +2416,9 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
 	int n_entries, ln;
 	u32 val;
 
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
-	else if (type == INTEL_OUTPUT_EDP)
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
 	else
 		ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
@@ -2376,22 +2472,16 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
 }
 
 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int level, enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 	int width, rate, ln;
 	u32 val;
 
-	if (type == INTEL_OUTPUT_HDMI) {
-		width = 4;
-		rate = 0; /* Rate is always < than 6GHz for HDMI */
-	} else {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		width = intel_dp->lane_count;
-		rate = intel_dp->link_rate;
-	}
+	width = crtc_state->lane_count;
+	rate = crtc_state->port_clock;
 
 	/*
 	 * 1. If port type is eDP or DP,
@@ -2399,10 +2489,10 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
 	 * else clear to 0b.
 	 */
 	val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
-	if (type != INTEL_OUTPUT_HDMI)
-		val |= COMMON_KEEPER_EN;
-	else
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		val &= ~COMMON_KEEPER_EN;
+	else
+		val |= COMMON_KEEPER_EN;
 	intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
 
 	/* 2. Program loadgen select */
@@ -2434,7 +2524,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
 
 	/* 5. Program swing and de-emphasis */
-	cnl_ddi_vswing_program(encoder, level, type);
+	cnl_ddi_vswing_program(encoder, crtc_state, level);
 
 	/* 6. Set training enable to trigger update */
 	val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
@@ -2443,23 +2533,21 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
 }
 
 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
-					 u32 level, int type, int rate)
+					 const struct intel_crtc_state *crtc_state,
+					 int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	const struct cnl_ddi_buf_trans *ddi_translations;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
-	u32 n_entries, val;
-	int ln;
+	int n_entries, ln;
+	u32 val;
 
 	if (INTEL_GEN(dev_priv) >= 12)
-		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
-							   &n_entries);
-	else if (IS_ELKHARTLAKE(dev_priv))
-		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
-							   &n_entries);
+		ddi_translations = tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
+	else if (IS_JSL_EHL(dev_priv))
+		ddi_translations = ehl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 	else
-		ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
-							   &n_entries);
+		ddi_translations = icl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
 	if (!ddi_translations)
 		return;
 
@@ -2470,7 +2558,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 		level = n_entries - 1;
 	}
 
-	if (type == INTEL_OUTPUT_EDP) {
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
 		val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
@@ -2518,25 +2606,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 }
 
 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
-					      u32 level,
-					      enum intel_output_type type)
+					      const struct intel_crtc_state *crtc_state,
+					      int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	int width = 0;
-	int rate = 0;
+	int width, rate, ln;
 	u32 val;
-	int ln = 0;
-
-	if (type == INTEL_OUTPUT_HDMI) {
-		width = 4;
-		/* Rate is always < than 6GHz for HDMI */
-	} else {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
-		width = intel_dp->lane_count;
-		rate = intel_dp->link_rate;
-	}
+	width = crtc_state->lane_count;
+	rate = crtc_state->port_clock;
 
 	/*
 	 * 1. If port type is eDP or DP,
@@ -2544,7 +2623,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	 * else clear to 0b.
 	 */
 	val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
-	if (type == INTEL_OUTPUT_HDMI)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		val &= ~COMMON_KEEPER_EN;
 	else
 		val |= COMMON_KEEPER_EN;
@@ -2579,7 +2658,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
 
 	/* 5. Program swing and de-emphasis */
-	icl_ddi_combo_vswing_program(encoder, level, type, rate);
+	icl_ddi_combo_vswing_program(encoder, crtc_state, level);
 
 	/* 6. Set training enable to trigger update */
 	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
@@ -2588,23 +2667,16 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 }
 
 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
-					   int link_clock, u32 level,
-					   enum intel_output_type type)
+					   const struct intel_crtc_state *crtc_state,
+					   int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
 	const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
-	u32 n_entries, val;
-	int ln, rate = 0;
-
-	if (type != INTEL_OUTPUT_HDMI) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		rate = intel_dp->link_rate;
-	}
+	int n_entries, ln;
+	u32 val;
 
-	ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
-						&n_entries);
+	ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
 	/* The table does not have values for level 3 and level 9. */
 	if (level >= n_entries || level == 3 || level == 9) {
 		drm_dbg_kms(&dev_priv->drm,
@@ -2671,7 +2743,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	 */
 	for (ln = 0; ln < 2; ln++) {
 		val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
-		if (link_clock < 300000)
+		if (crtc_state->port_clock < 300000)
 			val |= CFG_LOW_RATE_LKREN_EN;
 		else
 			val &= ~CFG_LOW_RATE_LKREN_EN;
@@ -2682,7 +2754,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	for (ln = 0; ln < 2; ln++) {
 		val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
 		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
-		if (link_clock <= 500000) {
+		if (crtc_state->port_clock <= 500000) {
 			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
 		} else {
 			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
@@ -2692,7 +2764,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 
 		val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
 		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
-		if (link_clock <= 500000) {
+		if (crtc_state->port_clock <= 500000) {
 			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
 		} else {
 			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
@@ -2718,38 +2790,30 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 }
 
 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int link_clock,
-				    u32 level,
-				    enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	if (intel_phy_is_combo(dev_priv, phy))
-		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+		icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
-		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
-					       type);
+		icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
-				u32 level, enum intel_output_type type)
+tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state,
+				int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
 	const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
-	u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
-	int rate = 0;
-
-	if (type != INTEL_OUTPUT_HDMI) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		rate = intel_dp->link_rate;
-	}
+	u32 val, dpcnt_mask, dpcnt_val;
+	int n_entries, ln;
 
-	ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
-						 &n_entries);
+	ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
 
 	if (level >= n_entries)
 		level = n_entries - 1;
@@ -2785,20 +2849,20 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
 }
 
 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
-				    int link_clock,
-				    u32 level,
-				    enum intel_output_type type)
+				    const struct intel_crtc_state *crtc_state,
+				    int level)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	if (intel_phy_is_combo(dev_priv, phy))
-		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
+		icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
-		tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type);
+		tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
-static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
+static int translate_signal_level(struct intel_dp *intel_dp,
+				  u8 signal_levels)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	int i;
@@ -2815,55 +2879,58 @@ static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
 	return 0;
 }
 
-static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
+static int intel_ddi_dp_level(struct intel_dp *intel_dp)
 {
 	u8 train_set = intel_dp->train_set[0];
-	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
-					 DP_TRAIN_PRE_EMPHASIS_MASK);
+	u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+					DP_TRAIN_PRE_EMPHASIS_MASK);
 
 	return translate_signal_level(intel_dp, signal_levels);
 }
 
 static void
-tgl_set_signal_levels(struct intel_dp *intel_dp)
+tgl_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
-				level, encoder->type);
+	tgl_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-icl_set_signal_levels(struct intel_dp *intel_dp)
+icl_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
-				level, encoder->type);
+	icl_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-cnl_set_signal_levels(struct intel_dp *intel_dp)
+cnl_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	cnl_ddi_vswing_sequence(encoder, level, encoder->type);
+	cnl_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-bxt_set_signal_levels(struct intel_dp *intel_dp)
+bxt_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	int level = intel_ddi_dp_level(intel_dp);
 
-	bxt_ddi_vswing_sequence(encoder, level, encoder->type);
+	bxt_ddi_vswing_sequence(encoder, crtc_state, level);
 }
 
 static void
-hsw_set_signal_levels(struct intel_dp *intel_dp)
+hsw_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2880,7 +2947,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
 	intel_dp->DP |= signal_levels;
 
 	if (IS_GEN9_BC(dev_priv))
-		skl_ddi_set_iboost(encoder, level, encoder->type);
+		skl_ddi_set_iboost(encoder, crtc_state, level);
 
 	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
 	intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
@@ -3068,7 +3135,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 		if (!intel_phy_is_combo(dev_priv, phy))
 			intel_de_write(dev_priv, DDI_CLK_SEL(port),
 				       icl_pll_to_ddi_clk_sel(encoder, crtc_state));
-		else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
+		else if (IS_JSL_EHL(dev_priv) && port >= PORT_C)
 			/*
 			 * MG does not exist but the programming is required
 			 * to ungate DDIC and DDID
@@ -3117,7 +3184,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 
 	if (INTEL_GEN(dev_priv) >= 11) {
 		if (!intel_phy_is_combo(dev_priv, phy) ||
-		    (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
+		    (IS_JSL_EHL(dev_priv) && port >= PORT_C))
 			intel_de_write(dev_priv, DDI_CLK_SEL(port),
 				       DDI_CLK_SEL_NONE);
 	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -3223,6 +3290,37 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 	}
 }
 
+static enum transcoder
+tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
+{
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
+		return crtc_state->mst_master_transcoder;
+	else
+		return crtc_state->cpu_transcoder;
+}
+
+i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
+	else
+		return DP_TP_CTL(encoder->port);
+}
+
+i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
+	else
+		return DP_TP_STATUS(encoder->port);
+}
+
 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
 					const struct intel_crtc_state *crtc_state)
 {
@@ -3247,11 +3345,12 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
 		return;
 
 	intel_dp = enc_to_intel_dp(encoder);
-	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 	val |= DP_TP_CTL_FEC_ENABLE;
-	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
+	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
 
-	if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
+	if (intel_de_wait_for_set(dev_priv,
+				  dp_tp_status_reg(encoder, crtc_state),
 				  DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
 		drm_err(&dev_priv->drm,
 			"Timed out waiting for FEC Enable Status\n");
@@ -3268,10 +3367,10 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
 		return;
 
 	intel_dp = enc_to_intel_dp(encoder);
-	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 	val &= ~DP_TP_CTL_FEC_ENABLE;
-	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
-	intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
+	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 }
 
 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -3285,13 +3384,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
 	int level = intel_ddi_dp_level(intel_dp);
-	enum transcoder transcoder = crtc_state->cpu_transcoder;
 
-	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
-				 crtc_state->lane_count, is_mst);
-
-	intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
-	intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
+	intel_dp_set_link_params(intel_dp,
+				 crtc_state->port_clock,
+				 crtc_state->lane_count);
 
 	/*
 	 * 1. Enable Power Wells
@@ -3360,8 +3456,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 */
 
 	/* 7.e Configure voltage swing and related IO settings */
-	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
-				encoder->type);
+	tgl_ddi_vswing_sequence(encoder, crtc_state, level);
 
 	/*
 	 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
@@ -3384,10 +3479,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 * We only configure what the register value will be here.  Actual
 	 * enabling happens during link training farther down.
 	 */
-	intel_ddi_init_dp_buf_reg(encoder);
+	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
 
 	if (!is_mst)
-		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+		intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
 
 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
 	/*
@@ -3404,11 +3499,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	 *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
 	 *     (timeout after 800 us)
 	 */
-	intel_dp_start_link_train(intel_dp);
+	intel_dp_start_link_train(intel_dp, crtc_state);
 
 	/* 7.k Set DP_TP_CTL link training to Normal */
 	if (!is_trans_port_sync_mode(crtc_state))
-		intel_dp_stop_link_train(intel_dp);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
 
 	/* 7.l Configure and enable FEC if needed */
 	intel_ddi_enable_fec(encoder, crtc_state);
@@ -3434,8 +3529,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	else
 		drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
 
-	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
-				 crtc_state->lane_count, is_mst);
+	intel_dp_set_link_params(intel_dp,
+				 crtc_state->port_clock,
+				 crtc_state->lane_count);
 
 	intel_edp_panel_on(intel_dp);
 
@@ -3449,12 +3545,11 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	icl_program_mg_dp_mode(dig_port, crtc_state);
 
 	if (INTEL_GEN(dev_priv) >= 11)
-		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
-					level, encoder->type);
+		icl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_CANNONLAKE(dev_priv))
-		cnl_ddi_vswing_sequence(encoder, level, encoder->type);
+		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_GEN9_LP(dev_priv))
-		bxt_ddi_vswing_sequence(encoder, level, encoder->type);
+		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
 		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
@@ -3467,17 +3562,17 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 					       lane_reversal);
 	}
 
-	intel_ddi_init_dp_buf_reg(encoder);
+	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
 	if (!is_mst)
-		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+		intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
 	intel_dp_configure_protocol_converter(intel_dp);
 	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
 					      true);
 	intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
-	intel_dp_start_link_train(intel_dp);
+	intel_dp_start_link_train(intel_dp, crtc_state);
 	if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
 	    !is_trans_port_sync_mode(crtc_state))
-		intel_dp_stop_link_train(intel_dp);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
 
 	intel_ddi_enable_fec(encoder, crtc_state);
 
@@ -3517,7 +3612,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	int level = intel_ddi_hdmi_level(encoder);
+	int level = intel_ddi_hdmi_level(encoder, crtc_state);
 
 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
 	intel_ddi_clk_select(encoder, crtc_state);
@@ -3527,20 +3622,18 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
 	icl_program_mg_dp_mode(dig_port, crtc_state);
 
 	if (INTEL_GEN(dev_priv) >= 12)
-		tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
-					level, INTEL_OUTPUT_HDMI);
+		tgl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (INTEL_GEN(dev_priv) == 11)
-		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
-					level, INTEL_OUTPUT_HDMI);
+		icl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_CANNONLAKE(dev_priv))
-		cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
+		cnl_ddi_vswing_sequence(encoder, crtc_state, level);
 	else if (IS_GEN9_LP(dev_priv))
-		bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
+		bxt_ddi_vswing_sequence(encoder, crtc_state, level);
 	else
 		intel_prepare_hdmi_ddi_buffers(encoder, level);
 
 	if (IS_GEN9_BC(dev_priv))
-		skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
+		skl_ddi_set_iboost(encoder, crtc_state, level);
 
 	intel_ddi_enable_pipe_clock(encoder, crtc_state);
 
@@ -3612,12 +3705,10 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
 	}
 
 	if (intel_crtc_has_dp_encoder(crtc_state)) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+		val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
-		intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
+		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
 	}
 
 	/* Disable FEC in DP Sink */
@@ -3647,7 +3738,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
 	 * Power down sink before disabling the port, otherwise we end
 	 * up getting interrupts from the sink on detecting link loss.
 	 */
-	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+	intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		if (is_mst) {
@@ -3830,12 +3921,14 @@ static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
 		    crtc_state->cpu_transcoder)
 			continue;
 
-		intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder));
+		intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
+					 slave_crtc_state);
 	}
 
 	usleep_range(200, 400);
 
-	intel_dp_stop_link_train(enc_to_intel_dp(encoder));
+	intel_dp_stop_link_train(enc_to_intel_dp(encoder),
+				 crtc_state);
 }
 
 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
@@ -3848,7 +3941,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state,
 	enum port port = encoder->port;
 
 	if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
-		intel_dp_stop_link_train(intel_dp);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
 
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state, conn_state);
@@ -4109,15 +4202,16 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
 						crtc_state->lane_lat_optim_mask);
 }
 
-static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
+static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state)
 {
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-	enum port port = dig_port->base.port;
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
 	u32 dp_tp_ctl, ddi_buf_ctl;
 	bool wait = false;
 
-	dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 
 	if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
 		ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
@@ -4129,23 +4223,23 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 
 		dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 		dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
-		intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
-		intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
+		intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 
 		if (wait)
 			intel_wait_ddi_buf_idle(dev_priv, port);
 	}
 
 	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
-	if (intel_dp->link_mst)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 		dp_tp_ctl |= DP_TP_CTL_MODE_MST;
-	else {
+	} else {
 		dp_tp_ctl |= DP_TP_CTL_MODE_SST;
 		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 			dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
 	}
-	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
-	intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
+	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 
 	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
 	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
@@ -4155,16 +4249,17 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 }
 
 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state,
 				     u8 dp_train_pat)
 {
-	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	u32 temp;
 
-	temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 
 	temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
-	switch (dp_train_pat & train_pat_mask) {
+	switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
 	case DP_TRAINING_PATTERN_DISABLE:
 		temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
 		break;
@@ -4182,20 +4277,21 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
 		break;
 	}
 
-	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
+	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
 }
 
-static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
+static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
+					  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 	u32 val;
 
-	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
+	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
 	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
-	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
+	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
 
 	/*
 	 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
@@ -4207,7 +4303,8 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
 	if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
 		return;
 
-	if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
+	if (intel_de_wait_for_set(dev_priv,
+				  dp_tp_status_reg(encoder, crtc_state),
 				  DP_TP_STATUS_IDLE_DONE, 1))
 		drm_err(&dev_priv->drm,
 			"Timed out waiting for DP idle patterns\n");
@@ -4231,7 +4328,7 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 {
 	if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 2;
-	else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
+	else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 3;
 	else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
 		crtc_state->min_voltage_level = 1;
@@ -4305,7 +4402,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	u32 temp, flags = 0;
 
 	/* XXX: DSI transcoder paranoia */
@@ -4375,12 +4471,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 		intel_dp_get_m_n(intel_crtc, pipe_config);
 
 		if (INTEL_GEN(dev_priv) >= 11) {
-			i915_reg_t dp_tp_ctl;
-
-			if (IS_GEN(dev_priv, 11))
-				dp_tp_ctl = DP_TP_CTL(encoder->port);
-			else
-				dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
+			i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
 
 			pipe_config->fec_enable =
 				intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
@@ -4413,16 +4504,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 		break;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 12) {
-		enum transcoder transcoder =
-			intel_dp_mst_is_slave_trans(pipe_config) ?
-			pipe_config->mst_master_transcoder :
-			pipe_config->cpu_transcoder;
-
-		intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
-		intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
-	}
-
 	pipe_config->has_audio =
 		intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
 
@@ -4477,6 +4558,22 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
 }
 
+static void intel_ddi_sync_state(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
+{
+	if (intel_crtc_has_dp_encoder(crtc_state))
+		intel_dp_sync_state(encoder, crtc_state);
+}
+
+static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
+					    struct intel_crtc_state *crtc_state)
+{
+	if (intel_crtc_has_dp_encoder(crtc_state))
+		return intel_dp_initial_fastset_check(encoder, crtc_state);
+
+	return true;
+}
+
 static enum intel_output_type
 intel_ddi_compute_output_type(struct intel_encoder *encoder,
 			      struct intel_crtc_state *crtc_state,
@@ -4687,11 +4784,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
 	dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
 	dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
 
-	if (INTEL_GEN(dev_priv) < 12) {
-		dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
-		dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
-	}
-
 	if (!intel_dp_init_connector(dig_port, connector)) {
 		kfree(connector);
 		return NULL;
@@ -4974,11 +5066,20 @@ static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
 		 i915->hti_state & HDPORT_PHY_USED_HDMI(phy));
 }
 
+static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
+				enum port port)
+{
+	if (port >= PORT_TC1)
+		return HPD_PORT_C + port - PORT_TC1;
+	else
+		return HPD_PORT_A + port - PORT_A;
+}
+
 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
 				enum port port)
 {
-	if (port >= PORT_D)
-		return HPD_PORT_TC1 + port - PORT_D;
+	if (port >= PORT_TC1)
+		return HPD_PORT_TC1 + port - PORT_TC1;
 	else
 		return HPD_PORT_A + port - PORT_A;
 }
@@ -4989,8 +5090,8 @@ static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
 	if (HAS_PCH_TGP(dev_priv))
 		return tgl_hpd_pin(dev_priv, port);
 
-	if (port >= PORT_D)
-		return HPD_PORT_C + port - PORT_D;
+	if (port >= PORT_TC1)
+		return HPD_PORT_C + port - PORT_TC1;
 	else
 		return HPD_PORT_A + port - PORT_A;
 }
@@ -5029,7 +5130,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 {
 	struct intel_digital_port *dig_port;
 	struct intel_encoder *encoder;
-	bool init_hdmi, init_dp, init_lspcon = false;
+	bool init_hdmi, init_dp;
 	enum phy phy = intel_port_to_phy(dev_priv, port);
 
 	/*
@@ -5055,7 +5156,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 		 * is initialized before lspcon.
 		 */
 		init_dp = true;
-		init_lspcon = true;
 		init_hdmi = false;
 		drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
 			    port_name(port));
@@ -5074,8 +5174,31 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 
 	encoder = &dig_port->base;
 
-	drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
-			 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
+	if (INTEL_GEN(dev_priv) >= 12) {
+		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+				 DRM_MODE_ENCODER_TMDS,
+				 "DDI %s%c/PHY %s%c",
+				 port >= PORT_TC1 ? "TC" : "",
+				 port >= PORT_TC1 ? port_name(port) : port - PORT_TC1 + '1',
+				 tc_port != TC_PORT_NONE ? "TC" : "",
+				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+				 DRM_MODE_ENCODER_TMDS,
+				 "DDI %c%s/PHY %s%c",
+				 port_name(port),
+				 port >= PORT_C ? " (TC)" : "",
+				 tc_port != TC_PORT_NONE ? "TC" : "",
+				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');
+	} else {
+		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+				 DRM_MODE_ENCODER_TMDS,
+				 "DDI %c/PHY %c", port_name(port),  phy_name(phy));
+	}
 
 	mutex_init(&dig_port->hdcp_mutex);
 	dig_port->num_hdcp_streams = 0;
@@ -5092,7 +5215,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->update_pipe = intel_ddi_update_pipe;
 	encoder->get_hw_state = intel_ddi_get_hw_state;
 	encoder->get_config = intel_ddi_get_config;
+	encoder->sync_state = intel_ddi_sync_state;
+	encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
 	encoder->suspend = intel_dp_encoder_suspend;
+	encoder->shutdown = intel_dp_encoder_shutdown;
 	encoder->get_power_domains = intel_ddi_get_power_domains;
 
 	encoder->type = INTEL_OUTPUT_DDI;
@@ -5101,11 +5227,13 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	encoder->cloneable = 0;
 	encoder->pipe_mask = ~0;
 
-	if (IS_ROCKETLAKE(dev_priv))
+	if (IS_DG1(dev_priv))
+		encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
+	else if (IS_ROCKETLAKE(dev_priv))
 		encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
 	else if (INTEL_GEN(dev_priv) >= 12)
 		encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
-	else if (IS_ELKHARTLAKE(dev_priv))
+	else if (IS_JSL_EHL(dev_priv))
 		encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
 	else if (IS_GEN(dev_priv, 11))
 		encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
@@ -5156,22 +5284,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 			goto err;
 	}
 
-	if (init_lspcon) {
-		if (lspcon_init(dig_port))
-			/* TODO: handle hdmi info frame part */
-			drm_dbg_kms(&dev_priv->drm,
-				    "LSPCON init success on port %c\n",
-				    port_name(port));
-		else
-			/*
-			 * LSPCON init faied, but DP init was success, so
-			 * lets try to drive as DP++ port.
-			 */
-			drm_err(&dev_priv->drm,
-				"LSPCON init failed on port %c\n",
-				port_name(port));
-	}
-
 	if (INTEL_GEN(dev_priv) >= 11) {
 		if (intel_phy_is_tc(dev_priv, phy))
 			dig_port->connected = intel_tc_port_connected;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index f5fb62fc9400..dcc711cfe4fe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -7,6 +7,7 @@
 #define __INTEL_DDI_H__
 
 #include "intel_display.h"
+#include "i915_reg.h"
 
 struct drm_connector_state;
 struct drm_i915_private;
@@ -18,6 +19,10 @@ struct intel_dpll_hw_state;
 struct intel_encoder;
 enum transcoder;
 
+i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state);
+i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state);
 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
 				struct intel_encoder *intel_encoder,
 				const struct intel_crtc_state *old_crtc_state,
@@ -41,8 +46,10 @@ void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
 				    bool state);
 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
 					 struct intel_crtc_state *crtc_state);
-u32 bxt_signal_levels(struct intel_dp *intel_dp);
-u32 ddi_signal_levels(struct intel_dp *intel_dp);
+u32 bxt_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state);
+u32 ddi_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state);
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
 				     enum transcoder cpu_transcoder,
 				     bool enable);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 31337d2a2cde..cddbda5303ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -154,7 +154,7 @@ static void ilk_pch_clock_get(struct intel_crtc *crtc,
 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 				  struct drm_i915_gem_object *obj,
 				  struct drm_mode_fb_cmd2 *mode_cmd);
-static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
+static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
 					 const struct intel_link_m_n *m_n,
@@ -1808,6 +1808,17 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
 static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	u32 mode_flags = crtc->mode_flags;
+
+	/*
+	 * From Gen 11, In case of dsi cmd mode, frame counter wouldnt
+	 * have updated at the beginning of TE, if we want to use
+	 * the hw counter, then we would find it updated in only
+	 * the next TE, hence switching to sw counter.
+	 */
+	if (mode_flags & (I915_MODE_FLAG_DSI_USE_TE0 | I915_MODE_FLAG_DSI_USE_TE1))
+		return 0;
 
 	/*
 	 * On i965gm the hardware frame counter reads
@@ -1990,13 +2001,17 @@ static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
 	return ccs_plane - fb->format->num_planes / 2;
 }
 
-/* Return either the main plane's CCS or - if not a CCS FB - UV plane */
 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
 {
+	struct drm_i915_private *i915 = to_i915(fb->dev);
+
 	if (is_ccs_modifier(fb->modifier))
 		return main_to_ccs_plane(fb, main_plane);
-
-	return 1;
+	else if (INTEL_GEN(i915) < 11 &&
+		 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
+		return 1;
+	else
+		return 0;
 }
 
 bool
@@ -3930,7 +3945,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 	 * main surface offset, and it must be non-negative. Make
 	 * sure that is what we will get.
 	 */
-	if (offset > aux_offset)
+	if (aux_plane && offset > aux_offset)
 		offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 							   offset, aux_offset & ~(alignment - 1));
 
@@ -4019,8 +4034,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 
 	if (is_ccs_modifier(fb->modifier)) {
 		int ccs_plane = main_to_ccs_plane(fb, uv_plane);
-		int aux_offset = plane_state->color_plane[ccs_plane].offset;
-		int alignment = intel_surf_alignment(fb, uv_plane);
+		u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
+		u32 alignment = intel_surf_alignment(fb, uv_plane);
 
 		if (offset > aux_offset)
 			offset = intel_plane_adjust_aligned_offset(&x, &y,
@@ -4128,7 +4143,7 @@ int skl_check_plane_surface(struct intel_plane_state *plane_state)
 	}
 
 	for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane); i++) {
-		plane_state->color_plane[i].offset = ~0xfff;
+		plane_state->color_plane[i].offset = 0;
 		plane_state->color_plane[i].x = 0;
 		plane_state->color_plane[i].y = 0;
 	}
@@ -4786,6 +4801,9 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	u32 plane_ctl = 0;
 
+	if (crtc_state->uapi.async_flip)
+		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
+
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 		return plane_ctl;
 
@@ -5023,18 +5041,14 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
 		intel_pps_unlock_regs_wa(dev_priv);
 		intel_modeset_init_hw(dev_priv);
 		intel_init_clock_gating(dev_priv);
-
-		spin_lock_irq(&dev_priv->irq_lock);
-		if (dev_priv->display.hpd_irq_setup)
-			dev_priv->display.hpd_irq_setup(dev_priv);
-		spin_unlock_irq(&dev_priv->irq_lock);
+		intel_hpd_init(dev_priv);
 
 		ret = __intel_display_resume(dev, state, ctx);
 		if (ret)
 			drm_err(&dev_priv->drm,
 				"Restoring old state failed with %i\n", ret);
 
-		intel_hpd_init(dev_priv);
+		intel_hpd_poll_disable(dev_priv);
 	}
 
 	drm_atomic_state_put(state);
@@ -6275,6 +6289,105 @@ void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
 		skl_detach_scaler(crtc, i);
 }
 
+static int cnl_coef_tap(int i)
+{
+	return i % 7;
+}
+
+static u16 cnl_nearest_filter_coef(int t)
+{
+	return t == 3 ? 0x0800 : 0x3000;
+}
+
+/*
+ *  Theory behind setting nearest-neighbor integer scaling:
+ *
+ *  17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
+ *  The letter represents the filter tap (D is the center tap) and the number
+ *  represents the coefficient set for a phase (0-16).
+ *
+ *         +------------+------------------------+------------------------+
+ *         |Index value | Data value coeffient 1 | Data value coeffient 2 |
+ *         +------------+------------------------+------------------------+
+ *         |   00h      |          B0            |          A0            |
+ *         +------------+------------------------+------------------------+
+ *         |   01h      |          D0            |          C0            |
+ *         +------------+------------------------+------------------------+
+ *         |   02h      |          F0            |          E0            |
+ *         +------------+------------------------+------------------------+
+ *         |   03h      |          A1            |          G0            |
+ *         +------------+------------------------+------------------------+
+ *         |   04h      |          C1            |          B1            |
+ *         +------------+------------------------+------------------------+
+ *         |   ...      |          ...           |          ...           |
+ *         +------------+------------------------+------------------------+
+ *         |   38h      |          B16           |          A16           |
+ *         +------------+------------------------+------------------------+
+ *         |   39h      |          D16           |          C16           |
+ *         +------------+------------------------+------------------------+
+ *         |   3Ah      |          F16           |          C16           |
+ *         +------------+------------------------+------------------------+
+ *         |   3Bh      |        Reserved        |          G16           |
+ *         +------------+------------------------+------------------------+
+ *
+ *  To enable nearest-neighbor scaling:  program scaler coefficents with
+ *  the center tap (Dxx) values set to 1 and all other values set to 0 as per
+ *  SCALER_COEFFICIENT_FORMAT
+ *
+ */
+
+static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
+					     enum pipe pipe, int id, int set)
+{
+	int i;
+
+	intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
+			  PS_COEE_INDEX_AUTO_INC);
+
+	for (i = 0; i < 17 * 7; i += 2) {
+		u32 tmp;
+		int t;
+
+		t = cnl_coef_tap(i);
+		tmp = cnl_nearest_filter_coef(t);
+
+		t = cnl_coef_tap(i + 1);
+		tmp |= cnl_nearest_filter_coef(t) << 16;
+
+		intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
+				  tmp);
+	}
+
+	intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
+}
+
+inline u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
+{
+	if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
+		return (PS_FILTER_PROGRAMMED |
+			PS_Y_VERT_FILTER_SELECT(set) |
+			PS_Y_HORZ_FILTER_SELECT(set) |
+			PS_UV_VERT_FILTER_SELECT(set) |
+			PS_UV_HORZ_FILTER_SELECT(set));
+	}
+
+	return PS_FILTER_MEDIUM;
+}
+
+void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
+			     int id, int set, enum drm_scaling_filter filter)
+{
+	switch (filter) {
+	case DRM_SCALING_FILTER_DEFAULT:
+		break;
+	case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
+		cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
+		break;
+	default:
+		MISSING_CASE(filter);
+	}
+}
+
 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -6295,6 +6408,7 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
 	int hscale, vscale;
 	unsigned long irqflags;
 	int id;
+	u32 ps_ctrl;
 
 	if (!crtc_state->pch_pfit.enabled)
 		return;
@@ -6311,10 +6425,16 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
 
 	id = scaler_state->scaler_id;
 
+	ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
+	ps_ctrl |=  PS_SCALER_EN | scaler_state->scalers[id].mode;
+
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
-	intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
-			  PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
+	skl_scaler_setup_filter(dev_priv, pipe, id, 0,
+				crtc_state->hw.scaling_filter);
+
+	intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
+
 	intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
 			  PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
 	intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
@@ -6560,6 +6680,43 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 		icl_wa_scalerclkgating(dev_priv, pipe, false);
 }
 
+static void skl_disable_async_flip_wa(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc,
+				      const struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_plane *plane;
+	struct intel_plane_state *new_plane_state;
+	int i;
+
+	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
+		u32 update_mask = new_crtc_state->update_planes;
+		u32 plane_ctl, surf_addr;
+		enum plane_id plane_id;
+		unsigned long irqflags;
+		enum pipe pipe;
+
+		if (crtc->pipe != plane->pipe ||
+		    !(update_mask & BIT(plane->id)))
+			continue;
+
+		plane_id = plane->id;
+		pipe = plane->pipe;
+
+		spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+		plane_ctl = intel_de_read_fw(dev_priv, PLANE_CTL(pipe, plane_id));
+		surf_addr = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id));
+
+		plane_ctl &= ~PLANE_CTL_ASYNC_FLIP;
+
+		intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+		intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), surf_addr);
+		spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+	}
+
+	intel_wait_for_vblank(dev_priv, crtc->pipe);
+}
+
 static void intel_pre_plane_update(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc)
 {
@@ -6645,6 +6802,15 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 	 */
 	if (IS_GEN(dev_priv, 2) && planes_disabling(old_crtc_state, new_crtc_state))
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+
+	/*
+	 * WA for platforms where async address update enable bit
+	 * is double buffered and only latched at start of vblank.
+	 */
+	if (old_crtc_state->uapi.async_flip &&
+	    !new_crtc_state->uapi.async_flip &&
+	    IS_GEN_RANGE(dev_priv, 9, 10))
+		skl_disable_async_flip_wa(state, crtc, new_crtc_state);
 }
 
 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
@@ -6944,7 +7110,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 	if (intel_crtc_has_dp_encoder(new_crtc_state))
 		intel_dp_set_m_n(new_crtc_state, M1_N1);
 
-	intel_set_pipe_timings(new_crtc_state);
+	intel_set_transcoder_timings(new_crtc_state);
 	intel_set_pipe_src_size(new_crtc_state);
 
 	if (new_crtc_state->has_pch_encoder)
@@ -7089,7 +7255,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
 	intel_encoders_pre_enable(state, crtc);
 
 	if (!transcoder_is_dsi(cpu_transcoder))
-		intel_set_pipe_timings(new_crtc_state);
+		intel_set_transcoder_timings(new_crtc_state);
 
 	intel_set_pipe_src_size(new_crtc_state);
 
@@ -7275,7 +7441,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 		return false;
 	else if (IS_ROCKETLAKE(dev_priv))
 		return phy <= PHY_D;
-	else if (IS_ELKHARTLAKE(dev_priv))
+	else if (IS_JSL_EHL(dev_priv))
 		return phy <= PHY_C;
 	else if (INTEL_GEN(dev_priv) >= 11)
 		return phy <= PHY_B;
@@ -7289,7 +7455,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 		return false;
 	else if (INTEL_GEN(dev_priv) >= 12)
 		return phy >= PHY_D && phy <= PHY_I;
-	else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+	else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv))
 		return phy >= PHY_C && phy <= PHY_F;
 	else
 		return false;
@@ -7297,23 +7463,23 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
-		return (enum phy)port - 1;
-	else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
+	if (IS_ROCKETLAKE(i915) && port >= PORT_TC1)
+		return PHY_C + port - PORT_TC1;
+	else if (IS_JSL_EHL(i915) && port == PORT_D)
 		return PHY_A;
 
-	return (enum phy)port;
+	return PHY_A + port - PORT_A;
 }
 
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 {
 	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
-		return PORT_TC_NONE;
+		return TC_PORT_NONE;
 
 	if (INTEL_GEN(dev_priv) >= 12)
-		return port - PORT_D;
-
-	return port - PORT_C;
+		return TC_PORT_1 + port - PORT_TC1;
+	else
+		return TC_PORT_1 + port - PORT_C;
 }
 
 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
@@ -7484,7 +7650,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 	if (intel_crtc_has_dp_encoder(new_crtc_state))
 		intel_dp_set_m_n(new_crtc_state, M1_N1);
 
-	intel_set_pipe_timings(new_crtc_state);
+	intel_set_transcoder_timings(new_crtc_state);
 	intel_set_pipe_src_size(new_crtc_state);
 
 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
@@ -7552,7 +7718,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
 	if (intel_crtc_has_dp_encoder(new_crtc_state))
 		intel_dp_set_m_n(new_crtc_state, M1_N1);
 
-	intel_set_pipe_timings(new_crtc_state);
+	intel_set_transcoder_timings(new_crtc_state);
 	intel_set_pipe_src_size(new_crtc_state);
 
 	i9xx_set_pipeconf(new_crtc_state);
@@ -8806,7 +8972,7 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
 	crtc_state->dpll_hw_state.dpll = dpll;
 }
 
-static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state)
+static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -8892,8 +9058,8 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
 		return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
 }
 
-static void intel_get_pipe_timings(struct intel_crtc *crtc,
-				   struct intel_crtc_state *pipe_config)
+static void intel_get_transcoder_timings(struct intel_crtc *crtc,
+					 struct intel_crtc_state *pipe_config)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -9516,7 +9682,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	if (INTEL_GEN(dev_priv) < 4)
 		pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
 
-	intel_get_pipe_timings(crtc, pipe_config);
+	intel_get_transcoder_timings(crtc, pipe_config);
 	intel_get_pipe_src_size(crtc, pipe_config);
 
 	i9xx_get_pfit_config(pipe_config);
@@ -10801,7 +10967,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
 		pipe_config->pixel_multiplier = 1;
 	}
 
-	intel_get_pipe_timings(crtc, pipe_config);
+	intel_get_transcoder_timings(crtc, pipe_config);
 	intel_get_pipe_src_size(crtc, pipe_config);
 
 	ilk_get_pfit_config(pipe_config);
@@ -11218,7 +11384,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
 	    INTEL_GEN(dev_priv) >= 11) {
 		hsw_get_ddi_port_state(crtc, pipe_config);
-		intel_get_pipe_timings(crtc, pipe_config);
+		intel_get_transcoder_timings(crtc, pipe_config);
 	}
 
 	intel_get_pipe_src_size(crtc, pipe_config);
@@ -11234,18 +11400,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 	} else {
 		pipe_config->output_format =
 			bdw_get_pipemisc_output_format(crtc);
-
-		/*
-		 * Currently there is no interface defined to
-		 * check user preference between RGB/YCBCR444
-		 * or YCBCR420. So the only possible case for
-		 * YCBCR444 usage is driving YCBCR420 output
-		 * with LSPCON, when pipe is configured for
-		 * YCBCR444 output and LSPCON takes care of
-		 * downsampling it.
-		 */
-		pipe_config->lspcon_downsampling =
-			pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444;
 	}
 
 	pipe_config->gamma_mode = intel_de_read(dev_priv,
@@ -11817,6 +11971,9 @@ static void i9xx_update_cursor(struct intel_plane *plane,
 	if (INTEL_GEN(dev_priv) >= 9)
 		skl_write_cursor_wm(plane, crtc_state);
 
+	if (!needs_modeset(crtc_state))
+		intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
+
 	if (plane->cursor.base != base ||
 	    plane->cursor.size != fbc_ctl ||
 	    plane->cursor.cntl != cntl) {
@@ -12828,8 +12985,11 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 
 	}
 
-	if (!mode_changed)
-		intel_psr2_sel_fetch_update(state, crtc);
+	if (!mode_changed) {
+		ret = intel_psr2_sel_fetch_update(state, crtc);
+		if (ret)
+			return ret;
+	}
 
 	return 0;
 }
@@ -13102,6 +13262,9 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 		    transcoder_name(pipe_config->cpu_transcoder),
 		    pipe_config->pipe_bpp, pipe_config->dither);
 
+	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
+		    transcoder_name(pipe_config->mst_master_transcoder));
+
 	drm_dbg_kms(&dev_priv->drm,
 		    "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
 		    transcoder_name(pipe_config->master_transcoder),
@@ -13199,8 +13362,11 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 			    pipe_config->csc_mode, pipe_config->gamma_mode,
 			    pipe_config->gamma_enable, pipe_config->csc_enable);
 
-	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
-		    transcoder_name(pipe_config->mst_master_transcoder));
+	drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
+		    pipe_config->hw.degamma_lut ?
+		    drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
+		    pipe_config->hw.gamma_lut ?
+		    drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
 
 dump_planes:
 	if (!state)
@@ -13294,6 +13460,7 @@ intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state)
 	crtc_state->hw.active = crtc_state->uapi.active;
 	crtc_state->hw.mode = crtc_state->uapi.mode;
 	crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode;
+	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
 	intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state);
 }
 
@@ -13305,6 +13472,7 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
 		    drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
 
 	crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
+	crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
 
 	/* copy color blobs to uapi */
 	drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
@@ -14852,8 +15020,10 @@ static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
 	int i;
 
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
-		int ret = intel_crtc_atomic_check(state, crtc);
 		struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+		int ret;
+
+		ret = intel_crtc_atomic_check(state, crtc);
 		if (ret) {
 			drm_dbg_atomic(&i915->drm,
 				       "[CRTC:%d:%s] atomic driver check failed\n",
@@ -14883,6 +15053,139 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
 }
 
 /**
+ * DOC: asynchronous flip implementation
+ *
+ * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
+ * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
+ * Correspondingly, support is currently added for primary plane only.
+ *
+ * Async flip can only change the plane surface address, so anything else
+ * changing is rejected from the intel_atomic_check_async() function.
+ * Once this check is cleared, flip done interrupt is enabled using
+ * the skl_enable_flip_done() function.
+ *
+ * As soon as the surface address register is written, flip done interrupt is
+ * generated and the requested events are sent to the usersapce in the interrupt
+ * handler itself. The timestamp and sequence sent during the flip done event
+ * correspond to the last vblank and have no relation to the actual time when
+ * the flip done event was sent.
+ */
+static int intel_atomic_check_async(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+	const struct intel_plane_state *new_plane_state, *old_plane_state;
+	struct intel_crtc *crtc;
+	struct intel_plane *plane;
+	int i;
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		if (needs_modeset(new_crtc_state)) {
+			drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
+			return -EINVAL;
+		}
+
+		if (!new_crtc_state->hw.active) {
+			drm_dbg_kms(&i915->drm, "CRTC inactive\n");
+			return -EINVAL;
+		}
+		if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
+			drm_dbg_kms(&i915->drm,
+				    "Active planes cannot be changed during async flip\n");
+			return -EINVAL;
+		}
+	}
+
+	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
+					     new_plane_state, i) {
+		/*
+		 * TODO: Async flip is only supported through the page flip IOCTL
+		 * as of now. So support currently added for primary plane only.
+		 * Support for other planes on platforms on which supports
+		 * this(vlv/chv and icl+) should be added when async flip is
+		 * enabled in the atomic IOCTL path.
+		 */
+		if (plane->id != PLANE_PRIMARY)
+			return -EINVAL;
+
+		/*
+		 * FIXME: This check is kept generic for all platforms.
+		 * Need to verify this for all gen9 and gen10 platforms to enable
+		 * this selectively if required.
+		 */
+		switch (new_plane_state->hw.fb->modifier) {
+		case I915_FORMAT_MOD_X_TILED:
+		case I915_FORMAT_MOD_Y_TILED:
+		case I915_FORMAT_MOD_Yf_TILED:
+			break;
+		default:
+			drm_dbg_kms(&i915->drm,
+				    "Linear memory/CCS does not support async flips\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->color_plane[0].stride !=
+		    new_plane_state->color_plane[0].stride) {
+			drm_dbg_kms(&i915->drm, "Stride cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.fb->modifier !=
+		    new_plane_state->hw.fb->modifier) {
+			drm_dbg_kms(&i915->drm,
+				    "Framebuffer modifiers cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.fb->format !=
+		    new_plane_state->hw.fb->format) {
+			drm_dbg_kms(&i915->drm,
+				    "Framebuffer format cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.rotation !=
+		    new_plane_state->hw.rotation) {
+			drm_dbg_kms(&i915->drm, "Rotation cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
+		    !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
+			drm_dbg_kms(&i915->drm,
+				    "Plane size/co-ordinates cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
+			drm_dbg_kms(&i915->drm, "Alpha value cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.pixel_blend_mode !=
+		    new_plane_state->hw.pixel_blend_mode) {
+			drm_dbg_kms(&i915->drm,
+				    "Pixel blend mode cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
+			drm_dbg_kms(&i915->drm,
+				    "Color encoding cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
+			drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+/**
  * intel_atomic_check - validate state object
  * @dev: drm device
  * @_state: state to validate
@@ -15050,6 +15353,12 @@ static int intel_atomic_check(struct drm_device *dev,
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip) {
+			ret = intel_atomic_check_async(state);
+			if (ret)
+				goto fail;
+		}
+
 		if (!needs_modeset(new_crtc_state) &&
 		    !new_crtc_state->update_pipe)
 			continue;
@@ -15615,6 +15924,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 
 	intel_dbuf_pre_plane_update(state);
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip)
+			skl_enable_flip_done(crtc);
+	}
+
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	dev_priv->display.commit_modeset_enables(state);
 
@@ -15636,6 +15950,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip)
+			skl_disable_flip_done(crtc);
+
 		if (new_crtc_state->hw.active &&
 		    !needs_modeset(new_crtc_state) &&
 		    !new_crtc_state->preload_luts &&
@@ -16750,6 +17067,11 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 		dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
 	}
 
+	if (INTEL_GEN(dev_priv) >= 10)
+		drm_crtc_create_scaling_filter_property(&crtc->base,
+						BIT(DRM_SCALING_FILTER_DEFAULT) |
+						BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
+
 	intel_color_init(crtc);
 
 	intel_crtc_crc_init(crtc);
@@ -16894,19 +17216,19 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (IS_ROCKETLAKE(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
-		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
-		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
+		intel_ddi_init(dev_priv, PORT_TC1);
+		intel_ddi_init(dev_priv, PORT_TC2);
 	} else if (INTEL_GEN(dev_priv) >= 12) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
-		intel_ddi_init(dev_priv, PORT_D);
-		intel_ddi_init(dev_priv, PORT_E);
-		intel_ddi_init(dev_priv, PORT_F);
-		intel_ddi_init(dev_priv, PORT_G);
-		intel_ddi_init(dev_priv, PORT_H);
-		intel_ddi_init(dev_priv, PORT_I);
+		intel_ddi_init(dev_priv, PORT_TC1);
+		intel_ddi_init(dev_priv, PORT_TC2);
+		intel_ddi_init(dev_priv, PORT_TC2);
+		intel_ddi_init(dev_priv, PORT_TC4);
+		intel_ddi_init(dev_priv, PORT_TC5);
+		intel_ddi_init(dev_priv, PORT_TC6);
 		icl_dsi_init(dev_priv);
-	} else if (IS_ELKHARTLAKE(dev_priv)) {
+	} else if (IS_JSL_EHL(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
@@ -17741,6 +18063,8 @@ retry:
 		}
 
 		if (crtc_state->hw.active) {
+			struct intel_encoder *encoder;
+
 			/*
 			 * We've not yet detected sink capabilities
 			 * (audio,infoframes,etc.) and thus we don't want to
@@ -17762,22 +18086,15 @@ retry:
 			 */
 			crtc_state->uapi.color_mgmt_changed = true;
 
-			/*
-			 * FIXME hack to force full modeset when DSC is being
-			 * used.
-			 *
-			 * As long as we do not have full state readout and
-			 * config comparison of crtc_state->dsc, we have no way
-			 * to ensure reliable fastset. Remove once we have
-			 * readout for DSC.
-			 */
-			if (crtc_state->dsc.compression_enable) {
-				ret = drm_atomic_add_affected_connectors(state,
-									 &crtc->base);
-				if (ret)
-					goto out;
-				crtc_state->uapi.mode_changed = true;
-				drm_dbg_kms(dev, "Force full modeset for DSC\n");
+			for_each_intel_encoder_mask(dev, encoder,
+						    crtc_state->uapi.encoder_mask) {
+				if (encoder->initial_fastset_check &&
+				    !encoder->initial_fastset_check(encoder, crtc_state)) {
+					ret = drm_atomic_add_affected_connectors(state,
+										 &crtc->base);
+					if (ret)
+						goto out;
+				}
 			}
 		}
 	}
@@ -17816,6 +18133,9 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
 
 	mode_config->funcs = &intel_mode_funcs;
 
+	if (INTEL_GEN(i915) >= 9)
+		mode_config->async_page_flip = true;
+
 	/*
 	 * Maximum framebuffer dimensions, chosen to match
 	 * the maximum render engine surface size on gen4+.
@@ -18049,6 +18369,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
 
 	/* Only enable hotplug handling once the fbdev is fully set up. */
 	intel_hpd_init(i915);
+	intel_hpd_poll_disable(i915);
 
 	intel_init_ipc(i915);
 
@@ -18515,6 +18836,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 
 			encoder->base.crtc = &crtc->base;
 			encoder->get_config(encoder, crtc_state);
+			if (encoder->sync_state)
+				encoder->sync_state(encoder, crtc_state);
 		} else {
 			encoder->base.crtc = NULL;
 		}
@@ -18685,6 +19008,15 @@ static void intel_early_display_was(struct drm_i915_private *dev_priv)
 		intel_de_write(dev_priv, CHICKEN_PAR1_1,
 			       intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
 	}
+
+	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
+		/* Display WA #1142:kbl,cfl,cml */
+		intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
+			     KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
+		intel_de_rmw(dev_priv, CHICKEN_MISC_2,
+			     KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
+			     KBL_ARB_FILL_SPARE_14);
+	}
 }
 
 static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d10b7c8cde3f..be774f216065 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -28,6 +28,7 @@
 #include <drm/drm_util.h>
 
 enum link_m_n_set;
+enum drm_scaling_filter;
 struct dpll;
 struct drm_connector;
 struct drm_device;
@@ -207,6 +208,14 @@ enum port {
 	PORT_H,
 	PORT_I,
 
+	/* tgl+ */
+	PORT_TC1 = PORT_D,
+	PORT_TC2,
+	PORT_TC3,
+	PORT_TC4,
+	PORT_TC5,
+	PORT_TC6,
+
 	I915_MAX_PORTS
 };
 
@@ -243,14 +252,14 @@ static inline const char *port_identifier(enum port port)
 }
 
 enum tc_port {
-	PORT_TC_NONE = -1,
+	TC_PORT_NONE = -1,
 
-	PORT_TC1 = 0,
-	PORT_TC2,
-	PORT_TC3,
-	PORT_TC4,
-	PORT_TC5,
-	PORT_TC6,
+	TC_PORT_1 = 0,
+	TC_PORT_2,
+	TC_PORT_3,
+	TC_PORT_4,
+	TC_PORT_5,
+	TC_PORT_6,
 
 	I915_MAX_TC_PORTS
 };
@@ -282,6 +291,14 @@ enum aux_ch {
 	AUX_CH_G,
 	AUX_CH_H,
 	AUX_CH_I,
+
+	/* tgl+ */
+	AUX_CH_USBC1 = AUX_CH_D,
+	AUX_CH_USBC2,
+	AUX_CH_USBC3,
+	AUX_CH_USBC4,
+	AUX_CH_USBC5,
+	AUX_CH_USBC6,
 };
 
 #define aux_ch_name(a) ((a) + 'A')
@@ -599,6 +616,9 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 
 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
+u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set);
+void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
+			     int id, int set, enum drm_scaling_filter filter);
 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 			const struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 0bf31f9a8af5..cfb4c1474982 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -518,8 +518,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 		   CSR_VERSION_MINOR(csr->version));
 
 	if (INTEL_GEN(dev_priv) >= 12) {
-		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
-		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+		if (IS_DGFX(dev_priv)) {
+			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
+		} else {
+			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
+			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+		}
+
 		/*
 		 * NOTE: DMC_DEBUG3 is a general purpose reg.
 		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7277e58b01f1..689922480661 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1424,6 +1424,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 		return;
 
 	intel_hpd_init(dev_priv);
+	intel_hpd_poll_disable(dev_priv);
 
 	/* Re-enable the ADPA, if we have one */
 	for_each_intel_encoder(&dev_priv->drm, encoder) {
@@ -1449,7 +1450,7 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 
 	/* Prevent us from re-enabling polling on accident in late suspend */
 	if (!dev_priv->drm.dev->power.is_suspended)
-		intel_hpd_poll_init(dev_priv);
+		intel_hpd_poll_enable(dev_priv);
 }
 
 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
@@ -3650,7 +3651,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
 		.name = "DDI F IO power well",
 		.domains = CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
+		.id = CNL_DISP_PW_DDI_F_IO,
 		{
 			.hsw.regs = &hsw_power_well_regs,
 			.hsw.idx = CNL_PW_CTL_IDX_DDI_F,
@@ -3660,7 +3661,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
 		.name = "AUX F",
 		.domains = CNL_DISPLAY_AUX_F_POWER_DOMAINS,
 		.ops = &hsw_power_well_ops,
-		.id = DISP_PW_ID_NONE,
+		.id = CNL_DISP_PW_DDI_F_AUX,
 		{
 			.hsw.regs = &hsw_power_well_regs,
 			.hsw.idx = CNL_PW_CTL_IDX_AUX_F,
@@ -4150,7 +4151,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
 		.name = "TC cold off",
 		.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
 		.ops = &tgl_tc_cold_off_ops,
-		.id = DISP_PW_ID_NONE,
+		.id = TGL_DISP_PW_TC_COLD_OFF,
 	},
 	{
 		.name = "AUX A",
@@ -4492,7 +4493,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	int max_dc;
 
 	if (INTEL_GEN(dev_priv) >= 12) {
-		max_dc = 4;
+		if (IS_DG1(dev_priv))
+			max_dc = 3;
+		else
+			max_dc = 4;
 		/*
 		 * DC9 has a separate HW flow from the rest of the DC states,
 		 * not depending on the DMC firmware. It's needed by system
@@ -4554,13 +4558,18 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 static int
 __set_power_wells(struct i915_power_domains *power_domains,
 		  const struct i915_power_well_desc *power_well_descs,
-		  int power_well_count)
+		  int power_well_descs_sz, u64 skip_mask)
 {
 	struct drm_i915_private *i915 = container_of(power_domains,
 						     struct drm_i915_private,
 						     power_domains);
 	u64 power_well_ids = 0;
-	int i;
+	int power_well_count = 0;
+	int i, plt_idx = 0;
+
+	for (i = 0; i < power_well_descs_sz; i++)
+		if (!(BIT_ULL(power_well_descs[i].id) & skip_mask))
+			power_well_count++;
 
 	power_domains->power_well_count = power_well_count;
 	power_domains->power_wells =
@@ -4570,10 +4579,14 @@ __set_power_wells(struct i915_power_domains *power_domains,
 	if (!power_domains->power_wells)
 		return -ENOMEM;
 
-	for (i = 0; i < power_well_count; i++) {
+	for (i = 0; i < power_well_descs_sz; i++) {
 		enum i915_power_well_id id = power_well_descs[i].id;
 
-		power_domains->power_wells[i].desc = &power_well_descs[i];
+		if (BIT_ULL(id) & skip_mask)
+			continue;
+
+		power_domains->power_wells[plt_idx++].desc =
+			&power_well_descs[i];
 
 		if (id == DISP_PW_ID_NONE)
 			continue;
@@ -4586,9 +4599,12 @@ __set_power_wells(struct i915_power_domains *power_domains,
 	return 0;
 }
 
-#define set_power_wells(power_domains, __power_well_descs) \
+#define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \
 	__set_power_wells(power_domains, __power_well_descs, \
-			  ARRAY_SIZE(__power_well_descs))
+			  ARRAY_SIZE(__power_well_descs), skip_mask)
+
+#define set_power_wells(power_domains, __power_well_descs) \
+	set_power_wells_mask(power_domains, __power_well_descs, 0)
 
 /**
  * intel_power_domains_init - initializes the power domain structures
@@ -4622,23 +4638,21 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	 * The enabling order will be from lower to higher indexed wells,
 	 * the disabling order is reversed.
 	 */
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		err = set_power_wells_mask(power_domains, tgl_power_wells,
+					   BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		err = set_power_wells(power_domains, rkl_power_wells);
 	} else if (IS_GEN(dev_priv, 12)) {
 		err = set_power_wells(power_domains, tgl_power_wells);
 	} else if (IS_GEN(dev_priv, 11)) {
 		err = set_power_wells(power_domains, icl_power_wells);
-	} else if (IS_CANNONLAKE(dev_priv)) {
+	} else if (IS_CNL_WITH_PORT_F(dev_priv)) {
 		err = set_power_wells(power_domains, cnl_power_wells);
-
-		/*
-		 * DDI and Aux IO are getting enabled for all ports
-		 * regardless the presence or use. So, in order to avoid
-		 * timeouts, lets remove them from the list
-		 * for the SKUs without port F.
-		 */
-		if (!IS_CNL_WITH_PORT_F(dev_priv))
-			power_domains->power_well_count -= 2;
+	} else if (IS_CANNONLAKE(dev_priv)) {
+		err = set_power_wells_mask(power_domains, cnl_power_wells,
+					   BIT_ULL(CNL_DISP_PW_DDI_F_IO) |
+					   BIT_ULL(CNL_DISP_PW_DDI_F_AUX));
 	} else if (IS_GEMINILAKE(dev_priv)) {
 		err = set_power_wells(power_domains, glk_power_wells);
 	} else if (IS_BROXTON(dev_priv)) {
@@ -4758,6 +4772,17 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
 	gen9_dbuf_slices_update(dev_priv, 0);
 }
 
+static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
+{
+	const int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+	enum dbuf_slice slice;
+
+	for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++)
+		intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
+			     DBUF_TRACKER_STATE_SERVICE_MASK,
+			     DBUF_TRACKER_STATE_SERVICE(8));
+}
+
 static void icl_mbus_init(struct drm_i915_private *dev_priv)
 {
 	unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
@@ -5263,8 +5288,9 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
 	int config, i;
 
-	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
-		/* Wa_1409767108: tgl */
+	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+		/* Wa_1409767108:tgl,dg1 */
 		table = wa_1409767108_buddy_page_masks;
 	else
 		table = tgl_buddy_page_masks;
@@ -5326,6 +5352,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	/* 4. Enable CDCLK. */
 	intel_cdclk_init_hw(dev_priv);
 
+	if (INTEL_GEN(dev_priv) >= 12)
+		gen12_dbuf_slices_config(dev_priv);
+
 	/* 5. Enable DBUF. */
 	gen9_dbuf_enable(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 54c20c76057e..4aa0a09cf14f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -101,8 +101,11 @@ enum i915_power_well_id {
 	SKL_DISP_PW_MISC_IO,
 	SKL_DISP_PW_1,
 	SKL_DISP_PW_2,
+	CNL_DISP_PW_DDI_F_IO,
+	CNL_DISP_PW_DDI_F_AUX,
 	ICL_DISP_PW_3,
 	SKL_DISP_DC_OFF,
+	TGL_DISP_PW_TC_COLD_OFF,
 };
 
 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3d4bf9b6a0a2..f6f0626649e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -187,6 +187,21 @@ struct intel_encoder {
 	 * be set correctly before calling this function. */
 	void (*get_config)(struct intel_encoder *,
 			   struct intel_crtc_state *pipe_config);
+
+	/*
+	 * Optional hook called during init/resume to sync any state
+	 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
+	 */
+	void (*sync_state)(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state);
+
+	/*
+	 * Optional hook, returning true if this encoder allows a fastset
+	 * during the initial commit, false otherwise.
+	 */
+	bool (*initial_fastset_check)(struct intel_encoder *encoder,
+				      struct intel_crtc_state *crtc_state);
+
 	/*
 	 * Acquires the power domains needed for an active encoder during
 	 * hardware state readout.
@@ -199,6 +214,11 @@ struct intel_encoder {
 	 * device interrupts are disabled.
 	 */
 	void (*suspend)(struct intel_encoder *);
+	/*
+	 * Called during system reboot/shutdown after all the
+	 * encoders have been disabled and suspended.
+	 */
+	void (*shutdown)(struct intel_encoder *encoder);
 	enum hpd_pin hpd_pin;
 	enum intel_display_power_domain power_domain;
 	/* for communication with audio component; protected by av_mutex */
@@ -515,6 +535,7 @@ struct intel_plane_state {
 		unsigned int rotation;
 		enum drm_color_encoding color_encoding;
 		enum drm_color_range color_range;
+		enum drm_scaling_filter scaling_filter;
 	} hw;
 
 	struct i915_ggtt_view view;
@@ -805,6 +826,7 @@ struct intel_crtc_state {
 		bool active, enable;
 		struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
 		struct drm_display_mode mode, adjusted_mode;
+		enum drm_scaling_filter scaling_filter;
 	} hw;
 
 	/**
@@ -1035,9 +1057,6 @@ struct intel_crtc_state {
 	/* Output format RGB/YCBCR etc */
 	enum intel_output_format output_format;
 
-	/* Output down scaling is done in LSPCON device */
-	bool lspcon_downsampling;
-
 	/* enable pipe gamma? */
 	bool gamma_enable;
 
@@ -1183,6 +1202,9 @@ struct intel_plane {
 			   struct intel_plane_state *plane_state);
 	int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
 			 const struct intel_plane_state *plane_state);
+	void (*async_flip)(struct intel_plane *plane,
+			   const struct intel_crtc_state *crtc_state,
+			   const struct intel_plane_state *plane_state);
 };
 
 struct intel_watermark_params {
@@ -1270,7 +1292,6 @@ struct intel_dp {
 	int link_rate;
 	u8 lane_count;
 	u8 sink_count;
-	bool link_mst;
 	bool link_trained;
 	bool has_hdmi_sink;
 	bool has_audio;
@@ -1280,6 +1301,8 @@ struct intel_dp {
 	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 	u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
+	u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
+	u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
 	u8 fec_capable;
 	/* source rates */
 	int num_source_rates;
@@ -1312,8 +1335,6 @@ struct intel_dp {
 	unsigned long last_backlight_off;
 	ktime_t panel_power_off_time;
 
-	struct notifier_block edp_notifier;
-
 	/*
 	 * Pipe whose power sequencer is currently locked into
 	 * this port. Only relevant on VLV/CHV.
@@ -1336,14 +1357,6 @@ struct intel_dp {
 	bool is_mst;
 	int active_mst_links;
 
-	/*
-	 * DP_TP_* registers may be either on port or transcoder register space.
-	 */
-	struct {
-		i915_reg_t dp_tp_ctl;
-		i915_reg_t dp_tp_status;
-	} regs;
-
 	/* connector directly attached - won't be use for modeset in mst world */
 	struct intel_connector *attached_connector;
 
@@ -1363,13 +1376,19 @@ struct intel_dp {
 	i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
 
 	/* This is called before a link training is starterd */
-	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
-	void (*set_link_train)(struct intel_dp *intel_dp, u8 dp_train_pat);
-	void (*set_idle_link_train)(struct intel_dp *intel_dp);
-	void (*set_signal_levels)(struct intel_dp *intel_dp);
+	void (*prepare_link_retrain)(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state);
+	void (*set_link_train)(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state,
+			       u8 dp_train_pat);
+	void (*set_idle_link_train)(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state);
+	void (*set_signal_levels)(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state);
 
 	u8 (*preemph_max)(struct intel_dp *intel_dp);
-	u8 (*voltage_max)(struct intel_dp *intel_dp);
+	u8 (*voltage_max)(struct intel_dp *intel_dp,
+			  const struct intel_crtc_state *crtc_state);
 
 	/* Displayport compliance testing */
 	struct intel_dp_compliance compliance;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index bf1e9cf1c0f3..cf09aca7607b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -28,7 +28,6 @@
 #include <linux/export.h>
 #include <linux/i2c.h>
 #include <linux/notifier.h>
-#include <linux/reboot.h>
 #include <linux/slab.h>
 #include <linux/types.h>
 
@@ -161,6 +160,7 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 		162000, 270000, 540000, 810000
 	};
 	int i, max_rate;
+	int max_lttpr_rate;
 
 	if (drm_dp_has_quirk(&intel_dp->desc, 0,
 			     DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
@@ -174,6 +174,9 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 	}
 
 	max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
+	max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
+	if (max_lttpr_rate)
+		max_rate = min(max_rate, max_lttpr_rate);
 
 	for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 		if (dp_rates[i] > max_rate)
@@ -219,6 +222,10 @@ static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 	int source_max = dig_port->max_lanes;
 	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 	int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
+	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
+
+	if (lttpr_max)
+		sink_max = min(sink_max, lttpr_max);
 
 	return min3(source_max, sink_max, fia_max);
 }
@@ -277,13 +284,20 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
 	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 
 	if (intel_phy_is_combo(dev_priv, phy) &&
-	    !IS_ELKHARTLAKE(dev_priv) &&
 	    !intel_dp_is_edp(intel_dp))
 		return 540000;
 
 	return 810000;
 }
 
+static int ehl_max_source_rate(struct intel_dp *intel_dp)
+{
+	if (intel_dp_is_edp(intel_dp))
+		return 540000;
+
+	return 810000;
+}
+
 static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
@@ -318,6 +332,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 		size = ARRAY_SIZE(cnl_rates);
 		if (IS_GEN(dev_priv, 10))
 			max_rate = cnl_max_source_rate(intel_dp);
+		else if (IS_JSL_EHL(dev_priv))
+			max_rate = ehl_max_source_rate(intel_dp);
 		else
 			max_rate = icl_max_source_rate(intel_dp);
 	} else if (IS_GEN9_LP(dev_priv)) {
@@ -592,6 +608,54 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 	return 0;
 }
 
+static enum intel_output_format
+intel_dp_output_format(struct drm_connector *connector,
+		       const struct drm_display_mode *mode)
+{
+	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
+	const struct drm_display_info *info = &connector->display_info;
+
+	if (!connector->ycbcr_420_allowed ||
+	    !drm_mode_is_420_only(info, mode))
+		return INTEL_OUTPUT_FORMAT_RGB;
+
+	if (intel_dp->dfp.ycbcr_444_to_420)
+		return INTEL_OUTPUT_FORMAT_YCBCR444;
+	else
+		return INTEL_OUTPUT_FORMAT_YCBCR420;
+}
+
+int intel_dp_min_bpp(enum intel_output_format output_format)
+{
+	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
+		return 6 * 3;
+	else
+		return 8 * 3;
+}
+
+static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
+{
+	/*
+	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
+	 * format of the number of bytes per pixel will be half the number
+	 * of bytes of RGB pixel.
+	 */
+	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		bpp /= 2;
+
+	return bpp;
+}
+
+static int
+intel_dp_mode_min_output_bpp(struct drm_connector *connector,
+			     const struct drm_display_mode *mode)
+{
+	enum intel_output_format output_format =
+		intel_dp_output_format(connector, mode);
+
+	return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
+}
+
 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 				  int hdisplay)
 {
@@ -671,7 +735,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	max_lanes = intel_dp_max_lane_count(intel_dp);
 
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
-	mode_rate = intel_dp_link_required(target_clock, 18);
+	mode_rate = intel_dp_link_required(target_clock,
+					   intel_dp_mode_min_output_bpp(connector, mode));
 
 	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 		return MODE_H_ILLEGAL;
@@ -1143,41 +1208,6 @@ _pp_stat_reg(struct intel_dp *intel_dp)
 	return regs.pp_stat;
 }
 
-/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
-   This function only applicable when panel PM state is not to be tracked */
-static int edp_notify_handler(struct notifier_block *this, unsigned long code,
-			      void *unused)
-{
-	struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
-						 edp_notifier);
-	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	intel_wakeref_t wakeref;
-
-	if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
-		return 0;
-
-	with_pps_lock(intel_dp, wakeref) {
-		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-			enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
-			i915_reg_t pp_ctrl_reg, pp_div_reg;
-			u32 pp_div;
-
-			pp_ctrl_reg = PP_CONTROL(pipe);
-			pp_div_reg  = PP_DIVISOR(pipe);
-			pp_div = intel_de_read(dev_priv, pp_div_reg);
-			pp_div &= PP_REFERENCE_DIVIDER_MASK;
-
-			/* 0x1F write to PP_DIV_REG sets max cycle delay */
-			intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F);
-			intel_de_write(dev_priv, pp_ctrl_reg,
-				       PANEL_UNLOCK_REGS);
-			msleep(intel_dp->panel_power_cycle_delay);
-		}
-	}
-
-	return 0;
-}
-
 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1744,7 +1774,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
 	case AUX_CH_D:
 	case AUX_CH_E:
 	case AUX_CH_F:
-	case AUX_CH_G:
 		return DP_AUX_CH_CTL(aux_ch);
 	default:
 		MISSING_CASE(aux_ch);
@@ -1765,7 +1794,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
 	case AUX_CH_D:
 	case AUX_CH_E:
 	case AUX_CH_F:
-	case AUX_CH_G:
+		return DP_AUX_CH_DATA(aux_ch, index);
+	default:
+		MISSING_CASE(aux_ch);
+		return DP_AUX_CH_DATA(AUX_CH_A, index);
+	}
+}
+
+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_C:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+	case AUX_CH_USBC5:
+	case AUX_CH_USBC6:
+		return DP_AUX_CH_CTL(aux_ch);
+	default:
+		MISSING_CASE(aux_ch);
+		return DP_AUX_CH_CTL(AUX_CH_A);
+	}
+}
+
+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_C:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+	case AUX_CH_USBC5:
+	case AUX_CH_USBC6:
 		return DP_AUX_CH_DATA(aux_ch, index);
 	default:
 		MISSING_CASE(aux_ch);
@@ -1785,8 +1859,12 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct intel_encoder *encoder = &dig_port->base;
+	enum aux_ch aux_ch = dig_port->aux_ch;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (INTEL_GEN(dev_priv) >= 12) {
+		intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
+		intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
+	} else if (INTEL_GEN(dev_priv) >= 9) {
 		intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
 		intel_dp->aux_ch_data_reg = skl_aux_data_reg;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
@@ -1814,9 +1892,15 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
 	drm_dp_aux_init(&intel_dp->aux);
 
 	/* Failure to allocate our preferred name is not critical */
-	intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
-				       aux_ch_name(dig_port->aux_ch),
-				       port_name(encoder->port));
+	if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+		intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
+					       aux_ch - AUX_CH_USBC1 + '1',
+					       encoder->base.name);
+	else
+		intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
+					       aux_ch_name(aux_ch),
+					       encoder->base.name);
+
 	intel_dp->aux.transfer = intel_dp_aux_transfer;
 }
 
@@ -2095,19 +2179,6 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 	}
 }
 
-static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
-{
-	/*
-	 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
-	 * format of the number of bytes per pixel will be half the number
-	 * of bytes of RGB pixel.
-	 */
-	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
-		bpp /= 2;
-
-	return bpp;
-}
-
 /* Optimize link config in order: max bpp, min clock, min lanes */
 static int
 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
@@ -2119,7 +2190,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 	int mode_rate, link_clock, link_avail;
 
 	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
-		int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
+		int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
 
 		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 						   output_bpp);
@@ -2330,14 +2401,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	return 0;
 }
 
-int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
-{
-	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
-		return 6 * 3;
-	else
-		return 8 * 3;
-}
-
 static int
 intel_dp_compute_link_config(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config,
@@ -2363,7 +2426,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	limits.min_lane_count = 1;
 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
 
-	limits.min_bpp = intel_dp_min_bpp(pipe_config);
+	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
 	limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
 
 	if (intel_dp_is_edp(intel_dp)) {
@@ -2429,32 +2492,6 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	return 0;
 }
 
-static int
-intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
-			 struct intel_crtc_state *crtc_state,
-			 const struct drm_connector_state *conn_state)
-{
-	struct drm_connector *connector = conn_state->connector;
-	const struct drm_display_info *info = &connector->display_info;
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
-
-	if (!connector->ycbcr_420_allowed)
-		return 0;
-
-	if (!drm_mode_is_420_only(info, adjusted_mode))
-		return 0;
-
-	if (intel_dp->dfp.ycbcr_444_to_420) {
-		crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
-		return 0;
-	}
-
-	crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
-
-	return intel_pch_panel_fitting(crtc_state, conn_state);
-}
-
 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state)
 {
@@ -2693,7 +2730,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-	struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
 	enum port port = encoder->port;
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	struct intel_digital_connector_state *intel_conn_state =
@@ -2705,15 +2741,14 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
 		pipe_config->has_pch_encoder = true;
 
-	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
+	pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
+							    adjusted_mode);
 
-	if (lspcon->active)
-		lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
-	else
-		ret = intel_dp_ycbcr420_config(intel_dp, pipe_config,
-					       conn_state);
-	if (ret)
-		return ret;
+	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+		ret = intel_pch_panel_fitting(pipe_config, conn_state);
+		if (ret)
+			return ret;
+	}
 
 	if (!intel_dp_port_has_audio(dev_priv, port))
 		pipe_config->has_audio = false;
@@ -2757,7 +2792,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (pipe_config->dsc.compression_enable)
 		output_bpp = pipe_config->dsc.compressed_bpp;
 	else
-		output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
+		output_bpp = intel_dp_output_bpp(pipe_config->output_format,
+						 pipe_config->pipe_bpp);
 
 	intel_link_compute_m_n(output_bpp,
 			       pipe_config->lane_count,
@@ -2779,13 +2815,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 }
 
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
-			      int link_rate, u8 lane_count,
-			      bool link_mst)
+			      int link_rate, int lane_count)
 {
 	intel_dp->link_trained = false;
 	intel_dp->link_rate = link_rate;
 	intel_dp->lane_count = lane_count;
-	intel_dp->link_mst = link_mst;
 }
 
 static void intel_dp_prepare(struct intel_encoder *encoder,
@@ -2797,10 +2831,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 
-	intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
-				 pipe_config->lane_count,
-				 intel_crtc_has_type(pipe_config,
-						     INTEL_OUTPUT_DP_MST));
+	intel_dp_set_link_params(intel_dp,
+				 pipe_config->port_clock,
+				 pipe_config->lane_count);
 
 	/*
 	 * There are four kinds of DP registers:
@@ -3492,32 +3525,33 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
 			    enable ? "enable" : "disable");
 }
 
-/* If the sink supports it, try to set the power state appropriately */
-void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
+/* If the device supports it, try to set the power state appropriately */
+void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
 {
-	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	int ret, i;
 
 	/* Should have a valid DPCD by this point */
 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
 		return;
 
-	if (mode != DRM_MODE_DPMS_ON) {
+	if (mode != DP_SET_POWER_D0) {
 		if (downstream_hpd_needs_d0(intel_dp))
 			return;
 
-		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
-					 DP_SET_POWER_D3);
+		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
 	} else {
 		struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
 
+		lspcon_resume(dp_to_dig_port(intel_dp));
+
 		/*
 		 * When turning on, we need to retry for 1ms to give the sink
 		 * time to wake up.
 		 */
 		for (i = 0; i < 3; i++) {
-			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
-						 DP_SET_POWER_D0);
+			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
 			if (ret == 1)
 				break;
 			msleep(1);
@@ -3528,8 +3562,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 	}
 
 	if (ret != 1)
-		drm_dbg_kms(&i915->drm, "failed to %s sink power state\n",
-			    mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
+		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
+			    encoder->base.base.id, encoder->base.name,
+			    mode == DP_SET_POWER_D0 ? "D0" : "D3");
 }
 
 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
@@ -3686,6 +3721,66 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 	}
 }
 
+static bool
+intel_dp_get_dpcd(struct intel_dp *intel_dp);
+
+/**
+ * intel_dp_sync_state - sync the encoder state during init/resume
+ * @encoder: intel encoder to sync
+ * @crtc_state: state for the CRTC connected to the encoder
+ *
+ * Sync any state stored in the encoder wrt. HW state during driver init
+ * and system resume.
+ */
+void intel_dp_sync_state(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+	/*
+	 * Don't clobber DPCD if it's been already read out during output
+	 * setup (eDP) or detect.
+	 */
+	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
+		intel_dp_get_dpcd(intel_dp);
+
+	intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
+	intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
+}
+
+bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
+				    struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+	/*
+	 * If BIOS has set an unsupported or non-standard link rate for some
+	 * reason force an encoder recompute and full modeset.
+	 */
+	if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
+				crtc_state->port_clock) < 0) {
+		drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
+		crtc_state->uapi.connectors_changed = true;
+		return false;
+	}
+
+	/*
+	 * FIXME hack to force full modeset when DSC is being used.
+	 *
+	 * As long as we do not have full state readout and config comparison
+	 * of crtc_state->dsc, we have no way to ensure reliable fastset.
+	 * Remove once we have readout for DSC.
+	 */
+	if (crtc_state->dsc.compression_enable) {
+		drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
+		crtc_state->uapi.mode_changed = true;
+		return false;
+	}
+
+	return true;
+}
+
 static void intel_disable_dp(struct intel_atomic_state *state,
 			     struct intel_encoder *encoder,
 			     const struct intel_crtc_state *old_crtc_state,
@@ -3703,7 +3798,7 @@ static void intel_disable_dp(struct intel_atomic_state *state,
 	 * ensure that we have vdd while we switch off the panel. */
 	intel_edp_panel_vdd_on(intel_dp);
 	intel_edp_backlight_off(old_conn_state);
-	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
+	intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
 	intel_edp_panel_off(intel_dp);
 }
 
@@ -3771,6 +3866,7 @@ static void chv_post_disable_dp(struct intel_atomic_state *state,
 
 static void
 cpt_set_link_train(struct intel_dp *intel_dp,
+		   const struct intel_crtc_state *crtc_state,
 		   u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -3778,7 +3874,7 @@ cpt_set_link_train(struct intel_dp *intel_dp,
 
 	*DP &= ~DP_LINK_TRAIN_MASK_CPT;
 
-	switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
+	switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
 	case DP_TRAINING_PATTERN_DISABLE:
 		*DP |= DP_LINK_TRAIN_OFF_CPT;
 		break;
@@ -3801,6 +3897,7 @@ cpt_set_link_train(struct intel_dp *intel_dp,
 
 static void
 g4x_set_link_train(struct intel_dp *intel_dp,
+		   const struct intel_crtc_state *crtc_state,
 		   u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -3808,7 +3905,7 @@ g4x_set_link_train(struct intel_dp *intel_dp,
 
 	*DP &= ~DP_LINK_TRAIN_MASK;
 
-	switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
+	switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
 	case DP_TRAINING_PATTERN_DISABLE:
 		*DP |= DP_LINK_TRAIN_OFF;
 		break;
@@ -3830,13 +3927,14 @@ g4x_set_link_train(struct intel_dp *intel_dp,
 }
 
 static void intel_dp_enable_port(struct intel_dp *intel_dp,
-				 const struct intel_crtc_state *old_crtc_state)
+				 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
 	/* enable with pattern 1 (as per spec) */
 
-	intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
+	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
+					       DP_TRAINING_PATTERN_1);
 
 	/*
 	 * Magic for VLV/CHV. We _must_ first set up the register
@@ -3845,7 +3943,7 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
 	 * fail when the power sequencer is freshly used for this port.
 	 */
 	intel_dp->DP |= DP_PORT_EN;
-	if (old_crtc_state->has_audio)
+	if (crtc_state->has_audio)
 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 
 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
@@ -3925,10 +4023,10 @@ static void intel_enable_dp(struct intel_atomic_state *state,
 				    lane_mask);
 	}
 
-	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+	intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
 	intel_dp_configure_protocol_converter(intel_dp);
-	intel_dp_start_link_train(intel_dp);
-	intel_dp_stop_link_train(intel_dp);
+	intel_dp_start_link_train(intel_dp, pipe_config);
+	intel_dp_stop_link_train(intel_dp, pipe_config);
 
 	if (pipe_config->has_audio) {
 		drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
@@ -4126,38 +4224,30 @@ static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
 	chv_phy_post_pll_disable(encoder, old_crtc_state);
 }
 
-/*
- * Fetch AUX CH registers 0x202 - 0x207 which contain
- * link status information
- */
-bool
-intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
-{
-	return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
-				DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
-}
-
-static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp)
+static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
 {
 	return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 }
 
-static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp)
+static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
 {
 	return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 }
 
-static u8 intel_dp_pre_empemph_max_2(struct intel_dp *intel_dp)
+static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
 {
 	return DP_TRAIN_PRE_EMPH_LEVEL_2;
 }
 
-static u8 intel_dp_pre_empemph_max_3(struct intel_dp *intel_dp)
+static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
 {
 	return DP_TRAIN_PRE_EMPH_LEVEL_3;
 }
 
-static void vlv_set_signal_levels(struct intel_dp *intel_dp)
+static void vlv_set_signal_levels(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	unsigned long demph_reg_value, preemph_reg_value,
@@ -4237,11 +4327,13 @@ static void vlv_set_signal_levels(struct intel_dp *intel_dp)
 		return;
 	}
 
-	vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
+	vlv_set_phy_signal_level(encoder, crtc_state,
+				 demph_reg_value, preemph_reg_value,
 				 uniqtranscale_reg_value, 0);
 }
 
-static void chv_set_signal_levels(struct intel_dp *intel_dp)
+static void chv_set_signal_levels(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 	u32 deemph_reg_value, margin_reg_value;
@@ -4318,8 +4410,9 @@ static void chv_set_signal_levels(struct intel_dp *intel_dp)
 		return;
 	}
 
-	chv_set_phy_signal_level(encoder, deemph_reg_value,
-				 margin_reg_value, uniq_trans_scale);
+	chv_set_phy_signal_level(encoder, crtc_state,
+				 deemph_reg_value, margin_reg_value,
+				 uniq_trans_scale);
 }
 
 static u32 g4x_signal_levels(u8 train_set)
@@ -4360,7 +4453,8 @@ static u32 g4x_signal_levels(u8 train_set)
 }
 
 static void
-g4x_set_signal_levels(struct intel_dp *intel_dp)
+g4x_set_signal_levels(struct intel_dp *intel_dp,
+		      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4407,7 +4501,8 @@ static u32 snb_cpu_edp_signal_levels(u8 train_set)
 }
 
 static void
-snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
+snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4458,7 +4553,8 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set)
 }
 
 static void
-ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
+ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4476,7 +4572,8 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp)
 	intel_de_posting_read(dev_priv, intel_dp->output_reg);
 }
 
-void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
+void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
+				const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 train_set = intel_dp->train_set[0];
@@ -4490,28 +4587,23 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
 		    " (max)" : "");
 
-	intel_dp->set_signal_levels(intel_dp);
+	intel_dp->set_signal_levels(intel_dp, crtc_state);
 }
 
 void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
+				       const struct intel_crtc_state *crtc_state,
 				       u8 dp_train_pat)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
 
-	if (dp_train_pat & train_pat_mask)
+	if ((intel_dp_training_pattern_symbol(dp_train_pat)) !=
+	    DP_TRAINING_PATTERN_DISABLE)
 		drm_dbg_kms(&dev_priv->drm,
 			    "Using DP training pattern TPS%d\n",
-			    dp_train_pat & train_pat_mask);
+			    intel_dp_training_pattern_symbol(dp_train_pat));
 
-	intel_dp->set_link_train(intel_dp, dp_train_pat);
-}
-
-void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
-{
-	if (intel_dp->set_idle_link_train)
-		intel_dp->set_idle_link_train(intel_dp);
+	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
 }
 
 static void
@@ -4732,6 +4824,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 {
 	int ret;
 
+	intel_dp_lttpr_init(intel_dp);
+
 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd))
 		return false;
 
@@ -5404,33 +5498,14 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
 	return test_result;
 }
 
-static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp)
-{
-	struct drm_dp_phy_test_params *data =
-		&intel_dp->compliance.test_data.phytest;
-
-	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
-		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
-		return DP_TEST_NAK;
-	}
-
-	/*
-	 * link_mst is set to false to avoid executing mst related code
-	 * during compliance testing.
-	 */
-	intel_dp->link_mst = false;
-
-	return DP_TEST_ACK;
-}
-
-static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
+static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
+					const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv =
 			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_dp_phy_test_params *data =
 			&intel_dp->compliance.test_data.phytest;
-	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum pipe pipe = crtc->pipe;
 	u32 pattern_val;
 
@@ -5490,7 +5565,8 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
 }
 
 static void
-intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
+intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
+				  const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -5516,7 +5592,8 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
 }
 
 static void
-intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
+intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
+				 const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -5542,27 +5619,30 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
 		       trans_ddi_func_ctl_value);
 }
 
-void intel_dp_process_phy_request(struct intel_dp *intel_dp)
+static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
+					 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_dp_phy_test_params *data =
 		&intel_dp->compliance.test_data.phytest;
 	u8 link_status[DP_LINK_STATUS_SIZE];
 
-	if (!intel_dp_get_link_status(intel_dp, link_status)) {
+	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
+					     link_status) < 0) {
 		DRM_DEBUG_KMS("failed to get link status\n");
 		return;
 	}
 
 	/* retrieve vswing & pre-emphasis setting */
-	intel_dp_get_adjust_train(intel_dp, link_status);
+	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
+				  link_status);
 
-	intel_dp_autotest_phy_ddi_disable(intel_dp);
+	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
 
-	intel_dp_set_signal_levels(intel_dp);
+	intel_dp_set_signal_levels(intel_dp, crtc_state);
 
-	intel_dp_phy_pattern_update(intel_dp);
+	intel_dp_phy_pattern_update(intel_dp, crtc_state);
 
-	intel_dp_autotest_phy_ddi_enable(intel_dp, data->num_lanes);
+	intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
 
 	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
 				    link_status[DP_DPCD_REV]);
@@ -5570,15 +5650,18 @@ void intel_dp_process_phy_request(struct intel_dp *intel_dp)
 
 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
 {
-	u8 test_result;
+	struct drm_dp_phy_test_params *data =
+		&intel_dp->compliance.test_data.phytest;
 
-	test_result = intel_dp_prepare_phytest(intel_dp);
-	if (test_result != DP_TEST_ACK)
-		DRM_ERROR("Phy test preparation failed\n");
+	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
+		DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
+		return DP_TEST_NAK;
+	}
 
-	intel_dp_process_phy_request(intel_dp);
+	/* Set test active flag here so userspace doesn't interrupt things */
+	intel_dp->compliance.test_active = true;
 
-	return test_result;
+	return DP_TEST_ACK;
 }
 
 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
@@ -5709,12 +5792,17 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
 	if (intel_psr_enabled(intel_dp))
 		return false;
 
-	if (!intel_dp_get_link_status(intel_dp, link_status))
+	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
+					     link_status) < 0)
 		return false;
 
 	/*
 	 * Validate the cached values of intel_dp->link_rate and
 	 * intel_dp->lane_count before attempting to retrain.
+	 *
+	 * FIXME would be nice to user the crtc state here, but since
+	 * we need to call this from the short HPD handler that seems
+	 * a bit hard.
 	 */
 	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
 					intel_dp->lane_count))
@@ -5848,8 +5936,20 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
 							      intel_crtc_pch_transcoder(crtc), false);
 	}
 
-	intel_dp_start_link_train(intel_dp);
-	intel_dp_stop_link_train(intel_dp);
+	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
+		const struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+
+		/* retrain on the MST master transcoder */
+		if (INTEL_GEN(dev_priv) >= 12 &&
+		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
+		    !intel_dp_mst_is_master_trans(crtc_state))
+			continue;
+
+		intel_dp_start_link_train(intel_dp, crtc_state);
+		intel_dp_stop_link_train(intel_dp, crtc_state);
+		break;
+	}
 
 	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
 		const struct intel_crtc_state *crtc_state =
@@ -5867,6 +5967,118 @@ int intel_dp_retrain_link(struct intel_encoder *encoder,
 	return 0;
 }
 
+static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
+				  struct drm_modeset_acquire_ctx *ctx,
+				  u32 *crtc_mask)
+{
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct drm_connector_list_iter conn_iter;
+	struct intel_connector *connector;
+	int ret = 0;
+
+	*crtc_mask = 0;
+
+	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+	for_each_intel_connector_iter(connector, &conn_iter) {
+		struct drm_connector_state *conn_state =
+			connector->base.state;
+		struct intel_crtc_state *crtc_state;
+		struct intel_crtc *crtc;
+
+		if (!intel_dp_has_connector(intel_dp, conn_state))
+			continue;
+
+		crtc = to_intel_crtc(conn_state->crtc);
+		if (!crtc)
+			continue;
+
+		ret = drm_modeset_lock(&crtc->base.mutex, ctx);
+		if (ret)
+			break;
+
+		crtc_state = to_intel_crtc_state(crtc->base.state);
+
+		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
+
+		if (!crtc_state->hw.active)
+			continue;
+
+		if (conn_state->commit &&
+		    !try_wait_for_completion(&conn_state->commit->hw_done))
+			continue;
+
+		*crtc_mask |= drm_crtc_mask(&crtc->base);
+	}
+	drm_connector_list_iter_end(&conn_iter);
+
+	return ret;
+}
+
+static int intel_dp_do_phy_test(struct intel_encoder *encoder,
+				struct drm_modeset_acquire_ctx *ctx)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct intel_crtc *crtc;
+	u32 crtc_mask;
+	int ret;
+
+	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
+			       ctx);
+	if (ret)
+		return ret;
+
+	ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
+	if (ret)
+		return ret;
+
+	if (crtc_mask == 0)
+		return 0;
+
+	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
+		    encoder->base.base.id, encoder->base.name);
+
+	for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
+		const struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+
+		/* test on the MST master transcoder */
+		if (INTEL_GEN(dev_priv) >= 12 &&
+		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
+		    !intel_dp_mst_is_master_trans(crtc_state))
+			continue;
+
+		intel_dp_process_phy_request(intel_dp, crtc_state);
+		break;
+	}
+
+	return 0;
+}
+
+static void intel_dp_phy_test(struct intel_encoder *encoder)
+{
+	struct drm_modeset_acquire_ctx ctx;
+	int ret;
+
+	drm_modeset_acquire_init(&ctx, 0);
+
+	for (;;) {
+		ret = intel_dp_do_phy_test(encoder, &ctx);
+
+		if (ret == -EDEADLK) {
+			drm_modeset_backoff(&ctx);
+			continue;
+		}
+
+		break;
+	}
+
+	drm_modeset_drop_locks(&ctx);
+	drm_modeset_acquire_fini(&ctx);
+	drm_WARN(encoder->base.dev, ret,
+		 "Acquiring modeset locks failed with %i\n", ret);
+}
+
 /*
  * If display is now connected check links status,
  * there has been known issues of link loss triggering
@@ -5883,10 +6095,18 @@ static enum intel_hotplug_state
 intel_dp_hotplug(struct intel_encoder *encoder,
 		 struct intel_connector *connector)
 {
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct drm_modeset_acquire_ctx ctx;
 	enum intel_hotplug_state state;
 	int ret;
 
+	if (intel_dp->compliance.test_active &&
+	    intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
+		intel_dp_phy_test(encoder);
+		/* just do the PHY test and nothing else */
+		return INTEL_HOTPLUG_UNCHANGED;
+	}
+
 	state = intel_encoder_hotplug(encoder, connector);
 
 	drm_modeset_acquire_init(&ctx, 0);
@@ -5991,11 +6211,23 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
 
 	intel_psr_short_pulse(intel_dp);
 
-	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
+	switch (intel_dp->compliance.test_type) {
+	case DP_TEST_LINK_TRAINING:
 		drm_dbg_kms(&dev_priv->drm,
 			    "Link Training Compliance Test requested\n");
 		/* Send a Hotplug Uevent to userspace to start modeset */
 		drm_kms_helper_hotplug_event(&dev_priv->drm);
+		break;
+	case DP_TEST_LINK_PHY_TEST_PATTERN:
+		drm_dbg_kms(&dev_priv->drm,
+			    "PHY test pattern Compliance Test requested\n");
+		/*
+		 * Schedule long hpd to do the test
+		 *
+		 * FIXME get rid of the ad-hoc phy test modeset code
+		 * and properly incorporate it into the normal modeset.
+		 */
+		return false;
 	}
 
 	return true;
@@ -6006,15 +6238,14 @@ static enum drm_connector_status
 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-	struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	u8 *dpcd = intel_dp->dpcd;
 	u8 type;
 
 	if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
 		return connector_status_connected;
 
-	if (lspcon->active)
-		lspcon_resume(lspcon);
+	lspcon_resume(dig_port);
 
 	if (!intel_dp_get_dpcd(intel_dp))
 		return connector_status_disconnected;
@@ -6220,7 +6451,9 @@ intel_dp_update_420(struct intel_dp *intel_dp)
 	ycbcr_420_passthrough =
 		drm_dp_downstream_420_passthrough(intel_dp->dpcd,
 						  intel_dp->downstream_ports);
+	/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
 	ycbcr_444_to_420 =
+		dp_to_dig_port(intel_dp)->lspcon.active ||
 		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
 							intel_dp->downstream_ports);
 
@@ -6523,11 +6756,6 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
 		 */
 		with_pps_lock(intel_dp, wakeref)
 			edp_panel_vdd_off_sync(intel_dp);
-
-		if (intel_dp->edp_notifier.notifier_call) {
-			unregister_reboot_notifier(&intel_dp->edp_notifier);
-			intel_dp->edp_notifier.notifier_call = NULL;
-		}
 	}
 
 	intel_dp_aux_fini(intel_dp);
@@ -6558,6 +6786,18 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
 		edp_panel_vdd_off_sync(intel_dp);
 }
 
+void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
+	intel_wakeref_t wakeref;
+
+	if (!intel_dp_is_edp(intel_dp))
+		return;
+
+	with_pps_lock(intel_dp, wakeref)
+		wait_panel_power_cycle(intel_dp);
+}
+
 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -6598,15 +6838,11 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
-	struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
 	intel_wakeref_t wakeref;
 
 	if (!HAS_DDI(dev_priv))
 		intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
 
-	if (lspcon->active)
-		lspcon_resume(lspcon);
-
 	intel_dp->reset_link_params = true;
 
 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
@@ -7671,9 +7907,6 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	mutex_unlock(&dev->mode_config.mutex);
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
-		register_reboot_notifier(&intel_dp->edp_notifier);
-
 		/*
 		 * Figure out the current pipe for the initial backlight setup.
 		 * If the current pipe isn't valid, try the PPS pipe, and if that
@@ -7892,8 +8125,11 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
 	intel_encoder->compute_config = intel_dp_compute_config;
 	intel_encoder->get_hw_state = intel_dp_get_hw_state;
 	intel_encoder->get_config = intel_dp_get_config;
+	intel_encoder->sync_state = intel_dp_sync_state;
+	intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
 	intel_encoder->update_pipe = intel_panel_update_backlight;
 	intel_encoder->suspend = intel_dp_encoder_suspend;
+	intel_encoder->shutdown = intel_dp_encoder_shutdown;
 	if (IS_CHERRYVIEW(dev_priv)) {
 		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
 		intel_encoder->pre_enable = chv_pre_enable_dp;
@@ -7933,17 +8169,15 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
 
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
 	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
-		dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3;
+		dig_port->dp.preemph_max = intel_dp_preemph_max_3;
 		dig_port->dp.voltage_max = intel_dp_voltage_max_3;
 	} else {
-		dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2;
+		dig_port->dp.preemph_max = intel_dp_preemph_max_2;
 		dig_port->dp.voltage_max = intel_dp_voltage_max_2;
 	}
 
 	dig_port->dp.output_reg = output_reg;
 	dig_port->max_lanes = 4;
-	dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
-	dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
 
 	intel_encoder->type = INTEL_OUTPUT_DP;
 	intel_encoder->power_domain = intel_port_to_power_domain(port);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 08a1c0aa8b94..3f862b4fd34f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -10,6 +10,7 @@
 
 #include "i915_reg.h"
 
+enum intel_output_format;
 enum pipe;
 enum port;
 struct drm_connector_state;
@@ -35,7 +36,7 @@ void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 				       struct link_config_limits *limits);
 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state);
-int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
+int intel_dp_min_bpp(enum intel_output_format output_format);
 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
 			   i915_reg_t dp_reg, enum port port,
 			   enum pipe *pipe);
@@ -44,19 +45,19 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
 bool intel_dp_init_connector(struct intel_digital_port *dig_port,
 			     struct intel_connector *intel_connector);
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
-			      int link_rate, u8 lane_count,
-			      bool link_mst);
+			      int link_rate, int lane_count);
 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 					    int link_rate, u8 lane_count);
 int intel_dp_retrain_link(struct intel_encoder *encoder,
 			  struct drm_modeset_acquire_ctx *ctx);
-void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp);
 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
 					   const struct intel_crtc_state *crtc_state,
 					   bool enable);
 void intel_dp_encoder_reset(struct drm_encoder *encoder);
 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
+void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);
 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
 int intel_dp_compute_config(struct intel_encoder *encoder,
 			    struct intel_crtc_state *pipe_config,
@@ -92,16 +93,15 @@ void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
 
 void
 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
+				       const struct intel_crtc_state *crtc_state,
 				       u8 dp_train_pat);
 void
-intel_dp_set_signal_levels(struct intel_dp *intel_dp);
-void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
+intel_dp_set_signal_levels(struct intel_dp *intel_dp,
+			   const struct intel_crtc_state *crtc_state);
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 			   u8 *link_bw, u8 *rate_select);
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
-bool
-intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
 
 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
 int intel_dp_link_required(int pixel_clock, int bpp);
@@ -122,7 +122,6 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,
 		       struct intel_crtc_state *crtc_state,
 		       unsigned int type);
 bool intel_digital_port_connected(struct intel_encoder *encoder);
-void intel_dp_process_phy_request(struct intel_dp *intel_dp);
 
 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
 {
@@ -139,4 +138,9 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
 int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
 		       struct intel_connector *intel_connector);
 
+bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
+				    struct intel_crtc_state *crtc_state);
+void intel_dp_sync_state(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 036f504ac7db..51d27fc98d48 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -343,8 +343,7 @@ intel_dp_aux_display_control_capable(struct intel_connector *connector)
 	 * the panel can support backlight control over the aux channel
 	 */
 	if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
-	    (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
-	    !(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
+	    (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
 		drm_dbg_kms(&i915->drm, "AUX Backlight Control Supported!\n");
 		return true;
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index f2c8b56be9ea..91d3979902d0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,6 +34,152 @@ intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
 		      link_status[3], link_status[4], link_status[5]);
 }
 
+static int intel_dp_lttpr_count(struct intel_dp *intel_dp)
+{
+	int count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+
+	/*
+	 * Pretend no LTTPRs in case of LTTPR detection error, or
+	 * if too many (>8) LTTPRs are detected. This translates to link
+	 * training in transparent mode.
+	 */
+	return count <= 0 ? 0 : count;
+}
+
+static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
+{
+	intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
+				    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
+}
+
+static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy,
+				     char *buf, size_t buf_size)
+{
+	if (dp_phy == DP_PHY_DPRX)
+		snprintf(buf, buf_size, "DPRX");
+	else
+		snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1);
+
+	return buf;
+}
+
+static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
+				   enum drm_dp_phy dp_phy)
+{
+	return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];
+}
+
+static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
+					 enum drm_dp_phy dp_phy)
+{
+	u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
+	char phy_name[10];
+
+	intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
+
+	if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
+		drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
+			    "failed to read the PHY caps for %s\n",
+			    phy_name);
+		return;
+	}
+
+	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
+		    "%s PHY capabilities: %*ph\n",
+		    phy_name,
+		    (int)sizeof(intel_dp->lttpr_phy_caps[0]),
+		    phy_caps);
+}
+
+static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
+{
+	if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
+					  intel_dp->lttpr_common_caps) < 0) {
+		memset(intel_dp->lttpr_common_caps, 0,
+		       sizeof(intel_dp->lttpr_common_caps));
+		return false;
+	}
+
+	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
+		    "LTTPR common capabilities: %*ph\n",
+		    (int)sizeof(intel_dp->lttpr_common_caps),
+		    intel_dp->lttpr_common_caps);
+
+	return true;
+}
+
+static bool
+intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
+{
+	u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
+			  DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
+
+	return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
+}
+
+/**
+ * intel_dp_lttpr_init - detect LTTPRs and init the LTTPR link training mode
+ * @intel_dp: Intel DP struct
+ *
+ * Read the LTTPR common capabilities, switch to non-transparent link training
+ * mode if any is detected and read the PHY capabilities for all detected
+ * LTTPRs. In case of an LTTPR detection error or if the number of
+ * LTTPRs is more than is supported (8), fall back to the no-LTTPR,
+ * transparent mode link training mode.
+ *
+ * Returns:
+ *   >0  if LTTPRs were detected and the non-transparent LT mode was set
+ *    0  if no LTTPRs or more than 8 LTTPRs were detected or in case of a
+ *       detection failure and the transparent LT mode was set
+ */
+int intel_dp_lttpr_init(struct intel_dp *intel_dp)
+{
+	int lttpr_count;
+	bool ret;
+	int i;
+
+	if (intel_dp_is_edp(intel_dp))
+		return 0;
+
+	ret = intel_dp_read_lttpr_common_caps(intel_dp);
+
+	/*
+	 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of
+	 * non-transparent mode and the disable->enable non-transparent mode
+	 * sequence.
+	 */
+	intel_dp_set_lttpr_transparent_mode(intel_dp, true);
+
+	if (!ret)
+		return 0;
+
+	lttpr_count = intel_dp_lttpr_count(intel_dp);
+
+	/*
+	 * In case of unsupported number of LTTPRs or failing to switch to
+	 * non-transparent mode fall-back to transparent link training mode,
+	 * still taking into account any LTTPR common lane- rate/count limits.
+	 */
+	if (lttpr_count == 0)
+		return 0;
+
+	if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
+		drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
+			    "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");
+
+		intel_dp_set_lttpr_transparent_mode(intel_dp, true);
+		intel_dp_reset_lttpr_count(intel_dp);
+
+		return 0;
+	}
+
+	for (i = 0; i < lttpr_count; i++)
+		intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
+
+	return lttpr_count;
+}
+EXPORT_SYMBOL(intel_dp_lttpr_init);
+
 static u8 dp_voltage_max(u8 preemph)
 {
 	switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
@@ -49,36 +195,109 @@ static u8 dp_voltage_max(u8 preemph)
 	}
 }
 
-void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
-			       const u8 link_status[DP_LINK_STATUS_SIZE])
+static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,
+				     enum drm_dp_phy dp_phy)
+{
+	const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
+
+	if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps))
+		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
+	else
+		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
+}
+
+static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,
+				     enum drm_dp_phy dp_phy)
+{
+	const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
+
+	if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps))
+		return DP_TRAIN_PRE_EMPH_LEVEL_3;
+	else
+		return DP_TRAIN_PRE_EMPH_LEVEL_2;
+}
+
+static bool
+intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,
+				     enum drm_dp_phy dp_phy)
+{
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	int lttpr_count = intel_dp_lttpr_count(intel_dp);
+
+	drm_WARN_ON_ONCE(&i915->drm, lttpr_count == 0 && dp_phy != DP_PHY_DPRX);
+
+	return lttpr_count == 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1);
+}
+
+static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,
+				   const struct intel_crtc_state *crtc_state,
+				   enum drm_dp_phy dp_phy)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	u8 voltage_max;
+
+	/*
+	 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from
+	 * the DPRX_PHY we train.
+	 */
+	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
+		voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
+	else
+		voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);
+
+	drm_WARN_ON_ONCE(&i915->drm,
+			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
+			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
+
+	return voltage_max;
+}
+
+static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
+				   enum drm_dp_phy dp_phy)
+{
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	u8 preemph_max;
+
+	/*
+	 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from
+	 * the DPRX_PHY we train.
+	 */
+	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
+		preemph_max = intel_dp->preemph_max(intel_dp);
+	else
+		preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);
+
+	drm_WARN_ON_ONCE(&i915->drm,
+			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
+			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
+
+	return preemph_max;
+}
+
+void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			  const struct intel_crtc_state *crtc_state,
+			  enum drm_dp_phy dp_phy,
+			  const u8 link_status[DP_LINK_STATUS_SIZE])
+{
 	u8 v = 0;
 	u8 p = 0;
 	int lane;
 	u8 voltage_max;
 	u8 preemph_max;
 
-	for (lane = 0; lane < intel_dp->lane_count; lane++) {
+	for (lane = 0; lane < crtc_state->lane_count; lane++) {
 		v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
 		p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
 	}
 
-	preemph_max = intel_dp->preemph_max(intel_dp);
-	drm_WARN_ON_ONCE(&i915->drm,
-			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
-			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
-
+	preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);
 	if (p >= preemph_max)
 		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 
 	v = min(v, dp_voltage_max(p));
 
-	voltage_max = intel_dp->voltage_max(intel_dp);
-	drm_WARN_ON_ONCE(&i915->drm,
-			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
-			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
-
+	voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);
 	if (v >= voltage_max)
 		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
 
@@ -86,59 +305,70 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 		intel_dp->train_set[lane] = v | p;
 }
 
+static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
+					     enum drm_dp_phy dp_phy)
+{
+	return dp_phy == DP_PHY_DPRX ?
+		DP_TRAINING_PATTERN_SET :
+		DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy);
+}
+
 static bool
 intel_dp_set_link_train(struct intel_dp *intel_dp,
+			const struct intel_crtc_state *crtc_state,
+			enum drm_dp_phy dp_phy,
 			u8 dp_train_pat)
 {
+	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
 	u8 buf[sizeof(intel_dp->train_set) + 1];
-	int ret, len;
+	int len;
 
-	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
+	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
+					       dp_train_pat);
 
 	buf[0] = dp_train_pat;
-	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
-	    DP_TRAINING_PATTERN_DISABLE) {
-		/* don't write DP_TRAINING_LANEx_SET on disable */
-		len = 1;
-	} else {
-		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
-		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
-		len = intel_dp->lane_count + 1;
-	}
-
-	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
-				buf, len);
+	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
+	memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
+	len = crtc_state->lane_count + 1;
 
-	return ret == len;
+	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
 }
 
 static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
-			u8 dp_train_pat)
+			  const struct intel_crtc_state *crtc_state,
+			  enum drm_dp_phy dp_phy,
+			  u8 dp_train_pat)
 {
 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
-	intel_dp_set_signal_levels(intel_dp);
-	return intel_dp_set_link_train(intel_dp, dp_train_pat);
+	intel_dp_set_signal_levels(intel_dp, crtc_state);
+	return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
 }
 
 static bool
-intel_dp_update_link_train(struct intel_dp *intel_dp)
+intel_dp_update_link_train(struct intel_dp *intel_dp,
+			   const struct intel_crtc_state *crtc_state,
+			   enum drm_dp_phy dp_phy)
 {
+	int reg = dp_phy == DP_PHY_DPRX ?
+			    DP_TRAINING_LANE0_SET :
+			    DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
 	int ret;
 
-	intel_dp_set_signal_levels(intel_dp);
+	intel_dp_set_signal_levels(intel_dp, crtc_state);
 
-	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
-				intel_dp->train_set, intel_dp->lane_count);
+	ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
+				intel_dp->train_set, crtc_state->lane_count);
 
-	return ret == intel_dp->lane_count;
+	return ret == crtc_state->lane_count;
 }
 
-static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
+static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
+					     const struct intel_crtc_state *crtc_state)
 {
 	int lane;
 
-	for (lane = 0; lane < intel_dp->lane_count; lane++)
+	for (lane = 0; lane < crtc_state->lane_count; lane++)
 		if ((intel_dp->train_set[lane] &
 		     DP_TRAIN_MAX_SWING_REACHED) == 0)
 			return false;
@@ -146,21 +376,22 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
 	return true;
 }
 
-/* Enable corresponding port and start training pattern 1 */
+/*
+ * Prepare link training by configuring the link parameters. On DDI platforms
+ * also enable the port here.
+ */
 static bool
-intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
+intel_dp_prepare_link_train(struct intel_dp *intel_dp,
+			    const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-	u8 voltage;
-	int voltage_tries, cr_tries, max_cr_tries;
-	bool max_vswing_reached = false;
 	u8 link_config[2];
 	u8 link_bw, rate_select;
 
 	if (intel_dp->prepare_link_retrain)
-		intel_dp->prepare_link_retrain(intel_dp);
+		intel_dp->prepare_link_retrain(intel_dp, crtc_state);
 
-	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
+	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
 			      &link_bw, &rate_select);
 
 	if (link_bw)
@@ -172,7 +403,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 
 	/* Write the link configuration data */
 	link_config[0] = link_bw;
-	link_config[1] = intel_dp->lane_count;
+	link_config[1] = crtc_state->lane_count;
 	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
@@ -188,8 +419,34 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 
 	intel_dp->DP |= DP_PORT_EN;
 
+	return true;
+}
+
+static void intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_dp,
+							enum drm_dp_phy dp_phy)
+{
+	if (dp_phy == DP_PHY_DPRX)
+		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
+	else
+		drm_dp_lttpr_link_train_clock_recovery_delay();
+}
+
+/*
+ * Perform the link training clock recovery phase on the given DP PHY using
+ * training pattern 1.
+ */
+static bool
+intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
+				      const struct intel_crtc_state *crtc_state,
+				      enum drm_dp_phy dp_phy)
+{
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	u8 voltage;
+	int voltage_tries, cr_tries, max_cr_tries;
+	bool max_vswing_reached = false;
+
 	/* clock recovery */
-	if (!intel_dp_reset_link_train(intel_dp,
+	if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
 				       DP_TRAINING_PATTERN_1 |
 				       DP_LINK_SCRAMBLING_DISABLE)) {
 		drm_err(&i915->drm, "failed to enable link training\n");
@@ -213,14 +470,15 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
 		u8 link_status[DP_LINK_STATUS_SIZE];
 
-		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
+		intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy);
 
-		if (!intel_dp_get_link_status(intel_dp, link_status)) {
+		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
+						     link_status) < 0) {
 			drm_err(&i915->drm, "failed to get link status\n");
 			return false;
 		}
 
-		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
+		if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
 			drm_dbg_kms(&i915->drm, "clock recovery OK\n");
 			return true;
 		}
@@ -239,8 +497,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 
 		/* Update training set as requested by target */
-		intel_dp_get_adjust_train(intel_dp, link_status);
-		if (!intel_dp_update_link_train(intel_dp)) {
+		intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
+					  link_status);
+		if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
 			drm_err(&i915->drm,
 				"failed to update link training\n");
 			return false;
@@ -252,7 +511,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 		else
 			voltage_tries = 1;
 
-		if (intel_dp_link_max_vswing_reached(intel_dp))
+		if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
 			max_vswing_reached = true;
 
 	}
@@ -266,7 +525,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
  * or for 1.4 devices that support it, training Pattern 3 for HBR2
  * or 1.2 devices that support it, Training Pattern 2 otherwise.
  */
-static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
+static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state,
+				     enum drm_dp_phy dp_phy)
 {
 	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 
@@ -275,12 +536,14 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 	 * for all downstream devices that support HBR3. There are no known eDP
 	 * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
 	 * specification.
+	 * LTTPRs must support TPS4.
 	 */
 	source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
-	sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
+	sink_tps4 = dp_phy != DP_PHY_DPRX ||
+		    drm_dp_tps4_supported(intel_dp->dpcd);
 	if (source_tps4 && sink_tps4) {
 		return DP_TRAINING_PATTERN_4;
-	} else if (intel_dp->link_rate == 810000) {
+	} else if (crtc_state->port_clock == 810000) {
 		if (!source_tps4)
 			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 				    "8.1 Gbps link rate without source HBR3/TPS4 support\n");
@@ -294,10 +557,11 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 	 * all sinks follow the spec.
 	 */
 	source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
-	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
+	sink_tps3 = dp_phy != DP_PHY_DPRX ||
+		    drm_dp_tps3_supported(intel_dp->dpcd);
 	if (source_tps3 && sink_tps3) {
 		return  DP_TRAINING_PATTERN_3;
-	} else if (intel_dp->link_rate >= 540000) {
+	} else if (crtc_state->port_clock >= 540000) {
 		if (!source_tps3)
 			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 				    ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
@@ -309,8 +573,28 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 	return DP_TRAINING_PATTERN_2;
 }
 
+static void
+intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp,
+						  enum drm_dp_phy dp_phy)
+{
+	if (dp_phy == DP_PHY_DPRX) {
+		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
+	} else {
+		const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
+
+		drm_dp_lttpr_link_train_channel_eq_delay(phy_caps);
+	}
+}
+
+/*
+ * Perform the link training channel equalization phase on the given DP PHY
+ * using one of training pattern 2, 3 or 4 depending on the source and
+ * sink capabilities.
+ */
 static bool
-intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
+intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
+					    const struct intel_crtc_state *crtc_state,
+					    enum drm_dp_phy dp_phy)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 	int tries;
@@ -318,22 +602,23 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 	u8 link_status[DP_LINK_STATUS_SIZE];
 	bool channel_eq = false;
 
-	training_pattern = intel_dp_training_pattern(intel_dp);
+	training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
 	/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
 	if (training_pattern != DP_TRAINING_PATTERN_4)
 		training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
 
 	/* channel equalization */
-	if (!intel_dp_set_link_train(intel_dp,
+	if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
 				     training_pattern)) {
 		drm_err(&i915->drm, "failed to start channel equalization\n");
 		return false;
 	}
 
 	for (tries = 0; tries < 5; tries++) {
-
-		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
-		if (!intel_dp_get_link_status(intel_dp, link_status)) {
+		intel_dp_link_training_channel_equalization_delay(intel_dp,
+								  dp_phy);
+		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
+						     link_status) < 0) {
 			drm_err(&i915->drm,
 				"failed to get link status\n");
 			break;
@@ -341,7 +626,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 
 		/* Make sure clock is still ok */
 		if (!drm_dp_clock_recovery_ok(link_status,
-					      intel_dp->lane_count)) {
+					      crtc_state->lane_count)) {
 			intel_dp_dump_link_status(link_status);
 			drm_dbg_kms(&i915->drm,
 				    "Clock recovery check failed, cannot "
@@ -350,7 +635,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 		}
 
 		if (drm_dp_channel_eq_ok(link_status,
-					 intel_dp->lane_count)) {
+					 crtc_state->lane_count)) {
 			channel_eq = true;
 			drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
 				    "successful\n");
@@ -358,8 +643,9 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 		}
 
 		/* Update training set as requested by target */
-		intel_dp_get_adjust_train(intel_dp, link_status);
-		if (!intel_dp_update_link_train(intel_dp)) {
+		intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
+					  link_status);
+		if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
 			drm_err(&i915->drm,
 				"failed to update link training\n");
 			break;
@@ -373,54 +659,142 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 			    "Channel equalization failed 5 times\n");
 	}
 
-	intel_dp_set_idle_link_train(intel_dp);
-
 	return channel_eq;
+}
 
+static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
+						   enum drm_dp_phy dp_phy)
+{
+	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
+	u8 val = DP_TRAINING_PATTERN_DISABLE;
+
+	return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
 }
 
-void intel_dp_stop_link_train(struct intel_dp *intel_dp)
+/**
+ * intel_dp_stop_link_train - stop link training
+ * @intel_dp: DP struct
+ * @crtc_state: state for CRTC attached to the encoder
+ *
+ * Stop the link training of the @intel_dp port, disabling the test pattern
+ * symbol generation on the port and disabling the training pattern in
+ * the sink's DPCD.
+ *
+ * What symbols are output on the port after this point is
+ * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern
+ * with the pipe being disabled, on older platforms it's HW specific if/how an
+ * idle pattern is generated, as the pipe is already enabled here for those.
+ *
+ * This function must be called after intel_dp_start_link_train().
+ */
+void intel_dp_stop_link_train(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state)
 {
 	intel_dp->link_trained = true;
 
-	intel_dp_set_link_train(intel_dp,
-				DP_TRAINING_PATTERN_DISABLE);
+	intel_dp_program_link_training_pattern(intel_dp,
+					       crtc_state,
+					       DP_TRAINING_PATTERN_DISABLE);
+	intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
 }
 
-void
-intel_dp_start_link_train(struct intel_dp *intel_dp)
+static bool
+intel_dp_link_train_phy(struct intel_dp *intel_dp,
+			const struct intel_crtc_state *crtc_state,
+			enum drm_dp_phy dp_phy)
 {
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
+	char phy_name[10];
+	bool ret = false;
 
-	if (!intel_dp_link_training_clock_recovery(intel_dp))
-		goto failure_handling;
-	if (!intel_dp_link_training_channel_equalization(intel_dp))
-		goto failure_handling;
+	if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
+		goto out;
 
-	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
-		    "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
-		    intel_connector->base.base.id,
-		    intel_connector->base.name,
-		    intel_dp->link_rate, intel_dp->lane_count);
-	return;
+	if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))
+		goto out;
+
+	ret = true;
 
- failure_handling:
+out:
 	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
-		    "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
+		    "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d, at %s",
 		    intel_connector->base.base.id,
 		    intel_connector->base.name,
-		    intel_dp->link_rate, intel_dp->lane_count);
+		    ret ? "passed" : "failed",
+		    crtc_state->port_clock, crtc_state->lane_count,
+		    intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
+
+	return ret;
+}
+
+static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
+						     const struct intel_crtc_state *crtc_state)
+{
+	struct intel_connector *intel_connector = intel_dp->attached_connector;
 
 	if (intel_dp->hobl_active) {
 		drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 			    "Link Training failed with HOBL active, not enabling it from now on");
 		intel_dp->hobl_failed = true;
 	} else if (intel_dp_get_link_train_fallback_values(intel_dp,
-							   intel_dp->link_rate,
-							   intel_dp->lane_count)) {
+							   crtc_state->port_clock,
+							   crtc_state->lane_count)) {
 		return;
 	}
 
 	/* Schedule a Hotplug Uevent to userspace to start modeset */
 	schedule_work(&intel_connector->modeset_retry_work);
 }
+
+/* Perform the link training on all LTTPRs and the DPRX on a link. */
+static bool
+intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
+			     const struct intel_crtc_state *crtc_state,
+			     int lttpr_count)
+{
+	bool ret = true;
+	int i;
+
+	intel_dp_prepare_link_train(intel_dp, crtc_state);
+
+	for (i = lttpr_count - 1; i >= 0; i--) {
+		enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i);
+
+		ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);
+		intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);
+
+		if (!ret)
+			break;
+	}
+
+	if (ret)
+		intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
+
+	if (intel_dp->set_idle_link_train)
+		intel_dp->set_idle_link_train(intel_dp, crtc_state);
+
+	return ret;
+}
+
+/**
+ * intel_dp_start_link_train - start link training
+ * @intel_dp: DP struct
+ * @crtc_state: state for CRTC attached to the encoder
+ *
+ * Start the link training of the @intel_dp port, scheduling a fallback
+ * retraining with reduced link rate/lane parameters if the link training
+ * fails.
+ * After calling this function intel_dp_stop_link_train() must be called.
+ */
+void intel_dp_start_link_train(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state)
+{
+	/*
+	 * TODO: Reiniting LTTPRs here won't be needed once proper connector
+	 * HW state readout is added.
+	 */
+	int lttpr_count = intel_dp_lttpr_init(intel_dp);
+
+	if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count))
+		intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 01f1dabbb060..86905aa24db7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -8,11 +8,24 @@
 
 #include <drm/drm_dp_helper.h>
 
+struct intel_crtc_state;
 struct intel_dp;
 
+int intel_dp_lttpr_init(struct intel_dp *intel_dp);
+
 void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state,
+			       enum drm_dp_phy dp_phy,
 			       const u8 link_status[DP_LINK_STATUS_SIZE]);
-void intel_dp_start_link_train(struct intel_dp *intel_dp);
-void intel_dp_stop_link_train(struct intel_dp *intel_dp);
+void intel_dp_start_link_train(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state);
+void intel_dp_stop_link_train(struct intel_dp *intel_dp,
+			      const struct intel_crtc_state *crtc_state);
+
+/* Get the TPSx symbol type of the value programmed to DP_TRAINING_PATTERN_SET */
+static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
+{
+	return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
+}
 
 #endif /* __INTEL_DP_LINK_TRAINING_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 64d885539e94..c8fcec4d0788 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -130,7 +130,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 	limits.min_lane_count =
 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
 
-	limits.min_bpp = intel_dp_min_bpp(pipe_config);
+	limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
 	/*
 	 * FIXME: If all the streams can't fit into the link with
 	 * their current pipe_bpp we should reduce pipe_bpp across
@@ -318,19 +318,23 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
 	return ret;
 }
 
-static void clear_act_sent(struct intel_dp *intel_dp)
+static void clear_act_sent(struct intel_encoder *encoder,
+			   const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 
-	intel_de_write(i915, intel_dp->regs.dp_tp_status,
+	intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
 		       DP_TP_STATUS_ACT_SENT);
 }
 
-static void wait_for_act_sent(struct intel_dp *intel_dp)
+static void wait_for_act_sent(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
+	struct intel_dp *intel_dp = &intel_mst->primary->dp;
 
-	if (intel_de_wait_for_set(i915, intel_dp->regs.dp_tp_status,
+	if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
 				  DP_TP_STATUS_ACT_SENT, 1))
 		drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
 
@@ -392,7 +396,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 
 	drm_dp_update_payload_part2(&intel_dp->mst_mgr);
 
-	clear_act_sent(intel_dp);
+	clear_act_sent(encoder, old_crtc_state);
 
 	val = intel_de_read(dev_priv,
 			    TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder));
@@ -401,7 +405,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 		       TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
 		       val);
 
-	wait_for_act_sent(intel_dp);
+	wait_for_act_sent(encoder, old_crtc_state);
 
 	drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port);
 
@@ -488,7 +492,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
 		    intel_dp->active_mst_links);
 
 	if (first_mst_stream)
-		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+		intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
 
 	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
 
@@ -535,7 +539,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
 
-	clear_act_sent(intel_dp);
+	clear_act_sent(encoder, pipe_config);
 
 	intel_ddi_enable_transcoder_func(encoder, pipe_config);
 
@@ -549,7 +553,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
 	drm_dbg_kms(&dev_priv->drm, "active links %d\n",
 		    intel_dp->active_mst_links);
 
-	wait_for_act_sent(intel_dp);
+	wait_for_act_sent(encoder, pipe_config);
 
 	drm_dp_update_payload_part2(&intel_dp->mst_mgr);
 
@@ -587,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
 	intel_ddi_get_config(&dig_port->base, pipe_config);
 }
 
+static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
+					       struct intel_crtc_state *crtc_state)
+{
+	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
+	struct intel_digital_port *dig_port = intel_mst->primary;
+
+	return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
+}
+
 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
 {
 	struct intel_connector *intel_connector = to_intel_connector(connector);
@@ -893,6 +906,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe
 	intel_encoder->enable = intel_mst_enable_dp;
 	intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
 	intel_encoder->get_config = intel_dp_mst_enc_get_config;
+	intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
 
 	return intel_mst;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 7910522273b2..514c4a7adffc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -644,16 +644,16 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
 	return mask;
 }
 
-
 void chv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 deemph_reg_value, u32 margin_reg_value,
 			      bool uniq_trans_scale)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-	enum pipe pipe = intel_crtc->pipe;
+	enum pipe pipe = crtc->pipe;
 	u32 val;
 	int i;
 
@@ -666,7 +666,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
 
-	if (intel_crtc->config->lane_count > 2) {
+	if (crtc_state->lane_count > 2) {
 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
 		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
 		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
@@ -679,7 +679,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
 
-	if (intel_crtc->config->lane_count > 2) {
+	if (crtc_state->lane_count > 2) {
 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
 		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
 		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
@@ -687,7 +687,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	}
 
 	/* Program swing deemph */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+	for (i = 0; i < crtc_state->lane_count; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
 		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
 		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
@@ -695,7 +695,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	}
 
 	/* Program swing margin */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+	for (i = 0; i < crtc_state->lane_count; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
 
 		val &= ~DPIO_SWING_MARGIN000_MASK;
@@ -718,7 +718,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	 * For now, for this unique transition scale selection, set bit
 	 * 27 for ch0 and ch1.
 	 */
-	for (i = 0; i < intel_crtc->config->lane_count; i++) {
+	for (i = 0; i < crtc_state->lane_count; i++) {
 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
 		if (uniq_trans_scale)
 			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
@@ -732,7 +732,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
 
-	if (intel_crtc->config->lane_count > 2) {
+	if (crtc_state->lane_count > 2) {
 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
 		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
@@ -992,14 +992,15 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
 }
 
 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 demph_reg_value, u32 preemph_reg_value,
 			      u32 uniqtranscale_reg_value, u32 tx3_demph)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
-	enum pipe pipe = intel_crtc->pipe;
+	enum pipe pipe = crtc->pipe;
 
 	vlv_dpio_get(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index f418aab90b7e..6473440e7457 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
@@ -32,6 +32,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
 u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
 
 void chv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 deemph_reg_value, u32 margin_reg_value,
 			      bool uniq_trans_scale);
 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
@@ -46,6 +47,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *old_crtc_state);
 
 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state,
 			      u32 demph_reg_value, u32 preemph_reg_value,
 			      u32 uniqtranscale_reg_value, u32 tx3_demph);
 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e08684e34078..eaef7a2d041f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -151,14 +151,14 @@ static i915_reg_t
 intel_combo_pll_enable_reg(struct drm_i915_private *i915,
 			   struct intel_shared_dpll *pll)
 {
-
-	if (IS_ELKHARTLAKE(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
+	if (IS_DG1(i915))
+		return DG1_DPLL_ENABLE(pll->info->id);
+	else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
 		return MG_PLL_ENABLE(0);
 
 	return CNL_DPLL_ENABLE(pll->info->id);
-
-
 }
+
 /**
  * intel_prepare_shared_dpll - call a dpll's prepare hook
  * @crtc_state: CRTC, and its state, which has a shared dpll
@@ -1602,9 +1602,19 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 	case DPLL_CFGCR2_PDIV_3:
 		p0 = 3;
 		break;
+	case DPLL_CFGCR2_PDIV_7_INVALID:
+		/*
+		 * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
+		 * handling it the same way as PDIV_7.
+		 */
+		drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
+		fallthrough;
 	case DPLL_CFGCR2_PDIV_7:
 		p0 = 7;
 		break;
+	default:
+		MISSING_CASE(p0);
+		return 0;
 	}
 
 	switch (p2) {
@@ -1620,6 +1630,9 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 	case DPLL_CFGCR2_KDIV_1:
 		p2 = 1;
 		break;
+	default:
+		MISSING_CASE(p2);
+		return 0;
 	}
 
 	dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
@@ -2622,11 +2635,22 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 	return true;
 }
 
+/*
+ * Display WA #22010492432: tgl
+ * Program half of the nominal DCO divider fraction value.
+ */
+static bool
+tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
+{
+	return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
+}
+
 static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
 				    const struct intel_shared_dpll *pll,
 				    int ref_clock)
 {
 	const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
+	u32 dco_fraction;
 	u32 p0, p1, p2, dco_freq;
 
 	p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
@@ -2669,8 +2693,13 @@ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
 	dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
 		   ref_clock;
 
-	dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
-		      DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
+	dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+		       DPLL_CFGCR0_DCO_FRACTION_SHIFT;
+
+	if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
+		dco_fraction *= 2;
+
+	dco_freq += (dco_fraction * ref_clock) / 0x8000;
 
 	if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
 		return 0;
@@ -2948,16 +2977,6 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
 	/* the following params are unused */
 };
 
-/*
- * Display WA #22010492432: tgl
- * Divide the nominal .dco_fraction value by 2.
- */
-static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = {
-	.dco_integer = 0x54, .dco_fraction = 0x1800,
-	/* the following params are unused */
-	.pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
-};
-
 static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
 				  struct skl_wrpll_params *pll_params)
 {
@@ -2991,14 +3010,12 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
 			MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
 			fallthrough;
 		case 19200:
+		case 38400:
 			*pll_params = tgl_tbt_pll_19_2MHz_values;
 			break;
 		case 24000:
 			*pll_params = tgl_tbt_pll_24MHz_values;
 			break;
-		case 38400:
-			*pll_params = tgl_tbt_pll_38_4MHz_values;
-			break;
 		}
 	} else {
 		switch (dev_priv->dpll.ref_clks.nssc) {
@@ -3065,9 +3082,14 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
 				const struct skl_wrpll_params *pll_params,
 				struct intel_dpll_hw_state *pll_state)
 {
+	u32 dco_fraction = pll_params->dco_fraction;
+
 	memset(pll_state, 0, sizeof(*pll_state));
 
-	pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params->dco_fraction) |
+	if (tgl_combo_pll_div_frac_wa_needed(i915))
+		dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
+
+	pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
 			    pll_params->dco_integer;
 
 	pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |
@@ -3524,12 +3546,22 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		if (port == PORT_D || port == PORT_E) {
+			dpll_mask =
+				BIT(DPLL_ID_DG1_DPLL2) |
+				BIT(DPLL_ID_DG1_DPLL3);
+		} else {
+			dpll_mask =
+				BIT(DPLL_ID_DG1_DPLL0) |
+				BIT(DPLL_ID_DG1_DPLL1);
+		}
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		dpll_mask =
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
 			BIT(DPLL_ID_ICL_DPLL0);
-	} else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) {
+	} else if (IS_JSL_EHL(dev_priv) && port != PORT_A) {
 		dpll_mask =
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
@@ -3820,7 +3852,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!(val & PLL_ENABLE))
 		goto out;
 
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
+		hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		hw_state->cfgcr0 = intel_de_read(dev_priv,
 						 RKL_DPLL_CFGCR0(id));
 		hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3831,7 +3866,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 		hw_state->cfgcr1 = intel_de_read(dev_priv,
 						 TGL_DPLL_CFGCR1(id));
 	} else {
-		if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+		if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
 			hw_state->cfgcr0 = intel_de_read(dev_priv,
 							 ICL_DPLL_CFGCR0(4));
 			hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3873,14 +3908,17 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
 	const enum intel_dpll_id id = pll->info->id;
 	i915_reg_t cfgcr0_reg, cfgcr1_reg;
 
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		cfgcr0_reg = DG1_DPLL_CFGCR0(id);
+		cfgcr1_reg = DG1_DPLL_CFGCR1(id);
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		cfgcr0_reg = RKL_DPLL_CFGCR0(id);
 		cfgcr1_reg = RKL_DPLL_CFGCR1(id);
 	} else if (INTEL_GEN(dev_priv) >= 12) {
 		cfgcr0_reg = TGL_DPLL_CFGCR0(id);
 		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
 	} else {
-		if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
+		if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
 			cfgcr0_reg = ICL_DPLL_CFGCR0(4);
 			cfgcr1_reg = ICL_DPLL_CFGCR1(4);
 		} else {
@@ -4054,7 +4092,7 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
 {
 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
 
-	if (IS_ELKHARTLAKE(dev_priv) &&
+	if (IS_JSL_EHL(dev_priv) &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4) {
 
 		/*
@@ -4167,7 +4205,7 @@ static void combo_pll_disable(struct drm_i915_private *dev_priv,
 
 	icl_pll_disable(dev_priv, pll, enable_reg);
 
-	if (IS_ELKHARTLAKE(dev_priv) &&
+	if (IS_JSL_EHL(dev_priv) &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4)
 		intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
 					pll->wakeref);
@@ -4317,6 +4355,22 @@ static const struct intel_dpll_mgr rkl_pll_mgr = {
 	.dump_hw_state = icl_dump_hw_state,
 };
 
+static const struct dpll_info dg1_plls[] = {
+	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
+	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
+	{ "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
+	{ "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
+	{ },
+};
+
+static const struct intel_dpll_mgr dg1_pll_mgr = {
+	.dpll_info = dg1_plls,
+	.get_dplls = icl_get_dplls,
+	.put_dplls = icl_put_dplls,
+	.update_ref_clks = icl_update_dpll_ref_clks,
+	.dump_hw_state = icl_dump_hw_state,
+};
+
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
  * @dev: drm device
@@ -4330,11 +4384,13 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (IS_ROCKETLAKE(dev_priv))
+	if (IS_DG1(dev_priv))
+		dpll_mgr = &dg1_pll_mgr;
+	else if (IS_ROCKETLAKE(dev_priv))
 		dpll_mgr = &rkl_pll_mgr;
 	else if (INTEL_GEN(dev_priv) >= 12)
 		dpll_mgr = &tgl_pll_mgr;
-	else if (IS_ELKHARTLAKE(dev_priv))
+	else if (IS_JSL_EHL(dev_priv))
 		dpll_mgr = &ehl_pll_mgr;
 	else if (INTEL_GEN(dev_priv) >= 11)
 		dpll_mgr = &icl_pll_mgr;
@@ -4476,7 +4532,7 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
 	pll->on = pll->info->funcs->get_hw_state(i915, pll,
 						 &pll->state.hw_state);
 
-	if (IS_ELKHARTLAKE(i915) && pll->on &&
+	if (IS_JSL_EHL(i915) && pll->on &&
 	    pll->info->id == DPLL_ID_EHL_DPLL4) {
 		pll->wakeref = intel_display_power_get(i915,
 						       POWER_DOMAIN_DPLL_DC_OFF);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 5d9a2bc371e7..205542fb8dc7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -154,6 +154,23 @@ enum intel_dpll_id {
 	 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
 	 */
 	DPLL_ID_TGL_MGPLL6 = 8,
+
+	/**
+	 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
+	 */
+	DPLL_ID_DG1_DPLL0 = 0,
+	/**
+	 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
+	 */
+	DPLL_ID_DG1_DPLL1 = 1,
+	/**
+	 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
+	 */
+	DPLL_ID_DG1_DPLL2 = 2,
+	/**
+	 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
+	 */
+	DPLL_ID_DG1_DPLL3 = 3,
 };
 
 #define I915_NUM_PLLS 9
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h
index 19f78a4022d3..625f2f1ae061 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.h
+++ b/drivers/gpu/drm/i915/display/intel_dsi.h
@@ -167,6 +167,7 @@ static inline u16 intel_dsi_encoder_ports(struct intel_encoder *encoder)
 
 /* icl_dsi.c */
 void icl_dsi_init(struct drm_i915_private *dev_priv);
+void icl_dsi_frame_update(struct intel_crtc_state *crtc_state);
 
 /* intel_dsi.c */
 int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 135f5e8a4d70..a5b072816a7b 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -907,6 +907,13 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 		return false;
 	}
 
+	/* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
+	if (INTEL_GEN(dev_priv) >= 11 &&
+	    (cache->plane.src_h + cache->plane.adjusted_y) % 4) {
+		fbc->no_fbc_reason = "plane height + offset is non-modulo of 4";
+		return false;
+	}
+
 	return true;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index e6b8d6dfb598..b0d71bbbf2ad 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -90,11 +90,20 @@ static const struct gmbus_pin gmbus_pins_icp[] = {
 	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
 };
 
+static const struct gmbus_pin gmbus_pins_dg1[] = {
+	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+		return &gmbus_pins_dg1[pin];
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		return &gmbus_pins_icp[pin];
 	else if (HAS_PCH_CNP(dev_priv))
 		return &gmbus_pins_cnp[pin];
@@ -113,7 +122,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+		size = ARRAY_SIZE(gmbus_pins_dg1);
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		size = ARRAY_SIZE(gmbus_pins_icp);
 	else if (HAS_PCH_CNP(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_cnp);
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 5492076d1ae0..b2a4bbcfdcd2 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1445,10 +1445,9 @@ static int hdcp2_session_key_exchange(struct intel_connector *connector)
 }
 
 static
-int hdcp2_propagate_stream_management_info(struct intel_connector *connector)
+int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
 {
 	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	struct intel_hdcp *hdcp = &connector->hdcp;
 	union {
 		struct hdcp2_rep_stream_manage stream_manage;
@@ -1457,6 +1456,9 @@ int hdcp2_propagate_stream_management_info(struct intel_connector *connector)
 	const struct intel_hdcp_shim *shim = hdcp->shim;
 	int ret;
 
+	if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
+		return -ERANGE;
+
 	/* Prepare RepeaterAuth_Stream_Manage msg */
 	msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
 	drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
@@ -1472,28 +1474,21 @@ int hdcp2_propagate_stream_management_info(struct intel_connector *connector)
 	ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
 				  sizeof(msgs.stream_manage));
 	if (ret < 0)
-		return ret;
+		goto out;
 
 	ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_STREAM_READY,
 				 &msgs.stream_ready, sizeof(msgs.stream_ready));
 	if (ret < 0)
-		return ret;
+		goto out;
 
 	hdcp->port_data.seq_num_m = hdcp->seq_num_m;
 	hdcp->port_data.streams[0].stream_type = hdcp->content_type;
-
 	ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
-	if (ret < 0)
-		return ret;
 
+out:
 	hdcp->seq_num_m++;
 
-	if (hdcp->seq_num_m > HDCP_2_2_SEQ_NUM_MAX) {
-		drm_dbg_kms(&i915->drm, "seq_num_m roll over.\n");
-		return -1;
-	}
-
-	return 0;
+	return ret;
 }
 
 static
@@ -1564,17 +1559,6 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector)
 	return 0;
 }
 
-static int hdcp2_authenticate_repeater(struct intel_connector *connector)
-{
-	int ret;
-
-	ret = hdcp2_authenticate_repeater_topology(connector);
-	if (ret < 0)
-		return ret;
-
-	return hdcp2_propagate_stream_management_info(connector);
-}
-
 static int hdcp2_authenticate_sink(struct intel_connector *connector)
 {
 	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
@@ -1611,7 +1595,7 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector)
 	}
 
 	if (hdcp->is_repeater) {
-		ret = hdcp2_authenticate_repeater(connector);
+		ret = hdcp2_authenticate_repeater_topology(connector);
 		if (ret < 0) {
 			drm_dbg_kms(&i915->drm,
 				    "Repeater Auth Failed. Err: %d\n", ret);
@@ -1619,11 +1603,6 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector)
 		}
 	}
 
-	hdcp->port_data.streams[0].stream_type = hdcp->content_type;
-	ret = hdcp2_authenticate_port(connector);
-	if (ret < 0)
-		return ret;
-
 	return ret;
 }
 
@@ -1704,15 +1683,59 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
 	return ret;
 }
 
+static int
+hdcp2_propagate_stream_management_info(struct intel_connector *connector)
+{
+	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	int i, tries = 3, ret;
+
+	if (!connector->hdcp.is_repeater)
+		return 0;
+
+	for (i = 0; i < tries; i++) {
+		ret = _hdcp2_propagate_stream_management_info(connector);
+		if (!ret)
+			break;
+
+		/* Lets restart the auth incase of seq_num_m roll over */
+		if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) {
+			drm_dbg_kms(&i915->drm,
+				    "seq_num_m roll over.(%d)\n", ret);
+			break;
+		}
+
+		drm_dbg_kms(&i915->drm,
+			    "HDCP2 stream management %d of %d Failed.(%d)\n",
+			    i + 1, tries, ret);
+	}
+
+	return ret;
+}
+
 static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
 {
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct intel_hdcp *hdcp = &connector->hdcp;
 	int ret, i, tries = 3;
 
 	for (i = 0; i < tries; i++) {
 		ret = hdcp2_authenticate_sink(connector);
-		if (!ret)
-			break;
+		if (!ret) {
+			ret = hdcp2_propagate_stream_management_info(connector);
+			if (ret) {
+				drm_dbg_kms(&i915->drm,
+					    "Stream management failed.(%d)\n",
+					    ret);
+				break;
+			}
+			hdcp->port_data.streams[0].stream_type =
+							hdcp->content_type;
+			ret = hdcp2_authenticate_port(connector);
+			if (!ret)
+				break;
+			drm_dbg_kms(&i915->drm, "HDCP2 port auth failed.(%d)\n",
+				    ret);
+		}
 
 		/* Clearing the mei hdcp session */
 		drm_dbg_kms(&i915->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n",
@@ -1721,7 +1744,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
 			drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
 	}
 
-	if (i != tries) {
+	if (!ret) {
 		/*
 		 * Ensuring the required 200mSec min time interval between
 		 * Session Key Exchange and encryption.
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 3f2008d845c2..f90838bc74fb 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2775,8 +2775,9 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
 	vlv_phy_pre_encoder_enable(encoder, pipe_config);
 
 	/* HDMI 1.0V-2dB */
-	vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
-				 0x2b247878);
+	vlv_set_phy_signal_level(encoder, pipe_config,
+				 0x2b245f5f, 0x00002000,
+				 0x5578b83a, 0x2b247878);
 
 	dig_port->set_infoframes(encoder,
 			      pipe_config->has_infoframe,
@@ -2853,7 +2854,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
 
 	/* FIXME: Program the support xxx V-dB */
 	/* Use 800mV-0dB */
-	chv_set_phy_signal_level(encoder, 128, 102, false);
+	chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
 
 	dig_port->set_infoframes(encoder,
 			      pipe_config->has_infoframe,
@@ -3139,6 +3140,11 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
 	return GMBUS_PIN_1_BXT + phy;
 }
 
+static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+	return intel_port_to_phy(dev_priv, port) + 1;
+}
+
 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
 			      enum port port)
 {
@@ -3176,7 +3182,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
 		return ddc_pin;
 	}
 
-	if (IS_ROCKETLAKE(dev_priv))
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+		ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
+	else if (IS_ROCKETLAKE(dev_priv))
 		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
 	else if (HAS_PCH_MCC(dev_priv))
 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
@@ -3214,7 +3222,7 @@ void intel_infoframe_init(struct intel_digital_port *dig_port)
 		dig_port->set_infoframes = g4x_set_infoframes;
 		dig_port->infoframes_enabled = g4x_infoframes_enabled;
 	} else if (HAS_DDI(dev_priv)) {
-		if (dig_port->lspcon.active) {
+		if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
 			dig_port->write_infoframe = lspcon_write_infoframe;
 			dig_port->read_infoframe = lspcon_read_infoframe;
 			dig_port->set_infoframes = lspcon_set_infoframes;
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 5c58c1ed6493..f46a1b7190b8 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -213,6 +213,12 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void intel_hpd_irq_setup(struct drm_i915_private *i915)
+{
+	if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
+		i915->display.hpd_irq_setup(i915);
+}
+
 static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
 {
 	struct drm_i915_private *dev_priv =
@@ -248,8 +254,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
 			dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
 	}
 
-	if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup)
-		dev_priv->display.hpd_irq_setup(dev_priv);
+	intel_hpd_irq_setup(dev_priv);
 
 	spin_unlock_irq(&dev_priv->irq_lock);
 
@@ -556,8 +561,8 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
 	 * Disable any IRQs that storms were detected on. Polling enablement
 	 * happens later in our hotplug work.
 	 */
-	if (storm_detected && dev_priv->display_irqs_enabled)
-		dev_priv->display.hpd_irq_setup(dev_priv);
+	if (storm_detected)
+		intel_hpd_irq_setup(dev_priv);
 	spin_unlock(&dev_priv->irq_lock);
 
 	/*
@@ -584,7 +589,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
  * This is a separate step from interrupt enabling to simplify the locking rules
  * in the driver load and resume code.
  *
- * Also see: intel_hpd_poll_init(), which enables connector polling
+ * Also see: intel_hpd_poll_enable() and intel_hpd_poll_disable().
  */
 void intel_hpd_init(struct drm_i915_private *dev_priv)
 {
@@ -595,19 +600,13 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
 		dev_priv->hotplug.stats[i].state = HPD_ENABLED;
 	}
 
-	WRITE_ONCE(dev_priv->hotplug.poll_enabled, false);
-	schedule_work(&dev_priv->hotplug.poll_init_work);
-
 	/*
 	 * Interrupt setup is already guaranteed to be single-threaded, this is
 	 * just to make the assert_spin_locked checks happy.
 	 */
-	if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) {
-		spin_lock_irq(&dev_priv->irq_lock);
-		if (dev_priv->display_irqs_enabled)
-			dev_priv->display.hpd_irq_setup(dev_priv);
-		spin_unlock_irq(&dev_priv->irq_lock);
-	}
+	spin_lock_irq(&dev_priv->irq_lock);
+	intel_hpd_irq_setup(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
 static void i915_hpd_poll_init_work(struct work_struct *work)
@@ -654,12 +653,12 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
 }
 
 /**
- * intel_hpd_poll_init - enables/disables polling for connectors with hpd
+ * intel_hpd_poll_enable - enable polling for connectors with hpd
  * @dev_priv: i915 device instance
  *
- * This function enables polling for all connectors, regardless of whether or
- * not they support hotplug detection. Under certain conditions HPD may not be
- * functional. On most Intel GPUs, this happens when we enter runtime suspend.
+ * This function enables polling for all connectors which support HPD.
+ * Under certain conditions HPD may not be functional. On most Intel GPUs,
+ * this happens when we enter runtime suspend.
  * On Valleyview and Cherryview systems, this also happens when we shut off all
  * of the powerwells.
  *
@@ -667,9 +666,9 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
  * dev->mode_config.mutex, we do the actual hotplug enabling in a seperate
  * worker.
  *
- * Also see: intel_hpd_init(), which restores hpd handling.
+ * Also see: intel_hpd_init() and intel_hpd_poll_disable().
  */
-void intel_hpd_poll_init(struct drm_i915_private *dev_priv)
+void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
 {
 	WRITE_ONCE(dev_priv->hotplug.poll_enabled, true);
 
@@ -682,6 +681,31 @@ void intel_hpd_poll_init(struct drm_i915_private *dev_priv)
 	schedule_work(&dev_priv->hotplug.poll_init_work);
 }
 
+/**
+ * intel_hpd_poll_disable - disable polling for connectors with hpd
+ * @dev_priv: i915 device instance
+ *
+ * This function disables polling for all connectors which support HPD.
+ * Under certain conditions HPD may not be functional. On most Intel GPUs,
+ * this happens when we enter runtime suspend.
+ * On Valleyview and Cherryview systems, this also happens when we shut off all
+ * of the powerwells.
+ *
+ * Since this function can get called in contexts where we're already holding
+ * dev->mode_config.mutex, we do the actual hotplug enabling in a seperate
+ * worker.
+ *
+ * Also used during driver init to initialize connector->polled
+ * appropriately for all connectors.
+ *
+ * Also see: intel_hpd_init() and intel_hpd_poll_enable().
+ */
+void intel_hpd_poll_disable(struct drm_i915_private *dev_priv)
+{
+	WRITE_ONCE(dev_priv->hotplug.poll_enabled, false);
+	schedule_work(&dev_priv->hotplug.poll_init_work);
+}
+
 void intel_hpd_init_work(struct drm_i915_private *dev_priv)
 {
 	INIT_DELAYED_WORK(&dev_priv->hotplug.hotplug_work,
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h b/drivers/gpu/drm/i915/display/intel_hotplug.h
index a704d7c94d16..b87e95d606e6 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.h
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.h
@@ -14,7 +14,8 @@ struct intel_digital_port;
 struct intel_encoder;
 enum port;
 
-void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
+void intel_hpd_poll_enable(struct drm_i915_private *dev_priv);
+void intel_hpd_poll_disable(struct drm_i915_private *dev_priv);
 enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder,
 					       struct intel_connector *connector);
 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index dc1b35559afd..e37d45e531df 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -184,21 +184,6 @@ static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon)
 	return true;
 }
 
-void lspcon_ycbcr420_config(struct drm_connector *connector,
-			    struct intel_crtc_state *crtc_state)
-{
-	const struct drm_display_info *info = &connector->display_info;
-	const struct drm_display_mode *adjusted_mode =
-					&crtc_state->hw.adjusted_mode;
-
-	if (drm_mode_is_420_only(info, adjusted_mode) &&
-	    connector->ycbcr_420_allowed) {
-		crtc_state->port_clock /= 2;
-		crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
-		crtc_state->lspcon_downsampling = true;
-	}
-}
-
 static bool lspcon_probe(struct intel_lspcon *lspcon)
 {
 	int retry;
@@ -492,14 +477,19 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
 		return;
 	}
 
-	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
-		if (crtc_state->lspcon_downsampling)
-			frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
-		else
-			frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
-	} else {
+	/*
+	 * Currently there is no interface defined to
+	 * check user preference between RGB/YCBCR444
+	 * or YCBCR420. So the only possible case for
+	 * YCBCR444 usage is driving YCBCR420 output
+	 * with LSPCON, when pipe is configured for
+	 * YCBCR444 output and LSPCON takes care of
+	 * downsampling it.
+	 */
+	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
+		frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
+	else
 		frame.avi.colorspace = HDMI_COLORSPACE_RGB;
-	}
 
 	drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 					   conn_state->connector,
@@ -525,44 +515,17 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
 	return 0;
 }
 
-void lspcon_resume(struct intel_lspcon *lspcon)
-{
-	enum drm_lspcon_mode expected_mode;
-
-	if (lspcon_wake_native_aux_ch(lspcon)) {
-		expected_mode = DRM_LSPCON_MODE_PCON;
-		lspcon_resume_in_pcon_wa(lspcon);
-	} else {
-		expected_mode = DRM_LSPCON_MODE_LS;
-	}
-
-	if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON)
-		return;
-
-	if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON))
-		DRM_ERROR("LSPCON resume failed\n");
-	else
-		DRM_DEBUG_KMS("LSPCON resume success\n");
-}
-
 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon)
 {
 	lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON);
 }
 
-bool lspcon_init(struct intel_digital_port *dig_port)
+static bool lspcon_init(struct intel_digital_port *dig_port)
 {
 	struct intel_dp *dp = &dig_port->dp;
 	struct intel_lspcon *lspcon = &dig_port->lspcon;
-	struct drm_device *dev = dig_port->base.base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct drm_connector *connector = &dp->attached_connector->base;
 
-	if (!HAS_LSPCON(dev_priv)) {
-		DRM_ERROR("LSPCON is not supported on this platform\n");
-		return false;
-	}
-
 	lspcon->active = false;
 	lspcon->mode = DRM_LSPCON_MODE_INVALID;
 
@@ -586,3 +549,37 @@ bool lspcon_init(struct intel_digital_port *dig_port)
 	DRM_DEBUG_KMS("Success: LSPCON init\n");
 	return true;
 }
+
+void lspcon_resume(struct intel_digital_port *dig_port)
+{
+	struct intel_lspcon *lspcon = &dig_port->lspcon;
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	enum drm_lspcon_mode expected_mode;
+
+	if (!intel_bios_is_lspcon_present(dev_priv, dig_port->base.port))
+		return;
+
+	if (!lspcon->active) {
+		if (!lspcon_init(dig_port)) {
+			DRM_ERROR("LSPCON init failed on port %c\n",
+				  port_name(dig_port->base.port));
+			return;
+		}
+	}
+
+	if (lspcon_wake_native_aux_ch(lspcon)) {
+		expected_mode = DRM_LSPCON_MODE_PCON;
+		lspcon_resume_in_pcon_wa(lspcon);
+	} else {
+		expected_mode = DRM_LSPCON_MODE_LS;
+	}
+
+	if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON)
+		return;
+
+	if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON))
+		DRM_ERROR("LSPCON resume failed\n");
+	else
+		DRM_DEBUG_KMS("LSPCON resume success\n");
+}
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h
index 1cffe8a42a08..b03dcb7076d8 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.h
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
@@ -15,8 +15,7 @@ struct intel_digital_port;
 struct intel_encoder;
 struct intel_lspcon;
 
-bool lspcon_init(struct intel_digital_port *dig_port);
-void lspcon_resume(struct intel_lspcon *lspcon);
+void lspcon_resume(struct intel_digital_port *dig_port);
 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
 void lspcon_write_infoframe(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state,
@@ -32,7 +31,5 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
 			   const struct drm_connector_state *conn_state);
 u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *pipe_config);
-void lspcon_ycbcr420_config(struct drm_connector *connector,
-			    struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_LSPCON_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index e65c2de522c3..c6c7c0b9989b 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -371,6 +371,15 @@ static void pch_post_disable_lvds(struct intel_atomic_state *state,
 	intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
 }
 
+static void intel_lvds_shutdown(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000))
+		drm_err(&dev_priv->drm,
+			"timed out waiting for panel power cycle delay\n");
+}
+
 static enum drm_mode_status
 intel_lvds_mode_valid(struct drm_connector *connector,
 		      struct drm_display_mode *mode)
@@ -897,6 +906,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
 	intel_encoder->get_hw_state = intel_lvds_get_hw_state;
 	intel_encoder->get_config = intel_lvds_get_config;
 	intel_encoder->update_pipe = intel_panel_update_backlight;
+	intel_encoder->shutdown = intel_lvds_shutdown;
 	intel_connector->get_hw_state = intel_connector_get_hw_state;
 
 	intel_connector_attach_encoder(intel_connector, intel_encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index de995362f428..4f77cf849171 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -1007,12 +1007,8 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv)
 	int ret;
 
 	ret = swsci(dev_priv, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Failed to get panel details from OpRegion (%d)\n",
-			    ret);
+	if (ret)
 		return ret;
-	}
 
 	ret = (panel_details >> 8) & 0xff;
 	if (ret > 0x10) {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8a9d0bdde1bf..1576c3722d0b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -91,19 +91,14 @@ static bool psr_global_enabled(struct drm_i915_private *i915)
 	}
 }
 
-static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
-			       const struct intel_crtc_state *crtc_state)
+static bool psr2_global_enabled(struct drm_i915_private *dev_priv)
 {
-	/* Cannot enable DSC and PSR2 simultaneously */
-	drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable &&
-		    crtc_state->has_psr2);
-
 	switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
 	case I915_PSR_DEBUG_DISABLE:
 	case I915_PSR_DEBUG_FORCE_PSR1:
 		return false;
 	default:
-		return crtc_state->has_psr2;
+		return true;
 	}
 }
 
@@ -729,6 +724,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	if (!psr2_global_enabled(dev_priv)) {
+		drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
+		return false;
+	}
+
 	/*
 	 * DSC and PSR2 cannot be enabled simultaneously. If a requested
 	 * resolution requires DSC to be enabled, priority is given to DSC
@@ -817,8 +817,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	if (intel_dp != dev_priv->psr.dp)
 		return;
 
-	if (!psr_global_enabled(dev_priv))
+	if (!psr_global_enabled(dev_priv)) {
+		drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
 		return;
+	}
+
 	/*
 	 * HSW spec explicitly says PSR is tied to port A.
 	 * BDW+ platforms have a instance of PSR registers per transcoder but
@@ -942,7 +945,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
 	}
 
-	if (HAS_PSR_HW_TRACKING(dev_priv))
+	if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
 		intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
 			     dev_priv->psr.psr2_sel_fetch_enabled ?
 			     IGNORE_PSR2_HW_TRACKING : 0);
@@ -959,7 +962,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
 
 	drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
 
-	dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
+	dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 	dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 	dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
@@ -1029,15 +1032,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
 	drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
 
 	mutex_lock(&dev_priv->psr.lock);
-
-	if (!psr_global_enabled(dev_priv)) {
-		drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
-		goto unlock;
-	}
-
 	intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
-
-unlock:
 	mutex_unlock(&dev_priv->psr.lock);
 }
 
@@ -1152,7 +1147,21 @@ void intel_psr_disable(struct intel_dp *intel_dp,
 
 static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
 {
-	if (INTEL_GEN(dev_priv) >= 9)
+	if (IS_TIGERLAKE(dev_priv))
+		/*
+		 * Writes to CURSURFLIVE in TGL are causing IOMMU errors and
+		 * visual glitches that are often reproduced when executing
+		 * CPU intensive workloads while a eDP 4K panel is attached.
+		 *
+		 * Manually exiting PSR causes the frontbuffer to be updated
+		 * without glitches and the IOMMU errors are also gone but
+		 * this comes at the cost of less time with PSR active.
+		 *
+		 * So using this workaround until this issue is root caused
+		 * and a better fix is found.
+		 */
+		intel_psr_exit(dev_priv);
+	else if (INTEL_GEN(dev_priv) >= 9)
 		/*
 		 * Display WA #0884: skl+
 		 * This documented WA for bxt can be safely applied
@@ -1171,6 +1180,38 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
 		intel_psr_exit(dev_priv);
 }
 
+void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
+					const struct intel_crtc_state *crtc_state,
+					const struct intel_plane_state *plane_state,
+					int color_plane)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum pipe pipe = plane->pipe;
+	u32 val;
+
+	if (!crtc_state->enable_psr2_sel_fetch)
+		return;
+
+	val = plane_state ? plane_state->ctl : 0;
+	val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
+	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
+	if (!val || plane->id == PLANE_CURSOR)
+		return;
+
+	val = plane_state->uapi.dst.y1 << 16 | plane_state->uapi.dst.x1;
+	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
+
+	val = plane_state->color_plane[color_plane].y << 16;
+	val |= plane_state->color_plane[color_plane].x;
+	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
+			  val);
+
+	/* Sizes are 0 based */
+	val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) << 16;
+	val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
+	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
+}
+
 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1185,16 +1226,91 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
 		       crtc_state->psr2_man_track_ctl);
 }
 
-void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
-				 struct intel_crtc *crtc)
+static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
+				  struct drm_rect *clip, bool full_update)
+{
+	u32 val = PSR2_MAN_TRK_CTL_ENABLE;
+
+	if (full_update) {
+		val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+		goto exit;
+	}
+
+	if (clip->y1 == -1)
+		goto exit;
+
+	val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
+	val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
+	val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) + 1);
+exit:
+	crtc_state->psr2_man_track_ctl = val;
+}
+
+static void clip_area_update(struct drm_rect *overlap_damage_area,
+			     struct drm_rect *damage_area)
+{
+	if (overlap_damage_area->y1 == -1) {
+		overlap_damage_area->y1 = damage_area->y1;
+		overlap_damage_area->y2 = damage_area->y2;
+		return;
+	}
+
+	if (damage_area->y1 < overlap_damage_area->y1)
+		overlap_damage_area->y1 = damage_area->y1;
+
+	if (damage_area->y2 > overlap_damage_area->y2)
+		overlap_damage_area->y2 = damage_area->y2;
+}
+
+int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
+				struct intel_crtc *crtc)
 {
 	struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+	struct intel_plane_state *new_plane_state, *old_plane_state;
+	struct drm_rect pipe_clip = { .y1 = -1 };
+	struct intel_plane *plane;
+	bool full_update = false;
+	int i, ret;
 
 	if (!crtc_state->enable_psr2_sel_fetch)
-		return;
+		return 0;
+
+	ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
+	if (ret)
+		return ret;
+
+	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
+					     new_plane_state, i) {
+		struct drm_rect temp;
+
+		if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
+			continue;
+
+		/*
+		 * TODO: Not clear how to handle planes with negative position,
+		 * also planes are not updated if they have a negative X
+		 * position so for now doing a full update in this cases
+		 */
+		if (new_plane_state->uapi.dst.y1 < 0 ||
+		    new_plane_state->uapi.dst.x1 < 0) {
+			full_update = true;
+			break;
+		}
+
+		if (!new_plane_state->uapi.visible)
+			continue;
 
-	crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE |
-					 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+		/*
+		 * For now doing a selective fetch in the whole plane area,
+		 * optimizations will come in the future.
+		 */
+		temp.y1 = new_plane_state->uapi.dst.y1;
+		temp.y2 = new_plane_state->uapi.dst.y2;
+		clip_area_update(&pipe_clip, &temp);
+	}
+
+	psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
+	return 0;
 }
 
 /**
@@ -1222,8 +1338,8 @@ void intel_psr_update(struct intel_dp *intel_dp,
 
 	mutex_lock(&dev_priv->psr.lock);
 
-	enable = crtc_state->has_psr && psr_global_enabled(dev_priv);
-	psr2_enable = intel_psr2_enabled(dev_priv, crtc_state);
+	enable = crtc_state->has_psr;
+	psr2_enable = crtc_state->has_psr2;
 
 	if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
 		/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
@@ -1320,11 +1436,12 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
 
 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
 {
+	struct drm_connector_list_iter conn_iter;
 	struct drm_device *dev = &dev_priv->drm;
 	struct drm_modeset_acquire_ctx ctx;
 	struct drm_atomic_state *state;
-	struct intel_crtc *crtc;
-	int err;
+	struct drm_connector *conn;
+	int err = 0;
 
 	state = drm_atomic_state_alloc(dev);
 	if (!state)
@@ -1334,25 +1451,38 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
 	state->acquire_ctx = &ctx;
 
 retry:
-	for_each_intel_crtc(dev, crtc) {
-		struct intel_crtc_state *crtc_state =
-			intel_atomic_get_crtc_state(state, crtc);
 
-		if (IS_ERR(crtc_state)) {
-			err = PTR_ERR(crtc_state);
-			goto error;
+	drm_connector_list_iter_begin(dev, &conn_iter);
+	drm_for_each_connector_iter(conn, &conn_iter) {
+		struct drm_connector_state *conn_state;
+		struct drm_crtc_state *crtc_state;
+
+		if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
+			continue;
+
+		conn_state = drm_atomic_get_connector_state(state, conn);
+		if (IS_ERR(conn_state)) {
+			err = PTR_ERR(conn_state);
+			break;
 		}
 
-		if (crtc_state->hw.active && crtc_state->has_psr) {
-			/* Mark mode as changed to trigger a pipe->update() */
-			crtc_state->uapi.mode_changed = true;
+		if (!conn_state->crtc)
+			continue;
+
+		crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
+		if (IS_ERR(crtc_state)) {
+			err = PTR_ERR(crtc_state);
 			break;
 		}
+
+		/* Mark mode as changed to trigger a pipe->update() */
+		crtc_state->mode_changed = true;
 	}
+	drm_connector_list_iter_end(&conn_iter);
 
-	err = drm_atomic_commit(state);
+	if (err == 0)
+		err = drm_atomic_commit(state);
 
-error:
 	if (err == -EDEADLK) {
 		drm_atomic_state_clear(state);
 		err = drm_modeset_backoff(&ctx);
@@ -1754,7 +1884,7 @@ void intel_psr_atomic_check(struct drm_connector *connector,
 		return;
 
 	intel_connector = to_intel_connector(connector);
-	dig_port = enc_to_dig_port(intel_attached_encoder(intel_connector));
+	dig_port = enc_to_dig_port(to_intel_encoder(new_state->best_encoder));
 	if (dev_priv->psr.dp != &dig_port->dp)
 		return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 6a83c8e682e6..3eca9dcec3c0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -15,6 +15,8 @@ struct intel_crtc_state;
 struct intel_dp;
 struct intel_crtc;
 struct intel_atomic_state;
+struct intel_plane_state;
+struct intel_plane;
 
 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
@@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct drm_connector *connector,
 			    struct drm_connector_state *old_state,
 			    struct drm_connector_state *new_state);
 void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp);
-void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
-				 struct intel_crtc *crtc);
+int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
+				struct intel_crtc *crtc);
 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);
+void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
+					const struct intel_crtc_state *crtc_state,
+					const struct intel_plane_state *plane_state,
+					int color_plane);
 
 #endif /* __INTEL_PSR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 63040cb0d4e1..b6deeb338477 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -47,6 +47,7 @@
 #include "intel_frontbuffer.h"
 #include "intel_pm.h"
 #include "intel_psr.h"
+#include "intel_dsi.h"
 #include "intel_sprite.h"
 
 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
@@ -93,6 +94,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
 	DEFINE_WAIT(wait);
 	u32 psr_status;
 
+	if (new_crtc_state->uapi.async_flip)
+		return;
+
 	vblank_start = adjusted_mode->crtc_vblank_start;
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 		vblank_start = DIV_ROUND_UP(vblank_start, 2);
@@ -200,8 +204,19 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 	ktime_t end_vbl_time = ktime_get();
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
+	if (new_crtc_state->uapi.async_flip)
+		return;
+
 	trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
 
+	/*
+	 * Incase of mipi dsi command mode, we need to set frame update
+	 * request for every commit.
+	 */
+	if (INTEL_GEN(dev_priv) >= 11 &&
+	    intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
+		icl_dsi_frame_update(new_crtc_state);
+
 	/* We're still in the vblank-evade critical section, this can't race.
 	 * Would be slightly nice to just grab the vblank count and arm the
 	 * event outside of the critical section - the spinlock might spin for a
@@ -429,6 +444,7 @@ skl_program_scaler(struct intel_plane *plane,
 	u16 y_hphase, uv_rgb_hphase;
 	u16 y_vphase, uv_rgb_vphase;
 	int hscale, vscale;
+	u32 ps_ctrl;
 
 	hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
 				      &plane_state->uapi.dst,
@@ -455,8 +471,13 @@ skl_program_scaler(struct intel_plane *plane,
 		uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
 	}
 
-	intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id),
-			  PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
+	ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
+	ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
+
+	skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
+				plane_state->hw.scaling_filter);
+
+	intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
 	intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
 			  PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
 	intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
@@ -604,6 +625,29 @@ icl_program_input_csc(struct intel_plane *plane,
 }
 
 static void
+skl_plane_async_flip(struct intel_plane *plane,
+		     const struct intel_crtc_state *crtc_state,
+		     const struct intel_plane_state *plane_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	unsigned long irqflags;
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = plane->pipe;
+	u32 surf_addr = plane_state->color_plane[0].offset;
+	u32 plane_ctl = plane_state->ctl;
+
+	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
+
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
+	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
+			  intel_plane_ggtt_offset(plane_state) + surf_addr);
+
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
+static void
 skl_program_plane(struct intel_plane *plane,
 		  const struct intel_crtc_state *crtc_state,
 		  const struct intel_plane_state *plane_state,
@@ -617,8 +661,6 @@ skl_program_plane(struct intel_plane *plane,
 	u32 stride = skl_plane_stride(plane_state, color_plane);
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	int aux_plane = intel_main_to_aux_plane(fb, color_plane);
-	u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
-	u32 aux_stride = skl_plane_stride(plane_state, aux_plane);
 	int crtc_x = plane_state->uapi.dst.x1;
 	int crtc_y = plane_state->uapi.dst.y1;
 	u32 x = plane_state->color_plane[color_plane].x;
@@ -626,7 +668,7 @@ skl_program_plane(struct intel_plane *plane,
 	u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 	u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 	u8 alpha = plane_state->hw.alpha >> 8;
-	u32 plane_color_ctl = 0;
+	u32 plane_color_ctl = 0, aux_dist = 0;
 	unsigned long irqflags;
 	u32 keymsk, keymax;
 	u32 plane_ctl = plane_state->ctl;
@@ -653,6 +695,13 @@ skl_program_plane(struct intel_plane *plane,
 		crtc_y = 0;
 	}
 
+	if (aux_plane) {
+		aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr;
+
+		if (INTEL_GEN(dev_priv) < 12)
+			aux_dist |= skl_plane_stride(plane_state, aux_plane);
+	}
+
 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 
 	intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
@@ -661,8 +710,6 @@ skl_program_plane(struct intel_plane *plane,
 	intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
 			  (src_h << 16) | src_w);
 
-	if (INTEL_GEN(dev_priv) < 12)
-		aux_dist |= aux_stride;
 	intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
 
 	if (icl_is_hdr_plane(dev_priv, plane_id))
@@ -690,6 +737,9 @@ skl_program_plane(struct intel_plane *plane,
 		intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
 				  (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x);
 
+	if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
+		intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
+
 	/*
 	 * The control register self-arms if the plane was previously
 	 * disabled. Try to make the plane enable atomic by writing
@@ -2842,8 +2892,8 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
 					enum plane_id plane_id)
 {
-	/* Wa_14010477008:tgl[a0..c0],rkl[all] */
-	if (IS_ROCKETLAKE(dev_priv) ||
+	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
+	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
 	    IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
 		return false;
 
@@ -3089,6 +3139,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 	plane->get_hw_state = skl_plane_get_hw_state;
 	plane->check_plane = skl_plane_check;
 	plane->min_cdclk = skl_plane_min_cdclk;
+	plane->async_flip = skl_plane_async_flip;
 
 	if (INTEL_GEN(dev_priv) >= 11)
 		formats = icl_get_plane_formats(dev_priv, pipe,
@@ -3160,6 +3211,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 	if (INTEL_GEN(dev_priv) >= 12)
 		drm_plane_enable_fb_damage_clips(&plane->base);
 
+	if (INTEL_GEN(dev_priv) >= 10)
+		drm_plane_create_scaling_filter_property(&plane->base,
+						BIT(DRM_SCALING_FILTER_DEFAULT) |
+						BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
+
 	drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
 
 	return plane;
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 8f67aef18b2d..4346bc1a747a 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -228,9 +228,9 @@ static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
 		return;
 
 	/* If live status mismatches the VBT flag, trust the live status. */
-	drm_err(&i915->drm,
-		"Port %s: live status %08x mismatches the legacy port flag, fix flag\n",
-		dig_port->tc_port_name, live_status_mask);
+	drm_dbg_kms(&i915->drm,
+		    "Port %s: live status %08x mismatches the legacy port flag %08x, fixing flag\n",
+		    dig_port->tc_port_name, live_status_mask, valid_hpd_mask);
 
 	dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
 }
@@ -652,7 +652,7 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
 	enum port port = dig_port->base.port;
 	enum tc_port tc_port = intel_port_to_tc(i915, port);
 
-	if (drm_WARN_ON(&i915->drm, tc_port == PORT_TC_NONE))
+	if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
 		return;
 
 	snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 54bcc6a6947c..49b4b5fca941 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -782,7 +782,7 @@ struct lfp_backlight_data_entry {
 	u8 active_low_pwm:1;
 	u8 obsolete1:5;
 	u16 pwm_freq_hz;
-	u8 min_brightness;
+	u8 min_brightness; /* Obsolete from 234+ */
 	u8 obsolete2;
 	u8 obsolete3;
 } __packed;
@@ -792,11 +792,19 @@ struct lfp_backlight_control_method {
 	u8 controller:4;
 } __packed;
 
+struct lfp_brightness_level {
+	u16 level;
+	u16 reserved;
+} __packed;
+
 struct bdb_lfp_backlight_data {
 	u8 entry_size;
 	struct lfp_backlight_data_entry data[16];
-	u8 level[16];
+	u8 level[16]; /* Obsolete from 234+ */
 	struct lfp_backlight_control_method backlight_control[16];
+	struct lfp_brightness_level brightness_level[16];		/* 234+ */
+	struct lfp_brightness_level brightness_min_level[16];	/* 234+ */
+	u8 brightness_precision_bits[16];						/* 236+ */
 } __packed;
 
 /*
@@ -827,6 +835,7 @@ struct bdb_lfp_power {
 	u16 lace_enabled_status;
 	struct agressiveness_profile_entry aggressivenes[16];
 	u16 hobl; /* 232+ */
+	u16 vrr_feature_enabled; /* 233+ */
 } __packed;
 
 /*
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 5e5522923b1e..d52f9c177908 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -985,6 +985,13 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state,
 	intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
 }
 
+static void intel_dsi_shutdown(struct intel_encoder *encoder)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+
+	intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
+}
+
 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 				   enum pipe *pipe)
 {
@@ -1843,6 +1850,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
 	intel_encoder->get_hw_state = intel_dsi_get_hw_state;
 	intel_encoder->get_config = intel_dsi_get_config;
 	intel_encoder->update_pipe = intel_panel_update_backlight;
+	intel_encoder->shutdown = intel_dsi_shutdown;
 
 	intel_connector->get_hw_state = intel_connector_get_hw_state;
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 7c90a63c273d..fcce6909f201 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -509,21 +509,6 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 		return -ENOENT;
 
 	/*
-	 * Already in the desired write domain? Nothing for us to do!
-	 *
-	 * We apply a little bit of cunning here to catch a broader set of
-	 * no-ops. If obj->write_domain is set, we must be in the same
-	 * obj->read_domains, and only that domain. Therefore, if that
-	 * obj->write_domain matches the request read_domains, we are
-	 * already in the same read/write domain and can skip the operation,
-	 * without having to further check the requested write_domain.
-	 */
-	if (READ_ONCE(obj->write_domain) == read_domains) {
-		err = 0;
-		goto out;
-	}
-
-	/*
 	 * Try to flush the object off the GPU without holding the lock.
 	 * We will repeat the flush holding the lock in the normal manner
 	 * to catch cases where we are gazumped.
@@ -560,6 +545,19 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 	if (err)
 		goto out;
 
+	/*
+	 * Already in the desired write domain? Nothing for us to do!
+	 *
+	 * We apply a little bit of cunning here to catch a broader set of
+	 * no-ops. If obj->write_domain is set, we must be in the same
+	 * obj->read_domains, and only that domain. Therefore, if that
+	 * obj->write_domain matches the request read_domains, we are
+	 * already in the same read/write domain and can skip the operation,
+	 * without having to further check the requested write_domain.
+	 */
+	if (READ_ONCE(obj->write_domain) == read_domains)
+		goto out_unpin;
+
 	err = i915_gem_object_lock_interruptible(obj, NULL);
 	if (err)
 		goto out_unpin;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 7c3a1012e702..760fefdfe392 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -245,22 +245,14 @@ static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u
 }
 
 static inline u32 *
-__gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
+__gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)
 {
-	/* We're using qword write, offset should be aligned to 8 bytes. */
-	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
-
-	/* w/a for post sync ops following a GPGPU operation we
-	 * need a prior CS_STALL, which is emitted by the flush
-	 * following the batch.
-	 */
 	*cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
-	*cs++ = flags1 | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
-	*cs++ = gtt_offset;
+	*cs++ = flags1 | PIPE_CONTROL_QW_WRITE;
+	*cs++ = offset;
 	*cs++ = 0;
 	*cs++ = value;
-	/* We're thrashing one dword of HWS. */
-	*cs++ = 0;
+	*cs++ = 0; /* We're thrashing one extra dword. */
 
 	return cs;
 }
@@ -268,13 +260,38 @@ __gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 f
 static inline u32*
 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
 {
-	return __gen8_emit_ggtt_write_rcs(cs, value, gtt_offset, 0, flags);
+	/* We're using qword write, offset should be aligned to 8 bytes. */
+	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
+
+	return __gen8_emit_write_rcs(cs,
+				     value,
+				     gtt_offset,
+				     0,
+				     flags | PIPE_CONTROL_GLOBAL_GTT_IVB);
 }
 
 static inline u32*
 gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
 {
-	return __gen8_emit_ggtt_write_rcs(cs, value, gtt_offset, flags0, flags1);
+	/* We're using qword write, offset should be aligned to 8 bytes. */
+	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
+
+	return __gen8_emit_write_rcs(cs,
+				     value,
+				     gtt_offset,
+				     flags0,
+				     flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB);
+}
+
+static inline u32 *
+__gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
+{
+	*cs++ = (MI_FLUSH_DW + 1) | flags;
+	*cs++ = gtt_offset;
+	*cs++ = 0;
+	*cs++ = value;
+
+	return cs;
 }
 
 static inline u32 *
@@ -285,12 +302,10 @@ gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
 	/* Offset should be aligned to 8 bytes for both (QW/DW) write types */
 	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
 
-	*cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW | flags;
-	*cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;
-	*cs++ = 0;
-	*cs++ = value;
-
-	return cs;
+	return __gen8_emit_flush_dw(cs,
+				    value,
+				    gtt_offset | MI_FLUSH_DW_USE_GTT,
+				    flags | MI_FLUSH_DW_OP_STOREDW);
 }
 
 static inline void __intel_engine_reset(struct intel_engine_cs *engine,
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 81c05f551b9c..188a5f70177d 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -835,7 +835,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
 	u16 snb_gmch_ctl;
 
 	/* TODO: We're not aware of mappable constraints on gen8 yet */
-	if (!IS_DGFX(i915)) {
+	if (!HAS_LMEM(i915)) {
 		ggtt->gmadr = pci_resource(pdev, 2);
 		ggtt->mappable_end = resource_size(&ggtt->gmadr);
 	}
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a32aabce7901..f82c6dd1de18 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3547,6 +3547,19 @@ static const struct intel_context_ops execlists_context_ops = {
 	.destroy = execlists_context_destroy,
 };
 
+static u32 hwsp_offset(const struct i915_request *rq)
+{
+	const struct intel_timeline_cacheline *cl;
+
+	/* Before the request is executed, the timeline/cachline is fixed */
+
+	cl = rcu_dereference_protected(rq->hwsp_cacheline, 1);
+	if (cl)
+		return cl->ggtt_offset;
+
+	return rcu_dereference_protected(rq->timeline, 1)->hwsp_offset;
+}
+
 static int gen8_emit_init_breadcrumb(struct i915_request *rq)
 {
 	u32 *cs;
@@ -3569,7 +3582,7 @@ static int gen8_emit_init_breadcrumb(struct i915_request *rq)
 	*cs++ = MI_NOOP;
 
 	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
-	*cs++ = i915_request_timeline(rq)->hwsp_offset;
+	*cs++ = hwsp_offset(rq);
 	*cs++ = 0;
 	*cs++ = rq->fence.seqno - 1;
 
@@ -4886,11 +4899,9 @@ gen8_emit_fini_breadcrumb_tail(struct i915_request *request, u32 *cs)
 	return gen8_emit_wa_tail(request, cs);
 }
 
-static u32 *emit_xcs_breadcrumb(struct i915_request *request, u32 *cs)
+static u32 *emit_xcs_breadcrumb(struct i915_request *rq, u32 *cs)
 {
-	u32 addr = i915_request_active_timeline(request)->hwsp_offset;
-
-	return gen8_emit_ggtt_write(cs, request->fence.seqno, addr, 0);
+	return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
 }
 
 static u32 *gen8_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
@@ -4909,7 +4920,7 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
 	/* XXX flush+write+CS_STALL all in one upsets gem_concurrent_blt:kbl */
 	cs = gen8_emit_ggtt_write_rcs(cs,
 				      request->fence.seqno,
-				      i915_request_active_timeline(request)->hwsp_offset,
+				      hwsp_offset(request),
 				      PIPE_CONTROL_FLUSH_ENABLE |
 				      PIPE_CONTROL_CS_STALL);
 
@@ -4921,7 +4932,7 @@ gen11_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
 {
 	cs = gen8_emit_ggtt_write_rcs(cs,
 				      request->fence.seqno,
-				      i915_request_active_timeline(request)->hwsp_offset,
+				      hwsp_offset(request),
 				      PIPE_CONTROL_CS_STALL |
 				      PIPE_CONTROL_TILE_CACHE_FLUSH |
 				      PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
@@ -4983,7 +4994,9 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *request, u32 *cs)
 
 static u32 *gen12_emit_fini_breadcrumb(struct i915_request *rq, u32 *cs)
 {
-	return gen12_emit_fini_breadcrumb_tail(rq, emit_xcs_breadcrumb(rq, cs));
+	/* XXX Stalling flush before seqno write; post-sync not */
+	cs = emit_xcs_breadcrumb(rq, __gen8_emit_flush_dw(cs, 0, 0, 0));
+	return gen12_emit_fini_breadcrumb_tail(rq, cs);
 }
 
 static u32 *
@@ -4991,7 +5004,7 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
 {
 	cs = gen12_emit_ggtt_write_rcs(cs,
 				       request->fence.seqno,
-				       i915_request_active_timeline(request)->hwsp_offset,
+				       hwsp_offset(request),
 				       PIPE_CONTROL0_HDC_PIPELINE_FLUSH,
 				       PIPE_CONTROL_CS_STALL |
 				       PIPE_CONTROL_TILE_CACHE_FLUSH |
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index b8f56e62158e..39179a3eee98 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -109,7 +109,7 @@ struct drm_i915_mocs_table {
  * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
  * PTE and will be initialized to an invalid value.
  *
- * The last two entries are reserved by the hardware. For ICL+ they
+ * The last few entries are reserved by the hardware. For ICL+ they
  * should be initialized according to bspec and never used, for older
  * platforms they should never be written to.
  *
@@ -286,6 +286,39 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
 	GEN11_MOCS_ENTRIES
 };
 
+static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
+	/* Error */
+	MOCS_ENTRY(0, 0, L3_0_DIRECT),
+
+	/* UC */
+	MOCS_ENTRY(1, 0, L3_1_UC),
+
+	/* Reserved */
+	MOCS_ENTRY(2, 0, L3_0_DIRECT),
+	MOCS_ENTRY(3, 0, L3_0_DIRECT),
+	MOCS_ENTRY(4, 0, L3_0_DIRECT),
+
+	/* WB - L3 */
+	MOCS_ENTRY(5, 0, L3_3_WB),
+	/* WB - L3 50% */
+	MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
+	/* WB - L3 25% */
+	MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
+	/* WB - L3 12.5% */
+	MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
+
+	/* HDC:L1 + L3 */
+	MOCS_ENTRY(48, 0, L3_3_WB),
+	/* HDC:L1 */
+	MOCS_ENTRY(49, 0, L3_1_UC),
+
+	/* HW Reserved */
+	MOCS_ENTRY(60, 0, L3_1_UC),
+	MOCS_ENTRY(61, 0, L3_1_UC),
+	MOCS_ENTRY(62, 0, L3_1_UC),
+	MOCS_ENTRY(63, 0, L3_1_UC),
+};
+
 enum {
 	HAS_GLOBAL_MOCS = BIT(0),
 	HAS_ENGINE_MOCS = BIT(1),
@@ -312,7 +345,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 {
 	unsigned int flags;
 
-	if (INTEL_GEN(i915) >= 12) {
+	if (IS_DG1(i915)) {
+		table->size = ARRAY_SIZE(dg1_mocs_table);
+		table->table = dg1_mocs_table;
+		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
+	} else if (INTEL_GEN(i915) >= 12) {
 		table->size  = ARRAY_SIZE(tgl_mocs_table);
 		table->table = tgl_mocs_table;
 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index e6a00eea0631..466ec671b379 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -390,6 +390,16 @@ static void gen5_rps_update(struct intel_rps *rps)
 	spin_unlock_irq(&mchdev_lock);
 }
 
+static unsigned int gen5_invert_freq(struct intel_rps *rps,
+				     unsigned int val)
+{
+	/* Invert the frequency bin into an ips delay */
+	val = rps->max_freq - val;
+	val = rps->min_freq + val;
+
+	return val;
+}
+
 static bool gen5_rps_set(struct intel_rps *rps, u8 val)
 {
 	struct intel_uncore *uncore = rps_to_uncore(rps);
@@ -404,8 +414,7 @@ static bool gen5_rps_set(struct intel_rps *rps, u8 val)
 	}
 
 	/* Invert the frequency bin into an ips delay */
-	val = rps->max_freq - val;
-	val = rps->min_freq + val;
+	val = gen5_invert_freq(rps, val);
 
 	rgvswctl =
 		(MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
@@ -500,6 +509,7 @@ static unsigned int init_emon(struct intel_uncore *uncore)
 
 static bool gen5_rps_enable(struct intel_rps *rps)
 {
+	struct drm_i915_private *i915 = rps_to_i915(rps);
 	struct intel_uncore *uncore = rps_to_uncore(rps);
 	u8 fstart, vstart;
 	u32 rgvmodectl;
@@ -557,6 +567,10 @@ static bool gen5_rps_enable(struct intel_rps *rps)
 	rps->ips.last_count2 = intel_uncore_read(uncore, GFXEC);
 	rps->ips.last_time2 = ktime_get_raw_ns();
 
+	spin_lock(&i915->irq_lock);
+	ilk_enable_display_irq(i915, DE_PCU_EVENT);
+	spin_unlock(&i915->irq_lock);
+
 	spin_unlock_irq(&mchdev_lock);
 
 	rps->ips.corr = init_emon(uncore);
@@ -566,11 +580,16 @@ static bool gen5_rps_enable(struct intel_rps *rps)
 
 static void gen5_rps_disable(struct intel_rps *rps)
 {
+	struct drm_i915_private *i915 = rps_to_i915(rps);
 	struct intel_uncore *uncore = rps_to_uncore(rps);
 	u16 rgvswctl;
 
 	spin_lock_irq(&mchdev_lock);
 
+	spin_lock(&i915->irq_lock);
+	ilk_disable_display_irq(i915, DE_PCU_EVENT);
+	spin_unlock(&i915->irq_lock);
+
 	rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
 
 	/* Ack interrupts, disable EFC interrupt */
@@ -578,11 +597,6 @@ static void gen5_rps_disable(struct intel_rps *rps)
 			   intel_uncore_read(uncore, MEMINTREN) &
 			   ~MEMINT_EVAL_CHG_EN);
 	intel_uncore_write(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
-	intel_uncore_write(uncore, DEIER,
-			   intel_uncore_read(uncore, DEIER) & ~DE_PCU_EVENT);
-	intel_uncore_write(uncore, DEIIR, DE_PCU_EVENT);
-	intel_uncore_write(uncore, DEIMR,
-			   intel_uncore_read(uncore, DEIMR) | DE_PCU_EVENT);
 
 	/* Go back to the starting frequency */
 	gen5_rps_set(rps, rps->idle_freq);
@@ -1272,8 +1286,9 @@ static unsigned long __ips_gfx_val(struct intel_ips *ips)
 {
 	struct intel_rps *rps = container_of(ips, typeof(*rps), ips);
 	struct intel_uncore *uncore = rps_to_uncore(rps);
-	unsigned long t, corr, state1, corr2, state2;
+	unsigned int t, state1, state2;
 	u32 pxvid, ext_v;
+	u64 corr, corr2;
 
 	lockdep_assert_held(&mchdev_lock);
 
@@ -1294,11 +1309,10 @@ static unsigned long __ips_gfx_val(struct intel_ips *ips)
 	else /* < 50 */
 		corr = t * 301 + 1004;
 
-	corr = corr * 150142 * state1 / 10000 - 78642;
-	corr /= 100000;
-	corr2 = corr * ips->corr;
+	corr = div_u64(corr * 150142 * state1, 10000) - 78642;
+	corr2 = div_u64(corr, 100000) * ips->corr;
 
-	state2 = corr2 * state1 / 10000;
+	state2 = div_u64(corr2 * state1, 10000);
 	state2 /= 100; /* convert to mW */
 
 	__gen5_ips_update(ips);
@@ -1432,8 +1446,10 @@ int intel_gpu_freq(struct intel_rps *rps, int val)
 		return chv_gpu_freq(rps, val);
 	else if (IS_VALLEYVIEW(i915))
 		return byt_gpu_freq(rps, val);
-	else
+	else if (INTEL_GEN(i915) >= 6)
 		return val * GT_FREQUENCY_MULTIPLIER;
+	else
+		return val;
 }
 
 int intel_freq_opcode(struct intel_rps *rps, int val)
@@ -1447,8 +1463,10 @@ int intel_freq_opcode(struct intel_rps *rps, int val)
 		return chv_freq_opcode(rps, val);
 	else if (IS_VALLEYVIEW(i915))
 		return byt_freq_opcode(rps, val);
-	else
+	else if (INTEL_GEN(i915) >= 6)
 		return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
+	else
+		return val;
 }
 
 static void vlv_init_gpll_ref_freq(struct intel_rps *rps)
@@ -1864,8 +1882,11 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
 		cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
 	else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
 		cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
-	else
+	else if (INTEL_GEN(i915) >= 6)
 		cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
+	else
+		cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
+					MEMSTAT_PSTATE_SHIFT);
 
 	return cagf;
 }
@@ -1873,14 +1894,17 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
 static u32 read_cagf(struct intel_rps *rps)
 {
 	struct drm_i915_private *i915 = rps_to_i915(rps);
+	struct intel_uncore *uncore = rps_to_uncore(rps);
 	u32 freq;
 
 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
 		vlv_punit_get(i915);
 		freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
 		vlv_punit_put(i915);
+	} else if (INTEL_GEN(i915) >= 6) {
+		freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
 	} else {
-		freq = intel_uncore_read(rps_to_uncore(rps), GEN6_RPSTAT1);
+		freq = intel_uncore_read(uncore, MEMSTAT_ILK);
 	}
 
 	return intel_rps_get_cagf(rps, freq);
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index f1c039e1b5ad..8a72e0fe34ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -169,7 +169,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
 	u8 eu_en;
 	u8 s_en;
 
-	if (IS_ELKHARTLAKE(gt->i915))
+	if (IS_JSL_EHL(gt->i915))
 		intel_sseu_set_info(sseu, 1, 4, 8);
 	else
 		intel_sseu_set_info(sseu, 1, 8, 8);
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index a2f74cefe4c3..7ea94d201fe6 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -188,10 +188,14 @@ cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline)
 	return cl;
 }
 
-static void cacheline_acquire(struct intel_timeline_cacheline *cl)
+static void cacheline_acquire(struct intel_timeline_cacheline *cl,
+			      u32 ggtt_offset)
 {
-	if (cl)
-		i915_active_acquire(&cl->active);
+	if (!cl)
+		return;
+
+	cl->ggtt_offset = ggtt_offset;
+	i915_active_acquire(&cl->active);
 }
 
 static void cacheline_release(struct intel_timeline_cacheline *cl)
@@ -340,7 +344,7 @@ int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww)
 	GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
 		 tl->fence_context, tl->hwsp_offset);
 
-	cacheline_acquire(tl->hwsp_cacheline);
+	cacheline_acquire(tl->hwsp_cacheline, tl->hwsp_offset);
 	if (atomic_fetch_inc(&tl->pin_count)) {
 		cacheline_release(tl->hwsp_cacheline);
 		__i915_vma_unpin(tl->hwsp_ggtt);
@@ -515,7 +519,7 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
 	GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
 		 tl->fence_context, tl->hwsp_offset);
 
-	cacheline_acquire(cl);
+	cacheline_acquire(cl, tl->hwsp_offset);
 	tl->hwsp_cacheline = cl;
 
 	*seqno = timeline_advance(tl);
@@ -573,9 +577,7 @@ int intel_timeline_read_hwsp(struct i915_request *from,
 	if (err)
 		goto out;
 
-	*hwsp = i915_ggtt_offset(cl->hwsp->vma) +
-		ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) * CACHELINE_BYTES;
-
+	*hwsp = cl->ggtt_offset;
 out:
 	i915_active_release(&cl->active);
 	return err;
diff --git a/drivers/gpu/drm/i915/gt/intel_timeline_types.h b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
index 02181c5020db..4474f487f589 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_timeline_types.h
@@ -94,6 +94,8 @@ struct intel_timeline_cacheline {
 	struct intel_timeline_hwsp *hwsp;
 	void *vaddr;
 
+	u32 ggtt_offset;
+
 	struct rcu_head rcu;
 };
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6c580d0d9ea8..fed9503a7c4e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -672,6 +672,20 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	       0);
 }
 
+static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
+				     struct i915_wa_list *wal)
+{
+	gen12_ctx_workarounds_init(engine, wal);
+
+	/* Wa_1409044764 */
+	WA_CLR_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+			  DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN);
+
+	/* Wa_22010493298 */
+	WA_SET_BIT_MASKED(HIZ_CHICKEN,
+			  DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
+}
+
 static void
 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 			   struct i915_wa_list *wal,
@@ -684,7 +698,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 
 	wa_init_start(wal, name, engine->name);
 
-	if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
+	if (IS_DG1(i915))
+		dg1_ctx_workarounds_init(engine, wal);
+	else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
 		tgl_ctx_workarounds_init(engine, wal);
 	else if (IS_GEN(i915, 12))
 		gen12_ctx_workarounds_init(engine, wal);
@@ -1212,7 +1228,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 
 	/* Wa_1607087056:icl,ehl,jsl */
 	if (IS_ICELAKE(i915) ||
-	    IS_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) {
+		IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) {
 		wa_write_or(wal,
 			    SLICE_UNIT_LEVEL_CLKGATE,
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
@@ -1245,9 +1261,35 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 }
 
 static void
+dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+	gen12_gt_workarounds_init(i915, wal);
+
+	/* Wa_1607087056:dg1 */
+	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
+		wa_write_or(wal,
+			    SLICE_UNIT_LEVEL_CLKGATE,
+			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+
+	/* Wa_1409420604:dg1 */
+	if (IS_DG1(i915))
+		wa_write_or(wal,
+			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
+			    CPSSUNIT_CLKGATE_DIS);
+
+	/* Wa_1408615072:dg1 */
+	/* Empirical testing shows this register is unaffected by engine reset. */
+	if (IS_DG1(i915))
+		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
+			    VSUNIT_CLKGATE_DIS_TGL);
+}
+
+static void
 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-	if (IS_TIGERLAKE(i915))
+	if (IS_DG1(i915))
+		dg1_gt_workarounds_init(i915, wal);
+	else if (IS_TIGERLAKE(i915))
 		tgl_gt_workarounds_init(i915, wal);
 	else if (IS_GEN(i915, 12))
 		gen12_gt_workarounds_init(i915, wal);
@@ -1612,6 +1654,20 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
 	}
 }
 
+static void dg1_whitelist_build(struct intel_engine_cs *engine)
+{
+	struct i915_wa_list *w = &engine->whitelist;
+
+	tgl_whitelist_build(engine);
+
+	/* GEN:BUG:1409280441:dg1 */
+	if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
+	    (engine->class == RENDER_CLASS ||
+	     engine->class == COPY_ENGINE_CLASS))
+		whitelist_reg_ext(w, RING_ID(engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
+}
+
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *i915 = engine->i915;
@@ -1619,7 +1675,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 
 	wa_init_start(w, "whitelist", engine->name);
 
-	if (IS_GEN(i915, 12))
+	if (IS_DG1(i915))
+		dg1_whitelist_build(engine);
+	else if (IS_GEN(i915, 12))
 		tgl_whitelist_build(engine);
 	else if (IS_GEN(i915, 11))
 		icl_whitelist_build(engine);
@@ -1673,15 +1731,18 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+	    IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
 		/*
-		 * Wa_1607138336:tgl
-		 * Wa_1607063988:tgl
+		 * Wa_1607138336:tgl[a0],dg1[a0]
+		 * Wa_1607063988:tgl[a0],dg1[a0]
 		 */
 		wa_write_or(wal,
 			    GEN9_CTX_PREEMPT_REG,
 			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
+	}
 
+	if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
 		/*
 		 * Wa_1606679103:tgl
 		 * (see also Wa_1606682166:icl)
@@ -1695,35 +1756,41 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    VSUNIT_CLKGATE_DIS_TGL);
 	}
 
-	if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-		/* Wa_1606931601:tgl,rkl */
+	if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+		/* Wa_1606931601:tgl,rkl,dg1 */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
 
-		/* Wa_1409804808:tgl,rkl */
+		/*
+		 * Wa_1407928979:tgl A*
+		 * Wa_18011464164:tgl[B0+],dg1[B0+]
+		 * Wa_22010931296:tgl[B0+],dg1[B0+]
+		 * Wa_14010919138:rkl, dg1
+		 */
+		wa_write_or(wal, GEN7_FF_THREAD_MODE,
+			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
+	}
+
+	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+		/* Wa_1409804808:tgl,rkl,dg1[a0] */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
 			     GEN12_PUSH_CONST_DEREF_HOLD_DIS);
 
 		/*
 		 * Wa_1409085225:tgl
-		 * Wa_14010229206:tgl,rkl
+		 * Wa_14010229206:tgl,rkl,dg1[a0]
 		 */
 		wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
 
 		/*
-		 * Wa_1407928979:tgl A*
-		 * Wa_18011464164:tgl B0+
-		 * Wa_22010931296:tgl B0+
-		 * Wa_14010919138:rkl,tgl
-		 */
-		wa_write_or(wal, GEN7_FF_THREAD_MODE,
-			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
-
-		/*
 		 * Wa_1607030317:tgl
 		 * Wa_1607186500:tgl
-		 * Wa_1607297627:tgl,rkl there are multiple entries for this
-		 * WA in the BSpec; some indicate this is an A0-only WA,
-		 * others indicate it applies to all steppings.
+		 * Wa_1607297627:tgl,rkl,dg1[a0]
+		 *
+		 * On TGL and RKL there are multiple entries for this WA in the
+		 * BSpec; some indicate this is an A0-only WA, others indicate
+		 * it applies to all steppings so we trust the "all steppings."
+		 * For DG1 this only applies to A0.
 		 */
 		wa_masked_en(wal,
 			     GEN6_RC_SLEEP_PSMI_CONTROL,
@@ -1839,7 +1906,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
 		/* Wa_22010271021:ehl */
-		if (IS_ELKHARTLAKE(i915))
+		if (IS_JSL_EHL(i915))
 			wa_masked_en(wal,
 				     GEN9_CS_DEBUG_MODE1,
 				     FF_DOP_CLOCK_GATE_DISABLE);
@@ -2031,10 +2098,12 @@ err_obj:
 	return ERR_PTR(err);
 }
 
-static const struct {
+struct mcr_range {
 	u32 start;
 	u32 end;
-} mcr_ranges_gen8[] = {
+};
+
+static const struct mcr_range mcr_ranges_gen8[] = {
 	{ .start = 0x5500, .end = 0x55ff },
 	{ .start = 0x7000, .end = 0x7fff },
 	{ .start = 0x9400, .end = 0x97ff },
@@ -2043,11 +2112,25 @@ static const struct {
 	{},
 };
 
+static const struct mcr_range mcr_ranges_gen12[] = {
+	{ .start =  0x8150, .end =  0x815f },
+	{ .start =  0x9520, .end =  0x955f },
+	{ .start =  0xb100, .end =  0xb3ff },
+	{ .start =  0xde80, .end =  0xe8ff },
+	{ .start = 0x24a00, .end = 0x24a7f },
+	{},
+};
+
 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
 {
+	const struct mcr_range *mcr_ranges;
 	int i;
 
-	if (INTEL_GEN(i915) < 8)
+	if (INTEL_GEN(i915) >= 12)
+		mcr_ranges = mcr_ranges_gen12;
+	else if (INTEL_GEN(i915) >= 8)
+		mcr_ranges = mcr_ranges_gen8;
+	else
 		return false;
 
 	/*
@@ -2055,9 +2138,9 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
 	 * which only controls CPU initiated MMIO. Routing does not
 	 * work for CS access so we cannot verify them on this path.
 	 */
-	for (i = 0; mcr_ranges_gen8[i].start; i++)
-		if (offset >= mcr_ranges_gen8[i].start &&
-		    offset <= mcr_ranges_gen8[i].end)
+	for (i = 0; mcr_ranges[i].start; i++)
+		if (offset >= mcr_ranges[i].start &&
+		    offset <= mcr_ranges[i].end)
 			return true;
 
 	return false;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 942c7c187adb..e4aaa5f29796 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -312,18 +312,18 @@ void intel_guc_write_params(struct intel_guc *guc)
 	int i;
 
 	/*
-	 * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
+	 * All SOFT_SCRATCH registers are in FORCEWAKE_GT domain and
 	 * they are power context saved so it's ok to release forcewake
 	 * when we are done here and take it again at xfer time.
 	 */
-	intel_uncore_forcewake_get(uncore, FORCEWAKE_BLITTER);
+	intel_uncore_forcewake_get(uncore, FORCEWAKE_GT);
 
 	intel_uncore_write(uncore, SOFT_SCRATCH(0), 0);
 
 	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 		intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]);
 
-	intel_uncore_forcewake_put(uncore, FORCEWAKE_BLITTER);
+	intel_uncore_forcewake_put(uncore, FORCEWAKE_GT);
 }
 
 int intel_guc_init(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 80e8b6c3bc8c..037bcaf3c8b5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -53,6 +53,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
 	fw_def(ROCKETLAKE,  0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 5, 0)) \
 	fw_def(TIGERLAKE,   0, guc_def(tgl, 35, 2, 0), huc_def(tgl,  7, 5, 0)) \
+	fw_def(JASPERLAKE,  0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9, 0, 0)) \
 	fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl,  9, 0, 0)) \
 	fw_def(ICELAKE,     0, guc_def(icl, 33, 0, 0), huc_def(icl,  9, 0, 0)) \
 	fw_def(COMETLAKE,   5, guc_def(cml, 33, 0, 0), huc_def(cml,  4, 0, 0)) \
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 7ba16ddfe75f..5b5c71a0b4af 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -173,23 +173,24 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 	int pipe;
 
 	if (IS_BROXTON(dev_priv)) {
-		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
-			BXT_DE_PORT_HP_DDIB |
-			BXT_DE_PORT_HP_DDIC);
+		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
+			~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
+			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
+			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDIA;
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
 		}
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDIB;
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
 		}
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDIC;
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
 		}
 
 		return;
@@ -327,7 +328,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 		if (IS_BROADWELL(dev_priv))
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				GEN8_PORT_DP_A_HOTPLUG;
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
 		else
 			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
 
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 3be37e6fe33d..ce93079cf933 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -290,8 +290,8 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu,
 		case FORCEWAKE_RENDER_GEN9_REG:
 			ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
 			break;
-		case FORCEWAKE_BLITTER_GEN9_REG:
-			ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
+		case FORCEWAKE_GT_GEN9_REG:
+			ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG;
 			break;
 		case FORCEWAKE_MEDIA_GEN9_REG:
 			ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
@@ -1489,7 +1489,8 @@ static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
 	const struct intel_engine_cs *engine =
 		intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
 
-	if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
+	if (value != 0 &&
+	    !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
 		gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
 			      offset, value);
 		return -EINVAL;
@@ -1650,6 +1651,34 @@ static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
 	return 0;
 }
 
+/**
+ * FixMe:
+ * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did:
+ * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.)
+ * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing
+ * these MI_BATCH_BUFFER.
+ * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
+ * PML4 PTE: PAT(0) PCD(1) PWT(1).
+ * The performance is still expected to be low, will need further improvement.
+ */
+static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset,
+			      void *p_data, unsigned int bytes)
+{
+	u64 pat =
+		GEN8_PPAT(0, CHV_PPAT_SNOOP) |
+		GEN8_PPAT(1, 0) |
+		GEN8_PPAT(2, 0) |
+		GEN8_PPAT(3, CHV_PPAT_SNOOP) |
+		GEN8_PPAT(4, CHV_PPAT_SNOOP) |
+		GEN8_PPAT(5, CHV_PPAT_SNOOP) |
+		GEN8_PPAT(6, CHV_PPAT_SNOOP) |
+		GEN8_PPAT(7, CHV_PPAT_SNOOP);
+
+	vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
+
+	return 0;
+}
+
 static int guc_status_read(struct intel_vgpu *vgpu,
 			   unsigned int offset, void *p_data,
 			   unsigned int bytes)
@@ -2209,9 +2238,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
 	MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
 
-	MMIO_D(WM0_PIPEA_ILK, D_ALL);
-	MMIO_D(WM0_PIPEB_ILK, D_ALL);
-	MMIO_D(WM0_PIPEC_IVB, D_ALL);
+	MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL);
+	MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL);
+	MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL);
 	MMIO_D(WM1_LP_ILK, D_ALL);
 	MMIO_D(WM2_LP_ILK, D_ALL);
 	MMIO_D(WM3_LP_ILK, D_ALL);
@@ -2812,7 +2841,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt)
 
 	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
 
-	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
+	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS & ~D_BXT);
 	MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
 
 	MMIO_D(GAMTARBMODE, D_BDW_PLUS);
@@ -2901,8 +2930,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
 
 	MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
 	MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
-	MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
-	MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
+	MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
+	MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
 	MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
 	MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
 
@@ -3139,7 +3168,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
 		 NULL, NULL);
 
 	MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
-	MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS);
+	MMIO_D(GEN9_CTX_PREEMPT_REG, D_SKL_PLUS & ~D_BXT);
 
 	return 0;
 }
@@ -3313,9 +3342,21 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
 	MMIO_D(GEN6_GFXPAUSE, D_BXT);
 	MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
+	MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
+	MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
+	MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+	       0, 0, D_BXT, NULL, NULL);
+	MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+	       0, 0, D_BXT, NULL, NULL);
+	MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+	       0, 0, D_BXT, NULL, NULL);
+	MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
+	       0, 0, D_BXT, NULL, NULL);
 
 	MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
 
+	MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index b88e033cbed4..b58860dee970 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -101,8 +101,8 @@
 
 #define FORCEWAKE_RENDER_GEN9_REG 0xa278
 #define FORCEWAKE_ACK_RENDER_GEN9_REG 0x0D84
-#define FORCEWAKE_BLITTER_GEN9_REG 0xa188
-#define FORCEWAKE_ACK_BLITTER_GEN9_REG 0x130044
+#define FORCEWAKE_GT_GEN9_REG 0xa188
+#define FORCEWAKE_ACK_GT_GEN9_REG 0x130044
 #define FORCEWAKE_MEDIA_GEN9_REG 0xa270
 #define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88
 #define FORCEWAKE_ACK_HSW_REG 0x130044
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 1570eb8aa978..aed2ef6466a2 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1277,7 +1277,7 @@ void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
 
 	i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm));
 	for_each_engine(engine, vgpu->gvt->gt, id)
-		intel_context_unpin(s->shadow[id]);
+		intel_context_put(s->shadow[id]);
 
 	kmem_cache_destroy(s->workloads);
 }
@@ -1369,11 +1369,6 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
 			ce->ring = __intel_context_ring_size(ring_size);
 		}
 
-		ret = intel_context_pin(ce);
-		intel_context_put(ce);
-		if (ret)
-			goto out_shadow_ctx;
-
 		s->shadow[i] = ce;
 	}
 
@@ -1405,7 +1400,6 @@ out_shadow_ctx:
 		if (IS_ERR(s->shadow[i]))
 			break;
 
-		intel_context_unpin(s->shadow[i]);
 		intel_context_put(s->shadow[i]);
 	}
 	i915_vm_put(&ppgtt->vm);
@@ -1479,6 +1473,7 @@ void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
 {
 	struct intel_vgpu_submission *s = &workload->vgpu->submission;
 
+	intel_context_unpin(s->shadow[workload->engine->id]);
 	release_shadow_batch_buffer(workload);
 	release_shadow_wa_ctx(&workload->wa_ctx);
 
@@ -1724,6 +1719,12 @@ intel_vgpu_create_workload(struct intel_vgpu *vgpu,
 		return ERR_PTR(ret);
 	}
 
+	ret = intel_context_pin(s->shadow[engine->id]);
+	if (ret) {
+		intel_vgpu_destroy_workload(workload);
+		return ERR_PTR(ret);
+	}
+
 	return workload;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ea469168cd44..200f6b86f864 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -786,7 +786,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 	struct intel_uncore *uncore = &dev_priv->uncore;
 	struct intel_rps *rps = &dev_priv->gt.rps;
 	intel_wakeref_t wakeref;
-	int ret = 0;
 
 	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
@@ -1009,7 +1008,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 	seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
 
 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
-	return ret;
+	return 0;
 }
 
 static int i915_ring_freq_table(struct seq_file *m, void *unused)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b15d206dca3a..f2389ba49c69 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -84,6 +84,7 @@
 #include "intel_gvt.h"
 #include "intel_memory_region.h"
 #include "intel_pm.h"
+#include "intel_sideband.h"
 #include "vlv_suspend.h"
 
 static const struct drm_driver driver;
@@ -616,6 +617,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 	 */
 	intel_dram_detect(dev_priv);
 
+	intel_pcode_init(dev_priv);
+
 	intel_bw_init_hw(dev_priv);
 
 	return 0;
@@ -668,7 +671,8 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
 	/* Reveal our presence to userspace */
 	if (drm_dev_register(dev, 0) == 0) {
 		i915_debugfs_register(dev_priv);
-		intel_display_debugfs_register(dev_priv);
+		if (HAS_DISPLAY(dev_priv))
+			intel_display_debugfs_register(dev_priv);
 		i915_setup_sysfs(dev_priv);
 
 		/* Depends on sysfs having been initialized */
@@ -840,9 +844,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 		    i915->params.fake_lmem_start) {
 			mkwrite_device_info(i915)->memory_regions =
 				REGION_SMEM | REGION_LMEM | REGION_STOLEN;
-			mkwrite_device_info(i915)->is_dgfx = true;
 			GEM_BUG_ON(!HAS_LMEM(i915));
-			GEM_BUG_ON(!IS_DGFX(i915));
 		}
 	}
 #endif
@@ -1036,6 +1038,35 @@ static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 	drm_modeset_unlock_all(dev);
 }
 
+static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
+{
+	struct drm_device *dev = &dev_priv->drm;
+	struct intel_encoder *encoder;
+
+	drm_modeset_lock_all(dev);
+	for_each_intel_encoder(dev, encoder)
+		if (encoder->shutdown)
+			encoder->shutdown(encoder);
+	drm_modeset_unlock_all(dev);
+}
+
+void i915_driver_shutdown(struct drm_i915_private *i915)
+{
+	i915_gem_suspend(i915);
+
+	drm_kms_helper_poll_disable(&i915->drm);
+
+	drm_atomic_helper_shutdown(&i915->drm);
+
+	intel_dp_mst_suspend(i915);
+
+	intel_runtime_pm_disable_interrupts(i915);
+	intel_hpd_cancel_work(i915);
+
+	intel_suspend_encoders(i915);
+	intel_shutdown_encoders(i915);
+}
+
 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
 {
 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
@@ -1089,7 +1120,7 @@ static int i915_drm_suspend(struct drm_device *dev)
 
 	i915_ggtt_suspend(&dev_priv->ggtt);
 
-	i915_save_state(dev_priv);
+	i915_save_display(dev_priv);
 
 	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
 	intel_opregion_suspend(dev_priv, opregion_target_state);
@@ -1202,7 +1233,7 @@ static int i915_drm_resume(struct drm_device *dev)
 
 	intel_csr_ucode_resume(dev_priv);
 
-	i915_restore_state(dev_priv);
+	i915_restore_display(dev_priv);
 	intel_pps_unlock_regs_wa(dev_priv);
 
 	intel_init_pch_refclk(dev_priv);
@@ -1225,26 +1256,15 @@ static int i915_drm_resume(struct drm_device *dev)
 
 	intel_modeset_init_hw(dev_priv);
 	intel_init_clock_gating(dev_priv);
+	intel_hpd_init(dev_priv);
 
-	spin_lock_irq(&dev_priv->irq_lock);
-	if (dev_priv->display.hpd_irq_setup)
-		dev_priv->display.hpd_irq_setup(dev_priv);
-	spin_unlock_irq(&dev_priv->irq_lock);
-
+	/* MST sideband requires HPD interrupts enabled */
 	intel_dp_mst_resume(dev_priv);
-
 	intel_display_resume(dev);
 
+	intel_hpd_poll_disable(dev_priv);
 	drm_kms_helper_poll_enable(dev);
 
-	/*
-	 * ... but also need to make sure that hotplug processing
-	 * doesn't cause havoc. Like in the driver load code we don't
-	 * bother with the tiny race here where we might lose hotplug
-	 * notifications.
-	 * */
-	intel_hpd_init(dev_priv);
-
 	intel_opregion_resume(dev_priv);
 
 	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
@@ -1556,7 +1576,7 @@ static int intel_runtime_suspend(struct device *kdev)
 	assert_forcewakes_inactive(&dev_priv->uncore);
 
 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
-		intel_hpd_poll_init(dev_priv);
+		intel_hpd_poll_enable(dev_priv);
 
 	drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
 	return 0;
@@ -1601,8 +1621,10 @@ static int intel_runtime_resume(struct device *kdev)
 	 * power well, so hpd is reinitialized from there. For
 	 * everyone else do it here.
 	 */
-	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
+	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
 		intel_hpd_init(dev_priv);
+		intel_hpd_poll_disable(dev_priv);
+	}
 
 	intel_enable_ipc(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8426d5974669..d7765b31fbef 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -110,8 +110,8 @@
 
 #define DRIVER_NAME		"i915"
 #define DRIVER_DESC		"Intel Graphics"
-#define DRIVER_DATE		"20200917"
-#define DRIVER_TIMESTAMP	1600375437
+#define DRIVER_DATE		"20201103"
+#define DRIVER_TIMESTAMP	1604406085
 
 struct drm_i915_gem_object;
 
@@ -1419,7 +1419,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
 #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
-#define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
+#define IS_JSL_EHL(dev_priv)	(IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
+				IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
 #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
@@ -1560,8 +1561,8 @@ extern const struct i915_rev_steppings kbl_revids[];
 
 #define EHL_REVID_A0            0x0
 
-#define IS_EHL_REVID(p, since, until) \
-	(IS_ELKHARTLAKE(p) && IS_REVID(p, since, until))
+#define IS_JSL_EHL_REVID(p, since, until) \
+	(IS_JSL_EHL(p) && IS_REVID(p, since, until))
 
 enum {
 	TGL_REVID_A0,
@@ -1783,6 +1784,7 @@ extern const struct dev_pm_ops i915_pm_ops;
 
 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
 void i915_driver_remove(struct drm_i915_private *i915);
+void i915_driver_shutdown(struct drm_i915_private *i915);
 
 int i915_resume_switcheroo(struct drm_i915_private *i915);
 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 759f523c6a6b..e0eb32bd9607 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -61,6 +61,8 @@
  */
 
 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
+typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915,
+				    enum hpd_pin pin);
 
 static const u32 hpd_ilk[HPD_NUM_PINS] = {
 	[HPD_PORT_A] = DE_DP_A_HOTPLUG,
@@ -71,7 +73,7 @@ static const u32 hpd_ivb[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_bdw[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
+	[HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
 };
 
 static const u32 hpd_ibx[HPD_NUM_PINS] = {
@@ -126,30 +128,37 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_bxt[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
-	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
-	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
+	[HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
+	[HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
+	[HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
-	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1),
-	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2),
-	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3),
-	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4),
-	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5),
-	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6),
+	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
+	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
+	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
+	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
+	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
+	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
 };
 
 static const u32 hpd_icp[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
-	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
-	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
-	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
-	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
-	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
-	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
-	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
-	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
+	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
+	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
+	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
+	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
+	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
+	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
+	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
+	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
+	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
+};
+
+static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
+	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
+	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
+	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
+	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
 };
 
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -176,11 +185,14 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 	else
 		hpd->hpd = hpd_ilk;
 
-	if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
+	if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
+	    (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
 		return;
 
-	if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
-	    HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
+	if (HAS_PCH_DG1(dev_priv))
+		hpd->pch_hpd = hpd_sde_dg1;
+	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) ||
+		 HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
 		hpd->pch_hpd = hpd_icp;
 	else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
 		hpd->pch_hpd = hpd_spt;
@@ -337,17 +349,14 @@ void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 	u32 new_val;
 
 	lockdep_assert_held(&dev_priv->irq_lock);
-
 	drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
 
-	if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
-		return;
-
 	new_val = dev_priv->irq_mask;
 	new_val &= ~interrupt_mask;
 	new_val |= (~enabled_irq_mask & interrupt_mask);
 
-	if (new_val != dev_priv->irq_mask) {
+	if (new_val != dev_priv->irq_mask &&
+	    !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) {
 		dev_priv->irq_mask = new_val;
 		I915_WRITE(DEIMR, dev_priv->irq_mask);
 		POSTING_READ(DEIMR);
@@ -682,8 +691,12 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
 u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
 	enum pipe pipe = to_intel_crtc(crtc)->pipe;
 
+	if (!vblank->max_vblank_count)
+		return 0;
+
 	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 }
 
@@ -1031,17 +1044,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_TC1:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC1);
 	case HPD_PORT_TC2:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC2);
 	case HPD_PORT_TC3:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC3);
 	case HPD_PORT_TC4:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC4);
 	case HPD_PORT_TC5:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC5);
 	case HPD_PORT_TC6:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC6);
 	default:
 		return false;
 	}
@@ -1065,11 +1078,13 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_A:
-		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_A);
 	case HPD_PORT_B:
-		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_B);
 	case HPD_PORT_C:
-		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_C);
+	case HPD_PORT_D:
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_D);
 	default:
 		return false;
 	}
@@ -1079,17 +1094,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_TC1:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC1);
 	case HPD_PORT_TC2:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC2);
 	case HPD_PORT_TC3:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC3);
 	case HPD_PORT_TC4:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC4);
 	case HPD_PORT_TC5:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC5);
 	case HPD_PORT_TC6:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC6);
 	default:
 		return false;
 	}
@@ -1192,6 +1207,43 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
 
 }
 
+static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
+				  const u32 hpd[HPD_NUM_PINS])
+{
+	struct intel_encoder *encoder;
+	u32 enabled_irqs = 0;
+
+	for_each_intel_encoder(&dev_priv->drm, encoder)
+		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
+			enabled_irqs |= hpd[encoder->hpd_pin];
+
+	return enabled_irqs;
+}
+
+static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
+				  const u32 hpd[HPD_NUM_PINS])
+{
+	struct intel_encoder *encoder;
+	u32 hotplug_irqs = 0;
+
+	for_each_intel_encoder(&dev_priv->drm, encoder)
+		hotplug_irqs |= hpd[encoder->hpd_pin];
+
+	return hotplug_irqs;
+}
+
+static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
+				     hotplug_enables_func hotplug_enables)
+{
+	struct intel_encoder *encoder;
+	u32 hotplug = 0;
+
+	for_each_intel_encoder(&i915->drm, encoder)
+		hotplug |= hotplug_enables(i915, encoder->hpd_pin);
+
+	return hotplug;
+}
+
 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
 {
 	wake_up_all(&dev_priv->gmbus_wait_queue);
@@ -1245,6 +1297,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 			     u32 crc4) {}
 #endif
 
+static void flip_done_handler(struct drm_i915_private *i915,
+			      enum pipe pipe)
+{
+	struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, pipe);
+	struct drm_crtc_state *crtc_state = crtc->base.state;
+	struct drm_pending_vblank_event *e = crtc_state->event;
+	struct drm_device *dev = &i915->drm;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev->event_lock, irqflags);
+
+	crtc_state->event = NULL;
+
+	drm_crtc_send_vblank_event(&crtc->base, e);
+
+	spin_unlock_irqrestore(&dev->event_lock, irqflags);
+}
 
 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 				     enum pipe pipe)
@@ -1840,27 +1909,10 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 
 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 {
-	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
+	u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
+	u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
 	u32 pin_mask = 0, long_mask = 0;
 
-	if (HAS_PCH_TGP(dev_priv)) {
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
-	} else if (HAS_PCH_JSP(dev_priv)) {
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
-		tc_hotplug_trigger = 0;
-	} else if (HAS_PCH_MCC(dev_priv)) {
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
-	} else {
-		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
-			 "Unrecognized PCH type 0x%x\n",
-			 INTEL_PCH_TYPE(dev_priv));
-
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
-	}
-
 	if (ddi_hotplug_trigger) {
 		u32 dig_hotplug_reg;
 
@@ -2237,6 +2289,63 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 		drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
 }
 
+static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
+					   u32 te_trigger)
+{
+	enum pipe pipe = INVALID_PIPE;
+	enum transcoder dsi_trans;
+	enum port port;
+	u32 val, tmp;
+
+	/*
+	 * Incase of dual link, TE comes from DSI_1
+	 * this is to check if dual link is enabled
+	 */
+	val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
+	val &= PORT_SYNC_MODE_ENABLE;
+
+	/*
+	 * if dual link is enabled, then read DSI_0
+	 * transcoder registers
+	 */
+	port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
+						  PORT_A : PORT_B;
+	dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
+
+	/* Check if DSI configured in command mode */
+	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+	val = val & OP_MODE_MASK;
+
+	if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) {
+		drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
+		return;
+	}
+
+	/* Get PIPE for handling VBLANK event */
+	val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
+	case TRANS_DDI_EDP_INPUT_A_ON:
+		pipe = PIPE_A;
+		break;
+	case TRANS_DDI_EDP_INPUT_B_ONOFF:
+		pipe = PIPE_B;
+		break;
+	case TRANS_DDI_EDP_INPUT_C_ONOFF:
+		pipe = PIPE_C;
+		break;
+	default:
+		drm_err(&dev_priv->drm, "Invalid PIPE\n");
+		return;
+	}
+
+	intel_handle_vblank(dev_priv, pipe);
+
+	/* clear TE in dsi IIR */
+	port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
+	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
+	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
+}
+
 static irqreturn_t
 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 {
@@ -2271,7 +2380,6 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	if (master_ctl & GEN8_DE_PORT_IRQ) {
 		iir = I915_READ(GEN8_DE_PORT_IIR);
 		if (iir) {
-			u32 tmp_mask;
 			bool found = false;
 
 			I915_WRITE(GEN8_DE_PORT_IIR, iir);
@@ -2283,15 +2391,17 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 			}
 
 			if (IS_GEN9_LP(dev_priv)) {
-				tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
-				if (tmp_mask) {
-					bxt_hpd_irq_handler(dev_priv, tmp_mask);
+				u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
+
+				if (hotplug_trigger) {
+					bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
 					found = true;
 				}
 			} else if (IS_BROADWELL(dev_priv)) {
-				tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
-				if (tmp_mask) {
-					ilk_hpd_irq_handler(dev_priv, tmp_mask);
+				u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
+
+				if (hotplug_trigger) {
+					ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
 					found = true;
 				}
 			}
@@ -2301,6 +2411,15 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 				found = true;
 			}
 
+			if (INTEL_GEN(dev_priv) >= 11) {
+				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
+
+				if (te_trigger) {
+					gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
+					found = true;
+				}
+			}
+
 			if (!found)
 				drm_err(&dev_priv->drm,
 					"Unexpected DE Port interrupt\n");
@@ -2329,6 +2448,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 		if (iir & GEN8_PIPE_VBLANK)
 			intel_handle_vblank(dev_priv, pipe);
 
+		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
+			flip_done_handler(dev_priv, pipe);
+
 		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
 			hsw_pipe_crc_irq_handler(dev_priv, pipe);
 
@@ -2631,12 +2753,47 @@ int ilk_enable_vblank(struct drm_crtc *crtc)
 	return 0;
 }
 
+static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc,
+				   bool enable)
+{
+	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+	enum port port;
+	u32 tmp;
+
+	if (!(intel_crtc->mode_flags &
+	    (I915_MODE_FLAG_DSI_USE_TE1 | I915_MODE_FLAG_DSI_USE_TE0)))
+		return false;
+
+	/* for dual link cases we consider TE from slave */
+	if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
+		port = PORT_B;
+	else
+		port = PORT_A;
+
+	tmp =  I915_READ(DSI_INTR_MASK_REG(port));
+	if (enable)
+		tmp &= ~DSI_TE_EVENT;
+	else
+		tmp |= DSI_TE_EVENT;
+
+	I915_WRITE(DSI_INTR_MASK_REG(port), tmp);
+
+	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
+	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
+
+	return true;
+}
+
 int bdw_enable_vblank(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
 	unsigned long irqflags;
 
+	if (gen11_dsi_configure_te(intel_crtc, true))
+		return 0;
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -2650,6 +2807,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
 	return 0;
 }
 
+void skl_enable_flip_done(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&i915->irq_lock, irqflags);
+
+	bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+	spin_unlock_irqrestore(&i915->irq_lock, irqflags);
+}
+
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
@@ -2702,14 +2872,31 @@ void ilk_disable_vblank(struct drm_crtc *crtc)
 void bdw_disable_vblank(struct drm_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	enum pipe pipe = intel_crtc->pipe;
 	unsigned long irqflags;
 
+	if (gen11_dsi_configure_te(intel_crtc, false))
+		return;
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
+void skl_disable_flip_done(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&i915->irq_lock, irqflags);
+
+	bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+	spin_unlock_irqrestore(&i915->irq_lock, irqflags);
+}
+
 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_uncore *uncore = &dev_priv->uncore;
@@ -2723,24 +2910,6 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv)
 		I915_WRITE(SERR_INT, 0xffffffff);
 }
 
-/*
- * SDEIER is also touched by the interrupt handler to work around missed PCH
- * interrupts. Hence we can't update it after the interrupt handler is enabled -
- * instead we unconditionally enable all PCH interrupt sources here, but then
- * only unmask them as needed with SDEIMR.
- *
- * This function needs to be called before interrupts are enabled.
- */
-static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
-{
-	if (HAS_PCH_NOP(dev_priv))
-		return;
-
-	drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
-	I915_WRITE(SDEIER, 0xffffffff);
-	POSTING_READ(SDEIER);
-}
-
 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_uncore *uncore = &dev_priv->uncore;
@@ -2797,6 +2966,8 @@ static void ilk_irq_reset(struct drm_i915_private *dev_priv)
 	struct intel_uncore *uncore = &dev_priv->uncore;
 
 	GEN3_IRQ_RESET(uncore, DE);
+	dev_priv->irq_mask = ~0u;
+
 	if (IS_GEN(dev_priv, 7))
 		intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
 
@@ -2920,6 +3091,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
 	enum pipe pipe;
 
+	if (INTEL_GEN(dev_priv) >= 9)
+		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
 	spin_lock_irq(&dev_priv->irq_lock);
 
 	if (!intel_irqs_enabled(dev_priv)) {
@@ -2974,29 +3148,29 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
-				  const u32 hpd[HPD_NUM_PINS])
-{
-	struct intel_encoder *encoder;
-	u32 enabled_irqs = 0;
-
-	for_each_intel_encoder(&dev_priv->drm, encoder)
-		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
-			enabled_irqs |= hpd[encoder->hpd_pin];
-
-	return enabled_irqs;
-}
-
-static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
-				  const u32 hpd[HPD_NUM_PINS])
+static u32 ibx_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
 {
-	struct intel_encoder *encoder;
-	u32 hotplug_irqs = 0;
-
-	for_each_intel_encoder(&dev_priv->drm, encoder)
-		hotplug_irqs |= hpd[encoder->hpd_pin];
-
-	return hotplug_irqs;
+	switch (pin) {
+	case HPD_PORT_A:
+		/*
+		 * When CPU and PCH are on the same package, port A
+		 * HPD must be enabled in both north and south.
+		 */
+		return HAS_PCH_LPT_LP(i915) ?
+			PORTA_HOTPLUG_ENABLE : 0;
+	case HPD_PORT_B:
+		return PORTB_HOTPLUG_ENABLE |
+			PORTB_PULSE_DURATION_2ms;
+	case HPD_PORT_C:
+		return PORTC_HOTPLUG_ENABLE |
+			PORTC_PULSE_DURATION_2ms;
+	case HPD_PORT_D:
+		return PORTD_HOTPLUG_ENABLE |
+			PORTD_PULSE_DURATION_2ms;
+	default:
+		return 0;
+	}
 }
 
 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -3009,18 +3183,14 @@ static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	 * The pulse duration bits are reserved on LPT+.
 	 */
 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
-	hotplug &= ~(PORTB_PULSE_DURATION_MASK |
+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+		     PORTB_HOTPLUG_ENABLE |
+		     PORTC_HOTPLUG_ENABLE |
+		     PORTD_HOTPLUG_ENABLE |
+		     PORTB_PULSE_DURATION_MASK |
 		     PORTC_PULSE_DURATION_MASK |
 		     PORTD_PULSE_DURATION_MASK);
-	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
-	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
-	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
-	/*
-	 * When CPU and PCH are on the same package, port A
-	 * HPD must be enabled in both north and south.
-	 */
-	if (HAS_PCH_LPT_LP(dev_priv))
-		hotplug |= PORTA_HOTPLUG_ENABLE;
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
@@ -3036,28 +3206,65 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	ibx_hpd_detection_setup(dev_priv);
 }
 
-static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
-					u32 enable_mask)
+static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915,
+				   enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+	case HPD_PORT_B:
+	case HPD_PORT_C:
+	case HPD_PORT_D:
+		return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
+	default:
+		return 0;
+	}
+}
+
+static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915,
+				  enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_TC1:
+	case HPD_PORT_TC2:
+	case HPD_PORT_TC3:
+	case HPD_PORT_TC4:
+	case HPD_PORT_TC5:
+	case HPD_PORT_TC6:
+		return ICP_TC_HPD_ENABLE(pin);
+	default:
+		return 0;
+	}
+}
+
+static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
 	hotplug = I915_READ(SHOTPLUG_CTL_DDI);
-	hotplug |= enable_mask;
+	hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
+		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) |
+		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) |
+		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_D));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);
 	I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
 }
 
-static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv,
-				       u32 enable_mask)
+static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
 	hotplug = I915_READ(SHOTPLUG_CTL_TC);
-	hotplug |= enable_mask;
+	hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC4) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC5) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC6));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);
 	I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
 }
 
-static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
-			      u32 ddi_enable_mask, u32 tc_enable_mask)
+static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug_irqs, enabled_irqs;
 
@@ -3069,52 +3276,67 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
 
 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
 
-	icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask);
-	if (tc_enable_mask)
-		icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask);
+	icp_ddi_hpd_detection_setup(dev_priv);
+	icp_tc_hpd_detection_setup(dev_priv);
 }
 
-/*
- * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
- * equivalent of SDE.
- */
-static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static u32 gen11_hotplug_enables(struct drm_i915_private *i915,
+				 enum hpd_pin pin)
 {
-	icp_hpd_irq_setup(dev_priv,
-			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
+	switch (pin) {
+	case HPD_PORT_TC1:
+	case HPD_PORT_TC2:
+	case HPD_PORT_TC3:
+	case HPD_PORT_TC4:
+	case HPD_PORT_TC5:
+	case HPD_PORT_TC6:
+		return GEN11_HOTPLUG_CTL_ENABLE(pin);
+	default:
+		return 0;
+	}
 }
 
-/*
- * JSP behaves exactly the same as MCC above except that port C is mapped to
- * the DDI-C pins instead of the TC1 pins.  This means we should follow TGP's
- * masks & tables rather than ICP's masks & tables.
- */
-static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
-	icp_hpd_irq_setup(dev_priv,
-			  TGP_DDI_HPD_ENABLE_MASK, 0);
+	u32 val;
+
+	val = I915_READ(SOUTH_CHICKEN1);
+	val |= (INVERT_DDIA_HPD |
+		INVERT_DDIB_HPD |
+		INVERT_DDIC_HPD |
+		INVERT_DDID_HPD);
+	I915_WRITE(SOUTH_CHICKEN1, val);
+
+	icp_hpd_irq_setup(dev_priv);
 }
 
-static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+	hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
+}
+
+static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
+{
+	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+	hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
 	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
 }
 
@@ -3132,14 +3354,39 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_DE_HPD_IMR, val);
 	POSTING_READ(GEN11_DE_HPD_IMR);
 
-	gen11_hpd_detection_setup(dev_priv);
+	gen11_tc_hpd_detection_setup(dev_priv);
+	gen11_tbt_hpd_detection_setup(dev_priv);
+
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+		icp_hpd_irq_setup(dev_priv);
+}
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
-		icp_hpd_irq_setup(dev_priv,
-				  TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
-	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
-		icp_hpd_irq_setup(dev_priv,
-				  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
+static u32 spt_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+		return PORTA_HOTPLUG_ENABLE;
+	case HPD_PORT_B:
+		return PORTB_HOTPLUG_ENABLE;
+	case HPD_PORT_C:
+		return PORTC_HOTPLUG_ENABLE;
+	case HPD_PORT_D:
+		return PORTD_HOTPLUG_ENABLE;
+	default:
+		return 0;
+	}
+}
+
+static u32 spt_hotplug2_enables(struct drm_i915_private *i915,
+				enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_E:
+		return PORTE_HOTPLUG_ENABLE;
+	default:
+		return 0;
+	}
 }
 
 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -3156,14 +3403,16 @@ static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 
 	/* Enable digital hotplug on the PCH */
 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
-	hotplug |= PORTA_HOTPLUG_ENABLE |
-		   PORTB_HOTPLUG_ENABLE |
-		   PORTC_HOTPLUG_ENABLE |
-		   PORTD_HOTPLUG_ENABLE;
+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+		     PORTB_HOTPLUG_ENABLE |
+		     PORTC_HOTPLUG_ENABLE |
+		     PORTD_HOTPLUG_ENABLE);
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 
 	hotplug = I915_READ(PCH_PORT_HOTPLUG2);
-	hotplug |= PORTE_HOTPLUG_ENABLE;
+	hotplug &= ~PORTE_HOTPLUG_ENABLE;
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);
 	I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
 }
 
@@ -3182,6 +3431,18 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	spt_hpd_detection_setup(dev_priv);
 }
 
+static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+		return DIGITAL_PORTA_HOTPLUG_ENABLE |
+			DIGITAL_PORTA_PULSE_DURATION_2ms;
+	default:
+		return 0;
+	}
+}
+
 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
@@ -3192,9 +3453,9 @@ static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	 * The pulse duration bits are reserved on HSW+.
 	 */
 	hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
-	hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
-	hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
-		   DIGITAL_PORTA_PULSE_DURATION_2ms;
+	hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE |
+		     DIGITAL_PORTA_PULSE_DURATION_MASK);
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);
 	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
 }
 
@@ -3215,41 +3476,45 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	ibx_hpd_irq_setup(dev_priv);
 }
 
-static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
-				      u32 enabled_irqs)
+static u32 bxt_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
 {
 	u32 hotplug;
 
-	hotplug = I915_READ(PCH_PORT_HOTPLUG);
-	hotplug |= PORTA_HOTPLUG_ENABLE |
-		   PORTB_HOTPLUG_ENABLE |
-		   PORTC_HOTPLUG_ENABLE;
-
-	drm_dbg_kms(&dev_priv->drm,
-		    "Invert bit setting: hp_ctl:%x hp_port:%x\n",
-		    hotplug, enabled_irqs);
-	hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
-
-	/*
-	 * For BXT invert bit has to be set based on AOB design
-	 * for HPD detection logic, update it based on VBT fields.
-	 */
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
-		hotplug |= BXT_DDIA_HPD_INVERT;
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
-		hotplug |= BXT_DDIB_HPD_INVERT;
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
-		hotplug |= BXT_DDIC_HPD_INVERT;
-
-	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
+	switch (pin) {
+	case HPD_PORT_A:
+		hotplug = PORTA_HOTPLUG_ENABLE;
+		if (intel_bios_is_port_hpd_inverted(i915, PORT_A))
+			hotplug |= BXT_DDIA_HPD_INVERT;
+		return hotplug;
+	case HPD_PORT_B:
+		hotplug = PORTB_HOTPLUG_ENABLE;
+		if (intel_bios_is_port_hpd_inverted(i915, PORT_B))
+			hotplug |= BXT_DDIB_HPD_INVERT;
+		return hotplug;
+	case HPD_PORT_C:
+		hotplug = PORTC_HOTPLUG_ENABLE;
+		if (intel_bios_is_port_hpd_inverted(i915, PORT_C))
+			hotplug |= BXT_DDIC_HPD_INVERT;
+		return hotplug;
+	default:
+		return 0;
+	}
 }
 
 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
-	__bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
+	u32 hotplug;
+
+	hotplug = I915_READ(PCH_PORT_HOTPLUG);
+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+		     PORTB_HOTPLUG_ENABLE |
+		     PORTC_HOTPLUG_ENABLE |
+		     BXT_DDIA_HPD_INVERT |
+		     BXT_DDIB_HPD_INVERT |
+		     BXT_DDIC_HPD_INVERT);
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);
+	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
@@ -3261,11 +3526,23 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 
 	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
 
-	__bxt_hpd_detection_setup(dev_priv, enabled_irqs);
+	bxt_hpd_detection_setup(dev_priv);
 }
 
+/*
+ * SDEIER is also touched by the interrupt handler to work around missed PCH
+ * interrupts. Hence we can't update it after the interrupt handler is enabled -
+ * instead we unconditionally enable all PCH interrupt sources here, but then
+ * only unmask them as needed with SDEIMR.
+ *
+ * Note that we currently do this after installing the interrupt handler,
+ * but before we enable the master interrupt. That should be sufficient
+ * to avoid races with the irq handler, assuming we have MSI. Shared legacy
+ * interrupts could still race.
+ */
 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
 {
+	struct intel_uncore *uncore = &dev_priv->uncore;
 	u32 mask;
 
 	if (HAS_PCH_NOP(dev_priv))
@@ -3278,14 +3555,7 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
 	else
 		mask = SDE_GMBUS_CPT;
 
-	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
-	I915_WRITE(SDEIMR, ~mask);
-
-	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
-	    HAS_PCH_LPT(dev_priv))
-		ibx_hpd_detection_setup(dev_priv);
-	else
-		spt_hpd_detection_setup(dev_priv);
+	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
 }
 
 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3303,7 +3573,7 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
 		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
 				DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
 				DE_PIPEA_CRC_DONE | DE_POISON);
-		extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
+		extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |
 			      DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
 			      DE_DP_A_HOTPLUG);
 	}
@@ -3313,29 +3583,17 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
 		display_mask |= DE_EDP_PSR_INT_HSW;
 	}
 
-	dev_priv->irq_mask = ~display_mask;
+	if (IS_IRONLAKE_M(dev_priv))
+		extra_mask |= DE_PCU_EVENT;
 
-	ibx_irq_pre_postinstall(dev_priv);
+	dev_priv->irq_mask = ~display_mask;
 
-	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
-		      display_mask | extra_mask);
+	ibx_irq_postinstall(dev_priv);
 
 	gen5_gt_irq_postinstall(&dev_priv->gt);
 
-	ilk_hpd_detection_setup(dev_priv);
-
-	ibx_irq_postinstall(dev_priv);
-
-	if (IS_IRONLAKE_M(dev_priv)) {
-		/* Enable PCU event interrupts
-		 *
-		 * spinlocking not required here for correctness since interrupt
-		 * setup is guaranteed to run in single-threaded context. But we
-		 * need it to make the assert_spin_locked happy. */
-		spin_lock_irq(&dev_priv->irq_lock);
-		ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
-		spin_unlock_irq(&dev_priv->irq_lock);
-	}
+	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
+		      display_mask | extra_mask);
 }
 
 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
@@ -3400,14 +3658,24 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	if (IS_GEN9_LP(dev_priv))
 		de_port_masked |= BXT_DE_PORT_GMBUS;
 
+	if (INTEL_GEN(dev_priv) >= 11) {
+		enum port port;
+
+		if (intel_bios_is_dsi_present(dev_priv, &port))
+			de_port_masked |= DSI0_TE | DSI1_TE;
+	}
+
 	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
 					   GEN8_PIPE_FIFO_UNDERRUN;
 
+	if (INTEL_GEN(dev_priv) >= 9)
+		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
 	de_port_enables = de_port_masked;
 	if (IS_GEN9_LP(dev_priv))
 		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
 	else if (IS_BROADWELL(dev_priv))
-		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
+		de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		enum transcoder trans;
@@ -3445,51 +3713,26 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 
 		GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
 			      de_hpd_enables);
-		gen11_hpd_detection_setup(dev_priv);
-	} else if (IS_GEN9_LP(dev_priv)) {
-		bxt_hpd_detection_setup(dev_priv);
-	} else if (IS_BROADWELL(dev_priv)) {
-		ilk_hpd_detection_setup(dev_priv);
 	}
 }
 
 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 {
 	if (HAS_PCH_SPLIT(dev_priv))
-		ibx_irq_pre_postinstall(dev_priv);
+		ibx_irq_postinstall(dev_priv);
 
 	gen8_gt_irq_postinstall(&dev_priv->gt);
 	gen8_de_irq_postinstall(dev_priv);
 
-	if (HAS_PCH_SPLIT(dev_priv))
-		ibx_irq_postinstall(dev_priv);
-
 	gen8_master_intr_enable(dev_priv->uncore.regs);
 }
 
 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 {
+	struct intel_uncore *uncore = &dev_priv->uncore;
 	u32 mask = SDE_GMBUS_ICP;
 
-	drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
-	I915_WRITE(SDEIER, 0xffffffff);
-	POSTING_READ(SDEIER);
-
-	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
-	I915_WRITE(SDEIMR, ~mask);
-
-	if (HAS_PCH_TGP(dev_priv)) {
-		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
-	} else if (HAS_PCH_JSP(dev_priv)) {
-		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
-	} else if (HAS_PCH_MCC(dev_priv)) {
-		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1));
-	} else {
-		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
-	}
+	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
 }
 
 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3536,6 +3779,7 @@ static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
 	i9xx_pipestat_irq_reset(dev_priv);
 
 	GEN2_IRQ_RESET(uncore);
+	dev_priv->irq_mask = ~0u;
 }
 
 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3705,6 +3949,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
 	i9xx_pipestat_irq_reset(dev_priv);
 
 	GEN3_IRQ_RESET(uncore, GEN2_);
+	dev_priv->irq_mask = ~0u;
 }
 
 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3811,6 +4056,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
 	i9xx_pipestat_irq_reset(dev_priv);
 
 	GEN3_IRQ_RESET(uncore, GEN2_);
+	dev_priv->irq_mask = ~0u;
 }
 
 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3995,10 +4241,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		if (I915_HAS_HOTPLUG(dev_priv))
 			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
 	} else {
-		if (HAS_PCH_JSP(dev_priv))
-			dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
-		else if (HAS_PCH_MCC(dev_priv))
-			dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
+		if (HAS_PCH_DG1(dev_priv))
+			dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
 		else if (INTEL_GEN(dev_priv) >= 11)
 			dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
 		else if (IS_GEN9_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 25f25cd95818..2efe609519ca 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -118,6 +118,9 @@ void i965_disable_vblank(struct drm_crtc *crtc);
 void ilk_disable_vblank(struct drm_crtc *crtc);
 void bdw_disable_vblank(struct drm_crtc *crtc);
 
+void skl_enable_flip_done(struct intel_crtc *crtc);
+void skl_disable_flip_done(struct intel_crtc *crtc);
+
 void gen2_irq_reset(struct intel_uncore *uncore);
 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
 		    i915_reg_t iir, i915_reg_t ier);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fb5e30de78c2..1fe390727d80 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -847,6 +847,14 @@ static const struct intel_device_info ehl_info = {
 	.ppgtt_size = 36,
 };
 
+static const struct intel_device_info jsl_info = {
+	GEN11_FEATURES,
+	PLATFORM(INTEL_JASPERLAKE),
+	.require_force_probe = 1,
+	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
+	.ppgtt_size = 36,
+};
+
 #define GEN12_FEATURES \
 	GEN11_FEATURES, \
 	GEN(12), \
@@ -901,6 +909,8 @@ static const struct intel_device_info rkl_info = {
 	GEN12_FEATURES, \
 	.memory_regions = REGION_SMEM | REGION_LMEM, \
 	.has_master_unit_irq = 1, \
+	.has_llc = 0, \
+	.has_snoop = 1, \
 	.is_dgfx = 1
 
 static const struct intel_device_info dg1_info __maybe_unused = {
@@ -911,6 +921,8 @@ static const struct intel_device_info dg1_info __maybe_unused = {
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
 		BIT(VCS0) | BIT(VCS2),
+	/* Wa_16011227922 */
+	.ppgtt_size = 47,
 };
 
 #undef GEN
@@ -986,6 +998,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_CNL_IDS(&cnl_info),
 	INTEL_ICL_11_IDS(&icl_info),
 	INTEL_EHL_IDS(&ehl_info),
+	INTEL_JSL_IDS(&jsl_info),
 	INTEL_TGL_12_IDS(&tgl_info),
 	INTEL_RKL_IDS(&rkl_info),
 	{0, 0, 0}
@@ -1091,11 +1104,19 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 	return 0;
 }
 
+static void i915_pci_shutdown(struct pci_dev *pdev)
+{
+	struct drm_i915_private *i915 = pci_get_drvdata(pdev);
+
+	i915_driver_shutdown(i915);
+}
+
 static struct pci_driver i915_pci_driver = {
 	.name = DRIVER_NAME,
 	.id_table = pciidlist,
 	.probe = i915_pci_probe,
 	.remove = i915_pci_remove,
+	.shutdown = i915_pci_shutdown,
 	.driver.pm = &i915_pm_ops,
 };
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d805d4da6181..bb0656875697 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,7 +242,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
-#define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
+#define _MMIO_PLL3(pll, ...)		_MMIO(_PICK(pll, __VA_ARGS__))
+
 
 /*
  * Device info offset array based helpers for groups of registers with unevenly
@@ -2527,6 +2528,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define RING_PSMI_CTL(base)	_MMIO((base) + 0x50)
 #define RING_MAX_IDLE(base)	_MMIO((base) + 0x54)
 #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
+#define RING_ID(base)		_MMIO((base) + 0x8c)
 #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
 #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
@@ -4146,6 +4148,7 @@ enum {
 
 #define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
 #define   TGL_VRH_GATING_DIS		REG_BIT(31)
+#define   DPT_GATING_DIS		REG_BIT(22)
 
 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
 #define   BXT_GMBUS_GATING_DIS		(1 << 14)
@@ -4618,6 +4621,110 @@ enum {
 #define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME	REG_BIT(2)
 #define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE	REG_BIT(1)
 
+/* Icelake DSC Rate Control Range Parameter Registers */
+#define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
+#define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
+#define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define RC_BPG_OFFSET_SHIFT			10
+#define RC_MAX_QP_SHIFT				5
+#define RC_MIN_QP_SHIFT				0
+
+#define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
+#define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
+#define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
+
+#define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
+#define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
+#define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
+
+#define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
+#define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
+#define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
+							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
+							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
+
 /* VGA port control */
 #define ADPA			_MMIO(0x61100)
 #define PCH_ADPA                _MMIO(0xe1100)
@@ -6327,15 +6434,16 @@ enum {
 	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
 
 /* define the Watermark register on Ironlake */
-#define WM0_PIPEA_ILK		_MMIO(0x45100)
+#define _WM0_PIPEA_ILK		0x45100
+#define _WM0_PIPEB_ILK		0x45104
+#define _WM0_PIPEC_IVB		0x45200
+#define WM0_PIPE_ILK(pipe)	_MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
+					    _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
 #define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
 #define  WM0_PIPE_PLANE_SHIFT	16
 #define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
 #define  WM0_PIPE_SPRITE_SHIFT	8
 #define  WM0_PIPE_CURSOR_MASK	(0xff)
-
-#define WM0_PIPEB_ILK		_MMIO(0x45104)
-#define WM0_PIPEC_IVB		_MMIO(0x45200)
 #define WM1_LP_ILK		_MMIO(0x45108)
 #define  WM1_LP_SR_EN		(1 << 31)
 #define  WM1_LP_LATENCY_SHIFT	24
@@ -6923,6 +7031,7 @@ enum {
 #define   PLANE_CTL_TILED_X			(1 << 10)
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
+#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
@@ -7379,6 +7488,7 @@ enum {
 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
 #define PS_FILTER_MASK         (3 << 23)
 #define PS_FILTER_MEDIUM       (0 << 23)
+#define PS_FILTER_PROGRAMMED   (1 << 23)
 #define PS_FILTER_EDGE_ENHANCE (2 << 23)
 #define PS_FILTER_BILINEAR     (3 << 23)
 #define PS_VERT3TAP            (1 << 21)
@@ -7393,6 +7503,10 @@ enum {
 #define PS_VADAPT_MODE_MOST_ADAPT  (3 << 5)
 #define PS_PLANE_Y_SEL_MASK  (7 << 5)
 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
+#define PS_Y_VERT_FILTER_SELECT(set)   ((set) << 4)
+#define PS_Y_HORZ_FILTER_SELECT(set)   ((set) << 3)
+#define PS_UV_VERT_FILTER_SELECT(set)  ((set) << 2)
+#define PS_UV_HORZ_FILTER_SELECT(set)  ((set) << 1)
 
 #define _PS_PWR_GATE_1A     0x68160
 #define _PS_PWR_GATE_2A     0x68260
@@ -7455,6 +7569,17 @@ enum {
 #define _PS_ECC_STAT_2B     0x68AD0
 #define _PS_ECC_STAT_1C     0x691D0
 
+#define _PS_COEF_SET0_INDEX_1A	   0x68198
+#define _PS_COEF_SET0_INDEX_2A	   0x68298
+#define _PS_COEF_SET0_INDEX_1B	   0x68998
+#define _PS_COEF_SET0_INDEX_2B	   0x68A98
+#define PS_COEE_INDEX_AUTO_INC	   (1 << 10)
+
+#define _PS_COEF_SET0_DATA_1A	   0x6819C
+#define _PS_COEF_SET0_DATA_2A	   0x6829C
+#define _PS_COEF_SET0_DATA_1B	   0x6899C
+#define _PS_COEF_SET0_DATA_2B	   0x68A9C
+
 #define _ID(id, a, b) _PICK_EVEN(id, a, b)
 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe,        \
 			_ID(id, _PS_1A_CTRL, _PS_2A_CTRL),       \
@@ -7483,7 +7608,13 @@ enum {
 #define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe,     \
 			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
 			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
+#define CNL_PS_COEF_INDEX_SET(pipe, id, set)  _MMIO_PIPE(pipe,    \
+			_ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
+			_ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
 
+#define CNL_PS_COEF_DATA_SET(pipe, id, set)  _MMIO_PIPE(pipe,     \
+			_ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
+			_ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
 /* legacy palette */
 #define _LGC_PALETTE_A           0x4a000
 #define _LGC_PALETTE_B           0x4a800
@@ -7532,6 +7663,7 @@ enum {
 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
 #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
 #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
+#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
 
 #define DMC_DEBUG3		_MMIO(0x101090)
 
@@ -7681,6 +7813,9 @@ enum {
 	(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
 	 GEN11_PIPE_PLANE5_FAULT)
 
+#define _HPD_PIN_DDI(hpd_pin)	((hpd_pin) - HPD_PORT_A)
+#define _HPD_PIN_TC(hpd_pin)	((hpd_pin) - HPD_PORT_TC1)
+
 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
@@ -7694,13 +7829,11 @@ enum {
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
 #define  DSI1_TE			(1 << 24)
 #define  DSI0_TE			(1 << 23)
-#define  BXT_DE_PORT_HP_DDIC		(1 << 5)
-#define  BXT_DE_PORT_HP_DDIB		(1 << 4)
-#define  BXT_DE_PORT_HP_DDIA		(1 << 3)
-#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
-					 BXT_DE_PORT_HP_DDIB | \
-					 BXT_DE_PORT_HP_DDIC)
-#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
+#define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
+#define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
+					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
+					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
+#define  BDW_DE_PORT_HOTPLUG_MASK	GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
 #define  BXT_DE_PORT_GMBUS		(1 << 1)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
 #define  TGL_DE_PORT_AUX_USBC6		(1 << 13)
@@ -7759,27 +7892,27 @@ enum {
 #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
-#define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))
-#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(PORT_TC6) | \
-						 GEN11_TC_HOTPLUG(PORT_TC5) | \
-						 GEN11_TC_HOTPLUG(PORT_TC4) | \
-						 GEN11_TC_HOTPLUG(PORT_TC3) | \
-						 GEN11_TC_HOTPLUG(PORT_TC2) | \
-						 GEN11_TC_HOTPLUG(PORT_TC1))
-#define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))
-#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(PORT_TC6) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC5) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC4) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC3) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC2) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC1))
+#define  GEN11_TC_HOTPLUG(hpd_pin)		REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
+#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
+#define  GEN11_TBT_HOTPLUG(hpd_pin)		REG_BIT(_HPD_PIN_TC(hpd_pin))
+#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
 
 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
-#define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)		(8 << (tc_port) * 4)
-#define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)		(2 << (tc_port) * 4)
-#define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
-#define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)		(0 << (tc_port) * 4)
+#define  GEN11_HOTPLUG_CTL_ENABLE(hpd_pin)		(8 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define  GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin)		(2 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define  GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin)	(1 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define  GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin)		(0 << (_HPD_PIN_TC(hpd_pin) * 4))
 
 #define GEN11_GT_INTR_DW0		_MMIO(0x190018)
 #define  GEN11_CSME			(31)
@@ -7865,6 +7998,7 @@ enum {
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)
 
 #define CHICKEN_PAR1_1			_MMIO(0x42080)
+#define  KBL_ARB_FILL_SPARE_22		REG_BIT(22)
 #define  DIS_RAM_BYPASS_PSR2_MAN_TRACK	(1 << 16)
 #define  SKL_DE_COMPRESSED_HASH_MODE	(1 << 15)
 #define  DPA_MASK_VBLANK_SRD		(1 << 15)
@@ -7877,6 +8011,8 @@ enum {
 
 #define CHICKEN_MISC_2		_MMIO(0x42084)
 #define  CNL_COMP_PWR_DOWN	(1 << 23)
+#define  KBL_ARB_FILL_SPARE_14	REG_BIT(14)
+#define  KBL_ARB_FILL_SPARE_13	REG_BIT(13)
 #define  GLK_CL2_PWR_DOWN	(1 << 12)
 #define  GLK_CL1_PWR_DOWN	(1 << 11)
 #define  GLK_CL0_PWR_DOWN	(1 << 10)
@@ -7919,11 +8055,15 @@ enum {
 #define DISP_ARB_CTL2	_MMIO(0x45004)
 #define  DISP_DATA_PARTITION_5_6	(1 << 6)
 #define  DISP_IPC_ENABLE		(1 << 3)
-#define _DBUF_CTL_S1			0x45008
-#define _DBUF_CTL_S2			0x44FE8
-#define DBUF_CTL_S(slice)		_MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
-#define  DBUF_POWER_REQUEST		(1 << 31)
-#define  DBUF_POWER_STATE		(1 << 30)
+
+#define _DBUF_CTL_S1				0x45008
+#define _DBUF_CTL_S2				0x44FE8
+#define DBUF_CTL_S(slice)			_MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
+#define  DBUF_POWER_REQUEST			REG_BIT(31)
+#define  DBUF_POWER_STATE			REG_BIT(30)
+#define  DBUF_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(23, 19)
+#define  DBUF_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
+
 #define GEN7_MSG_CTL	_MMIO(0x45010)
 #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
 #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
@@ -8014,13 +8154,15 @@ enum {
 #define GEN8_L3CNTLREG	_MMIO(0x7034)
   #define GEN8_ERRDETBCTRL (1 << 9)
 
-#define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
-  #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC	(1 << 11)
-  #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE	(1 << 9)
+#define GEN11_COMMON_SLICE_CHICKEN3			_MMIO(0x7304)
+  #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN	REG_BIT(12)
+  #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC		REG_BIT(11)
+  #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE		REG_BIT(9)
 
 #define HIZ_CHICKEN					_MMIO(0x7018)
-# define CHV_HZ_8X8_MODE_IN_1X				(1 << 15)
-# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1 << 3)
+# define CHV_HZ_8X8_MODE_IN_1X				REG_BIT(15)
+# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE   REG_BIT(14)
+# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	REG_BIT(3)
 
 #define GEN9_SLICE_COMMON_ECO_CHICKEN0		_MMIO(0x7308)
 #define  DISABLE_PIXEL_MASK_CAMMING		(1 << 14)
@@ -8208,23 +8350,18 @@ enum {
 
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP			(1 << 23)
-#define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))
-#define SDE_DDI_HOTPLUG_ICP(port)	(1 << ((port) + 16))
-#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(PORT_B) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
-#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(PORT_C) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
+#define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
+#define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
+#define SDE_TC_HOTPLUG_MASK_ICP		(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
@@ -8292,139 +8429,21 @@ enum {
  */
 
 #define SHOTPLUG_CTL_DDI				_MMIO(0xc4030)
-#define   SHOTPLUG_CTL_DDI_HPD_ENABLE(port)		(0x8 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port)	(0x3 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port)		(0x0 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port)	(0x1 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port)	(0x2 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port)	(0x3 << (4 * (port)))
+#define   SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin)			(0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin)		(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin)		(0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin)		(0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin)		(0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin)	(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
 
 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
-#define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
+#define   ICP_TC_HPD_ENABLE(hpd_pin)		(8 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define   ICP_TC_HPD_LONG_DETECT(hpd_pin)	(2 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define   ICP_TC_HPD_SHORT_DETECT(hpd_pin)	(1 << (_HPD_PIN_TC(hpd_pin) * 4))
 
 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
 
-/* Icelake DSC Rate Control Range Parameter Registers */
-#define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
-#define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
-#define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
-#define RC_BPG_OFFSET_SHIFT			10
-#define RC_MAX_QP_SHIFT				5
-#define RC_MIN_QP_SHIFT				0
-
-#define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
-#define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
-#define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
-
-#define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
-#define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
-#define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
-
-#define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
-#define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
-#define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
-							_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe)		_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
-							_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
-
-#define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
-#define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
-
-#define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC4) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC3) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC2) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC1))
-#define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC6) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
-					 ICP_TC_HPD_ENABLE_MASK)
-
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
@@ -8684,6 +8703,10 @@ enum {
 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
+#define  INVERT_DDID_HPD			(1 << 18)
+#define  INVERT_DDIC_HPD			(1 << 17)
+#define  INVERT_DDIB_HPD			(1 << 16)
+#define  INVERT_DDIA_HPD			(1 << 15)
 #define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
 #define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
 #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
@@ -8954,12 +8977,12 @@ enum {
 #define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)		_MMIO(0xa540 + (n) * 4)
 #define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)		_MMIO(0xa560 + (n) * 4)
 #define  FORCEWAKE_RENDER_GEN9			_MMIO(0xa278)
-#define  FORCEWAKE_BLITTER_GEN9			_MMIO(0xa188)
+#define  FORCEWAKE_GT_GEN9			_MMIO(0xa188)
 #define  FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0x0D88)
 #define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)	_MMIO(0x0D50 + (n) * 4)
 #define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)	_MMIO(0x0D70 + (n) * 4)
 #define  FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0x0D84)
-#define  FORCEWAKE_ACK_BLITTER_GEN9		_MMIO(0x130044)
+#define  FORCEWAKE_ACK_GT_GEN9			_MMIO(0x130044)
 #define   FORCEWAKE_KERNEL			BIT(0)
 #define   FORCEWAKE_USER			BIT(1)
 #define   FORCEWAKE_KERNEL_FALLBACK		BIT(15)
@@ -9223,6 +9246,9 @@ enum {
 #define     GEN9_SAGV_DISABLE			0x0
 #define     GEN9_SAGV_IS_DISABLED		0x1
 #define     GEN9_SAGV_ENABLE			0x3
+#define   DG1_PCODE_STATUS			0x7E
+#define     DG1_UNCORE_GET_INIT_STATUS		0x0
+#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
 #define GEN6_PCODE_DATA				_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
@@ -10257,6 +10283,7 @@ enum skl_power_gate {
 #define  DPLL_CFGCR2_PDIV_2 (1 << 2)
 #define  DPLL_CFGCR2_PDIV_3 (2 << 2)
 #define  DPLL_CFGCR2_PDIV_7 (4 << 2)
+#define  DPLL_CFGCR2_PDIV_7_INVALID	(5 << 2)
 #define  DPLL_CFGCR2_CENTRAL_FREQ_MASK	(3)
 
 #define DPLL_CFGCR1(id)	_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
@@ -10276,9 +10303,9 @@ enum skl_power_gate {
 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
-#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \
 						       (tc_port) + 12 : \
-						       (tc_port) - PORT_TC4 + 21))
+						       (tc_port) - TC_PORT_4 + 21))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
@@ -10307,6 +10334,10 @@ enum skl_power_gate {
 #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
 					   _MG_PLL2_ENABLE)
 
+/* DG1 PLL */
+#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+					   _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+
 #define _MG_REFCLKIN_CTL_PORT1				0x16892C
 #define _MG_REFCLKIN_CTL_PORT2				0x16992C
 #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
@@ -10523,6 +10554,20 @@ enum skl_power_gate {
 #define RKL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
 						  _TGL_DPLL1_CFGCR1)
 
+#define _DG1_DPLL2_CFGCR0		0x16C284
+#define _DG1_DPLL3_CFGCR0		0x16C28C
+#define DG1_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+						   _TGL_DPLL1_CFGCR0, \
+						   _DG1_DPLL2_CFGCR0, \
+						   _DG1_DPLL3_CFGCR0)
+
+#define _DG1_DPLL2_CFGCR1               0x16C288
+#define _DG1_DPLL3_CFGCR1               0x16C290
+#define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+						   _TGL_DPLL1_CFGCR1, \
+						   _DG1_DPLL2_CFGCR1, \
+						   _DG1_DPLL3_CFGCR1)
+
 #define _DKL_PHY1_BASE			0x168000
 #define _DKL_PHY2_BASE			0x169000
 #define _DKL_PHY3_BASE			0x16A000
@@ -11003,14 +11048,17 @@ enum skl_power_gate {
 #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
 #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
 #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
+#define   CGM_PIPE_DEGAMMA_RED_MASK	REG_GENMASK(13, 0)
+#define   CGM_PIPE_DEGAMMA_GREEN_MASK	REG_GENMASK(29, 16)
+#define   CGM_PIPE_DEGAMMA_BLUE_MASK	REG_GENMASK(13, 0)
 #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
+#define   CGM_PIPE_GAMMA_RED_MASK	REG_GENMASK(9, 0)
+#define   CGM_PIPE_GAMMA_GREEN_MASK	REG_GENMASK(25, 16)
+#define   CGM_PIPE_GAMMA_BLUE_MASK	REG_GENMASK(9, 0)
 #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
 #define   CGM_PIPE_MODE_GAMMA	(1 << 2)
 #define   CGM_PIPE_MODE_CSC	(1 << 1)
 #define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)
-#define   CGM_PIPE_GAMMA_RED_MASK   REG_GENMASK(9, 0)
-#define   CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
-#define   CGM_PIPE_GAMMA_BLUE_MASK  REG_GENMASK(9, 0)
 
 #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
 #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 7b64e7137270..db2111fc809e 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -32,45 +32,10 @@
 #include "i915_reg.h"
 #include "i915_suspend.h"
 
-static void i915_save_display(struct drm_i915_private *dev_priv)
-{
-	struct pci_dev *pdev = dev_priv->drm.pdev;
-
-	/* Display arbitration control */
-	if (INTEL_GEN(dev_priv) <= 4)
-		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
-
-	if (IS_GEN(dev_priv, 4))
-		pci_read_config_word(pdev, GCDGMBUS,
-				     &dev_priv->regfile.saveGCDGMBUS);
-}
-
-static void i915_restore_display(struct drm_i915_private *dev_priv)
-{
-	struct pci_dev *pdev = dev_priv->drm.pdev;
-
-	if (IS_GEN(dev_priv, 4))
-		pci_write_config_word(pdev, GCDGMBUS,
-				      dev_priv->regfile.saveGCDGMBUS);
-
-	/* Display arbitration */
-	if (INTEL_GEN(dev_priv) <= 4)
-		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
-
-	/* only restore FBC info on the platform that supports FBC*/
-	intel_fbc_global_disable(dev_priv);
-
-	intel_vga_redisable(dev_priv);
-
-	intel_gmbus_reset(dev_priv);
-}
-
-int i915_save_state(struct drm_i915_private *dev_priv)
+static void intel_save_swf(struct drm_i915_private *dev_priv)
 {
 	int i;
 
-	i915_save_display(dev_priv);
-
 	/* Scratch space */
 	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
 		for (i = 0; i < 7; i++) {
@@ -90,16 +55,12 @@ int i915_save_state(struct drm_i915_private *dev_priv)
 		for (i = 0; i < 3; i++)
 			dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
 	}
-
-	return 0;
 }
 
-int i915_restore_state(struct drm_i915_private *dev_priv)
+static void intel_restore_swf(struct drm_i915_private *dev_priv)
 {
 	int i;
 
-	i915_restore_display(dev_priv);
-
 	/* Scratch space */
 	if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
 		for (i = 0; i < 7; i++) {
@@ -119,6 +80,41 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
 		for (i = 0; i < 3; i++)
 			I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
 	}
+}
+
+void i915_save_display(struct drm_i915_private *dev_priv)
+{
+	struct pci_dev *pdev = dev_priv->drm.pdev;
+
+	/* Display arbitration control */
+	if (INTEL_GEN(dev_priv) <= 4)
+		dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
 
-	return 0;
+	if (IS_GEN(dev_priv, 4))
+		pci_read_config_word(pdev, GCDGMBUS,
+				     &dev_priv->regfile.saveGCDGMBUS);
+
+	intel_save_swf(dev_priv);
+}
+
+void i915_restore_display(struct drm_i915_private *dev_priv)
+{
+	struct pci_dev *pdev = dev_priv->drm.pdev;
+
+	intel_restore_swf(dev_priv);
+
+	if (IS_GEN(dev_priv, 4))
+		pci_write_config_word(pdev, GCDGMBUS,
+				      dev_priv->regfile.saveGCDGMBUS);
+
+	/* Display arbitration */
+	if (INTEL_GEN(dev_priv) <= 4)
+		I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
+
+	/* only restore FBC info on the platform that supports FBC*/
+	intel_fbc_global_disable(dev_priv);
+
+	intel_vga_redisable(dev_priv);
+
+	intel_gmbus_reset(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/i915_suspend.h b/drivers/gpu/drm/i915/i915_suspend.h
index 3a36fb4ecc05..e5a611ee3d15 100644
--- a/drivers/gpu/drm/i915/i915_suspend.h
+++ b/drivers/gpu/drm/i915/i915_suspend.h
@@ -8,7 +8,7 @@
 
 struct drm_i915_private;
 
-int i915_save_state(struct drm_i915_private *i915);
-int i915_restore_state(struct drm_i915_private *i915);
+void i915_save_display(struct drm_i915_private *i915);
+void i915_restore_display(struct drm_i915_private *i915);
 
 #endif /* __I915_SUSPEND_H__ */
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index ffb5287e055a..caa9b041616b 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -314,8 +314,10 @@ static void __vma_release(struct dma_fence_work *work)
 {
 	struct i915_vma_work *vw = container_of(work, typeof(*vw), base);
 
-	if (vw->pinned)
+	if (vw->pinned) {
 		__i915_gem_object_unpin_pages(vw->pinned);
+		i915_gem_object_put(vw->pinned);
+	}
 
 	i915_vm_free_pt_stash(vw->vm, &vw->stash);
 	i915_vm_put(vw->vm);
@@ -431,7 +433,7 @@ int i915_vma_bind(struct i915_vma *vma,
 
 		if (vma->obj) {
 			__i915_gem_object_pin_pages(vma->obj);
-			work->pinned = vma->obj;
+			work->pinned = i915_gem_object_get(vma->obj);
 		}
 	} else {
 		vma->ops->bind_vma(vma->vm, NULL, vma, cache_level, bind_flags);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index adc836f15fde..e67cec8fa2aa 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -62,6 +62,7 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(CANNONLAKE),
 	PLATFORM_NAME(ICELAKE),
 	PLATFORM_NAME(ELKHARTLAKE),
+	PLATFORM_NAME(JASPERLAKE),
 	PLATFORM_NAME(TIGERLAKE),
 	PLATFORM_NAME(ROCKETLAKE),
 	PLATFORM_NAME(DG1),
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6a3d607218aa..d92fa041c700 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -79,6 +79,7 @@ enum intel_platform {
 	/* gen11 */
 	INTEL_ICELAKE,
 	INTEL_ELKHARTLAKE,
+	INTEL_JASPERLAKE,
 	/* gen12 */
 	INTEL_TIGERLAKE,
 	INTEL_ROCKETLAKE,
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 8aa12cad93ce..4754296a250e 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -7,7 +7,8 @@
 #include "intel_dram.h"
 
 struct dram_dimm_info {
-	u8 size, width, ranks;
+	u16 size;
+	u8 width, ranks;
 };
 
 struct dram_channel_info {
@@ -41,10 +42,10 @@ static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
 	return dimm->ranks * 64 / (dimm->width ?: 1);
 }
 
-/* Returns total GB for the whole DIMM */
+/* Returns total Gb for the whole DIMM */
 static int skl_get_dimm_size(u16 val)
 {
-	return val & SKL_DRAM_SIZE_MASK;
+	return (val & SKL_DRAM_SIZE_MASK) * 8;
 }
 
 static int skl_get_dimm_width(u16 val)
@@ -74,10 +75,10 @@ static int skl_get_dimm_ranks(u16 val)
 	return val + 1;
 }
 
-/* Returns total GB for the whole DIMM */
+/* Returns total Gb for the whole DIMM */
 static int cnl_get_dimm_size(u16 val)
 {
-	return (val & CNL_DRAM_SIZE_MASK) / 2;
+	return (val & CNL_DRAM_SIZE_MASK) * 8 / 2;
 }
 
 static int cnl_get_dimm_width(u16 val)
@@ -110,8 +111,8 @@ static int cnl_get_dimm_ranks(u16 val)
 static bool
 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
 {
-	/* Convert total GB to Gb per DRAM device */
-	return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
+	/* Convert total Gb to Gb per DRAM device */
+	return dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
 }
 
 static void
@@ -130,7 +131,7 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915,
 	}
 
 	drm_dbg_kms(&i915->drm,
-		    "CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
+		    "CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
 		    channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
 		    yesno(skl_is_16gb_dimm(dimm)));
 }
@@ -354,9 +355,9 @@ static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
 
 	/*
 	 * Size in register is Gb per DRAM device. Convert to total
-	 * GB to match the way we report this for non-LP platforms.
+	 * Gb to match the way we report this for non-LP platforms.
 	 */
-	dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
+	dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm);
 }
 
 static int bxt_get_dram_info(struct drm_i915_private *i915)
@@ -404,7 +405,7 @@ static int bxt_get_dram_info(struct drm_i915_private *i915)
 			    dram_info->type != type);
 
 		drm_dbg_kms(&i915->drm,
-			    "CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
+			    "CH%u DIMM size: %u Gb, width: X%u, ranks: %u, type: %s\n",
 			    i - BXT_D_CR_DRP0_DUNIT_START,
 			    dimm.size, dimm.width, dimm.ranks,
 			    intel_dram_type_str(type));
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 6c97192e9ca8..f31c0dabd0cc 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -115,7 +115,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 		return PCH_ICP;
 	case INTEL_PCH_MCC_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
-		drm_WARN_ON(&dev_priv->drm, !IS_ELKHARTLAKE(dev_priv));
+		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
 		return PCH_MCC;
 	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
 	case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
@@ -126,7 +126,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 	case INTEL_PCH_JSP_DEVICE_ID_TYPE:
 	case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
 		drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
-		drm_WARN_ON(&dev_priv->drm, !IS_ELKHARTLAKE(dev_priv));
+		drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
 		return PCH_JSP;
 	default:
 		return PCH_NONE;
@@ -157,7 +157,7 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 
 	if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
-	else if (IS_ELKHARTLAKE(dev_priv))
+	else if (IS_JSL_EHL(dev_priv))
 		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
 	else if (IS_ICELAKE(dev_priv))
 		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 34e0d22d456b..f54375b11964 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3573,11 +3573,11 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
 	_ilk_disable_lp_wm(dev_priv, dirty);
 
 	if (dirty & WM_DIRTY_PIPE(PIPE_A))
-		I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
+		I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
 	if (dirty & WM_DIRTY_PIPE(PIPE_B))
-		I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
+		I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
 	if (dirty & WM_DIRTY_PIPE(PIPE_C))
-		I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
+		I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
 
 	if (dirty & WM_DIRTY_DDB) {
 		if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -3706,7 +3706,7 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
  *  - All planes can enable watermarks for latencies >= SAGV engine block time
  *  - We're not using an interlaced display configuration
  */
-int
+static int
 intel_enable_sagv(struct drm_i915_private *dev_priv)
 {
 	int ret;
@@ -3740,7 +3740,7 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
-int
+static int
 intel_disable_sagv(struct drm_i915_private *dev_priv)
 {
 	int ret;
@@ -6287,13 +6287,8 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
 	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
 	struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
 	enum pipe pipe = crtc->pipe;
-	static const i915_reg_t wm0_pipe_reg[] = {
-		[PIPE_A] = WM0_PIPEA_ILK,
-		[PIPE_B] = WM0_PIPEB_ILK,
-		[PIPE_C] = WM0_PIPEC_IVB,
-	};
 
-	hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
+	hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
 
 	memset(active, 0, sizeof(*active));
 
@@ -7116,25 +7111,26 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 			 0, CNL_DELAY_PMRSP);
 }
 
-static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
+static void gen12_init_clock_gating(struct drm_i915_private *i915)
 {
-	u32 vd_pg_enable = 0;
 	unsigned int i;
 
+	/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
+	for (i = 0; i < I915_MAX_VCS; i++)
+		if (HAS_ENGINE(&i915->gt, _VCS(i)))
+			intel_uncore_rmw(&i915->uncore, POWERGATE_ENABLE, 0,
+					 VDN_HCP_POWERGATE_ENABLE(i) |
+					 VDN_MFX_POWERGATE_ENABLE(i));
+}
+
+static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+	gen12_init_clock_gating(dev_priv);
+
 	/* Wa_1409120013:tgl */
 	I915_WRITE(ILK_DPFC_CHICKEN,
 		   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 
-	/* This is not a WA. Enable VD HCP & MFX_ENC powergate */
-	for (i = 0; i < I915_MAX_VCS; i++) {
-		if (HAS_ENGINE(&dev_priv->gt, _VCS(i)))
-			vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
-					VDN_MFX_POWERGATE_ENABLE(i);
-	}
-
-	I915_WRITE(POWERGATE_ENABLE,
-		   I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
-
 	/* Wa_1409825376:tgl (pre-prod)*/
 	if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
 		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
@@ -7145,6 +7141,16 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 			 0, DFR_DISABLE);
 }
 
+static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+	gen12_init_clock_gating(dev_priv);
+
+	/* Wa_1409836686:dg1[a0] */
+	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
+		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
+			   DPT_GATING_DIS);
+}
+
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	if (!HAS_PCH_CNP(dev_priv))
@@ -7197,6 +7203,10 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
 	cnp_init_clock_gating(dev_priv);
 	gen9_init_clock_gating(dev_priv);
 
+	/* WAC6entrylatency:cfl */
+	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
+		   FBC_LLC_FULLY_OPEN);
+
 	/*
 	 * WaFbcTurnOffFbcWatermark:cfl
 	 * Display WA #0562: cfl
@@ -7216,6 +7226,10 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	gen9_init_clock_gating(dev_priv);
 
+	/* WAC6entrylatency:kbl */
+	I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
+		   FBC_LLC_FULLY_OPEN);
+
 	/* WaDisableSDEUnitClockGating:kbl */
 	if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0))
 		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
@@ -7590,7 +7604,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_GEN(dev_priv, 12))
+	if (IS_DG1(dev_priv))
+		dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+	else if (IS_GEN(dev_priv, 12))
 		dev_priv->display.init_clock_gating = tgl_init_clock_gating;
 	else if (IS_GEN(dev_priv, 11))
 		dev_priv->display.init_clock_gating = icl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index a2473594c2db..eab83e251dd5 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -49,8 +49,6 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
 			   const struct intel_bw_state *bw_state);
-int intel_enable_sagv(struct drm_i915_private *dev_priv);
-int intel_disable_sagv(struct drm_i915_private *dev_priv);
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
 void intel_sagv_post_plane_update(struct intel_atomic_state *state);
 bool skl_wm_level_equals(const struct skl_wm_level *l1,
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 5b3279262123..02ebf5a04a9b 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -555,3 +555,18 @@ out:
 	return ret ? ret : status;
 #undef COND
 }
+
+void intel_pcode_init(struct drm_i915_private *i915)
+{
+	int ret;
+
+	if (!IS_DGFX(i915))
+		return;
+
+	ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
+				DG1_UNCORE_GET_INIT_STATUS,
+				DG1_UNCORE_INIT_STATUS_COMPLETE,
+				DG1_UNCORE_INIT_STATUS_COMPLETE, 50);
+	if (ret)
+		drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
+}
diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
index 7fb95745a444..094c7b19c5d4 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
 int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
 		      u32 reply_mask, u32 reply, int timeout_base_ms);
 
+void intel_pcode_init(struct drm_i915_private *i915);
+
 #endif /* _INTEL_SIDEBAND_H */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 97ded2a59cf4..1c14a07eba7d 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1051,37 +1051,37 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
 
 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
-	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
 	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
 	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
-	GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
-	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
-	GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
-	GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
-	GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 };
 
@@ -1089,33 +1089,33 @@ static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 static const struct intel_forcewake_range __gen11_fw_ranges[] = {
 	GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
 	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x8800, 0x8bff, 0),
 	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
 	GEN_FW_RANGE(0x9560, 0x95ff, 0),
-	GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x24000, 0x2407f, 0),
-	GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x40000, 0x1bffff, 0),
 	GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
 	GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
@@ -1124,44 +1124,113 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = {
 	GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
 };
 
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
+/*
+ * *Must* be sorted by offset ranges! See intel_fw_table_check().
+ *
+ * Note that the spec lists several reserved/unused ranges that don't
+ * actually contain any registers.  In the table below we'll combine those
+ * reserved ranges with either the preceding or following range to keep the
+ * table small and lookups fast.
+ */
 static const struct intel_forcewake_range __gen12_fw_ranges[] = {
-	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
-	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+	GEN_FW_RANGE(0x0, 0x1fff, 0), /*
+		0x0   -  0xaff: reserved
+		0xb00 - 0x1fff: always on */
 	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT),
+	GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
-	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /*
+		0x4000 - 0x48ff: gt
+		0x4900 - 0x51ff: reserved */
+	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /*
+		0x5200 - 0x53ff: render
+		0x5400 - 0x54ff: reserved
+		0x5500 - 0x7fff: render */
+	GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8160, 0x81ff, 0), /*
+		0x8160 - 0x817f: reserved
+		0x8180 - 0x81ff: always on */
+	GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
-	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
-	GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
-	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
-	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
-	GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
-	GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
-	GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
-	GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
-	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
-	GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /*
+		0x8500 - 0x87ff: gt
+		0x8800 - 0x8fff: reserved
+		0x9000 - 0x947f: gt
+		0x9480 - 0x94cf: reserved */
+	GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x9560, 0x97ff, 0), /*
+		0x9560 - 0x95ff: always on
+		0x9600 - 0x97ff: reserved */
+	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT),
+	GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /*
+		0xb400 - 0xbf7f: gt
+		0xb480 - 0xbfff: reserved
+		0xc000 - 0xcfff: gt */
+	GEN_FW_RANGE(0xd000, 0xd7ff, 0),
+	GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT),
+	GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /*
+		0xdc00 - 0xddff: render
+		0xde00 - 0xde7f: reserved
+		0xde80 - 0xe8ff: render
+		0xe900 - 0xefff: reserved */
+	GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /*
+		 0xf000 - 0xffff: gt
+		0x10000 - 0x147ff: reserved */
+	GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /*
+		0x14800 - 0x14fff: render
+		0x15000 - 0x16dff: reserved
+		0x16e00 - 0x1bfff: render
+		0x1c000 - 0x1ffff: reserved */
+	GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0),
+	GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2),
+	GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
+	GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
+		0x24000 - 0x2407f: always on
+		0x24080 - 0x2417f: reserved */
+	GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /*
+		0x24180 - 0x241ff: gt
+		0x24200 - 0x249ff: reserved */
+	GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /*
+		0x24a00 - 0x24a7f: render
+		0x24a80 - 0x251ff: reserved */
+	GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /*
+		0x25200 - 0x252ff: gt
+		0x25300 - 0x255ff: reserved */
+	GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0),
+	GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /*
+		0x25680 - 0x256ff: VD2
+		0x25700 - 0x259ff: reserved */
+	GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0),
+	GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /*
+		0x25a80 - 0x25aff: VD2
+		0x25b00 - 0x2ffff: reserved */
+	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT),
 	GEN_FW_RANGE(0x40000, 0x1bffff, 0),
-	GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
-	GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
-	GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
-	GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
-	GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
-	GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
-	GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
+	GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
+		0x1c0000 - 0x1c2bff: VD0
+		0x1c2c00 - 0x1c2cff: reserved
+		0x1c2d00 - 0x1c2dff: VD0
+		0x1c2e00 - 0x1c3eff: reserved
+		0x1c3f00 - 0x1c3fff: VD0 */
+	GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0),
+	GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /*
+		0x1c8000 - 0x1ca0ff: VE0
+		0x1ca100 - 0x1cbeff: reserved
+		0x1cbf00 - 0x1cbfff: VE0 */
+	GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /*
+		0x1cc000 - 0x1ccfff: VD0
+		0x1cd000 - 0x1cffff: reserved */
+	GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /*
+		0x1d0000 - 0x1d2bff: VD2
+		0x1d2c00 - 0x1d2cff: reserved
+		0x1d2d00 - 0x1d2dff: VD2
+		0x1d2e00 - 0x1d3eff: reserved
+		0x1d3f00 - 0x1d3fff: VD2 */
 };
 
 static void
@@ -1491,7 +1560,7 @@ static int __fw_domain_init(struct intel_uncore *uncore,
 	d->id = domain_id;
 
 	BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
-	BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
+	BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT));
 	BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
@@ -1560,9 +1629,9 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
 		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
 			       FORCEWAKE_RENDER_GEN9,
 			       FORCEWAKE_ACK_RENDER_GEN9);
-		fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
-			       FORCEWAKE_BLITTER_GEN9,
-			       FORCEWAKE_ACK_BLITTER_GEN9);
+		fw_domain_init(uncore, FW_DOMAIN_ID_GT,
+			       FORCEWAKE_GT_GEN9,
+			       FORCEWAKE_ACK_GT_GEN9);
 
 		for (i = 0; i < I915_MAX_VCS; i++) {
 			if (!__HAS_ENGINE(emask, _VCS(i)))
@@ -1586,9 +1655,9 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
 		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
 			       FORCEWAKE_RENDER_GEN9,
 			       FORCEWAKE_ACK_RENDER_GEN9);
-		fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
-			       FORCEWAKE_BLITTER_GEN9,
-			       FORCEWAKE_ACK_BLITTER_GEN9);
+		fw_domain_init(uncore, FW_DOMAIN_ID_GT,
+			       FORCEWAKE_GT_GEN9,
+			       FORCEWAKE_ACK_GT_GEN9);
 		fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA,
 			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
 	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
@@ -1723,11 +1792,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
 	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 	 * the register BAR remains the same size for all the earlier
 	 * generations up to Ironlake.
+	 * For dgfx chips register range is expanded to 4MB.
 	 */
 	if (INTEL_GEN(i915) < 5)
 		mmio_size = 512 * 1024;
+	else if (IS_DGFX(i915))
+		mmio_size = 4 * 1024 * 1024;
 	else
 		mmio_size = 2 * 1024 * 1024;
+
 	uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 	if (uncore->regs == NULL) {
 		drm_err(&i915->drm, "failed to map registers\n");
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index c4b22d9d0b45..bd2467284295 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -46,7 +46,7 @@ struct intel_uncore_mmio_debug {
 
 enum forcewake_domain_id {
 	FW_DOMAIN_ID_RENDER = 0,
-	FW_DOMAIN_ID_BLITTER,
+	FW_DOMAIN_ID_GT,        /* also includes blitter engine */
 	FW_DOMAIN_ID_MEDIA,
 	FW_DOMAIN_ID_MEDIA_VDBOX0,
 	FW_DOMAIN_ID_MEDIA_VDBOX1,
@@ -60,7 +60,7 @@ enum forcewake_domain_id {
 
 enum forcewake_domains {
 	FORCEWAKE_RENDER	= BIT(FW_DOMAIN_ID_RENDER),
-	FORCEWAKE_BLITTER	= BIT(FW_DOMAIN_ID_BLITTER),
+	FORCEWAKE_GT		= BIT(FW_DOMAIN_ID_GT),
 	FORCEWAKE_MEDIA		= BIT(FW_DOMAIN_ID_MEDIA),
 	FORCEWAKE_MEDIA_VDBOX0	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
 	FORCEWAKE_MEDIA_VDBOX1	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c
index 71d84c7a5378..d07b39b8afd2 100644
--- a/drivers/gpu/drm/imx/dw_hdmi-imx.c
+++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c
@@ -111,10 +111,6 @@ static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
 	return 0;
 }
 
-static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
-{
-}
-
 static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
 {
 	struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder);
@@ -140,7 +136,6 @@ static int dw_hdmi_imx_atomic_check(struct drm_encoder *encoder,
 
 static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
 	.enable     = dw_hdmi_imx_encoder_enable,
-	.disable    = dw_hdmi_imx_encoder_disable,
 	.atomic_check = dw_hdmi_imx_atomic_check,
 };
 
@@ -219,15 +214,9 @@ static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
 	hdmi->dev = &pdev->dev;
 	encoder = &hdmi->encoder;
 
-	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
-	/*
-	 * If we failed to find the CRTC(s) which this encoder is
-	 * supposed to be connected to, it's because the CRTC has
-	 * not been registered yet.  Defer probing, and hope that
-	 * the required CRTC is added later.
-	 */
-	if (encoder->possible_crtcs == 0)
-		return -EPROBE_DEFER;
+	ret = imx_drm_encoder_parse_of(drm, encoder, dev->of_node);
+	if (ret)
+		return ret;
 
 	ret = dw_hdmi_imx_parse_dt(hdmi);
 	if (ret < 0)
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c
index bffa4a5487bd..d1a9841adeed 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -20,6 +20,7 @@
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_gem_cma_helper.h>
 #include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_managed.h>
 #include <drm/drm_of.h>
 #include <drm/drm_plane_helper.h>
 #include <drm/drm_probe_helper.h>
@@ -212,7 +213,9 @@ static int imx_drm_bind(struct device *dev)
 	drm->mode_config.allow_fb_modifiers = true;
 	drm->mode_config.normalize_zpos = true;
 
-	drm_mode_config_init(drm);
+	ret = drmm_mode_config_init(drm);
+	if (ret)
+		return ret;
 
 	ret = drm_vblank_init(drm, MAX_CRTC);
 	if (ret)
@@ -251,7 +254,6 @@ err_poll_fini:
 	drm_kms_helper_poll_fini(drm);
 	component_unbind_all(drm->dev, drm);
 err_kms:
-	drm_mode_config_cleanup(drm);
 	drm_dev_put(drm);
 
 	return ret;
@@ -267,11 +269,9 @@ static void imx_drm_unbind(struct device *dev)
 
 	component_unbind_all(drm->dev, drm);
 
-	drm_mode_config_cleanup(drm);
+	drm_dev_put(drm);
 
 	dev_set_drvdata(dev, NULL);
-
-	drm_dev_put(drm);
 }
 
 static const struct component_master_ops imx_drm_ops = {
diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c
index af757d1e21fe..41e2978cb1eb 100644
--- a/drivers/gpu/drm/imx/imx-ldb.c
+++ b/drivers/gpu/drm/imx/imx-ldb.c
@@ -62,7 +62,6 @@ struct imx_ldb_channel {
 	struct i2c_adapter *ddc;
 	int chno;
 	void *edid;
-	int edid_len;
 	struct drm_display_mode mode;
 	int mode_valid;
 	u32 bus_format;
@@ -536,15 +535,14 @@ static int imx_ldb_panel_ddc(struct device *dev,
 	}
 
 	if (!channel->ddc) {
+		int edid_len;
+
 		/* if no DDC available, fallback to hardcoded EDID */
 		dev_dbg(dev, "no ddc available\n");
 
-		edidp = of_get_property(child, "edid",
-					&channel->edid_len);
+		edidp = of_get_property(child, "edid", &edid_len);
 		if (edidp) {
-			channel->edid = kmemdup(edidp,
-						channel->edid_len,
-						GFP_KERNEL);
+			channel->edid = kmemdup(edidp, edid_len, GFP_KERNEL);
 		} else if (!channel->panel) {
 			/* fallback to display-timings node */
 			ret = of_get_drm_display_mode(child,
diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c
index 813bb6156a68..2a8d2e32e7b4 100644
--- a/drivers/gpu/drm/imx/imx-tve.c
+++ b/drivers/gpu/drm/imx/imx-tve.c
@@ -13,7 +13,6 @@
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
 #include <linux/regulator/consumer.h>
-#include <linux/spinlock.h>
 #include <linux/videodev2.h>
 
 #include <video/imx-ipu-v3.h>
@@ -104,8 +103,6 @@ struct imx_tve {
 	struct drm_connector connector;
 	struct drm_encoder encoder;
 	struct device *dev;
-	spinlock_t lock;	/* register lock */
-	bool enabled;
 	int mode;
 	int di_hsync_pin;
 	int di_vsync_pin;
@@ -129,30 +126,10 @@ static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
 	return container_of(e, struct imx_tve, encoder);
 }
 
-static void tve_lock(void *__tve)
-__acquires(&tve->lock)
-{
-	struct imx_tve *tve = __tve;
-
-	spin_lock(&tve->lock);
-}
-
-static void tve_unlock(void *__tve)
-__releases(&tve->lock)
-{
-	struct imx_tve *tve = __tve;
-
-	spin_unlock(&tve->lock);
-}
-
 static void tve_enable(struct imx_tve *tve)
 {
-	if (!tve->enabled) {
-		tve->enabled = true;
-		clk_prepare_enable(tve->clk);
-		regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
-				   TVE_EN, TVE_EN);
-	}
+	clk_prepare_enable(tve->clk);
+	regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN);
 
 	/* clear interrupt status register */
 	regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
@@ -169,11 +146,8 @@ static void tve_enable(struct imx_tve *tve)
 
 static void tve_disable(struct imx_tve *tve)
 {
-	if (tve->enabled) {
-		tve->enabled = false;
-		regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
-		clk_disable_unprepare(tve->clk);
-	}
+	regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
+	clk_disable_unprepare(tve->clk);
 }
 
 static int tve_setup_tvout(struct imx_tve *tve)
@@ -500,8 +474,7 @@ static struct regmap_config tve_regmap_config = {
 
 	.readable_reg = imx_tve_readable_reg,
 
-	.lock = tve_lock,
-	.unlock = tve_unlock,
+	.fast_io = true,
 
 	.max_register = 0xdc,
 };
@@ -511,7 +484,7 @@ static const char * const imx_tve_modes[] = {
 	[TVE_MODE_VGA] = "vga",
 };
 
-static const int of_get_tve_mode(struct device_node *np)
+static int of_get_tve_mode(struct device_node *np)
 {
 	const char *bm;
 	int ret, i;
@@ -544,7 +517,6 @@ static int imx_tve_bind(struct device *dev, struct device *master, void *data)
 	memset(tve, 0, sizeof(*tve));
 
 	tve->dev = dev;
-	spin_lock_init(&tve->lock);
 
 	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
 	if (ddc_node) {
diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/parallel-display.c
index 8232f512b9ed..2eb8df4697df 100644
--- a/drivers/gpu/drm/imx/parallel-display.c
+++ b/drivers/gpu/drm/imx/parallel-display.c
@@ -28,7 +28,6 @@ struct imx_parallel_display {
 	struct drm_bridge bridge;
 	struct device *dev;
 	void *edid;
-	int edid_len;
 	u32 bus_format;
 	u32 bus_flags;
 	struct drm_display_mode mode;
@@ -41,11 +40,6 @@ static inline struct imx_parallel_display *con_to_imxpd(struct drm_connector *c)
 	return container_of(c, struct imx_parallel_display, connector);
 }
 
-static inline struct imx_parallel_display *enc_to_imxpd(struct drm_encoder *e)
-{
-	return container_of(e, struct imx_parallel_display, encoder);
-}
-
 static inline struct imx_parallel_display *bridge_to_imxpd(struct drm_bridge *b)
 {
 	return container_of(b, struct imx_parallel_display, bridge);
@@ -310,6 +304,7 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
 	struct device_node *np = dev->of_node;
 	const u8 *edidp;
 	struct imx_parallel_display *imxpd;
+	int edid_len;
 	int ret;
 	u32 bus_format = 0;
 	const char *fmt;
@@ -323,9 +318,9 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
 	if (ret && ret != -ENODEV)
 		return ret;
 
-	edidp = of_get_property(np, "edid", &imxpd->edid_len);
+	edidp = of_get_property(np, "edid", &edid_len);
 	if (edidp)
-		imxpd->edid = kmemdup(edidp, imxpd->edid_len, GFP_KERNEL);
+		imxpd->edid = devm_kmemdup(dev, edidp, edid_len, GFP_KERNEL);
 
 	ret = of_property_read_string(np, "interface-pix-fmt", &fmt);
 	if (!ret) {
@@ -349,17 +344,8 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
 	return 0;
 }
 
-static void imx_pd_unbind(struct device *dev, struct device *master,
-	void *data)
-{
-	struct imx_parallel_display *imxpd = dev_get_drvdata(dev);
-
-	kfree(imxpd->edid);
-}
-
 static const struct component_ops imx_pd_ops = {
 	.bind	= imx_pd_bind,
-	.unbind	= imx_pd_unbind,
 };
 
 static int imx_pd_probe(struct platform_device *pdev)
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index ef8703d4a74e..83a461bdeea8 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -628,6 +628,7 @@ static int panfrost_probe(struct platform_device *pdev)
 err_out1:
 	pm_runtime_disable(pfdev->dev);
 	panfrost_device_fini(pfdev);
+	pm_runtime_set_suspended(pfdev->dev);
 err_out0:
 	drm_dev_put(ddev);
 	return err;
@@ -642,9 +643,9 @@ static int panfrost_remove(struct platform_device *pdev)
 	panfrost_gem_shrinker_cleanup(ddev);
 
 	pm_runtime_get_sync(pfdev->dev);
-	panfrost_device_fini(pfdev);
-	pm_runtime_put_sync_suspend(pfdev->dev);
 	pm_runtime_disable(pfdev->dev);
+	panfrost_device_fini(pfdev);
+	pm_runtime_set_suspended(pfdev->dev);
 
 	drm_dev_put(ddev);
 	return 0;
diff --git a/drivers/gpu/drm/panfrost/panfrost_gem.c b/drivers/gpu/drm/panfrost/panfrost_gem.c
index fb9f7334ce18..57a31dd0ffed 100644
--- a/drivers/gpu/drm/panfrost/panfrost_gem.c
+++ b/drivers/gpu/drm/panfrost/panfrost_gem.c
@@ -105,14 +105,12 @@ void panfrost_gem_mapping_put(struct panfrost_gem_mapping *mapping)
 	kref_put(&mapping->refcount, panfrost_gem_mapping_release);
 }
 
-void panfrost_gem_teardown_mappings(struct panfrost_gem_object *bo)
+void panfrost_gem_teardown_mappings_locked(struct panfrost_gem_object *bo)
 {
 	struct panfrost_gem_mapping *mapping;
 
-	mutex_lock(&bo->mappings.lock);
 	list_for_each_entry(mapping, &bo->mappings.list, node)
 		panfrost_gem_teardown_mapping(mapping);
-	mutex_unlock(&bo->mappings.lock);
 }
 
 int panfrost_gem_open(struct drm_gem_object *obj, struct drm_file *file_priv)
diff --git a/drivers/gpu/drm/panfrost/panfrost_gem.h b/drivers/gpu/drm/panfrost/panfrost_gem.h
index b3517ff9630c..8088d5fd8480 100644
--- a/drivers/gpu/drm/panfrost/panfrost_gem.h
+++ b/drivers/gpu/drm/panfrost/panfrost_gem.h
@@ -82,7 +82,7 @@ struct panfrost_gem_mapping *
 panfrost_gem_mapping_get(struct panfrost_gem_object *bo,
 			 struct panfrost_file_priv *priv);
 void panfrost_gem_mapping_put(struct panfrost_gem_mapping *mapping);
-void panfrost_gem_teardown_mappings(struct panfrost_gem_object *bo);
+void panfrost_gem_teardown_mappings_locked(struct panfrost_gem_object *bo);
 
 void panfrost_gem_shrinker_init(struct drm_device *dev);
 void panfrost_gem_shrinker_cleanup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c b/drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c
index 288e46c40673..1b9f68d8e9aa 100644
--- a/drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c
+++ b/drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c
@@ -40,18 +40,26 @@ static bool panfrost_gem_purge(struct drm_gem_object *obj)
 {
 	struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj);
 	struct panfrost_gem_object *bo = to_panfrost_bo(obj);
+	bool ret = false;
 
 	if (atomic_read(&bo->gpu_usecount))
 		return false;
 
-	if (!mutex_trylock(&shmem->pages_lock))
+	if (!mutex_trylock(&bo->mappings.lock))
 		return false;
 
-	panfrost_gem_teardown_mappings(bo);
+	if (!mutex_trylock(&shmem->pages_lock))
+		goto unlock_mappings;
+
+	panfrost_gem_teardown_mappings_locked(bo);
 	drm_gem_shmem_purge_locked(obj);
+	ret = true;
 
 	mutex_unlock(&shmem->pages_lock);
-	return true;
+
+unlock_mappings:
+	mutex_unlock(&bo->mappings.lock);
+	return ret;
 }
 
 static unsigned long
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 6969327722d1..28cb8ced91b9 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1990,6 +1990,7 @@ struct radeon_asic {
 		int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
 		u32 (*get_current_sclk)(struct radeon_device *rdev);
 		u32 (*get_current_mclk)(struct radeon_device *rdev);
+		u16 (*get_current_vddc)(struct radeon_device *rdev);
 	} dpm;
 	/* pageflipping */
 	struct {
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 495700d16fc9..8becbe09af2f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1513,6 +1513,7 @@ static struct radeon_asic sumo_asic = {
 		.force_performance_level = &sumo_dpm_force_performance_level,
 		.get_current_sclk = &sumo_dpm_get_current_sclk,
 		.get_current_mclk = &sumo_dpm_get_current_mclk,
+		.get_current_vddc = &sumo_dpm_get_current_vddc,
 	},
 	.pflip = {
 		.page_flip = &evergreen_page_flip,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index a74fa18cd27b..24644daead53 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -596,6 +596,7 @@ int sumo_dpm_force_performance_level(struct radeon_device *rdev,
 				     enum radeon_dpm_forced_level level);
 u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev);
 u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev);
+u16 sumo_dpm_get_current_vddc(struct radeon_device *rdev);
 
 /*
  * cayman
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 05c4196a8212..65d172b13e06 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -737,6 +737,26 @@ static ssize_t radeon_hwmon_show_sclk(struct device *dev,
 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, radeon_hwmon_show_sclk, NULL,
 			  0);
 
+static ssize_t radeon_hwmon_show_vddc(struct device *dev,
+				      struct device_attribute *attr, char *buf)
+{
+	struct radeon_device *rdev = dev_get_drvdata(dev);
+	struct drm_device *ddev = rdev->ddev;
+	u16 vddc = 0;
+
+	/* Can't get vddc when the card is off */
+	if ((rdev->flags & RADEON_IS_PX) &&
+		(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+		return -EINVAL;
+
+	if (rdev->asic->dpm.get_current_vddc)
+		vddc = rdev->asic->dpm.get_current_vddc(rdev);
+
+	return snprintf(buf, PAGE_SIZE, "%u\n", vddc);
+}
+
+static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, radeon_hwmon_show_vddc, NULL,
+			  0);
 
 static struct attribute *hwmon_attributes[] = {
 	&sensor_dev_attr_temp1_input.dev_attr.attr,
@@ -747,6 +767,7 @@ static struct attribute *hwmon_attributes[] = {
 	&sensor_dev_attr_pwm1_min.dev_attr.attr,
 	&sensor_dev_attr_pwm1_max.dev_attr.attr,
 	&sensor_dev_attr_freq1_input.dev_attr.attr,
+	&sensor_dev_attr_in0_input.dev_attr.attr,
 	NULL
 };
 
@@ -765,7 +786,13 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
 	     attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 	     attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 	     attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
-	     attr == &sensor_dev_attr_freq1_input.dev_attr.attr))
+	     attr == &sensor_dev_attr_freq1_input.dev_attr.attr ||
+	     attr == &sensor_dev_attr_in0_input.dev_attr.attr))
+		return 0;
+
+	/* Skip vddc attribute if get_current_vddc is not implemented */
+	if(attr == &sensor_dev_attr_in0_input.dev_attr.attr &&
+		!rdev->asic->dpm.get_current_vddc)
 		return 0;
 
 	/* Skip fan attributes if fan is not present */
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c
index b95d5d390caf..f74f381af05f 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -1865,6 +1865,26 @@ u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev)
 	return pi->sys_info.bootup_uma_clk;
 }
 
+u16 sumo_dpm_get_current_vddc(struct radeon_device *rdev)
+{
+	struct sumo_power_info *pi = sumo_get_pi(rdev);
+	struct radeon_ps *rps = &pi->current_rps;
+	struct sumo_ps *ps = sumo_get_ps(rps);
+	struct sumo_pl *pl;
+	u32 current_index =
+		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
+		CURR_INDEX_SHIFT;
+
+	if (current_index == BOOST_DPM_LEVEL) {
+		pl = &pi->boost_pl;
+	} else if (current_index >= ps->num_levels) {
+		return 0;
+	} else {
+		pl = &ps->levels[current_index];
+	}
+	return sumo_convert_voltage_index_to_value(rdev, pl->vddc_index);
+}
+
 void sumo_dpm_fini(struct radeon_device *rdev)
 {
 	int i;
diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c
index f290a9a942dc..a21a6c53ffcf 100644
--- a/drivers/gpu/drm/vc4/vc4_bo.c
+++ b/drivers/gpu/drm/vc4/vc4_bo.c
@@ -467,7 +467,7 @@ struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t unaligned_size,
 	}
 
 	if (IS_ERR(cma_obj)) {
-		struct drm_printer p = drm_info_printer(vc4->dev->dev);
+		struct drm_printer p = drm_info_printer(vc4->base.dev);
 		DRM_ERROR("Failed to allocate from CMA:\n");
 		vc4_bo_stats_print(&p, vc4);
 		return ERR_PTR(-ENOMEM);
@@ -608,7 +608,7 @@ static void vc4_bo_cache_time_work(struct work_struct *work)
 {
 	struct vc4_dev *vc4 =
 		container_of(work, struct vc4_dev, bo_cache.time_work);
-	struct drm_device *dev = vc4->dev;
+	struct drm_device *dev = &vc4->base;
 
 	mutex_lock(&vc4->bo_lock);
 	vc4_bo_cache_free_old(dev);
@@ -1023,6 +1023,7 @@ int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
 	return 0;
 }
 
+static void vc4_bo_cache_destroy(struct drm_device *dev, void *unused);
 int vc4_bo_cache_init(struct drm_device *dev)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
@@ -1051,10 +1052,10 @@ int vc4_bo_cache_init(struct drm_device *dev)
 	INIT_WORK(&vc4->bo_cache.time_work, vc4_bo_cache_time_work);
 	timer_setup(&vc4->bo_cache.time_timer, vc4_bo_cache_time_timer, 0);
 
-	return 0;
+	return drmm_add_action_or_reset(dev, vc4_bo_cache_destroy, NULL);
 }
 
-void vc4_bo_cache_destroy(struct drm_device *dev)
+static void vc4_bo_cache_destroy(struct drm_device *dev, void *unused)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	int i;
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 8f10f609e4f8..2cd97a39c286 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -245,37 +245,37 @@ static int vc4_drm_bind(struct device *dev)
 
 	dev->coherent_dma_mask = DMA_BIT_MASK(32);
 
-	vc4 = devm_kzalloc(dev, sizeof(*vc4), GFP_KERNEL);
-	if (!vc4)
-		return -ENOMEM;
-
 	/* If VC4 V3D is missing, don't advertise render nodes. */
 	node = of_find_matching_node_and_match(NULL, vc4_v3d_dt_match, NULL);
 	if (!node || !of_device_is_available(node))
 		vc4_drm_driver.driver_features &= ~DRIVER_RENDER;
 	of_node_put(node);
 
-	drm = drm_dev_alloc(&vc4_drm_driver, dev);
-	if (IS_ERR(drm))
-		return PTR_ERR(drm);
+	vc4 = devm_drm_dev_alloc(dev, &vc4_drm_driver, struct vc4_dev, base);
+	if (IS_ERR(vc4))
+		return PTR_ERR(vc4);
+
+	drm = &vc4->base;
 	platform_set_drvdata(pdev, drm);
-	vc4->dev = drm;
-	drm->dev_private = vc4;
 	INIT_LIST_HEAD(&vc4->debugfs_list);
 
 	mutex_init(&vc4->bin_bo_lock);
 
 	ret = vc4_bo_cache_init(drm);
 	if (ret)
-		goto dev_put;
+		return ret;
 
-	drm_mode_config_init(drm);
+	ret = drmm_mode_config_init(drm);
+	if (ret)
+		return ret;
 
-	vc4_gem_init(drm);
+	ret = vc4_gem_init(drm);
+	if (ret)
+		return ret;
 
 	ret = component_bind_all(dev, drm);
 	if (ret)
-		goto gem_destroy;
+		return ret;
 
 	ret = vc4_plane_create_additional_planes(drm);
 	if (ret)
@@ -300,30 +300,17 @@ static int vc4_drm_bind(struct device *dev)
 
 unbind_all:
 	component_unbind_all(dev, drm);
-gem_destroy:
-	vc4_gem_destroy(drm);
-	drm_mode_config_cleanup(drm);
-	vc4_bo_cache_destroy(drm);
-dev_put:
-	drm_dev_put(drm);
+
 	return ret;
 }
 
 static void vc4_drm_unbind(struct device *dev)
 {
 	struct drm_device *drm = dev_get_drvdata(dev);
-	struct vc4_dev *vc4 = to_vc4_dev(drm);
 
 	drm_dev_unregister(drm);
 
 	drm_atomic_helper_shutdown(drm);
-
-	drm_mode_config_cleanup(drm);
-
-	drm_atomic_private_obj_fini(&vc4->load_tracker);
-	drm_atomic_private_obj_fini(&vc4->ctm_manager);
-
-	drm_dev_put(drm);
 }
 
 static const struct component_master_ops vc4_drm_ops = {
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index fe078648e0f5..137c382256d5 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -14,6 +14,7 @@
 #include <drm/drm_device.h>
 #include <drm/drm_encoder.h>
 #include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_managed.h>
 #include <drm/drm_mm.h>
 #include <drm/drm_modeset_lock.h>
 
@@ -71,7 +72,7 @@ struct vc4_perfmon {
 };
 
 struct vc4_dev {
-	struct drm_device *dev;
+	struct drm_device base;
 
 	struct vc4_hvs *hvs;
 	struct vc4_v3d *v3d;
@@ -234,7 +235,7 @@ struct vc4_dev {
 static inline struct vc4_dev *
 to_vc4_dev(struct drm_device *dev)
 {
-	return (struct vc4_dev *)dev->dev_private;
+	return container_of(dev, struct vc4_dev, base);
 }
 
 struct vc4_bo {
@@ -808,7 +809,6 @@ struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
 						 struct sg_table *sgt);
 int vc4_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
 int vc4_bo_cache_init(struct drm_device *dev);
-void vc4_bo_cache_destroy(struct drm_device *dev);
 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
 void vc4_bo_dec_usecnt(struct vc4_bo *bo);
 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
@@ -873,8 +873,7 @@ extern struct platform_driver vc4_dsi_driver;
 extern const struct dma_fence_ops vc4_fence_ops;
 
 /* vc4_gem.c */
-void vc4_gem_init(struct drm_device *dev);
-void vc4_gem_destroy(struct drm_device *dev);
+int vc4_gem_init(struct drm_device *dev);
 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file_priv);
 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
index 9f01ddd5b932..b641252939d8 100644
--- a/drivers/gpu/drm/vc4/vc4_gem.c
+++ b/drivers/gpu/drm/vc4/vc4_gem.c
@@ -314,16 +314,16 @@ vc4_reset_work(struct work_struct *work)
 	struct vc4_dev *vc4 =
 		container_of(work, struct vc4_dev, hangcheck.reset_work);
 
-	vc4_save_hang_state(vc4->dev);
+	vc4_save_hang_state(&vc4->base);
 
-	vc4_reset(vc4->dev);
+	vc4_reset(&vc4->base);
 }
 
 static void
 vc4_hangcheck_elapsed(struct timer_list *t)
 {
 	struct vc4_dev *vc4 = from_timer(vc4, t, hangcheck.timer);
-	struct drm_device *dev = vc4->dev;
+	struct drm_device *dev = &vc4->base;
 	uint32_t ct0ca, ct1ca;
 	unsigned long irqflags;
 	struct vc4_exec_info *bin_exec, *render_exec;
@@ -1000,7 +1000,7 @@ vc4_job_handle_completed(struct vc4_dev *vc4)
 		list_del(&exec->head);
 
 		spin_unlock_irqrestore(&vc4->job_lock, irqflags);
-		vc4_complete_exec(vc4->dev, exec);
+		vc4_complete_exec(&vc4->base, exec);
 		spin_lock_irqsave(&vc4->job_lock, irqflags);
 	}
 
@@ -1258,13 +1258,13 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
 	return 0;
 
 fail:
-	vc4_complete_exec(vc4->dev, exec);
+	vc4_complete_exec(&vc4->base, exec);
 
 	return ret;
 }
 
-void
-vc4_gem_init(struct drm_device *dev)
+static void vc4_gem_destroy(struct drm_device *dev, void *unused);
+int vc4_gem_init(struct drm_device *dev)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 
@@ -1285,10 +1285,11 @@ vc4_gem_init(struct drm_device *dev)
 
 	INIT_LIST_HEAD(&vc4->purgeable.list);
 	mutex_init(&vc4->purgeable.lock);
+
+	return drmm_add_action_or_reset(dev, vc4_gem_destroy, NULL);
 }
 
-void
-vc4_gem_destroy(struct drm_device *dev)
+static void vc4_gem_destroy(struct drm_device *dev, void *unused)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
 
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 0bd5ea435120..cccd341e5d67 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -562,7 +562,7 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	struct drm_device *drm = dev_get_drvdata(master);
-	struct vc4_dev *vc4 = drm->dev_private;
+	struct vc4_dev *vc4 = to_vc4_dev(drm);
 	struct vc4_hvs *hvs = NULL;
 	int ret;
 	u32 dispctrl;
@@ -681,7 +681,7 @@ static void vc4_hvs_unbind(struct device *dev, struct device *master,
 			   void *data)
 {
 	struct drm_device *drm = dev_get_drvdata(master);
-	struct vc4_dev *vc4 = drm->dev_private;
+	struct vc4_dev *vc4 = to_vc4_dev(drm);
 	struct vc4_hvs *hvs = vc4->hvs;
 
 	if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter))
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 149825ff5df8..2b951cae04ad 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -51,7 +51,7 @@ static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
 					       struct drm_private_obj *manager)
 {
 	struct drm_device *dev = state->dev;
-	struct vc4_dev *vc4 = dev->dev_private;
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
 	struct drm_private_state *priv_state;
 	int ret;
 
@@ -93,6 +93,29 @@ static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
 	.atomic_destroy_state = vc4_ctm_destroy_state,
 };
 
+static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused)
+{
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
+
+	drm_atomic_private_obj_fini(&vc4->ctm_manager);
+}
+
+static int vc4_ctm_obj_init(struct vc4_dev *vc4)
+{
+	struct vc4_ctm_state *ctm_state;
+
+	drm_modeset_lock_init(&vc4->ctm_state_lock);
+
+	ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
+	if (!ctm_state)
+		return -ENOMEM;
+
+	drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base,
+				    &vc4_ctm_state_funcs);
+
+	return drmm_add_action(&vc4->base, vc4_ctm_obj_fini, NULL);
+}
+
 /* Converts a DRM S31.32 value to the HW S0.9 format. */
 static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
 {
@@ -609,6 +632,34 @@ static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
 	.atomic_destroy_state = vc4_load_tracker_destroy_state,
 };
 
+static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused)
+{
+	struct vc4_dev *vc4 = to_vc4_dev(dev);
+
+	if (!vc4->load_tracker_available)
+		return;
+
+	drm_atomic_private_obj_fini(&vc4->load_tracker);
+}
+
+static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
+{
+	struct vc4_load_tracker_state *load_state;
+
+	if (!vc4->load_tracker_available)
+		return 0;
+
+	load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
+	if (!load_state)
+		return -ENOMEM;
+
+	drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker,
+				    &load_state->base,
+				    &vc4_load_tracker_state_funcs);
+
+	return drmm_add_action(&vc4->base, vc4_load_tracker_obj_fini, NULL);
+}
+
 #define NUM_OUTPUTS  6
 #define NUM_CHANNELS 3
 
@@ -711,8 +762,6 @@ static const struct drm_mode_config_funcs vc4_mode_funcs = {
 int vc4_kms_load(struct drm_device *dev)
 {
 	struct vc4_dev *vc4 = to_vc4_dev(dev);
-	struct vc4_ctm_state *ctm_state;
-	struct vc4_load_tracker_state *load_state;
 	bool is_vc5 = of_device_is_compatible(dev->dev->of_node,
 					      "brcm,bcm2711-vc5");
 	int ret;
@@ -751,26 +800,13 @@ int vc4_kms_load(struct drm_device *dev)
 	dev->mode_config.async_page_flip = true;
 	dev->mode_config.allow_fb_modifiers = true;
 
-	drm_modeset_lock_init(&vc4->ctm_state_lock);
-
-	ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
-	if (!ctm_state)
-		return -ENOMEM;
-
-	drm_atomic_private_obj_init(dev, &vc4->ctm_manager, &ctm_state->base,
-				    &vc4_ctm_state_funcs);
-
-	if (vc4->load_tracker_available) {
-		load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
-		if (!load_state) {
-			drm_atomic_private_obj_fini(&vc4->ctm_manager);
-			return -ENOMEM;
-		}
+	ret = vc4_ctm_obj_init(vc4);
+	if (ret)
+		return ret;
 
-		drm_atomic_private_obj_init(dev, &vc4->load_tracker,
-					    &load_state->base,
-					    &vc4_load_tracker_state_funcs);
-	}
+	ret = vc4_load_tracker_obj_init(vc4);
+	if (ret)
+		return ret;
 
 	drm_mode_config_reset(dev);
 
diff --git a/drivers/gpu/drm/vc4/vc4_v3d.c b/drivers/gpu/drm/vc4/vc4_v3d.c
index f7ab979721b3..65d0dac69b0b 100644
--- a/drivers/gpu/drm/vc4/vc4_v3d.c
+++ b/drivers/gpu/drm/vc4/vc4_v3d.c
@@ -168,7 +168,7 @@ static void vc4_v3d_init_hw(struct drm_device *dev)
 
 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4)
 {
-	struct drm_device *dev = vc4->dev;
+	struct drm_device *dev = &vc4->base;
 	unsigned long irqflags;
 	int slot;
 	uint64_t seqno = 0;
@@ -246,7 +246,7 @@ static int bin_bo_alloc(struct vc4_dev *vc4)
 	INIT_LIST_HEAD(&list);
 
 	while (true) {
-		struct vc4_bo *bo = vc4_bo_create(vc4->dev, size, true,
+		struct vc4_bo *bo = vc4_bo_create(&vc4->base, size, true,
 						  VC4_BO_TYPE_BIN);
 
 		if (IS_ERR(bo)) {
@@ -361,7 +361,7 @@ static int vc4_v3d_runtime_suspend(struct device *dev)
 	struct vc4_v3d *v3d = dev_get_drvdata(dev);
 	struct vc4_dev *vc4 = v3d->vc4;
 
-	vc4_irq_uninstall(vc4->dev);
+	vc4_irq_uninstall(&vc4->base);
 
 	clk_disable_unprepare(v3d->clk);
 
@@ -378,11 +378,11 @@ static int vc4_v3d_runtime_resume(struct device *dev)
 	if (ret != 0)
 		return ret;
 
-	vc4_v3d_init_hw(vc4->dev);
+	vc4_v3d_init_hw(&vc4->base);
 
 	/* We disabled the IRQ as part of vc4_irq_uninstall in suspend. */
-	enable_irq(vc4->dev->irq);
-	vc4_irq_postinstall(vc4->dev);
+	enable_irq(vc4->base.irq);
+	vc4_irq_postinstall(&vc4->base);
 
 	return 0;
 }
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index b3dae9ec1a38..d166ee262ce4 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -133,73 +133,6 @@ enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
 }
 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
 
-bool ipu_pixelformat_is_planar(u32 pixelformat)
-{
-	switch (pixelformat) {
-	case V4L2_PIX_FMT_YUV420:
-	case V4L2_PIX_FMT_YVU420:
-	case V4L2_PIX_FMT_YUV422P:
-	case V4L2_PIX_FMT_NV12:
-	case V4L2_PIX_FMT_NV21:
-	case V4L2_PIX_FMT_NV16:
-	case V4L2_PIX_FMT_NV61:
-		return true;
-	}
-
-	return false;
-}
-EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
-
-enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
-{
-	switch (mbus_code & 0xf000) {
-	case 0x1000:
-		return IPUV3_COLORSPACE_RGB;
-	case 0x2000:
-		return IPUV3_COLORSPACE_YUV;
-	default:
-		return IPUV3_COLORSPACE_UNKNOWN;
-	}
-}
-EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
-
-int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
-{
-	switch (pixelformat) {
-	case V4L2_PIX_FMT_YUV420:
-	case V4L2_PIX_FMT_YVU420:
-	case V4L2_PIX_FMT_YUV422P:
-	case V4L2_PIX_FMT_NV12:
-	case V4L2_PIX_FMT_NV21:
-	case V4L2_PIX_FMT_NV16:
-	case V4L2_PIX_FMT_NV61:
-		/*
-		 * for the planar YUV formats, the stride passed to
-		 * cpmem must be the stride in bytes of the Y plane.
-		 * And all the planar YUV formats have an 8-bit
-		 * Y component.
-		 */
-		return (8 * pixel_stride) >> 3;
-	case V4L2_PIX_FMT_RGB565:
-	case V4L2_PIX_FMT_YUYV:
-	case V4L2_PIX_FMT_UYVY:
-		return (16 * pixel_stride) >> 3;
-	case V4L2_PIX_FMT_BGR24:
-	case V4L2_PIX_FMT_RGB24:
-		return (24 * pixel_stride) >> 3;
-	case V4L2_PIX_FMT_BGR32:
-	case V4L2_PIX_FMT_RGB32:
-	case V4L2_PIX_FMT_XBGR32:
-	case V4L2_PIX_FMT_XRGB32:
-		return (32 * pixel_stride) >> 3;
-	default:
-		break;
-	}
-
-	return -EINVAL;
-}
-EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
-
 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
 			    bool hflip, bool vflip)
 {
diff --git a/drivers/hv/hv_balloon.c b/drivers/hv/hv_balloon.c
index b64d2efbefe7..eb56e09ae15f 100644
--- a/drivers/hv/hv_balloon.c
+++ b/drivers/hv/hv_balloon.c
@@ -1275,7 +1275,7 @@ static void balloon_up(struct work_struct *dummy)
 
 	/* Refuse to balloon below the floor. */
 	if (avail_pages < num_pages || avail_pages - num_pages < floor) {
-		pr_warn("Balloon request will be partially fulfilled. %s\n",
+		pr_info("Balloon request will be partially fulfilled. %s\n",
 			avail_pages < num_pages ? "Not enough memory." :
 			"Balloon floor reached.");
 
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a4f473ef4e5c..a97a9d058198 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -733,7 +733,7 @@ config I2C_LPC2K
 
 config I2C_MLXBF
         tristate "Mellanox BlueField I2C controller"
-        depends on ARM64
+        depends on MELLANOX_PLATFORM && ARM64
         help
           Enabling this option will add I2C SMBus support for Mellanox BlueField
           system.
diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses/i2c-designware-slave.c
index 44974b53a626..0d15f4c1e9f7 100644
--- a/drivers/i2c/busses/i2c-designware-slave.c
+++ b/drivers/i2c/busses/i2c-designware-slave.c
@@ -159,7 +159,6 @@ static int i2c_dw_irq_handler_slave(struct dw_i2c_dev *dev)
 	u32 raw_stat, stat, enabled, tmp;
 	u8 val = 0, slave_activity;
 
-	regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
 	regmap_read(dev->map, DW_IC_ENABLE, &enabled);
 	regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_stat);
 	regmap_read(dev->map, DW_IC_STATUS, &tmp);
@@ -168,32 +167,30 @@ static int i2c_dw_irq_handler_slave(struct dw_i2c_dev *dev)
 	if (!enabled || !(raw_stat & ~DW_IC_INTR_ACTIVITY) || !dev->slave)
 		return 0;
 
+	stat = i2c_dw_read_clear_intrbits_slave(dev);
 	dev_dbg(dev->dev,
 		"%#x STATUS SLAVE_ACTIVITY=%#x : RAW_INTR_STAT=%#x : INTR_STAT=%#x\n",
 		enabled, slave_activity, raw_stat, stat);
 
-	if ((stat & DW_IC_INTR_RX_FULL) && (stat & DW_IC_INTR_STOP_DET))
-		i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, &val);
+	if (stat & DW_IC_INTR_RX_FULL) {
+		if (dev->status != STATUS_WRITE_IN_PROGRESS) {
+			dev->status = STATUS_WRITE_IN_PROGRESS;
+			i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED,
+					&val);
+		}
+
+		regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
+		val = tmp;
+		if (!i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED,
+				     &val))
+			dev_vdbg(dev->dev, "Byte %X acked!", val);
+	}
 
 	if (stat & DW_IC_INTR_RD_REQ) {
 		if (slave_activity) {
-			if (stat & DW_IC_INTR_RX_FULL) {
-				regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
-				val = tmp;
-
-				if (!i2c_slave_event(dev->slave,
-						     I2C_SLAVE_WRITE_RECEIVED,
-						     &val)) {
-					dev_vdbg(dev->dev, "Byte %X acked!",
-						 val);
-				}
-				regmap_read(dev->map, DW_IC_CLR_RD_REQ, &tmp);
-				stat = i2c_dw_read_clear_intrbits_slave(dev);
-			} else {
-				regmap_read(dev->map, DW_IC_CLR_RD_REQ, &tmp);
-				regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &tmp);
-				stat = i2c_dw_read_clear_intrbits_slave(dev);
-			}
+			regmap_read(dev->map, DW_IC_CLR_RD_REQ, &tmp);
+
+			dev->status = STATUS_READ_IN_PROGRESS;
 			if (!i2c_slave_event(dev->slave,
 					     I2C_SLAVE_READ_REQUESTED,
 					     &val))
@@ -205,21 +202,11 @@ static int i2c_dw_irq_handler_slave(struct dw_i2c_dev *dev)
 		if (!i2c_slave_event(dev->slave, I2C_SLAVE_READ_PROCESSED,
 				     &val))
 			regmap_read(dev->map, DW_IC_CLR_RX_DONE, &tmp);
-
-		i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
-		stat = i2c_dw_read_clear_intrbits_slave(dev);
-		return 1;
 	}
 
-	if (stat & DW_IC_INTR_RX_FULL) {
-		regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
-		val = tmp;
-		if (!i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED,
-				     &val))
-			dev_vdbg(dev->dev, "Byte %X acked!", val);
-	} else {
+	if (stat & DW_IC_INTR_STOP_DET) {
+		dev->status = STATUS_IDLE;
 		i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
-		stat = i2c_dw_read_clear_intrbits_slave(dev);
 	}
 
 	return 1;
@@ -230,7 +217,6 @@ static irqreturn_t i2c_dw_isr_slave(int this_irq, void *dev_id)
 	struct dw_i2c_dev *dev = dev_id;
 	int ret;
 
-	i2c_dw_read_clear_intrbits_slave(dev);
 	ret = i2c_dw_irq_handler_slave(dev);
 	if (ret > 0)
 		complete(&dev->cmd_complete);
diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c
index ee59e0da082d..33574d40ea9c 100644
--- a/drivers/i2c/busses/i2c-mlxbf.c
+++ b/drivers/i2c/busses/i2c-mlxbf.c
@@ -62,10 +62,8 @@
  * Master. Default value is set to 400MHz.
  */
 #define MLXBF_I2C_TYU_PLL_OUT_FREQ  (400 * 1000 * 1000)
-/* Reference clock for Bluefield 1 - 156 MHz. */
-#define MLXBF_I2C_TYU_PLL_IN_FREQ   (156 * 1000 * 1000)
-/* Reference clock for BlueField 2 - 200 MHz. */
-#define MLXBF_I2C_YU_PLL_IN_FREQ    (200 * 1000 * 1000)
+/* Reference clock for Bluefield - 156 MHz. */
+#define MLXBF_I2C_PLL_IN_FREQ       (156 * 1000 * 1000)
 
 /* Constant used to determine the PLL frequency. */
 #define MLNXBF_I2C_COREPLL_CONST    16384
@@ -489,44 +487,6 @@ static struct mutex mlxbf_i2c_bus_lock;
 
 #define MLXBF_I2C_FREQUENCY_1GHZ  1000000000
 
-static void mlxbf_i2c_write(void __iomem *io, int reg, u32 val)
-{
-	writel(val, io + reg);
-}
-
-static u32 mlxbf_i2c_read(void __iomem *io, int reg)
-{
-	return readl(io + reg);
-}
-
-/*
- * This function is used to read data from Master GW Data Descriptor.
- * Data bytes in the Master GW Data Descriptor are shifted left so the
- * data starts at the MSB of the descriptor registers as set by the
- * underlying hardware. TYU_READ_DATA enables byte swapping while
- * reading data bytes, and MUST be called by the SMBus read routines
- * to copy data from the 32 * 32-bit HW Data registers a.k.a Master GW
- * Data Descriptor.
- */
-static u32 mlxbf_i2c_read_data(void __iomem *io, int reg)
-{
-	return (u32)be32_to_cpu(mlxbf_i2c_read(io, reg));
-}
-
-/*
- * This function is used to write data to the Master GW Data Descriptor.
- * Data copied to the Master GW Data Descriptor MUST be shifted left so
- * the data starts at the MSB of the descriptor registers as required by
- * the underlying hardware. TYU_WRITE_DATA enables byte swapping when
- * writing data bytes, and MUST be called by the SMBus write routines to
- * copy data to the 32 * 32-bit HW Data registers a.k.a Master GW Data
- * Descriptor.
- */
-static void mlxbf_i2c_write_data(void __iomem *io, int reg, u32 val)
-{
-	mlxbf_i2c_write(io, reg, (u32)cpu_to_be32(val));
-}
-
 /*
  * Function to poll a set of bits at a specific address; it checks whether
  * the bits are equal to zero when eq_zero is set to 'true', and not equal
@@ -541,7 +501,7 @@ static u32 mlxbf_smbus_poll(void __iomem *io, u32 addr, u32 mask,
 	timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1;
 
 	do {
-		bits = mlxbf_i2c_read(io, addr) & mask;
+		bits = readl(io + addr) & mask;
 		if (eq_zero ? bits == 0 : bits != 0)
 			return eq_zero ? 1 : bits;
 		udelay(MLXBF_I2C_POLL_FREQ_IN_USEC);
@@ -609,16 +569,16 @@ static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv)
 			 MLXBF_I2C_SMBUS_TIMEOUT);
 
 	/* Read cause status bits. */
-	cause_status_bits = mlxbf_i2c_read(priv->mst_cause->io,
-					   MLXBF_I2C_CAUSE_ARBITER);
+	cause_status_bits = readl(priv->mst_cause->io +
+					MLXBF_I2C_CAUSE_ARBITER);
 	cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK;
 
 	/*
 	 * Parse both Cause and Master GW bits, then return transaction status.
 	 */
 
-	master_status_bits = mlxbf_i2c_read(priv->smbus->io,
-					    MLXBF_I2C_SMBUS_MASTER_STATUS);
+	master_status_bits = readl(priv->smbus->io +
+					MLXBF_I2C_SMBUS_MASTER_STATUS);
 	master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK;
 
 	if (mlxbf_i2c_smbus_transaction_success(master_status_bits,
@@ -649,10 +609,17 @@ static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv,
 
 	aligned_length = round_up(length, 4);
 
-	/* Copy data bytes from 4-byte aligned source buffer. */
+	/*
+	 * Copy data bytes from 4-byte aligned source buffer.
+	 * Data copied to the Master GW Data Descriptor MUST be shifted
+	 * left so the data starts at the MSB of the descriptor registers
+	 * as required by the underlying hardware. Enable byte swapping
+	 * when writing data bytes to the 32 * 32-bit HW Data registers
+	 * a.k.a Master GW Data Descriptor.
+	 */
 	for (offset = 0; offset < aligned_length; offset += sizeof(u32)) {
 		data32 = *((u32 *)(data + offset));
-		mlxbf_i2c_write_data(priv->smbus->io, addr + offset, data32);
+		iowrite32be(data32, priv->smbus->io + addr + offset);
 	}
 }
 
@@ -664,15 +631,23 @@ static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv,
 
 	mask = sizeof(u32) - 1;
 
+	/*
+	 * Data bytes in the Master GW Data Descriptor are shifted left
+	 * so the data starts at the MSB of the descriptor registers as
+	 * set by the underlying hardware. Enable byte swapping while
+	 * reading data bytes from the 32 * 32-bit HW Data registers
+	 * a.k.a Master GW Data Descriptor.
+	 */
+
 	for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) {
-		data32 = mlxbf_i2c_read_data(priv->smbus->io, addr + offset);
+		data32 = ioread32be(priv->smbus->io + addr + offset);
 		*((u32 *)(data + offset)) = data32;
 	}
 
 	if (!(length & mask))
 		return;
 
-	data32 = mlxbf_i2c_read_data(priv->smbus->io, addr + offset);
+	data32 = ioread32be(priv->smbus->io + addr + offset);
 
 	for (byte = 0; byte < (length & mask); byte++) {
 		data[offset + byte] = data32 & GENMASK(7, 0);
@@ -698,16 +673,16 @@ static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave,
 	command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT);
 
 	/* Clear status bits. */
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_STATUS, 0x0);
+	writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_STATUS);
 	/* Set the cause data. */
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_CAUSE_OR_CLEAR, ~0x0);
+	writel(~0x0, priv->smbus->io + MLXBF_I2C_CAUSE_OR_CLEAR);
 	/* Zero PEC byte. */
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_PEC, 0x0);
+	writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_PEC);
 	/* Zero byte count. */
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_RS_BYTES, 0x0);
+	writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_RS_BYTES);
 
 	/* GW activation. */
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW, command);
+	writel(command, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW);
 
 	/*
 	 * Poll master status and check status bits. An ACK is sent when
@@ -823,8 +798,8 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,
 		 * needs to be 'manually' reset. This should be removed in
 		 * next tag integration.
 		 */
-		mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_FSM,
-				MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK);
+		writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK,
+			priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM);
 	}
 
 	return ret;
@@ -1113,8 +1088,8 @@ static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv,
 	timer |= mlxbf_i2c_set_timer(priv, timings->scl_low,
 				     false, MLXBF_I2C_MASK_16,
 				     MLXBF_I2C_SHIFT_16);
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH,
-			  timer);
+	writel(timer, priv->smbus->io +
+		MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH);
 
 	timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false,
 				    MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0);
@@ -1124,37 +1099,34 @@ static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv,
 				     MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16);
 	timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false,
 				     MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24);
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE,
-			  timer);
+	writel(timer, priv->smbus->io +
+		MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE);
 
 	timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true,
 				    MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
 	timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true,
 				     MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_THOLD, timer);
+	writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_THOLD);
 
 	timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true,
 				    MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
 	timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true,
 				     MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
-	mlxbf_i2c_write(priv->smbus->io,
-			MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP, timer);
+	writel(timer, priv->smbus->io +
+		MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP);
 
 	timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true,
 				    MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA,
-			  timer);
+	writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA);
 
 	timer = mlxbf_i2c_set_timer(priv, timings->buf, false,
 				    MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
 	timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false,
 				     MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_THIGH_MAX_TBUF,
-			timer);
+	writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF);
 
 	timer = timings->timeout;
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT,
-			timer);
+	writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT);
 }
 
 enum mlxbf_i2c_timings_config {
@@ -1426,19 +1398,15 @@ static int mlxbf_i2c_init_master(struct platform_device *pdev,
 	 * platform firmware; disabling the bus might compromise the system
 	 * functionality.
 	 */
-	config_reg = mlxbf_i2c_read(gpio_res->io,
-				    MLXBF_I2C_GPIO_0_FUNC_EN_0);
+	config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
 	config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus,
 							 config_reg);
-	mlxbf_i2c_write(gpio_res->io, MLXBF_I2C_GPIO_0_FUNC_EN_0,
-			config_reg);
+	writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
 
-	config_reg = mlxbf_i2c_read(gpio_res->io,
-				    MLXBF_I2C_GPIO_0_FORCE_OE_EN);
+	config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
 	config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus,
 							config_reg);
-	mlxbf_i2c_write(gpio_res->io, MLXBF_I2C_GPIO_0_FORCE_OE_EN,
-			config_reg);
+	writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
 
 	mutex_unlock(gpio_res->lock);
 
@@ -1452,10 +1420,9 @@ static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res)
 	u32 corepll_val;
 	u16 core_f;
 
-	pad_frequency = MLXBF_I2C_TYU_PLL_IN_FREQ;
+	pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
 
-	corepll_val = mlxbf_i2c_read(corepll_res->io,
-				     MLXBF_I2C_CORE_PLL_REG1);
+	corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
 
 	/* Get Core PLL configuration bits. */
 	core_f = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT) &
@@ -1488,12 +1455,10 @@ static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res)
 	u8 core_od, core_r;
 	u32 core_f;
 
-	pad_frequency = MLXBF_I2C_YU_PLL_IN_FREQ;
+	pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
 
-	corepll_reg1_val = mlxbf_i2c_read(corepll_res->io,
-					  MLXBF_I2C_CORE_PLL_REG1);
-	corepll_reg2_val = mlxbf_i2c_read(corepll_res->io,
-					  MLXBF_I2C_CORE_PLL_REG2);
+	corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
+	corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);
 
 	/* Get Core PLL configuration bits */
 	core_f = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT) &
@@ -1585,7 +1550,7 @@ static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr)
 	 * (7-bit address, 1 status bit (1 if enabled, 0 if not)).
 	 */
 	for (reg = 0; reg < reg_cnt; reg++) {
-		slave_reg = mlxbf_i2c_read(priv->smbus->io,
+		slave_reg = readl(priv->smbus->io +
 				MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
 		/*
 		 * Each register holds 4 slave addresses. So, we have to keep
@@ -1643,8 +1608,8 @@ static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr)
 
 	/* Enable the slave address and update the register. */
 	slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8);
-	mlxbf_i2c_write(priv->smbus->io,
-			MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4, slave_reg);
+	writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
+		reg * 0x4);
 
 	return 0;
 }
@@ -1668,7 +1633,7 @@ static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv)
 	 * (7-bit address, 1 status bit (1 if enabled, 0 if not)).
 	 */
 	for (reg = 0; reg < reg_cnt; reg++) {
-		slave_reg = mlxbf_i2c_read(priv->smbus->io,
+		slave_reg = readl(priv->smbus->io +
 				MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
 
 		/* Check whether the address slots are empty. */
@@ -1708,8 +1673,8 @@ static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv)
 
 	/* Cleanup the slave address slot. */
 	slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8));
-	mlxbf_i2c_write(priv->smbus->io,
-			MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4, slave_reg);
+	writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
+		reg * 0x4);
 
 	return 0;
 }
@@ -1801,7 +1766,7 @@ static int mlxbf_i2c_init_slave(struct platform_device *pdev,
 	int ret;
 
 	/* Reset FSM. */
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_FSM, 0);
+	writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_FSM);
 
 	/*
 	 * Enable slave cause interrupt bits. Drive
@@ -1810,15 +1775,13 @@ static int mlxbf_i2c_init_slave(struct platform_device *pdev,
 	 * masters issue a Read and Write, respectively. But, clear all
 	 * interrupts first.
 	 */
-	mlxbf_i2c_write(priv->slv_cause->io,
-			  MLXBF_I2C_CAUSE_OR_CLEAR, ~0);
+	writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
 	int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE;
 	int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS;
-	mlxbf_i2c_write(priv->slv_cause->io,
-			  MLXBF_I2C_CAUSE_OR_EVTEN0, int_reg);
+	writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0);
 
 	/* Finally, set the 'ready' bit to start handling transactions. */
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1);
+	writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
 
 	/* Initialize the cause coalesce resource. */
 	ret = mlxbf_i2c_init_coalesce(pdev, priv);
@@ -1844,23 +1807,21 @@ static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read,
 				MLXBF_I2C_CAUSE_YU_SLAVE_BIT :
 				priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT;
 
-	coalesce0_reg = mlxbf_i2c_read(priv->coalesce->io,
-				       MLXBF_I2C_CAUSE_COALESCE_0);
+	coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0);
 	is_set = coalesce0_reg & (1 << slave_shift);
 
 	if (!is_set)
 		return false;
 
 	/* Check the source of the interrupt, i.e. whether a Read or Write. */
-	cause_reg = mlxbf_i2c_read(priv->slv_cause->io,
-				     MLXBF_I2C_CAUSE_ARBITER);
+	cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER);
 	if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE)
 		*read = true;
 	else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS)
 		*write = true;
 
 	/* Clear cause bits. */
-	mlxbf_i2c_write(priv->slv_cause->io, MLXBF_I2C_CAUSE_OR_CLEAR, ~0x0);
+	writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
 
 	return true;
 }
@@ -1900,8 +1861,8 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
 	 * address, if supplied.
 	 */
 	if (recv_bytes > 0) {
-		data32 = mlxbf_i2c_read_data(priv->smbus->io,
-					     MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
+		data32 = ioread32be(priv->smbus->io +
+					MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
 
 		/* Parse the received bytes. */
 		switch (recv_bytes) {
@@ -1966,7 +1927,7 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
 	control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT);
 	control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT);
 
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_GW, control32);
+	writel(control32, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_GW);
 
 	/*
 	 * Wait until the transfer is completed; the driver will wait
@@ -1975,10 +1936,9 @@ static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
 	mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT);
 
 	/* Release the Slave GW. */
-	mlxbf_i2c_write(priv->smbus->io,
-			MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES, 0x0);
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_PEC, 0x0);
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1);
+	writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
+	writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
+	writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
 
 	return 0;
 }
@@ -2023,10 +1983,9 @@ static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
 	i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
 
 	/* Release the Slave GW. */
-	mlxbf_i2c_write(priv->smbus->io,
-			MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES, 0x0);
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_PEC, 0x0);
-	mlxbf_i2c_write(priv->smbus->io, MLXBF_I2C_SMBUS_SLAVE_READY, 0x1);
+	writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
+	writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
+	writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
 
 	return ret;
 }
@@ -2061,8 +2020,8 @@ static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr)
 	 * slave, if the higher 8 bits are sent then the slave expect N bytes
 	 * from the master.
 	 */
-	rw_bytes_reg = mlxbf_i2c_read(priv->smbus->io,
-				      MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
+	rw_bytes_reg = readl(priv->smbus->io +
+				MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
 	recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0);
 
 	/*
@@ -2264,6 +2223,7 @@ static const struct of_device_id mlxbf_i2c_dt_ids[] = {
 
 MODULE_DEVICE_TABLE(of, mlxbf_i2c_dt_ids);
 
+#ifdef CONFIG_ACPI
 static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = {
 	{ "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] },
 	{ "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] },
@@ -2305,6 +2265,12 @@ static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
 
 	return ret;
 }
+#else
+static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
+{
+	return -ENOENT;
+}
+#endif /* CONFIG_ACPI */
 
 static int mlxbf_i2c_of_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
 {
@@ -2473,7 +2439,9 @@ static struct platform_driver mlxbf_i2c_driver = {
 	.driver = {
 		.name = "i2c-mlxbf",
 		.of_match_table = mlxbf_i2c_dt_ids,
+#ifdef CONFIG_ACPI
 		.acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids),
+#endif /* CONFIG_ACPI  */
 	},
 };
 
@@ -2502,5 +2470,5 @@ static void __exit mlxbf_i2c_exit(void)
 module_exit(mlxbf_i2c_exit);
 
 MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver");
-MODULE_AUTHOR("Khalil Blaiech <kblaiech@mellanox.com>");
+MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 0cbdfbe605b5..33de99b7bc20 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -475,6 +475,10 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 {
 	u16 control_reg;
 
+	writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
+	udelay(50);
+	writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
+
 	mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
 
 	/* Set ioconfig */
@@ -529,10 +533,6 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 
 	mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
 	mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
-
-	writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
-	udelay(50);
-	writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 }
 
 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index cab725559999..bdd60770779a 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -129,6 +129,7 @@ struct sh_mobile_i2c_data {
 	int sr;
 	bool send_stop;
 	bool stop_after_dma;
+	bool atomic_xfer;
 
 	struct resource *res;
 	struct dma_chan *dma_tx;
@@ -330,13 +331,15 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, enum sh_mobile_i2c_op
 		ret = iic_rd(pd, ICDR);
 		break;
 	case OP_RX_STOP: /* enable DTE interrupt, issue stop */
-		iic_wr(pd, ICIC,
-		       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
+		if (!pd->atomic_xfer)
+			iic_wr(pd, ICIC,
+			       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 		iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 		break;
 	case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
-		iic_wr(pd, ICIC,
-		       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
+		if (!pd->atomic_xfer)
+			iic_wr(pd, ICIC,
+			       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 		ret = iic_rd(pd, ICDR);
 		iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 		break;
@@ -429,7 +432,8 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 
 	if (wakeup) {
 		pd->sr |= SW_DONE;
-		wake_up(&pd->wait);
+		if (!pd->atomic_xfer)
+			wake_up(&pd->wait);
 	}
 
 	/* defeat write posting to avoid spurious WAIT interrupts */
@@ -581,6 +585,9 @@ static void start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
 	pd->pos = -1;
 	pd->sr = 0;
 
+	if (pd->atomic_xfer)
+		return;
+
 	pd->dma_buf = i2c_get_dma_safe_msg_buf(pd->msg, 8);
 	if (pd->dma_buf)
 		sh_mobile_i2c_xfer_dma(pd);
@@ -637,15 +644,13 @@ static int poll_busy(struct sh_mobile_i2c_data *pd)
 	return i ? 0 : -ETIMEDOUT;
 }
 
-static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
-			      struct i2c_msg *msgs,
-			      int num)
+static int sh_mobile_xfer(struct sh_mobile_i2c_data *pd,
+			 struct i2c_msg *msgs, int num)
 {
-	struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
 	struct i2c_msg	*msg;
 	int err = 0;
 	int i;
-	long timeout;
+	long time_left;
 
 	/* Wake up device and enable clock */
 	pm_runtime_get_sync(pd->dev);
@@ -662,15 +667,35 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 		if (do_start)
 			i2c_op(pd, OP_START);
 
-		/* The interrupt handler takes care of the rest... */
-		timeout = wait_event_timeout(pd->wait,
-				       pd->sr & (ICSR_TACK | SW_DONE),
-				       adapter->timeout);
-
-		/* 'stop_after_dma' tells if DMA transfer was complete */
-		i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg, pd->stop_after_dma);
+		if (pd->atomic_xfer) {
+			unsigned long j = jiffies + pd->adap.timeout;
+
+			time_left = time_before_eq(jiffies, j);
+			while (time_left &&
+			       !(pd->sr & (ICSR_TACK | SW_DONE))) {
+				unsigned char sr = iic_rd(pd, ICSR);
+
+				if (sr & (ICSR_AL   | ICSR_TACK |
+					  ICSR_WAIT | ICSR_DTE)) {
+					sh_mobile_i2c_isr(0, pd);
+					udelay(150);
+				} else {
+					cpu_relax();
+				}
+				time_left = time_before_eq(jiffies, j);
+			}
+		} else {
+			/* The interrupt handler takes care of the rest... */
+			time_left = wait_event_timeout(pd->wait,
+					pd->sr & (ICSR_TACK | SW_DONE),
+					pd->adap.timeout);
+
+			/* 'stop_after_dma' tells if DMA xfer was complete */
+			i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg,
+						 pd->stop_after_dma);
+		}
 
-		if (!timeout) {
+		if (!time_left) {
 			dev_err(pd->dev, "Transfer request timed out\n");
 			if (pd->dma_direction != DMA_NONE)
 				sh_mobile_i2c_cleanup_dma(pd);
@@ -696,14 +721,35 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 	return err ?: num;
 }
 
+static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
+			      struct i2c_msg *msgs,
+			      int num)
+{
+	struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
+
+	pd->atomic_xfer = false;
+	return sh_mobile_xfer(pd, msgs, num);
+}
+
+static int sh_mobile_i2c_xfer_atomic(struct i2c_adapter *adapter,
+				     struct i2c_msg *msgs,
+				     int num)
+{
+	struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
+
+	pd->atomic_xfer = true;
+	return sh_mobile_xfer(pd, msgs, num);
+}
+
 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
 {
 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 }
 
 static const struct i2c_algorithm sh_mobile_i2c_algorithm = {
-	.functionality	= sh_mobile_i2c_func,
-	.master_xfer	= sh_mobile_i2c_xfer,
+	.functionality = sh_mobile_i2c_func,
+	.master_xfer = sh_mobile_i2c_xfer,
+	.master_xfer_atomic = sh_mobile_i2c_xfer_atomic,
 };
 
 static const struct i2c_adapter_quirks sh_mobile_i2c_quirks = {
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h
index f0e5ffba2d51..97ed8f952f6e 100644
--- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h
@@ -176,7 +176,7 @@ struct pvrdma_port_attr {
 	u8			subnet_timeout;
 	u8			init_type_reply;
 	u8			active_width;
-	u16			active_speed;
+	u8			active_speed;
 	u8			phys_state;
 	u8			reserved[2];
 };
diff --git a/drivers/infiniband/sw/rdmavt/vt.c b/drivers/infiniband/sw/rdmavt/vt.c
index 52218684ad4a..670a9623b46e 100644
--- a/drivers/infiniband/sw/rdmavt/vt.c
+++ b/drivers/infiniband/sw/rdmavt/vt.c
@@ -524,6 +524,7 @@ static noinline int check_support(struct rvt_dev_info *rdi, int verb)
 int rvt_register_device(struct rvt_dev_info *rdi)
 {
 	int ret = 0, i;
+	u64 dma_mask;
 
 	if (!rdi)
 		return -EINVAL;
@@ -580,8 +581,10 @@ int rvt_register_device(struct rvt_dev_info *rdi)
 
 	/* DMA Operations */
 	rdi->ibdev.dev.dma_parms = rdi->ibdev.dev.parent->dma_parms;
-	dma_set_coherent_mask(&rdi->ibdev.dev,
-			      rdi->ibdev.dev.parent->coherent_dma_mask);
+	dma_mask = IS_ENABLED(CONFIG_64BIT) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32);
+	ret = dma_coerce_mask_and_coherent(&rdi->ibdev.dev, dma_mask);
+	if (ret)
+		goto bail_wss;
 
 	/* Protection Domain */
 	spin_lock_init(&rdi->n_pds_lock);
diff --git a/drivers/infiniband/sw/rxe/rxe_verbs.c b/drivers/infiniband/sw/rxe/rxe_verbs.c
index 1fc022362fbe..f9c832e82552 100644
--- a/drivers/infiniband/sw/rxe/rxe_verbs.c
+++ b/drivers/infiniband/sw/rxe/rxe_verbs.c
@@ -1118,6 +1118,7 @@ int rxe_register_device(struct rxe_dev *rxe, const char *ibdev_name)
 	int err;
 	struct ib_device *dev = &rxe->ib_dev;
 	struct crypto_shash *tfm;
+	u64 dma_mask;
 
 	strlcpy(dev->node_desc, "rxe", sizeof(dev->node_desc));
 
@@ -1130,7 +1131,10 @@ int rxe_register_device(struct rxe_dev *rxe, const char *ibdev_name)
 			    rxe->ndev->dev_addr);
 	dev->dev.dma_parms = &rxe->dma_parms;
 	dma_set_max_seg_size(&dev->dev, UINT_MAX);
-	dma_set_coherent_mask(&dev->dev, dma_get_required_mask(&dev->dev));
+	dma_mask = IS_ENABLED(CONFIG_64BIT) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32);
+	err = dma_coerce_mask_and_coherent(&dev->dev, dma_mask);
+	if (err)
+		return err;
 
 	dev->uverbs_cmd_mask = BIT_ULL(IB_USER_VERBS_CMD_GET_CONTEXT)
 	    | BIT_ULL(IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL)
diff --git a/drivers/infiniband/sw/siw/siw_main.c b/drivers/infiniband/sw/siw/siw_main.c
index ca8bc7296867..181e06c1c43d 100644
--- a/drivers/infiniband/sw/siw/siw_main.c
+++ b/drivers/infiniband/sw/siw/siw_main.c
@@ -306,6 +306,7 @@ static struct siw_device *siw_device_create(struct net_device *netdev)
 	struct siw_device *sdev = NULL;
 	struct ib_device *base_dev;
 	struct device *parent = netdev->dev.parent;
+	u64 dma_mask;
 	int rv;
 
 	if (!parent) {
@@ -384,8 +385,10 @@ static struct siw_device *siw_device_create(struct net_device *netdev)
 	base_dev->dev.parent = parent;
 	base_dev->dev.dma_parms = &sdev->dma_parms;
 	dma_set_max_seg_size(&base_dev->dev, UINT_MAX);
-	dma_set_coherent_mask(&base_dev->dev,
-			      dma_get_required_mask(&base_dev->dev));
+	dma_mask = IS_ENABLED(CONFIG_64BIT) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32);
+	if (dma_coerce_mask_and_coherent(&base_dev->dev, dma_mask))
+		goto error;
+
 	base_dev->num_comp_vectors = num_possible_cpus();
 
 	xa_init_flags(&sdev->qp_xa, XA_FLAGS_ALLOC1);
diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c
index 0065eb17ae36..53a8becac827 100644
--- a/drivers/infiniband/ulp/srpt/ib_srpt.c
+++ b/drivers/infiniband/ulp/srpt/ib_srpt.c
@@ -622,10 +622,11 @@ static int srpt_refresh_port(struct srpt_port *sport)
 /**
  * srpt_unregister_mad_agent - unregister MAD callback functions
  * @sdev: SRPT HCA pointer.
+ * @port_cnt: number of ports with registered MAD
  *
  * Note: It is safe to call this function more than once for the same device.
  */
-static void srpt_unregister_mad_agent(struct srpt_device *sdev)
+static void srpt_unregister_mad_agent(struct srpt_device *sdev, int port_cnt)
 {
 	struct ib_port_modify port_modify = {
 		.clr_port_cap_mask = IB_PORT_DEVICE_MGMT_SUP,
@@ -633,7 +634,7 @@ static void srpt_unregister_mad_agent(struct srpt_device *sdev)
 	struct srpt_port *sport;
 	int i;
 
-	for (i = 1; i <= sdev->device->phys_port_cnt; i++) {
+	for (i = 1; i <= port_cnt; i++) {
 		sport = &sdev->port[i - 1];
 		WARN_ON(sport->port != i);
 		if (sport->mad_agent) {
@@ -3185,7 +3186,8 @@ static int srpt_add_one(struct ib_device *device)
 		if (ret) {
 			pr_err("MAD registration failed for %s-%d.\n",
 			       dev_name(&sdev->device->dev), i);
-			goto err_event;
+			i--;
+			goto err_port;
 		}
 	}
 
@@ -3197,7 +3199,8 @@ static int srpt_add_one(struct ib_device *device)
 	pr_debug("added %s.\n", dev_name(&device->dev));
 	return 0;
 
-err_event:
+err_port:
+	srpt_unregister_mad_agent(sdev, i);
 	ib_unregister_event_handler(&sdev->event_handler);
 err_cm:
 	if (sdev->cm_id)
@@ -3221,7 +3224,7 @@ static void srpt_remove_one(struct ib_device *device, void *client_data)
 	struct srpt_device *sdev = client_data;
 	int i;
 
-	srpt_unregister_mad_agent(sdev);
+	srpt_unregister_mad_agent(sdev, sdev->device->phys_port_cnt);
 
 	ib_unregister_event_handler(&sdev->event_handler);
 
diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.h b/drivers/infiniband/ulp/srpt/ib_srpt.h
index 41435a699b53..bdeb010efee6 100644
--- a/drivers/infiniband/ulp/srpt/ib_srpt.h
+++ b/drivers/infiniband/ulp/srpt/ib_srpt.h
@@ -256,6 +256,7 @@ enum rdma_ch_state {
  * @rdma_cm:	   See below.
  * @rdma_cm.cm_id: RDMA CM ID associated with the channel.
  * @cq:            IB completion queue for this channel.
+ * @cq_size:	   Number of CQEs in @cq.
  * @zw_cqe:	   Zero-length write CQE.
  * @rcu:           RCU head.
  * @kref:	   kref for this channel.
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index f696ac7c5f89..89647700bab2 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -409,7 +409,11 @@ extern bool amd_iommu_np_cache;
 /* Only true if all IOMMUs support device IOTLBs */
 extern bool amd_iommu_iotlb_sup;
 
-#define MAX_IRQS_PER_TABLE	256
+/*
+ * AMD IOMMU hardware only support 512 IRTEs despite
+ * the architectural limitation of 2048 entries.
+ */
+#define MAX_IRQS_PER_TABLE	512
 #define IRQ_TABLE_ALIGNMENT	128
 
 struct irq_remap_table {
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 8651f6d4dfa0..1b1ca63e6bbe 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -2525,6 +2525,9 @@ struct dmar_domain *find_domain(struct device *dev)
 {
 	struct device_domain_info *info;
 
+	if (unlikely(!dev || !dev->iommu))
+		return NULL;
+
 	if (unlikely(attach_deferred(dev)))
 		return NULL;
 
diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c
index f1861fa3d0e4..3242ebd0bca3 100644
--- a/drivers/iommu/intel/svm.c
+++ b/drivers/iommu/intel/svm.c
@@ -279,6 +279,7 @@ int intel_svm_bind_gpasid(struct iommu_domain *domain, struct device *dev,
 	struct intel_iommu *iommu = device_to_iommu(dev, NULL, NULL);
 	struct intel_svm_dev *sdev = NULL;
 	struct dmar_domain *dmar_domain;
+	struct device_domain_info *info;
 	struct intel_svm *svm = NULL;
 	int ret = 0;
 
@@ -310,6 +311,10 @@ int intel_svm_bind_gpasid(struct iommu_domain *domain, struct device *dev,
 	if (data->hpasid <= 0 || data->hpasid >= PASID_MAX)
 		return -EINVAL;
 
+	info = get_domain_info(dev);
+	if (!info)
+		return -EINVAL;
+
 	dmar_domain = to_dmar_domain(domain);
 
 	mutex_lock(&pasid_mutex);
@@ -357,6 +362,7 @@ int intel_svm_bind_gpasid(struct iommu_domain *domain, struct device *dev,
 		goto out;
 	}
 	sdev->dev = dev;
+	sdev->sid = PCI_DEVID(info->bus, info->devfn);
 
 	/* Only count users if device has aux domains */
 	if (iommu_dev_feature_enabled(dev, IOMMU_DEV_FEAT_AUX))
@@ -1029,7 +1035,7 @@ no_pasid:
 			resp.qw0 = QI_PGRP_PASID(req->pasid) |
 				QI_PGRP_DID(req->rid) |
 				QI_PGRP_PASID_P(req->pasid_present) |
-				QI_PGRP_PDP(req->pasid_present) |
+				QI_PGRP_PDP(req->priv_data_present) |
 				QI_PGRP_RESP_CODE(result) |
 				QI_PGRP_RESP_TYPE;
 			resp.qw1 = QI_PGRP_IDX(req->prg_index) |
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index 8c470f451a32..b53446bb8c6b 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -2071,7 +2071,7 @@ EXPORT_SYMBOL_GPL(iommu_uapi_cache_invalidate);
 
 static int iommu_check_bind_data(struct iommu_gpasid_bind_data *data)
 {
-	u32 mask;
+	u64 mask;
 	int i;
 
 	if (data->version != IOMMU_GPASID_BIND_VERSION_1)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c6098eee0c7c..2aa79c32ee22 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -180,7 +180,6 @@ config IRQ_MIPS_CPU
 	select GENERIC_IRQ_CHIP
 	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
 	select IRQ_DOMAIN
-	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
 	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 
 config CLPS711X_IRQCHIP
@@ -315,7 +314,6 @@ config KEYSTONE_IRQ
 config MIPS_GIC
 	bool
 	select GENERIC_IRQ_IPI
-	select IRQ_DOMAIN_HIERARCHY
 	select MIPS_CM
 
 config INGENIC_IRQ
@@ -591,6 +589,7 @@ config LOONGSON_PCH_MSI
 
 config MST_IRQ
 	bool "MStar Interrupt Controller"
+	depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
 	default ARCH_MEDIATEK
 	select IRQ_DOMAIN
 	select IRQ_DOMAIN_HIERARCHY
diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c
index 97838eb705f9..cbc7c740e4dc 100644
--- a/drivers/irqchip/irq-bcm2836.c
+++ b/drivers/irqchip/irq-bcm2836.c
@@ -244,7 +244,7 @@ static int bcm2836_cpu_dying(unsigned int cpu)
 
 #define BITS_PER_MBOX	32
 
-static void bcm2836_arm_irqchip_smp_init(void)
+static void __init bcm2836_arm_irqchip_smp_init(void)
 {
 	struct irq_fwspec ipi_fwspec = {
 		.fwnode		= intc.domain->fwnode,
diff --git a/drivers/irqchip/irq-mst-intc.c b/drivers/irqchip/irq-mst-intc.c
index 4be077591898..143657b0cf28 100644
--- a/drivers/irqchip/irq-mst-intc.c
+++ b/drivers/irqchip/irq-mst-intc.c
@@ -154,8 +154,8 @@ static const struct irq_domain_ops mst_intc_domain_ops = {
 	.free		= irq_domain_free_irqs_common,
 };
 
-int __init
-mst_intc_of_init(struct device_node *dn, struct device_node *parent)
+static int __init mst_intc_of_init(struct device_node *dn,
+				   struct device_node *parent)
 {
 	struct irq_domain *domain, *domain_parent;
 	struct mst_intc_chip_data *cd;
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
index 3819185bfd02..cb7f60b3b4a9 100644
--- a/drivers/irqchip/irq-renesas-intc-irqpin.c
+++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
@@ -71,8 +71,7 @@ struct intc_irqpin_priv {
 };
 
 struct intc_irqpin_config {
-	unsigned int irlm_bit;
-	unsigned needs_irlm:1;
+	int irlm_bit;		/* -1 if non-existent */
 };
 
 static unsigned long intc_irqpin_read32(void __iomem *iomem)
@@ -349,11 +348,10 @@ static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
 
 static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
 	.irlm_bit = 23, /* ICR0.IRLM0 */
-	.needs_irlm = 1,
 };
 
 static const struct intc_irqpin_config intc_irqpin_rmobile = {
-	.needs_irlm = 0,
+	.irlm_bit = -1,
 };
 
 static const struct of_device_id intc_irqpin_dt_ids[] = {
@@ -470,7 +468,7 @@ static int intc_irqpin_probe(struct platform_device *pdev)
 	}
 
 	/* configure "individual IRQ mode" where needed */
-	if (config && config->needs_irlm) {
+	if (config && config->irlm_bit >= 0) {
 		if (io[INTC_IRQPIN_REG_IRLM])
 			intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
 						      config->irlm_bit, 1, 1);
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index eaa3e9fe54e9..6f432d2a5ceb 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -99,7 +99,7 @@ static inline void plic_irq_toggle(const struct cpumask *mask,
 				   struct irq_data *d, int enable)
 {
 	int cpu;
-	struct plic_priv *priv = irq_get_chip_data(d->irq);
+	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 
 	writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
 	for_each_cpu(cpu, mask) {
@@ -115,7 +115,7 @@ static void plic_irq_unmask(struct irq_data *d)
 {
 	struct cpumask amask;
 	unsigned int cpu;
-	struct plic_priv *priv = irq_get_chip_data(d->irq);
+	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 
 	cpumask_and(&amask, &priv->lmask, cpu_online_mask);
 	cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
@@ -127,7 +127,7 @@ static void plic_irq_unmask(struct irq_data *d)
 
 static void plic_irq_mask(struct irq_data *d)
 {
-	struct plic_priv *priv = irq_get_chip_data(d->irq);
+	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 
 	plic_irq_toggle(&priv->lmask, d, 0);
 }
@@ -138,7 +138,7 @@ static int plic_set_affinity(struct irq_data *d,
 {
 	unsigned int cpu;
 	struct cpumask amask;
-	struct plic_priv *priv = irq_get_chip_data(d->irq);
+	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 
 	cpumask_and(&amask, &priv->lmask, mask_val);
 
@@ -151,7 +151,7 @@ static int plic_set_affinity(struct irq_data *d,
 		return -EINVAL;
 
 	plic_irq_toggle(&priv->lmask, d, 0);
-	plic_irq_toggle(cpumask_of(cpu), d, 1);
+	plic_irq_toggle(cpumask_of(cpu), d, !irqd_irq_masked(d));
 
 	irq_data_update_effective_affinity(d, cpumask_of(cpu));
 
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 0c2c61db26b4..8662d7b7b262 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -195,6 +195,10 @@ static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
 	{ .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
 	{ .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
 	{ .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
+	{ .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
+	{ .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
+	{ .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
+	{ .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
 	{ .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
 	{ .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
 	{ .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
diff --git a/drivers/irqchip/irq-ti-sci-inta.c b/drivers/irqchip/irq-ti-sci-inta.c
index e0cceb81c648..b2ab8db439d9 100644
--- a/drivers/irqchip/irq-ti-sci-inta.c
+++ b/drivers/irqchip/irq-ti-sci-inta.c
@@ -85,6 +85,17 @@ struct ti_sci_inta_vint_desc {
  * @base:		Base address of the memory mapped IO registers
  * @pdev:		Pointer to platform device.
  * @ti_sci_id:		TI-SCI device identifier
+ * @unmapped_cnt:	Number of @unmapped_dev_ids entries
+ * @unmapped_dev_ids:	Pointer to an array of TI-SCI device identifiers of
+ *			unmapped event sources.
+ *			Unmapped Events are not part of the Global Event Map and
+ *			they are converted to Global event within INTA to be
+ *			received by the same INTA to generate an interrupt.
+ *			In case an interrupt request comes for a device which is
+ *			generating Unmapped Event, we must use the INTA's TI-SCI
+ *			device identifier in place of the source device
+ *			identifier to let sysfw know where it has to program the
+ *			Global Event number.
  */
 struct ti_sci_inta_irq_domain {
 	const struct ti_sci_handle *sci;
@@ -96,11 +107,37 @@ struct ti_sci_inta_irq_domain {
 	void __iomem *base;
 	struct platform_device *pdev;
 	u32 ti_sci_id;
+
+	int unmapped_cnt;
+	u16 *unmapped_dev_ids;
 };
 
 #define to_vint_desc(e, i) container_of(e, struct ti_sci_inta_vint_desc, \
 					events[i])
 
+static u16 ti_sci_inta_get_dev_id(struct ti_sci_inta_irq_domain *inta, u32 hwirq)
+{
+	u16 dev_id = HWIRQ_TO_DEVID(hwirq);
+	int i;
+
+	if (inta->unmapped_cnt == 0)
+		return dev_id;
+
+	/*
+	 * For devices sending Unmapped Events we must use the INTA's TI-SCI
+	 * device identifier number to be able to convert it to a Global Event
+	 * and map it to an interrupt.
+	 */
+	for (i = 0; i < inta->unmapped_cnt; i++) {
+		if (dev_id == inta->unmapped_dev_ids[i]) {
+			dev_id = inta->ti_sci_id;
+			break;
+		}
+	}
+
+	return dev_id;
+}
+
 /**
  * ti_sci_inta_irq_handler() - Chained IRQ handler for the vint irqs
  * @desc:	Pointer to irq_desc corresponding to the irq
@@ -251,7 +288,7 @@ static struct ti_sci_inta_event_desc *ti_sci_inta_alloc_event(struct ti_sci_inta
 	u16 dev_id, dev_index;
 	int err;
 
-	dev_id = HWIRQ_TO_DEVID(hwirq);
+	dev_id = ti_sci_inta_get_dev_id(inta, hwirq);
 	dev_index = HWIRQ_TO_IRQID(hwirq);
 
 	event_desc = &vint_desc->events[free_bit];
@@ -352,14 +389,15 @@ static void ti_sci_inta_free_irq(struct ti_sci_inta_event_desc *event_desc,
 {
 	struct ti_sci_inta_vint_desc *vint_desc;
 	struct ti_sci_inta_irq_domain *inta;
+	u16 dev_id;
 
 	vint_desc = to_vint_desc(event_desc, event_desc->vint_bit);
 	inta = vint_desc->domain->host_data;
+	dev_id = ti_sci_inta_get_dev_id(inta, hwirq);
 	/* free event irq */
 	mutex_lock(&inta->vint_mutex);
 	inta->sci->ops.rm_irq_ops.free_event_map(inta->sci,
-						 HWIRQ_TO_DEVID(hwirq),
-						 HWIRQ_TO_IRQID(hwirq),
+						 dev_id, HWIRQ_TO_IRQID(hwirq),
 						 inta->ti_sci_id,
 						 vint_desc->vint_id,
 						 event_desc->global_event,
@@ -574,6 +612,41 @@ static struct msi_domain_info ti_sci_inta_msi_domain_info = {
 	.chip	= &ti_sci_inta_msi_irq_chip,
 };
 
+static int ti_sci_inta_get_unmapped_sources(struct ti_sci_inta_irq_domain *inta)
+{
+	struct device *dev = &inta->pdev->dev;
+	struct device_node *node = dev_of_node(dev);
+	struct of_phandle_iterator it;
+	int count, err, ret, i;
+
+	count = of_count_phandle_with_args(node, "ti,unmapped-event-sources", NULL);
+	if (count <= 0)
+		return 0;
+
+	inta->unmapped_dev_ids = devm_kcalloc(dev, count,
+					      sizeof(*inta->unmapped_dev_ids),
+					      GFP_KERNEL);
+	if (!inta->unmapped_dev_ids)
+		return -ENOMEM;
+
+	i = 0;
+	of_for_each_phandle(&it, err, node, "ti,unmapped-event-sources", NULL, 0) {
+		u32 dev_id;
+
+		ret = of_property_read_u32(it.node, "ti,sci-dev-id", &dev_id);
+		if (ret) {
+			dev_err(dev, "ti,sci-dev-id read failure for %pOFf\n", it.node);
+			of_node_put(it.node);
+			return ret;
+		}
+		inta->unmapped_dev_ids[i++] = dev_id;
+	}
+
+	inta->unmapped_cnt = count;
+
+	return 0;
+}
+
 static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev)
 {
 	struct irq_domain *parent_domain, *domain, *msi_domain;
@@ -629,6 +702,10 @@ static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev)
 	if (IS_ERR(inta->base))
 		return PTR_ERR(inta->base);
 
+	ret = ti_sci_inta_get_unmapped_sources(inta);
+	if (ret)
+		return ret;
+
 	domain = irq_domain_add_linear(dev_of_node(dev),
 				       ti_sci_get_num_resources(inta->vint),
 				       &ti_sci_inta_irq_domain_ops, inta);
diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
index 0e7a9b64301e..e345f9d9f8e8 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c
@@ -707,6 +707,30 @@ static int fsl_ifc_attach_chip(struct nand_chip *chip)
 {
 	struct mtd_info *mtd = nand_to_mtd(chip);
 	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
+	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+	struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
+	u32 csor;
+
+	csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
+
+	/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
+	if (csor & CSOR_NAND_ECC_DEC_EN) {
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
+		mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
+
+		/* Hardware generates ECC per 512 Bytes */
+		chip->ecc.size = 512;
+		if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
+			chip->ecc.bytes = 8;
+			chip->ecc.strength = 4;
+		} else {
+			chip->ecc.bytes = 16;
+			chip->ecc.strength = 8;
+		}
+	} else {
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
+		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
+	}
 
 	dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
 		nanddev_ntargets(&chip->base));
@@ -910,25 +934,6 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 		return -ENODEV;
 	}
 
-	/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
-	if (csor & CSOR_NAND_ECC_DEC_EN) {
-		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
-		mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
-
-		/* Hardware generates ECC per 512 Bytes */
-		chip->ecc.size = 512;
-		if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
-			chip->ecc.bytes = 8;
-			chip->ecc.strength = 4;
-		} else {
-			chip->ecc.bytes = 16;
-			chip->ecc.strength = 8;
-		}
-	} else {
-		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
-		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
-	}
-
 	ret = fsl_ifc_sram_init(priv);
 	if (ret)
 		return ret;
diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index d4200eb2ad32..684c51e5e60d 100644
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c
@@ -1681,6 +1681,11 @@ static int mxcnd_attach_chip(struct nand_chip *chip)
 	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	struct device *dev = mtd->dev.parent;
 
+	chip->ecc.bytes = host->devtype_data->eccbytes;
+	host->eccsize = host->devtype_data->eccsize;
+	chip->ecc.size = 512;
+	mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
+
 	switch (chip->ecc.engine_type) {
 	case NAND_ECC_ENGINE_TYPE_ON_HOST:
 		chip->ecc.read_page = mxc_nand_read_page;
@@ -1836,19 +1841,7 @@ static int mxcnd_probe(struct platform_device *pdev)
 	if (host->devtype_data->axi_offset)
 		host->regs_axi = host->base + host->devtype_data->axi_offset;
 
-	this->ecc.bytes = host->devtype_data->eccbytes;
-	host->eccsize = host->devtype_data->eccsize;
-
 	this->legacy.select_chip = host->devtype_data->select_chip;
-	this->ecc.size = 512;
-	mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
-
-	if (host->pdata.hw_ecc) {
-		this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
-	} else {
-		this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
-		this->ecc.algo = NAND_ECC_ALGO_HAMMING;
-	}
 
 	/* NAND bus width determines access functions used by upper layer */
 	if (host->pdata.width == 2)
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
index b31a5818234d..550bda4d1415 100644
--- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
@@ -1708,6 +1708,13 @@ static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip)
 		return -EINVAL;
 	}
 
+	/* Default ECC settings in case they are not set in the device tree */
+	if (!chip->ecc.size)
+		chip->ecc.size = FMC2_ECC_STEP_SIZE;
+
+	if (!chip->ecc.strength)
+		chip->ecc.strength = FMC2_ECC_BCH8;
+
 	ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps,
 				   mtd->oobsize - FMC2_BBM_LEN);
 	if (ret) {
@@ -1727,8 +1734,7 @@ static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip)
 
 	mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops);
 
-	if (chip->options & NAND_BUSWIDTH_16)
-		stm32_fmc2_nfc_set_buswidth_16(nfc, true);
+	stm32_fmc2_nfc_setup(chip);
 
 	return 0;
 }
@@ -1952,11 +1958,6 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
 	chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
 			 NAND_USES_DMA;
 
-	/* Default ECC settings */
-	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
-	chip->ecc.size = FMC2_ECC_STEP_SIZE;
-	chip->ecc.strength = FMC2_ECC_BCH8;
-
 	/* Scan to find existence of the device */
 	ret = nand_scan(chip, nand->ncs);
 	if (ret)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 0369d98b2d12..f0ae7a01703a 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2701,11 +2701,10 @@ static void spi_nor_sfdp_init_params(struct spi_nor *nor)
 
 	memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
 
-	if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
+	if (spi_nor_parse_sfdp(nor, nor->params)) {
+		memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
 		nor->addr_width = 0;
 		nor->flags &= ~SNOR_F_4B_OPCODES;
-	} else {
-		memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
 	}
 }
 
@@ -3009,13 +3008,15 @@ static int spi_nor_set_addr_width(struct spi_nor *nor)
 		/* already configured from SFDP */
 	} else if (nor->info->addr_width) {
 		nor->addr_width = nor->info->addr_width;
-	} else if (nor->mtd.size > 0x1000000) {
-		/* enable 4-byte addressing if the device exceeds 16MiB */
-		nor->addr_width = 4;
 	} else {
 		nor->addr_width = 3;
 	}
 
+	if (nor->addr_width == 3 && nor->mtd.size > 0x1000000) {
+		/* enable 4-byte addressing if the device exceeds 16MiB */
+		nor->addr_width = 4;
+	}
+
 	if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
 		dev_dbg(nor->dev, "address width is too large: %u\n",
 			nor->addr_width);
diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev.c
index b70ded3760f2..6dee4f8f2024 100644
--- a/drivers/net/can/dev.c
+++ b/drivers/net/can/dev.c
@@ -512,9 +512,13 @@ __can_get_echo_skb(struct net_device *dev, unsigned int idx, u8 *len_ptr)
 		 */
 		struct sk_buff *skb = priv->echo_skb[idx];
 		struct canfd_frame *cf = (struct canfd_frame *)skb->data;
-		u8 len = cf->len;
 
-		*len_ptr = len;
+		/* get the real payload length for netdev statistics */
+		if (cf->can_id & CAN_RTR_FLAG)
+			*len_ptr = 0;
+		else
+			*len_ptr = cf->len;
+
 		priv->echo_skb[idx] = NULL;
 
 		return skb;
@@ -538,7 +542,11 @@ unsigned int can_get_echo_skb(struct net_device *dev, unsigned int idx)
 	if (!skb)
 		return 0;
 
-	netif_rx(skb);
+	skb_get(skb);
+	if (netif_rx(skb) == NET_RX_SUCCESS)
+		dev_consume_skb_any(skb);
+	else
+		dev_kfree_skb_any(skb);
 
 	return len;
 }
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 4d594e977497..881799bd9c5e 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -217,7 +217,7 @@
  *   MX8MP FlexCAN3  03.00.17.01    yes       yes        no      yes       yes          yes
  *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?          no
  * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes           no
- * LX2160A FlexCAN3  03.00.23.00     no       yes        no       no       yes          yes
+ * LX2160A FlexCAN3  03.00.23.00     no       yes        no      yes       yes          yes
  *
  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
  */
@@ -400,19 +400,19 @@ static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
-		FLEXCAN_QUIRK_BROKEN_PERR_STATE,
+		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC,
 };
 
 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
-		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
-		FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
+		FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 };
 
 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
 	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
-		FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_SUPPORT_FD,
+		FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_SUPPORT_FD |
+		FLEXCAN_QUIRK_SUPPORT_ECC,
 };
 
 static const struct can_bittiming_const flexcan_bittiming_const = {
@@ -2062,6 +2062,8 @@ static int flexcan_remove(struct platform_device *pdev)
 {
 	struct net_device *dev = platform_get_drvdata(pdev);
 
+	device_set_wakeup_enable(&pdev->dev, false);
+	device_set_wakeup_capable(&pdev->dev, false);
 	unregister_flexcandev(dev);
 	pm_runtime_disable(&pdev->dev);
 	free_candev(dev);
diff --git a/drivers/net/can/peak_canfd/peak_canfd.c b/drivers/net/can/peak_canfd/peak_canfd.c
index 10aa3e457c33..40c33b8a5fda 100644
--- a/drivers/net/can/peak_canfd/peak_canfd.c
+++ b/drivers/net/can/peak_canfd/peak_canfd.c
@@ -262,8 +262,7 @@ static int pucan_handle_can_rx(struct peak_canfd_priv *priv,
 		cf_len = get_can_dlc(pucan_msg_get_dlc(msg));
 
 	/* if this frame is an echo, */
-	if ((rx_msg_flags & PUCAN_MSG_LOOPED_BACK) &&
-	    !(rx_msg_flags & PUCAN_MSG_SELF_RECEIVE)) {
+	if (rx_msg_flags & PUCAN_MSG_LOOPED_BACK) {
 		unsigned long flags;
 
 		spin_lock_irqsave(&priv->echo_lock, flags);
@@ -277,7 +276,13 @@ static int pucan_handle_can_rx(struct peak_canfd_priv *priv,
 		netif_wake_queue(priv->ndev);
 
 		spin_unlock_irqrestore(&priv->echo_lock, flags);
-		return 0;
+
+		/* if this frame is only an echo, stop here. Otherwise,
+		 * continue to push this application self-received frame into
+		 * its own rx queue.
+		 */
+		if (!(rx_msg_flags & PUCAN_MSG_SELF_RECEIVE))
+			return 0;
 	}
 
 	/* otherwise, it should be pushed into rx fifo */
diff --git a/drivers/net/can/rx-offload.c b/drivers/net/can/rx-offload.c
index 3b180269a92d..6e95193b215b 100644
--- a/drivers/net/can/rx-offload.c
+++ b/drivers/net/can/rx-offload.c
@@ -245,7 +245,7 @@ int can_rx_offload_queue_sorted(struct can_rx_offload *offload,
 
 	if (skb_queue_len(&offload->skb_queue) >
 	    offload->skb_queue_len_max) {
-		kfree_skb(skb);
+		dev_kfree_skb_any(skb);
 		return -ENOBUFS;
 	}
 
@@ -290,7 +290,7 @@ int can_rx_offload_queue_tail(struct can_rx_offload *offload,
 {
 	if (skb_queue_len(&offload->skb_queue) >
 	    offload->skb_queue_len_max) {
-		kfree_skb(skb);
+		dev_kfree_skb_any(skb);
 		return -ENOBUFS;
 	}
 
diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
index c3f49543ff26..9c215f7c5f81 100644
--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
+++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c
@@ -75,11 +75,11 @@ static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model)
 {
 	switch (model) {
 	case MCP251XFD_MODEL_MCP2517FD:
-		return "MCP2517FD"; break;
+		return "MCP2517FD";
 	case MCP251XFD_MODEL_MCP2518FD:
-		return "MCP2518FD"; break;
+		return "MCP2518FD";
 	case MCP251XFD_MODEL_MCP251XFD:
-		return "MCP251xFD"; break;
+		return "MCP251xFD";
 	}
 
 	return "<unknown>";
@@ -95,21 +95,21 @@ static const char *mcp251xfd_get_mode_str(const u8 mode)
 {
 	switch (mode) {
 	case MCP251XFD_REG_CON_MODE_MIXED:
-		return "Mixed (CAN FD/CAN 2.0)"; break;
+		return "Mixed (CAN FD/CAN 2.0)";
 	case MCP251XFD_REG_CON_MODE_SLEEP:
-		return "Sleep"; break;
+		return "Sleep";
 	case MCP251XFD_REG_CON_MODE_INT_LOOPBACK:
-		return "Internal Loopback"; break;
+		return "Internal Loopback";
 	case MCP251XFD_REG_CON_MODE_LISTENONLY:
-		return "Listen Only"; break;
+		return "Listen Only";
 	case MCP251XFD_REG_CON_MODE_CONFIG:
-		return "Configuration"; break;
+		return "Configuration";
 	case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK:
-		return "External Loopback"; break;
+		return "External Loopback";
 	case MCP251XFD_REG_CON_MODE_CAN2_0:
-		return "CAN 2.0"; break;
+		return "CAN 2.0";
 	case MCP251XFD_REG_CON_MODE_RESTRICTED:
-		return "Restricted Operation"; break;
+		return "Restricted Operation";
 	}
 
 	return "<unknown>";
diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
index ba25902dd78c..314f868b3465 100644
--- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
+++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c
@@ -173,7 +173,7 @@ mcp251xfd_regmap_nocrc_read(void *context,
 		memcpy(&buf_tx->cmd, reg, sizeof(buf_tx->cmd));
 		if (MCP251XFD_SANITIZE_SPI)
 			memset(buf_tx->data, 0x0, val_len);
-	};
+	}
 
 	err = spi_sync(spi, &msg);
 	if (err)
@@ -330,17 +330,17 @@ mcp251xfd_regmap_crc_read(void *context,
 			goto out;
 		}
 
-		netdev_dbg(priv->ndev,
-			   "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x) retrying.\n",
-			   reg, val_len, (int)val_len, buf_rx->data,
-			   get_unaligned_be16(buf_rx->data + val_len));
-	}
-
-	if (err) {
 		netdev_info(priv->ndev,
-			    "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x).\n",
+			    "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x) retrying.\n",
 			    reg, val_len, (int)val_len, buf_rx->data,
 			    get_unaligned_be16(buf_rx->data + val_len));
+	}
+
+	if (err) {
+		netdev_err(priv->ndev,
+			   "CRC read error at address 0x%04x (length=%zd, data=%*ph, CRC=0x%04x).\n",
+			   reg, val_len, (int)val_len, buf_rx->data,
+			   get_unaligned_be16(buf_rx->data + val_len));
 
 		return err;
 	}
diff --git a/drivers/net/can/ti_hecc.c b/drivers/net/can/ti_hecc.c
index 1d63006c97bc..9913f5458279 100644
--- a/drivers/net/can/ti_hecc.c
+++ b/drivers/net/can/ti_hecc.c
@@ -933,7 +933,7 @@ static int ti_hecc_probe(struct platform_device *pdev)
 	err = clk_prepare_enable(priv->clk);
 	if (err) {
 		dev_err(&pdev->dev, "clk_prepare_enable() failed\n");
-		goto probe_exit_clk;
+		goto probe_exit_release_clk;
 	}
 
 	priv->offload.mailbox_read = ti_hecc_mailbox_read;
@@ -942,7 +942,7 @@ static int ti_hecc_probe(struct platform_device *pdev)
 	err = can_rx_offload_add_timestamp(ndev, &priv->offload);
 	if (err) {
 		dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n");
-		goto probe_exit_clk;
+		goto probe_exit_disable_clk;
 	}
 
 	err = register_candev(ndev);
@@ -960,7 +960,9 @@ static int ti_hecc_probe(struct platform_device *pdev)
 
 probe_exit_offload:
 	can_rx_offload_del(&priv->offload);
-probe_exit_clk:
+probe_exit_disable_clk:
+	clk_disable_unprepare(priv->clk);
+probe_exit_release_clk:
 	clk_put(priv->clk);
 probe_exit_candev:
 	free_candev(ndev);
diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_core.c b/drivers/net/can/usb/peak_usb/pcan_usb_core.c
index d91df34e7fa8..c2764799f9ef 100644
--- a/drivers/net/can/usb/peak_usb/pcan_usb_core.c
+++ b/drivers/net/can/usb/peak_usb/pcan_usb_core.c
@@ -130,14 +130,55 @@ void peak_usb_get_ts_time(struct peak_time_ref *time_ref, u32 ts, ktime_t *time)
 	/* protect from getting time before setting now */
 	if (ktime_to_ns(time_ref->tv_host)) {
 		u64 delta_us;
+		s64 delta_ts = 0;
+
+		/* General case: dev_ts_1 < dev_ts_2 < ts, with:
+		 *
+		 * - dev_ts_1 = previous sync timestamp
+		 * - dev_ts_2 = last sync timestamp
+		 * - ts = event timestamp
+		 * - ts_period = known sync period (theoretical)
+		 *             ~ dev_ts2 - dev_ts1
+		 * *but*:
+		 *
+		 * - time counters wrap (see adapter->ts_used_bits)
+		 * - sometimes, dev_ts_1 < ts < dev_ts2
+		 *
+		 * "normal" case (sync time counters increase):
+		 * must take into account case when ts wraps (tsw)
+		 *
+		 *      < ts_period > <          >
+		 *     |             |            |
+		 *  ---+--------+----+-------0-+--+-->
+		 *     ts_dev_1 |    ts_dev_2  |
+		 *              ts             tsw
+		 */
+		if (time_ref->ts_dev_1 < time_ref->ts_dev_2) {
+			/* case when event time (tsw) wraps */
+			if (ts < time_ref->ts_dev_1)
+				delta_ts = 1 << time_ref->adapter->ts_used_bits;
+
+		/* Otherwise, sync time counter (ts_dev_2) has wrapped:
+		 * handle case when event time (tsn) hasn't.
+		 *
+		 *      < ts_period > <          >
+		 *     |             |            |
+		 *  ---+--------+--0-+---------+--+-->
+		 *     ts_dev_1 |    ts_dev_2  |
+		 *              tsn            ts
+		 */
+		} else if (time_ref->ts_dev_1 < ts) {
+			delta_ts = -(1 << time_ref->adapter->ts_used_bits);
+		}
 
-		delta_us = ts - time_ref->ts_dev_2;
-		if (ts < time_ref->ts_dev_2)
-			delta_us &= (1 << time_ref->adapter->ts_used_bits) - 1;
+		/* add delay between last sync and event timestamps */
+		delta_ts += (signed int)(ts - time_ref->ts_dev_2);
 
-		delta_us += time_ref->ts_total;
+		/* add time from beginning to last sync */
+		delta_ts += time_ref->ts_total;
 
-		delta_us *= time_ref->adapter->us_per_ts_scale;
+		/* convert ticks number into microseconds */
+		delta_us = delta_ts * time_ref->adapter->us_per_ts_scale;
 		delta_us >>= time_ref->adapter->us_per_ts_shift;
 
 		*time = ktime_add_us(time_ref->tv_host_0, delta_us);
diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_fd.c b/drivers/net/can/usb/peak_usb/pcan_usb_fd.c
index ab63fd9eb982..d29d20525588 100644
--- a/drivers/net/can/usb/peak_usb/pcan_usb_fd.c
+++ b/drivers/net/can/usb/peak_usb/pcan_usb_fd.c
@@ -468,12 +468,18 @@ static int pcan_usb_fd_decode_canmsg(struct pcan_usb_fd_if *usb_if,
 				     struct pucan_msg *rx_msg)
 {
 	struct pucan_rx_msg *rm = (struct pucan_rx_msg *)rx_msg;
-	struct peak_usb_device *dev = usb_if->dev[pucan_msg_get_channel(rm)];
-	struct net_device *netdev = dev->netdev;
+	struct peak_usb_device *dev;
+	struct net_device *netdev;
 	struct canfd_frame *cfd;
 	struct sk_buff *skb;
 	const u16 rx_msg_flags = le16_to_cpu(rm->flags);
 
+	if (pucan_msg_get_channel(rm) >= ARRAY_SIZE(usb_if->dev))
+		return -ENOMEM;
+
+	dev = usb_if->dev[pucan_msg_get_channel(rm)];
+	netdev = dev->netdev;
+
 	if (rx_msg_flags & PUCAN_MSG_EXT_DATA_LEN) {
 		/* CANFD frame case */
 		skb = alloc_canfd_skb(netdev, &cfd);
@@ -519,15 +525,21 @@ static int pcan_usb_fd_decode_status(struct pcan_usb_fd_if *usb_if,
 				     struct pucan_msg *rx_msg)
 {
 	struct pucan_status_msg *sm = (struct pucan_status_msg *)rx_msg;
-	struct peak_usb_device *dev = usb_if->dev[pucan_stmsg_get_channel(sm)];
-	struct pcan_usb_fd_device *pdev =
-			container_of(dev, struct pcan_usb_fd_device, dev);
+	struct pcan_usb_fd_device *pdev;
 	enum can_state new_state = CAN_STATE_ERROR_ACTIVE;
 	enum can_state rx_state, tx_state;
-	struct net_device *netdev = dev->netdev;
+	struct peak_usb_device *dev;
+	struct net_device *netdev;
 	struct can_frame *cf;
 	struct sk_buff *skb;
 
+	if (pucan_stmsg_get_channel(sm) >= ARRAY_SIZE(usb_if->dev))
+		return -ENOMEM;
+
+	dev = usb_if->dev[pucan_stmsg_get_channel(sm)];
+	pdev = container_of(dev, struct pcan_usb_fd_device, dev);
+	netdev = dev->netdev;
+
 	/* nothing should be sent while in BUS_OFF state */
 	if (dev->can.state == CAN_STATE_BUS_OFF)
 		return 0;
@@ -579,9 +591,14 @@ static int pcan_usb_fd_decode_error(struct pcan_usb_fd_if *usb_if,
 				    struct pucan_msg *rx_msg)
 {
 	struct pucan_error_msg *er = (struct pucan_error_msg *)rx_msg;
-	struct peak_usb_device *dev = usb_if->dev[pucan_ermsg_get_channel(er)];
-	struct pcan_usb_fd_device *pdev =
-			container_of(dev, struct pcan_usb_fd_device, dev);
+	struct pcan_usb_fd_device *pdev;
+	struct peak_usb_device *dev;
+
+	if (pucan_ermsg_get_channel(er) >= ARRAY_SIZE(usb_if->dev))
+		return -EINVAL;
+
+	dev = usb_if->dev[pucan_ermsg_get_channel(er)];
+	pdev = container_of(dev, struct pcan_usb_fd_device, dev);
 
 	/* keep a trace of tx and rx error counters for later use */
 	pdev->bec.txerr = er->tx_err_cnt;
@@ -595,11 +612,17 @@ static int pcan_usb_fd_decode_overrun(struct pcan_usb_fd_if *usb_if,
 				      struct pucan_msg *rx_msg)
 {
 	struct pcan_ufd_ovr_msg *ov = (struct pcan_ufd_ovr_msg *)rx_msg;
-	struct peak_usb_device *dev = usb_if->dev[pufd_omsg_get_channel(ov)];
-	struct net_device *netdev = dev->netdev;
+	struct peak_usb_device *dev;
+	struct net_device *netdev;
 	struct can_frame *cf;
 	struct sk_buff *skb;
 
+	if (pufd_omsg_get_channel(ov) >= ARRAY_SIZE(usb_if->dev))
+		return -EINVAL;
+
+	dev = usb_if->dev[pufd_omsg_get_channel(ov)];
+	netdev = dev->netdev;
+
 	/* allocate an skb to store the error frame */
 	skb = alloc_can_err_skb(netdev, &cf);
 	if (!skb)
@@ -716,6 +739,9 @@ static int pcan_usb_fd_encode_msg(struct peak_usb_device *dev,
 	u16 tx_msg_size, tx_msg_flags;
 	u8 can_dlc;
 
+	if (cfd->len > CANFD_MAX_DLEN)
+		return -EINVAL;
+
 	tx_msg_size = ALIGN(sizeof(struct pucan_tx_msg) + cfd->len, 4);
 	tx_msg->size = cpu_to_le16(tx_msg_size);
 	tx_msg->type = cpu_to_le16(PUCAN_MSG_CAN_TX);
diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
index 6c4d00d2dbdc..48d746e18f30 100644
--- a/drivers/net/can/xilinx_can.c
+++ b/drivers/net/can/xilinx_can.c
@@ -1395,7 +1395,7 @@ static int xcan_open(struct net_device *ndev)
 	if (ret < 0) {
 		netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
 			   __func__, ret);
-		return ret;
+		goto err;
 	}
 
 	ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
@@ -1479,6 +1479,7 @@ static int xcan_get_berr_counter(const struct net_device *ndev,
 	if (ret < 0) {
 		netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
 			   __func__, ret);
+		pm_runtime_put(priv->dev);
 		return ret;
 	}
 
@@ -1793,7 +1794,7 @@ static int xcan_probe(struct platform_device *pdev)
 	if (ret < 0) {
 		netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
 			   __func__, ret);
-		goto err_pmdisable;
+		goto err_disableclks;
 	}
 
 	if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {
@@ -1828,7 +1829,6 @@ static int xcan_probe(struct platform_device *pdev)
 
 err_disableclks:
 	pm_runtime_put(priv->dev);
-err_pmdisable:
 	pm_runtime_disable(&pdev->dev);
 err_free:
 	free_candev(ndev);
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 53064e0e1618..5bdac669a339 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1219,8 +1219,8 @@ qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
 	priv->port_mtu[port] = new_mtu;
 
 	for (i = 0; i < QCA8K_NUM_PORTS; i++)
-		if (priv->port_mtu[port] > mtu)
-			mtu = priv->port_mtu[port];
+		if (priv->port_mtu[i] > mtu)
+			mtu = priv->port_mtu[i];
 
 	/* Include L2 header / FCS length */
 	qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 883e47c5b1a7..286f0341bdf8 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -1929,7 +1929,8 @@ static inline int macb_clear_csum(struct sk_buff *skb)
 
 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
 {
-	bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb);
+	bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
+		      skb_is_nonlinear(*skb);
 	int padlen = ETH_ZLEN - (*skb)->len;
 	int headroom = skb_headroom(*skb);
 	int tailroom = skb_tailroom(*skb);
diff --git a/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_cm.c b/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_cm.c
index d581c4e623f8..96d561653496 100644
--- a/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_cm.c
+++ b/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_cm.c
@@ -212,7 +212,7 @@ static struct sk_buff *alloc_ctrl_skb(struct sk_buff *skb, int len)
 {
 	if (likely(skb && !skb_shared(skb) && !skb_cloned(skb))) {
 		__skb_trim(skb, 0);
-		refcount_add(2, &skb->users);
+		refcount_inc(&skb->users);
 	} else {
 		skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
 	}
diff --git a/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_hw.c b/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_hw.c
index f1820aca0d33..62c829023da5 100644
--- a/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_hw.c
+++ b/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_hw.c
@@ -383,6 +383,9 @@ int chtls_setkey(struct chtls_sock *csk, u32 keylen,
 	if (ret)
 		goto out_notcb;
 
+	if (unlikely(csk_flag(sk, CSK_ABORT_SHUTDOWN)))
+		goto out_notcb;
+
 	set_wr_txq(skb, CPL_PRIORITY_DATA, csk->tlshws.txqid);
 	csk->wr_credits -= DIV_ROUND_UP(len, 16);
 	csk->wr_unacked += DIV_ROUND_UP(len, 16);
diff --git a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
index 06cc863f4dd6..d9c285948fc2 100644
--- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
+++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
@@ -174,12 +174,17 @@ MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
 #define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)
 #define DPAA_TIME_STAMP_SIZE 8
 #define DPAA_HASH_RESULTS_SIZE 8
+#define DPAA_HWA_SIZE (DPAA_PARSE_RESULTS_SIZE + DPAA_TIME_STAMP_SIZE \
+		       + DPAA_HASH_RESULTS_SIZE)
+#define DPAA_RX_PRIV_DATA_DEFAULT_SIZE (DPAA_TX_PRIV_DATA_SIZE + \
+					dpaa_rx_extra_headroom)
 #ifdef CONFIG_DPAA_ERRATUM_A050385
-#define DPAA_RX_PRIV_DATA_SIZE (DPAA_A050385_ALIGN - (DPAA_PARSE_RESULTS_SIZE\
-	 + DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE))
+#define DPAA_RX_PRIV_DATA_A050385_SIZE (DPAA_A050385_ALIGN - DPAA_HWA_SIZE)
+#define DPAA_RX_PRIV_DATA_SIZE (fman_has_errata_a050385() ? \
+				DPAA_RX_PRIV_DATA_A050385_SIZE : \
+				DPAA_RX_PRIV_DATA_DEFAULT_SIZE)
 #else
-#define DPAA_RX_PRIV_DATA_SIZE	(u16)(DPAA_TX_PRIV_DATA_SIZE + \
-					dpaa_rx_extra_headroom)
+#define DPAA_RX_PRIV_DATA_SIZE DPAA_RX_PRIV_DATA_DEFAULT_SIZE
 #endif
 
 #define DPAA_ETH_PCD_RXQ_NUM	128
@@ -2840,7 +2845,8 @@ out_error:
 	return err;
 }
 
-static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl)
+static u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl,
+			     enum port_type port)
 {
 	u16 headroom;
 
@@ -2854,10 +2860,12 @@ static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl)
 	 *
 	 * Also make sure the headroom is a multiple of data_align bytes
 	 */
-	headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE +
-		DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE);
+	headroom = (u16)(bl[port].priv_data_size + DPAA_HWA_SIZE);
 
-	return ALIGN(headroom, DPAA_FD_DATA_ALIGNMENT);
+	if (port == RX)
+		return ALIGN(headroom, DPAA_FD_RX_DATA_ALIGNMENT);
+	else
+		return ALIGN(headroom, DPAA_FD_DATA_ALIGNMENT);
 }
 
 static int dpaa_eth_probe(struct platform_device *pdev)
@@ -3025,8 +3033,8 @@ static int dpaa_eth_probe(struct platform_device *pdev)
 			goto free_dpaa_fqs;
 	}
 
-	priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]);
-	priv->rx_headroom = dpaa_get_headroom(&priv->buf_layout[RX]);
+	priv->tx_headroom = dpaa_get_headroom(priv->buf_layout, TX);
+	priv->rx_headroom = dpaa_get_headroom(priv->buf_layout, RX);
 
 	/* All real interfaces need their ports initialized */
 	err = dpaa_eth_init_ports(mac_dev, dpaa_bp, &port_fqs,
diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h
index 832a2175636d..c527f4ee1d3a 100644
--- a/drivers/net/ethernet/freescale/fec.h
+++ b/drivers/net/ethernet/freescale/fec.h
@@ -456,6 +456,12 @@ struct bufdesc_ex {
  */
 #define FEC_QUIRK_HAS_FRREG		(1 << 16)
 
+/* Some FEC hardware blocks need the MMFR cleared at setup time to avoid
+ * the generation of an MII event. This must be avoided in the older
+ * FEC blocks where it will stop MII events being generated.
+ */
+#define FEC_QUIRK_CLEAR_SETUP_MII	(1 << 17)
+
 struct bufdesc_prop {
 	int qid;
 	/* Address of Rx and Tx buffers */
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 8f7eca1e7716..d7919555250d 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -100,14 +100,14 @@ static const struct fec_devinfo fec_imx27_info = {
 static const struct fec_devinfo fec_imx28_info = {
 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
 		  FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
-		  FEC_QUIRK_HAS_FRREG,
+		  FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII,
 };
 
 static const struct fec_devinfo fec_imx6q_info = {
 	.quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
-		  FEC_QUIRK_HAS_RACC,
+		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII,
 };
 
 static const struct fec_devinfo fec_mvf600_info = {
@@ -119,7 +119,8 @@ static const struct fec_devinfo fec_imx6x_info = {
 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
 		  FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
-		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
+		  FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
+		  FEC_QUIRK_CLEAR_SETUP_MII,
 };
 
 static const struct fec_devinfo fec_imx6ul_info = {
@@ -127,7 +128,7 @@ static const struct fec_devinfo fec_imx6ul_info = {
 		  FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
 		  FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
 		  FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
-		  FEC_QUIRK_HAS_COALESCE,
+		  FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII,
 };
 
 static struct platform_device_id fec_devtype[] = {
@@ -2134,15 +2135,17 @@ static int fec_enet_mii_init(struct platform_device *pdev)
 	if (suppress_preamble)
 		fep->phy_speed |= BIT(7);
 
-	/* Clear MMFR to avoid to generate MII event by writing MSCR.
-	 * MII event generation condition:
-	 * - writing MSCR:
-	 *	- mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
-	 *	  mscr_reg_data_in[7:0] != 0
-	 * - writing MMFR:
-	 *	- mscr[7:0]_not_zero
-	 */
-	writel(0, fep->hwp + FEC_MII_DATA);
+	if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) {
+		/* Clear MMFR to avoid to generate MII event by writing MSCR.
+		 * MII event generation condition:
+		 * - writing MSCR:
+		 *	- mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
+		 *	  mscr_reg_data_in[7:0] != 0
+		 * - writing MMFR:
+		 *	- mscr[7:0]_not_zero
+		 */
+		writel(0, fep->hwp + FEC_MII_DATA);
+	}
 
 	writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
 
diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c
index 41dd3d0f3452..d391a45cebb6 100644
--- a/drivers/net/ethernet/freescale/gianfar.c
+++ b/drivers/net/ethernet/freescale/gianfar.c
@@ -1829,20 +1829,12 @@ static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
 		fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
 
 	/* make space for additional header when fcb is needed */
-	if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
-		struct sk_buff *skb_new;
-
-		skb_new = skb_realloc_headroom(skb, fcb_len);
-		if (!skb_new) {
+	if (fcb_len) {
+		if (unlikely(skb_cow_head(skb, fcb_len))) {
 			dev->stats.tx_errors++;
 			dev_kfree_skb_any(skb);
 			return NETDEV_TX_OK;
 		}
-
-		if (skb->sk)
-			skb_set_owner_w(skb_new, skb->sk);
-		dev_consume_skb_any(skb);
-		skb = skb_new;
 	}
 
 	/* total number of fragments in the SKB */
@@ -3380,7 +3372,7 @@ static int gfar_probe(struct platform_device *ofdev)
 
 	if (dev->features & NETIF_F_IP_CSUM ||
 	    priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
-		dev->needed_headroom = GMAC_FCB_LEN;
+		dev->needed_headroom = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
 
 	/* Initializing some of the rx/tx queue level parameters */
 	for (i = 0; i < priv->num_tx_queues; i++) {
diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
index af4dfbe28d56..da15913879f8 100644
--- a/drivers/net/ethernet/ibm/ibmvnic.c
+++ b/drivers/net/ethernet/ibm/ibmvnic.c
@@ -1185,18 +1185,27 @@ static int ibmvnic_open(struct net_device *netdev)
 	if (adapter->state != VNIC_CLOSED) {
 		rc = ibmvnic_login(netdev);
 		if (rc)
-			return rc;
+			goto out;
 
 		rc = init_resources(adapter);
 		if (rc) {
 			netdev_err(netdev, "failed to initialize resources\n");
 			release_resources(adapter);
-			return rc;
+			goto out;
 		}
 	}
 
 	rc = __ibmvnic_open(netdev);
 
+out:
+	/*
+	 * If open fails due to a pending failover, set device state and
+	 * return. Device operation will be handled by reset routine.
+	 */
+	if (rc && adapter->failover_pending) {
+		adapter->state = VNIC_OPEN;
+		rc = 0;
+	}
 	return rc;
 }
 
@@ -1922,6 +1931,13 @@ static int do_reset(struct ibmvnic_adapter *adapter,
 		   rwi->reset_reason);
 
 	rtnl_lock();
+	/*
+	 * Now that we have the rtnl lock, clear any pending failover.
+	 * This will ensure ibmvnic_open() has either completed or will
+	 * block until failover is complete.
+	 */
+	if (rwi->reset_reason == VNIC_RESET_FAILOVER)
+		adapter->failover_pending = false;
 
 	netif_carrier_off(netdev);
 	adapter->reset_reason = rwi->reset_reason;
@@ -2202,6 +2218,13 @@ static void __ibmvnic_reset(struct work_struct *work)
 			/* CHANGE_PARAM requestor holds rtnl_lock */
 			rc = do_change_param_reset(adapter, rwi, reset_state);
 		} else if (adapter->force_reset_recovery) {
+			/*
+			 * Since we are doing a hard reset now, clear the
+			 * failover_pending flag so we don't ignore any
+			 * future MOBILITY or other resets.
+			 */
+			adapter->failover_pending = false;
+
 			/* Transport event occurred during previous reset */
 			if (adapter->wait_for_reset) {
 				/* Previous was CHANGE_PARAM; caller locked */
@@ -2266,9 +2289,15 @@ static int ibmvnic_reset(struct ibmvnic_adapter *adapter,
 	unsigned long flags;
 	int ret;
 
+	/*
+	 * If failover is pending don't schedule any other reset.
+	 * Instead let the failover complete. If there is already a
+	 * a failover reset scheduled, we will detect and drop the
+	 * duplicate reset when walking the ->rwi_list below.
+	 */
 	if (adapter->state == VNIC_REMOVING ||
 	    adapter->state == VNIC_REMOVED ||
-	    adapter->failover_pending) {
+	    (adapter->failover_pending && reason != VNIC_RESET_FAILOVER)) {
 		ret = EBUSY;
 		netdev_dbg(netdev, "Adapter removing or pending failover, skipping reset\n");
 		goto err;
@@ -4713,7 +4742,6 @@ static void ibmvnic_handle_crq(union ibmvnic_crq *crq,
 		case IBMVNIC_CRQ_INIT:
 			dev_info(dev, "Partner initialized\n");
 			adapter->from_passive_init = true;
-			adapter->failover_pending = false;
 			if (!completion_done(&adapter->init_done)) {
 				complete(&adapter->init_done);
 				adapter->init_done_rc = -EIO;
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
index ed9808fc743b..35c72d4a78b3 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
@@ -126,6 +126,11 @@ static int ionic_get_link_ksettings(struct net_device *netdev,
 
 	ethtool_link_ksettings_zero_link_mode(ks, supported);
 
+	if (!idev->port_info) {
+		netdev_err(netdev, "port_info not initialized\n");
+		return -EOPNOTSUPP;
+	}
+
 	/* The port_info data is found in a DMA space that the NIC keeps
 	 * up-to-date, so there's no need to request the data from the
 	 * NIC, we already have it in our memory space.
diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index 00f13805c6f7..7766d73823eb 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -4080,9 +4080,17 @@ err_out:
 	return -EIO;
 }
 
-static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
+static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp)
 {
-	return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
+	switch (tp->mac_version) {
+	case RTL_GIGA_MAC_VER_34:
+	case RTL_GIGA_MAC_VER_60:
+	case RTL_GIGA_MAC_VER_61:
+	case RTL_GIGA_MAC_VER_63:
+		return true;
+	default:
+		return false;
+	}
 }
 
 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
@@ -4154,7 +4162,7 @@ static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
 
 		opts[1] |= transport_offset << TCPHO_SHIFT;
 	} else {
-		if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
+		if (unlikely(skb->len < ETH_ZLEN && rtl_test_hw_pad_bug(tp)))
 			return !eth_skb_pad(skb);
 	}
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index b6e5e3e36b63..81ee0a071b4e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -625,13 +625,6 @@ static int intel_eth_pci_probe(struct pci_dev *pdev,
 	if (ret)
 		return ret;
 
-	if (plat->eee_usecs_rate > 0) {
-		u32 tx_lpi_usec;
-
-		tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
-		writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
-	}
-
 	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
 	if (ret < 0)
 		return ret;
@@ -641,6 +634,13 @@ static int intel_eth_pci_probe(struct pci_dev *pdev,
 	res.wol_irq = pci_irq_vector(pdev, 0);
 	res.irq = pci_irq_vector(pdev, 0);
 
+	if (plat->eee_usecs_rate > 0) {
+		u32 tx_lpi_usec;
+
+		tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
+		writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
+	}
+
 	ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
 	if (ret) {
 		pci_free_irq_vectors(pdev);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 220626a8d499..d833908b660a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -4757,6 +4757,7 @@ static void stmmac_napi_add(struct net_device *dev)
 
 		ch->priv_data = priv;
 		ch->index = queue;
+		spin_lock_init(&ch->lock);
 
 		if (queue < priv->plat->rx_queues_to_use) {
 			netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx,
diff --git a/drivers/net/ethernet/ti/cpsw_ethtool.c b/drivers/net/ethernet/ti/cpsw_ethtool.c
index 4d02c5135611..4619c3a950b0 100644
--- a/drivers/net/ethernet/ti/cpsw_ethtool.c
+++ b/drivers/net/ethernet/ti/cpsw_ethtool.c
@@ -728,7 +728,6 @@ int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info)
 		(1 << HWTSTAMP_TX_ON);
 	info->rx_filters =
 		(1 << HWTSTAMP_FILTER_NONE) |
-		(1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
 		(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
 	return 0;
 }
diff --git a/drivers/net/ethernet/ti/cpsw_priv.c b/drivers/net/ethernet/ti/cpsw_priv.c
index 51cc29f39038..31c5e36ff706 100644
--- a/drivers/net/ethernet/ti/cpsw_priv.c
+++ b/drivers/net/ethernet/ti/cpsw_priv.c
@@ -639,13 +639,10 @@ static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 		break;
 	case HWTSTAMP_FILTER_ALL:
 	case HWTSTAMP_FILTER_NTP_ALL:
-		return -ERANGE;
 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
-		priv->rx_ts_enabled = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
-		cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
-		break;
+		return -ERANGE;
 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c
index 1d18c10e8f82..34aa196b7465 100644
--- a/drivers/net/phy/sfp.c
+++ b/drivers/net/phy/sfp.c
@@ -2389,7 +2389,8 @@ static int sfp_probe(struct platform_device *pdev)
 			continue;
 
 		sfp->gpio_irq[i] = gpiod_to_irq(sfp->gpio[i]);
-		if (!sfp->gpio_irq[i]) {
+		if (sfp->gpio_irq[i] < 0) {
+			sfp->gpio_irq[i] = 0;
 			sfp->need_poll = true;
 			continue;
 		}
diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
index a322f51873d0..581ed51abb53 100644
--- a/drivers/net/usb/qmi_wwan.c
+++ b/drivers/net/usb/qmi_wwan.c
@@ -1309,6 +1309,7 @@ static const struct usb_device_id products[] = {
 	{QMI_FIXED_INTF(0x1bc7, 0x1101, 3)},	/* Telit ME910 dual modem */
 	{QMI_FIXED_INTF(0x1bc7, 0x1200, 5)},	/* Telit LE920 */
 	{QMI_QUIRK_SET_DTR(0x1bc7, 0x1201, 2)},	/* Telit LE920, LE920A4 */
+	{QMI_QUIRK_SET_DTR(0x1bc7, 0x1230, 2)},	/* Telit LE910Cx */
 	{QMI_QUIRK_SET_DTR(0x1bc7, 0x1260, 2)},	/* Telit LE910Cx */
 	{QMI_QUIRK_SET_DTR(0x1bc7, 0x1261, 2)},	/* Telit LE910Cx */
 	{QMI_QUIRK_SET_DTR(0x1bc7, 0x1900, 1)},	/* Telit LN940 series */
diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index 376096bfc54a..40ca71b29bb9 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -4582,8 +4582,7 @@ void nvme_start_queues(struct nvme_ctrl *ctrl)
 }
 EXPORT_SYMBOL_GPL(nvme_start_queues);
 
-
-void nvme_sync_queues(struct nvme_ctrl *ctrl)
+void nvme_sync_io_queues(struct nvme_ctrl *ctrl)
 {
 	struct nvme_ns *ns;
 
@@ -4591,7 +4590,12 @@ void nvme_sync_queues(struct nvme_ctrl *ctrl)
 	list_for_each_entry(ns, &ctrl->namespaces, list)
 		blk_sync_queue(ns->queue);
 	up_read(&ctrl->namespaces_rwsem);
+}
+EXPORT_SYMBOL_GPL(nvme_sync_io_queues);
 
+void nvme_sync_queues(struct nvme_ctrl *ctrl)
+{
+	nvme_sync_io_queues(ctrl);
 	if (ctrl->admin_q)
 		blk_sync_queue(ctrl->admin_q);
 }
diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index cc111136a981..bc330bf0d3bd 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -602,6 +602,7 @@ void nvme_stop_queues(struct nvme_ctrl *ctrl);
 void nvme_start_queues(struct nvme_ctrl *ctrl);
 void nvme_kill_queues(struct nvme_ctrl *ctrl);
 void nvme_sync_queues(struct nvme_ctrl *ctrl);
+void nvme_sync_io_queues(struct nvme_ctrl *ctrl);
 void nvme_unfreeze(struct nvme_ctrl *ctrl);
 void nvme_wait_freeze(struct nvme_ctrl *ctrl);
 int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index df8f3612107f..0578ff253c47 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -198,6 +198,7 @@ struct nvme_queue {
 	u32 q_depth;
 	u16 cq_vector;
 	u16 sq_tail;
+	u16 last_sq_tail;
 	u16 cq_head;
 	u16 qid;
 	u8 cq_phase;
@@ -455,11 +456,24 @@ static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 	return 0;
 }
 
-static inline void nvme_write_sq_db(struct nvme_queue *nvmeq)
+/*
+ * Write sq tail if we are asked to, or if the next command would wrap.
+ */
+static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 {
+	if (!write_sq) {
+		u16 next_tail = nvmeq->sq_tail + 1;
+
+		if (next_tail == nvmeq->q_depth)
+			next_tail = 0;
+		if (next_tail != nvmeq->last_sq_tail)
+			return;
+	}
+
 	if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 			nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 		writel(nvmeq->sq_tail, nvmeq->q_db);
+	nvmeq->last_sq_tail = nvmeq->sq_tail;
 }
 
 /**
@@ -476,8 +490,7 @@ static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
 	       cmd, sizeof(*cmd));
 	if (++nvmeq->sq_tail == nvmeq->q_depth)
 		nvmeq->sq_tail = 0;
-	if (write_sq)
-		nvme_write_sq_db(nvmeq);
+	nvme_write_sq_db(nvmeq, write_sq);
 	spin_unlock(&nvmeq->sq_lock);
 }
 
@@ -486,7 +499,8 @@ static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 	struct nvme_queue *nvmeq = hctx->driver_data;
 
 	spin_lock(&nvmeq->sq_lock);
-	nvme_write_sq_db(nvmeq);
+	if (nvmeq->sq_tail != nvmeq->last_sq_tail)
+		nvme_write_sq_db(nvmeq, true);
 	spin_unlock(&nvmeq->sq_lock);
 }
 
@@ -1496,6 +1510,7 @@ static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
 	struct nvme_dev *dev = nvmeq->dev;
 
 	nvmeq->sq_tail = 0;
+	nvmeq->last_sq_tail = 0;
 	nvmeq->cq_head = 0;
 	nvmeq->cq_phase = 1;
 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
diff --git a/drivers/nvme/host/rdma.c b/drivers/nvme/host/rdma.c
index 541b0cba6d80..65e3d0ef36e1 100644
--- a/drivers/nvme/host/rdma.c
+++ b/drivers/nvme/host/rdma.c
@@ -122,7 +122,6 @@ struct nvme_rdma_ctrl {
 	struct sockaddr_storage src_addr;
 
 	struct nvme_ctrl	ctrl;
-	struct mutex		teardown_lock;
 	bool			use_inline_data;
 	u32			io_queues[HCTX_MAX_TYPES];
 };
@@ -1010,8 +1009,8 @@ out_free_io_queues:
 static void nvme_rdma_teardown_admin_queue(struct nvme_rdma_ctrl *ctrl,
 		bool remove)
 {
-	mutex_lock(&ctrl->teardown_lock);
 	blk_mq_quiesce_queue(ctrl->ctrl.admin_q);
+	blk_sync_queue(ctrl->ctrl.admin_q);
 	nvme_rdma_stop_queue(&ctrl->queues[0]);
 	if (ctrl->ctrl.admin_tagset) {
 		blk_mq_tagset_busy_iter(ctrl->ctrl.admin_tagset,
@@ -1021,16 +1020,15 @@ static void nvme_rdma_teardown_admin_queue(struct nvme_rdma_ctrl *ctrl,
 	if (remove)
 		blk_mq_unquiesce_queue(ctrl->ctrl.admin_q);
 	nvme_rdma_destroy_admin_queue(ctrl, remove);
-	mutex_unlock(&ctrl->teardown_lock);
 }
 
 static void nvme_rdma_teardown_io_queues(struct nvme_rdma_ctrl *ctrl,
 		bool remove)
 {
-	mutex_lock(&ctrl->teardown_lock);
 	if (ctrl->ctrl.queue_count > 1) {
 		nvme_start_freeze(&ctrl->ctrl);
 		nvme_stop_queues(&ctrl->ctrl);
+		nvme_sync_io_queues(&ctrl->ctrl);
 		nvme_rdma_stop_io_queues(ctrl);
 		if (ctrl->ctrl.tagset) {
 			blk_mq_tagset_busy_iter(ctrl->ctrl.tagset,
@@ -1041,7 +1039,6 @@ static void nvme_rdma_teardown_io_queues(struct nvme_rdma_ctrl *ctrl,
 			nvme_start_queues(&ctrl->ctrl);
 		nvme_rdma_destroy_io_queues(ctrl, remove);
 	}
-	mutex_unlock(&ctrl->teardown_lock);
 }
 
 static void nvme_rdma_free_ctrl(struct nvme_ctrl *nctrl)
@@ -1976,16 +1973,12 @@ static void nvme_rdma_complete_timed_out(struct request *rq)
 {
 	struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
 	struct nvme_rdma_queue *queue = req->queue;
-	struct nvme_rdma_ctrl *ctrl = queue->ctrl;
 
-	/* fence other contexts that may complete the command */
-	mutex_lock(&ctrl->teardown_lock);
 	nvme_rdma_stop_queue(queue);
-	if (!blk_mq_request_completed(rq)) {
+	if (blk_mq_request_started(rq) && !blk_mq_request_completed(rq)) {
 		nvme_req(rq)->status = NVME_SC_HOST_ABORTED_CMD;
 		blk_mq_complete_request(rq);
 	}
-	mutex_unlock(&ctrl->teardown_lock);
 }
 
 static enum blk_eh_timer_return
@@ -2320,7 +2313,6 @@ static struct nvme_ctrl *nvme_rdma_create_ctrl(struct device *dev,
 		return ERR_PTR(-ENOMEM);
 	ctrl->ctrl.opts = opts;
 	INIT_LIST_HEAD(&ctrl->list);
-	mutex_init(&ctrl->teardown_lock);
 
 	if (!(opts->mask & NVMF_OPT_TRSVCID)) {
 		opts->trsvcid =
diff --git a/drivers/nvme/host/tcp.c b/drivers/nvme/host/tcp.c
index d6a3e1487354..c0c33320fe65 100644
--- a/drivers/nvme/host/tcp.c
+++ b/drivers/nvme/host/tcp.c
@@ -124,7 +124,6 @@ struct nvme_tcp_ctrl {
 	struct sockaddr_storage src_addr;
 	struct nvme_ctrl	ctrl;
 
-	struct mutex		teardown_lock;
 	struct work_struct	err_work;
 	struct delayed_work	connect_work;
 	struct nvme_tcp_request async_req;
@@ -1886,8 +1885,8 @@ out_free_queue:
 static void nvme_tcp_teardown_admin_queue(struct nvme_ctrl *ctrl,
 		bool remove)
 {
-	mutex_lock(&to_tcp_ctrl(ctrl)->teardown_lock);
 	blk_mq_quiesce_queue(ctrl->admin_q);
+	blk_sync_queue(ctrl->admin_q);
 	nvme_tcp_stop_queue(ctrl, 0);
 	if (ctrl->admin_tagset) {
 		blk_mq_tagset_busy_iter(ctrl->admin_tagset,
@@ -1897,18 +1896,17 @@ static void nvme_tcp_teardown_admin_queue(struct nvme_ctrl *ctrl,
 	if (remove)
 		blk_mq_unquiesce_queue(ctrl->admin_q);
 	nvme_tcp_destroy_admin_queue(ctrl, remove);
-	mutex_unlock(&to_tcp_ctrl(ctrl)->teardown_lock);
 }
 
 static void nvme_tcp_teardown_io_queues(struct nvme_ctrl *ctrl,
 		bool remove)
 {
-	mutex_lock(&to_tcp_ctrl(ctrl)->teardown_lock);
 	if (ctrl->queue_count <= 1)
-		goto out;
+		return;
 	blk_mq_quiesce_queue(ctrl->admin_q);
 	nvme_start_freeze(ctrl);
 	nvme_stop_queues(ctrl);
+	nvme_sync_io_queues(ctrl);
 	nvme_tcp_stop_io_queues(ctrl);
 	if (ctrl->tagset) {
 		blk_mq_tagset_busy_iter(ctrl->tagset,
@@ -1918,8 +1916,6 @@ static void nvme_tcp_teardown_io_queues(struct nvme_ctrl *ctrl,
 	if (remove)
 		nvme_start_queues(ctrl);
 	nvme_tcp_destroy_io_queues(ctrl, remove);
-out:
-	mutex_unlock(&to_tcp_ctrl(ctrl)->teardown_lock);
 }
 
 static void nvme_tcp_reconnect_or_remove(struct nvme_ctrl *ctrl)
@@ -2171,14 +2167,11 @@ static void nvme_tcp_complete_timed_out(struct request *rq)
 	struct nvme_tcp_request *req = blk_mq_rq_to_pdu(rq);
 	struct nvme_ctrl *ctrl = &req->queue->ctrl->ctrl;
 
-	/* fence other contexts that may complete the command */
-	mutex_lock(&to_tcp_ctrl(ctrl)->teardown_lock);
 	nvme_tcp_stop_queue(ctrl, nvme_tcp_queue_id(req->queue));
-	if (!blk_mq_request_completed(rq)) {
+	if (blk_mq_request_started(rq) && !blk_mq_request_completed(rq)) {
 		nvme_req(rq)->status = NVME_SC_HOST_ABORTED_CMD;
 		blk_mq_complete_request(rq);
 	}
-	mutex_unlock(&to_tcp_ctrl(ctrl)->teardown_lock);
 }
 
 static enum blk_eh_timer_return
@@ -2455,7 +2448,6 @@ static struct nvme_ctrl *nvme_tcp_create_ctrl(struct device *dev,
 			nvme_tcp_reconnect_ctrl_work);
 	INIT_WORK(&ctrl->err_work, nvme_tcp_error_recovery_work);
 	INIT_WORK(&ctrl->ctrl.reset_work, nvme_reset_ctrl_work);
-	mutex_init(&ctrl->teardown_lock);
 
 	if (!(opts->mask & NVMF_OPT_TRSVCID)) {
 		opts->trsvcid =
diff --git a/drivers/of/device.c b/drivers/of/device.c
index 3a469c79e6b0..aedfaaafd3e7 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -112,7 +112,7 @@ int of_dma_configure_id(struct device *dev, struct device_node *np,
 		u64 dma_end = 0;
 
 		/* Determine the overall bounds of all DMA regions */
-		for (dma_start = ~0ULL; r->size; r++) {
+		for (dma_start = ~0; r->size; r++) {
 			/* Take lower and upper limits */
 			if (r->dma_start < dma_start)
 				dma_start = r->dma_start;
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index 2483e765318a..0e0a5269dc82 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -1181,6 +1181,10 @@ static void _opp_table_kref_release(struct kref *kref)
 	struct opp_device *opp_dev, *temp;
 	int i;
 
+	/* Drop the lock as soon as we can */
+	list_del(&opp_table->node);
+	mutex_unlock(&opp_table_lock);
+
 	_of_clear_opp_table(opp_table);
 
 	/* Release clk */
@@ -1208,10 +1212,7 @@ static void _opp_table_kref_release(struct kref *kref)
 
 	mutex_destroy(&opp_table->genpd_virt_dev_lock);
 	mutex_destroy(&opp_table->lock);
-	list_del(&opp_table->node);
 	kfree(opp_table);
-
-	mutex_unlock(&opp_table_lock);
 }
 
 void dev_pm_opp_put_opp_table(struct opp_table *opp_table)
@@ -1930,7 +1931,7 @@ struct opp_table *dev_pm_opp_register_set_opp_helper(struct device *dev,
 		return ERR_PTR(-EINVAL);
 
 	opp_table = dev_pm_opp_get_opp_table(dev);
-	if (!IS_ERR(opp_table))
+	if (IS_ERR(opp_table))
 		return opp_table;
 
 	/* This should be called before OPPs are initialized */
diff --git a/drivers/opp/of.c b/drivers/opp/of.c
index 874b58756220..9faeb83e4b32 100644
--- a/drivers/opp/of.c
+++ b/drivers/opp/of.c
@@ -944,6 +944,8 @@ static int _of_add_opp_table_v1(struct device *dev, struct opp_table *opp_table)
 		nr -= 2;
 	}
 
+	return 0;
+
 remove_static_opp:
 	_opp_remove_all_static(opp_table);
 
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 674f32db85ca..44c2a6572199 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	 * ATU, so we should not program the ATU here.
 	 */
 	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
-		struct resource_entry *entry =
-			resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
+		struct resource_entry *tmp, *entry = NULL;
+
+		/* Get last memory resource entry */
+		resource_list_for_each_entry(tmp, &pp->bridge->windows)
+			if (resource_type(tmp->res) == IORESOURCE_MEM)
+				entry = tmp;
 
 		dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
 					  PCIE_ATU_TYPE_MEM, entry->res->start,
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index eee82838f4ba..ed13e81cd691 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -958,25 +958,16 @@ static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
 }
 
 /*
- * We can't use devm_of_pci_get_host_bridge_resources() because we
- * need to parse our special DT properties encoding the MEM and IO
- * apertures.
+ * devm_of_pci_get_host_bridge_resources() only sets up translateable resources,
+ * so we need extra resource setup parsing our special DT properties encoding
+ * the MEM and IO apertures.
  */
 static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
 {
 	struct device *dev = &pcie->pdev->dev;
-	struct device_node *np = dev->of_node;
 	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
 	int ret;
 
-	/* Get the bus range */
-	ret = of_pci_parse_bus_range(np, &pcie->busn);
-	if (ret) {
-		dev_err(dev, "failed to parse bus-range property: %d\n", ret);
-		return ret;
-	}
-	pci_add_resource(&bridge->windows, &pcie->busn);
-
 	/* Get the PCIe memory aperture */
 	mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
 	if (resource_size(&pcie->mem) == 0) {
@@ -986,6 +977,9 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
 
 	pcie->mem.name = "PCI MEM";
 	pci_add_resource(&bridge->windows, &pcie->mem);
+	ret = devm_request_resource(dev, &iomem_resource, &pcie->mem);
+	if (ret)
+		return ret;
 
 	/* Get the PCIe IO aperture */
 	mvebu_mbus_get_pcie_io_aperture(&pcie->io);
@@ -999,9 +993,12 @@ static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
 		pcie->realio.name = "PCI I/O";
 
 		pci_add_resource(&bridge->windows, &pcie->realio);
+		ret = devm_request_resource(dev, &ioport_resource, &pcie->realio);
+		if (ret)
+			return ret;
 	}
 
-	return devm_request_pci_bus_resources(dev, &bridge->windows);
+	return 0;
 }
 
 /*
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 6d4d5a2f923d..e578d34095e9 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3516,8 +3516,13 @@ void pci_acs_init(struct pci_dev *dev)
 {
 	dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
 
-	if (dev->acs_cap)
-		pci_enable_acs(dev);
+	/*
+	 * Attempt to enable ACS regardless of capability because some Root
+	 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
+	 * the standard ACS capability but still support ACS via those
+	 * quirks.
+	 */
+	pci_enable_acs(dev);
 }
 
 /**
diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 0b2830efc574..70d6d52bc1e2 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -620,7 +620,7 @@ static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
 	case ARBITRARY_UNIT:
 	default:
 		return value;
-	};
+	}
 
 	if (to_raw)
 		return div64_u64(value, units) * scale;
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index a4ffd71696da..a5ad553da8cd 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -4165,6 +4165,8 @@ int regulator_get_voltage_rdev(struct regulator_dev *rdev)
 		ret = rdev->desc->fixed_uV;
 	} else if (rdev->supply) {
 		ret = regulator_get_voltage_rdev(rdev->supply->rdev);
+	} else if (rdev->supply_name) {
+		return -EPROBE_DEFER;
 	} else {
 		return -EINVAL;
 	}
diff --git a/drivers/s390/crypto/ap_bus.c b/drivers/s390/crypto/ap_bus.c
index 485cbfcbf06e..ef738b42a092 100644
--- a/drivers/s390/crypto/ap_bus.c
+++ b/drivers/s390/crypto/ap_bus.c
@@ -680,7 +680,10 @@ static int ap_device_probe(struct device *dev)
 {
 	struct ap_device *ap_dev = to_ap_dev(dev);
 	struct ap_driver *ap_drv = to_ap_drv(dev->driver);
-	int card, queue, devres, drvres, rc;
+	int card, queue, devres, drvres, rc = -ENODEV;
+
+	if (!get_device(dev))
+		return rc;
 
 	if (is_queue_dev(dev)) {
 		/*
@@ -697,7 +700,7 @@ static int ap_device_probe(struct device *dev)
 		mutex_unlock(&ap_perms_mutex);
 		drvres = ap_drv->flags & AP_DRIVER_FLAG_DEFAULT;
 		if (!!devres != !!drvres)
-			return -ENODEV;
+			goto out;
 	}
 
 	/* Add queue/card to list of active queues/cards */
@@ -718,6 +721,9 @@ static int ap_device_probe(struct device *dev)
 		ap_dev->drv = NULL;
 	}
 
+out:
+	if (rc)
+		put_device(dev);
 	return rc;
 }
 
@@ -744,6 +750,8 @@ static int ap_device_remove(struct device *dev)
 		hash_del(&to_ap_queue(dev)->hnode);
 	spin_unlock_bh(&ap_queues_lock);
 
+	put_device(dev);
+
 	return 0;
 }
 
@@ -1371,6 +1379,8 @@ static inline void ap_scan_domains(struct ap_card *ac)
 					    __func__, ac->id, dom);
 				goto put_dev_and_continue;
 			}
+			/* get it and thus adjust reference counter */
+			get_device(dev);
 			if (decfg)
 				AP_DBF_INFO("%s(%d,%d) new (decfg) queue device created\n",
 					    __func__, ac->id, dom);
diff --git a/drivers/s390/crypto/pkey_api.c b/drivers/s390/crypto/pkey_api.c
index 99cb60ea663d..dd84995049b9 100644
--- a/drivers/s390/crypto/pkey_api.c
+++ b/drivers/s390/crypto/pkey_api.c
@@ -35,9 +35,6 @@ MODULE_DESCRIPTION("s390 protected key interface");
 #define PROTKEYBLOBBUFSIZE 256	/* protected key buffer size used internal */
 #define MAXAPQNSINLIST 64	/* max 64 apqns within a apqn list */
 
-/* mask of available pckmo subfunctions, fetched once at module init */
-static cpacf_mask_t pckmo_functions;
-
 /*
  * debug feature data and functions
  */
@@ -91,6 +88,9 @@ static int pkey_clr2protkey(u32 keytype,
 			    const struct pkey_clrkey *clrkey,
 			    struct pkey_protkey *protkey)
 {
+	/* mask of available pckmo subfunctions */
+	static cpacf_mask_t pckmo_functions;
+
 	long fc;
 	int keysize;
 	u8 paramblock[64];
@@ -114,11 +114,13 @@ static int pkey_clr2protkey(u32 keytype,
 		return -EINVAL;
 	}
 
-	/*
-	 * Check if the needed pckmo subfunction is available.
-	 * These subfunctions can be enabled/disabled by customers
-	 * in the LPAR profile or may even change on the fly.
-	 */
+	/* Did we already check for PCKMO ? */
+	if (!pckmo_functions.bytes[0]) {
+		/* no, so check now */
+		if (!cpacf_query(CPACF_PCKMO, &pckmo_functions))
+			return -ENODEV;
+	}
+	/* check for the pckmo subfunction we need now */
 	if (!cpacf_test_func(&pckmo_functions, fc)) {
 		DEBUG_ERR("%s pckmo functions not available\n", __func__);
 		return -ENODEV;
@@ -2058,7 +2060,7 @@ static struct miscdevice pkey_dev = {
  */
 static int __init pkey_init(void)
 {
-	cpacf_mask_t kmc_functions;
+	cpacf_mask_t func_mask;
 
 	/*
 	 * The pckmo instruction should be available - even if we don't
@@ -2066,15 +2068,15 @@ static int __init pkey_init(void)
 	 * is also the minimum level for the kmc instructions which
 	 * are able to work with protected keys.
 	 */
-	if (!cpacf_query(CPACF_PCKMO, &pckmo_functions))
+	if (!cpacf_query(CPACF_PCKMO, &func_mask))
 		return -ENODEV;
 
 	/* check for kmc instructions available */
-	if (!cpacf_query(CPACF_KMC, &kmc_functions))
+	if (!cpacf_query(CPACF_KMC, &func_mask))
 		return -ENODEV;
-	if (!cpacf_test_func(&kmc_functions, CPACF_KMC_PAES_128) ||
-	    !cpacf_test_func(&kmc_functions, CPACF_KMC_PAES_192) ||
-	    !cpacf_test_func(&kmc_functions, CPACF_KMC_PAES_256))
+	if (!cpacf_test_func(&func_mask, CPACF_KMC_PAES_128) ||
+	    !cpacf_test_func(&func_mask, CPACF_KMC_PAES_192) ||
+	    !cpacf_test_func(&func_mask, CPACF_KMC_PAES_256))
 		return -ENODEV;
 
 	pkey_debug_init();
diff --git a/drivers/s390/crypto/zcrypt_card.c b/drivers/s390/crypto/zcrypt_card.c
index e342eb86acd1..33b23884b133 100644
--- a/drivers/s390/crypto/zcrypt_card.c
+++ b/drivers/s390/crypto/zcrypt_card.c
@@ -157,11 +157,6 @@ int zcrypt_card_register(struct zcrypt_card *zc)
 {
 	int rc;
 
-	rc = sysfs_create_group(&zc->card->ap_dev.device.kobj,
-				&zcrypt_card_attr_group);
-	if (rc)
-		return rc;
-
 	spin_lock(&zcrypt_list_lock);
 	list_add_tail(&zc->list, &zcrypt_card_list);
 	spin_unlock(&zcrypt_list_lock);
@@ -170,6 +165,14 @@ int zcrypt_card_register(struct zcrypt_card *zc)
 
 	ZCRYPT_DBF(DBF_INFO, "card=%02x register online=1\n", zc->card->id);
 
+	rc = sysfs_create_group(&zc->card->ap_dev.device.kobj,
+				&zcrypt_card_attr_group);
+	if (rc) {
+		spin_lock(&zcrypt_list_lock);
+		list_del_init(&zc->list);
+		spin_unlock(&zcrypt_list_lock);
+	}
+
 	return rc;
 }
 EXPORT_SYMBOL(zcrypt_card_register);
diff --git a/drivers/s390/crypto/zcrypt_queue.c b/drivers/s390/crypto/zcrypt_queue.c
index 3c207066313c..5062eae73d4a 100644
--- a/drivers/s390/crypto/zcrypt_queue.c
+++ b/drivers/s390/crypto/zcrypt_queue.c
@@ -180,7 +180,6 @@ int zcrypt_queue_register(struct zcrypt_queue *zq)
 				&zcrypt_queue_attr_group);
 	if (rc)
 		goto out;
-	get_device(&zq->queue->ap_dev.device);
 
 	if (zq->ops->rng) {
 		rc = zcrypt_rng_device_add();
@@ -192,7 +191,6 @@ int zcrypt_queue_register(struct zcrypt_queue *zq)
 out_unregister:
 	sysfs_remove_group(&zq->queue->ap_dev.device.kobj,
 			   &zcrypt_queue_attr_group);
-	put_device(&zq->queue->ap_dev.device);
 out:
 	spin_lock(&zcrypt_list_lock);
 	list_del_init(&zq->list);
@@ -220,12 +218,10 @@ void zcrypt_queue_unregister(struct zcrypt_queue *zq)
 	list_del_init(&zq->list);
 	zcrypt_device_count--;
 	spin_unlock(&zcrypt_list_lock);
-	zcrypt_card_put(zc);
 	if (zq->ops->rng)
 		zcrypt_rng_device_remove();
 	sysfs_remove_group(&zq->queue->ap_dev.device.kobj,
 			   &zcrypt_queue_attr_group);
-	put_device(&zq->queue->ap_dev.device);
-	zcrypt_queue_put(zq);
+	zcrypt_card_put(zc);
 }
 EXPORT_SYMBOL(zcrypt_queue_unregister);
diff --git a/drivers/scsi/device_handler/scsi_dh_alua.c b/drivers/scsi/device_handler/scsi_dh_alua.c
index f32da0ca529e..308bda2e9c00 100644
--- a/drivers/scsi/device_handler/scsi_dh_alua.c
+++ b/drivers/scsi/device_handler/scsi_dh_alua.c
@@ -658,8 +658,8 @@ static int alua_rtpg(struct scsi_device *sdev, struct alua_port_group *pg)
 					rcu_read_lock();
 					list_for_each_entry_rcu(h,
 						&tmp_pg->dh_list, node) {
-						/* h->sdev should always be valid */
-						BUG_ON(!h->sdev);
+						if (!h->sdev)
+							continue;
 						h->sdev->access_state = desc[0];
 					}
 					rcu_read_unlock();
@@ -705,7 +705,8 @@ static int alua_rtpg(struct scsi_device *sdev, struct alua_port_group *pg)
 			pg->expiry = 0;
 			rcu_read_lock();
 			list_for_each_entry_rcu(h, &pg->dh_list, node) {
-				BUG_ON(!h->sdev);
+				if (!h->sdev)
+					continue;
 				h->sdev->access_state =
 					(pg->state & SCSI_ACCESS_STATE_MASK);
 				if (pg->pref)
@@ -1147,7 +1148,6 @@ static void alua_bus_detach(struct scsi_device *sdev)
 	spin_lock(&h->pg_lock);
 	pg = rcu_dereference_protected(h->pg, lockdep_is_held(&h->pg_lock));
 	rcu_assign_pointer(h->pg, NULL);
-	h->sdev = NULL;
 	spin_unlock(&h->pg_lock);
 	if (pg) {
 		spin_lock_irq(&pg->lock);
@@ -1156,6 +1156,7 @@ static void alua_bus_detach(struct scsi_device *sdev)
 		kref_put(&pg->kref, release_port_group);
 	}
 	sdev->handler_data = NULL;
+	synchronize_rcu();
 	kfree(h);
 }
 
diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c
index 83ce4f11a589..8df70c92911d 100644
--- a/drivers/scsi/hpsa.c
+++ b/drivers/scsi/hpsa.c
@@ -8855,7 +8855,7 @@ reinit_after_soft_reset:
 	/* hook into SCSI subsystem */
 	rc = hpsa_scsi_add_host(h);
 	if (rc)
-		goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
+		goto clean8; /* lastlogicals, perf, sg, cmd, irq, shost, pci, lu, aer/h */
 
 	/* Monitor the controller for firmware lockups */
 	h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
@@ -8870,6 +8870,8 @@ reinit_after_soft_reset:
 				HPSA_EVENT_MONITOR_INTERVAL);
 	return 0;
 
+clean8: /* lastlogicals, perf, sg, cmd, irq, shost, pci, lu, aer/h */
+	kfree(h->lastlogicals);
 clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
 	hpsa_free_performant_mode(h);
 	h->access.set_intr_mask(h, HPSA_INTR_OFF);
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
index 93230cd1982f..e4cc92bc4d94 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -1740,6 +1740,13 @@ _base_irqpoll(struct irq_poll *irqpoll, int budget)
 		reply_q->irq_poll_scheduled = false;
 		reply_q->irq_line_enable = true;
 		enable_irq(reply_q->os_irq);
+		/*
+		 * Go for one more round of processing the
+		 * reply descriptor post queue incase if HBA
+		 * Firmware has posted some reply descriptors
+		 * while reenabling the IRQ.
+		 */
+		_base_process_reply_queue(reply_q);
 	}
 
 	return num_entries;
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index b87116e9b413..7104cf17b848 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -1193,7 +1193,6 @@ static int bcm2835_spi_setup(struct spi_device *spi)
 	struct spi_controller *ctlr = spi->controller;
 	struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
 	struct gpio_chip *chip;
-	enum gpio_lookup_flags lflags;
 	u32 cs;
 
 	/*
@@ -1259,21 +1258,9 @@ static int bcm2835_spi_setup(struct spi_device *spi)
 	if (!chip)
 		return 0;
 
-	/*
-	 * Retrieve the corresponding GPIO line used for CS.
-	 * The inversion semantics will be handled by the GPIO core
-	 * code, so we pass GPIOD_OUT_LOW for "unasserted" and
-	 * the correct flag for inversion semantics. The SPI_CS_HIGH
-	 * on spi->mode cannot be checked for polarity in this case
-	 * as the flag use_gpio_descriptors enforces SPI_CS_HIGH.
-	 */
-	if (of_property_read_bool(spi->dev.of_node, "spi-cs-high"))
-		lflags = GPIO_ACTIVE_HIGH;
-	else
-		lflags = GPIO_ACTIVE_LOW;
 	spi->cs_gpiod = gpiochip_request_own_desc(chip, 8 - spi->chip_select,
 						  DRV_NAME,
-						  lflags,
+						  GPIO_LOOKUP_FLAGS_DEFAULT,
 						  GPIOD_OUT_LOW);
 	if (IS_ERR(spi->cs_gpiod))
 		return PTR_ERR(spi->cs_gpiod);
diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 3967afa465f0..1a08c1d584ab 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -1080,12 +1080,11 @@ MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
 #ifdef CONFIG_PM_SLEEP
 static int dspi_suspend(struct device *dev)
 {
-	struct spi_controller *ctlr = dev_get_drvdata(dev);
-	struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
+	struct fsl_dspi *dspi = dev_get_drvdata(dev);
 
 	if (dspi->irq)
 		disable_irq(dspi->irq);
-	spi_controller_suspend(ctlr);
+	spi_controller_suspend(dspi->ctlr);
 	clk_disable_unprepare(dspi->clk);
 
 	pinctrl_pm_select_sleep_state(dev);
@@ -1095,8 +1094,7 @@ static int dspi_suspend(struct device *dev)
 
 static int dspi_resume(struct device *dev)
 {
-	struct spi_controller *ctlr = dev_get_drvdata(dev);
-	struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
+	struct fsl_dspi *dspi = dev_get_drvdata(dev);
 	int ret;
 
 	pinctrl_pm_select_default_state(dev);
@@ -1104,7 +1102,7 @@ static int dspi_resume(struct device *dev)
 	ret = clk_prepare_enable(dspi->clk);
 	if (ret)
 		return ret;
-	spi_controller_resume(ctlr);
+	spi_controller_resume(dspi->ctlr);
 	if (dspi->irq)
 		enable_irq(dspi->irq);
 
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 060b1f5c9b04..4b80e27ecdbf 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -1676,15 +1676,18 @@ static int spi_imx_probe(struct platform_device *pdev)
 		goto out_master_put;
 	}
 
-	pm_runtime_enable(spi_imx->dev);
+	ret = clk_prepare_enable(spi_imx->clk_per);
+	if (ret)
+		goto out_master_put;
+
+	ret = clk_prepare_enable(spi_imx->clk_ipg);
+	if (ret)
+		goto out_put_per;
+
 	pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
 	pm_runtime_use_autosuspend(spi_imx->dev);
-
-	ret = pm_runtime_get_sync(spi_imx->dev);
-	if (ret < 0) {
-		dev_err(spi_imx->dev, "failed to enable clock\n");
-		goto out_runtime_pm_put;
-	}
+	pm_runtime_set_active(spi_imx->dev);
+	pm_runtime_enable(spi_imx->dev);
 
 	spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
 	/*
@@ -1722,8 +1725,12 @@ out_bitbang_start:
 		spi_imx_sdma_exit(spi_imx);
 out_runtime_pm_put:
 	pm_runtime_dont_use_autosuspend(spi_imx->dev);
-	pm_runtime_put_sync(spi_imx->dev);
+	pm_runtime_set_suspended(&pdev->dev);
 	pm_runtime_disable(spi_imx->dev);
+
+	clk_disable_unprepare(spi_imx->clk_ipg);
+out_put_per:
+	clk_disable_unprepare(spi_imx->clk_per);
 out_master_put:
 	spi_master_put(master);
 
diff --git a/drivers/staging/wfx/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml b/drivers/staging/wfx/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml
index 43b5630c0407..510edd12ed19 100644
--- a/drivers/staging/wfx/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml
+++ b/drivers/staging/wfx/Documentation/devicetree/bindings/net/wireless/silabs,wfx.yaml
@@ -24,7 +24,7 @@ description:
     In addition, it is recommended to declare a mmc-pwrseq on SDIO host above
     WFx. Without it, you may encounter issues with warm boot. The mmc-pwrseq
     should be compatible with mmc-pwrseq-simple. Please consult
-    Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt for more
+    Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml for more
     information.
 
   For SPI':'
diff --git a/drivers/tty/serial/8250/8250_mtk.c b/drivers/tty/serial/8250/8250_mtk.c
index 41f4120abdf2..fa876e2c13e5 100644
--- a/drivers/tty/serial/8250/8250_mtk.c
+++ b/drivers/tty/serial/8250/8250_mtk.c
@@ -317,7 +317,7 @@ mtk8250_set_termios(struct uart_port *port, struct ktermios *termios,
 	 */
 	baud = tty_termios_baud_rate(termios);
 
-	serial8250_do_set_termios(port, termios, old);
+	serial8250_do_set_termios(port, termios, NULL);
 
 	tty_termios_encode_baud_rate(termios, baud, baud);
 
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 1044fc387691..28f22e58639c 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -522,6 +522,7 @@ config SERIAL_IMX_EARLYCON
 	depends on OF
 	select SERIAL_EARLYCON
 	select SERIAL_CORE_CONSOLE
+	default y if SERIAL_IMX_CONSOLE
 	help
 	  If you have enabled the earlycon on the Freescale IMX
 	  CPU you can make it the earlycon by answering Y to this option.
diff --git a/drivers/tty/serial/serial_txx9.c b/drivers/tty/serial/serial_txx9.c
index b4d89e31730e..7a07e7272de1 100644
--- a/drivers/tty/serial/serial_txx9.c
+++ b/drivers/tty/serial/serial_txx9.c
@@ -1280,6 +1280,9 @@ static int __init serial_txx9_init(void)
 
 #ifdef ENABLE_SERIAL_TXX9_PCI
 	ret = pci_register_driver(&serial_txx9_pci_driver);
+	if (ret) {
+		platform_driver_unregister(&serial_txx9_plat_driver);
+	}
 #endif
 	if (ret == 0)
 		goto out;
diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c
index 7a4c02548fb3..9f8b9a567b35 100644
--- a/drivers/tty/tty_io.c
+++ b/drivers/tty/tty_io.c
@@ -1515,10 +1515,12 @@ static void release_tty(struct tty_struct *tty, int idx)
 		tty->ops->shutdown(tty);
 	tty_save_termios(tty);
 	tty_driver_remove_tty(tty->driver, tty);
-	tty->port->itty = NULL;
+	if (tty->port)
+		tty->port->itty = NULL;
 	if (tty->link)
 		tty->link->port->itty = NULL;
-	tty_buffer_cancel_work(tty->port);
+	if (tty->port)
+		tty_buffer_cancel_work(tty->port);
 	if (tty->link)
 		tty_buffer_cancel_work(tty->link->port);
 
diff --git a/drivers/tty/vt/vt.c b/drivers/tty/vt/vt.c
index 9506a76f3ab6..d04a162939a4 100644
--- a/drivers/tty/vt/vt.c
+++ b/drivers/tty/vt/vt.c
@@ -4704,27 +4704,6 @@ static int con_font_default(struct vc_data *vc, struct console_font_op *op)
 	return rc;
 }
 
-static int con_font_copy(struct vc_data *vc, struct console_font_op *op)
-{
-	int con = op->height;
-	int rc;
-
-
-	console_lock();
-	if (vc->vc_mode != KD_TEXT)
-		rc = -EINVAL;
-	else if (!vc->vc_sw->con_font_copy)
-		rc = -ENOSYS;
-	else if (con < 0 || !vc_cons_allocated(con))
-		rc = -ENOTTY;
-	else if (con == vc->vc_num)	/* nothing to do */
-		rc = 0;
-	else
-		rc = vc->vc_sw->con_font_copy(vc, con);
-	console_unlock();
-	return rc;
-}
-
 int con_font_op(struct vc_data *vc, struct console_font_op *op)
 {
 	switch (op->op) {
@@ -4735,7 +4714,8 @@ int con_font_op(struct vc_data *vc, struct console_font_op *op)
 	case KD_FONT_OP_SET_DEFAULT:
 		return con_font_default(vc, op);
 	case KD_FONT_OP_COPY:
-		return con_font_copy(vc, op);
+		/* was buggy and never really used */
+		return -EINVAL;
 	}
 	return -ENOSYS;
 }
diff --git a/drivers/tty/vt/vt_ioctl.c b/drivers/tty/vt/vt_ioctl.c
index 2321775ef098..5f61b25a9aaa 100644
--- a/drivers/tty/vt/vt_ioctl.c
+++ b/drivers/tty/vt/vt_ioctl.c
@@ -484,7 +484,7 @@ static int vt_k_ioctl(struct tty_struct *tty, unsigned int cmd,
 	return 0;
 }
 
-static inline int do_fontx_ioctl(int cmd,
+static inline int do_fontx_ioctl(struct vc_data *vc, int cmd,
 		struct consolefontdesc __user *user_cfd,
 		struct console_font_op *op)
 {
@@ -502,15 +502,16 @@ static inline int do_fontx_ioctl(int cmd,
 		op->height = cfdarg.charheight;
 		op->charcount = cfdarg.charcount;
 		op->data = cfdarg.chardata;
-		return con_font_op(vc_cons[fg_console].d, op);
-	case GIO_FONTX: {
+		return con_font_op(vc, op);
+
+	case GIO_FONTX:
 		op->op = KD_FONT_OP_GET;
 		op->flags = KD_FONT_FLAG_OLD;
 		op->width = 8;
 		op->height = cfdarg.charheight;
 		op->charcount = cfdarg.charcount;
 		op->data = cfdarg.chardata;
-		i = con_font_op(vc_cons[fg_console].d, op);
+		i = con_font_op(vc, op);
 		if (i)
 			return i;
 		cfdarg.charheight = op->height;
@@ -518,12 +519,11 @@ static inline int do_fontx_ioctl(int cmd,
 		if (copy_to_user(user_cfd, &cfdarg, sizeof(struct consolefontdesc)))
 			return -EFAULT;
 		return 0;
-		}
 	}
 	return -EINVAL;
 }
 
-static int vt_io_fontreset(struct console_font_op *op)
+static int vt_io_fontreset(struct vc_data *vc, struct console_font_op *op)
 {
 	int ret;
 
@@ -537,12 +537,12 @@ static int vt_io_fontreset(struct console_font_op *op)
 
 	op->op = KD_FONT_OP_SET_DEFAULT;
 	op->data = NULL;
-	ret = con_font_op(vc_cons[fg_console].d, op);
+	ret = con_font_op(vc, op);
 	if (ret)
 		return ret;
 
 	console_lock();
-	con_set_default_unimap(vc_cons[fg_console].d);
+	con_set_default_unimap(vc);
 	console_unlock();
 
 	return 0;
@@ -584,7 +584,7 @@ static int vt_io_ioctl(struct vc_data *vc, unsigned int cmd, void __user *up,
 		op.height = 0;
 		op.charcount = 256;
 		op.data = up;
-		return con_font_op(vc_cons[fg_console].d, &op);
+		return con_font_op(vc, &op);
 
 	case GIO_FONT:
 		op.op = KD_FONT_OP_GET;
@@ -593,7 +593,7 @@ static int vt_io_ioctl(struct vc_data *vc, unsigned int cmd, void __user *up,
 		op.height = 32;
 		op.charcount = 256;
 		op.data = up;
-		return con_font_op(vc_cons[fg_console].d, &op);
+		return con_font_op(vc, &op);
 
 	case PIO_CMAP:
                 if (!perm)
@@ -609,13 +609,13 @@ static int vt_io_ioctl(struct vc_data *vc, unsigned int cmd, void __user *up,
 
 		fallthrough;
 	case GIO_FONTX:
-		return do_fontx_ioctl(cmd, up, &op);
+		return do_fontx_ioctl(vc, cmd, up, &op);
 
 	case PIO_FONTRESET:
 		if (!perm)
 			return -EPERM;
 
-		return vt_io_fontreset(&op);
+		return vt_io_fontreset(vc, &op);
 
 	case PIO_SCRNMAP:
 		if (!perm)
@@ -1066,8 +1066,9 @@ struct compat_consolefontdesc {
 };
 
 static inline int
-compat_fontx_ioctl(int cmd, struct compat_consolefontdesc __user *user_cfd,
-			 int perm, struct console_font_op *op)
+compat_fontx_ioctl(struct vc_data *vc, int cmd,
+		   struct compat_consolefontdesc __user *user_cfd,
+		   int perm, struct console_font_op *op)
 {
 	struct compat_consolefontdesc cfdarg;
 	int i;
@@ -1085,7 +1086,8 @@ compat_fontx_ioctl(int cmd, struct compat_consolefontdesc __user *user_cfd,
 		op->height = cfdarg.charheight;
 		op->charcount = cfdarg.charcount;
 		op->data = compat_ptr(cfdarg.chardata);
-		return con_font_op(vc_cons[fg_console].d, op);
+		return con_font_op(vc, op);
+
 	case GIO_FONTX:
 		op->op = KD_FONT_OP_GET;
 		op->flags = KD_FONT_FLAG_OLD;
@@ -1093,7 +1095,7 @@ compat_fontx_ioctl(int cmd, struct compat_consolefontdesc __user *user_cfd,
 		op->height = cfdarg.charheight;
 		op->charcount = cfdarg.charcount;
 		op->data = compat_ptr(cfdarg.chardata);
-		i = con_font_op(vc_cons[fg_console].d, op);
+		i = con_font_op(vc, op);
 		if (i)
 			return i;
 		cfdarg.charheight = op->height;
@@ -1183,7 +1185,7 @@ long vt_compat_ioctl(struct tty_struct *tty,
 	 */
 	case PIO_FONTX:
 	case GIO_FONTX:
-		return compat_fontx_ioctl(cmd, up, perm, &op);
+		return compat_fontx_ioctl(vc, cmd, up, perm, &op);
 
 	case KDFONTOP:
 		return compat_kdfontop_ioctl(up, perm, &op, vc);
diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c
index 10574fa3f927..a1e3a037a289 100644
--- a/drivers/usb/core/quirks.c
+++ b/drivers/usb/core/quirks.c
@@ -378,6 +378,9 @@ static const struct usb_device_id usb_quirk_list[] = {
 	{ USB_DEVICE(0x0926, 0x3333), .driver_info =
 			USB_QUIRK_CONFIG_INTF_STRINGS },
 
+	/* Kingston DataTraveler 3.0 */
+	{ USB_DEVICE(0x0951, 0x1666), .driver_info = USB_QUIRK_NO_LPM },
+
 	/* X-Rite/Gretag-Macbeth Eye-One Pro display colorimeter */
 	{ USB_DEVICE(0x0971, 0x2000), .driver_info = USB_QUIRK_NO_SET_INTF },
 
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index e2820676beb1..5f18acac7406 100644
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -608,10 +608,13 @@ static int dwc2_driver_probe(struct platform_device *dev)
 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
 	return 0;
 
+#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
+	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
 error_debugfs:
 	dwc2_debugfs_exit(hsotg);
 	if (hsotg->hcd_enabled)
 		dwc2_hcd_remove(hsotg);
+#endif
 error_drd:
 	dwc2_drd_exit(hsotg);
 
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 242b6210380a..bae6a70664c8 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -40,6 +40,7 @@
 #define PCI_DEVICE_ID_INTEL_TGPLP		0xa0ee
 #define PCI_DEVICE_ID_INTEL_TGPH		0x43ee
 #define PCI_DEVICE_ID_INTEL_JSP			0x4dee
+#define PCI_DEVICE_ID_INTEL_ADLS		0x7ae1
 
 #define PCI_INTEL_BXT_DSM_GUID		"732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
 #define PCI_INTEL_BXT_FUNC_PMU_PWR	4
@@ -367,6 +368,9 @@ static const struct pci_device_id dwc3_pci_id_table[] = {
 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
 	  (kernel_ulong_t) &dwc3_pci_intel_properties, },
 
+	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
+	  (kernel_ulong_t) &dwc3_pci_intel_properties, },
+
 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
 	  (kernel_ulong_t) &dwc3_pci_amd_properties, },
 	{  }	/* Terminating Entry */
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 7be3903cb842..8b668ef46f7f 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -1058,10 +1058,11 @@ void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
 {
 	unsigned int direction = !dwc->ep0_expect_in;
 
+	dwc->delayed_status = false;
+
 	if (dwc->ep0state != EP0_STATUS_PHASE)
 		return;
 
-	dwc->delayed_status = false;
 	__dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 }
 
diff --git a/drivers/usb/gadget/legacy/raw_gadget.c b/drivers/usb/gadget/legacy/raw_gadget.c
index e01e366d89cd..062dfac30399 100644
--- a/drivers/usb/gadget/legacy/raw_gadget.c
+++ b/drivers/usb/gadget/legacy/raw_gadget.c
@@ -564,9 +564,12 @@ static int raw_ioctl_event_fetch(struct raw_dev *dev, unsigned long value)
 		return -ENODEV;
 	}
 	length = min(arg.length, event->length);
-	if (copy_to_user((void __user *)value, event, sizeof(*event) + length))
+	if (copy_to_user((void __user *)value, event, sizeof(*event) + length)) {
+		kfree(event);
 		return -EFAULT;
+	}
 
+	kfree(event);
 	return 0;
 }
 
diff --git a/drivers/usb/gadget/udc/fsl_udc_core.c b/drivers/usb/gadget/udc/fsl_udc_core.c
index de528e3b0662..ad6ff9c4188e 100644
--- a/drivers/usb/gadget/udc/fsl_udc_core.c
+++ b/drivers/usb/gadget/udc/fsl_udc_core.c
@@ -1051,7 +1051,7 @@ static int fsl_ep_fifo_status(struct usb_ep *_ep)
 	u32 bitmask;
 	struct ep_queue_head *qh;
 
-	if (!_ep || _ep->desc || !(_ep->desc->bEndpointAddress&0xF))
+	if (!_ep || !_ep->desc || !(_ep->desc->bEndpointAddress&0xF))
 		return -ENODEV;
 
 	ep = container_of(_ep, struct fsl_ep, ep);
diff --git a/drivers/usb/gadget/udc/goku_udc.c b/drivers/usb/gadget/udc/goku_udc.c
index 25c1d6ab5adb..3e1267d38774 100644
--- a/drivers/usb/gadget/udc/goku_udc.c
+++ b/drivers/usb/gadget/udc/goku_udc.c
@@ -1760,6 +1760,7 @@ static int goku_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 		goto err;
 	}
 
+	pci_set_drvdata(pdev, dev);
 	spin_lock_init(&dev->lock);
 	dev->pdev = pdev;
 	dev->gadget.ops = &goku_ops;
@@ -1793,7 +1794,6 @@ static int goku_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	}
 	dev->regs = (struct goku_udc_regs __iomem *) base;
 
-	pci_set_drvdata(pdev, dev);
 	INFO(dev, "%s\n", driver_desc);
 	INFO(dev, "version: " DRIVER_VERSION " %s\n", dmastr());
 	INFO(dev, "irq %d, pci mem %p\n", pdev->irq, base);
diff --git a/drivers/usb/misc/apple-mfi-fastcharge.c b/drivers/usb/misc/apple-mfi-fastcharge.c
index 579d8c84de42..9de0171b5177 100644
--- a/drivers/usb/misc/apple-mfi-fastcharge.c
+++ b/drivers/usb/misc/apple-mfi-fastcharge.c
@@ -120,8 +120,10 @@ static int apple_mfi_fc_set_property(struct power_supply *psy,
 	dev_dbg(&mfi->udev->dev, "prop: %d\n", psp);
 
 	ret = pm_runtime_get_sync(&mfi->udev->dev);
-	if (ret < 0)
+	if (ret < 0) {
+		pm_runtime_put_noidle(&mfi->udev->dev);
 		return ret;
+	}
 
 	switch (psp) {
 	case POWER_SUPPLY_PROP_CHARGE_TYPE:
diff --git a/drivers/usb/mtu3/mtu3_gadget.c b/drivers/usb/mtu3/mtu3_gadget.c
index 1de5c9a1d20a..38f17d66d5bc 100644
--- a/drivers/usb/mtu3/mtu3_gadget.c
+++ b/drivers/usb/mtu3/mtu3_gadget.c
@@ -564,6 +564,7 @@ static int mtu3_gadget_stop(struct usb_gadget *g)
 
 	spin_unlock_irqrestore(&mtu->lock, flags);
 
+	synchronize_irq(mtu->irq);
 	return 0;
 }
 
diff --git a/drivers/usb/serial/cyberjack.c b/drivers/usb/serial/cyberjack.c
index 821970609695..2e40908963da 100644
--- a/drivers/usb/serial/cyberjack.c
+++ b/drivers/usb/serial/cyberjack.c
@@ -357,11 +357,12 @@ static void cyberjack_write_bulk_callback(struct urb *urb)
 	struct device *dev = &port->dev;
 	int status = urb->status;
 	unsigned long flags;
+	bool resubmitted = false;
 
-	set_bit(0, &port->write_urbs_free);
 	if (status) {
 		dev_dbg(dev, "%s - nonzero write bulk status received: %d\n",
 			__func__, status);
+		set_bit(0, &port->write_urbs_free);
 		return;
 	}
 
@@ -394,6 +395,8 @@ static void cyberjack_write_bulk_callback(struct urb *urb)
 			goto exit;
 		}
 
+		resubmitted = true;
+
 		dev_dbg(dev, "%s - priv->wrsent=%d\n", __func__, priv->wrsent);
 		dev_dbg(dev, "%s - priv->wrfilled=%d\n", __func__, priv->wrfilled);
 
@@ -410,6 +413,8 @@ static void cyberjack_write_bulk_callback(struct urb *urb)
 
 exit:
 	spin_unlock_irqrestore(&priv->lock, flags);
+	if (!resubmitted)
+		set_bit(0, &port->write_urbs_free);
 	usb_serial_port_softint(port);
 }
 
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index 2a3bfd6f867e..54ca85cc920d 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -250,6 +250,7 @@ static void option_instat_callback(struct urb *urb);
 #define QUECTEL_PRODUCT_EP06			0x0306
 #define QUECTEL_PRODUCT_EM12			0x0512
 #define QUECTEL_PRODUCT_RM500Q			0x0800
+#define QUECTEL_PRODUCT_EC200T			0x6026
 
 #define CMOTECH_VENDOR_ID			0x16d8
 #define CMOTECH_PRODUCT_6001			0x6001
@@ -1117,6 +1118,7 @@ static const struct usb_device_id option_ids[] = {
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500Q, 0xff, 0, 0) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500Q, 0xff, 0xff, 0x10),
 	  .driver_info = ZLP },
+	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200T, 0xff, 0, 0) },
 
 	{ USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6001) },
 	{ USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_CMU_300) },
@@ -1189,6 +1191,8 @@ static const struct usb_device_id option_ids[] = {
 	  .driver_info = NCTRL(0) | RSVD(1) },
 	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1054, 0xff),	/* Telit FT980-KS */
 	  .driver_info = NCTRL(2) | RSVD(3) },
+	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1055, 0xff),	/* Telit FN980 (PCIe) */
+	  .driver_info = NCTRL(0) | RSVD(1) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910),
 	  .driver_info = NCTRL(0) | RSVD(1) | RSVD(3) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910_DUAL_MODEM),
@@ -1201,6 +1205,8 @@ static const struct usb_device_id option_ids[] = {
 	  .driver_info = NCTRL(0) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE910),
 	  .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) },
+	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1203, 0xff),	/* Telit LE910Cx (RNDIS) */
+	  .driver_info = NCTRL(2) | RSVD(3) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE910_USBCFG4),
 	  .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) | RSVD(3) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE920),
@@ -1215,6 +1221,10 @@ static const struct usb_device_id option_ids[] = {
 	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, TELIT_PRODUCT_LE920A4_1213, 0xff) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE920A4_1214),
 	  .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) | RSVD(3) },
+	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1230, 0xff),	/* Telit LE910Cx (rmnet) */
+	  .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) },
+	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1231, 0xff),	/* Telit LE910Cx (RNDIS) */
+	  .driver_info = NCTRL(2) | RSVD(3) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, 0x1260),
 	  .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, 0x1261),
diff --git a/drivers/vfio/fsl-mc/vfio_fsl_mc.c b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
index 0113a980f974..f27e25112c40 100644
--- a/drivers/vfio/fsl-mc/vfio_fsl_mc.c
+++ b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
@@ -248,7 +248,9 @@ static long vfio_fsl_mc_ioctl(void *device_data, unsigned int cmd,
 		info.size = vdev->regions[info.index].size;
 		info.flags = vdev->regions[info.index].flags;
 
-		return copy_to_user((void __user *)arg, &info, minsz);
+		if (copy_to_user((void __user *)arg, &info, minsz))
+			return -EFAULT;
+		return 0;
 	}
 	case VFIO_DEVICE_GET_IRQ_INFO:
 	{
@@ -267,7 +269,9 @@ static long vfio_fsl_mc_ioctl(void *device_data, unsigned int cmd,
 		info.flags = VFIO_IRQ_INFO_EVENTFD;
 		info.count = 1;
 
-		return copy_to_user((void __user *)arg, &info, minsz);
+		if (copy_to_user((void __user *)arg, &info, minsz))
+			return -EFAULT;
+		return 0;
 	}
 	case VFIO_DEVICE_SET_IRQS:
 	{
@@ -468,7 +472,7 @@ static int vfio_fsl_mc_mmap(void *device_data, struct vm_area_struct *vma)
 {
 	struct vfio_fsl_mc_device *vdev = device_data;
 	struct fsl_mc_device *mc_dev = vdev->mc_dev;
-	int index;
+	unsigned int index;
 
 	index = vma->vm_pgoff >> (VFIO_FSL_MC_OFFSET_SHIFT - PAGE_SHIFT);
 
diff --git a/drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c b/drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c
index c80dceb46f79..0d9f3002df7f 100644
--- a/drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c
+++ b/drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c
@@ -13,7 +13,7 @@
 #include "linux/fsl/mc.h"
 #include "vfio_fsl_mc_private.h"
 
-int vfio_fsl_mc_irqs_allocate(struct vfio_fsl_mc_device *vdev)
+static int vfio_fsl_mc_irqs_allocate(struct vfio_fsl_mc_device *vdev)
 {
 	struct fsl_mc_device *mc_dev = vdev->mc_dev;
 	struct vfio_fsl_mc_irq *mc_irq;
diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c
index fbd2b3404184..e6190173482c 100644
--- a/drivers/vfio/pci/vfio_pci.c
+++ b/drivers/vfio/pci/vfio_pci.c
@@ -385,7 +385,7 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev)
 	    pdev->vendor == PCI_VENDOR_ID_INTEL &&
 	    IS_ENABLED(CONFIG_VFIO_PCI_IGD)) {
 		ret = vfio_pci_igd_init(vdev);
-		if (ret) {
+		if (ret && ret != -ENODEV) {
 			pci_warn(pdev, "Failed to setup Intel IGD regions\n");
 			goto disable_exit;
 		}
diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c
index 9e353c484ace..a0b5fc8e46f4 100644
--- a/drivers/vfio/pci/vfio_pci_rdwr.c
+++ b/drivers/vfio/pci/vfio_pci_rdwr.c
@@ -356,34 +356,60 @@ ssize_t vfio_pci_vga_rw(struct vfio_pci_device *vdev, char __user *buf,
 	return done;
 }
 
-static int vfio_pci_ioeventfd_handler(void *opaque, void *unused)
+static void vfio_pci_ioeventfd_do_write(struct vfio_pci_ioeventfd *ioeventfd,
+					bool test_mem)
 {
-	struct vfio_pci_ioeventfd *ioeventfd = opaque;
-
 	switch (ioeventfd->count) {
 	case 1:
-		vfio_pci_iowrite8(ioeventfd->vdev, ioeventfd->test_mem,
+		vfio_pci_iowrite8(ioeventfd->vdev, test_mem,
 				  ioeventfd->data, ioeventfd->addr);
 		break;
 	case 2:
-		vfio_pci_iowrite16(ioeventfd->vdev, ioeventfd->test_mem,
+		vfio_pci_iowrite16(ioeventfd->vdev, test_mem,
 				   ioeventfd->data, ioeventfd->addr);
 		break;
 	case 4:
-		vfio_pci_iowrite32(ioeventfd->vdev, ioeventfd->test_mem,
+		vfio_pci_iowrite32(ioeventfd->vdev, test_mem,
 				   ioeventfd->data, ioeventfd->addr);
 		break;
 #ifdef iowrite64
 	case 8:
-		vfio_pci_iowrite64(ioeventfd->vdev, ioeventfd->test_mem,
+		vfio_pci_iowrite64(ioeventfd->vdev, test_mem,
 				   ioeventfd->data, ioeventfd->addr);
 		break;
 #endif
 	}
+}
+
+static int vfio_pci_ioeventfd_handler(void *opaque, void *unused)
+{
+	struct vfio_pci_ioeventfd *ioeventfd = opaque;
+	struct vfio_pci_device *vdev = ioeventfd->vdev;
+
+	if (ioeventfd->test_mem) {
+		if (!down_read_trylock(&vdev->memory_lock))
+			return 1; /* Lock contended, use thread */
+		if (!__vfio_pci_memory_enabled(vdev)) {
+			up_read(&vdev->memory_lock);
+			return 0;
+		}
+	}
+
+	vfio_pci_ioeventfd_do_write(ioeventfd, false);
+
+	if (ioeventfd->test_mem)
+		up_read(&vdev->memory_lock);
 
 	return 0;
 }
 
+static void vfio_pci_ioeventfd_thread(void *opaque, void *unused)
+{
+	struct vfio_pci_ioeventfd *ioeventfd = opaque;
+
+	vfio_pci_ioeventfd_do_write(ioeventfd, ioeventfd->test_mem);
+}
+
 long vfio_pci_ioeventfd(struct vfio_pci_device *vdev, loff_t offset,
 			uint64_t data, int count, int fd)
 {
@@ -457,7 +483,8 @@ long vfio_pci_ioeventfd(struct vfio_pci_device *vdev, loff_t offset,
 	ioeventfd->test_mem = vdev->pdev->resource[bar].flags & IORESOURCE_MEM;
 
 	ret = vfio_virqfd_enable(ioeventfd, vfio_pci_ioeventfd_handler,
-				 NULL, NULL, &ioeventfd->virqfd, fd);
+				 vfio_pci_ioeventfd_thread, NULL,
+				 &ioeventfd->virqfd, fd);
 	if (ret) {
 		kfree(ioeventfd);
 		goto out_unlock;
diff --git a/drivers/vfio/platform/vfio_platform_common.c b/drivers/vfio/platform/vfio_platform_common.c
index c0771a9567fb..fb4b385191f2 100644
--- a/drivers/vfio/platform/vfio_platform_common.c
+++ b/drivers/vfio/platform/vfio_platform_common.c
@@ -267,7 +267,7 @@ static int vfio_platform_open(void *device_data)
 
 		ret = pm_runtime_get_sync(vdev->device);
 		if (ret < 0)
-			goto err_pm;
+			goto err_rst;
 
 		ret = vfio_platform_call_reset(vdev, &extra_dbg);
 		if (ret && vdev->reset_required) {
@@ -284,7 +284,6 @@ static int vfio_platform_open(void *device_data)
 
 err_rst:
 	pm_runtime_put(vdev->device);
-err_pm:
 	vfio_platform_irq_cleanup(vdev);
 err_irq:
 	vfio_platform_regions_cleanup(vdev);
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index bb2684cc245e..67e827638995 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -1993,6 +1993,7 @@ static void vfio_iommu_iova_insert_copy(struct vfio_iommu *iommu,
 
 	list_splice_tail(iova_copy, iova);
 }
+
 static int vfio_iommu_type1_attach_group(void *iommu_data,
 					 struct iommu_group *iommu_group)
 {
@@ -2009,18 +2010,10 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
 
 	mutex_lock(&iommu->lock);
 
-	list_for_each_entry(d, &iommu->domain_list, next) {
-		if (find_iommu_group(d, iommu_group)) {
-			mutex_unlock(&iommu->lock);
-			return -EINVAL;
-		}
-	}
-
-	if (iommu->external_domain) {
-		if (find_iommu_group(iommu->external_domain, iommu_group)) {
-			mutex_unlock(&iommu->lock);
-			return -EINVAL;
-		}
+	/* Check for duplicates */
+	if (vfio_iommu_find_iommu_group(iommu, iommu_group)) {
+		mutex_unlock(&iommu->lock);
+		return -EINVAL;
 	}
 
 	group = kzalloc(sizeof(*group), GFP_KERNEL);
diff --git a/fs/afs/xattr.c b/fs/afs/xattr.c
index 38884d6c57cd..95c573dcda11 100644
--- a/fs/afs/xattr.c
+++ b/fs/afs/xattr.c
@@ -148,11 +148,6 @@ static const struct xattr_handler afs_xattr_afs_acl_handler = {
 	.set    = afs_xattr_set_acl,
 };
 
-static void yfs_acl_put(struct afs_operation *op)
-{
-	yfs_free_opaque_acl(op->yacl);
-}
-
 static const struct afs_operation_ops yfs_fetch_opaque_acl_operation = {
 	.issue_yfs_rpc	= yfs_fs_fetch_opaque_acl,
 	.success	= afs_acl_success,
@@ -246,7 +241,7 @@ error:
 static const struct afs_operation_ops yfs_store_opaque_acl2_operation = {
 	.issue_yfs_rpc	= yfs_fs_store_opaque_acl2,
 	.success	= afs_acl_success,
-	.put		= yfs_acl_put,
+	.put		= afs_acl_put,
 };
 
 /*
diff --git a/fs/afs/yfsclient.c b/fs/afs/yfsclient.c
index 3b1239b7e90d..bd787e71a657 100644
--- a/fs/afs/yfsclient.c
+++ b/fs/afs/yfsclient.c
@@ -1990,6 +1990,7 @@ void yfs_fs_store_opaque_acl2(struct afs_operation *op)
 	memcpy(bp, acl->data, acl->size);
 	if (acl->size != size)
 		memset((void *)bp + acl->size, 0, size - acl->size);
+	bp += size / sizeof(__be32);
 	yfs_check_req(call, bp);
 
 	trace_afs_make_fs_call(call, &vp->fid);
diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c
index 5027bbdca419..ded4229c314a 100644
--- a/fs/ceph/caps.c
+++ b/fs/ceph/caps.c
@@ -4074,7 +4074,7 @@ void ceph_handle_caps(struct ceph_mds_session *session,
 	     vino.snap, inode);
 
 	mutex_lock(&session->s_mutex);
-	session->s_seq++;
+	inc_session_sequence(session);
 	dout(" mds%d seq %lld cap seq %u\n", session->s_mds, session->s_seq,
 	     (unsigned)seq);
 
diff --git a/fs/ceph/mds_client.c b/fs/ceph/mds_client.c
index 08f1c0c31dc2..8f1d7500a7ec 100644
--- a/fs/ceph/mds_client.c
+++ b/fs/ceph/mds_client.c
@@ -4231,7 +4231,7 @@ static void handle_lease(struct ceph_mds_client *mdsc,
 	     dname.len, dname.name);
 
 	mutex_lock(&session->s_mutex);
-	session->s_seq++;
+	inc_session_sequence(session);
 
 	if (!inode) {
 		dout("handle_lease no inode %llx\n", vino.ino);
@@ -4385,29 +4385,49 @@ static void maybe_recover_session(struct ceph_mds_client *mdsc)
 
 bool check_session_state(struct ceph_mds_session *s)
 {
-	if (s->s_state == CEPH_MDS_SESSION_CLOSING) {
-		dout("resending session close request for mds%d\n",
-				s->s_mds);
-		request_close_session(s);
-		return false;
-	}
-	if (s->s_ttl && time_after(jiffies, s->s_ttl)) {
-		if (s->s_state == CEPH_MDS_SESSION_OPEN) {
+	switch (s->s_state) {
+	case CEPH_MDS_SESSION_OPEN:
+		if (s->s_ttl && time_after(jiffies, s->s_ttl)) {
 			s->s_state = CEPH_MDS_SESSION_HUNG;
 			pr_info("mds%d hung\n", s->s_mds);
 		}
-	}
-	if (s->s_state == CEPH_MDS_SESSION_NEW ||
-	    s->s_state == CEPH_MDS_SESSION_RESTARTING ||
-	    s->s_state == CEPH_MDS_SESSION_CLOSED ||
-	    s->s_state == CEPH_MDS_SESSION_REJECTED)
-		/* this mds is failed or recovering, just wait */
+		break;
+	case CEPH_MDS_SESSION_CLOSING:
+		/* Should never reach this when we're unmounting */
+		WARN_ON_ONCE(true);
+		fallthrough;
+	case CEPH_MDS_SESSION_NEW:
+	case CEPH_MDS_SESSION_RESTARTING:
+	case CEPH_MDS_SESSION_CLOSED:
+	case CEPH_MDS_SESSION_REJECTED:
 		return false;
+	}
 
 	return true;
 }
 
 /*
+ * If the sequence is incremented while we're waiting on a REQUEST_CLOSE reply,
+ * then we need to retransmit that request.
+ */
+void inc_session_sequence(struct ceph_mds_session *s)
+{
+	lockdep_assert_held(&s->s_mutex);
+
+	s->s_seq++;
+
+	if (s->s_state == CEPH_MDS_SESSION_CLOSING) {
+		int ret;
+
+		dout("resending session close request for mds%d\n", s->s_mds);
+		ret = request_close_session(s);
+		if (ret < 0)
+			pr_err("unable to close session to mds%d: %d\n",
+			       s->s_mds, ret);
+	}
+}
+
+/*
  * delayed work -- periodically trim expired leases, renew caps with mds
  */
 static void schedule_delayed(struct ceph_mds_client *mdsc)
diff --git a/fs/ceph/mds_client.h b/fs/ceph/mds_client.h
index cbf8af437140..f5adbebcb38e 100644
--- a/fs/ceph/mds_client.h
+++ b/fs/ceph/mds_client.h
@@ -480,6 +480,7 @@ struct ceph_mds_client {
 extern const char *ceph_mds_op_name(int op);
 
 extern bool check_session_state(struct ceph_mds_session *s);
+void inc_session_sequence(struct ceph_mds_session *s);
 
 extern struct ceph_mds_session *
 __ceph_lookup_mds_session(struct ceph_mds_client *, int mds);
diff --git a/fs/ceph/quota.c b/fs/ceph/quota.c
index 83cb4f26b689..9b785f11e95a 100644
--- a/fs/ceph/quota.c
+++ b/fs/ceph/quota.c
@@ -53,7 +53,7 @@ void ceph_handle_quota(struct ceph_mds_client *mdsc,
 
 	/* increment msg sequence number */
 	mutex_lock(&session->s_mutex);
-	session->s_seq++;
+	inc_session_sequence(session);
 	mutex_unlock(&session->s_mutex);
 
 	/* lookup inode */
diff --git a/fs/ceph/snap.c b/fs/ceph/snap.c
index 0da39c16dab4..b611f829cb61 100644
--- a/fs/ceph/snap.c
+++ b/fs/ceph/snap.c
@@ -873,7 +873,7 @@ void ceph_handle_snap(struct ceph_mds_client *mdsc,
 	     ceph_snap_op_name(op), split, trace_len);
 
 	mutex_lock(&session->s_mutex);
-	session->s_seq++;
+	inc_session_sequence(session);
 	mutex_unlock(&session->s_mutex);
 
 	down_write(&mdsc->snap_rwsem);
diff --git a/fs/gfs2/glock.c b/fs/gfs2/glock.c
index 5441c17562c5..d98a2e5dab9f 100644
--- a/fs/gfs2/glock.c
+++ b/fs/gfs2/glock.c
@@ -1078,7 +1078,8 @@ int gfs2_glock_get(struct gfs2_sbd *sdp, u64 number,
 out_free:
 	kfree(gl->gl_lksb.sb_lvbptr);
 	kmem_cache_free(cachep, gl);
-	atomic_dec(&sdp->sd_glock_disposal);
+	if (atomic_dec_and_test(&sdp->sd_glock_disposal))
+		wake_up(&sdp->sd_glock_wait);
 
 out:
 	return ret;
diff --git a/fs/gfs2/glops.c b/fs/gfs2/glops.c
index aa3f5236befb..6c1432d78dce 100644
--- a/fs/gfs2/glops.c
+++ b/fs/gfs2/glops.c
@@ -165,6 +165,31 @@ void gfs2_ail_flush(struct gfs2_glock *gl, bool fsync)
 }
 
 /**
+ * gfs2_rgrp_metasync - sync out the metadata of a resource group
+ * @gl: the glock protecting the resource group
+ *
+ */
+
+static int gfs2_rgrp_metasync(struct gfs2_glock *gl)
+{
+	struct gfs2_sbd *sdp = gl->gl_name.ln_sbd;
+	struct address_space *metamapping = &sdp->sd_aspace;
+	struct gfs2_rgrpd *rgd = gfs2_glock2rgrp(gl);
+	const unsigned bsize = sdp->sd_sb.sb_bsize;
+	loff_t start = (rgd->rd_addr * bsize) & PAGE_MASK;
+	loff_t end = PAGE_ALIGN((rgd->rd_addr + rgd->rd_length) * bsize) - 1;
+	int error;
+
+	filemap_fdatawrite_range(metamapping, start, end);
+	error = filemap_fdatawait_range(metamapping, start, end);
+	WARN_ON_ONCE(error && !gfs2_withdrawn(sdp));
+	mapping_set_error(metamapping, error);
+	if (error)
+		gfs2_io_error(sdp);
+	return error;
+}
+
+/**
  * rgrp_go_sync - sync out the metadata for this glock
  * @gl: the glock
  *
@@ -176,11 +201,7 @@ void gfs2_ail_flush(struct gfs2_glock *gl, bool fsync)
 static int rgrp_go_sync(struct gfs2_glock *gl)
 {
 	struct gfs2_sbd *sdp = gl->gl_name.ln_sbd;
-	struct address_space *mapping = &sdp->sd_aspace;
 	struct gfs2_rgrpd *rgd = gfs2_glock2rgrp(gl);
-	const unsigned bsize = sdp->sd_sb.sb_bsize;
-	loff_t start = (rgd->rd_addr * bsize) & PAGE_MASK;
-	loff_t end = PAGE_ALIGN((rgd->rd_addr + rgd->rd_length) * bsize) - 1;
 	int error;
 
 	if (!test_and_clear_bit(GLF_DIRTY, &gl->gl_flags))
@@ -189,10 +210,7 @@ static int rgrp_go_sync(struct gfs2_glock *gl)
 
 	gfs2_log_flush(sdp, gl, GFS2_LOG_HEAD_FLUSH_NORMAL |
 		       GFS2_LFC_RGRP_GO_SYNC);
-	filemap_fdatawrite_range(mapping, start, end);
-	error = filemap_fdatawait_range(mapping, start, end);
-	WARN_ON_ONCE(error && !gfs2_withdrawn(sdp));
-	mapping_set_error(mapping, error);
+	error = gfs2_rgrp_metasync(gl);
 	if (!error)
 		error = gfs2_ail_empty_gl(gl);
 	gfs2_free_clones(rgd);
@@ -266,7 +284,24 @@ static void gfs2_clear_glop_pending(struct gfs2_inode *ip)
 }
 
 /**
- * inode_go_sync - Sync the dirty data and/or metadata for an inode glock
+ * gfs2_inode_metasync - sync out the metadata of an inode
+ * @gl: the glock protecting the inode
+ *
+ */
+int gfs2_inode_metasync(struct gfs2_glock *gl)
+{
+	struct address_space *metamapping = gfs2_glock2aspace(gl);
+	int error;
+
+	filemap_fdatawrite(metamapping);
+	error = filemap_fdatawait(metamapping);
+	if (error)
+		gfs2_io_error(gl->gl_name.ln_sbd);
+	return error;
+}
+
+/**
+ * inode_go_sync - Sync the dirty metadata of an inode
  * @gl: the glock protecting the inode
  *
  */
@@ -297,8 +332,7 @@ static int inode_go_sync(struct gfs2_glock *gl)
 		error = filemap_fdatawait(mapping);
 		mapping_set_error(mapping, error);
 	}
-	ret = filemap_fdatawait(metamapping);
-	mapping_set_error(metamapping, ret);
+	ret = gfs2_inode_metasync(gl);
 	if (!error)
 		error = ret;
 	gfs2_ail_empty_gl(gl);
diff --git a/fs/gfs2/glops.h b/fs/gfs2/glops.h
index 2dd192e85618..695898afcaf1 100644
--- a/fs/gfs2/glops.h
+++ b/fs/gfs2/glops.h
@@ -22,6 +22,7 @@ extern const struct gfs2_glock_operations gfs2_quota_glops;
 extern const struct gfs2_glock_operations gfs2_journal_glops;
 extern const struct gfs2_glock_operations *gfs2_glops_list[];
 
+extern int gfs2_inode_metasync(struct gfs2_glock *gl);
 extern void gfs2_ail_flush(struct gfs2_glock *gl, bool fsync);
 
 #endif /* __GLOPS_DOT_H__ */
diff --git a/fs/gfs2/inode.c b/fs/gfs2/inode.c
index 6774865f5b5b..077ccb1b3ccc 100644
--- a/fs/gfs2/inode.c
+++ b/fs/gfs2/inode.c
@@ -180,7 +180,8 @@ struct inode *gfs2_inode_lookup(struct super_block *sb, unsigned int type,
 		error = gfs2_glock_nq_init(io_gl, LM_ST_SHARED, GL_EXACT, &ip->i_iopen_gh);
 		if (unlikely(error))
 			goto fail;
-		gfs2_cancel_delete_work(ip->i_iopen_gh.gh_gl);
+		if (blktype != GFS2_BLKST_UNLINKED)
+			gfs2_cancel_delete_work(ip->i_iopen_gh.gh_gl);
 		glock_set_object(ip->i_iopen_gh.gh_gl, ip);
 		gfs2_glock_put(io_gl);
 		io_gl = NULL;
diff --git a/fs/gfs2/lops.c b/fs/gfs2/lops.c
index ed69298dd824..3922b26264f5 100644
--- a/fs/gfs2/lops.c
+++ b/fs/gfs2/lops.c
@@ -22,6 +22,7 @@
 #include "incore.h"
 #include "inode.h"
 #include "glock.h"
+#include "glops.h"
 #include "log.h"
 #include "lops.h"
 #include "meta_io.h"
@@ -817,41 +818,19 @@ static int buf_lo_scan_elements(struct gfs2_jdesc *jd, u32 start,
 	return error;
 }
 
-/**
- * gfs2_meta_sync - Sync all buffers associated with a glock
- * @gl: The glock
- *
- */
-
-void gfs2_meta_sync(struct gfs2_glock *gl)
-{
-	struct address_space *mapping = gfs2_glock2aspace(gl);
-	struct gfs2_sbd *sdp = gl->gl_name.ln_sbd;
-	int error;
-
-	if (mapping == NULL)
-		mapping = &sdp->sd_aspace;
-
-	filemap_fdatawrite(mapping);
-	error = filemap_fdatawait(mapping);
-
-	if (error)
-		gfs2_io_error(gl->gl_name.ln_sbd);
-}
-
 static void buf_lo_after_scan(struct gfs2_jdesc *jd, int error, int pass)
 {
 	struct gfs2_inode *ip = GFS2_I(jd->jd_inode);
 	struct gfs2_sbd *sdp = GFS2_SB(jd->jd_inode);
 
 	if (error) {
-		gfs2_meta_sync(ip->i_gl);
+		gfs2_inode_metasync(ip->i_gl);
 		return;
 	}
 	if (pass != 1)
 		return;
 
-	gfs2_meta_sync(ip->i_gl);
+	gfs2_inode_metasync(ip->i_gl);
 
 	fs_info(sdp, "jid=%u: Replayed %u of %u blocks\n",
 	        jd->jd_jid, jd->jd_replayed_blocks, jd->jd_found_blocks);
@@ -1060,14 +1039,14 @@ static void databuf_lo_after_scan(struct gfs2_jdesc *jd, int error, int pass)
 	struct gfs2_sbd *sdp = GFS2_SB(jd->jd_inode);
 
 	if (error) {
-		gfs2_meta_sync(ip->i_gl);
+		gfs2_inode_metasync(ip->i_gl);
 		return;
 	}
 	if (pass != 1)
 		return;
 
 	/* data sync? */
-	gfs2_meta_sync(ip->i_gl);
+	gfs2_inode_metasync(ip->i_gl);
 
 	fs_info(sdp, "jid=%u: Replayed %u of %u data blocks\n",
 		jd->jd_jid, jd->jd_replayed_blocks, jd->jd_found_blocks);
diff --git a/fs/gfs2/lops.h b/fs/gfs2/lops.h
index 4a3d8aecdf82..fbdbb08dcec6 100644
--- a/fs/gfs2/lops.h
+++ b/fs/gfs2/lops.h
@@ -27,8 +27,6 @@ extern void gfs2_log_submit_bio(struct bio **biop, int opf);
 extern void gfs2_pin(struct gfs2_sbd *sdp, struct buffer_head *bh);
 extern int gfs2_find_jhead(struct gfs2_jdesc *jd,
 			   struct gfs2_log_header_host *head, bool keep_cache);
-extern void gfs2_meta_sync(struct gfs2_glock *gl);
-
 static inline unsigned int buf_limit(struct gfs2_sbd *sdp)
 {
 	unsigned int limit;
diff --git a/fs/gfs2/ops_fstype.c b/fs/gfs2/ops_fstype.c
index 7a7e3c10a9a9..61fce59cb4d3 100644
--- a/fs/gfs2/ops_fstype.c
+++ b/fs/gfs2/ops_fstype.c
@@ -633,8 +633,10 @@ static int init_statfs(struct gfs2_sbd *sdp)
 	if (IS_ERR(sdp->sd_statfs_inode)) {
 		error = PTR_ERR(sdp->sd_statfs_inode);
 		fs_err(sdp, "can't read in statfs inode: %d\n", error);
-		goto fail;
+		goto out;
 	}
+	if (sdp->sd_args.ar_spectator)
+		goto out;
 
 	pn = gfs2_lookup_simple(master, "per_node");
 	if (IS_ERR(pn)) {
@@ -682,15 +684,17 @@ free_local:
 	iput(pn);
 put_statfs:
 	iput(sdp->sd_statfs_inode);
-fail:
+out:
 	return error;
 }
 
 /* Uninitialize and free up memory used by the list of statfs inodes */
 static void uninit_statfs(struct gfs2_sbd *sdp)
 {
-	gfs2_glock_dq_uninit(&sdp->sd_sc_gh);
-	free_local_statfs_inodes(sdp);
+	if (!sdp->sd_args.ar_spectator) {
+		gfs2_glock_dq_uninit(&sdp->sd_sc_gh);
+		free_local_statfs_inodes(sdp);
+	}
 	iput(sdp->sd_statfs_inode);
 }
 
@@ -704,7 +708,7 @@ static int init_journal(struct gfs2_sbd *sdp, int undo)
 
 	if (undo) {
 		jindex = 0;
-		goto fail_jinode_gh;
+		goto fail_statfs;
 	}
 
 	sdp->sd_jindex = gfs2_lookup_simple(master, "jindex");
diff --git a/fs/gfs2/recovery.c b/fs/gfs2/recovery.c
index b5cbe21efdfb..c26c68ebd29d 100644
--- a/fs/gfs2/recovery.c
+++ b/fs/gfs2/recovery.c
@@ -349,7 +349,7 @@ static int update_statfs_inode(struct gfs2_jdesc *jd,
 
 	mark_buffer_dirty(bh);
 	brelse(bh);
-	gfs2_meta_sync(ip->i_gl);
+	gfs2_inode_metasync(ip->i_gl);
 
 out:
 	return error;
diff --git a/fs/gfs2/rgrp.c b/fs/gfs2/rgrp.c
index ee491bb9c1cc..92d799a193b8 100644
--- a/fs/gfs2/rgrp.c
+++ b/fs/gfs2/rgrp.c
@@ -719,9 +719,9 @@ void gfs2_clear_rgrpd(struct gfs2_sbd *sdp)
 		}
 
 		gfs2_free_clones(rgd);
+		return_all_reservations(rgd);
 		kfree(rgd->rd_bits);
 		rgd->rd_bits = NULL;
-		return_all_reservations(rgd);
 		kmem_cache_free(gfs2_rgrpd_cachep, rgd);
 	}
 }
@@ -1370,6 +1370,9 @@ int gfs2_fitrim(struct file *filp, void __user *argp)
 	if (!capable(CAP_SYS_ADMIN))
 		return -EPERM;
 
+	if (!test_bit(SDF_JOURNAL_LIVE, &sdp->sd_flags))
+		return -EROFS;
+
 	if (!blk_queue_discard(q))
 		return -EOPNOTSUPP;
 
diff --git a/fs/gfs2/super.c b/fs/gfs2/super.c
index b285192bd6b3..b3d951ab8068 100644
--- a/fs/gfs2/super.c
+++ b/fs/gfs2/super.c
@@ -738,6 +738,7 @@ restart:
 	gfs2_jindex_free(sdp);
 	/*  Take apart glock structures and buffer lists  */
 	gfs2_gl_hash_clear(sdp);
+	truncate_inode_pages_final(&sdp->sd_aspace);
 	gfs2_delete_debugfs_file(sdp);
 	/*  Unmount the locking protocol  */
 	gfs2_lm_unmount(sdp);
diff --git a/fs/io-wq.c b/fs/io-wq.c
index 02894df7656d..b53c055bea6a 100644
--- a/fs/io-wq.c
+++ b/fs/io-wq.c
@@ -482,6 +482,10 @@ static void io_impersonate_work(struct io_worker *worker,
 		current->files = work->identity->files;
 		current->nsproxy = work->identity->nsproxy;
 		task_unlock(current);
+		if (!work->identity->files) {
+			/* failed grabbing files, ensure work gets cancelled */
+			work->flags |= IO_WQ_WORK_CANCEL;
+		}
 	}
 	if ((work->flags & IO_WQ_WORK_FS) && current->fs != work->identity->fs)
 		current->fs = work->identity->fs;
diff --git a/fs/io_uring.c b/fs/io_uring.c
index a7429c977eb3..8018c7076b25 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -995,20 +995,33 @@ static void io_sq_thread_drop_mm(void)
 	if (mm) {
 		kthread_unuse_mm(mm);
 		mmput(mm);
+		current->mm = NULL;
 	}
 }
 
 static int __io_sq_thread_acquire_mm(struct io_ring_ctx *ctx)
 {
-	if (!current->mm) {
-		if (unlikely(!(ctx->flags & IORING_SETUP_SQPOLL) ||
-			     !ctx->sqo_task->mm ||
-			     !mmget_not_zero(ctx->sqo_task->mm)))
-			return -EFAULT;
-		kthread_use_mm(ctx->sqo_task->mm);
+	struct mm_struct *mm;
+
+	if (current->mm)
+		return 0;
+
+	/* Should never happen */
+	if (unlikely(!(ctx->flags & IORING_SETUP_SQPOLL)))
+		return -EFAULT;
+
+	task_lock(ctx->sqo_task);
+	mm = ctx->sqo_task->mm;
+	if (unlikely(!mm || !mmget_not_zero(mm)))
+		mm = NULL;
+	task_unlock(ctx->sqo_task);
+
+	if (mm) {
+		kthread_use_mm(mm);
+		return 0;
 	}
 
-	return 0;
+	return -EFAULT;
 }
 
 static int io_sq_thread_acquire_mm(struct io_ring_ctx *ctx,
@@ -1274,9 +1287,12 @@ static bool io_identity_cow(struct io_kiocb *req)
 	/* add one for this request */
 	refcount_inc(&id->count);
 
-	/* drop old identity, assign new one. one ref for req, one for tctx */
-	if (req->work.identity != tctx->identity &&
-	    refcount_sub_and_test(2, &req->work.identity->count))
+	/* drop tctx and req identity references, if needed */
+	if (tctx->identity != &tctx->__identity &&
+	    refcount_dec_and_test(&tctx->identity->count))
+		kfree(tctx->identity);
+	if (req->work.identity != &tctx->__identity &&
+	    refcount_dec_and_test(&req->work.identity->count))
 		kfree(req->work.identity);
 
 	req->work.identity = id;
@@ -1577,14 +1593,29 @@ static void io_cqring_mark_overflow(struct io_ring_ctx *ctx)
 	}
 }
 
-static inline bool io_match_files(struct io_kiocb *req,
-				       struct files_struct *files)
+static inline bool __io_match_files(struct io_kiocb *req,
+				    struct files_struct *files)
 {
+	return ((req->flags & REQ_F_WORK_INITIALIZED) &&
+	        (req->work.flags & IO_WQ_WORK_FILES)) &&
+		req->work.identity->files == files;
+}
+
+static bool io_match_files(struct io_kiocb *req,
+			   struct files_struct *files)
+{
+	struct io_kiocb *link;
+
 	if (!files)
 		return true;
-	if ((req->flags & REQ_F_WORK_INITIALIZED) &&
-	    (req->work.flags & IO_WQ_WORK_FILES))
-		return req->work.identity->files == files;
+	if (__io_match_files(req, files))
+		return true;
+	if (req->flags & REQ_F_LINK_HEAD) {
+		list_for_each_entry(link, &req->link_list, link_list) {
+			if (__io_match_files(link, files))
+				return true;
+		}
+	}
 	return false;
 }
 
@@ -1668,7 +1699,8 @@ static void __io_cqring_fill_event(struct io_kiocb *req, long res, long cflags)
 		WRITE_ONCE(cqe->user_data, req->user_data);
 		WRITE_ONCE(cqe->res, res);
 		WRITE_ONCE(cqe->flags, cflags);
-	} else if (ctx->cq_overflow_flushed || req->task->io_uring->in_idle) {
+	} else if (ctx->cq_overflow_flushed ||
+		   atomic_read(&req->task->io_uring->in_idle)) {
 		/*
 		 * If we're in ring overflow flush mode, or in task cancel mode,
 		 * then we cannot store the request for later flushing, we need
@@ -1838,7 +1870,7 @@ static void __io_free_req(struct io_kiocb *req)
 	io_dismantle_req(req);
 
 	percpu_counter_dec(&tctx->inflight);
-	if (tctx->in_idle)
+	if (atomic_read(&tctx->in_idle))
 		wake_up(&tctx->wait);
 	put_task_struct(req->task);
 
@@ -7695,7 +7727,8 @@ static int io_uring_alloc_task_context(struct task_struct *task)
 	xa_init(&tctx->xa);
 	init_waitqueue_head(&tctx->wait);
 	tctx->last = NULL;
-	tctx->in_idle = 0;
+	atomic_set(&tctx->in_idle, 0);
+	tctx->sqpoll = false;
 	io_init_identity(&tctx->__identity);
 	tctx->identity = &tctx->__identity;
 	task->io_uring = tctx;
@@ -8388,22 +8421,6 @@ static bool io_match_link(struct io_kiocb *preq, struct io_kiocb *req)
 	return false;
 }
 
-static bool io_match_link_files(struct io_kiocb *req,
-				struct files_struct *files)
-{
-	struct io_kiocb *link;
-
-	if (io_match_files(req, files))
-		return true;
-	if (req->flags & REQ_F_LINK_HEAD) {
-		list_for_each_entry(link, &req->link_list, link_list) {
-			if (io_match_files(link, files))
-				return true;
-		}
-	}
-	return false;
-}
-
 /*
  * We're looking to cancel 'req' because it's holding on to our files, but
  * 'req' could be a link to another request. See if it is, and cancel that
@@ -8453,7 +8470,21 @@ static bool io_timeout_remove_link(struct io_ring_ctx *ctx,
 
 static bool io_cancel_link_cb(struct io_wq_work *work, void *data)
 {
-	return io_match_link(container_of(work, struct io_kiocb, work), data);
+	struct io_kiocb *req = container_of(work, struct io_kiocb, work);
+	bool ret;
+
+	if (req->flags & REQ_F_LINK_TIMEOUT) {
+		unsigned long flags;
+		struct io_ring_ctx *ctx = req->ctx;
+
+		/* protect against races with linked timeouts */
+		spin_lock_irqsave(&ctx->completion_lock, flags);
+		ret = io_match_link(req, data);
+		spin_unlock_irqrestore(&ctx->completion_lock, flags);
+	} else {
+		ret = io_match_link(req, data);
+	}
+	return ret;
 }
 
 static void io_attempt_cancel(struct io_ring_ctx *ctx, struct io_kiocb *req)
@@ -8479,6 +8510,7 @@ static void io_attempt_cancel(struct io_ring_ctx *ctx, struct io_kiocb *req)
 }
 
 static void io_cancel_defer_files(struct io_ring_ctx *ctx,
+				  struct task_struct *task,
 				  struct files_struct *files)
 {
 	struct io_defer_entry *de = NULL;
@@ -8486,7 +8518,8 @@ static void io_cancel_defer_files(struct io_ring_ctx *ctx,
 
 	spin_lock_irq(&ctx->completion_lock);
 	list_for_each_entry_reverse(de, &ctx->defer_list, list) {
-		if (io_match_link_files(de->req, files)) {
+		if (io_task_match(de->req, task) &&
+		    io_match_files(de->req, files)) {
 			list_cut_position(&list, &ctx->defer_list, &de->list);
 			break;
 		}
@@ -8512,7 +8545,6 @@ static bool io_uring_cancel_files(struct io_ring_ctx *ctx,
 	if (list_empty_careful(&ctx->inflight_list))
 		return false;
 
-	io_cancel_defer_files(ctx, files);
 	/* cancel all at once, should be faster than doing it one by one*/
 	io_wq_cancel_cb(ctx->io_wq, io_wq_files_match, files, true);
 
@@ -8598,8 +8630,16 @@ static void io_uring_cancel_task_requests(struct io_ring_ctx *ctx,
 {
 	struct task_struct *task = current;
 
-	if ((ctx->flags & IORING_SETUP_SQPOLL) && ctx->sq_data)
+	if ((ctx->flags & IORING_SETUP_SQPOLL) && ctx->sq_data) {
 		task = ctx->sq_data->thread;
+		atomic_inc(&task->io_uring->in_idle);
+		io_sq_thread_park(ctx->sq_data);
+	}
+
+	if (files)
+		io_cancel_defer_files(ctx, NULL, files);
+	else
+		io_cancel_defer_files(ctx, task, NULL);
 
 	io_cqring_overflow_flush(ctx, true, task, files);
 
@@ -8607,12 +8647,23 @@ static void io_uring_cancel_task_requests(struct io_ring_ctx *ctx,
 		io_run_task_work();
 		cond_resched();
 	}
+
+	if ((ctx->flags & IORING_SETUP_SQPOLL) && ctx->sq_data) {
+		atomic_dec(&task->io_uring->in_idle);
+		/*
+		 * If the files that are going away are the ones in the thread
+		 * identity, clear them out.
+		 */
+		if (task->io_uring->identity->files == files)
+			task->io_uring->identity->files = NULL;
+		io_sq_thread_unpark(ctx->sq_data);
+	}
 }
 
 /*
  * Note that this task has used io_uring. We use it for cancelation purposes.
  */
-static int io_uring_add_task_file(struct file *file)
+static int io_uring_add_task_file(struct io_ring_ctx *ctx, struct file *file)
 {
 	struct io_uring_task *tctx = current->io_uring;
 
@@ -8634,6 +8685,14 @@ static int io_uring_add_task_file(struct file *file)
 		tctx->last = file;
 	}
 
+	/*
+	 * This is race safe in that the task itself is doing this, hence it
+	 * cannot be going through the exit/cancel paths at the same time.
+	 * This cannot be modified while exit/cancel is running.
+	 */
+	if (!tctx->sqpoll && (ctx->flags & IORING_SETUP_SQPOLL))
+		tctx->sqpoll = true;
+
 	return 0;
 }
 
@@ -8675,7 +8734,7 @@ void __io_uring_files_cancel(struct files_struct *files)
 	unsigned long index;
 
 	/* make sure overflow events are dropped */
-	tctx->in_idle = true;
+	atomic_inc(&tctx->in_idle);
 
 	xa_for_each(&tctx->xa, index, file) {
 		struct io_ring_ctx *ctx = file->private_data;
@@ -8684,6 +8743,35 @@ void __io_uring_files_cancel(struct files_struct *files)
 		if (files)
 			io_uring_del_task_file(file);
 	}
+
+	atomic_dec(&tctx->in_idle);
+}
+
+static s64 tctx_inflight(struct io_uring_task *tctx)
+{
+	unsigned long index;
+	struct file *file;
+	s64 inflight;
+
+	inflight = percpu_counter_sum(&tctx->inflight);
+	if (!tctx->sqpoll)
+		return inflight;
+
+	/*
+	 * If we have SQPOLL rings, then we need to iterate and find them, and
+	 * add the pending count for those.
+	 */
+	xa_for_each(&tctx->xa, index, file) {
+		struct io_ring_ctx *ctx = file->private_data;
+
+		if (ctx->flags & IORING_SETUP_SQPOLL) {
+			struct io_uring_task *__tctx = ctx->sqo_task->io_uring;
+
+			inflight += percpu_counter_sum(&__tctx->inflight);
+		}
+	}
+
+	return inflight;
 }
 
 /*
@@ -8697,11 +8785,11 @@ void __io_uring_task_cancel(void)
 	s64 inflight;
 
 	/* make sure overflow events are dropped */
-	tctx->in_idle = true;
+	atomic_inc(&tctx->in_idle);
 
 	do {
 		/* read completions before cancelations */
-		inflight = percpu_counter_sum(&tctx->inflight);
+		inflight = tctx_inflight(tctx);
 		if (!inflight)
 			break;
 		__io_uring_files_cancel(NULL);
@@ -8712,13 +8800,13 @@ void __io_uring_task_cancel(void)
 		 * If we've seen completions, retry. This avoids a race where
 		 * a completion comes in before we did prepare_to_wait().
 		 */
-		if (inflight != percpu_counter_sum(&tctx->inflight))
+		if (inflight != tctx_inflight(tctx))
 			continue;
 		schedule();
 	} while (1);
 
 	finish_wait(&tctx->wait, &wait);
-	tctx->in_idle = false;
+	atomic_dec(&tctx->in_idle);
 }
 
 static int io_uring_flush(struct file *file, void *data)
@@ -8863,7 +8951,7 @@ SYSCALL_DEFINE6(io_uring_enter, unsigned int, fd, u32, to_submit,
 			io_sqpoll_wait_sq(ctx);
 		submitted = to_submit;
 	} else if (to_submit) {
-		ret = io_uring_add_task_file(f.file);
+		ret = io_uring_add_task_file(ctx, f.file);
 		if (unlikely(ret))
 			goto out;
 		mutex_lock(&ctx->uring_lock);
@@ -8900,7 +8988,8 @@ out_fput:
 #ifdef CONFIG_PROC_FS
 static int io_uring_show_cred(int id, void *p, void *data)
 {
-	const struct cred *cred = p;
+	struct io_identity *iod = p;
+	const struct cred *cred = iod->creds;
 	struct seq_file *m = data;
 	struct user_namespace *uns = seq_user_ns(m);
 	struct group_info *gi;
@@ -9092,7 +9181,7 @@ err_fd:
 #if defined(CONFIG_UNIX)
 	ctx->ring_sock->file = file;
 #endif
-	if (unlikely(io_uring_add_task_file(file))) {
+	if (unlikely(io_uring_add_task_file(ctx, file))) {
 		file = ERR_PTR(-ENOMEM);
 		goto err_fd;
 	}
diff --git a/fs/iomap/buffered-io.c b/fs/iomap/buffered-io.c
index 8180061b9e16..10cc7979ce38 100644
--- a/fs/iomap/buffered-io.c
+++ b/fs/iomap/buffered-io.c
@@ -1374,6 +1374,7 @@ iomap_writepage_map(struct iomap_writepage_ctx *wpc,
 	WARN_ON_ONCE(!wpc->ioend && !list_empty(&submit_list));
 	WARN_ON_ONCE(!PageLocked(page));
 	WARN_ON_ONCE(PageWriteback(page));
+	WARN_ON_ONCE(PageDirty(page));
 
 	/*
 	 * We cannot cancel the ioend directly here on error.  We may have
@@ -1382,33 +1383,22 @@ iomap_writepage_map(struct iomap_writepage_ctx *wpc,
 	 * appropriately.
 	 */
 	if (unlikely(error)) {
+		/*
+		 * Let the filesystem know what portion of the current page
+		 * failed to map. If the page wasn't been added to ioend, it
+		 * won't be affected by I/O completion and we must unlock it
+		 * now.
+		 */
+		if (wpc->ops->discard_page)
+			wpc->ops->discard_page(page, file_offset);
 		if (!count) {
-			/*
-			 * If the current page hasn't been added to ioend, it
-			 * won't be affected by I/O completions and we must
-			 * discard and unlock it right here.
-			 */
-			if (wpc->ops->discard_page)
-				wpc->ops->discard_page(page);
 			ClearPageUptodate(page);
 			unlock_page(page);
 			goto done;
 		}
-
-		/*
-		 * If the page was not fully cleaned, we need to ensure that the
-		 * higher layers come back to it correctly.  That means we need
-		 * to keep the page dirty, and for WB_SYNC_ALL writeback we need
-		 * to ensure the PAGECACHE_TAG_TOWRITE index mark is not removed
-		 * so another attempt to write this page in this writeback sweep
-		 * will be made.
-		 */
-		set_page_writeback_keepwrite(page);
-	} else {
-		clear_page_dirty_for_io(page);
-		set_page_writeback(page);
 	}
 
+	set_page_writeback(page);
 	unlock_page(page);
 
 	/*
diff --git a/fs/proc/base.c b/fs/proc/base.c
index 0f707003dda5..b362523a9829 100644
--- a/fs/proc/base.c
+++ b/fs/proc/base.c
@@ -1049,6 +1049,8 @@ static ssize_t oom_adj_read(struct file *file, char __user *buf, size_t count,
 		oom_adj = (task->signal->oom_score_adj * -OOM_DISABLE) /
 			  OOM_SCORE_ADJ_MAX;
 	put_task_struct(task);
+	if (oom_adj > OOM_ADJUST_MAX)
+		oom_adj = OOM_ADJUST_MAX;
 	len = snprintf(buffer, sizeof(buffer), "%d\n", oom_adj);
 	return simple_read_from_buffer(buf, count, ppos, buffer, len);
 }
diff --git a/fs/proc/cpuinfo.c b/fs/proc/cpuinfo.c
index d0989a443c77..419760fd77bd 100644
--- a/fs/proc/cpuinfo.c
+++ b/fs/proc/cpuinfo.c
@@ -19,7 +19,7 @@ static int cpuinfo_open(struct inode *inode, struct file *file)
 static const struct proc_ops cpuinfo_proc_ops = {
 	.proc_flags	= PROC_ENTRY_PERMANENT,
 	.proc_open	= cpuinfo_open,
-	.proc_read	= seq_read,
+	.proc_read_iter	= seq_read_iter,
 	.proc_lseek	= seq_lseek,
 	.proc_release	= seq_release,
 };
diff --git a/fs/proc/generic.c b/fs/proc/generic.c
index 2f9fa179194d..b84663252add 100644
--- a/fs/proc/generic.c
+++ b/fs/proc/generic.c
@@ -590,7 +590,7 @@ static int proc_seq_release(struct inode *inode, struct file *file)
 static const struct proc_ops proc_seq_ops = {
 	/* not permanent -- can call into arbitrary seq_operations */
 	.proc_open	= proc_seq_open,
-	.proc_read	= seq_read,
+	.proc_read_iter	= seq_read_iter,
 	.proc_lseek	= seq_lseek,
 	.proc_release	= proc_seq_release,
 };
@@ -621,7 +621,7 @@ static int proc_single_open(struct inode *inode, struct file *file)
 static const struct proc_ops proc_single_ops = {
 	/* not permanent -- can call into arbitrary ->single_show */
 	.proc_open	= proc_single_open,
-	.proc_read	= seq_read,
+	.proc_read_iter = seq_read_iter,
 	.proc_lseek	= seq_lseek,
 	.proc_release	= single_release,
 };
diff --git a/fs/proc/inode.c b/fs/proc/inode.c
index 58c075e2a452..bde6b6f69852 100644
--- a/fs/proc/inode.c
+++ b/fs/proc/inode.c
@@ -597,6 +597,7 @@ static const struct file_operations proc_iter_file_ops = {
 	.llseek		= proc_reg_llseek,
 	.read_iter	= proc_reg_read_iter,
 	.write		= proc_reg_write,
+	.splice_read	= generic_file_splice_read,
 	.poll		= proc_reg_poll,
 	.unlocked_ioctl	= proc_reg_unlocked_ioctl,
 	.mmap		= proc_reg_mmap,
@@ -622,6 +623,7 @@ static const struct file_operations proc_reg_file_ops_compat = {
 static const struct file_operations proc_iter_file_ops_compat = {
 	.llseek		= proc_reg_llseek,
 	.read_iter	= proc_reg_read_iter,
+	.splice_read	= generic_file_splice_read,
 	.write		= proc_reg_write,
 	.poll		= proc_reg_poll,
 	.unlocked_ioctl	= proc_reg_unlocked_ioctl,
diff --git a/fs/proc/stat.c b/fs/proc/stat.c
index 46b3293015fe..4695b6de3151 100644
--- a/fs/proc/stat.c
+++ b/fs/proc/stat.c
@@ -226,7 +226,7 @@ static int stat_open(struct inode *inode, struct file *file)
 static const struct proc_ops stat_proc_ops = {
 	.proc_flags	= PROC_ENTRY_PERMANENT,
 	.proc_open	= stat_open,
-	.proc_read	= seq_read,
+	.proc_read_iter	= seq_read_iter,
 	.proc_lseek	= seq_lseek,
 	.proc_release	= single_release,
 };
diff --git a/fs/seq_file.c b/fs/seq_file.c
index 31219c1db17d..3b20e21604e7 100644
--- a/fs/seq_file.c
+++ b/fs/seq_file.c
@@ -18,6 +18,7 @@
 #include <linux/mm.h>
 #include <linux/printk.h>
 #include <linux/string_helpers.h>
+#include <linux/uio.h>
 
 #include <linux/uaccess.h>
 #include <asm/page.h>
@@ -146,7 +147,28 @@ Eoverflow:
  */
 ssize_t seq_read(struct file *file, char __user *buf, size_t size, loff_t *ppos)
 {
-	struct seq_file *m = file->private_data;
+	struct iovec iov = { .iov_base = buf, .iov_len = size};
+	struct kiocb kiocb;
+	struct iov_iter iter;
+	ssize_t ret;
+
+	init_sync_kiocb(&kiocb, file);
+	iov_iter_init(&iter, READ, &iov, 1, size);
+
+	kiocb.ki_pos = *ppos;
+	ret = seq_read_iter(&kiocb, &iter);
+	*ppos = kiocb.ki_pos;
+	return ret;
+}
+EXPORT_SYMBOL(seq_read);
+
+/*
+ * Ready-made ->f_op->read_iter()
+ */
+ssize_t seq_read_iter(struct kiocb *iocb, struct iov_iter *iter)
+{
+	struct seq_file *m = iocb->ki_filp->private_data;
+	size_t size = iov_iter_count(iter);
 	size_t copied = 0;
 	size_t n;
 	void *p;
@@ -158,14 +180,14 @@ ssize_t seq_read(struct file *file, char __user *buf, size_t size, loff_t *ppos)
 	 * if request is to read from zero offset, reset iterator to first
 	 * record as it might have been already advanced by previous requests
 	 */
-	if (*ppos == 0) {
+	if (iocb->ki_pos == 0) {
 		m->index = 0;
 		m->count = 0;
 	}
 
-	/* Don't assume *ppos is where we left it */
-	if (unlikely(*ppos != m->read_pos)) {
-		while ((err = traverse(m, *ppos)) == -EAGAIN)
+	/* Don't assume ki_pos is where we left it */
+	if (unlikely(iocb->ki_pos != m->read_pos)) {
+		while ((err = traverse(m, iocb->ki_pos)) == -EAGAIN)
 			;
 		if (err) {
 			/* With prejudice... */
@@ -174,7 +196,7 @@ ssize_t seq_read(struct file *file, char __user *buf, size_t size, loff_t *ppos)
 			m->count = 0;
 			goto Done;
 		} else {
-			m->read_pos = *ppos;
+			m->read_pos = iocb->ki_pos;
 		}
 	}
 
@@ -187,13 +209,11 @@ ssize_t seq_read(struct file *file, char __user *buf, size_t size, loff_t *ppos)
 	/* if not empty - flush it first */
 	if (m->count) {
 		n = min(m->count, size);
-		err = copy_to_user(buf, m->buf + m->from, n);
-		if (err)
+		if (copy_to_iter(m->buf + m->from, n, iter) != n)
 			goto Efault;
 		m->count -= n;
 		m->from += n;
 		size -= n;
-		buf += n;
 		copied += n;
 		if (!size)
 			goto Done;
@@ -254,8 +274,7 @@ Fill:
 	}
 	m->op->stop(m, p);
 	n = min(m->count, size);
-	err = copy_to_user(buf, m->buf, n);
-	if (err)
+	if (copy_to_iter(m->buf, n, iter) != n)
 		goto Efault;
 	copied += n;
 	m->count -= n;
@@ -264,7 +283,7 @@ Done:
 	if (!copied)
 		copied = err;
 	else {
-		*ppos += copied;
+		iocb->ki_pos += copied;
 		m->read_pos += copied;
 	}
 	mutex_unlock(&m->lock);
@@ -276,7 +295,7 @@ Efault:
 	err = -EFAULT;
 	goto Done;
 }
-EXPORT_SYMBOL(seq_read);
+EXPORT_SYMBOL(seq_read_iter);
 
 /**
  *	seq_lseek -	->llseek() method for sequential files.
diff --git a/fs/xfs/libxfs/xfs_alloc.c b/fs/xfs/libxfs/xfs_alloc.c
index 852b536551b5..15640015be9d 100644
--- a/fs/xfs/libxfs/xfs_alloc.c
+++ b/fs/xfs/libxfs/xfs_alloc.c
@@ -2467,6 +2467,7 @@ xfs_defer_agfl_block(
 	new->xefi_startblock = XFS_AGB_TO_FSB(mp, agno, agbno);
 	new->xefi_blockcount = 1;
 	new->xefi_oinfo = *oinfo;
+	new->xefi_skip_discard = false;
 
 	trace_xfs_agfl_free_defer(mp, agno, 0, agbno, 1);
 
diff --git a/fs/xfs/libxfs/xfs_bmap.h b/fs/xfs/libxfs/xfs_bmap.h
index e1bd484e5548..6747e97a7949 100644
--- a/fs/xfs/libxfs/xfs_bmap.h
+++ b/fs/xfs/libxfs/xfs_bmap.h
@@ -52,9 +52,9 @@ struct xfs_extent_free_item
 {
 	xfs_fsblock_t		xefi_startblock;/* starting fs block number */
 	xfs_extlen_t		xefi_blockcount;/* number of blocks in extent */
+	bool			xefi_skip_discard;
 	struct list_head	xefi_list;
 	struct xfs_owner_info	xefi_oinfo;	/* extent owner */
-	bool			xefi_skip_discard;
 };
 
 #define	XFS_BMAP_MAX_NMAP	4
diff --git a/fs/xfs/scrub/inode.c b/fs/xfs/scrub/inode.c
index 3aa85b64de36..bb25ff1b770d 100644
--- a/fs/xfs/scrub/inode.c
+++ b/fs/xfs/scrub/inode.c
@@ -121,8 +121,7 @@ xchk_inode_flags(
 		goto bad;
 
 	/* rt flags require rt device */
-	if ((flags & (XFS_DIFLAG_REALTIME | XFS_DIFLAG_RTINHERIT)) &&
-	    !mp->m_rtdev_targp)
+	if ((flags & XFS_DIFLAG_REALTIME) && !mp->m_rtdev_targp)
 		goto bad;
 
 	/* new rt bitmap flag only valid for rbmino */
diff --git a/fs/xfs/xfs_aops.c b/fs/xfs/xfs_aops.c
index 55d126d4e096..4304c6416fbb 100644
--- a/fs/xfs/xfs_aops.c
+++ b/fs/xfs/xfs_aops.c
@@ -346,8 +346,8 @@ xfs_map_blocks(
 	ssize_t			count = i_blocksize(inode);
 	xfs_fileoff_t		offset_fsb = XFS_B_TO_FSBT(mp, offset);
 	xfs_fileoff_t		end_fsb = XFS_B_TO_FSB(mp, offset + count);
-	xfs_fileoff_t		cow_fsb = NULLFILEOFF;
-	int			whichfork = XFS_DATA_FORK;
+	xfs_fileoff_t		cow_fsb;
+	int			whichfork;
 	struct xfs_bmbt_irec	imap;
 	struct xfs_iext_cursor	icur;
 	int			retries = 0;
@@ -381,6 +381,8 @@ xfs_map_blocks(
 	 * landed in a hole and we skip the block.
 	 */
 retry:
+	cow_fsb = NULLFILEOFF;
+	whichfork = XFS_DATA_FORK;
 	xfs_ilock(ip, XFS_ILOCK_SHARED);
 	ASSERT(ip->i_df.if_format != XFS_DINODE_FMT_BTREE ||
 	       (ip->i_df.if_flags & XFS_IFEXTENTS));
@@ -527,13 +529,15 @@ xfs_prepare_ioend(
  */
 static void
 xfs_discard_page(
-	struct page		*page)
+	struct page		*page,
+	loff_t			fileoff)
 {
 	struct inode		*inode = page->mapping->host;
 	struct xfs_inode	*ip = XFS_I(inode);
 	struct xfs_mount	*mp = ip->i_mount;
-	loff_t			offset = page_offset(page);
-	xfs_fileoff_t		start_fsb = XFS_B_TO_FSBT(mp, offset);
+	unsigned int		pageoff = offset_in_page(fileoff);
+	xfs_fileoff_t		start_fsb = XFS_B_TO_FSBT(mp, fileoff);
+	xfs_fileoff_t		pageoff_fsb = XFS_B_TO_FSBT(mp, pageoff);
 	int			error;
 
 	if (XFS_FORCED_SHUTDOWN(mp))
@@ -541,14 +545,14 @@ xfs_discard_page(
 
 	xfs_alert_ratelimited(mp,
 		"page discard on page "PTR_FMT", inode 0x%llx, offset %llu.",
-			page, ip->i_ino, offset);
+			page, ip->i_ino, fileoff);
 
 	error = xfs_bmap_punch_delalloc_range(ip, start_fsb,
-			i_blocks_per_page(inode, page));
+			i_blocks_per_page(inode, page) - pageoff_fsb);
 	if (error && !XFS_FORCED_SHUTDOWN(mp))
 		xfs_alert(mp, "page discard unable to remove delalloc mapping.");
 out_invalidate:
-	iomap_invalidatepage(page, 0, PAGE_SIZE);
+	iomap_invalidatepage(page, pageoff, PAGE_SIZE - pageoff);
 }
 
 static const struct iomap_writeback_ops xfs_writeback_ops = {
diff --git a/fs/xfs/xfs_iops.c b/fs/xfs/xfs_iops.c
index 5e165456da68..1414ab79eacf 100644
--- a/fs/xfs/xfs_iops.c
+++ b/fs/xfs/xfs_iops.c
@@ -911,6 +911,16 @@ xfs_setattr_size(
 		error = iomap_zero_range(inode, oldsize, newsize - oldsize,
 				&did_zeroing, &xfs_buffered_write_iomap_ops);
 	} else {
+		/*
+		 * iomap won't detect a dirty page over an unwritten block (or a
+		 * cow block over a hole) and subsequently skips zeroing the
+		 * newly post-EOF portion of the page. Flush the new EOF to
+		 * convert the block before the pagecache truncate.
+		 */
+		error = filemap_write_and_wait_range(inode->i_mapping, newsize,
+						     newsize);
+		if (error)
+			return error;
 		error = iomap_truncate_page(inode, newsize, &did_zeroing,
 				&xfs_buffered_write_iomap_ops);
 	}
diff --git a/fs/xfs/xfs_reflink.c b/fs/xfs/xfs_reflink.c
index 16098dc42add..6fa05fb78189 100644
--- a/fs/xfs/xfs_reflink.c
+++ b/fs/xfs/xfs_reflink.c
@@ -1502,7 +1502,8 @@ xfs_reflink_unshare(
 			&xfs_buffered_write_iomap_ops);
 	if (error)
 		goto out;
-	error = filemap_write_and_wait(inode->i_mapping);
+
+	error = filemap_write_and_wait_range(inode->i_mapping, offset, len);
 	if (error)
 		goto out;
 
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
index 8712e14991ed..cde3c8c9f20c 100644
--- a/include/drm/amd_asic_type.h
+++ b/include/drm/amd_asic_type.h
@@ -56,6 +56,8 @@ enum amd_asic_type {
 	CHIP_NAVI12,	/* 27 */
 	CHIP_SIENNA_CICHLID,	/* 28 */
 	CHIP_NAVY_FLOUNDER,	/* 29 */
+	CHIP_VANGOGH,	/* 30 */
+	CHIP_DIMGREY_CAVEFISH,	/* 31 */
 	CHIP_LAST,
 };
 
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 59b51a09cae6..ba839e5e357d 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -325,6 +325,13 @@ struct drm_crtc_state {
 	bool self_refresh_active;
 
 	/**
+	 * @scaling_filter:
+	 *
+	 * Scaling filter to be applied
+	 */
+	enum drm_scaling_filter scaling_filter;
+
+	/**
 	 * @event:
 	 *
 	 * Optional pointer to a DRM event to signal upon completion of the
@@ -1084,6 +1091,12 @@ struct drm_crtc {
 	struct drm_object_properties properties;
 
 	/**
+	 * @scaling_filter_property: property to apply a particular filter while
+	 * scaling.
+	 */
+	struct drm_property *scaling_filter_property;
+
+	/**
 	 * @state:
 	 *
 	 * Current atomic state for this CRTC.
@@ -1266,4 +1279,7 @@ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev,
 #define drm_for_each_crtc(crtc, dev) \
 	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 
+int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc,
+					    unsigned int supported_filters);
+
 #endif /* __DRM_CRTC_H__ */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1f0ee7f3f473..6b40258927bf 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1118,15 +1118,58 @@ struct drm_device;
 #define DP_MAX_LANE_COUNT_PHY_REPEATER			    0xf0004 /* 1.4a */
 #define DP_Repeater_FEC_CAPABILITY			    0xf0004 /* 1.4 */
 #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT		    0xf0005 /* 1.4a */
+
+enum drm_dp_phy {
+	DP_PHY_DPRX,
+
+	DP_PHY_LTTPR1,
+	DP_PHY_LTTPR2,
+	DP_PHY_LTTPR3,
+	DP_PHY_LTTPR4,
+	DP_PHY_LTTPR5,
+	DP_PHY_LTTPR6,
+	DP_PHY_LTTPR7,
+	DP_PHY_LTTPR8,
+
+	DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
+};
+
+#define DP_PHY_LTTPR(i)					    (DP_PHY_LTTPR1 + (i))
+
+#define __DP_LTTPR1_BASE				    0xf0010 /* 1.3 */
+#define __DP_LTTPR2_BASE				    0xf0060 /* 1.3 */
+#define DP_LTTPR_BASE(dp_phy) \
+	(__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
+		((dp_phy) - DP_PHY_LTTPR1))
+
+#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
+	(DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
+
 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1		    0xf0010 /* 1.3 */
+#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
+	DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
+
 #define DP_TRAINING_LANE0_SET_PHY_REPEATER1		    0xf0011 /* 1.3 */
+#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
+	DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
+
 #define DP_TRAINING_LANE1_SET_PHY_REPEATER1		    0xf0012 /* 1.3 */
 #define DP_TRAINING_LANE2_SET_PHY_REPEATER1		    0xf0013 /* 1.3 */
 #define DP_TRAINING_LANE3_SET_PHY_REPEATER1		    0xf0014 /* 1.3 */
 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1	    0xf0020 /* 1.4a */
+#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy)	\
+	DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
+
 #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1		    0xf0021 /* 1.4a */
+# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED		    BIT(0)
+# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED		    BIT(1)
+
 #define DP_LANE0_1_STATUS_PHY_REPEATER1			    0xf0030 /* 1.3 */
+#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
+	DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
+
 #define DP_LANE2_3_STATUS_PHY_REPEATER1			    0xf0031 /* 1.3 */
+
 #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1	    0xf0032 /* 1.3 */
 #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1		    0xf0033 /* 1.3 */
 #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1		    0xf0034 /* 1.3 */
@@ -1237,9 +1280,13 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ
 #define DP_DSC_RECEIVER_CAP_SIZE        0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
 #define EDP_DISPLAY_CTL_CAP_SIZE	3
+#define DP_LTTPR_COMMON_CAP_SIZE	8
+#define DP_LTTPR_PHY_CAP_SIZE		3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
+void drm_dp_lttpr_link_train_clock_recovery_delay(void);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
+void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
 
 u8 drm_dp_link_rate_to_bw_code(int link_rate);
 int drm_dp_bw_code_to_link_rate(u8 link_bw);
@@ -1698,6 +1745,10 @@ int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
 				 u8 status[DP_LINK_STATUS_SIZE]);
 
+int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
+				     enum drm_dp_phy dp_phy,
+				     u8 link_status[DP_LINK_STATUS_SIZE]);
+
 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
 				    u8 real_edid_checksum);
 
@@ -1747,6 +1798,17 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
 				const struct drm_dp_desc *desc);
 int drm_dp_read_sink_count(struct drm_dp_aux *aux);
 
+int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+				  u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
+int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+			       enum drm_dp_phy dp_phy,
+			       u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
+int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
+int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
+int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
+bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
+bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
+
 void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
 void drm_dp_aux_init(struct drm_dp_aux *aux);
 int drm_dp_aux_register(struct drm_dp_aux *aux);
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 3f396d94afe4..1d82b264e5e4 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -35,6 +35,11 @@ struct drm_crtc;
 struct drm_printer;
 struct drm_modeset_acquire_ctx;
 
+enum drm_scaling_filter {
+	DRM_SCALING_FILTER_DEFAULT,
+	DRM_SCALING_FILTER_NEAREST_NEIGHBOR,
+};
+
 /**
  * struct drm_plane_state - mutable plane state
  *
@@ -215,6 +220,13 @@ struct drm_plane_state {
 	bool visible;
 
 	/**
+	 * @scaling_filter:
+	 *
+	 * Scaling filter to be applied
+	 */
+	enum drm_scaling_filter scaling_filter;
+
+	/**
 	 * @commit: Tracks the pending commit to prevent use-after-free conditions,
 	 * and for async plane updates.
 	 *
@@ -724,6 +736,12 @@ struct drm_plane {
 	 * See drm_plane_create_color_properties().
 	 */
 	struct drm_property *color_range_property;
+
+	/**
+	 * @scaling_filter_property: property to apply a particular filter while
+	 * scaling.
+	 */
+	struct drm_property *scaling_filter_property;
 };
 
 #define obj_to_plane(x) container_of(x, struct drm_plane, base)
@@ -862,4 +880,7 @@ drm_plane_get_damage_clips(const struct drm_plane_state *state)
 					state->fb_damage_clips->data : NULL);
 }
 
+int drm_plane_create_scaling_filter_property(struct drm_plane *plane,
+					     unsigned int supported_filters);
+
 #endif
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7eeecb07c9a1..3b5ed1e4f3ec 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -170,9 +170,9 @@
 
 #define INTEL_HSW_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
 	INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
-	INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
-	INTEL_VGA_DEVICE(0x0A06, info)  /* ULT GT1 mobile */
+	INTEL_VGA_DEVICE(0x0A0B, info)  /* ULT GT1 reserved */
 
 #define INTEL_HSW_ULX_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
@@ -181,26 +181,26 @@
 	INTEL_HSW_ULT_GT1_IDS(info), \
 	INTEL_HSW_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
-	INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
+	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
+	INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
 	INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
 	INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
 	INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */	\
 	INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
 	INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
-	INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
-	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
-	INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
-	INTEL_VGA_DEVICE(0x0D06, info)  /* CRW GT1 mobile */
+	INTEL_VGA_DEVICE(0x0D0E, info)  /* CRW GT1 reserved */
 
 #define INTEL_HSW_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */	\
 	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
-	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
-	INTEL_VGA_DEVICE(0x0A16, info)  /* ULT GT2 mobile */
+	INTEL_VGA_DEVICE(0x0A1B, info)  /* ULT GT2 reserved */ \
 
 #define INTEL_HSW_ULX_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
@@ -209,45 +209,45 @@
 	INTEL_HSW_ULT_GT2_IDS(info), \
 	INTEL_HSW_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
-	INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
+	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
+	INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \
 	INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
 	INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
 	INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
 	INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
 	INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
 	INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
 	INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
-	INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
-	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
-	INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
-	INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
-	INTEL_VGA_DEVICE(0x0D16, info)  /* CRW GT2 mobile */
+	INTEL_VGA_DEVICE(0x0D1E, info)  /* CRW GT2 reserved */
 
 #define INTEL_HSW_ULT_GT3_IDS(info) \
 	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
 	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
 	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
-	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
 	INTEL_VGA_DEVICE(0x0A2E, info)  /* ULT GT3 reserved */
 
 #define INTEL_HSW_GT3_IDS(info) \
 	INTEL_HSW_ULT_GT3_IDS(info), \
 	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
-	INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
+	INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
+	INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \
 	INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
 	INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
 	INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \
 	INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
 	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
-	INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
-	INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
-	INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
+	INTEL_VGA_DEVICE(0x0D2E, info)  /* CRW GT3 reserved */
 
 #define INTEL_HSW_IDS(info) \
 	INTEL_HSW_GT1_IDS(info), \
@@ -329,17 +329,20 @@
 	INTEL_VGA_DEVICE(0x22b3, info)
 
 #define INTEL_SKL_ULT_GT1_IDS(info) \
-	INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */
+	INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
+	INTEL_VGA_DEVICE(0x1913, info)  /* ULT GT1.5 */
 
 #define INTEL_SKL_ULX_GT1_IDS(info) \
-	INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */
+	INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+	INTEL_VGA_DEVICE(0x1915, info)  /* ULX GT1.5 */
 
 #define INTEL_SKL_GT1_IDS(info)	\
 	INTEL_SKL_ULT_GT1_IDS(info), \
 	INTEL_SKL_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
+	INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
 	INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
-	INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
+	INTEL_VGA_DEVICE(0x1917, info)  /* DT  GT1.5 */
 
 #define INTEL_SKL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
@@ -352,26 +355,26 @@
 	INTEL_SKL_ULT_GT2_IDS(info), \
 	INTEL_SKL_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
-	INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
+	INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
 
 #define INTEL_SKL_ULT_GT3_IDS(info) \
-	INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */
+	INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
+	INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3e */ \
+	INTEL_VGA_DEVICE(0x1927, info)  /* ULT GT3e */
 
 #define INTEL_SKL_GT3_IDS(info) \
 	INTEL_SKL_ULT_GT3_IDS(info), \
-	INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
-	INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
-	INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
-	INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3 */
+	INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
+	INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3e */ \
+	INTEL_VGA_DEVICE(0x192D, info)  /* SRV GT3e */
 
 #define INTEL_SKL_GT4_IDS(info) \
 	INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
-	INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
-	INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
-	INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
-	INTEL_VGA_DEVICE(0x193A, info)  /* SRV GT4e */
+	INTEL_VGA_DEVICE(0x193A, info), /* SRV GT4e */ \
+	INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4e */ \
+	INTEL_VGA_DEVICE(0x193D, info) /* WKS GT4e */
 
 #define INTEL_SKL_IDS(info)	 \
 	INTEL_SKL_GT1_IDS(info), \
@@ -403,8 +406,8 @@
 	INTEL_KBL_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
 	INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
-	INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
-	INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
+	INTEL_VGA_DEVICE(0x590A, info), /* SRV GT1 */ \
+	INTEL_VGA_DEVICE(0x590B, info) /* Halo GT1 */
 
 #define INTEL_KBL_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
@@ -416,10 +419,10 @@
 #define INTEL_KBL_GT2_IDS(info)	\
 	INTEL_KBL_ULT_GT2_IDS(info), \
 	INTEL_KBL_ULX_GT2_IDS(info), \
-	INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
 	INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
-	INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
+	INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
 	INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
+	INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
 	INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
 
 #define INTEL_KBL_ULT_GT3_IDS(info) \
@@ -444,10 +447,10 @@
 
 /* CML GT1 */
 #define INTEL_CML_GT1_IDS(info)	\
-	INTEL_VGA_DEVICE(0x9BA5, info), \
-	INTEL_VGA_DEVICE(0x9BA8, info), \
+	INTEL_VGA_DEVICE(0x9BA2, info), \
 	INTEL_VGA_DEVICE(0x9BA4, info), \
-	INTEL_VGA_DEVICE(0x9BA2, info)
+	INTEL_VGA_DEVICE(0x9BA5, info), \
+	INTEL_VGA_DEVICE(0x9BA8, info)
 
 #define INTEL_CML_U_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x9B21, info), \
@@ -456,11 +459,11 @@
 
 /* CML GT2 */
 #define INTEL_CML_GT2_IDS(info)	\
-	INTEL_VGA_DEVICE(0x9BC5, info), \
-	INTEL_VGA_DEVICE(0x9BC8, info), \
-	INTEL_VGA_DEVICE(0x9BC4, info), \
 	INTEL_VGA_DEVICE(0x9BC2, info), \
+	INTEL_VGA_DEVICE(0x9BC4, info), \
+	INTEL_VGA_DEVICE(0x9BC5, info), \
 	INTEL_VGA_DEVICE(0x9BC6, info), \
+	INTEL_VGA_DEVICE(0x9BC8, info), \
 	INTEL_VGA_DEVICE(0x9BE6, info), \
 	INTEL_VGA_DEVICE(0x9BF6, info)
 
@@ -494,8 +497,8 @@
 	INTEL_VGA_DEVICE(0x3E9C, info)
 
 #define INTEL_CFL_H_GT2_IDS(info) \
-	INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
-	INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
+	INTEL_VGA_DEVICE(0x3E94, info),  /* Halo GT2 */ \
+	INTEL_VGA_DEVICE(0x3E9B, info) /* Halo GT2 */
 
 /* CFL U GT2 */
 #define INTEL_CFL_U_GT2_IDS(info) \
@@ -540,54 +543,57 @@
 
 /* CNL */
 #define INTEL_CNL_PORT_F_IDS(info) \
-	INTEL_VGA_DEVICE(0x5A54, info), \
-	INTEL_VGA_DEVICE(0x5A5C, info), \
 	INTEL_VGA_DEVICE(0x5A44, info), \
-	INTEL_VGA_DEVICE(0x5A4C, info)
+	INTEL_VGA_DEVICE(0x5A4C, info), \
+	INTEL_VGA_DEVICE(0x5A54, info), \
+	INTEL_VGA_DEVICE(0x5A5C, info)
 
 #define INTEL_CNL_IDS(info) \
 	INTEL_CNL_PORT_F_IDS(info), \
-	INTEL_VGA_DEVICE(0x5A51, info), \
-	INTEL_VGA_DEVICE(0x5A59, info), \
+	INTEL_VGA_DEVICE(0x5A40, info), \
 	INTEL_VGA_DEVICE(0x5A41, info), \
-	INTEL_VGA_DEVICE(0x5A49, info), \
-	INTEL_VGA_DEVICE(0x5A52, info), \
-	INTEL_VGA_DEVICE(0x5A5A, info), \
 	INTEL_VGA_DEVICE(0x5A42, info), \
+	INTEL_VGA_DEVICE(0x5A49, info), \
 	INTEL_VGA_DEVICE(0x5A4A, info), \
 	INTEL_VGA_DEVICE(0x5A50, info), \
-	INTEL_VGA_DEVICE(0x5A40, info)
+	INTEL_VGA_DEVICE(0x5A51, info), \
+	INTEL_VGA_DEVICE(0x5A52, info), \
+	INTEL_VGA_DEVICE(0x5A59, info), \
+	INTEL_VGA_DEVICE(0x5A5A, info)
 
 /* ICL */
 #define INTEL_ICL_PORT_F_IDS(info) \
 	INTEL_VGA_DEVICE(0x8A50, info), \
-	INTEL_VGA_DEVICE(0x8A5C, info), \
-	INTEL_VGA_DEVICE(0x8A59, info),	\
-	INTEL_VGA_DEVICE(0x8A58, info),	\
 	INTEL_VGA_DEVICE(0x8A52, info), \
+	INTEL_VGA_DEVICE(0x8A53, info), \
+	INTEL_VGA_DEVICE(0x8A54, info), \
+	INTEL_VGA_DEVICE(0x8A56, info), \
+	INTEL_VGA_DEVICE(0x8A57, info), \
+	INTEL_VGA_DEVICE(0x8A58, info),	\
+	INTEL_VGA_DEVICE(0x8A59, info),	\
 	INTEL_VGA_DEVICE(0x8A5A, info), \
 	INTEL_VGA_DEVICE(0x8A5B, info), \
-	INTEL_VGA_DEVICE(0x8A57, info), \
-	INTEL_VGA_DEVICE(0x8A56, info), \
-	INTEL_VGA_DEVICE(0x8A71, info), \
+	INTEL_VGA_DEVICE(0x8A5C, info), \
 	INTEL_VGA_DEVICE(0x8A70, info), \
-	INTEL_VGA_DEVICE(0x8A53, info), \
-	INTEL_VGA_DEVICE(0x8A54, info)
+	INTEL_VGA_DEVICE(0x8A71, info)
 
 #define INTEL_ICL_11_IDS(info) \
 	INTEL_ICL_PORT_F_IDS(info), \
 	INTEL_VGA_DEVICE(0x8A51, info), \
 	INTEL_VGA_DEVICE(0x8A5D, info)
 
-/* EHL/JSL */
+/* EHL */
 #define INTEL_EHL_IDS(info) \
 	INTEL_VGA_DEVICE(0x4500, info),	\
 	INTEL_VGA_DEVICE(0x4571, info), \
 	INTEL_VGA_DEVICE(0x4551, info), \
 	INTEL_VGA_DEVICE(0x4541, info), \
-	INTEL_VGA_DEVICE(0x4E71, info), \
 	INTEL_VGA_DEVICE(0x4557, info), \
-	INTEL_VGA_DEVICE(0x4555, info), \
+	INTEL_VGA_DEVICE(0x4555, info)
+
+/* JSL */
+#define INTEL_JSL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4E71, info), \
 	INTEL_VGA_DEVICE(0x4E61, info), \
 	INTEL_VGA_DEVICE(0x4E57, info), \
 	INTEL_VGA_DEVICE(0x4E55, info), \
@@ -624,6 +630,9 @@
 
 /* DG1 */
 #define INTEL_DG1_IDS(info) \
-	INTEL_VGA_DEVICE(0x4905, info)
+	INTEL_VGA_DEVICE(0x4905, info), \
+	INTEL_VGA_DEVICE(0x4906, info), \
+	INTEL_VGA_DEVICE(0x4907, info), \
+	INTEL_VGA_DEVICE(0x4908, info)
 
 #endif /* _I915_PCIIDS_H */
diff --git a/include/kunit/test.h b/include/kunit/test.h
index 9197da792336..db1b0ae666c4 100644
--- a/include/kunit/test.h
+++ b/include/kunit/test.h
@@ -252,13 +252,14 @@ static inline int kunit_run_all_tests(void)
 }
 #endif /* IS_BUILTIN(CONFIG_KUNIT) */
 
+#ifdef MODULE
 /**
- * kunit_test_suites() - used to register one or more &struct kunit_suite
- *			 with KUnit.
+ * kunit_test_suites_for_module() - used to register one or more
+ *			 &struct kunit_suite with KUnit.
  *
- * @suites_list...: a statically allocated list of &struct kunit_suite.
+ * @__suites: a statically allocated list of &struct kunit_suite.
  *
- * Registers @suites_list with the test framework. See &struct kunit_suite for
+ * Registers @__suites with the test framework. See &struct kunit_suite for
  * more information.
  *
  * If a test suite is built-in, module_init() gets translated into
@@ -267,7 +268,6 @@ static inline int kunit_run_all_tests(void)
  * module_{init|exit} functions for the builtin case when registering
  * suites via kunit_test_suites() below.
  */
-#ifdef MODULE
 #define kunit_test_suites_for_module(__suites)				\
 	static int __init kunit_test_suites_init(void)			\
 	{								\
@@ -294,7 +294,7 @@ static inline int kunit_run_all_tests(void)
  * kunit_test_suites() - used to register one or more &struct kunit_suite
  *			 with KUnit.
  *
- * @suites: a statically allocated list of &struct kunit_suite.
+ * @__suites: a statically allocated list of &struct kunit_suite.
  *
  * Registers @suites with the test framework. See &struct kunit_suite for
  * more information.
@@ -308,10 +308,10 @@ static inline int kunit_run_all_tests(void)
  * module.
  *
  */
-#define kunit_test_suites(...)						\
+#define kunit_test_suites(__suites...)						\
 	__kunit_test_suites(__UNIQUE_ID(array),				\
 			    __UNIQUE_ID(suites),			\
-			    __VA_ARGS__)
+			    ##__suites)
 
 #define kunit_test_suite(suite)	kunit_test_suites(&suite)
 
diff --git a/include/linux/blk-mq.h b/include/linux/blk-mq.h
index b23eeca4d677..794b2a33a2c3 100644
--- a/include/linux/blk-mq.h
+++ b/include/linux/blk-mq.h
@@ -235,6 +235,8 @@ enum hctx_type {
  * @flags:	   Zero or more BLK_MQ_F_* flags.
  * @driver_data:   Pointer to data owned by the block driver that created this
  *		   tag set.
+ * @active_queues_shared_sbitmap:
+ * 		   number of active request queues per tag set.
  * @__bitmap_tags: A shared tags sbitmap, used over all hctx's
  * @__breserved_tags:
  *		   A shared reserved tags sbitmap, used over all hctx's
diff --git a/include/linux/can/skb.h b/include/linux/can/skb.h
index 900b9f4e0605..fc61cf4eff1c 100644
--- a/include/linux/can/skb.h
+++ b/include/linux/can/skb.h
@@ -61,21 +61,17 @@ static inline void can_skb_set_owner(struct sk_buff *skb, struct sock *sk)
  */
 static inline struct sk_buff *can_create_echo_skb(struct sk_buff *skb)
 {
-	if (skb_shared(skb)) {
-		struct sk_buff *nskb = skb_clone(skb, GFP_ATOMIC);
+	struct sk_buff *nskb;
 
-		if (likely(nskb)) {
-			can_skb_set_owner(nskb, skb->sk);
-			consume_skb(skb);
-			return nskb;
-		} else {
-			kfree_skb(skb);
-			return NULL;
-		}
+	nskb = skb_clone(skb, GFP_ATOMIC);
+	if (unlikely(!nskb)) {
+		kfree_skb(skb);
+		return NULL;
 	}
 
-	/* we can assume to have an unshared skb with proper owner */
-	return skb;
+	can_skb_set_owner(nskb, skb->sk);
+	consume_skb(skb);
+	return nskb;
 }
 
 #endif /* !_CAN_SKB_H */
diff --git a/include/linux/io_uring.h b/include/linux/io_uring.h
index 868364cea3b7..35b2d845704d 100644
--- a/include/linux/io_uring.h
+++ b/include/linux/io_uring.h
@@ -30,7 +30,8 @@ struct io_uring_task {
 	struct percpu_counter	inflight;
 	struct io_identity	__identity;
 	struct io_identity	*identity;
-	bool			in_idle;
+	atomic_t		in_idle;
+	bool			sqpoll;
 };
 
 #if defined(CONFIG_IO_URING)
diff --git a/include/linux/iomap.h b/include/linux/iomap.h
index 172b3397a1a3..5bd3cac4df9c 100644
--- a/include/linux/iomap.h
+++ b/include/linux/iomap.h
@@ -221,7 +221,7 @@ struct iomap_writeback_ops {
 	 * Optional, allows the file system to discard state on a page where
 	 * we failed to submit any I/O.
 	 */
-	void (*discard_page)(struct page *page);
+	void (*discard_page)(struct page *page, loff_t fileoff);
 };
 
 struct iomap_writepage_ctx {
diff --git a/include/linux/mm.h b/include/linux/mm.h
index ef360fe70aaf..db6ae4d3fb4e 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -2759,6 +2759,15 @@ static inline vm_fault_t vmf_insert_page(struct vm_area_struct *vma,
 	return VM_FAULT_NOPAGE;
 }
 
+#ifndef io_remap_pfn_range
+static inline int io_remap_pfn_range(struct vm_area_struct *vma,
+				     unsigned long addr, unsigned long pfn,
+				     unsigned long size, pgprot_t prot)
+{
+	return remap_pfn_range(vma, addr, pfn, size, pgprot_decrypted(prot));
+}
+#endif
+
 static inline vm_fault_t vmf_error(int err)
 {
 	if (err == -ENOMEM)
diff --git a/include/linux/netfilter/nfnetlink.h b/include/linux/netfilter/nfnetlink.h
index 89016d08f6a2..f6267e2883f2 100644
--- a/include/linux/netfilter/nfnetlink.h
+++ b/include/linux/netfilter/nfnetlink.h
@@ -24,6 +24,12 @@ struct nfnl_callback {
 	const u_int16_t attr_count;		/* number of nlattr's */
 };
 
+enum nfnl_abort_action {
+	NFNL_ABORT_NONE		= 0,
+	NFNL_ABORT_AUTOLOAD,
+	NFNL_ABORT_VALIDATE,
+};
+
 struct nfnetlink_subsystem {
 	const char *name;
 	__u8 subsys_id;			/* nfnetlink subsystem ID */
@@ -31,7 +37,8 @@ struct nfnetlink_subsystem {
 	const struct nfnl_callback *cb;	/* callback for individual types */
 	struct module *owner;
 	int (*commit)(struct net *net, struct sk_buff *skb);
-	int (*abort)(struct net *net, struct sk_buff *skb, bool autoload);
+	int (*abort)(struct net *net, struct sk_buff *skb,
+		     enum nfnl_abort_action action);
 	void (*cleanup)(struct net *net);
 	bool (*valid_genid)(struct net *net, u32 genid);
 };
diff --git a/include/linux/netfilter_ipv4.h b/include/linux/netfilter_ipv4.h
index 082e2c41b7ff..5b70ca868bb1 100644
--- a/include/linux/netfilter_ipv4.h
+++ b/include/linux/netfilter_ipv4.h
@@ -16,7 +16,7 @@ struct ip_rt_info {
 	u_int32_t mark;
 };
 
-int ip_route_me_harder(struct net *net, struct sk_buff *skb, unsigned addr_type);
+int ip_route_me_harder(struct net *net, struct sock *sk, struct sk_buff *skb, unsigned addr_type);
 
 struct nf_queue_entry;
 
diff --git a/include/linux/netfilter_ipv6.h b/include/linux/netfilter_ipv6.h
index 9b67394471e1..48314ade1506 100644
--- a/include/linux/netfilter_ipv6.h
+++ b/include/linux/netfilter_ipv6.h
@@ -42,7 +42,7 @@ struct nf_ipv6_ops {
 #if IS_MODULE(CONFIG_IPV6)
 	int (*chk_addr)(struct net *net, const struct in6_addr *addr,
 			const struct net_device *dev, int strict);
-	int (*route_me_harder)(struct net *net, struct sk_buff *skb);
+	int (*route_me_harder)(struct net *net, struct sock *sk, struct sk_buff *skb);
 	int (*dev_get_saddr)(struct net *net, const struct net_device *dev,
 		       const struct in6_addr *daddr, unsigned int srcprefs,
 		       struct in6_addr *saddr);
@@ -143,9 +143,9 @@ static inline int nf_br_ip6_fragment(struct net *net, struct sock *sk,
 #endif
 }
 
-int ip6_route_me_harder(struct net *net, struct sk_buff *skb);
+int ip6_route_me_harder(struct net *net, struct sock *sk, struct sk_buff *skb);
 
-static inline int nf_ip6_route_me_harder(struct net *net, struct sk_buff *skb)
+static inline int nf_ip6_route_me_harder(struct net *net, struct sock *sk, struct sk_buff *skb)
 {
 #if IS_MODULE(CONFIG_IPV6)
 	const struct nf_ipv6_ops *v6_ops = nf_get_ipv6_ops();
@@ -153,9 +153,9 @@ static inline int nf_ip6_route_me_harder(struct net *net, struct sk_buff *skb)
 	if (!v6_ops)
 		return -EHOSTUNREACH;
 
-	return v6_ops->route_me_harder(net, skb);
+	return v6_ops->route_me_harder(net, sk, skb);
 #elif IS_BUILTIN(CONFIG_IPV6)
-	return ip6_route_me_harder(net, skb);
+	return ip6_route_me_harder(net, sk, skb);
 #else
 	return -EHOSTUNREACH;
 #endif
diff --git a/include/linux/pagemap.h b/include/linux/pagemap.h
index c77b7c31b2e4..e1e19c1f9ec9 100644
--- a/include/linux/pagemap.h
+++ b/include/linux/pagemap.h
@@ -344,9 +344,9 @@ static inline struct page *find_get_page_flags(struct address_space *mapping,
 /**
  * find_lock_page - locate, pin and lock a pagecache page
  * @mapping: the address_space to search
- * @offset: the page index
+ * @index: the page index
  *
- * Looks up the page cache entry at @mapping & @offset.  If there is a
+ * Looks up the page cache entry at @mapping & @index.  If there is a
  * page cache page, it is returned locked and with an increased
  * refcount.
  *
@@ -363,9 +363,9 @@ static inline struct page *find_lock_page(struct address_space *mapping,
 /**
  * find_lock_head - Locate, pin and lock a pagecache page.
  * @mapping: The address_space to search.
- * @offset: The page index.
+ * @index: The page index.
  *
- * Looks up the page cache entry at @mapping & @offset.  If there is a
+ * Looks up the page cache entry at @mapping & @index.  If there is a
  * page cache page, its head page is returned locked and with an increased
  * refcount.
  *
diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
index 38c33eabea89..71125a4676c4 100644
--- a/include/linux/pgtable.h
+++ b/include/linux/pgtable.h
@@ -1427,10 +1427,6 @@ typedef unsigned int pgtbl_mod_mask;
 
 #endif /* !__ASSEMBLY__ */
 
-#ifndef io_remap_pfn_range
-#define io_remap_pfn_range remap_pfn_range
-#endif
-
 #ifndef has_transparent_hugepage
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 #define has_transparent_hugepage() 1
diff --git a/include/linux/phy.h b/include/linux/phy.h
index eb3cb1a98b45..56563e5e0dc7 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -147,16 +147,8 @@ typedef enum {
 	PHY_INTERFACE_MODE_MAX,
 } phy_interface_t;
 
-/**
+/*
  * phy_supported_speeds - return all speeds currently supported by a PHY device
- * @phy: The PHY device to return supported speeds of.
- * @speeds: buffer to store supported speeds in.
- * @size: size of speeds buffer.
- *
- * Description: Returns the number of supported speeds, and fills
- * the speeds buffer with the supported speeds. If speeds buffer is
- * too small to contain all currently supported speeds, will return as
- * many speeds as can fit.
  */
 unsigned int phy_supported_speeds(struct phy_device *phy,
 				      unsigned int *speeds,
@@ -1022,14 +1014,9 @@ static inline int __phy_modify_changed(struct phy_device *phydev, u32 regnum,
 					regnum, mask, set);
 }
 
-/**
+/*
  * phy_read_mmd - Convenience function for reading a register
  * from an MMD on a given PHY.
- * @phydev: The phy_device struct
- * @devad: The MMD to read from
- * @regnum: The register on the MMD to read
- *
- * Same rules as for phy_read();
  */
 int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
 
@@ -1064,38 +1051,21 @@ int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
 	__ret; \
 })
 
-/**
+/*
  * __phy_read_mmd - Convenience function for reading a register
  * from an MMD on a given PHY.
- * @phydev: The phy_device struct
- * @devad: The MMD to read from
- * @regnum: The register on the MMD to read
- *
- * Same rules as for __phy_read();
  */
 int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
 
-/**
+/*
  * phy_write_mmd - Convenience function for writing a register
  * on an MMD on a given PHY.
- * @phydev: The phy_device struct
- * @devad: The MMD to write to
- * @regnum: The register on the MMD to read
- * @val: value to write to @regnum
- *
- * Same rules as for phy_write();
  */
 int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
 
-/**
+/*
  * __phy_write_mmd - Convenience function for writing a register
  * on an MMD on a given PHY.
- * @phydev: The phy_device struct
- * @devad: The MMD to write to
- * @regnum: The register on the MMD to read
- * @val: value to write to @regnum
- *
- * Same rules as for __phy_write();
  */
 int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
 
diff --git a/include/linux/pm_runtime.h b/include/linux/pm_runtime.h
index 18b02dcc168e..4b708f4e8eed 100644
--- a/include/linux/pm_runtime.h
+++ b/include/linux/pm_runtime.h
@@ -54,11 +54,10 @@ extern u64 pm_runtime_autosuspend_expiration(struct device *dev);
 extern void pm_runtime_update_max_time_suspended(struct device *dev,
 						 s64 delta_ns);
 extern void pm_runtime_set_memalloc_noio(struct device *dev, bool enable);
-extern void pm_runtime_clean_up_links(struct device *dev);
 extern void pm_runtime_get_suppliers(struct device *dev);
 extern void pm_runtime_put_suppliers(struct device *dev);
 extern void pm_runtime_new_link(struct device *dev);
-extern void pm_runtime_drop_link(struct device *dev);
+extern void pm_runtime_drop_link(struct device_link *link);
 
 /**
  * pm_runtime_get_if_in_use - Conditionally bump up runtime PM usage counter.
@@ -276,11 +275,10 @@ static inline u64 pm_runtime_autosuspend_expiration(
 				struct device *dev) { return 0; }
 static inline void pm_runtime_set_memalloc_noio(struct device *dev,
 						bool enable){}
-static inline void pm_runtime_clean_up_links(struct device *dev) {}
 static inline void pm_runtime_get_suppliers(struct device *dev) {}
 static inline void pm_runtime_put_suppliers(struct device *dev) {}
 static inline void pm_runtime_new_link(struct device *dev) {}
-static inline void pm_runtime_drop_link(struct device *dev) {}
+static inline void pm_runtime_drop_link(struct device_link *link) {}
 
 #endif /* !CONFIG_PM */
 
diff --git a/include/linux/refcount.h b/include/linux/refcount.h
index 7fabb1af18e0..497990c69b0b 100644
--- a/include/linux/refcount.h
+++ b/include/linux/refcount.h
@@ -147,24 +147,6 @@ static inline unsigned int refcount_read(const refcount_t *r)
 	return atomic_read(&r->refs);
 }
 
-/**
- * refcount_add_not_zero - add a value to a refcount unless it is 0
- * @i: the value to add to the refcount
- * @r: the refcount
- *
- * Will saturate at REFCOUNT_SATURATED and WARN.
- *
- * Provides no memory ordering, it is assumed the caller has guaranteed the
- * object memory to be stable (RCU, etc.). It does provide a control dependency
- * and thereby orders future stores. See the comment on top.
- *
- * Use of this function is not recommended for the normal reference counting
- * use case in which references are taken and released one at a time.  In these
- * cases, refcount_inc(), or one of its variants, should instead be used to
- * increment a reference count.
- *
- * Return: false if the passed refcount is 0, true otherwise
- */
 static inline __must_check bool __refcount_add_not_zero(int i, refcount_t *r, int *oldp)
 {
 	int old = refcount_read(r);
@@ -183,17 +165,12 @@ static inline __must_check bool __refcount_add_not_zero(int i, refcount_t *r, in
 	return old;
 }
 
-static inline __must_check bool refcount_add_not_zero(int i, refcount_t *r)
-{
-	return __refcount_add_not_zero(i, r, NULL);
-}
-
 /**
- * refcount_add - add a value to a refcount
+ * refcount_add_not_zero - add a value to a refcount unless it is 0
  * @i: the value to add to the refcount
  * @r: the refcount
  *
- * Similar to atomic_add(), but will saturate at REFCOUNT_SATURATED and WARN.
+ * Will saturate at REFCOUNT_SATURATED and WARN.
  *
  * Provides no memory ordering, it is assumed the caller has guaranteed the
  * object memory to be stable (RCU, etc.). It does provide a control dependency
@@ -203,7 +180,14 @@ static inline __must_check bool refcount_add_not_zero(int i, refcount_t *r)
  * use case in which references are taken and released one at a time.  In these
  * cases, refcount_inc(), or one of its variants, should instead be used to
  * increment a reference count.
+ *
+ * Return: false if the passed refcount is 0, true otherwise
  */
+static inline __must_check bool refcount_add_not_zero(int i, refcount_t *r)
+{
+	return __refcount_add_not_zero(i, r, NULL);
+}
+
 static inline void __refcount_add(int i, refcount_t *r, int *oldp)
 {
 	int old = atomic_fetch_add_relaxed(i, &r->refs);
@@ -217,11 +201,32 @@ static inline void __refcount_add(int i, refcount_t *r, int *oldp)
 		refcount_warn_saturate(r, REFCOUNT_ADD_OVF);
 }
 
+/**
+ * refcount_add - add a value to a refcount
+ * @i: the value to add to the refcount
+ * @r: the refcount
+ *
+ * Similar to atomic_add(), but will saturate at REFCOUNT_SATURATED and WARN.
+ *
+ * Provides no memory ordering, it is assumed the caller has guaranteed the
+ * object memory to be stable (RCU, etc.). It does provide a control dependency
+ * and thereby orders future stores. See the comment on top.
+ *
+ * Use of this function is not recommended for the normal reference counting
+ * use case in which references are taken and released one at a time.  In these
+ * cases, refcount_inc(), or one of its variants, should instead be used to
+ * increment a reference count.
+ */
 static inline void refcount_add(int i, refcount_t *r)
 {
 	__refcount_add(i, r, NULL);
 }
 
+static inline __must_check bool __refcount_inc_not_zero(refcount_t *r, int *oldp)
+{
+	return __refcount_add_not_zero(1, r, oldp);
+}
+
 /**
  * refcount_inc_not_zero - increment a refcount unless it is 0
  * @r: the refcount to increment
@@ -235,14 +240,14 @@ static inline void refcount_add(int i, refcount_t *r)
  *
  * Return: true if the increment was successful, false otherwise
  */
-static inline __must_check bool __refcount_inc_not_zero(refcount_t *r, int *oldp)
+static inline __must_check bool refcount_inc_not_zero(refcount_t *r)
 {
-	return __refcount_add_not_zero(1, r, oldp);
+	return __refcount_inc_not_zero(r, NULL);
 }
 
-static inline __must_check bool refcount_inc_not_zero(refcount_t *r)
+static inline void __refcount_inc(refcount_t *r, int *oldp)
 {
-	return __refcount_inc_not_zero(r, NULL);
+	__refcount_add(1, r, oldp);
 }
 
 /**
@@ -257,14 +262,27 @@ static inline __must_check bool refcount_inc_not_zero(refcount_t *r)
  * Will WARN if the refcount is 0, as this represents a possible use-after-free
  * condition.
  */
-static inline void __refcount_inc(refcount_t *r, int *oldp)
+static inline void refcount_inc(refcount_t *r)
 {
-	__refcount_add(1, r, oldp);
+	__refcount_inc(r, NULL);
 }
 
-static inline void refcount_inc(refcount_t *r)
+static inline __must_check bool __refcount_sub_and_test(int i, refcount_t *r, int *oldp)
 {
-	__refcount_inc(r, NULL);
+	int old = atomic_fetch_sub_release(i, &r->refs);
+
+	if (oldp)
+		*oldp = old;
+
+	if (old == i) {
+		smp_acquire__after_ctrl_dep();
+		return true;
+	}
+
+	if (unlikely(old < 0 || old - i < 0))
+		refcount_warn_saturate(r, REFCOUNT_SUB_UAF);
+
+	return false;
 }
 
 /**
@@ -287,27 +305,14 @@ static inline void refcount_inc(refcount_t *r)
  *
  * Return: true if the resulting refcount is 0, false otherwise
  */
-static inline __must_check bool __refcount_sub_and_test(int i, refcount_t *r, int *oldp)
+static inline __must_check bool refcount_sub_and_test(int i, refcount_t *r)
 {
-	int old = atomic_fetch_sub_release(i, &r->refs);
-
-	if (oldp)
-		*oldp = old;
-
-	if (old == i) {
-		smp_acquire__after_ctrl_dep();
-		return true;
-	}
-
-	if (unlikely(old < 0 || old - i < 0))
-		refcount_warn_saturate(r, REFCOUNT_SUB_UAF);
-
-	return false;
+	return __refcount_sub_and_test(i, r, NULL);
 }
 
-static inline __must_check bool refcount_sub_and_test(int i, refcount_t *r)
+static inline __must_check bool __refcount_dec_and_test(refcount_t *r, int *oldp)
 {
-	return __refcount_sub_and_test(i, r, NULL);
+	return __refcount_sub_and_test(1, r, oldp);
 }
 
 /**
@@ -323,26 +328,11 @@ static inline __must_check bool refcount_sub_and_test(int i, refcount_t *r)
  *
  * Return: true if the resulting refcount is 0, false otherwise
  */
-static inline __must_check bool __refcount_dec_and_test(refcount_t *r, int *oldp)
-{
-	return __refcount_sub_and_test(1, r, oldp);
-}
-
 static inline __must_check bool refcount_dec_and_test(refcount_t *r)
 {
 	return __refcount_dec_and_test(r, NULL);
 }
 
-/**
- * refcount_dec - decrement a refcount
- * @r: the refcount
- *
- * Similar to atomic_dec(), it will WARN on underflow and fail to decrement
- * when saturated at REFCOUNT_SATURATED.
- *
- * Provides release memory ordering, such that prior loads and stores are done
- * before.
- */
 static inline void __refcount_dec(refcount_t *r, int *oldp)
 {
 	int old = atomic_fetch_sub_release(1, &r->refs);
@@ -354,6 +344,16 @@ static inline void __refcount_dec(refcount_t *r, int *oldp)
 		refcount_warn_saturate(r, REFCOUNT_DEC_LEAK);
 }
 
+/**
+ * refcount_dec - decrement a refcount
+ * @r: the refcount
+ *
+ * Similar to atomic_dec(), it will WARN on underflow and fail to decrement
+ * when saturated at REFCOUNT_SATURATED.
+ *
+ * Provides release memory ordering, such that prior loads and stores are done
+ * before.
+ */
 static inline void refcount_dec(refcount_t *r)
 {
 	__refcount_dec(r, NULL);
diff --git a/include/linux/seq_file.h b/include/linux/seq_file.h
index 813614d4b71f..b83b3ae3c877 100644
--- a/include/linux/seq_file.h
+++ b/include/linux/seq_file.h
@@ -107,6 +107,7 @@ void seq_pad(struct seq_file *m, char c);
 char *mangle_path(char *s, const char *p, const char *esc);
 int seq_open(struct file *, const struct seq_operations *);
 ssize_t seq_read(struct file *, char __user *, size_t, loff_t *);
+ssize_t seq_read_iter(struct kiocb *iocb, struct iov_iter *iter);
 loff_t seq_lseek(struct file *, loff_t, int);
 int seq_release(struct inode *, struct file *);
 int seq_write(struct seq_file *seq, const void *data, size_t len);
diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index 661edfc8722e..d5ab8d99739f 100644
--- a/include/net/cfg80211.h
+++ b/include/net/cfg80211.h
@@ -1444,7 +1444,7 @@ int cfg80211_check_station_change(struct wiphy *wiphy,
 				  enum cfg80211_station_type statype);
 
 /**
- * enum station_info_rate_flags - bitrate info flags
+ * enum rate_info_flags - bitrate info flags
  *
  * Used by the driver to indicate the specific rate transmission
  * type for 802.11n transmissions.
@@ -1517,7 +1517,7 @@ struct rate_info {
 };
 
 /**
- * enum station_info_rate_flags - bitrate info flags
+ * enum bss_param_flags - bitrate info flags
  *
  * Used by the driver to indicate the specific rate transmission
  * type for 802.11n transmissions.
@@ -6467,7 +6467,8 @@ void cfg80211_ibss_joined(struct net_device *dev, const u8 *bssid,
 			  struct ieee80211_channel *channel, gfp_t gfp);
 
 /**
- * cfg80211_notify_new_candidate - notify cfg80211 of a new mesh peer candidate
+ * cfg80211_notify_new_peer_candidate - notify cfg80211 of a new mesh peer
+ * 					candidate
  *
  * @dev: network device
  * @macaddr: the MAC address of the new candidate
@@ -7606,7 +7607,7 @@ u32 cfg80211_calculate_bitrate(struct rate_info *rate);
 void cfg80211_unregister_wdev(struct wireless_dev *wdev);
 
 /**
- * struct cfg80211_ft_event - FT Information Elements
+ * struct cfg80211_ft_event_params - FT Information Elements
  * @ies: FT IEs
  * @ies_len: length of the FT IE in bytes
  * @target_ap: target AP's MAC address
diff --git a/include/net/mac80211.h b/include/net/mac80211.h
index e8e295dae744..dcdba96814a2 100644
--- a/include/net/mac80211.h
+++ b/include/net/mac80211.h
@@ -3311,7 +3311,7 @@ enum ieee80211_roc_type {
 };
 
 /**
- * enum ieee80211_reconfig_complete_type - reconfig type
+ * enum ieee80211_reconfig_type - reconfig type
  *
  * This enum is used by the reconfig_complete() callback to indicate what
  * reconfiguration type was completed.
@@ -6334,7 +6334,8 @@ bool ieee80211_tx_prepare_skb(struct ieee80211_hw *hw,
 			      int band, struct ieee80211_sta **sta);
 
 /**
- * Sanity-check and parse the radiotap header of injected frames
+ * ieee80211_parse_tx_radiotap - Sanity-check and parse the radiotap header
+ *				 of injected frames
  * @skb: packet injected by userspace
  * @dev: the &struct device of this 802.11 device
  */
@@ -6389,7 +6390,7 @@ int ieee80211_parse_p2p_noa(const struct ieee80211_p2p_noa_attr *attr,
 void ieee80211_update_p2p_noa(struct ieee80211_noa_data *data, u32 tsf);
 
 /**
- * ieee80211_tdls_oper - request userspace to perform a TDLS operation
+ * ieee80211_tdls_oper_request - request userspace to perform a TDLS operation
  * @vif: virtual interface
  * @peer: the peer's destination address
  * @oper: the requested TDLS operation
diff --git a/include/sound/control.h b/include/sound/control.h
index e128cff10dfa..77d9fa10812d 100644
--- a/include/sound/control.h
+++ b/include/sound/control.h
@@ -42,7 +42,7 @@ struct snd_kcontrol_new {
 	snd_ctl_elem_iface_t iface;	/* interface identifier */
 	unsigned int device;		/* device/client number */
 	unsigned int subdevice;		/* subdevice (substream) number */
-	const unsigned char *name;	/* ASCII name of item */
+	const char *name;		/* ASCII name of item */
 	unsigned int index;		/* index of item */
 	unsigned int access;		/* access rights */
 	unsigned int count;		/* count of same elements */
diff --git a/include/sound/core.h b/include/sound/core.h
index 381a010a1bd4..0462c577d7a3 100644
--- a/include/sound/core.h
+++ b/include/sound/core.h
@@ -332,7 +332,8 @@ void __snd_printk(unsigned int level, const char *file, int line,
 #define snd_BUG()		WARN(1, "BUG?\n")
 
 /**
- * Suppress high rates of output when CONFIG_SND_DEBUG is enabled.
+ * snd_printd_ratelimit - Suppress high rates of output when
+ * 			  CONFIG_SND_DEBUG is enabled.
  */
 #define snd_printd_ratelimit() printk_ratelimit()
 
diff --git a/include/sound/pcm.h b/include/sound/pcm.h
index 2ba5df2c9e23..2336bf9243e1 100644
--- a/include/sound/pcm.h
+++ b/include/sound/pcm.h
@@ -1284,8 +1284,8 @@ snd_pcm_sgbuf_get_ptr(struct snd_pcm_substream *substream, unsigned int ofs)
 }
 
 /**
- * snd_pcm_sgbuf_chunk_size - Compute the max size that fits within the contig.
- * page from the given size
+ * snd_pcm_sgbuf_get_chunk_size - Compute the max size that fits within the
+ * contig. page from the given size
  * @substream: PCM substream
  * @ofs: byte offset
  * @size: byte size to examine
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index c5ff2b275fcd..7fb9c09ee93f 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -667,7 +667,7 @@ struct drm_amdgpu_cs_chunk_data {
 	};
 };
 
-/**
+/*
  *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
  *
  */
@@ -724,6 +724,8 @@ struct drm_amdgpu_cs_chunk_data {
 	#define AMDGPU_INFO_FW_TA		0x13
 	/* Subquery id: Query DMCUB firmware version */
 	#define AMDGPU_INFO_FW_DMCUB		0x14
+	/* Subquery id: Query TOC firmware version */
+	#define AMDGPU_INFO_FW_TOC		0x15
 
 /* number of bytes moved for TTM migration */
 #define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
@@ -946,6 +948,7 @@ struct drm_amdgpu_info_firmware {
 #define AMDGPU_VRAM_TYPE_DDR3  7
 #define AMDGPU_VRAM_TYPE_DDR4  8
 #define AMDGPU_VRAM_TYPE_GDDR6 9
+#define AMDGPU_VRAM_TYPE_DDR5  10
 
 struct drm_amdgpu_info_device {
 	/** PCI Device ID */
@@ -1083,6 +1086,7 @@ struct drm_amdgpu_info_vce_clock_table {
 #define AMDGPU_FAMILY_AI			141 /* Vega10 */
 #define AMDGPU_FAMILY_RV			142 /* Raven */
 #define AMDGPU_FAMILY_NV			143 /* Navi10 */
+#define AMDGPU_FAMILY_VGH			144 /* Van Gogh */
 
 #if defined(__cplusplus)
 }
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 9f7e19c9416c..ca48ed0e6bc1 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -1095,6 +1095,121 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
  */
 #define AMLOGIC_FBC_OPTION_MEM_SAVING		(1ULL << 0)
 
+/*
+ * AMD modifiers
+ *
+ * Memory layout:
+ *
+ * without DCC:
+ *   - main surface
+ *
+ * with DCC & without DCC_RETILE:
+ *   - main surface in plane 0
+ *   - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
+ *
+ * with DCC & DCC_RETILE:
+ *   - main surface in plane 0
+ *   - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
+ *   - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
+ *
+ * For multi-plane formats the above surfaces get merged into one plane for
+ * each format plane, based on the required alignment only.
+ */
+#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
+
+#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
+
+/* Reserve 0 for GFX8 and older */
+#define AMD_FMT_MOD_TILE_VER_GFX9 1
+#define AMD_FMT_MOD_TILE_VER_GFX10 2
+#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
+
+/*
+ * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
+ * version.
+ */
+#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
+
+/*
+ * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
+ * GFX9 as canonical version.
+ */
+#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
+#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
+#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
+#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
+
+#define AMD_FMT_MOD_DCC_BLOCK_64B 0
+#define AMD_FMT_MOD_DCC_BLOCK_128B 1
+#define AMD_FMT_MOD_DCC_BLOCK_256B 2
+
+#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
+#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
+#define AMD_FMT_MOD_TILE_SHIFT 8
+#define AMD_FMT_MOD_TILE_MASK 0x1F
+
+/* Whether DCC compression is enabled. */
+#define AMD_FMT_MOD_DCC_SHIFT 13
+#define AMD_FMT_MOD_DCC_MASK 0x1
+
+/*
+ * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
+ * one which is not-aligned.
+ */
+#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
+#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
+
+/* Only set if DCC_RETILE = false */
+#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
+#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
+
+#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
+#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
+#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
+#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
+#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
+#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1
+
+/*
+ * DCC supports embedding some clear colors directly in the DCC surface.
+ * However, on older GPUs the rendering HW ignores the embedded clear color
+ * and prefers the driver provided color. This necessitates doing a fastclear
+ * eliminate operation before a process transfers control.
+ *
+ * If this bit is set that means the fastclear eliminate is not needed for these
+ * embeddable colors.
+ */
+#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19
+#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
+
+/*
+ * The below fields are for accounting for per GPU differences. These are only
+ * relevant for GFX9 and later and if the tile field is *_X/_T.
+ *
+ * PIPE_XOR_BITS = always needed
+ * BANK_XOR_BITS = only for TILE_VER_GFX9
+ * PACKERS = only for TILE_VER_GFX10_RBPLUS
+ * RB = only for TILE_VER_GFX9 & DCC
+ * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
+ */
+#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20
+#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
+#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23
+#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
+#define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */
+#define AMD_FMT_MOD_PACKERS_MASK 0x7
+#define AMD_FMT_MOD_RB_SHIFT 29
+#define AMD_FMT_MOD_RB_MASK 0x7
+#define AMD_FMT_MOD_PIPE_SHIFT 32
+#define AMD_FMT_MOD_PIPE_MASK 0x7
+
+#define AMD_FMT_MOD_SET(field, value) \
+	((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
+#define AMD_FMT_MOD_GET(field, value) \
+	(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
+#define AMD_FMT_MOD_CLEAR(field) \
+	(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/include/uapi/linux/icmpv6.h b/include/uapi/linux/icmpv6.h
index c1661febc2dc..0564fd7ccde4 100644
--- a/include/uapi/linux/icmpv6.h
+++ b/include/uapi/linux/icmpv6.h
@@ -138,6 +138,7 @@ struct icmp6hdr {
 #define ICMPV6_HDR_FIELD		0
 #define ICMPV6_UNK_NEXTHDR		1
 #define ICMPV6_UNK_OPTION		2
+#define ICMPV6_HDR_INCOMP		3
 
 /*
  *	constants for (set|get)sockopt
diff --git a/include/uapi/sound/compress_offload.h b/include/uapi/sound/compress_offload.h
index 7184265c0b0d..9555f31c8425 100644
--- a/include/uapi/sound/compress_offload.h
+++ b/include/uapi/sound/compress_offload.h
@@ -144,7 +144,7 @@ struct snd_compr_metadata {
 	 __u32 value[8];
 } __attribute__((packed, aligned(4)));
 
-/**
+/*
  * compress path ioctl definitions
  * SNDRV_COMPRESS_GET_CAPS: Query capability of DSP
  * SNDRV_COMPRESS_GET_CODEC_CAPS: Query capability of a codec
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 06b0b57e996c..d1b3889f74d8 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -484,9 +484,6 @@ int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
 
 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
-enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
-int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
-bool ipu_pixelformat_is_planar(u32 pixelformat);
 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
 			    bool hflip, bool vflip);
 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
diff --git a/kernel/entry/common.c b/kernel/entry/common.c
index 2b8366693d5c..e9e2df3f3f9e 100644
--- a/kernel/entry/common.c
+++ b/kernel/entry/common.c
@@ -337,10 +337,10 @@ noinstr irqentry_state_t irqentry_enter(struct pt_regs *regs)
 	 * already contains a warning when RCU is not watching, so no point
 	 * in having another one here.
 	 */
+	lockdep_hardirqs_off(CALLER_ADDR0);
 	instrumentation_begin();
 	rcu_irq_enter_check_tick();
-	/* Use the combo lockdep/tracing function */
-	trace_hardirqs_off();
+	trace_hardirqs_off_finish();
 	instrumentation_end();
 
 	return ret;
diff --git a/kernel/events/core.c b/kernel/events/core.c
index da467e1dd49a..5a29ab09e72d 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -10085,6 +10085,7 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr,
 			if (token == IF_SRC_FILE || token == IF_SRC_FILEADDR) {
 				int fpos = token == IF_SRC_FILE ? 2 : 1;
 
+				kfree(filename);
 				filename = match_strdup(&args[fpos]);
 				if (!filename) {
 					ret = -ENOMEM;
@@ -10131,16 +10132,13 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr,
 				 */
 				ret = -EOPNOTSUPP;
 				if (!event->ctx->task)
-					goto fail_free_name;
+					goto fail;
 
 				/* look up the path and grab its inode */
 				ret = kern_path(filename, LOOKUP_FOLLOW,
 						&filter->path);
 				if (ret)
-					goto fail_free_name;
-
-				kfree(filename);
-				filename = NULL;
+					goto fail;
 
 				ret = -EINVAL;
 				if (!filter->path.dentry ||
@@ -10160,13 +10158,13 @@ perf_event_parse_addr_filter(struct perf_event *event, char *fstr,
 	if (state != IF_STATE_ACTION)
 		goto fail;
 
+	kfree(filename);
 	kfree(orig);
 
 	return 0;
 
-fail_free_name:
-	kfree(filename);
 fail:
+	kfree(filename);
 	free_filters_list(filters);
 	kfree(orig);
 
diff --git a/kernel/fork.c b/kernel/fork.c
index 32083db7a2a2..6d266388d380 100644
--- a/kernel/fork.c
+++ b/kernel/fork.c
@@ -2167,14 +2167,9 @@ static __latent_entropy struct task_struct *copy_process(
 	/* ok, now we should be set up.. */
 	p->pid = pid_nr(pid);
 	if (clone_flags & CLONE_THREAD) {
-		p->exit_signal = -1;
 		p->group_leader = current->group_leader;
 		p->tgid = current->tgid;
 	} else {
-		if (clone_flags & CLONE_PARENT)
-			p->exit_signal = current->group_leader->exit_signal;
-		else
-			p->exit_signal = args->exit_signal;
 		p->group_leader = p;
 		p->tgid = p->pid;
 	}
@@ -2218,9 +2213,14 @@ static __latent_entropy struct task_struct *copy_process(
 	if (clone_flags & (CLONE_PARENT|CLONE_THREAD)) {
 		p->real_parent = current->real_parent;
 		p->parent_exec_id = current->parent_exec_id;
+		if (clone_flags & CLONE_THREAD)
+			p->exit_signal = -1;
+		else
+			p->exit_signal = current->group_leader->exit_signal;
 	} else {
 		p->real_parent = current;
 		p->parent_exec_id = current->self_exec_id;
+		p->exit_signal = args->exit_signal;
 	}
 
 	klp_copy_process(p);
diff --git a/kernel/futex.c b/kernel/futex.c
index f8614ef4ff31..ac328874f6e5 100644
--- a/kernel/futex.c
+++ b/kernel/futex.c
@@ -2380,10 +2380,22 @@ retry:
 		}
 
 		/*
-		 * Since we just failed the trylock; there must be an owner.
+		 * The trylock just failed, so either there is an owner or
+		 * there is a higher priority waiter than this one.
 		 */
 		newowner = rt_mutex_owner(&pi_state->pi_mutex);
-		BUG_ON(!newowner);
+		/*
+		 * If the higher priority waiter has not yet taken over the
+		 * rtmutex then newowner is NULL. We can't return here with
+		 * that state because it's inconsistent vs. the user space
+		 * state. So drop the locks and try again. It's a valid
+		 * situation and not any different from the other retry
+		 * conditions.
+		 */
+		if (unlikely(!newowner)) {
+			err = -EAGAIN;
+			goto handle_err;
+		}
 	} else {
 		WARN_ON_ONCE(argowner != current);
 		if (oldowner == current) {
diff --git a/kernel/hung_task.c b/kernel/hung_task.c
index ce76f490126c..396ebaebea3f 100644
--- a/kernel/hung_task.c
+++ b/kernel/hung_task.c
@@ -225,8 +225,7 @@ static long hung_timeout_jiffies(unsigned long last_checked,
  * Process updating of timeout sysctl
  */
 int proc_dohung_task_timeout_secs(struct ctl_table *table, int write,
-				  void __user *buffer,
-				  size_t *lenp, loff_t *ppos)
+				  void *buffer, size_t *lenp, loff_t *ppos)
 {
 	int ret;
 
diff --git a/kernel/irq/Kconfig b/kernel/irq/Kconfig
index 10a5aff4eecc..164a031cfdb6 100644
--- a/kernel/irq/Kconfig
+++ b/kernel/irq/Kconfig
@@ -82,6 +82,7 @@ config IRQ_FASTEOI_HIERARCHY_HANDLERS
 # Generic IRQ IPI support
 config GENERIC_IRQ_IPI
 	bool
+	select IRQ_DOMAIN_HIERARCHY
 
 # Generic MSI interrupt support
 config GENERIC_MSI_IRQ
diff --git a/kernel/kprobes.c b/kernel/kprobes.c
index 8a12a25fa40d..41fdbb7953c6 100644
--- a/kernel/kprobes.c
+++ b/kernel/kprobes.c
@@ -1249,7 +1249,13 @@ __acquires(hlist_lock)
 
 	*head = &kretprobe_inst_table[hash];
 	hlist_lock = kretprobe_table_lock_ptr(hash);
-	raw_spin_lock_irqsave(hlist_lock, *flags);
+	/*
+	 * Nested is a workaround that will soon not be needed.
+	 * There's other protections that make sure the same lock
+	 * is not taken on the same CPU that lockdep is unaware of.
+	 * Differentiate when it is taken in NMI context.
+	 */
+	raw_spin_lock_irqsave_nested(hlist_lock, *flags, !!in_nmi());
 }
 NOKPROBE_SYMBOL(kretprobe_hash_lock);
 
@@ -1258,7 +1264,13 @@ static void kretprobe_table_lock(unsigned long hash,
 __acquires(hlist_lock)
 {
 	raw_spinlock_t *hlist_lock = kretprobe_table_lock_ptr(hash);
-	raw_spin_lock_irqsave(hlist_lock, *flags);
+	/*
+	 * Nested is a workaround that will soon not be needed.
+	 * There's other protections that make sure the same lock
+	 * is not taken on the same CPU that lockdep is unaware of.
+	 * Differentiate when it is taken in NMI context.
+	 */
+	raw_spin_lock_irqsave_nested(hlist_lock, *flags, !!in_nmi());
 }
 NOKPROBE_SYMBOL(kretprobe_table_lock);
 
@@ -2028,7 +2040,12 @@ static int pre_handler_kretprobe(struct kprobe *p, struct pt_regs *regs)
 
 	/* TODO: consider to only swap the RA after the last pre_handler fired */
 	hash = hash_ptr(current, KPROBE_HASH_BITS);
-	raw_spin_lock_irqsave(&rp->lock, flags);
+	/*
+	 * Nested is a workaround that will soon not be needed.
+	 * There's other protections that make sure the same lock
+	 * is not taken on the same CPU that lockdep is unaware of.
+	 */
+	raw_spin_lock_irqsave_nested(&rp->lock, flags, 1);
 	if (!hlist_empty(&rp->free_instances)) {
 		ri = hlist_entry(rp->free_instances.first,
 				struct kretprobe_instance, hlist);
@@ -2039,7 +2056,7 @@ static int pre_handler_kretprobe(struct kprobe *p, struct pt_regs *regs)
 		ri->task = current;
 
 		if (rp->entry_handler && rp->entry_handler(ri, regs)) {
-			raw_spin_lock_irqsave(&rp->lock, flags);
+			raw_spin_lock_irqsave_nested(&rp->lock, flags, 1);
 			hlist_add_head(&ri->hlist, &rp->free_instances);
 			raw_spin_unlock_irqrestore(&rp->lock, flags);
 			return 0;
diff --git a/kernel/kthread.c b/kernel/kthread.c
index e29773c82b70..933a625621b8 100644
--- a/kernel/kthread.c
+++ b/kernel/kthread.c
@@ -897,7 +897,8 @@ void kthread_delayed_work_timer_fn(struct timer_list *t)
 	/* Move the work from worker->delayed_work_list. */
 	WARN_ON_ONCE(list_empty(&work->node));
 	list_del_init(&work->node);
-	kthread_insert_work(worker, work, &worker->work_list);
+	if (!work->canceling)
+		kthread_insert_work(worker, work, &worker->work_list);
 
 	raw_spin_unlock_irqrestore(&worker->lock, flags);
 }
diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c
index c03a5775d019..d73bccde2720 100644
--- a/kernel/sched/cpufreq_schedutil.c
+++ b/kernel/sched/cpufreq_schedutil.c
@@ -102,9 +102,12 @@ static bool sugov_should_update_freq(struct sugov_policy *sg_policy, u64 time)
 static bool sugov_update_next_freq(struct sugov_policy *sg_policy, u64 time,
 				   unsigned int next_freq)
 {
-	if (sg_policy->next_freq == next_freq &&
-	    !cpufreq_driver_test_flags(CPUFREQ_NEED_UPDATE_LIMITS))
-		return false;
+	if (!sg_policy->need_freq_update) {
+		if (sg_policy->next_freq == next_freq)
+			return false;
+	} else {
+		sg_policy->need_freq_update = cpufreq_driver_test_flags(CPUFREQ_NEED_UPDATE_LIMITS);
+	}
 
 	sg_policy->next_freq = next_freq;
 	sg_policy->last_freq_update_time = time;
@@ -162,11 +165,9 @@ static unsigned int get_next_freq(struct sugov_policy *sg_policy,
 
 	freq = map_util_freq(util, freq, max);
 
-	if (freq == sg_policy->cached_raw_freq && !sg_policy->need_freq_update &&
-	    !cpufreq_driver_test_flags(CPUFREQ_NEED_UPDATE_LIMITS))
+	if (freq == sg_policy->cached_raw_freq && !sg_policy->need_freq_update)
 		return sg_policy->next_freq;
 
-	sg_policy->need_freq_update = false;
 	sg_policy->cached_raw_freq = freq;
 	return cpufreq_driver_resolve_freq(policy, freq);
 }
@@ -442,7 +443,6 @@ static void sugov_update_single(struct update_util_data *hook, u64 time,
 	struct sugov_policy *sg_policy = sg_cpu->sg_policy;
 	unsigned long util, max;
 	unsigned int next_f;
-	bool busy;
 	unsigned int cached_freq = sg_policy->cached_raw_freq;
 
 	sugov_iowait_boost(sg_cpu, time, flags);
@@ -453,9 +453,6 @@ static void sugov_update_single(struct update_util_data *hook, u64 time,
 	if (!sugov_should_update_freq(sg_policy, time))
 		return;
 
-	/* Limits may have changed, don't skip frequency update */
-	busy = !sg_policy->need_freq_update && sugov_cpu_is_busy(sg_cpu);
-
 	util = sugov_get_util(sg_cpu);
 	max = sg_cpu->max;
 	util = sugov_iowait_apply(sg_cpu, time, util, max);
@@ -464,7 +461,7 @@ static void sugov_update_single(struct update_util_data *hook, u64 time,
 	 * Do not reduce the frequency if the CPU has not been idle
 	 * recently, as the reduction is likely to be premature then.
 	 */
-	if (busy && next_f < sg_policy->next_freq) {
+	if (sugov_cpu_is_busy(sg_cpu) && next_f < sg_policy->next_freq) {
 		next_f = sg_policy->next_freq;
 
 		/* Restore cached freq as next_freq has changed */
@@ -829,9 +826,10 @@ static int sugov_start(struct cpufreq_policy *policy)
 	sg_policy->next_freq			= 0;
 	sg_policy->work_in_progress		= false;
 	sg_policy->limits_changed		= false;
-	sg_policy->need_freq_update		= false;
 	sg_policy->cached_raw_freq		= 0;
 
+	sg_policy->need_freq_update = cpufreq_driver_test_flags(CPUFREQ_NEED_UPDATE_LIMITS);
+
 	for_each_cpu(cpu, policy->cpus) {
 		struct sugov_cpu *sg_cpu = &per_cpu(sugov_cpu, cpu);
 
diff --git a/kernel/signal.c b/kernel/signal.c
index a38b3edc6851..ef8f2a28d37c 100644
--- a/kernel/signal.c
+++ b/kernel/signal.c
@@ -391,16 +391,17 @@ static bool task_participate_group_stop(struct task_struct *task)
 
 void task_join_group_stop(struct task_struct *task)
 {
+	unsigned long mask = current->jobctl & JOBCTL_STOP_SIGMASK;
+	struct signal_struct *sig = current->signal;
+
+	if (sig->group_stop_count) {
+		sig->group_stop_count++;
+		mask |= JOBCTL_STOP_CONSUME;
+	} else if (!(sig->flags & SIGNAL_STOP_STOPPED))
+		return;
+
 	/* Have the new thread join an on-going signal group stop */
-	unsigned long jobctl = current->jobctl;
-	if (jobctl & JOBCTL_STOP_PENDING) {
-		struct signal_struct *sig = current->signal;
-		unsigned long signr = jobctl & JOBCTL_STOP_SIGMASK;
-		unsigned long gstop = JOBCTL_STOP_PENDING | JOBCTL_STOP_CONSUME;
-		if (task_set_jobctl_pending(task, signr | gstop)) {
-			sig->group_stop_count++;
-		}
-	}
+	task_set_jobctl_pending(task, mask | JOBCTL_STOP_PENDING);
 }
 
 /*
diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
index 7f45fd9d5a45..dc83b3fa9fe7 100644
--- a/kernel/trace/ring_buffer.c
+++ b/kernel/trace/ring_buffer.c
@@ -438,14 +438,16 @@ enum {
 };
 /*
  * Used for which event context the event is in.
- *  NMI     = 0
- *  IRQ     = 1
- *  SOFTIRQ = 2
- *  NORMAL  = 3
+ *  TRANSITION = 0
+ *  NMI     = 1
+ *  IRQ     = 2
+ *  SOFTIRQ = 3
+ *  NORMAL  = 4
  *
  * See trace_recursive_lock() comment below for more details.
  */
 enum {
+	RB_CTX_TRANSITION,
 	RB_CTX_NMI,
 	RB_CTX_IRQ,
 	RB_CTX_SOFTIRQ,
@@ -3014,10 +3016,10 @@ rb_wakeups(struct trace_buffer *buffer, struct ring_buffer_per_cpu *cpu_buffer)
  * a bit of overhead in something as critical as function tracing,
  * we use a bitmask trick.
  *
- *  bit 0 =  NMI context
- *  bit 1 =  IRQ context
- *  bit 2 =  SoftIRQ context
- *  bit 3 =  normal context.
+ *  bit 1 =  NMI context
+ *  bit 2 =  IRQ context
+ *  bit 3 =  SoftIRQ context
+ *  bit 4 =  normal context.
  *
  * This works because this is the order of contexts that can
  * preempt other contexts. A SoftIRQ never preempts an IRQ
@@ -3040,6 +3042,30 @@ rb_wakeups(struct trace_buffer *buffer, struct ring_buffer_per_cpu *cpu_buffer)
  * The least significant bit can be cleared this way, and it
  * just so happens that it is the same bit corresponding to
  * the current context.
+ *
+ * Now the TRANSITION bit breaks the above slightly. The TRANSITION bit
+ * is set when a recursion is detected at the current context, and if
+ * the TRANSITION bit is already set, it will fail the recursion.
+ * This is needed because there's a lag between the changing of
+ * interrupt context and updating the preempt count. In this case,
+ * a false positive will be found. To handle this, one extra recursion
+ * is allowed, and this is done by the TRANSITION bit. If the TRANSITION
+ * bit is already set, then it is considered a recursion and the function
+ * ends. Otherwise, the TRANSITION bit is set, and that bit is returned.
+ *
+ * On the trace_recursive_unlock(), the TRANSITION bit will be the first
+ * to be cleared. Even if it wasn't the context that set it. That is,
+ * if an interrupt comes in while NORMAL bit is set and the ring buffer
+ * is called before preempt_count() is updated, since the check will
+ * be on the NORMAL bit, the TRANSITION bit will then be set. If an
+ * NMI then comes in, it will set the NMI bit, but when the NMI code
+ * does the trace_recursive_unlock() it will clear the TRANSTION bit
+ * and leave the NMI bit set. But this is fine, because the interrupt
+ * code that set the TRANSITION bit will then clear the NMI bit when it
+ * calls trace_recursive_unlock(). If another NMI comes in, it will
+ * set the TRANSITION bit and continue.
+ *
+ * Note: The TRANSITION bit only handles a single transition between context.
  */
 
 static __always_inline int
@@ -3055,8 +3081,16 @@ trace_recursive_lock(struct ring_buffer_per_cpu *cpu_buffer)
 		bit = pc & NMI_MASK ? RB_CTX_NMI :
 			pc & HARDIRQ_MASK ? RB_CTX_IRQ : RB_CTX_SOFTIRQ;
 
-	if (unlikely(val & (1 << (bit + cpu_buffer->nest))))
-		return 1;
+	if (unlikely(val & (1 << (bit + cpu_buffer->nest)))) {
+		/*
+		 * It is possible that this was called by transitioning
+		 * between interrupt context, and preempt_count() has not
+		 * been updated yet. In this case, use the TRANSITION bit.
+		 */
+		bit = RB_CTX_TRANSITION;
+		if (val & (1 << (bit + cpu_buffer->nest)))
+			return 1;
+	}
 
 	val |= (1 << (bit + cpu_buffer->nest));
 	cpu_buffer->current_context = val;
@@ -3071,8 +3105,8 @@ trace_recursive_unlock(struct ring_buffer_per_cpu *cpu_buffer)
 		cpu_buffer->current_context - (1 << cpu_buffer->nest);
 }
 
-/* The recursive locking above uses 4 bits */
-#define NESTED_BITS 4
+/* The recursive locking above uses 5 bits */
+#define NESTED_BITS 5
 
 /**
  * ring_buffer_nest_start - Allow to trace while nested
diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index 528971714fc6..410cfeb16db5 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -2750,7 +2750,7 @@ trace_event_buffer_lock_reserve(struct trace_buffer **current_rb,
 	/*
 	 * If tracing is off, but we have triggers enabled
 	 * we still need to look at the event data. Use the temp_buffer
-	 * to store the trace event for the tigger to use. It's recusive
+	 * to store the trace event for the trigger to use. It's recursive
 	 * safe and will not be recorded anywhere.
 	 */
 	if (!entry && trace_file->flags & EVENT_FILE_FL_TRIGGER_COND) {
@@ -2952,7 +2952,7 @@ static void __ftrace_trace_stack(struct trace_buffer *buffer,
 	stackidx = __this_cpu_inc_return(ftrace_stack_reserve) - 1;
 
 	/* This should never happen. If it does, yell once and skip */
-	if (WARN_ON_ONCE(stackidx > FTRACE_KSTACK_NESTING))
+	if (WARN_ON_ONCE(stackidx >= FTRACE_KSTACK_NESTING))
 		goto out;
 
 	/*
@@ -3132,7 +3132,7 @@ static char *get_trace_buf(void)
 
 	/* Interrupts must see nesting incremented before we use the buffer */
 	barrier();
-	return &buffer->buffer[buffer->nesting][0];
+	return &buffer->buffer[buffer->nesting - 1][0];
 }
 
 static void put_trace_buf(void)
diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
index f3f5e77123ad..1dadef445cd1 100644
--- a/kernel/trace/trace.h
+++ b/kernel/trace/trace.h
@@ -637,6 +637,12 @@ enum {
 	 * function is called to clear it.
 	 */
 	TRACE_GRAPH_NOTRACE_BIT,
+
+	/*
+	 * When transitioning between context, the preempt_count() may
+	 * not be correct. Allow for a single recursion to cover this case.
+	 */
+	TRACE_TRANSITION_BIT,
 };
 
 #define trace_recursion_set(bit)	do { (current)->trace_recursion |= (1<<(bit)); } while (0)
@@ -691,14 +697,27 @@ static __always_inline int trace_test_and_set_recursion(int start, int max)
 		return 0;
 
 	bit = trace_get_context_bit() + start;
-	if (unlikely(val & (1 << bit)))
-		return -1;
+	if (unlikely(val & (1 << bit))) {
+		/*
+		 * It could be that preempt_count has not been updated during
+		 * a switch between contexts. Allow for a single recursion.
+		 */
+		bit = TRACE_TRANSITION_BIT;
+		if (trace_recursion_test(bit))
+			return -1;
+		trace_recursion_set(bit);
+		barrier();
+		return bit + 1;
+	}
+
+	/* Normal check passed, clear the transition to allow it again */
+	trace_recursion_clear(TRACE_TRANSITION_BIT);
 
 	val |= 1 << bit;
 	current->trace_recursion = val;
 	barrier();
 
-	return bit;
+	return bit + 1;
 }
 
 static __always_inline void trace_clear_recursion(int bit)
@@ -708,6 +727,7 @@ static __always_inline void trace_clear_recursion(int bit)
 	if (!bit)
 		return;
 
+	bit--;
 	bit = 1 << bit;
 	val &= ~bit;
 
diff --git a/kernel/trace/trace_events_synth.c b/kernel/trace/trace_events_synth.c
index 84b7cab55291..881df991742a 100644
--- a/kernel/trace/trace_events_synth.c
+++ b/kernel/trace/trace_events_synth.c
@@ -584,7 +584,7 @@ static struct synth_field *parse_synth_field(int argc, const char **argv,
 {
 	struct synth_field *field;
 	const char *prefix = NULL, *field_type = argv[0], *field_name, *array;
-	int len, ret = 0;
+	int len, ret = -ENOMEM;
 	struct seq_buf s;
 	ssize_t size;
 
@@ -617,10 +617,9 @@ static struct synth_field *parse_synth_field(int argc, const char **argv,
 		len--;
 
 	field->name = kmemdup_nul(field_name, len, GFP_KERNEL);
-	if (!field->name) {
-		ret = -ENOMEM;
+	if (!field->name)
 		goto free;
-	}
+
 	if (!is_good_name(field->name)) {
 		synth_err(SYNTH_ERR_BAD_NAME, errpos(field_name));
 		ret = -EINVAL;
@@ -638,10 +637,9 @@ static struct synth_field *parse_synth_field(int argc, const char **argv,
 		len += strlen(prefix);
 
 	field->type = kzalloc(len, GFP_KERNEL);
-	if (!field->type) {
-		ret = -ENOMEM;
+	if (!field->type)
 		goto free;
-	}
+
 	seq_buf_init(&s, field->type, len);
 	if (prefix)
 		seq_buf_puts(&s, prefix);
@@ -653,6 +651,7 @@ static struct synth_field *parse_synth_field(int argc, const char **argv,
 	}
 	if (WARN_ON_ONCE(!seq_buf_buffer_left(&s)))
 		goto free;
+
 	s.buffer[s.len] = '\0';
 
 	size = synth_field_size(field->type);
@@ -666,10 +665,8 @@ static struct synth_field *parse_synth_field(int argc, const char **argv,
 
 			len = sizeof("__data_loc ") + strlen(field->type) + 1;
 			type = kzalloc(len, GFP_KERNEL);
-			if (!type) {
-				ret = -ENOMEM;
+			if (!type)
 				goto free;
-			}
 
 			seq_buf_init(&s, type, len);
 			seq_buf_puts(&s, "__data_loc ");
diff --git a/kernel/trace/trace_selftest.c b/kernel/trace/trace_selftest.c
index b5e3496cf803..4738ad48a667 100644
--- a/kernel/trace/trace_selftest.c
+++ b/kernel/trace/trace_selftest.c
@@ -492,8 +492,13 @@ trace_selftest_function_recursion(void)
 	unregister_ftrace_function(&test_rec_probe);
 
 	ret = -1;
-	if (trace_selftest_recursion_cnt != 1) {
-		pr_cont("*callback not called once (%d)* ",
+	/*
+	 * Recursion allows for transitions between context,
+	 * and may call the callback twice.
+	 */
+	if (trace_selftest_recursion_cnt != 1 &&
+	    trace_selftest_recursion_cnt != 2) {
+		pr_cont("*callback not called once (or twice) (%d)* ",
 			trace_selftest_recursion_cnt);
 		goto out;
 	}
diff --git a/lib/crc32test.c b/lib/crc32test.c
index 97d6a57cefcc..61ddce2cff77 100644
--- a/lib/crc32test.c
+++ b/lib/crc32test.c
@@ -683,7 +683,6 @@ static int __init crc32c_test(void)
 
 	/* reduce OS noise */
 	local_irq_save(flags);
-	local_irq_disable();
 
 	nsec = ktime_get_ns();
 	for (i = 0; i < 100; i++) {
@@ -694,7 +693,6 @@ static int __init crc32c_test(void)
 	nsec = ktime_get_ns() - nsec;
 
 	local_irq_restore(flags);
-	local_irq_enable();
 
 	pr_info("crc32c: CRC_LE_BITS = %d\n", CRC_LE_BITS);
 
@@ -768,7 +766,6 @@ static int __init crc32_test(void)
 
 	/* reduce OS noise */
 	local_irq_save(flags);
-	local_irq_disable();
 
 	nsec = ktime_get_ns();
 	for (i = 0; i < 100; i++) {
@@ -783,7 +780,6 @@ static int __init crc32_test(void)
 	nsec = ktime_get_ns() - nsec;
 
 	local_irq_restore(flags);
-	local_irq_enable();
 
 	pr_info("crc32: CRC_LE_BITS = %d, CRC_BE BITS = %d\n",
 		 CRC_LE_BITS, CRC_BE_BITS);
diff --git a/lib/fonts/font_10x18.c b/lib/fonts/font_10x18.c
index 0e2deac97da0..e02f9df24d1e 100644
--- a/lib/fonts/font_10x18.c
+++ b/lib/fonts/font_10x18.c
@@ -8,7 +8,7 @@
 
 #define FONTDATAMAX 9216
 
-static struct font_data fontdata_10x18 = {
+static const struct font_data fontdata_10x18 = {
 	{ 0, 0, FONTDATAMAX, 0 }, {
 	/* 0 0x00 '^@' */
 	0x00, 0x00, /* 0000000000 */
diff --git a/lib/fonts/font_6x10.c b/lib/fonts/font_6x10.c
index 87da8acd07db..6e3c4b7691c8 100644
--- a/lib/fonts/font_6x10.c
+++ b/lib/fonts/font_6x10.c
@@ -3,7 +3,7 @@
 
 #define FONTDATAMAX 2560
 
-static struct font_data fontdata_6x10 = {
+static const struct font_data fontdata_6x10 = {
 	{ 0, 0, FONTDATAMAX, 0 }, {
 	/* 0 0x00 '^@' */
 	0x00, /* 00000000 */
diff --git a/lib/fonts/font_6x11.c b/lib/fonts/font_6x11.c
index 5e975dfa10a5..2d22a24e816f 100644
--- a/lib/fonts/font_6x11.c
+++ b/lib/fonts/font_6x11.c
@@ -9,7 +9,7 @@
 
 #define FONTDATAMAX (11*256)
 
-static struct font_data fontdata_6x11 = {
+static const struct font_data fontdata_6x11 = {
 	{ 0, 0, FONTDATAMAX, 0 }, {
 	/* 0 0x00 '^@' */
 	0x00, /* 00000000 */
diff --git a/lib/fonts/font_6x8.c b/lib/fonts/font_6x8.c
index 700039a9ceae..e7442a0d183d 100644
--- a/lib/fonts/font_6x8.c
+++ b/lib/fonts/font_6x8.c
@@ -3,7 +3,7 @@
 
 #define FONTDATAMAX 2048
 
-static struct font_data fontdata_6x8 = {
+static const struct font_data fontdata_6x8 = {
 	{ 0, 0, FONTDATAMAX, 0 }, {
 	/* 0 0x00 '^@' */
 	0x00, /* 000000 */
diff --git a/lib/fonts/font_7x14.c b/lib/fonts/font_7x14.c
index 86d298f38505..9cc7ae2e03f7 100644
--- a/lib/fonts/font_7x14.c
+++ b/lib/fonts/font_7x14.c
@@ -8,7 +8,7 @@
 
 #define FONTDATAMAX 3584
 
-static struct font_data fontdata_7x14 = {
+static const struct font_data fontdata_7x14 = {
 	{ 0, 0, FONTDATAMAX, 0 }, {
 	/* 0 0x00 '^@' */
 	0x00, /* 0000000 */
diff --git a/lib/fonts/font_8x16.c b/lib/fonts/font_8x16.c
index 37cedd36ca5e..bab25dc59e8d 100644
--- a/lib/fonts/font_8x16.c
+++ b/lib/fonts/font_8x16.c
@@ -10,7 +10,7 @@
 
 #define FONTDATAMAX 4096
 
-static struct font_data fontdata_8x16 = {
+static const struct font_data fontdata_8x16 = {
 	{ 0, 0, FONTDATAMAX, 0 }, {
 	/* 0 0x00 '^@' */
 	0x00, /* 00000000 */
diff --git a/lib/fonts/font_8x8.c b/lib/fonts/font_8x8.c
index 8ab695538395..109d0572368f 100644
--- a/lib/fonts/font_8x8.c
+++ b/lib/fonts/font_8x8.c
@@ -9,7 +9,7 @@
 
 #define FONTDATAMAX 2048
 
-static struct font_data fontdata_8x8 = {
+static const struct font_data fontdata_8x8 = {
 	{ 0, 0, FONTDATAMAX, 0 }, {
 	/* 0 0x00 '^@' */
 	0x00, /* 00000000 */
diff --git a/lib/fonts/font_acorn_8x8.c b/lib/fonts/font_acorn_8x8.c
index 069b3e80c434..fb395f0d4031 100644
--- a/lib/fonts/font_acorn_8x8.c
+++ b/lib/fonts/font_acorn_8x8.c
@@ -5,7 +5,7 @@
 
 #define FONTDATAMAX 2048
 
-static struct font_data acorndata_8x8 = {
+static const struct font_data acorndata_8x8 = {
 { 0, 0, FONTDATAMAX, 0 }, {
 /* 00 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ^@ */
 /* 01 */  0x7e, 0x81, 0xa5, 0x81, 0xbd, 0x99, 0x81, 0x7e, /* ^A */
diff --git a/lib/fonts/font_mini_4x6.c b/lib/fonts/font_mini_4x6.c
index 1449876c6a27..592774a90917 100644
--- a/lib/fonts/font_mini_4x6.c
+++ b/lib/fonts/font_mini_4x6.c
@@ -43,7 +43,7 @@ __END__;
 
 #define FONTDATAMAX 1536
 
-static struct font_data fontdata_mini_4x6 = {
+static const struct font_data fontdata_mini_4x6 = {
 	{ 0, 0, FONTDATAMAX, 0 }, {
 	/*{*/
 	  	/*   Char 0: ' '  */
diff --git a/lib/fonts/font_pearl_8x8.c b/lib/fonts/font_pearl_8x8.c
index 32d65551e7ed..a6f95ebce950 100644
--- a/lib/fonts/font_pearl_8x8.c
+++ b/lib/fonts/font_pearl_8x8.c
@@ -14,7 +14,7 @@
 
 #define FONTDATAMAX 2048
 
-static struct font_data fontdata_pearl8x8 = {
+static const struct font_data fontdata_pearl8x8 = {
    { 0, 0, FONTDATAMAX, 0 }, {
    /* 0 0x00 '^@' */
    0x00, /* 00000000 */
diff --git a/lib/fonts/font_sun12x22.c b/lib/fonts/font_sun12x22.c
index 641a6b4dca42..a5b65bd49604 100644
--- a/lib/fonts/font_sun12x22.c
+++ b/lib/fonts/font_sun12x22.c
@@ -3,7 +3,7 @@
 
 #define FONTDATAMAX 11264
 
-static struct font_data fontdata_sun12x22 = {
+static const struct font_data fontdata_sun12x22 = {
 	{ 0, 0, FONTDATAMAX, 0 }, {
 	/* 0 0x00 '^@' */
 	0x00, 0x00, /* 000000000000 */
diff --git a/lib/fonts/font_sun8x16.c b/lib/fonts/font_sun8x16.c
index 193fe6d988e0..e577e76a6a7c 100644
--- a/lib/fonts/font_sun8x16.c
+++ b/lib/fonts/font_sun8x16.c
@@ -3,7 +3,7 @@
 
 #define FONTDATAMAX 4096
 
-static struct font_data fontdata_sun8x16 = {
+static const struct font_data fontdata_sun8x16 = {
 { 0, 0, FONTDATAMAX, 0 }, {
 /* */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
 /* */ 0x00,0x00,0x7e,0x81,0xa5,0x81,0x81,0xbd,0x99,0x81,0x81,0x7e,0x00,0x00,0x00,0x00,
diff --git a/lib/fonts/font_ter16x32.c b/lib/fonts/font_ter16x32.c
index 91b9c283bd9c..f7c3abb6b99e 100644
--- a/lib/fonts/font_ter16x32.c
+++ b/lib/fonts/font_ter16x32.c
@@ -4,7 +4,7 @@
 
 #define FONTDATAMAX 16384
 
-static struct font_data fontdata_ter16x32 = {
+static const struct font_data fontdata_ter16x32 = {
 	{ 0, 0, FONTDATAMAX, 0 }, {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x00, 0x00, 0x00, 0x00, 0x7f, 0xfc, 0x7f, 0xfc,
diff --git a/lib/test_kasan.c b/lib/test_kasan.c
index 63c26171a791..662f862702fc 100644
--- a/lib/test_kasan.c
+++ b/lib/test_kasan.c
@@ -216,6 +216,12 @@ static void kmalloc_oob_16(struct kunit *test)
 		u64 words[2];
 	} *ptr1, *ptr2;
 
+	/* This test is specifically crafted for the generic mode. */
+	if (!IS_ENABLED(CONFIG_KASAN_GENERIC)) {
+		kunit_info(test, "CONFIG_KASAN_GENERIC required\n");
+		return;
+	}
+
 	ptr1 = kmalloc(sizeof(*ptr1) - 3, GFP_KERNEL);
 	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr1);
 
@@ -227,6 +233,23 @@ static void kmalloc_oob_16(struct kunit *test)
 	kfree(ptr2);
 }
 
+static void kmalloc_uaf_16(struct kunit *test)
+{
+	struct {
+		u64 words[2];
+	} *ptr1, *ptr2;
+
+	ptr1 = kmalloc(sizeof(*ptr1), GFP_KERNEL);
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr1);
+
+	ptr2 = kmalloc(sizeof(*ptr2), GFP_KERNEL);
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr2);
+	kfree(ptr2);
+
+	KUNIT_EXPECT_KASAN_FAIL(test, *ptr1 = *ptr2);
+	kfree(ptr1);
+}
+
 static void kmalloc_oob_memset_2(struct kunit *test)
 {
 	char *ptr;
@@ -429,6 +452,12 @@ static void kasan_global_oob(struct kunit *test)
 	volatile int i = 3;
 	char *p = &global_array[ARRAY_SIZE(global_array) + i];
 
+	/* Only generic mode instruments globals. */
+	if (!IS_ENABLED(CONFIG_KASAN_GENERIC)) {
+		kunit_info(test, "CONFIG_KASAN_GENERIC required");
+		return;
+	}
+
 	KUNIT_EXPECT_KASAN_FAIL(test, *(volatile char *)p);
 }
 
@@ -467,6 +496,12 @@ static void kasan_alloca_oob_left(struct kunit *test)
 	char alloca_array[i];
 	char *p = alloca_array - 1;
 
+	/* Only generic mode instruments dynamic allocas. */
+	if (!IS_ENABLED(CONFIG_KASAN_GENERIC)) {
+		kunit_info(test, "CONFIG_KASAN_GENERIC required");
+		return;
+	}
+
 	if (!IS_ENABLED(CONFIG_KASAN_STACK)) {
 		kunit_info(test, "CONFIG_KASAN_STACK is not enabled");
 		return;
@@ -481,6 +516,12 @@ static void kasan_alloca_oob_right(struct kunit *test)
 	char alloca_array[i];
 	char *p = alloca_array + i;
 
+	/* Only generic mode instruments dynamic allocas. */
+	if (!IS_ENABLED(CONFIG_KASAN_GENERIC)) {
+		kunit_info(test, "CONFIG_KASAN_GENERIC required");
+		return;
+	}
+
 	if (!IS_ENABLED(CONFIG_KASAN_STACK)) {
 		kunit_info(test, "CONFIG_KASAN_STACK is not enabled");
 		return;
@@ -551,6 +592,9 @@ static void kasan_memchr(struct kunit *test)
 		return;
 	}
 
+	if (OOB_TAG_OFF)
+		size = round_up(size, OOB_TAG_OFF);
+
 	ptr = kmalloc(size, GFP_KERNEL | __GFP_ZERO);
 	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr);
 
@@ -573,6 +617,9 @@ static void kasan_memcmp(struct kunit *test)
 		return;
 	}
 
+	if (OOB_TAG_OFF)
+		size = round_up(size, OOB_TAG_OFF);
+
 	ptr = kmalloc(size, GFP_KERNEL | __GFP_ZERO);
 	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ptr);
 	memset(arr, 0, sizeof(arr));
@@ -619,13 +666,50 @@ static void kasan_strings(struct kunit *test)
 	KUNIT_EXPECT_KASAN_FAIL(test, kasan_int_result = strnlen(ptr, 1));
 }
 
-static void kasan_bitops(struct kunit *test)
+static void kasan_bitops_modify(struct kunit *test, int nr, void *addr)
+{
+	KUNIT_EXPECT_KASAN_FAIL(test, set_bit(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, __set_bit(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, clear_bit(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, __clear_bit(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, clear_bit_unlock(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, __clear_bit_unlock(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, change_bit(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, __change_bit(nr, addr));
+}
+
+static void kasan_bitops_test_and_modify(struct kunit *test, int nr, void *addr)
+{
+	KUNIT_EXPECT_KASAN_FAIL(test, test_and_set_bit(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, __test_and_set_bit(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, test_and_set_bit_lock(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, test_and_clear_bit(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, __test_and_clear_bit(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, test_and_change_bit(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, __test_and_change_bit(nr, addr));
+	KUNIT_EXPECT_KASAN_FAIL(test, kasan_int_result = test_bit(nr, addr));
+
+#if defined(clear_bit_unlock_is_negative_byte)
+	KUNIT_EXPECT_KASAN_FAIL(test, kasan_int_result =
+				clear_bit_unlock_is_negative_byte(nr, addr));
+#endif
+}
+
+static void kasan_bitops_generic(struct kunit *test)
 {
+	long *bits;
+
+	/* This test is specifically crafted for the generic mode. */
+	if (!IS_ENABLED(CONFIG_KASAN_GENERIC)) {
+		kunit_info(test, "CONFIG_KASAN_GENERIC required\n");
+		return;
+	}
+
 	/*
 	 * Allocate 1 more byte, which causes kzalloc to round up to 16-bytes;
 	 * this way we do not actually corrupt other memory.
 	 */
-	long *bits = kzalloc(sizeof(*bits) + 1, GFP_KERNEL);
+	bits = kzalloc(sizeof(*bits) + 1, GFP_KERNEL);
 	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, bits);
 
 	/*
@@ -633,55 +717,34 @@ static void kasan_bitops(struct kunit *test)
 	 * below accesses are still out-of-bounds, since bitops are defined to
 	 * operate on the whole long the bit is in.
 	 */
-	KUNIT_EXPECT_KASAN_FAIL(test, set_bit(BITS_PER_LONG, bits));
-
-	KUNIT_EXPECT_KASAN_FAIL(test, __set_bit(BITS_PER_LONG, bits));
-
-	KUNIT_EXPECT_KASAN_FAIL(test, clear_bit(BITS_PER_LONG, bits));
-
-	KUNIT_EXPECT_KASAN_FAIL(test, __clear_bit(BITS_PER_LONG, bits));
-
-	KUNIT_EXPECT_KASAN_FAIL(test, clear_bit_unlock(BITS_PER_LONG, bits));
-
-	KUNIT_EXPECT_KASAN_FAIL(test, __clear_bit_unlock(BITS_PER_LONG, bits));
-
-	KUNIT_EXPECT_KASAN_FAIL(test, change_bit(BITS_PER_LONG, bits));
-
-	KUNIT_EXPECT_KASAN_FAIL(test, __change_bit(BITS_PER_LONG, bits));
+	kasan_bitops_modify(test, BITS_PER_LONG, bits);
 
 	/*
 	 * Below calls try to access bit beyond allocated memory.
 	 */
-	KUNIT_EXPECT_KASAN_FAIL(test,
-		test_and_set_bit(BITS_PER_LONG + BITS_PER_BYTE, bits));
-
-	KUNIT_EXPECT_KASAN_FAIL(test,
-		__test_and_set_bit(BITS_PER_LONG + BITS_PER_BYTE, bits));
-
-	KUNIT_EXPECT_KASAN_FAIL(test,
-		test_and_set_bit_lock(BITS_PER_LONG + BITS_PER_BYTE, bits));
+	kasan_bitops_test_and_modify(test, BITS_PER_LONG + BITS_PER_BYTE, bits);
 
-	KUNIT_EXPECT_KASAN_FAIL(test,
-		test_and_clear_bit(BITS_PER_LONG + BITS_PER_BYTE, bits));
+	kfree(bits);
+}
 
-	KUNIT_EXPECT_KASAN_FAIL(test,
-		__test_and_clear_bit(BITS_PER_LONG + BITS_PER_BYTE, bits));
+static void kasan_bitops_tags(struct kunit *test)
+{
+	long *bits;
 
-	KUNIT_EXPECT_KASAN_FAIL(test,
-		test_and_change_bit(BITS_PER_LONG + BITS_PER_BYTE, bits));
+	/* This test is specifically crafted for the tag-based mode. */
+	if (IS_ENABLED(CONFIG_KASAN_GENERIC)) {
+		kunit_info(test, "CONFIG_KASAN_SW_TAGS required\n");
+		return;
+	}
 
-	KUNIT_EXPECT_KASAN_FAIL(test,
-		__test_and_change_bit(BITS_PER_LONG + BITS_PER_BYTE, bits));
+	/* Allocation size will be rounded to up granule size, which is 16. */
+	bits = kzalloc(sizeof(*bits), GFP_KERNEL);
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, bits);
 
-	KUNIT_EXPECT_KASAN_FAIL(test,
-		kasan_int_result =
-			test_bit(BITS_PER_LONG + BITS_PER_BYTE, bits));
+	/* Do the accesses past the 16 allocated bytes. */
+	kasan_bitops_modify(test, BITS_PER_LONG, &bits[1]);
+	kasan_bitops_test_and_modify(test, BITS_PER_LONG + BITS_PER_BYTE, &bits[1]);
 
-#if defined(clear_bit_unlock_is_negative_byte)
-	KUNIT_EXPECT_KASAN_FAIL(test,
-		kasan_int_result = clear_bit_unlock_is_negative_byte(
-			BITS_PER_LONG + BITS_PER_BYTE, bits));
-#endif
 	kfree(bits);
 }
 
@@ -728,6 +791,7 @@ static struct kunit_case kasan_kunit_test_cases[] = {
 	KUNIT_CASE(kmalloc_oob_krealloc_more),
 	KUNIT_CASE(kmalloc_oob_krealloc_less),
 	KUNIT_CASE(kmalloc_oob_16),
+	KUNIT_CASE(kmalloc_uaf_16),
 	KUNIT_CASE(kmalloc_oob_in_memset),
 	KUNIT_CASE(kmalloc_oob_memset_2),
 	KUNIT_CASE(kmalloc_oob_memset_4),
@@ -751,7 +815,8 @@ static struct kunit_case kasan_kunit_test_cases[] = {
 	KUNIT_CASE(kasan_memchr),
 	KUNIT_CASE(kasan_memcmp),
 	KUNIT_CASE(kasan_strings),
-	KUNIT_CASE(kasan_bitops),
+	KUNIT_CASE(kasan_bitops_generic),
+	KUNIT_CASE(kasan_bitops_tags),
 	KUNIT_CASE(kmalloc_double_kzfree),
 	KUNIT_CASE(vmalloc_oob),
 	{}
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index fe76f8fd5a73..5a620f690911 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -648,6 +648,8 @@ retry:
 			}
 
 			del += t - f;
+			hugetlb_cgroup_uncharge_file_region(
+				resv, rg, t - f);
 
 			/* New entry for end of split region */
 			nrg->from = t;
@@ -660,9 +662,6 @@ retry:
 			/* Original entry is trimmed */
 			rg->to = f;
 
-			hugetlb_cgroup_uncharge_file_region(
-				resv, rg, nrg->to - nrg->from);
-
 			list_add(&nrg->link, &rg->link);
 			nrg = NULL;
 			break;
@@ -678,17 +677,17 @@ retry:
 		}
 
 		if (f <= rg->from) {	/* Trim beginning of region */
-			del += t - rg->from;
-			rg->from = t;
-
 			hugetlb_cgroup_uncharge_file_region(resv, rg,
 							    t - rg->from);
-		} else {		/* Trim end of region */
-			del += rg->to - f;
-			rg->to = f;
 
+			del += t - rg->from;
+			rg->from = t;
+		} else {		/* Trim end of region */
 			hugetlb_cgroup_uncharge_file_region(resv, rg,
 							    rg->to - f);
+
+			del += rg->to - f;
+			rg->to = f;
 		}
 	}
 
@@ -2443,6 +2442,9 @@ struct page *alloc_huge_page(struct vm_area_struct *vma,
 
 		rsv_adjust = hugepage_subpool_put_pages(spool, 1);
 		hugetlb_acct_memory(h, -rsv_adjust);
+		if (deferred_reserve)
+			hugetlb_cgroup_uncharge_page_rsvd(hstate_index(h),
+					pages_per_huge_page(h), page);
 	}
 	return page;
 
diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index 3a24e3b619f5..3dcbf24d2227 100644
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
@@ -4110,11 +4110,17 @@ static int memcg_stat_show(struct seq_file *m, void *v)
 			   (u64)memsw * PAGE_SIZE);
 
 	for (i = 0; i < ARRAY_SIZE(memcg1_stats); i++) {
+		unsigned long nr;
+
 		if (memcg1_stats[i] == MEMCG_SWAP && !do_memsw_account())
 			continue;
+		nr = memcg_page_state(memcg, memcg1_stats[i]);
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+		if (memcg1_stats[i] == NR_ANON_THPS)
+			nr *= HPAGE_PMD_NR;
+#endif
 		seq_printf(m, "total_%s %llu\n", memcg1_stat_names[i],
-			   (u64)memcg_page_state(memcg, memcg1_stats[i]) *
-			   PAGE_SIZE);
+						(u64)nr * PAGE_SIZE);
 	}
 
 	for (i = 0; i < ARRAY_SIZE(memcg1_events); i++)
@@ -5339,17 +5345,22 @@ mem_cgroup_css_alloc(struct cgroup_subsys_state *parent_css)
 		memcg->swappiness = mem_cgroup_swappiness(parent);
 		memcg->oom_kill_disable = parent->oom_kill_disable;
 	}
-	if (parent && parent->use_hierarchy) {
+	if (!parent) {
+		page_counter_init(&memcg->memory, NULL);
+		page_counter_init(&memcg->swap, NULL);
+		page_counter_init(&memcg->kmem, NULL);
+		page_counter_init(&memcg->tcpmem, NULL);
+	} else if (parent->use_hierarchy) {
 		memcg->use_hierarchy = true;
 		page_counter_init(&memcg->memory, &parent->memory);
 		page_counter_init(&memcg->swap, &parent->swap);
 		page_counter_init(&memcg->kmem, &parent->kmem);
 		page_counter_init(&memcg->tcpmem, &parent->tcpmem);
 	} else {
-		page_counter_init(&memcg->memory, NULL);
-		page_counter_init(&memcg->swap, NULL);
-		page_counter_init(&memcg->kmem, NULL);
-		page_counter_init(&memcg->tcpmem, NULL);
+		page_counter_init(&memcg->memory, &root_mem_cgroup->memory);
+		page_counter_init(&memcg->swap, &root_mem_cgroup->swap);
+		page_counter_init(&memcg->kmem, &root_mem_cgroup->kmem);
+		page_counter_init(&memcg->tcpmem, &root_mem_cgroup->tcpmem);
 		/*
 		 * Deeper hierachy with use_hierarchy == false doesn't make
 		 * much sense so let cgroup subsystem know about this
diff --git a/mm/mempolicy.c b/mm/mempolicy.c
index 3fde772ef5ef..3ca4898f3f24 100644
--- a/mm/mempolicy.c
+++ b/mm/mempolicy.c
@@ -525,7 +525,7 @@ static int queue_pages_pte_range(pmd_t *pmd, unsigned long addr,
 	unsigned long flags = qp->flags;
 	int ret;
 	bool has_unmovable = false;
-	pte_t *pte;
+	pte_t *pte, *mapped_pte;
 	spinlock_t *ptl;
 
 	ptl = pmd_trans_huge_lock(pmd, vma);
@@ -539,7 +539,7 @@ static int queue_pages_pte_range(pmd_t *pmd, unsigned long addr,
 	if (pmd_trans_unstable(pmd))
 		return 0;
 
-	pte = pte_offset_map_lock(walk->mm, pmd, addr, &ptl);
+	mapped_pte = pte = pte_offset_map_lock(walk->mm, pmd, addr, &ptl);
 	for (; addr != end; pte++, addr += PAGE_SIZE) {
 		if (!pte_present(*pte))
 			continue;
@@ -571,7 +571,7 @@ static int queue_pages_pte_range(pmd_t *pmd, unsigned long addr,
 		} else
 			break;
 	}
-	pte_unmap_unlock(pte - 1, ptl);
+	pte_unmap_unlock(mapped_pte, ptl);
 	cond_resched();
 
 	if (has_unmovable)
diff --git a/mm/memremap.c b/mm/memremap.c
index 73a206d0f645..16b2fb482da1 100644
--- a/mm/memremap.c
+++ b/mm/memremap.c
@@ -41,28 +41,24 @@ EXPORT_SYMBOL_GPL(memremap_compat_align);
 DEFINE_STATIC_KEY_FALSE(devmap_managed_key);
 EXPORT_SYMBOL(devmap_managed_key);
 
-static void devmap_managed_enable_put(void)
+static void devmap_managed_enable_put(struct dev_pagemap *pgmap)
 {
-	static_branch_dec(&devmap_managed_key);
+	if (pgmap->type == MEMORY_DEVICE_PRIVATE ||
+	    pgmap->type == MEMORY_DEVICE_FS_DAX)
+		static_branch_dec(&devmap_managed_key);
 }
 
-static int devmap_managed_enable_get(struct dev_pagemap *pgmap)
+static void devmap_managed_enable_get(struct dev_pagemap *pgmap)
 {
-	if (pgmap->type == MEMORY_DEVICE_PRIVATE &&
-	    (!pgmap->ops || !pgmap->ops->page_free)) {
-		WARN(1, "Missing page_free method\n");
-		return -EINVAL;
-	}
-
-	static_branch_inc(&devmap_managed_key);
-	return 0;
+	if (pgmap->type == MEMORY_DEVICE_PRIVATE ||
+	    pgmap->type == MEMORY_DEVICE_FS_DAX)
+		static_branch_inc(&devmap_managed_key);
 }
 #else
-static int devmap_managed_enable_get(struct dev_pagemap *pgmap)
+static void devmap_managed_enable_get(struct dev_pagemap *pgmap)
 {
-	return -EINVAL;
 }
-static void devmap_managed_enable_put(void)
+static void devmap_managed_enable_put(struct dev_pagemap *pgmap)
 {
 }
 #endif /* CONFIG_DEV_PAGEMAP_OPS */
@@ -169,7 +165,7 @@ void memunmap_pages(struct dev_pagemap *pgmap)
 		pageunmap_range(pgmap, i);
 
 	WARN_ONCE(pgmap->altmap.alloc, "failed to free all reserved pages\n");
-	devmap_managed_enable_put();
+	devmap_managed_enable_put(pgmap);
 }
 EXPORT_SYMBOL_GPL(memunmap_pages);
 
@@ -307,7 +303,6 @@ void *memremap_pages(struct dev_pagemap *pgmap, int nid)
 		.pgprot = PAGE_KERNEL,
 	};
 	const int nr_range = pgmap->nr_range;
-	bool need_devmap_managed = true;
 	int error, i;
 
 	if (WARN_ONCE(!nr_range, "nr_range must be specified\n"))
@@ -323,6 +318,10 @@ void *memremap_pages(struct dev_pagemap *pgmap, int nid)
 			WARN(1, "Missing migrate_to_ram method\n");
 			return ERR_PTR(-EINVAL);
 		}
+		if (!pgmap->ops->page_free) {
+			WARN(1, "Missing page_free method\n");
+			return ERR_PTR(-EINVAL);
+		}
 		if (!pgmap->owner) {
 			WARN(1, "Missing owner\n");
 			return ERR_PTR(-EINVAL);
@@ -336,11 +335,9 @@ void *memremap_pages(struct dev_pagemap *pgmap, int nid)
 		}
 		break;
 	case MEMORY_DEVICE_GENERIC:
-		need_devmap_managed = false;
 		break;
 	case MEMORY_DEVICE_PCI_P2PDMA:
 		params.pgprot = pgprot_noncached(params.pgprot);
-		need_devmap_managed = false;
 		break;
 	default:
 		WARN(1, "Invalid pgmap type %d\n", pgmap->type);
@@ -364,11 +361,7 @@ void *memremap_pages(struct dev_pagemap *pgmap, int nid)
 		}
 	}
 
-	if (need_devmap_managed) {
-		error = devmap_managed_enable_get(pgmap);
-		if (error)
-			return ERR_PTR(error);
-	}
+	devmap_managed_enable_get(pgmap);
 
 	/*
 	 * Clear the pgmap nr_range as it will be incremented for each
diff --git a/mm/truncate.c b/mm/truncate.c
index 18cec39a9f53..960edf5803ca 100644
--- a/mm/truncate.c
+++ b/mm/truncate.c
@@ -528,7 +528,7 @@ void truncate_inode_pages_final(struct address_space *mapping)
 }
 EXPORT_SYMBOL(truncate_inode_pages_final);
 
-unsigned long __invalidate_mapping_pages(struct address_space *mapping,
+static unsigned long __invalidate_mapping_pages(struct address_space *mapping,
 		pgoff_t start, pgoff_t end, unsigned long *nr_pagevec)
 {
 	pgoff_t indices[PAGEVEC_SIZE];
diff --git a/net/atm/lec.c b/net/atm/lec.c
index dbabb65d8b67..7226c784dbe0 100644
--- a/net/atm/lec.c
+++ b/net/atm/lec.c
@@ -954,9 +954,8 @@ static void *lec_seq_next(struct seq_file *seq, void *v, loff_t *pos)
 {
 	struct lec_state *state = seq->private;
 
-	v = lec_get_idx(state, 1);
-	*pos += !!PTR_ERR(v);
-	return v;
+	++*pos;
+	return lec_get_idx(state, 1);
 }
 
 static int lec_seq_show(struct seq_file *seq, void *v)
diff --git a/net/can/Kconfig b/net/can/Kconfig
index 224e5e0283a9..7c9958df91d3 100644
--- a/net/can/Kconfig
+++ b/net/can/Kconfig
@@ -62,8 +62,9 @@ config CAN_ISOTP
 	  communication between CAN nodes via two defined CAN Identifiers.
 	  As CAN frames can only transport a small amount of data bytes
 	  (max. 8 bytes for 'classic' CAN and max. 64 bytes for CAN FD) this
-	  segmentation is needed to transport longer PDUs as needed e.g. for
-	  vehicle diagnosis (UDS, ISO 14229) or IP-over-CAN traffic.
+	  segmentation is needed to transport longer Protocol Data Units (PDU)
+	  as needed e.g. for vehicle diagnosis (UDS, ISO 14229) or IP-over-CAN
+	  traffic.
 	  This protocol driver implements data transfers according to
 	  ISO 15765-2:2016 for 'classic' CAN and CAN FD frame types.
 	  If you want to perform automotive vehicle diagnostic services (UDS),
diff --git a/net/can/isotp.c b/net/can/isotp.c
index 4c2062875893..d78ab13bd8be 100644
--- a/net/can/isotp.c
+++ b/net/can/isotp.c
@@ -252,14 +252,16 @@ static void isotp_rcv_skb(struct sk_buff *skb, struct sock *sk)
 
 static u8 padlen(u8 datalen)
 {
-	const u8 plen[] = {8, 8, 8, 8, 8, 8, 8, 8, 8,		/* 0 - 8 */
-			   12, 12, 12, 12,			/* 9 - 12 */
-			   16, 16, 16, 16,			/* 13 - 16 */
-			   20, 20, 20, 20,			/* 17 - 20 */
-			   24, 24, 24, 24,			/* 21 - 24 */
-			   32, 32, 32, 32, 32, 32, 32, 32,	/* 25 - 32 */
-			   48, 48, 48, 48, 48, 48, 48, 48,	/* 33 - 40 */
-			   48, 48, 48, 48, 48, 48, 48, 48};	/* 41 - 48 */
+	static const u8 plen[] = {
+		8, 8, 8, 8, 8, 8, 8, 8, 8,	/* 0 - 8 */
+		12, 12, 12, 12,			/* 9 - 12 */
+		16, 16, 16, 16,			/* 13 - 16 */
+		20, 20, 20, 20,			/* 17 - 20 */
+		24, 24, 24, 24,			/* 21 - 24 */
+		32, 32, 32, 32, 32, 32, 32, 32,	/* 25 - 32 */
+		48, 48, 48, 48, 48, 48, 48, 48,	/* 33 - 40 */
+		48, 48, 48, 48, 48, 48, 48, 48	/* 41 - 48 */
+	};
 
 	if (datalen > 48)
 		return 64;
@@ -569,10 +571,6 @@ static int isotp_rcv_cf(struct sock *sk, struct canfd_frame *cf, int ae,
 		return 0;
 	}
 
-	/* no creation of flow control frames */
-	if (so->opt.flags & CAN_ISOTP_LISTEN_MODE)
-		return 0;
-
 	/* perform blocksize handling, if enabled */
 	if (!so->rxfc.bs || ++so->rx.bs < so->rxfc.bs) {
 		/* start rx timeout watchdog */
@@ -581,6 +579,10 @@ static int isotp_rcv_cf(struct sock *sk, struct canfd_frame *cf, int ae,
 		return 0;
 	}
 
+	/* no creation of flow control frames */
+	if (so->opt.flags & CAN_ISOTP_LISTEN_MODE)
+		return 0;
+
 	/* we reached the specified blocksize so->rxfc.bs */
 	isotp_send_fc(sk, ae, ISOTP_FC_CTS);
 	return 0;
diff --git a/net/can/j1939/socket.c b/net/can/j1939/socket.c
index 1be4c898b2fa..f23966526a88 100644
--- a/net/can/j1939/socket.c
+++ b/net/can/j1939/socket.c
@@ -475,6 +475,12 @@ static int j1939_sk_bind(struct socket *sock, struct sockaddr *uaddr, int len)
 			goto out_release_sock;
 		}
 
+		if (!(ndev->flags & IFF_UP)) {
+			dev_put(ndev);
+			ret = -ENETDOWN;
+			goto out_release_sock;
+		}
+
 		priv = j1939_netdev_start(ndev);
 		dev_put(ndev);
 		if (IS_ERR(priv)) {
diff --git a/net/can/proc.c b/net/can/proc.c
index 550928b8b8a2..5ea8695f507e 100644
--- a/net/can/proc.c
+++ b/net/can/proc.c
@@ -462,6 +462,9 @@ void can_init_proc(struct net *net)
  */
 void can_remove_proc(struct net *net)
 {
+	if (!net->can.proc_dir)
+		return;
+
 	if (net->can.pde_stats)
 		remove_proc_entry(CAN_PROC_STATS, net->can.proc_dir);
 
@@ -486,6 +489,5 @@ void can_remove_proc(struct net *net)
 	if (net->can.pde_rcvlist_sff)
 		remove_proc_entry(CAN_PROC_RCVLIST_SFF, net->can.proc_dir);
 
-	if (net->can.proc_dir)
-		remove_proc_entry("can", net->proc_net);
+	remove_proc_entry("can", net->proc_net);
 }
diff --git a/net/ipv4/ip_tunnel.c b/net/ipv4/ip_tunnel.c
index 8b04d1dcfec4..ee65c9225178 100644
--- a/net/ipv4/ip_tunnel.c
+++ b/net/ipv4/ip_tunnel.c
@@ -608,9 +608,6 @@ void ip_md_tunnel_xmit(struct sk_buff *skb, struct net_device *dev,
 			ttl = ip4_dst_hoplimit(&rt->dst);
 	}
 
-	if (!df && skb->protocol == htons(ETH_P_IP))
-		df = inner_iph->frag_off & htons(IP_DF);
-
 	headroom += LL_RESERVED_SPACE(rt->dst.dev) + rt->dst.header_len;
 	if (headroom > dev->needed_headroom)
 		dev->needed_headroom = headroom;
diff --git a/net/ipv4/netfilter.c b/net/ipv4/netfilter.c
index a058213b77a7..7c841037c533 100644
--- a/net/ipv4/netfilter.c
+++ b/net/ipv4/netfilter.c
@@ -17,17 +17,19 @@
 #include <net/netfilter/nf_queue.h>
 
 /* route_me_harder function, used by iptable_nat, iptable_mangle + ip_queue */
-int ip_route_me_harder(struct net *net, struct sk_buff *skb, unsigned int addr_type)
+int ip_route_me_harder(struct net *net, struct sock *sk, struct sk_buff *skb, unsigned int addr_type)
 {
 	const struct iphdr *iph = ip_hdr(skb);
 	struct rtable *rt;
 	struct flowi4 fl4 = {};
 	__be32 saddr = iph->saddr;
-	const struct sock *sk = skb_to_full_sk(skb);
-	__u8 flags = sk ? inet_sk_flowi_flags(sk) : 0;
+	__u8 flags;
 	struct net_device *dev = skb_dst(skb)->dev;
 	unsigned int hh_len;
 
+	sk = sk_to_full_sk(sk);
+	flags = sk ? inet_sk_flowi_flags(sk) : 0;
+
 	if (addr_type == RTN_UNSPEC)
 		addr_type = inet_addr_type_dev_table(net, dev, saddr);
 	if (addr_type == RTN_LOCAL || addr_type == RTN_UNICAST)
diff --git a/net/ipv4/netfilter/iptable_mangle.c b/net/ipv4/netfilter/iptable_mangle.c
index f703a717ab1d..833079589273 100644
--- a/net/ipv4/netfilter/iptable_mangle.c
+++ b/net/ipv4/netfilter/iptable_mangle.c
@@ -62,7 +62,7 @@ ipt_mangle_out(struct sk_buff *skb, const struct nf_hook_state *state)
 		    iph->daddr != daddr ||
 		    skb->mark != mark ||
 		    iph->tos != tos) {
-			err = ip_route_me_harder(state->net, skb, RTN_UNSPEC);
+			err = ip_route_me_harder(state->net, state->sk, skb, RTN_UNSPEC);
 			if (err < 0)
 				ret = NF_DROP_ERR(err);
 		}
diff --git a/net/ipv4/netfilter/nf_reject_ipv4.c b/net/ipv4/netfilter/nf_reject_ipv4.c
index 9dcfa4e461b6..93b07739807b 100644
--- a/net/ipv4/netfilter/nf_reject_ipv4.c
+++ b/net/ipv4/netfilter/nf_reject_ipv4.c
@@ -145,7 +145,7 @@ void nf_send_reset(struct net *net, struct sk_buff *oldskb, int hook)
 				   ip4_dst_hoplimit(skb_dst(nskb)));
 	nf_reject_ip_tcphdr_put(nskb, oldskb, oth);
 
-	if (ip_route_me_harder(net, nskb, RTN_UNSPEC))
+	if (ip_route_me_harder(net, nskb->sk, nskb, RTN_UNSPEC))
 		goto free_nskb;
 
 	niph = ip_hdr(nskb);
diff --git a/net/ipv4/xfrm4_tunnel.c b/net/ipv4/xfrm4_tunnel.c
index dc19aff7c2e0..fb0648e7fb32 100644
--- a/net/ipv4/xfrm4_tunnel.c
+++ b/net/ipv4/xfrm4_tunnel.c
@@ -64,14 +64,14 @@ static int xfrm_tunnel_err(struct sk_buff *skb, u32 info)
 static struct xfrm_tunnel xfrm_tunnel_handler __read_mostly = {
 	.handler	=	xfrm_tunnel_rcv,
 	.err_handler	=	xfrm_tunnel_err,
-	.priority	=	3,
+	.priority	=	4,
 };
 
 #if IS_ENABLED(CONFIG_IPV6)
 static struct xfrm_tunnel xfrm64_tunnel_handler __read_mostly = {
 	.handler	=	xfrm_tunnel_rcv,
 	.err_handler	=	xfrm_tunnel_err,
-	.priority	=	2,
+	.priority	=	3,
 };
 #endif
 
diff --git a/net/ipv6/icmp.c b/net/ipv6/icmp.c
index ec448b71bf9a..8956144ea65e 100644
--- a/net/ipv6/icmp.c
+++ b/net/ipv6/icmp.c
@@ -158,7 +158,13 @@ static bool is_ineligible(const struct sk_buff *skb)
 		tp = skb_header_pointer(skb,
 			ptr+offsetof(struct icmp6hdr, icmp6_type),
 			sizeof(_type), &_type);
-		if (!tp || !(*tp & ICMPV6_INFOMSG_MASK))
+
+		/* Based on RFC 8200, Section 4.5 Fragment Header, return
+		 * false if this is a fragment packet with no icmp header info.
+		 */
+		if (!tp && frag_off != 0)
+			return false;
+		else if (!tp || !(*tp & ICMPV6_INFOMSG_MASK))
 			return true;
 	}
 	return false;
diff --git a/net/ipv6/ip6_tunnel.c b/net/ipv6/ip6_tunnel.c
index a0217e5bf3bc..648db3fe508f 100644
--- a/net/ipv6/ip6_tunnel.c
+++ b/net/ipv6/ip6_tunnel.c
@@ -1271,6 +1271,8 @@ route_lookup:
 	if (max_headroom > dev->needed_headroom)
 		dev->needed_headroom = max_headroom;
 
+	skb_set_inner_ipproto(skb, proto);
+
 	err = ip6_tnl_encap(skb, t, &proto, fl6);
 	if (err)
 		return err;
@@ -1280,8 +1282,6 @@ route_lookup:
 		ipv6_push_frag_opts(skb, &opt.ops, &proto);
 	}
 
-	skb_set_inner_ipproto(skb, proto);
-
 	skb_push(skb, sizeof(struct ipv6hdr));
 	skb_reset_network_header(skb);
 	ipv6h = ipv6_hdr(skb);
diff --git a/net/ipv6/netfilter.c b/net/ipv6/netfilter.c
index 6d0e942d082d..ab9a279dd6d4 100644
--- a/net/ipv6/netfilter.c
+++ b/net/ipv6/netfilter.c
@@ -20,10 +20,10 @@
 #include <net/netfilter/ipv6/nf_defrag_ipv6.h>
 #include "../bridge/br_private.h"
 
-int ip6_route_me_harder(struct net *net, struct sk_buff *skb)
+int ip6_route_me_harder(struct net *net, struct sock *sk_partial, struct sk_buff *skb)
 {
 	const struct ipv6hdr *iph = ipv6_hdr(skb);
-	struct sock *sk = sk_to_full_sk(skb->sk);
+	struct sock *sk = sk_to_full_sk(sk_partial);
 	unsigned int hh_len;
 	struct dst_entry *dst;
 	int strict = (ipv6_addr_type(&iph->daddr) &
@@ -84,7 +84,7 @@ static int nf_ip6_reroute(struct sk_buff *skb,
 		if (!ipv6_addr_equal(&iph->daddr, &rt_info->daddr) ||
 		    !ipv6_addr_equal(&iph->saddr, &rt_info->saddr) ||
 		    skb->mark != rt_info->mark)
-			return ip6_route_me_harder(entry->state.net, skb);
+			return ip6_route_me_harder(entry->state.net, entry->state.sk, skb);
 	}
 	return 0;
 }
diff --git a/net/ipv6/netfilter/ip6table_mangle.c b/net/ipv6/netfilter/ip6table_mangle.c
index 1a2748611e00..cee74803d7a1 100644
--- a/net/ipv6/netfilter/ip6table_mangle.c
+++ b/net/ipv6/netfilter/ip6table_mangle.c
@@ -57,7 +57,7 @@ ip6t_mangle_out(struct sk_buff *skb, const struct nf_hook_state *state)
 	     skb->mark != mark ||
 	     ipv6_hdr(skb)->hop_limit != hop_limit ||
 	     flowlabel != *((u_int32_t *)ipv6_hdr(skb)))) {
-		err = ip6_route_me_harder(state->net, skb);
+		err = ip6_route_me_harder(state->net, state->sk, skb);
 		if (err < 0)
 			ret = NF_DROP_ERR(err);
 	}
diff --git a/net/ipv6/reassembly.c b/net/ipv6/reassembly.c
index 1f5d4d196dcc..c8cf1bbad74a 100644
--- a/net/ipv6/reassembly.c
+++ b/net/ipv6/reassembly.c
@@ -42,6 +42,8 @@
 #include <linux/skbuff.h>
 #include <linux/slab.h>
 #include <linux/export.h>
+#include <linux/tcp.h>
+#include <linux/udp.h>
 
 #include <net/sock.h>
 #include <net/snmp.h>
@@ -322,7 +324,9 @@ static int ipv6_frag_rcv(struct sk_buff *skb)
 	struct frag_queue *fq;
 	const struct ipv6hdr *hdr = ipv6_hdr(skb);
 	struct net *net = dev_net(skb_dst(skb)->dev);
-	int iif;
+	__be16 frag_off;
+	int iif, offset;
+	u8 nexthdr;
 
 	if (IP6CB(skb)->flags & IP6SKB_FRAGMENTED)
 		goto fail_hdr;
@@ -351,6 +355,33 @@ static int ipv6_frag_rcv(struct sk_buff *skb)
 		return 1;
 	}
 
+	/* RFC 8200, Section 4.5 Fragment Header:
+	 * If the first fragment does not include all headers through an
+	 * Upper-Layer header, then that fragment should be discarded and
+	 * an ICMP Parameter Problem, Code 3, message should be sent to
+	 * the source of the fragment, with the Pointer field set to zero.
+	 */
+	nexthdr = hdr->nexthdr;
+	offset = ipv6_skip_exthdr(skb, skb_transport_offset(skb), &nexthdr, &frag_off);
+	if (offset >= 0) {
+		/* Check some common protocols' header */
+		if (nexthdr == IPPROTO_TCP)
+			offset += sizeof(struct tcphdr);
+		else if (nexthdr == IPPROTO_UDP)
+			offset += sizeof(struct udphdr);
+		else if (nexthdr == IPPROTO_ICMPV6)
+			offset += sizeof(struct icmp6hdr);
+		else
+			offset += 1;
+
+		if (!(frag_off & htons(IP6_OFFSET)) && offset > skb->len) {
+			__IP6_INC_STATS(net, __in6_dev_get_safely(skb->dev),
+					IPSTATS_MIB_INHDRERRORS);
+			icmpv6_param_prob(skb, ICMPV6_HDR_INCOMP, 0);
+			return -1;
+		}
+	}
+
 	iif = skb->dev ? skb->dev->ifindex : 0;
 	fq = fq_find(net, fhdr->identification, hdr, iif);
 	if (fq) {
diff --git a/net/ipv6/xfrm6_tunnel.c b/net/ipv6/xfrm6_tunnel.c
index 25b7ebda2fab..f696d46e6910 100644
--- a/net/ipv6/xfrm6_tunnel.c
+++ b/net/ipv6/xfrm6_tunnel.c
@@ -303,13 +303,13 @@ static const struct xfrm_type xfrm6_tunnel_type = {
 static struct xfrm6_tunnel xfrm6_tunnel_handler __read_mostly = {
 	.handler	= xfrm6_tunnel_rcv,
 	.err_handler	= xfrm6_tunnel_err,
-	.priority	= 2,
+	.priority	= 3,
 };
 
 static struct xfrm6_tunnel xfrm46_tunnel_handler __read_mostly = {
 	.handler	= xfrm6_tunnel_rcv,
 	.err_handler	= xfrm6_tunnel_err,
-	.priority	= 2,
+	.priority	= 3,
 };
 
 static int __net_init xfrm6_tunnel_net_init(struct net *net)
diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c
index f400240a556f..6adfcb9c06dc 100644
--- a/net/mac80211/mlme.c
+++ b/net/mac80211/mlme.c
@@ -5464,6 +5464,7 @@ int ieee80211_mgd_assoc(struct ieee80211_sub_if_data *sdata,
 			struct cfg80211_assoc_request *req)
 {
 	bool is_6ghz = req->bss->channel->band == NL80211_BAND_6GHZ;
+	bool is_5ghz = req->bss->channel->band == NL80211_BAND_5GHZ;
 	struct ieee80211_local *local = sdata->local;
 	struct ieee80211_if_managed *ifmgd = &sdata->u.mgd;
 	struct ieee80211_bss *bss = (void *)req->bss->priv;
@@ -5616,7 +5617,7 @@ int ieee80211_mgd_assoc(struct ieee80211_sub_if_data *sdata,
 	if (vht_ie && vht_ie[1] >= sizeof(struct ieee80211_vht_cap))
 		memcpy(&assoc_data->ap_vht_cap, vht_ie + 2,
 		       sizeof(struct ieee80211_vht_cap));
-	else if (!is_6ghz)
+	else if (is_5ghz)
 		ifmgd->flags |= IEEE80211_STA_DISABLE_VHT |
 				IEEE80211_STA_DISABLE_HE;
 	rcu_read_unlock();
diff --git a/net/mac80211/sta_info.c b/net/mac80211/sta_info.c
index fb4f2b9b294f..4fe284ff1ea3 100644
--- a/net/mac80211/sta_info.c
+++ b/net/mac80211/sta_info.c
@@ -258,6 +258,24 @@ struct sta_info *sta_info_get_by_idx(struct ieee80211_sub_if_data *sdata,
  */
 void sta_info_free(struct ieee80211_local *local, struct sta_info *sta)
 {
+	/*
+	 * If we had used sta_info_pre_move_state() then we might not
+	 * have gone through the state transitions down again, so do
+	 * it here now (and warn if it's inserted).
+	 *
+	 * This will clear state such as fast TX/RX that may have been
+	 * allocated during state transitions.
+	 */
+	while (sta->sta_state > IEEE80211_STA_NONE) {
+		int ret;
+
+		WARN_ON_ONCE(test_sta_flag(sta, WLAN_STA_INSERTED));
+
+		ret = sta_info_move_state(sta, sta->sta_state - 1);
+		if (WARN_ONCE(ret, "sta_info_move_state() returned %d\n", ret))
+			break;
+	}
+
 	if (sta->rate_ctrl)
 		rate_control_free_sta(sta);
 
diff --git a/net/mac80211/sta_info.h b/net/mac80211/sta_info.h
index 00ae81e9e1a1..7afd07636b81 100644
--- a/net/mac80211/sta_info.h
+++ b/net/mac80211/sta_info.h
@@ -785,7 +785,7 @@ int sta_info_init(struct ieee80211_local *local);
 void sta_info_stop(struct ieee80211_local *local);
 
 /**
- * sta_info_flush - flush matching STA entries from the STA table
+ * __sta_info_flush - flush matching STA entries from the STA table
  *
  * Returns the number of removed STA entries.
  *
@@ -794,6 +794,13 @@ void sta_info_stop(struct ieee80211_local *local);
  */
 int __sta_info_flush(struct ieee80211_sub_if_data *sdata, bool vlans);
 
+/**
+ * sta_info_flush - flush matching STA entries from the STA table
+ *
+ * Returns the number of removed STA entries.
+ *
+ * @sdata: sdata to remove all stations from
+ */
 static inline int sta_info_flush(struct ieee80211_sub_if_data *sdata)
 {
 	return __sta_info_flush(sdata, false);
diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c
index 8ba10a48ded4..56a4d0d20a26 100644
--- a/net/mac80211/tx.c
+++ b/net/mac80211/tx.c
@@ -1942,19 +1942,24 @@ static bool ieee80211_tx(struct ieee80211_sub_if_data *sdata,
 
 /* device xmit handlers */
 
+enum ieee80211_encrypt {
+	ENCRYPT_NO,
+	ENCRYPT_MGMT,
+	ENCRYPT_DATA,
+};
+
 static int ieee80211_skb_resize(struct ieee80211_sub_if_data *sdata,
 				struct sk_buff *skb,
-				int head_need, bool may_encrypt)
+				int head_need,
+				enum ieee80211_encrypt encrypt)
 {
 	struct ieee80211_local *local = sdata->local;
-	struct ieee80211_hdr *hdr;
 	bool enc_tailroom;
 	int tail_need = 0;
 
-	hdr = (struct ieee80211_hdr *) skb->data;
-	enc_tailroom = may_encrypt &&
-		       (sdata->crypto_tx_tailroom_needed_cnt ||
-			ieee80211_is_mgmt(hdr->frame_control));
+	enc_tailroom = encrypt == ENCRYPT_MGMT ||
+		       (encrypt == ENCRYPT_DATA &&
+			sdata->crypto_tx_tailroom_needed_cnt);
 
 	if (enc_tailroom) {
 		tail_need = IEEE80211_ENCRYPT_TAILROOM;
@@ -1985,23 +1990,29 @@ void ieee80211_xmit(struct ieee80211_sub_if_data *sdata,
 {
 	struct ieee80211_local *local = sdata->local;
 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
-	struct ieee80211_hdr *hdr;
+	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
 	int headroom;
-	bool may_encrypt;
+	enum ieee80211_encrypt encrypt;
 
-	may_encrypt = !(info->flags & IEEE80211_TX_INTFL_DONT_ENCRYPT);
+	if (info->flags & IEEE80211_TX_INTFL_DONT_ENCRYPT)
+		encrypt = ENCRYPT_NO;
+	else if (ieee80211_is_mgmt(hdr->frame_control))
+		encrypt = ENCRYPT_MGMT;
+	else
+		encrypt = ENCRYPT_DATA;
 
 	headroom = local->tx_headroom;
-	if (may_encrypt)
+	if (encrypt != ENCRYPT_NO)
 		headroom += sdata->encrypt_headroom;
 	headroom -= skb_headroom(skb);
 	headroom = max_t(int, 0, headroom);
 
-	if (ieee80211_skb_resize(sdata, skb, headroom, may_encrypt)) {
+	if (ieee80211_skb_resize(sdata, skb, headroom, encrypt)) {
 		ieee80211_free_txskb(&local->hw, skb);
 		return;
 	}
 
+	/* reload after potential resize */
 	hdr = (struct ieee80211_hdr *) skb->data;
 	info->control.vif = &sdata->vif;
 
@@ -2828,7 +2839,7 @@ static struct sk_buff *ieee80211_build_hdr(struct ieee80211_sub_if_data *sdata,
 		head_need += sdata->encrypt_headroom;
 		head_need += local->tx_headroom;
 		head_need = max_t(int, 0, head_need);
-		if (ieee80211_skb_resize(sdata, skb, head_need, true)) {
+		if (ieee80211_skb_resize(sdata, skb, head_need, ENCRYPT_DATA)) {
 			ieee80211_free_txskb(&local->hw, skb);
 			skb = NULL;
 			return ERR_PTR(-ENOMEM);
@@ -3502,7 +3513,7 @@ static bool ieee80211_xmit_fast(struct ieee80211_sub_if_data *sdata,
 	if (unlikely(ieee80211_skb_resize(sdata, skb,
 					  max_t(int, extra_head + hw_headroom -
 						     skb_headroom(skb), 0),
-					  false))) {
+					  ENCRYPT_NO))) {
 		kfree_skb(skb);
 		return true;
 	}
@@ -3619,13 +3630,14 @@ begin:
 	tx.skb = skb;
 	tx.sdata = vif_to_sdata(info->control.vif);
 
-	if (txq->sta && !(info->flags & IEEE80211_TX_CTL_INJECTED)) {
+	if (txq->sta) {
 		tx.sta = container_of(txq->sta, struct sta_info, sta);
 		/*
 		 * Drop unicast frames to unauthorised stations unless they are
-		 * EAPOL frames from the local station.
+		 * injected frames or EAPOL frames from the local station.
 		 */
-		if (unlikely(ieee80211_is_data(hdr->frame_control) &&
+		if (unlikely(!(info->flags & IEEE80211_TX_CTL_INJECTED) &&
+			     ieee80211_is_data(hdr->frame_control) &&
 			     !ieee80211_vif_is_mesh(&tx.sdata->vif) &&
 			     tx.sdata->vif.type != NL80211_IFTYPE_OCB &&
 			     !is_multicast_ether_addr(hdr->addr1) &&
diff --git a/net/mptcp/token.c b/net/mptcp/token.c
index 8b47c4bb1c6b..feb4b9ffd462 100644
--- a/net/mptcp/token.c
+++ b/net/mptcp/token.c
@@ -291,7 +291,7 @@ struct mptcp_sock *mptcp_token_iter_next(const struct net *net, long *s_slot,
 {
 	struct mptcp_sock *ret = NULL;
 	struct hlist_nulls_node *pos;
-	int slot, num;
+	int slot, num = 0;
 
 	for (slot = *s_slot; slot <= token_mask; *s_num = 0, slot++) {
 		struct token_bucket *bucket = &token_hash[slot];
diff --git a/net/netfilter/ipset/ip_set_core.c b/net/netfilter/ipset/ip_set_core.c
index 6f35832f0de3..7cff6e5e7445 100644
--- a/net/netfilter/ipset/ip_set_core.c
+++ b/net/netfilter/ipset/ip_set_core.c
@@ -637,13 +637,14 @@ ip_set_match_extensions(struct ip_set *set, const struct ip_set_ext *ext,
 	if (SET_WITH_COUNTER(set)) {
 		struct ip_set_counter *counter = ext_counter(data, set);
 
+		ip_set_update_counter(counter, ext, flags);
+
 		if (flags & IPSET_FLAG_MATCH_COUNTERS &&
 		    !(ip_set_match_counter(ip_set_get_packets(counter),
 				mext->packets, mext->packets_op) &&
 		      ip_set_match_counter(ip_set_get_bytes(counter),
 				mext->bytes, mext->bytes_op)))
 			return false;
-		ip_set_update_counter(counter, ext, flags);
 	}
 	if (SET_WITH_SKBINFO(set))
 		ip_set_get_skbinfo(ext_skbinfo(data, set),
diff --git a/net/netfilter/ipvs/ip_vs_core.c b/net/netfilter/ipvs/ip_vs_core.c
index cc3c275934f4..c0b8215ab3d4 100644
--- a/net/netfilter/ipvs/ip_vs_core.c
+++ b/net/netfilter/ipvs/ip_vs_core.c
@@ -742,12 +742,12 @@ static int ip_vs_route_me_harder(struct netns_ipvs *ipvs, int af,
 		struct dst_entry *dst = skb_dst(skb);
 
 		if (dst->dev && !(dst->dev->flags & IFF_LOOPBACK) &&
-		    ip6_route_me_harder(ipvs->net, skb) != 0)
+		    ip6_route_me_harder(ipvs->net, skb->sk, skb) != 0)
 			return 1;
 	} else
 #endif
 		if (!(skb_rtable(skb)->rt_flags & RTCF_LOCAL) &&
-		    ip_route_me_harder(ipvs->net, skb, RTN_LOCAL) != 0)
+		    ip_route_me_harder(ipvs->net, skb->sk, skb, RTN_LOCAL) != 0)
 			return 1;
 
 	return 0;
diff --git a/net/netfilter/nf_nat_proto.c b/net/netfilter/nf_nat_proto.c
index 59151dc07fdc..e87b6bd6b3cd 100644
--- a/net/netfilter/nf_nat_proto.c
+++ b/net/netfilter/nf_nat_proto.c
@@ -715,7 +715,7 @@ nf_nat_ipv4_local_fn(void *priv, struct sk_buff *skb,
 
 		if (ct->tuplehash[dir].tuple.dst.u3.ip !=
 		    ct->tuplehash[!dir].tuple.src.u3.ip) {
-			err = ip_route_me_harder(state->net, skb, RTN_UNSPEC);
+			err = ip_route_me_harder(state->net, state->sk, skb, RTN_UNSPEC);
 			if (err < 0)
 				ret = NF_DROP_ERR(err);
 		}
@@ -953,7 +953,7 @@ nf_nat_ipv6_local_fn(void *priv, struct sk_buff *skb,
 
 		if (!nf_inet_addr_cmp(&ct->tuplehash[dir].tuple.dst.u3,
 				      &ct->tuplehash[!dir].tuple.src.u3)) {
-			err = nf_ip6_route_me_harder(state->net, skb);
+			err = nf_ip6_route_me_harder(state->net, state->sk, skb);
 			if (err < 0)
 				ret = NF_DROP_ERR(err);
 		}
diff --git a/net/netfilter/nf_synproxy_core.c b/net/netfilter/nf_synproxy_core.c
index 9cca35d22927..d7d34a62d3bf 100644
--- a/net/netfilter/nf_synproxy_core.c
+++ b/net/netfilter/nf_synproxy_core.c
@@ -446,7 +446,7 @@ synproxy_send_tcp(struct net *net,
 
 	skb_dst_set_noref(nskb, skb_dst(skb));
 	nskb->protocol = htons(ETH_P_IP);
-	if (ip_route_me_harder(net, nskb, RTN_UNSPEC))
+	if (ip_route_me_harder(net, nskb->sk, nskb, RTN_UNSPEC))
 		goto free_nskb;
 
 	if (nfct) {
diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
index 65cb8e3c13d9..0f58e98542be 100644
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
@@ -7137,7 +7137,7 @@ static void nf_tables_flowtable_notify(struct nft_ctx *ctx,
 			GFP_KERNEL);
 	kfree(buf);
 
-	if (ctx->report &&
+	if (!ctx->report &&
 	    !nfnetlink_has_listeners(ctx->net, NFNLGRP_NFTABLES))
 		return;
 
@@ -7259,7 +7259,7 @@ static void nf_tables_gen_notify(struct net *net, struct sk_buff *skb,
 	audit_log_nfcfg("?:0;?:0", 0, net->nft.base_seq,
 			AUDIT_NFT_OP_GEN_REGISTER, GFP_KERNEL);
 
-	if (nlmsg_report(nlh) &&
+	if (!nlmsg_report(nlh) &&
 	    !nfnetlink_has_listeners(net, NFNLGRP_NFTABLES))
 		return;
 
@@ -8053,12 +8053,16 @@ static void nf_tables_abort_release(struct nft_trans *trans)
 	kfree(trans);
 }
 
-static int __nf_tables_abort(struct net *net, bool autoload)
+static int __nf_tables_abort(struct net *net, enum nfnl_abort_action action)
 {
 	struct nft_trans *trans, *next;
 	struct nft_trans_elem *te;
 	struct nft_hook *hook;
 
+	if (action == NFNL_ABORT_VALIDATE &&
+	    nf_tables_validate(net) < 0)
+		return -EAGAIN;
+
 	list_for_each_entry_safe_reverse(trans, next, &net->nft.commit_list,
 					 list) {
 		switch (trans->msg_type) {
@@ -8190,7 +8194,7 @@ static int __nf_tables_abort(struct net *net, bool autoload)
 		nf_tables_abort_release(trans);
 	}
 
-	if (autoload)
+	if (action == NFNL_ABORT_AUTOLOAD)
 		nf_tables_module_autoload(net);
 	else
 		nf_tables_module_autoload_cleanup(net);
@@ -8203,9 +8207,10 @@ static void nf_tables_cleanup(struct net *net)
 	nft_validate_state_update(net, NFT_VALIDATE_SKIP);
 }
 
-static int nf_tables_abort(struct net *net, struct sk_buff *skb, bool autoload)
+static int nf_tables_abort(struct net *net, struct sk_buff *skb,
+			   enum nfnl_abort_action action)
 {
-	int ret = __nf_tables_abort(net, autoload);
+	int ret = __nf_tables_abort(net, action);
 
 	mutex_unlock(&net->nft.commit_mutex);
 
@@ -8836,7 +8841,7 @@ static void __net_exit nf_tables_exit_net(struct net *net)
 {
 	mutex_lock(&net->nft.commit_mutex);
 	if (!list_empty(&net->nft.commit_list))
-		__nf_tables_abort(net, false);
+		__nf_tables_abort(net, NFNL_ABORT_NONE);
 	__nft_release_tables(net);
 	mutex_unlock(&net->nft.commit_mutex);
 	WARN_ON_ONCE(!list_empty(&net->nft.tables));
diff --git a/net/netfilter/nfnetlink.c b/net/netfilter/nfnetlink.c
index 2daa1f6ae344..d3df66a39b5e 100644
--- a/net/netfilter/nfnetlink.c
+++ b/net/netfilter/nfnetlink.c
@@ -333,7 +333,7 @@ static void nfnetlink_rcv_batch(struct sk_buff *skb, struct nlmsghdr *nlh,
 		return netlink_ack(skb, nlh, -EINVAL, NULL);
 replay:
 	status = 0;
-
+replay_abort:
 	skb = netlink_skb_clone(oskb, GFP_KERNEL);
 	if (!skb)
 		return netlink_ack(oskb, nlh, -ENOMEM, NULL);
@@ -499,7 +499,7 @@ ack:
 	}
 done:
 	if (status & NFNL_BATCH_REPLAY) {
-		ss->abort(net, oskb, true);
+		ss->abort(net, oskb, NFNL_ABORT_AUTOLOAD);
 		nfnl_err_reset(&err_list);
 		kfree_skb(skb);
 		module_put(ss->owner);
@@ -510,11 +510,25 @@ done:
 			status |= NFNL_BATCH_REPLAY;
 			goto done;
 		} else if (err) {
-			ss->abort(net, oskb, false);
+			ss->abort(net, oskb, NFNL_ABORT_NONE);
 			netlink_ack(oskb, nlmsg_hdr(oskb), err, NULL);
 		}
 	} else {
-		ss->abort(net, oskb, false);
+		enum nfnl_abort_action abort_action;
+
+		if (status & NFNL_BATCH_FAILURE)
+			abort_action = NFNL_ABORT_NONE;
+		else
+			abort_action = NFNL_ABORT_VALIDATE;
+
+		err = ss->abort(net, oskb, abort_action);
+		if (err == -EAGAIN) {
+			nfnl_err_reset(&err_list);
+			kfree_skb(skb);
+			module_put(ss->owner);
+			status |= NFNL_BATCH_FAILURE;
+			goto replay_abort;
+		}
 	}
 	if (ss->cleanup)
 		ss->cleanup(net);
diff --git a/net/netfilter/nft_chain_route.c b/net/netfilter/nft_chain_route.c
index 8826bbe71136..edd02cda57fc 100644
--- a/net/netfilter/nft_chain_route.c
+++ b/net/netfilter/nft_chain_route.c
@@ -42,7 +42,7 @@ static unsigned int nf_route_table_hook4(void *priv,
 		    iph->daddr != daddr ||
 		    skb->mark != mark ||
 		    iph->tos != tos) {
-			err = ip_route_me_harder(state->net, skb, RTN_UNSPEC);
+			err = ip_route_me_harder(state->net, state->sk, skb, RTN_UNSPEC);
 			if (err < 0)
 				ret = NF_DROP_ERR(err);
 		}
@@ -92,7 +92,7 @@ static unsigned int nf_route_table_hook6(void *priv,
 	     skb->mark != mark ||
 	     ipv6_hdr(skb)->hop_limit != hop_limit ||
 	     flowlabel != *((u32 *)ipv6_hdr(skb)))) {
-		err = nf_ip6_route_me_harder(state->net, skb);
+		err = nf_ip6_route_me_harder(state->net, state->sk, skb);
 		if (err < 0)
 			ret = NF_DROP_ERR(err);
 	}
diff --git a/net/netfilter/utils.c b/net/netfilter/utils.c
index cedf47ab3c6f..2182d361e273 100644
--- a/net/netfilter/utils.c
+++ b/net/netfilter/utils.c
@@ -191,8 +191,8 @@ static int nf_ip_reroute(struct sk_buff *skb, const struct nf_queue_entry *entry
 		      skb->mark == rt_info->mark &&
 		      iph->daddr == rt_info->daddr &&
 		      iph->saddr == rt_info->saddr))
-			return ip_route_me_harder(entry->state.net, skb,
-						  RTN_UNSPEC);
+			return ip_route_me_harder(entry->state.net, entry->state.sk,
+						  skb, RTN_UNSPEC);
 	}
 #endif
 	return 0;
diff --git a/net/openvswitch/datapath.c b/net/openvswitch/datapath.c
index 832f898edb6a..9d6ef6cb9b26 100644
--- a/net/openvswitch/datapath.c
+++ b/net/openvswitch/datapath.c
@@ -1703,13 +1703,13 @@ static int ovs_dp_cmd_new(struct sk_buff *skb, struct genl_info *info)
 	parms.port_no = OVSP_LOCAL;
 	parms.upcall_portids = a[OVS_DP_ATTR_UPCALL_PID];
 
-	err = ovs_dp_change(dp, a);
-	if (err)
-		goto err_destroy_meters;
-
 	/* So far only local changes have been made, now need the lock. */
 	ovs_lock();
 
+	err = ovs_dp_change(dp, a);
+	if (err)
+		goto err_unlock_and_destroy_meters;
+
 	vport = new_vport(&parms);
 	if (IS_ERR(vport)) {
 		err = PTR_ERR(vport);
@@ -1725,8 +1725,7 @@ static int ovs_dp_cmd_new(struct sk_buff *skb, struct genl_info *info)
 				ovs_dp_reset_user_features(skb, info);
 		}
 
-		ovs_unlock();
-		goto err_destroy_meters;
+		goto err_unlock_and_destroy_meters;
 	}
 
 	err = ovs_dp_cmd_fill_info(dp, reply, info->snd_portid,
@@ -1741,7 +1740,8 @@ static int ovs_dp_cmd_new(struct sk_buff *skb, struct genl_info *info)
 	ovs_notify(&dp_datapath_genl_family, reply, info);
 	return 0;
 
-err_destroy_meters:
+err_unlock_and_destroy_meters:
+	ovs_unlock();
 	ovs_meters_exit(dp);
 err_destroy_ports:
 	kfree(dp->ports);
diff --git a/net/openvswitch/flow_table.c b/net/openvswitch/flow_table.c
index f3486a37361a..c89c8da99f1a 100644
--- a/net/openvswitch/flow_table.c
+++ b/net/openvswitch/flow_table.c
@@ -390,7 +390,7 @@ static struct mask_cache *tbl_mask_cache_alloc(u32 size)
 }
 int ovs_flow_tbl_masks_cache_resize(struct flow_table *table, u32 size)
 {
-	struct mask_cache *mc = rcu_dereference(table->mask_cache);
+	struct mask_cache *mc = rcu_dereference_ovsl(table->mask_cache);
 	struct mask_cache *new;
 
 	if (size == mc->cache_size)
diff --git a/net/sctp/sm_sideeffect.c b/net/sctp/sm_sideeffect.c
index aa821e71f05e..813d30767204 100644
--- a/net/sctp/sm_sideeffect.c
+++ b/net/sctp/sm_sideeffect.c
@@ -1601,12 +1601,12 @@ static int sctp_cmd_interpreter(enum sctp_event_type event_type,
 			break;
 
 		case SCTP_CMD_INIT_FAILED:
-			sctp_cmd_init_failed(commands, asoc, cmd->obj.u32);
+			sctp_cmd_init_failed(commands, asoc, cmd->obj.u16);
 			break;
 
 		case SCTP_CMD_ASSOC_FAILED:
 			sctp_cmd_assoc_failed(commands, asoc, event_type,
-					      subtype, chunk, cmd->obj.u32);
+					      subtype, chunk, cmd->obj.u16);
 			break;
 
 		case SCTP_CMD_INIT_COUNTER_INC:
diff --git a/net/wireless/core.c b/net/wireless/core.c
index 9f23923e8d29..240282c083aa 100644
--- a/net/wireless/core.c
+++ b/net/wireless/core.c
@@ -1250,8 +1250,7 @@ void cfg80211_stop_iface(struct wiphy *wiphy, struct wireless_dev *wdev,
 }
 EXPORT_SYMBOL(cfg80211_stop_iface);
 
-void cfg80211_init_wdev(struct cfg80211_registered_device *rdev,
-			struct wireless_dev *wdev)
+void cfg80211_init_wdev(struct wireless_dev *wdev)
 {
 	mutex_init(&wdev->mtx);
 	INIT_LIST_HEAD(&wdev->event_list);
@@ -1262,6 +1261,30 @@ void cfg80211_init_wdev(struct cfg80211_registered_device *rdev,
 	spin_lock_init(&wdev->pmsr_lock);
 	INIT_WORK(&wdev->pmsr_free_wk, cfg80211_pmsr_free_wk);
 
+#ifdef CONFIG_CFG80211_WEXT
+	wdev->wext.default_key = -1;
+	wdev->wext.default_mgmt_key = -1;
+	wdev->wext.connect.auth_type = NL80211_AUTHTYPE_AUTOMATIC;
+#endif
+
+	if (wdev->wiphy->flags & WIPHY_FLAG_PS_ON_BY_DEFAULT)
+		wdev->ps = true;
+	else
+		wdev->ps = false;
+	/* allow mac80211 to determine the timeout */
+	wdev->ps_timeout = -1;
+
+	if ((wdev->iftype == NL80211_IFTYPE_STATION ||
+	     wdev->iftype == NL80211_IFTYPE_P2P_CLIENT ||
+	     wdev->iftype == NL80211_IFTYPE_ADHOC) && !wdev->use_4addr)
+		wdev->netdev->priv_flags |= IFF_DONT_BRIDGE;
+
+	INIT_WORK(&wdev->disconnect_wk, cfg80211_autodisconnect_wk);
+}
+
+void cfg80211_register_wdev(struct cfg80211_registered_device *rdev,
+			    struct wireless_dev *wdev)
+{
 	/*
 	 * We get here also when the interface changes network namespaces,
 	 * as it's registered into the new one, but we don't want it to
@@ -1295,6 +1318,11 @@ static int cfg80211_netdev_notifier_call(struct notifier_block *nb,
 	switch (state) {
 	case NETDEV_POST_INIT:
 		SET_NETDEV_DEVTYPE(dev, &wiphy_type);
+		wdev->netdev = dev;
+		/* can only change netns with wiphy */
+		dev->features |= NETIF_F_NETNS_LOCAL;
+
+		cfg80211_init_wdev(wdev);
 		break;
 	case NETDEV_REGISTER:
 		/*
@@ -1302,35 +1330,12 @@ static int cfg80211_netdev_notifier_call(struct notifier_block *nb,
 		 * called within code protected by it when interfaces
 		 * are added with nl80211.
 		 */
-		/* can only change netns with wiphy */
-		dev->features |= NETIF_F_NETNS_LOCAL;
-
 		if (sysfs_create_link(&dev->dev.kobj, &rdev->wiphy.dev.kobj,
 				      "phy80211")) {
 			pr_err("failed to add phy80211 symlink to netdev!\n");
 		}
-		wdev->netdev = dev;
-#ifdef CONFIG_CFG80211_WEXT
-		wdev->wext.default_key = -1;
-		wdev->wext.default_mgmt_key = -1;
-		wdev->wext.connect.auth_type = NL80211_AUTHTYPE_AUTOMATIC;
-#endif
-
-		if (wdev->wiphy->flags & WIPHY_FLAG_PS_ON_BY_DEFAULT)
-			wdev->ps = true;
-		else
-			wdev->ps = false;
-		/* allow mac80211 to determine the timeout */
-		wdev->ps_timeout = -1;
-
-		if ((wdev->iftype == NL80211_IFTYPE_STATION ||
-		     wdev->iftype == NL80211_IFTYPE_P2P_CLIENT ||
-		     wdev->iftype == NL80211_IFTYPE_ADHOC) && !wdev->use_4addr)
-			dev->priv_flags |= IFF_DONT_BRIDGE;
-
-		INIT_WORK(&wdev->disconnect_wk, cfg80211_autodisconnect_wk);
 
-		cfg80211_init_wdev(rdev, wdev);
+		cfg80211_register_wdev(rdev, wdev);
 		break;
 	case NETDEV_GOING_DOWN:
 		cfg80211_leave(rdev, wdev);
diff --git a/net/wireless/core.h b/net/wireless/core.h
index e1ec9ac8e608..e3e9686859d4 100644
--- a/net/wireless/core.h
+++ b/net/wireless/core.h
@@ -209,8 +209,9 @@ struct wiphy *wiphy_idx_to_wiphy(int wiphy_idx);
 int cfg80211_switch_netns(struct cfg80211_registered_device *rdev,
 			  struct net *net);
 
-void cfg80211_init_wdev(struct cfg80211_registered_device *rdev,
-			struct wireless_dev *wdev);
+void cfg80211_init_wdev(struct wireless_dev *wdev);
+void cfg80211_register_wdev(struct cfg80211_registered_device *rdev,
+			    struct wireless_dev *wdev);
 
 static inline void wdev_lock(struct wireless_dev *wdev)
 	__acquires(wdev)
diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index 554796a6c6fe..a77174b99b07 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -3885,7 +3885,8 @@ static int nl80211_new_interface(struct sk_buff *skb, struct genl_info *info)
 		 * P2P Device and NAN do not have a netdev, so don't go
 		 * through the netdev notifier and must be added here
 		 */
-		cfg80211_init_wdev(rdev, wdev);
+		cfg80211_init_wdev(wdev);
+		cfg80211_register_wdev(rdev, wdev);
 		break;
 	default:
 		break;
diff --git a/net/wireless/reg.c b/net/wireless/reg.c
index 3dab859641e1..a04fdfb35f07 100644
--- a/net/wireless/reg.c
+++ b/net/wireless/reg.c
@@ -3616,7 +3616,7 @@ static void print_rd_rules(const struct ieee80211_regdomain *rd)
 		power_rule = &reg_rule->power_rule;
 
 		if (reg_rule->flags & NL80211_RRF_AUTO_BW)
-			snprintf(bw, sizeof(bw), "%d KHz, %d KHz AUTO",
+			snprintf(bw, sizeof(bw), "%d KHz, %u KHz AUTO",
 				 freq_range->max_bandwidth_khz,
 				 reg_get_max_bandwidth(rd, reg_rule));
 		else
diff --git a/net/xfrm/xfrm_interface.c b/net/xfrm/xfrm_interface.c
index aa4cdcf69d47..9b8e292a7c6a 100644
--- a/net/xfrm/xfrm_interface.c
+++ b/net/xfrm/xfrm_interface.c
@@ -803,14 +803,14 @@ static struct xfrm6_tunnel xfrmi_ipv6_handler __read_mostly = {
 	.handler	=	xfrmi6_rcv_tunnel,
 	.cb_handler	=	xfrmi_rcv_cb,
 	.err_handler	=	xfrmi6_err,
-	.priority	=	-1,
+	.priority	=	2,
 };
 
 static struct xfrm6_tunnel xfrmi_ip6ip_handler __read_mostly = {
 	.handler	=	xfrmi6_rcv_tunnel,
 	.cb_handler	=	xfrmi_rcv_cb,
 	.err_handler	=	xfrmi6_err,
-	.priority	=	-1,
+	.priority	=	2,
 };
 #endif
 
@@ -848,14 +848,14 @@ static struct xfrm_tunnel xfrmi_ipip_handler __read_mostly = {
 	.handler	=	xfrmi4_rcv_tunnel,
 	.cb_handler	=	xfrmi_rcv_cb,
 	.err_handler	=	xfrmi4_err,
-	.priority	=	-1,
+	.priority	=	3,
 };
 
 static struct xfrm_tunnel xfrmi_ipip6_handler __read_mostly = {
 	.handler	=	xfrmi4_rcv_tunnel,
 	.cb_handler	=	xfrmi_rcv_cb,
 	.err_handler	=	xfrmi4_err,
-	.priority	=	-1,
+	.priority	=	2,
 };
 #endif
 
diff --git a/net/xfrm/xfrm_state.c b/net/xfrm/xfrm_state.c
index bbd4643d7e82..a77da7aae6fe 100644
--- a/net/xfrm/xfrm_state.c
+++ b/net/xfrm/xfrm_state.c
@@ -2004,6 +2004,7 @@ int xfrm_alloc_spi(struct xfrm_state *x, u32 low, u32 high)
 	int err = -ENOENT;
 	__be32 minspi = htonl(low);
 	__be32 maxspi = htonl(high);
+	__be32 newspi = 0;
 	u32 mark = x->mark.v & x->mark.m;
 
 	spin_lock_bh(&x->lock);
@@ -2022,21 +2023,22 @@ int xfrm_alloc_spi(struct xfrm_state *x, u32 low, u32 high)
 			xfrm_state_put(x0);
 			goto unlock;
 		}
-		x->id.spi = minspi;
+		newspi = minspi;
 	} else {
 		u32 spi = 0;
 		for (h = 0; h < high-low+1; h++) {
 			spi = low + prandom_u32()%(high-low+1);
 			x0 = xfrm_state_lookup(net, mark, &x->id.daddr, htonl(spi), x->id.proto, x->props.family);
 			if (x0 == NULL) {
-				x->id.spi = htonl(spi);
+				newspi = htonl(spi);
 				break;
 			}
 			xfrm_state_put(x0);
 		}
 	}
-	if (x->id.spi) {
+	if (newspi) {
 		spin_lock_bh(&net->xfrm.xfrm_state_lock);
+		x->id.spi = newspi;
 		h = xfrm_spi_hash(net, &x->id.daddr, x->id.spi, x->id.proto, x->props.family);
 		hlist_add_head_rcu(&x->byspi, net->xfrm.state_byspi + h);
 		spin_unlock_bh(&net->xfrm.xfrm_state_lock);
diff --git a/scripts/get_abi.pl b/scripts/get_abi.pl
index 2cb592f8eba4..68dab828a722 100755
--- a/scripts/get_abi.pl
+++ b/scripts/get_abi.pl
@@ -287,6 +287,8 @@ my $bondary = qr { (?<![\w\/\`\{])(?=[\w\/\`\{])|(?<=[\w\/\`\{])(?![\w\/\`\{]) }
 sub output_rest {
 	create_labels();
 
+	my $part = "";
+
 	foreach my $what (sort {
 				($data{$a}->{type} eq "File") cmp ($data{$b}->{type} eq "File") ||
 				$a cmp $b
@@ -306,6 +308,21 @@ sub output_rest {
 		$w =~ s/([\(\)\_\-\*\=\^\~\\])/\\$1/g;
 
 		if ($type ne "File") {
+			my $cur_part = $what;
+			if ($what =~ '/') {
+				if ($what =~ m#^(\/?(?:[\w\-]+\/?){1,2})#) {
+					$cur_part = "Symbols under $1";
+					$cur_part =~ s,/$,,;
+				}
+			}
+
+			if ($cur_part ne "" && $part ne $cur_part) {
+			    $part = $cur_part;
+			    my $bar = $part;
+			    $bar =~ s/./-/g;
+			    print "$part\n$bar\n\n";
+			}
+
 			printf ".. _%s:\n\n", $data{$what}->{label};
 
 			my @names = split /, /,$w;
@@ -352,6 +369,12 @@ sub output_rest {
 
 		if (!($desc =~ /^\s*$/)) {
 			if ($description_is_rst) {
+				# Remove title markups from the description
+				# Having titles inside ABI files will only work if extra
+				# care would be taken in order to strictly follow the same
+				# level order for each markup.
+				$desc =~ s/\n[\-\*\=\^\~]+\n/\n\n/g;
+
 				# Enrich text by creating cross-references
 
 				$desc =~ s,Documentation/(?!devicetree)(\S+)\.rst,:doc:`/$1`,g;
diff --git a/scripts/kernel-doc b/scripts/kernel-doc
index c8f6b11d5da1..f699cf05d409 100755
--- a/scripts/kernel-doc
+++ b/scripts/kernel-doc
@@ -1092,7 +1092,11 @@ sub output_struct_rst(%) {
 	print "\n\n.. c:type:: " . $name . "\n\n";
     } else {
 	my $name = $args{'struct'};
-	print "\n\n.. c:struct:: " . $name . "\n\n";
+	if ($args{'type'} eq 'union') {
+	    print "\n\n.. c:union:: " . $name . "\n\n";
+	} else {
+	    print "\n\n.. c:struct:: " . $name . "\n\n";
+	}
     }
     print_lineno($declaration_start_line);
     $lineprefix = "   ";
@@ -1427,20 +1431,25 @@ sub dump_enum($$) {
     }
 }
 
+my $typedef_type = qr { ((?:\s+[\w\*]+){1,8})\s* }x;
+my $typedef_ident = qr { \*?\s*(\w\S+)\s* }x;
+my $typedef_args = qr { \s*\((.*)\); }x;
+
+my $typedef1 = qr { typedef$typedef_type\($typedef_ident\)$typedef_args }x;
+my $typedef2 = qr { typedef$typedef_type$typedef_ident$typedef_args }x;
+
 sub dump_typedef($$) {
     my $x = shift;
     my $file = shift;
 
     $x =~ s@/\*.*?\*/@@gos;	# strip comments.
 
-    # Parse function prototypes
-    if ($x =~ /typedef\s+(\w+)\s*\(\*\s*(\w\S+)\s*\)\s*\((.*)\);/ ||
-	$x =~ /typedef\s+(\w+)\s*(\w\S+)\s*\s*\((.*)\);/) {
-
-	# Function typedefs
+    # Parse function typedef prototypes
+    if ($x =~ $typedef1 || $x =~ $typedef2) {
 	$return_type = $1;
 	$declaration_name = $2;
 	my $args = $3;
+	$return_type =~ s/^\s+//;
 
 	create_parameterlist($args, ',', $file, $declaration_name);
 
diff --git a/sound/core/control.c b/sound/core/control.c
index 421ddc76f264..4373de42a5a0 100644
--- a/sound/core/control.c
+++ b/sound/core/control.c
@@ -1925,8 +1925,8 @@ EXPORT_SYMBOL(snd_ctl_unregister_ioctl);
 
 #ifdef CONFIG_COMPAT
 /**
- * snd_ctl_unregister_ioctl - de-register the device-specific compat 32bit
- * control-ioctls
+ * snd_ctl_unregister_ioctl_compat - de-register the device-specific compat
+ * 32bit control-ioctls
  * @fcn: ioctl callback function to unregister
  */
 int snd_ctl_unregister_ioctl_compat(snd_kctl_ioctl_func_t fcn)
diff --git a/sound/core/pcm_dmaengine.c b/sound/core/pcm_dmaengine.c
index 4d059ff2b2e4..4d0e8fe535a1 100644
--- a/sound/core/pcm_dmaengine.c
+++ b/sound/core/pcm_dmaengine.c
@@ -356,7 +356,8 @@ int snd_dmaengine_pcm_close(struct snd_pcm_substream *substream)
 EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_close);
 
 /**
- * snd_dmaengine_pcm_release_chan_close - Close a dmaengine based PCM substream and release channel
+ * snd_dmaengine_pcm_close_release_chan - Close a dmaengine based PCM
+ *					  substream and release channel
  * @substream: PCM substream
  *
  * Releases the DMA channel associated with the PCM substream.
diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c
index d531e1bc2b81..bda3514c7b2d 100644
--- a/sound/core/pcm_lib.c
+++ b/sound/core/pcm_lib.c
@@ -490,7 +490,7 @@ void snd_pcm_set_ops(struct snd_pcm *pcm, int direction,
 EXPORT_SYMBOL(snd_pcm_set_ops);
 
 /**
- * snd_pcm_sync - set the PCM sync id
+ * snd_pcm_set_sync - set the PCM sync id
  * @substream: the pcm substream
  *
  * Sets the PCM sync identifier for the card.
diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index 9e0b2d73faf6..47b155a49226 100644
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
@@ -112,7 +112,7 @@ void snd_pcm_stream_lock(struct snd_pcm_substream *substream)
 EXPORT_SYMBOL_GPL(snd_pcm_stream_lock);
 
 /**
- * snd_pcm_stream_lock - Unlock the PCM stream
+ * snd_pcm_stream_unlock - Unlock the PCM stream
  * @substream: PCM substream
  *
  * This unlocks the PCM stream that has been locked via snd_pcm_stream_lock().
@@ -595,7 +595,7 @@ static void snd_pcm_sync_stop(struct snd_pcm_substream *substream)
 }
 
 /**
- * snd_pcm_hw_param_choose - choose a configuration defined by @params
+ * snd_pcm_hw_params_choose - choose a configuration defined by @params
  * @pcm: PCM instance
  * @params: the hw_params instance
  *
diff --git a/sound/hda/ext/hdac_ext_controller.c b/sound/hda/ext/hdac_ext_controller.c
index 4d060d5b1db6..b0c0ef824d7d 100644
--- a/sound/hda/ext/hdac_ext_controller.c
+++ b/sound/hda/ext/hdac_ext_controller.c
@@ -148,6 +148,8 @@ struct hdac_ext_link *snd_hdac_ext_bus_get_link(struct hdac_bus *bus,
 		return NULL;
 	if (bus->idx != bus_idx)
 		return NULL;
+	if (addr < 0 || addr > 31)
+		return NULL;
 
 	list_for_each_entry(hlink, &bus->hlink_list, list) {
 		for (i = 0; i < HDA_MAX_CODECS; i++) {
diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c
index a356c21edb90..4bb58e8b08a8 100644
--- a/sound/pci/hda/hda_codec.c
+++ b/sound/pci/hda/hda_codec.c
@@ -2934,7 +2934,7 @@ static void hda_call_codec_resume(struct hda_codec *codec)
 	snd_hdac_leave_pm(&codec->core);
 }
 
-static int hda_codec_runtime_suspend(struct device *dev)
+static int hda_codec_suspend(struct device *dev)
 {
 	struct hda_codec *codec = dev_to_hda_codec(dev);
 	unsigned int state;
@@ -2953,7 +2953,7 @@ static int hda_codec_runtime_suspend(struct device *dev)
 	return 0;
 }
 
-static int hda_codec_runtime_resume(struct device *dev)
+static int hda_codec_resume(struct device *dev)
 {
 	struct hda_codec *codec = dev_to_hda_codec(dev);
 
@@ -2967,57 +2967,70 @@ static int hda_codec_runtime_resume(struct device *dev)
 	pm_runtime_mark_last_busy(dev);
 	return 0;
 }
+
+static int hda_codec_runtime_suspend(struct device *dev)
+{
+	return hda_codec_suspend(dev);
+}
+
+static int hda_codec_runtime_resume(struct device *dev)
+{
+	return hda_codec_resume(dev);
+}
+
 #endif /* CONFIG_PM */
 
 #ifdef CONFIG_PM_SLEEP
-static int hda_codec_force_resume(struct device *dev)
+static int hda_codec_pm_prepare(struct device *dev)
+{
+	return pm_runtime_suspended(dev);
+}
+
+static void hda_codec_pm_complete(struct device *dev)
 {
 	struct hda_codec *codec = dev_to_hda_codec(dev);
-	int ret;
 
-	ret = pm_runtime_force_resume(dev);
-	/* schedule jackpoll work for jack detection update */
-	if (codec->jackpoll_interval ||
-	    (pm_runtime_suspended(dev) && hda_codec_need_resume(codec)))
-		schedule_delayed_work(&codec->jackpoll_work,
-				      codec->jackpoll_interval);
-	return ret;
+	if (pm_runtime_suspended(dev) && (codec->jackpoll_interval ||
+	    hda_codec_need_resume(codec) || codec->forced_resume))
+		pm_request_resume(dev);
 }
 
 static int hda_codec_pm_suspend(struct device *dev)
 {
 	dev->power.power_state = PMSG_SUSPEND;
-	return pm_runtime_force_suspend(dev);
+	return hda_codec_suspend(dev);
 }
 
 static int hda_codec_pm_resume(struct device *dev)
 {
 	dev->power.power_state = PMSG_RESUME;
-	return hda_codec_force_resume(dev);
+	return hda_codec_resume(dev);
 }
 
 static int hda_codec_pm_freeze(struct device *dev)
 {
 	dev->power.power_state = PMSG_FREEZE;
-	return pm_runtime_force_suspend(dev);
+	return hda_codec_suspend(dev);
 }
 
 static int hda_codec_pm_thaw(struct device *dev)
 {
 	dev->power.power_state = PMSG_THAW;
-	return hda_codec_force_resume(dev);
+	return hda_codec_resume(dev);
 }
 
 static int hda_codec_pm_restore(struct device *dev)
 {
 	dev->power.power_state = PMSG_RESTORE;
-	return hda_codec_force_resume(dev);
+	return hda_codec_resume(dev);
 }
 #endif /* CONFIG_PM_SLEEP */
 
 /* referred in hda_bind.c */
 const struct dev_pm_ops hda_codec_driver_pm = {
 #ifdef CONFIG_PM_SLEEP
+	.prepare = hda_codec_pm_prepare,
+	.complete = hda_codec_pm_complete,
 	.suspend = hda_codec_pm_suspend,
 	.resume = hda_codec_pm_resume,
 	.freeze = hda_codec_pm_freeze,
diff --git a/sound/pci/hda/hda_controller.h b/sound/pci/hda/hda_controller.h
index be63ead8161f..68f9668788ea 100644
--- a/sound/pci/hda/hda_controller.h
+++ b/sound/pci/hda/hda_controller.h
@@ -41,7 +41,7 @@
 /* 24 unused */
 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)	/* Take LPIB as delay */
 #define AZX_DCAPS_PM_RUNTIME	(1 << 26)	/* runtime PM support */
-#define AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP (1 << 27) /* Workaround for spurious wakeups after suspend */
+/* 27 unused */
 #define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28)	/* CORBRP clears itself after reset */
 #define AZX_DCAPS_NO_MSI64      (1 << 29)	/* Stick to 32-bit MSIs */
 #define AZX_DCAPS_SEPARATE_STREAM_TAG	(1 << 30) /* capture and playback use separate stream tag */
@@ -143,6 +143,7 @@ struct azx {
 	unsigned int align_buffer_size:1;
 	unsigned int region_requested:1;
 	unsigned int disabled:1; /* disabled by vga_switcheroo */
+	unsigned int pm_prepared:1;
 
 	/* GTS present */
 	unsigned int gts_present:1;
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 749b88090970..d539f52009a1 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -297,8 +297,7 @@ enum {
 /* PCH for HSW/BDW; with runtime PM */
 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 #define AZX_DCAPS_INTEL_PCH \
-	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
-	 AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP)
+	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 
 /* HSW HDMI */
 #define AZX_DCAPS_INTEL_HASWELL \
@@ -985,7 +984,7 @@ static void __azx_runtime_suspend(struct azx *chip)
 	display_power(chip, false);
 }
 
-static void __azx_runtime_resume(struct azx *chip, bool from_rt)
+static void __azx_runtime_resume(struct azx *chip)
 {
 	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 	struct hdac_bus *bus = azx_bus(chip);
@@ -1002,7 +1001,8 @@ static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 	azx_init_pci(chip);
 	hda_intel_init_chip(chip, true);
 
-	if (from_rt) {
+	/* Avoid codec resume if runtime resume is for system suspend */
+	if (!chip->pm_prepared) {
 		list_for_each_codec(codec, &chip->bus) {
 			if (codec->relaxed_resume)
 				continue;
@@ -1018,6 +1018,29 @@ static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 }
 
 #ifdef CONFIG_PM_SLEEP
+static int azx_prepare(struct device *dev)
+{
+	struct snd_card *card = dev_get_drvdata(dev);
+	struct azx *chip;
+
+	chip = card->private_data;
+	chip->pm_prepared = 1;
+
+	/* HDA controller always requires different WAKEEN for runtime suspend
+	 * and system suspend, so don't use direct-complete here.
+	 */
+	return 0;
+}
+
+static void azx_complete(struct device *dev)
+{
+	struct snd_card *card = dev_get_drvdata(dev);
+	struct azx *chip;
+
+	chip = card->private_data;
+	chip->pm_prepared = 0;
+}
+
 static int azx_suspend(struct device *dev)
 {
 	struct snd_card *card = dev_get_drvdata(dev);
@@ -1029,15 +1052,7 @@ static int azx_suspend(struct device *dev)
 
 	chip = card->private_data;
 	bus = azx_bus(chip);
-	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
-	/* An ugly workaround: direct call of __azx_runtime_suspend() and
-	 * __azx_runtime_resume() for old Intel platforms that suffer from
-	 * spurious wakeups after S3 suspend
-	 */
-	if (chip->driver_caps & AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP)
-		__azx_runtime_suspend(chip);
-	else
-		pm_runtime_force_suspend(dev);
+	__azx_runtime_suspend(chip);
 	if (bus->irq >= 0) {
 		free_irq(bus->irq, chip);
 		bus->irq = -1;
@@ -1066,11 +1081,7 @@ static int azx_resume(struct device *dev)
 	if (azx_acquire_irq(chip, 1) < 0)
 		return -EIO;
 
-	if (chip->driver_caps & AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP)
-		__azx_runtime_resume(chip, false);
-	else
-		pm_runtime_force_resume(dev);
-	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
+	__azx_runtime_resume(chip);
 
 	trace_azx_resume(chip);
 	return 0;
@@ -1118,10 +1129,7 @@ static int azx_runtime_suspend(struct device *dev)
 	chip = card->private_data;
 
 	/* enable controller wake up event */
-	if (snd_power_get_state(card) == SNDRV_CTL_POWER_D0) {
-		azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
-			   STATESTS_INT_MASK);
-	}
+	azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
 
 	__azx_runtime_suspend(chip);
 	trace_azx_runtime_suspend(chip);
@@ -1132,18 +1140,14 @@ static int azx_runtime_resume(struct device *dev)
 {
 	struct snd_card *card = dev_get_drvdata(dev);
 	struct azx *chip;
-	bool from_rt = snd_power_get_state(card) == SNDRV_CTL_POWER_D0;
 
 	if (!azx_is_pm_ready(card))
 		return 0;
 	chip = card->private_data;
-	__azx_runtime_resume(chip, from_rt);
+	__azx_runtime_resume(chip);
 
 	/* disable controller Wake Up event*/
-	if (from_rt) {
-		azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
-			   ~STATESTS_INT_MASK);
-	}
+	azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
 
 	trace_azx_runtime_resume(chip);
 	return 0;
@@ -1177,6 +1181,8 @@ static int azx_runtime_idle(struct device *dev)
 static const struct dev_pm_ops azx_pm = {
 	SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
 #ifdef CONFIG_PM_SLEEP
+	.prepare = azx_prepare,
+	.complete = azx_complete,
 	.freeze_noirq = azx_freeze_noirq,
 	.thaw_noirq = azx_thaw_noirq,
 #endif
@@ -2356,6 +2362,7 @@ static int azx_probe_continue(struct azx *chip)
 
 	if (azx_has_pm_runtime(chip)) {
 		pm_runtime_use_autosuspend(&pci->dev);
+		pm_runtime_allow(&pci->dev);
 		pm_runtime_put_autosuspend(&pci->dev);
 	}
 
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index f2398721ac1e..6899089d132e 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -6008,6 +6008,27 @@ static void alc285_fixup_invalidate_dacs(struct hda_codec *codec,
 	snd_hda_override_wcaps(codec, 0x03, 0);
 }
 
+static void alc_combo_jack_hp_jd_restart(struct hda_codec *codec)
+{
+	switch (codec->core.vendor_id) {
+	case 0x10ec0274:
+	case 0x10ec0294:
+	case 0x10ec0225:
+	case 0x10ec0295:
+	case 0x10ec0299:
+		alc_update_coef_idx(codec, 0x4a, 0x8000, 1 << 15); /* Reset HP JD */
+		alc_update_coef_idx(codec, 0x4a, 0x8000, 0 << 15);
+		break;
+	case 0x10ec0235:
+	case 0x10ec0236:
+	case 0x10ec0255:
+	case 0x10ec0256:
+		alc_update_coef_idx(codec, 0x1b, 0x8000, 1 << 15); /* Reset HP JD */
+		alc_update_coef_idx(codec, 0x1b, 0x8000, 0 << 15);
+		break;
+	}
+}
+
 static void alc295_fixup_chromebook(struct hda_codec *codec,
 				    const struct hda_fixup *fix, int action)
 {
@@ -6018,16 +6039,7 @@ static void alc295_fixup_chromebook(struct hda_codec *codec,
 		spec->ultra_low_power = true;
 		break;
 	case HDA_FIXUP_ACT_INIT:
-		switch (codec->core.vendor_id) {
-		case 0x10ec0295:
-			alc_update_coef_idx(codec, 0x4a, 0x8000, 1 << 15); /* Reset HP JD */
-			alc_update_coef_idx(codec, 0x4a, 0x8000, 0 << 15);
-			break;
-		case 0x10ec0236:
-			alc_update_coef_idx(codec, 0x1b, 0x8000, 1 << 15); /* Reset HP JD */
-			alc_update_coef_idx(codec, 0x1b, 0x8000, 0 << 15);
-			break;
-		}
+		alc_combo_jack_hp_jd_restart(codec);
 		break;
 	}
 }
@@ -6083,6 +6095,16 @@ static void  alc285_fixup_hp_gpio_amp_init(struct hda_codec *codec,
 	alc_write_coef_idx(codec, 0x65, 0x0);
 }
 
+static void alc274_fixup_hp_headset_mic(struct hda_codec *codec,
+				    const struct hda_fixup *fix, int action)
+{
+	switch (action) {
+	case HDA_FIXUP_ACT_INIT:
+		alc_combo_jack_hp_jd_restart(codec);
+		break;
+	}
+}
+
 /* for hda_fixup_thinkpad_acpi() */
 #include "thinkpad_helper.c"
 
@@ -6277,6 +6299,8 @@ enum {
 	ALC256_FIXUP_INTEL_NUC8_RUGGED,
 	ALC255_FIXUP_XIAOMI_HEADSET_MIC,
 	ALC274_FIXUP_HP_MIC,
+	ALC274_FIXUP_HP_HEADSET_MIC,
+	ALC256_FIXUP_ASUS_HPE,
 };
 
 static const struct hda_fixup alc269_fixups[] = {
@@ -7664,6 +7688,23 @@ static const struct hda_fixup alc269_fixups[] = {
 			{ }
 		},
 	},
+	[ALC274_FIXUP_HP_HEADSET_MIC] = {
+		.type = HDA_FIXUP_FUNC,
+		.v.func = alc274_fixup_hp_headset_mic,
+		.chained = true,
+		.chain_id = ALC274_FIXUP_HP_MIC
+	},
+	[ALC256_FIXUP_ASUS_HPE] = {
+		.type = HDA_FIXUP_VERBS,
+		.v.verbs = (const struct hda_verb[]) {
+			/* Set EAPD high */
+			{ 0x20, AC_VERB_SET_COEF_INDEX, 0x0f },
+			{ 0x20, AC_VERB_SET_PROC_COEF, 0x7778 },
+			{ }
+		},
+		.chained = true,
+		.chain_id = ALC294_FIXUP_ASUS_HEADSET_MIC
+	},
 };
 
 static const struct snd_pci_quirk alc269_fixup_tbl[] = {
@@ -7815,7 +7856,6 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
 	SND_PCI_QUIRK(0x103c, 0x869d, "HP", ALC236_FIXUP_HP_MUTE_LED),
 	SND_PCI_QUIRK(0x103c, 0x8729, "HP", ALC285_FIXUP_HP_GPIO_LED),
 	SND_PCI_QUIRK(0x103c, 0x8736, "HP", ALC285_FIXUP_HP_GPIO_AMP_INIT),
-	SND_PCI_QUIRK(0x103c, 0x874e, "HP", ALC274_FIXUP_HP_MIC),
 	SND_PCI_QUIRK(0x103c, 0x8760, "HP", ALC285_FIXUP_HP_MUTE_LED),
 	SND_PCI_QUIRK(0x103c, 0x877a, "HP", ALC285_FIXUP_HP_MUTE_LED),
 	SND_PCI_QUIRK(0x103c, 0x877d, "HP", ALC236_FIXUP_HP_MUTE_LED),
@@ -7848,6 +7888,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
 	SND_PCI_QUIRK(0x1043, 0x1bbd, "ASUS Z550MA", ALC255_FIXUP_ASUS_MIC_NO_PRESENCE),
 	SND_PCI_QUIRK(0x1043, 0x1c23, "Asus X55U", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
 	SND_PCI_QUIRK(0x1043, 0x1ccd, "ASUS X555UB", ALC256_FIXUP_ASUS_MIC),
+	SND_PCI_QUIRK(0x1043, 0x1d4e, "ASUS TM420", ALC256_FIXUP_ASUS_HPE),
 	SND_PCI_QUIRK(0x1043, 0x1e11, "ASUS Zephyrus G15", ALC289_FIXUP_ASUS_GA502),
 	SND_PCI_QUIRK(0x1043, 0x1f11, "ASUS Zephyrus G14", ALC289_FIXUP_ASUS_GA401),
 	SND_PCI_QUIRK(0x1043, 0x1881, "ASUS Zephyrus S/M", ALC294_FIXUP_ASUS_GX502_PINS),
@@ -8339,6 +8380,10 @@ static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = {
 		{0x1a, 0x90a70130},
 		{0x1b, 0x90170110},
 		{0x21, 0x03211020}),
+       SND_HDA_PIN_QUIRK(0x10ec0274, 0x103c, "HP", ALC274_FIXUP_HP_HEADSET_MIC,
+		{0x17, 0x90170110},
+		{0x19, 0x03a11030},
+		{0x21, 0x03211020}),
 	SND_HDA_PIN_QUIRK(0x10ec0280, 0x103c, "HP", ALC280_FIXUP_HP_GPIO4,
 		{0x12, 0x90a60130},
 		{0x14, 0x90170110},
diff --git a/sound/soc/atmel/mchp-spdiftx.c b/sound/soc/atmel/mchp-spdiftx.c
index 82c1eecd2528..3bd350afb743 100644
--- a/sound/soc/atmel/mchp-spdiftx.c
+++ b/sound/soc/atmel/mchp-spdiftx.c
@@ -487,7 +487,6 @@ static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream,
 	}
 	mchp_spdiftx_channel_status_write(dev);
 	spin_unlock_irqrestore(&ctrl->lock, flags);
-	mr |= SPDIFTX_MR_VALID1 | SPDIFTX_MR_VALID2;
 
 	if (dev->gclk_enabled) {
 		clk_disable_unprepare(dev->gclk);
diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c
index 097c4e8d9950..c61b17dc2af8 100644
--- a/sound/soc/codecs/cs42l51.c
+++ b/sound/soc/codecs/cs42l51.c
@@ -254,8 +254,28 @@ static const struct snd_soc_dapm_widget cs42l51_dapm_widgets[] = {
 		&cs42l51_adcr_mux_controls),
 };
 
+static int mclk_event(struct snd_soc_dapm_widget *w,
+		      struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
+	struct cs42l51_private *cs42l51 = snd_soc_component_get_drvdata(comp);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		return clk_prepare_enable(cs42l51->mclk_handle);
+	case SND_SOC_DAPM_POST_PMD:
+		/* Delay mclk shutdown to fulfill power-down sequence requirements */
+		msleep(20);
+		clk_disable_unprepare(cs42l51->mclk_handle);
+		break;
+	}
+
+	return 0;
+}
+
 static const struct snd_soc_dapm_widget cs42l51_dapm_mclk_widgets[] = {
-	SND_SOC_DAPM_CLOCK_SUPPLY("MCLK")
+	SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, mclk_event,
+			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 };
 
 static const struct snd_soc_dapm_route cs42l51_routes[] = {
diff --git a/sound/soc/codecs/wcd9335.c b/sound/soc/codecs/wcd9335.c
index f2d9d52ee171..4d2b1ec7c03b 100644
--- a/sound/soc/codecs/wcd9335.c
+++ b/sound/soc/codecs/wcd9335.c
@@ -618,7 +618,7 @@ static const char * const sb_tx8_mux_text[] = {
 	"ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
 };
 
-static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
+static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
diff --git a/sound/soc/codecs/wcd934x.c b/sound/soc/codecs/wcd934x.c
index 35697b072367..40f682f5dab8 100644
--- a/sound/soc/codecs/wcd934x.c
+++ b/sound/soc/codecs/wcd934x.c
@@ -551,7 +551,7 @@ struct wcd_iir_filter_ctl {
 	struct soc_bytes_ext bytes_ext;
 };
 
-static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
+static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
diff --git a/sound/soc/codecs/wsa881x.c b/sound/soc/codecs/wsa881x.c
index 68e774e69c85..4530b74f5921 100644
--- a/sound/soc/codecs/wsa881x.c
+++ b/sound/soc/codecs/wsa881x.c
@@ -1026,6 +1026,8 @@ static struct snd_soc_dai_driver wsa881x_dais[] = {
 		.id = 0,
 		.playback = {
 			.stream_name = "SPKR Playback",
+			.rates = SNDRV_PCM_RATE_48000,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
 			.rate_max = 48000,
 			.rate_min = 48000,
 			.channels_min = 1,
diff --git a/sound/soc/intel/Kconfig b/sound/soc/intel/Kconfig
index d5bae5d1ab6f..a5b446d5af19 100644
--- a/sound/soc/intel/Kconfig
+++ b/sound/soc/intel/Kconfig
@@ -15,22 +15,6 @@ config SND_SOC_INTEL_SST_TOPLEVEL
 
 if SND_SOC_INTEL_SST_TOPLEVEL
 
-config SND_SST_IPC
-	tristate
-	# This option controls the IPC core for HiFi2 platforms
-
-config SND_SST_IPC_PCI
-	tristate
-	select SND_SST_IPC
-	# This option controls the PCI-based IPC for HiFi2 platforms
-	#  (Medfield, Merrifield).
-
-config SND_SST_IPC_ACPI
-	tristate
-	select SND_SST_IPC
-	# This option controls the ACPI-based IPC for HiFi2 platforms
-	# (Baytrail, Cherrytrail)
-
 config SND_SOC_INTEL_SST
 	tristate
 
@@ -57,7 +41,6 @@ config SND_SST_ATOM_HIFI2_PLATFORM
 config SND_SST_ATOM_HIFI2_PLATFORM_PCI
 	tristate "PCI HiFi2 (Merrifield) Platforms"
 	depends on X86 && PCI
-	select SND_SST_IPC_PCI
 	select SND_SST_ATOM_HIFI2_PLATFORM
 	help
 	  If you have a Intel Merrifield/Edison platform, then
@@ -70,7 +53,6 @@ config SND_SST_ATOM_HIFI2_PLATFORM_ACPI
 	tristate "ACPI HiFi2 (Baytrail, Cherrytrail) Platforms"
 	default ACPI
 	depends on X86 && ACPI && PCI
-	select SND_SST_IPC_ACPI
 	select SND_SST_ATOM_HIFI2_PLATFORM
 	select SND_SOC_ACPI_INTEL_MATCH
 	select IOSF_MBI
diff --git a/sound/soc/intel/atom/Makefile b/sound/soc/intel/atom/Makefile
index a9326d5ec44c..c66f03f5d8d6 100644
--- a/sound/soc/intel/atom/Makefile
+++ b/sound/soc/intel/atom/Makefile
@@ -6,4 +6,4 @@ snd-soc-sst-atom-hifi2-platform-objs :=	sst-mfld-platform-pcm.o \
 obj-$(CONFIG_SND_SST_ATOM_HIFI2_PLATFORM) += snd-soc-sst-atom-hifi2-platform.o
 
 # DSP driver
-obj-$(CONFIG_SND_SST_IPC) += sst/
+obj-$(CONFIG_SND_SST_ATOM_HIFI2_PLATFORM) += sst/
diff --git a/sound/soc/intel/atom/sst/Makefile b/sound/soc/intel/atom/sst/Makefile
index f17c905df3e2..5761d30a5f9d 100644
--- a/sound/soc/intel/atom/sst/Makefile
+++ b/sound/soc/intel/atom/sst/Makefile
@@ -3,6 +3,6 @@ snd-intel-sst-core-objs := sst.o sst_ipc.o sst_stream.o sst_drv_interface.o sst_
 snd-intel-sst-pci-objs += sst_pci.o
 snd-intel-sst-acpi-objs += sst_acpi.o
 
-obj-$(CONFIG_SND_SST_IPC) += snd-intel-sst-core.o
-obj-$(CONFIG_SND_SST_IPC_PCI) += snd-intel-sst-pci.o
-obj-$(CONFIG_SND_SST_IPC_ACPI) += snd-intel-sst-acpi.o
+obj-$(CONFIG_SND_SST_ATOM_HIFI2_PLATFORM) += snd-intel-sst-core.o
+obj-$(CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI) += snd-intel-sst-pci.o
+obj-$(CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI) += snd-intel-sst-acpi.o
diff --git a/sound/soc/intel/boards/kbl_rt5663_max98927.c b/sound/soc/intel/boards/kbl_rt5663_max98927.c
index 3ea4602dfb3e..9a4b3d0973f6 100644
--- a/sound/soc/intel/boards/kbl_rt5663_max98927.c
+++ b/sound/soc/intel/boards/kbl_rt5663_max98927.c
@@ -401,17 +401,40 @@ static int kabylake_ssp_fixup(struct snd_soc_pcm_runtime *rtd,
 	struct snd_interval *chan = hw_param_interval(params,
 			SNDRV_PCM_HW_PARAM_CHANNELS);
 	struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
-	struct snd_soc_dpcm *dpcm = container_of(
-			params, struct snd_soc_dpcm, hw_params);
-	struct snd_soc_dai_link *fe_dai_link = dpcm->fe->dai_link;
-	struct snd_soc_dai_link *be_dai_link = dpcm->be->dai_link;
+	struct snd_soc_dpcm *dpcm, *rtd_dpcm = NULL;
+
+	/*
+	 * The following loop will be called only for playback stream
+	 * In this platform, there is only one playback device on every SSP
+	 */
+	for_each_dpcm_fe(rtd, SNDRV_PCM_STREAM_PLAYBACK, dpcm) {
+		rtd_dpcm = dpcm;
+		break;
+	}
+
+	/*
+	 * This following loop will be called only for capture stream
+	 * In this platform, there is only one capture device on every SSP
+	 */
+	for_each_dpcm_fe(rtd, SNDRV_PCM_STREAM_CAPTURE, dpcm) {
+		rtd_dpcm = dpcm;
+		break;
+	}
+
+	if (!rtd_dpcm)
+		return -EINVAL;
+
+	/*
+	 * The above 2 loops are mutually exclusive based on the stream direction,
+	 * thus rtd_dpcm variable will never be overwritten
+	 */
 
 	/*
 	 * The ADSP will convert the FE rate to 48k, stereo, 24 bit
 	 */
-	if (!strcmp(fe_dai_link->name, "Kbl Audio Port") ||
-	    !strcmp(fe_dai_link->name, "Kbl Audio Headset Playback") ||
-	    !strcmp(fe_dai_link->name, "Kbl Audio Capture Port")) {
+	if (!strcmp(rtd_dpcm->fe->dai_link->name, "Kbl Audio Port") ||
+	    !strcmp(rtd_dpcm->fe->dai_link->name, "Kbl Audio Headset Playback") ||
+	    !strcmp(rtd_dpcm->fe->dai_link->name, "Kbl Audio Capture Port")) {
 		rate->min = rate->max = 48000;
 		chan->min = chan->max = 2;
 		snd_mask_none(fmt);
@@ -421,7 +444,7 @@ static int kabylake_ssp_fixup(struct snd_soc_pcm_runtime *rtd,
 	 * The speaker on the SSP0 supports S16_LE and not S24_LE.
 	 * thus changing the mask here
 	 */
-	if (!strcmp(be_dai_link->name, "SSP0-Codec"))
+	if (!strcmp(rtd_dpcm->be->dai_link->name, "SSP0-Codec"))
 		snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
 
 	return 0;
diff --git a/sound/soc/intel/catpt/dsp.c b/sound/soc/intel/catpt/dsp.c
index 7d2968571951..9e807b941732 100644
--- a/sound/soc/intel/catpt/dsp.c
+++ b/sound/soc/intel/catpt/dsp.c
@@ -267,9 +267,12 @@ static int catpt_dsp_select_lpclock(struct catpt_dev *cdev, bool lp, bool waiti)
 					    reg, (reg & CATPT_ISD_DCPWM),
 					    500, 10000);
 		if (ret) {
-			dev_err(cdev->dev, "await WAITI timeout\n");
-			mutex_unlock(&cdev->clk_mutex);
-			return ret;
+			dev_warn(cdev->dev, "await WAITI timeout\n");
+			/* no signal - only high clock selection allowed */
+			if (lp) {
+				mutex_unlock(&cdev->clk_mutex);
+				return 0;
+			}
 		}
 	}
 
diff --git a/sound/soc/intel/catpt/pcm.c b/sound/soc/intel/catpt/pcm.c
index f78018c857b8..ba653ebea7d1 100644
--- a/sound/soc/intel/catpt/pcm.c
+++ b/sound/soc/intel/catpt/pcm.c
@@ -667,7 +667,17 @@ static int catpt_dai_pcm_new(struct snd_soc_pcm_runtime *rtm,
 		break;
 	}
 
+	/* see if this is a new configuration */
+	if (!memcmp(&cdev->devfmt[devfmt.iface], &devfmt, sizeof(devfmt)))
+		return 0;
+
+	pm_runtime_get_sync(cdev->dev);
+
 	ret = catpt_ipc_set_device_format(cdev, &devfmt);
+
+	pm_runtime_mark_last_busy(cdev->dev);
+	pm_runtime_put_autosuspend(cdev->dev);
+
 	if (ret)
 		return CATPT_IPC_ERROR(ret);
 
diff --git a/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c b/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c
index c2c1eb16fcc0..26e7d9a7198f 100644
--- a/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c
+++ b/sound/soc/mediatek/mt8183/mt8183-da7219-max98357.c
@@ -630,15 +630,34 @@ static struct snd_soc_codec_conf mt8183_da7219_rt1015_codec_conf[] = {
 	},
 };
 
+static const struct snd_kcontrol_new mt8183_da7219_rt1015_snd_controls[] = {
+	SOC_DAPM_PIN_SWITCH("Left Spk"),
+	SOC_DAPM_PIN_SWITCH("Right Spk"),
+};
+
+static const
+struct snd_soc_dapm_widget mt8183_da7219_rt1015_dapm_widgets[] = {
+	SND_SOC_DAPM_SPK("Left Spk", NULL),
+	SND_SOC_DAPM_SPK("Right Spk", NULL),
+	SND_SOC_DAPM_PINCTRL("TDM_OUT_PINCTRL",
+			     "aud_tdm_out_on", "aud_tdm_out_off"),
+};
+
+static const struct snd_soc_dapm_route mt8183_da7219_rt1015_dapm_routes[] = {
+	{"Left Spk", NULL, "Left SPO"},
+	{"Right Spk", NULL, "Right SPO"},
+	{"I2S Playback", NULL, "TDM_OUT_PINCTRL"},
+};
+
 static struct snd_soc_card mt8183_da7219_rt1015_card = {
 	.name = "mt8183_da7219_rt1015",
 	.owner = THIS_MODULE,
-	.controls = mt8183_da7219_max98357_snd_controls,
-	.num_controls = ARRAY_SIZE(mt8183_da7219_max98357_snd_controls),
-	.dapm_widgets = mt8183_da7219_max98357_dapm_widgets,
-	.num_dapm_widgets = ARRAY_SIZE(mt8183_da7219_max98357_dapm_widgets),
-	.dapm_routes = mt8183_da7219_max98357_dapm_routes,
-	.num_dapm_routes = ARRAY_SIZE(mt8183_da7219_max98357_dapm_routes),
+	.controls = mt8183_da7219_rt1015_snd_controls,
+	.num_controls = ARRAY_SIZE(mt8183_da7219_rt1015_snd_controls),
+	.dapm_widgets = mt8183_da7219_rt1015_dapm_widgets,
+	.num_dapm_widgets = ARRAY_SIZE(mt8183_da7219_rt1015_dapm_widgets),
+	.dapm_routes = mt8183_da7219_rt1015_dapm_routes,
+	.num_dapm_routes = ARRAY_SIZE(mt8183_da7219_rt1015_dapm_routes),
 	.dai_link = mt8183_da7219_dai_links,
 	.num_links = ARRAY_SIZE(mt8183_da7219_dai_links),
 	.aux_dev = &mt8183_da7219_max98357_headset_dev,
diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c
index ba2aca301a9b..9d17c87445a9 100644
--- a/sound/soc/qcom/lpass-cpu.c
+++ b/sound/soc/qcom/lpass-cpu.c
@@ -80,6 +80,12 @@ static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
 		dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
 		return ret;
 	}
+	ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
+	if (ret) {
+		dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
+		clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
+		return ret;
+	}
 	return 0;
 }
 
@@ -88,9 +94,8 @@ static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
 {
 	struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
 
-	clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
-
 	clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
+	clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
 }
 
 static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
@@ -303,10 +308,10 @@ static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
 			dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
 				ret);
 
-		ret = clk_prepare_enable(drvdata->mi2s_bit_clk[id]);
+		ret = clk_enable(drvdata->mi2s_bit_clk[id]);
 		if (ret) {
 			dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
-			clk_disable_unprepare(drvdata->mi2s_osr_clk[id]);
+			clk_disable(drvdata->mi2s_osr_clk[id]);
 			return ret;
 		}
 
@@ -324,6 +329,7 @@ static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
 		if (ret)
 			dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
 				ret);
+		clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
 		break;
 	}
 
diff --git a/sound/soc/qcom/lpass-sc7180.c b/sound/soc/qcom/lpass-sc7180.c
index c6292f9e613f..bc998d501600 100644
--- a/sound/soc/qcom/lpass-sc7180.c
+++ b/sound/soc/qcom/lpass-sc7180.c
@@ -188,7 +188,7 @@ static struct lpass_variant sc7180_data = {
 	.micmode		= REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
 	.micmono		= REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
 	.wssrc			= REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
-	.bitwidth		= REG_FIELD_ID(0x1000, 0, 0, 3, 0x1000),
+	.bitwidth		= REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
 
 	.rdma_dyncclk		= REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
 	.rdma_bursten		= REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
diff --git a/sound/soc/qcom/sdm845.c b/sound/soc/qcom/sdm845.c
index ab1bf23c21a6..6c2760e27ea6 100644
--- a/sound/soc/qcom/sdm845.c
+++ b/sound/soc/qcom/sdm845.c
@@ -17,6 +17,7 @@
 #include "qdsp6/q6afe.h"
 #include "../codecs/rt5663.h"
 
+#define DRIVER_NAME	"sdm845"
 #define DEFAULT_SAMPLE_RATE_48K		48000
 #define DEFAULT_MCLK_RATE		24576000
 #define TDM_BCLK_RATE		6144000
@@ -552,6 +553,7 @@ static int sdm845_snd_platform_probe(struct platform_device *pdev)
 	if (!data)
 		return -ENOMEM;
 
+	card->driver_name = DRIVER_NAME;
 	card->dapm_widgets = sdm845_snd_widgets;
 	card->num_dapm_widgets = ARRAY_SIZE(sdm845_snd_widgets);
 	card->dev = dev;
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index ea3986a46c12..05a085f6dc7c 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -2341,7 +2341,7 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component,
 }
 
 /**
- * snd_soc_unregister_dai - Unregister DAIs from the ASoC core
+ * snd_soc_unregister_dais - Unregister DAIs from the ASoC core
  *
  * @component: The component for which the DAIs should be unregistered
  */
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 980f2c330b87..7f87b449f950 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -1276,7 +1276,7 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget,
 }
 
 /**
- * snd_soc_dapm_get_connected_widgets - query audio path and it's widgets.
+ * snd_soc_dapm_dai_get_connected_widgets - query audio path and it's widgets.
  * @dai: the soc DAI.
  * @stream: stream direction.
  * @list: list of active widgets for this stream.
diff --git a/sound/soc/sof/loader.c b/sound/soc/sof/loader.c
index 68ed454f7ddf..ba9ed66f98bc 100644
--- a/sound/soc/sof/loader.c
+++ b/sound/soc/sof/loader.c
@@ -118,6 +118,11 @@ int snd_sof_fw_parse_ext_data(struct snd_sof_dev *sdev, u32 bar, u32 offset)
 		case SOF_IPC_EXT_CC_INFO:
 			ret = get_cc_info(sdev, ext_hdr);
 			break;
+		case SOF_IPC_EXT_UNUSED:
+		case SOF_IPC_EXT_PROBE_INFO:
+		case SOF_IPC_EXT_USER_ABI_INFO:
+			/* They are supported but we don't do anything here */
+			break;
 		default:
 			dev_warn(sdev->dev, "warning: unknown ext header type %d size 0x%x\n",
 				 ext_hdr->type, ext_hdr->hdr.size);
diff --git a/sound/usb/pcm.c b/sound/usb/pcm.c
index b401ee894e1b..a860303cc522 100644
--- a/sound/usb/pcm.c
+++ b/sound/usb/pcm.c
@@ -336,6 +336,7 @@ static int set_sync_ep_implicit_fb_quirk(struct snd_usb_substream *subs,
 	switch (subs->stream->chip->usb_id) {
 	case USB_ID(0x0763, 0x2030): /* M-Audio Fast Track C400 */
 	case USB_ID(0x0763, 0x2031): /* M-Audio Fast Track C600 */
+	case USB_ID(0x22f0, 0x0006): /* Allen&Heath Qu-16 */
 		ep = 0x81;
 		ifnum = 3;
 		goto add_sync_ep_from_ifnum;
@@ -345,6 +346,7 @@ static int set_sync_ep_implicit_fb_quirk(struct snd_usb_substream *subs,
 		ifnum = 2;
 		goto add_sync_ep_from_ifnum;
 	case USB_ID(0x2466, 0x8003): /* Fractal Audio Axe-Fx II */
+	case USB_ID(0x0499, 0x172a): /* Yamaha MODX */
 		ep = 0x86;
 		ifnum = 2;
 		goto add_sync_ep_from_ifnum;
@@ -352,6 +354,10 @@ static int set_sync_ep_implicit_fb_quirk(struct snd_usb_substream *subs,
 		ep = 0x81;
 		ifnum = 2;
 		goto add_sync_ep_from_ifnum;
+	case USB_ID(0x1686, 0xf029): /* Zoom UAC-2 */
+		ep = 0x82;
+		ifnum = 2;
+		goto add_sync_ep_from_ifnum;
 	case USB_ID(0x1397, 0x0001): /* Behringer UFX1604 */
 	case USB_ID(0x1397, 0x0002): /* Behringer UFX1204 */
 		ep = 0x81;
diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
index b4fa80ef730d..c989ad8052ae 100644
--- a/sound/usb/quirks.c
+++ b/sound/usb/quirks.c
@@ -1800,6 +1800,7 @@ u64 snd_usb_interface_dsd_format_quirks(struct snd_usb_audio *chip,
 	case 0x278b:  /* Rotel? */
 	case 0x292b:  /* Gustard/Ess based devices */
 	case 0x2ab6:  /* T+A devices */
+	case 0x3353:  /* Khadas devices */
 	case 0x3842:  /* EVGA */
 	case 0xc502:  /* HiBy devices */
 		if (fp->dsd_raw)
diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h b/tools/arch/arm64/include/uapi/asm/kvm.h
index ba85bb23f060..1c17c3a24411 100644
--- a/tools/arch/arm64/include/uapi/asm/kvm.h
+++ b/tools/arch/arm64/include/uapi/asm/kvm.h
@@ -159,6 +159,21 @@ struct kvm_sync_regs {
 struct kvm_arch_memory_slot {
 };
 
+/*
+ * PMU filter structure. Describe a range of events with a particular
+ * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER.
+ */
+struct kvm_pmu_event_filter {
+	__u16	base_event;
+	__u16	nevents;
+
+#define KVM_PMU_EVENT_ALLOW	0
+#define KVM_PMU_EVENT_DENY	1
+
+	__u8	action;
+	__u8	pad[3];
+};
+
 /* for KVM_GET/SET_VCPU_EVENTS */
 struct kvm_vcpu_events {
 	struct {
@@ -242,6 +257,15 @@ struct kvm_vcpu_events {
 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL		0
 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL		1
 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED	2
+
+/*
+ * Only two states can be presented by the host kernel:
+ * - NOT_REQUIRED: the guest doesn't need to do anything
+ * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
+ *
+ * All the other values are deprecated. The host still accepts all
+ * values (they are ABI), but will narrow them to the above two.
+ */
 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2	KVM_REG_ARM_FW_REG(2)
 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL		0
 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN		1
@@ -329,6 +353,7 @@ struct kvm_vcpu_events {
 #define KVM_ARM_VCPU_PMU_V3_CTRL	0
 #define   KVM_ARM_VCPU_PMU_V3_IRQ	0
 #define   KVM_ARM_VCPU_PMU_V3_INIT	1
+#define   KVM_ARM_VCPU_PMU_V3_FILTER	2
 #define KVM_ARM_VCPU_TIMER_CTRL		1
 #define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER		0
 #define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER		1
diff --git a/tools/arch/s390/include/uapi/asm/sie.h b/tools/arch/s390/include/uapi/asm/sie.h
index 6ca1e68d7103..ede318653c87 100644
--- a/tools/arch/s390/include/uapi/asm/sie.h
+++ b/tools/arch/s390/include/uapi/asm/sie.h
@@ -29,7 +29,7 @@
 	{ 0x13, "SIGP conditional emergency signal" },		\
 	{ 0x15, "SIGP sense running" },				\
 	{ 0x16, "SIGP set multithreading"},			\
-	{ 0x17, "SIGP store additional status ait address"}
+	{ 0x17, "SIGP store additional status at address"}
 
 #define icpt_prog_codes						\
 	{ 0x0001, "Prog Operation" },				\
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 2901d5df4366..dad350d42ecf 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -96,7 +96,7 @@
 #define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */
 #define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */
 #define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */
-/* free					( 3*32+17) */
+#define X86_FEATURE_SME_COHERENT	( 3*32+17) /* "" AMD hardware-enforced cache coherency */
 #define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */
 #define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */
 #define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */
@@ -236,6 +236,7 @@
 #define X86_FEATURE_EPT_AD		( 8*32+17) /* Intel Extended Page Table access-dirty bit */
 #define X86_FEATURE_VMCALL		( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
 #define X86_FEATURE_VMW_VMMCALL		( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
+#define X86_FEATURE_SEV_ES		( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
 #define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
@@ -288,6 +289,7 @@
 #define X86_FEATURE_FENCE_SWAPGS_USER	(11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
 #define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
 #define X86_FEATURE_SPLIT_LOCK_DETECT	(11*32+ 6) /* #AC for split lock */
+#define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
 #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
@@ -353,6 +355,7 @@
 #define X86_FEATURE_CLDEMOTE		(16*32+25) /* CLDEMOTE instruction */
 #define X86_FEATURE_MOVDIRI		(16*32+27) /* MOVDIRI instruction */
 #define X86_FEATURE_MOVDIR64B		(16*32+28) /* MOVDIR64B instruction */
+#define X86_FEATURE_ENQCMD		(16*32+29) /* ENQCMD and ENQCMDS instructions */
 
 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
 #define X86_FEATURE_OVERFLOW_RECOV	(17*32+ 0) /* MCA overflow recovery support */
@@ -368,6 +371,7 @@
 #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
 #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
 #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
+#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
diff --git a/tools/arch/x86/include/asm/disabled-features.h b/tools/arch/x86/include/asm/disabled-features.h
index 4ea8584682f9..5861d34f9771 100644
--- a/tools/arch/x86/include/asm/disabled-features.h
+++ b/tools/arch/x86/include/asm/disabled-features.h
@@ -56,6 +56,12 @@
 # define DISABLE_PTI		(1 << (X86_FEATURE_PTI & 31))
 #endif
 
+#ifdef CONFIG_IOMMU_SUPPORT
+# define DISABLE_ENQCMD	0
+#else
+# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))
+#endif
+
 /*
  * Make sure to add features to the correct mask
  */
@@ -75,7 +81,8 @@
 #define DISABLED_MASK13	0
 #define DISABLED_MASK14	0
 #define DISABLED_MASK15	0
-#define DISABLED_MASK16	(DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP)
+#define DISABLED_MASK16	(DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \
+			 DISABLE_ENQCMD)
 #define DISABLED_MASK17	0
 #define DISABLED_MASK18	0
 #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index 2859ee4f39a8..972a34d93505 100644
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -257,6 +257,9 @@
 #define MSR_IA32_LASTINTFROMIP		0x000001dd
 #define MSR_IA32_LASTINTTOIP		0x000001de
 
+#define MSR_IA32_PASID			0x00000d93
+#define MSR_IA32_PASID_VALID		BIT_ULL(31)
+
 /* DEBUGCTLMSR bits (others vary by model): */
 #define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */
 #define DEBUGCTLMSR_BTF_SHIFT		1
@@ -464,11 +467,15 @@
 #define MSR_AMD64_IBSOP_REG_MASK	((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
 #define MSR_AMD64_IBSCTL		0xc001103a
 #define MSR_AMD64_IBSBRTARGET		0xc001103b
+#define MSR_AMD64_ICIBSEXTDCTL		0xc001103c
 #define MSR_AMD64_IBSOPDATA4		0xc001103d
 #define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
+#define MSR_AMD64_SEV_ES_GHCB		0xc0010130
 #define MSR_AMD64_SEV			0xc0010131
 #define MSR_AMD64_SEV_ENABLED_BIT	0
+#define MSR_AMD64_SEV_ES_ENABLED_BIT	1
 #define MSR_AMD64_SEV_ENABLED		BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
+#define MSR_AMD64_SEV_ES_ENABLED	BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
 
 #define MSR_AMD64_VIRT_SPEC_CTRL	0xc001011f
 
@@ -857,11 +864,14 @@
 #define MSR_CORE_PERF_FIXED_CTR0	0x00000309
 #define MSR_CORE_PERF_FIXED_CTR1	0x0000030a
 #define MSR_CORE_PERF_FIXED_CTR2	0x0000030b
+#define MSR_CORE_PERF_FIXED_CTR3	0x0000030c
 #define MSR_CORE_PERF_FIXED_CTR_CTRL	0x0000038d
 #define MSR_CORE_PERF_GLOBAL_STATUS	0x0000038e
 #define MSR_CORE_PERF_GLOBAL_CTRL	0x0000038f
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x00000390
 
+#define MSR_PERF_METRICS		0x00000329
+
 /* PERF_GLOBAL_OVF_CTL bits */
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT	55
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI		(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
diff --git a/tools/arch/x86/include/asm/required-features.h b/tools/arch/x86/include/asm/required-features.h
index 6847d85400a8..3ff0d48469f2 100644
--- a/tools/arch/x86/include/asm/required-features.h
+++ b/tools/arch/x86/include/asm/required-features.h
@@ -54,7 +54,7 @@
 #endif
 
 #ifdef CONFIG_X86_64
-#ifdef CONFIG_PARAVIRT
+#ifdef CONFIG_PARAVIRT_XXL
 /* Paravirtualized systems may not have PSE or PGE available */
 #define NEED_PSE	0
 #define NEED_PGE	0
diff --git a/tools/arch/x86/include/uapi/asm/kvm.h b/tools/arch/x86/include/uapi/asm/kvm.h
index 0780f97c1850..89e5f3d1bba8 100644
--- a/tools/arch/x86/include/uapi/asm/kvm.h
+++ b/tools/arch/x86/include/uapi/asm/kvm.h
@@ -192,6 +192,26 @@ struct kvm_msr_list {
 	__u32 indices[0];
 };
 
+/* Maximum size of any access bitmap in bytes */
+#define KVM_MSR_FILTER_MAX_BITMAP_SIZE 0x600
+
+/* for KVM_X86_SET_MSR_FILTER */
+struct kvm_msr_filter_range {
+#define KVM_MSR_FILTER_READ  (1 << 0)
+#define KVM_MSR_FILTER_WRITE (1 << 1)
+	__u32 flags;
+	__u32 nmsrs; /* number of msrs in bitmap */
+	__u32 base;  /* MSR index the bitmap starts at */
+	__u8 *bitmap; /* a 1 bit allows the operations in flags, 0 denies */
+};
+
+#define KVM_MSR_FILTER_MAX_RANGES 16
+struct kvm_msr_filter {
+#define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0)
+#define KVM_MSR_FILTER_DEFAULT_DENY  (1 << 0)
+	__u32 flags;
+	struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES];
+};
 
 struct kvm_cpuid_entry {
 	__u32 function;
diff --git a/tools/arch/x86/include/uapi/asm/svm.h b/tools/arch/x86/include/uapi/asm/svm.h
index 2e8a30f06c74..f1d8307454e0 100644
--- a/tools/arch/x86/include/uapi/asm/svm.h
+++ b/tools/arch/x86/include/uapi/asm/svm.h
@@ -29,6 +29,7 @@
 #define SVM_EXIT_WRITE_DR6     0x036
 #define SVM_EXIT_WRITE_DR7     0x037
 #define SVM_EXIT_EXCP_BASE     0x040
+#define SVM_EXIT_LAST_EXCP     0x05f
 #define SVM_EXIT_INTR          0x060
 #define SVM_EXIT_NMI           0x061
 #define SVM_EXIT_SMI           0x062
@@ -76,10 +77,21 @@
 #define SVM_EXIT_MWAIT_COND    0x08c
 #define SVM_EXIT_XSETBV        0x08d
 #define SVM_EXIT_RDPRU         0x08e
+#define SVM_EXIT_INVPCID       0x0a2
 #define SVM_EXIT_NPF           0x400
 #define SVM_EXIT_AVIC_INCOMPLETE_IPI		0x401
 #define SVM_EXIT_AVIC_UNACCELERATED_ACCESS	0x402
 
+/* SEV-ES software-defined VMGEXIT events */
+#define SVM_VMGEXIT_MMIO_READ			0x80000001
+#define SVM_VMGEXIT_MMIO_WRITE			0x80000002
+#define SVM_VMGEXIT_NMI_COMPLETE		0x80000003
+#define SVM_VMGEXIT_AP_HLT_LOOP			0x80000004
+#define SVM_VMGEXIT_AP_JUMP_TABLE		0x80000005
+#define SVM_VMGEXIT_SET_AP_JUMP_TABLE		0
+#define SVM_VMGEXIT_GET_AP_JUMP_TABLE		1
+#define SVM_VMGEXIT_UNSUPPORTED_EVENT		0x8000ffff
+
 #define SVM_EXIT_ERR           -1
 
 #define SVM_EXIT_REASONS \
@@ -171,6 +183,7 @@
 	{ SVM_EXIT_MONITOR,     "monitor" }, \
 	{ SVM_EXIT_MWAIT,       "mwait" }, \
 	{ SVM_EXIT_XSETBV,      "xsetbv" }, \
+	{ SVM_EXIT_INVPCID,     "invpcid" }, \
 	{ SVM_EXIT_NPF,         "npf" }, \
 	{ SVM_EXIT_AVIC_INCOMPLETE_IPI,		"avic_incomplete_ipi" }, \
 	{ SVM_EXIT_AVIC_UNACCELERATED_ACCESS,   "avic_unaccelerated_access" }, \
diff --git a/tools/build/feature/test-all.c b/tools/build/feature/test-all.c
index a04e81321c66..464873883396 100644
--- a/tools/build/feature/test-all.c
+++ b/tools/build/feature/test-all.c
@@ -185,7 +185,6 @@ int main(int argc, char *argv[])
 	main_test_libperl();
 	main_test_hello();
 	main_test_libelf();
-	main_test_libelf_mmap();
 	main_test_get_current_dir_name();
 	main_test_gettid();
 	main_test_glibc();
diff --git a/tools/include/linux/compiler-gcc.h b/tools/include/linux/compiler-gcc.h
index b9d4322e1e65..95c072b70d0e 100644
--- a/tools/include/linux/compiler-gcc.h
+++ b/tools/include/linux/compiler-gcc.h
@@ -27,18 +27,6 @@
 #define  __pure		__attribute__((pure))
 #endif
 #define  noinline	__attribute__((noinline))
-#ifdef __has_attribute
-#if __has_attribute(disable_tail_calls)
-#define __no_tail_call	__attribute__((disable_tail_calls))
-#endif
-#endif
-#ifndef __no_tail_call
-#if GCC_VERSION > 40201
-#define __no_tail_call	__attribute__((optimize("no-optimize-sibling-calls")))
-#else
-#define __no_tail_call
-#endif
-#endif
 #ifndef __packed
 #define __packed	__attribute__((packed))
 #endif
diff --git a/tools/include/linux/compiler.h b/tools/include/linux/compiler.h
index 2b3f7353e891..d22a974372c0 100644
--- a/tools/include/linux/compiler.h
+++ b/tools/include/linux/compiler.h
@@ -47,9 +47,6 @@
 #ifndef noinline
 #define noinline
 #endif
-#ifndef __no_tail_call
-#define __no_tail_call
-#endif
 
 /* Are two types/vars the same type (ignoring qualifiers)? */
 #ifndef __same_type
diff --git a/tools/include/uapi/asm-generic/unistd.h b/tools/include/uapi/asm-generic/unistd.h
index f2b5d72a46c2..2056318988f7 100644
--- a/tools/include/uapi/asm-generic/unistd.h
+++ b/tools/include/uapi/asm-generic/unistd.h
@@ -857,9 +857,11 @@ __SYSCALL(__NR_openat2, sys_openat2)
 __SYSCALL(__NR_pidfd_getfd, sys_pidfd_getfd)
 #define __NR_faccessat2 439
 __SYSCALL(__NR_faccessat2, sys_faccessat2)
+#define __NR_process_madvise 440
+__SYSCALL(__NR_process_madvise, sys_process_madvise)
 
 #undef __NR_syscalls
-#define __NR_syscalls 440
+#define __NR_syscalls 441
 
 /*
  * 32 bit systems traditionally used different
diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h
index 00546062e023..fa1f3d62f9a6 100644
--- a/tools/include/uapi/drm/i915_drm.h
+++ b/tools/include/uapi/drm/i915_drm.h
@@ -619,6 +619,12 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_PERF_REVISION	54
 
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
+ * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See
+ * I915_EXEC_USE_EXTENSIONS.
+ */
+#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
+
 /* Must be kept compact -- no holes and well documented */
 
 typedef struct drm_i915_getparam {
@@ -1046,6 +1052,38 @@ struct drm_i915_gem_exec_fence {
 	__u32 flags;
 };
 
+/**
+ * See drm_i915_gem_execbuffer_ext_timeline_fences.
+ */
+#define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
+
+/**
+ * This structure describes an array of drm_syncobj and associated points for
+ * timeline variants of drm_syncobj. It is invalid to append this structure to
+ * the execbuf if I915_EXEC_FENCE_ARRAY is set.
+ */
+struct drm_i915_gem_execbuffer_ext_timeline_fences {
+	struct i915_user_extension base;
+
+	/**
+	 * Number of element in the handles_ptr & value_ptr arrays.
+	 */
+	__u64 fence_count;
+
+	/**
+	 * Pointer to an array of struct drm_i915_gem_exec_fence of length
+	 * fence_count.
+	 */
+	__u64 handles_ptr;
+
+	/**
+	 * Pointer to an array of u64 values of length fence_count. Values
+	 * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline
+	 * drm_syncobj is invalid as it turns a drm_syncobj into a binary one.
+	 */
+	__u64 values_ptr;
+};
+
 struct drm_i915_gem_execbuffer2 {
 	/**
 	 * List of gem_exec_object2 structs
@@ -1062,8 +1100,14 @@ struct drm_i915_gem_execbuffer2 {
 	__u32 num_cliprects;
 	/**
 	 * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
-	 * is not set.  If I915_EXEC_FENCE_ARRAY is set, then this is a
-	 * struct drm_i915_gem_exec_fence *fences.
+	 * & I915_EXEC_USE_EXTENSIONS are not set.
+	 *
+	 * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
+	 * of struct drm_i915_gem_exec_fence and num_cliprects is the length
+	 * of the array.
+	 *
+	 * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
+	 * single struct i915_user_extension and num_cliprects is 0.
 	 */
 	__u64 cliprects_ptr;
 #define I915_EXEC_RING_MASK              (0x3f)
@@ -1181,7 +1225,16 @@ struct drm_i915_gem_execbuffer2 {
  */
 #define I915_EXEC_FENCE_SUBMIT		(1 << 20)
 
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
+/*
+ * Setting I915_EXEC_USE_EXTENSIONS implies that
+ * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
+ * list of i915_user_extension. Each i915_user_extension node is the base of a
+ * larger structure. The list of supported structures are listed in the
+ * drm_i915_gem_execbuffer_ext enum.
+ */
+#define I915_EXEC_USE_EXTENSIONS	(1 << 21)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))
 
 #define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)
 #define i915_execbuffer2_set_context_id(eb2, context) \
diff --git a/tools/include/uapi/linux/fscrypt.h b/tools/include/uapi/linux/fscrypt.h
index 7875709ccfeb..e5de60336938 100644
--- a/tools/include/uapi/linux/fscrypt.h
+++ b/tools/include/uapi/linux/fscrypt.h
@@ -45,7 +45,6 @@ struct fscrypt_policy_v1 {
 	__u8 flags;
 	__u8 master_key_descriptor[FSCRYPT_KEY_DESCRIPTOR_SIZE];
 };
-#define fscrypt_policy	fscrypt_policy_v1
 
 /*
  * Process-subscribed "logon" key description prefix and payload format.
@@ -156,9 +155,9 @@ struct fscrypt_get_key_status_arg {
 	__u32 __out_reserved[13];
 };
 
-#define FS_IOC_SET_ENCRYPTION_POLICY		_IOR('f', 19, struct fscrypt_policy)
+#define FS_IOC_SET_ENCRYPTION_POLICY		_IOR('f', 19, struct fscrypt_policy_v1)
 #define FS_IOC_GET_ENCRYPTION_PWSALT		_IOW('f', 20, __u8[16])
-#define FS_IOC_GET_ENCRYPTION_POLICY		_IOW('f', 21, struct fscrypt_policy)
+#define FS_IOC_GET_ENCRYPTION_POLICY		_IOW('f', 21, struct fscrypt_policy_v1)
 #define FS_IOC_GET_ENCRYPTION_POLICY_EX		_IOWR('f', 22, __u8[9]) /* size + version */
 #define FS_IOC_ADD_ENCRYPTION_KEY		_IOWR('f', 23, struct fscrypt_add_key_arg)
 #define FS_IOC_REMOVE_ENCRYPTION_KEY		_IOWR('f', 24, struct fscrypt_remove_key_arg)
@@ -170,6 +169,7 @@ struct fscrypt_get_key_status_arg {
 
 /* old names; don't add anything new here! */
 #ifndef __KERNEL__
+#define fscrypt_policy			fscrypt_policy_v1
 #define FS_KEY_DESCRIPTOR_SIZE		FSCRYPT_KEY_DESCRIPTOR_SIZE
 #define FS_POLICY_FLAGS_PAD_4		FSCRYPT_POLICY_FLAGS_PAD_4
 #define FS_POLICY_FLAGS_PAD_8		FSCRYPT_POLICY_FLAGS_PAD_8
diff --git a/tools/include/uapi/linux/kvm.h b/tools/include/uapi/linux/kvm.h
index 7d8eced6f459..ca41220b40b8 100644
--- a/tools/include/uapi/linux/kvm.h
+++ b/tools/include/uapi/linux/kvm.h
@@ -248,6 +248,8 @@ struct kvm_hyperv_exit {
 #define KVM_EXIT_IOAPIC_EOI       26
 #define KVM_EXIT_HYPERV           27
 #define KVM_EXIT_ARM_NISV         28
+#define KVM_EXIT_X86_RDMSR        29
+#define KVM_EXIT_X86_WRMSR        30
 
 /* For KVM_EXIT_INTERNAL_ERROR */
 /* Emulate instruction failed. */
@@ -413,6 +415,17 @@ struct kvm_run {
 			__u64 esr_iss;
 			__u64 fault_ipa;
 		} arm_nisv;
+		/* KVM_EXIT_X86_RDMSR / KVM_EXIT_X86_WRMSR */
+		struct {
+			__u8 error; /* user -> kernel */
+			__u8 pad[7];
+#define KVM_MSR_EXIT_REASON_INVAL	(1 << 0)
+#define KVM_MSR_EXIT_REASON_UNKNOWN	(1 << 1)
+#define KVM_MSR_EXIT_REASON_FILTER	(1 << 2)
+			__u32 reason; /* kernel -> user */
+			__u32 index; /* kernel -> user */
+			__u64 data; /* kernel <-> user */
+		} msr;
 		/* Fix the size of the union. */
 		char padding[256];
 	};
@@ -1037,6 +1050,9 @@ struct kvm_ppc_resize_hpt {
 #define KVM_CAP_SMALLER_MAXPHYADDR 185
 #define KVM_CAP_S390_DIAG318 186
 #define KVM_CAP_STEAL_TIME 187
+#define KVM_CAP_X86_USER_SPACE_MSR 188
+#define KVM_CAP_X86_MSR_FILTER 189
+#define KVM_CAP_ENFORCE_PV_FEATURE_CPUID 190
 
 #ifdef KVM_CAP_IRQ_ROUTING
 
@@ -1538,6 +1554,9 @@ struct kvm_pv_cmd {
 /* Available with KVM_CAP_S390_PROTECTED */
 #define KVM_S390_PV_COMMAND		_IOWR(KVMIO, 0xc5, struct kvm_pv_cmd)
 
+/* Available with KVM_CAP_X86_MSR_FILTER */
+#define KVM_X86_SET_MSR_FILTER	_IOW(KVMIO,  0xc6, struct kvm_msr_filter)
+
 /* Secure Encrypted Virtualization command */
 enum sev_cmd_id {
 	/* Guest initialization commands */
diff --git a/tools/include/uapi/linux/mman.h b/tools/include/uapi/linux/mman.h
index 923cc162609c..f55bc680b5b0 100644
--- a/tools/include/uapi/linux/mman.h
+++ b/tools/include/uapi/linux/mman.h
@@ -27,6 +27,7 @@
 #define MAP_HUGE_SHIFT	HUGETLB_FLAG_ENCODE_SHIFT
 #define MAP_HUGE_MASK	HUGETLB_FLAG_ENCODE_MASK
 
+#define MAP_HUGE_16KB	HUGETLB_FLAG_ENCODE_16KB
 #define MAP_HUGE_64KB	HUGETLB_FLAG_ENCODE_64KB
 #define MAP_HUGE_512KB	HUGETLB_FLAG_ENCODE_512KB
 #define MAP_HUGE_1MB	HUGETLB_FLAG_ENCODE_1MB
diff --git a/tools/include/uapi/linux/mount.h b/tools/include/uapi/linux/mount.h
index 96a0240f23fe..dd8306ea336c 100644
--- a/tools/include/uapi/linux/mount.h
+++ b/tools/include/uapi/linux/mount.h
@@ -16,6 +16,7 @@
 #define MS_REMOUNT	32	/* Alter flags of a mounted FS */
 #define MS_MANDLOCK	64	/* Allow mandatory locks on an FS */
 #define MS_DIRSYNC	128	/* Directory modifications are synchronous */
+#define MS_NOSYMFOLLOW	256	/* Do not follow symlinks */
 #define MS_NOATIME	1024	/* Do not update access times. */
 #define MS_NODIRATIME	2048	/* Do not update directory access times */
 #define MS_BIND		4096
diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h
index 3e5dcdd48a49..b95d3c485d27 100644
--- a/tools/include/uapi/linux/perf_event.h
+++ b/tools/include/uapi/linux/perf_event.h
@@ -1196,7 +1196,7 @@ union perf_mem_data_src {
 
 #define PERF_MEM_SNOOPX_FWD	0x01 /* forward */
 /* 1 free */
-#define PERF_MEM_SNOOPX_SHIFT	38
+#define PERF_MEM_SNOOPX_SHIFT  38
 
 /* locked instruction */
 #define PERF_MEM_LOCK_NA	0x01 /* not available */
diff --git a/tools/include/uapi/linux/prctl.h b/tools/include/uapi/linux/prctl.h
index 07b4f8131e36..7f0827705c9a 100644
--- a/tools/include/uapi/linux/prctl.h
+++ b/tools/include/uapi/linux/prctl.h
@@ -233,6 +233,15 @@ struct prctl_mm_map {
 #define PR_SET_TAGGED_ADDR_CTRL		55
 #define PR_GET_TAGGED_ADDR_CTRL		56
 # define PR_TAGGED_ADDR_ENABLE		(1UL << 0)
+/* MTE tag check fault modes */
+# define PR_MTE_TCF_SHIFT		1
+# define PR_MTE_TCF_NONE		(0UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_SYNC		(1UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_ASYNC		(2UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_MASK		(3UL << PR_MTE_TCF_SHIFT)
+/* MTE tag inclusion mask */
+# define PR_MTE_TAG_SHIFT		3
+# define PR_MTE_TAG_MASK		(0xffffUL << PR_MTE_TAG_SHIFT)
 
 /* Control reclaim behavior when allocating memory */
 #define PR_SET_IO_FLUSHER		57
diff --git a/tools/include/uapi/linux/vhost.h b/tools/include/uapi/linux/vhost.h
index 75232185324a..c998860d7bbc 100644
--- a/tools/include/uapi/linux/vhost.h
+++ b/tools/include/uapi/linux/vhost.h
@@ -146,4 +146,8 @@
 
 /* Set event fd for config interrupt*/
 #define VHOST_VDPA_SET_CONFIG_CALL	_IOW(VHOST_VIRTIO, 0x77, int)
+
+/* Get the valid iova range */
+#define VHOST_VDPA_GET_IOVA_RANGE	_IOR(VHOST_VIRTIO, 0x78, \
+					     struct vhost_vdpa_iova_range)
 #endif
diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config
index 6890fc4b063a..ce8516e4de34 100644
--- a/tools/perf/Makefile.config
+++ b/tools/perf/Makefile.config
@@ -749,6 +749,7 @@ else
   PERL_EMBED_LIBADD = $(call grep-libs,$(PERL_EMBED_LDOPTS))
   PERL_EMBED_CCOPTS = $(shell perl -MExtUtils::Embed -e ccopts 2>/dev/null)
   PERL_EMBED_CCOPTS := $(filter-out -specs=%,$(PERL_EMBED_CCOPTS))
+  PERL_EMBED_CCOPTS := $(filter-out -flto=auto -ffat-lto-objects, $(PERL_EMBED_CCOPTS))
   PERL_EMBED_LDOPTS := $(filter-out -specs=%,$(PERL_EMBED_LDOPTS))
   FLAGS_PERL_EMBED=$(PERL_EMBED_CCOPTS) $(PERL_EMBED_LDOPTS)
 
diff --git a/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl b/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
index 347809649ba2..379819244b91 100644
--- a/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
+++ b/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
@@ -361,12 +361,13 @@
 437	common	openat2			sys_openat2
 438	common	pidfd_getfd		sys_pidfd_getfd
 439	common	faccessat2		sys_faccessat2
+440	common	process_madvise		sys_process_madvise
 
 #
-# x32-specific system call numbers start at 512 to avoid cache impact
-# for native 64-bit operation. The __x32_compat_sys stubs are created
-# on-the-fly for compat_sys_*() compatibility system calls if X86_X32
-# is defined.
+# Due to a historical design error, certain syscalls are numbered differently
+# in x32 as compared to native x86_64.  These syscalls have numbers 512-547.
+# Do not add new syscalls to this range.  Numbers 548 and above are available
+# for non-x32 use.
 #
 512	x32	rt_sigaction		compat_sys_rt_sigaction
 513	x32	rt_sigreturn		compat_sys_x32_rt_sigreturn
@@ -404,3 +405,5 @@
 545	x32	execveat		compat_sys_execveat
 546	x32	preadv2			compat_sys_preadv64v2
 547	x32	pwritev2		compat_sys_pwritev64v2
+# This is the end of the legacy x32 range.  Numbers 548 and above are
+# not special and are not to be used for x32-specific syscalls.
diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c
index 44a75f234db1..de80534473af 100644
--- a/tools/perf/builtin-trace.c
+++ b/tools/perf/builtin-trace.c
@@ -4639,9 +4639,9 @@ do_concat:
 	err = 0;
 
 	if (lists[0]) {
-		struct option o = OPT_CALLBACK('e', "event", &trace->evlist, "event",
-					       "event selector. use 'perf list' to list available events",
-					       parse_events_option);
+		struct option o = {
+			.value = &trace->evlist,
+		};
 		err = parse_events_option(&o, lists[0], 0);
 	}
 out:
@@ -4655,9 +4655,12 @@ static int trace__parse_cgroups(const struct option *opt, const char *str, int u
 {
 	struct trace *trace = opt->value;
 
-	if (!list_empty(&trace->evlist->core.entries))
-		return parse_cgroups(opt, str, unset);
-
+	if (!list_empty(&trace->evlist->core.entries)) {
+		struct option o = {
+			.value = &trace->evlist,
+		};
+		return parse_cgroups(&o, str, unset);
+	}
 	trace->cgroup = evlist__findnew_cgroup(trace->evlist, str);
 
 	return 0;
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
index de3193552277..00f4fcffa815 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
@@ -329,7 +329,7 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time",
+        "MetricExpr": "( ( ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) * 1048576 ) / 1000000000 ) / duration_time",
         "MetricGroup": "Memory_BW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
index f31794d3b926..0dd8b13b5cfb 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json
@@ -323,7 +323,7 @@
     },
     {
         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
-        "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time",
+        "MetricExpr": "( ( ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) * 1048576 ) / 1000000000 ) / duration_time",
         "MetricGroup": "Memory_BW;SoC",
         "MetricName": "DRAM_BW_Use"
     },
diff --git a/tools/perf/tests/dwarf-unwind.c b/tools/perf/tests/dwarf-unwind.c
index 2491d167bf76..83638097c3bc 100644
--- a/tools/perf/tests/dwarf-unwind.c
+++ b/tools/perf/tests/dwarf-unwind.c
@@ -95,7 +95,7 @@ static int unwind_entry(struct unwind_entry *entry, void *arg)
 	return strcmp((const char *) symbol, funcs[idx]);
 }
 
-__no_tail_call noinline int test_dwarf_unwind__thread(struct thread *thread)
+noinline int test_dwarf_unwind__thread(struct thread *thread)
 {
 	struct perf_sample sample;
 	unsigned long cnt = 0;
@@ -126,7 +126,7 @@ __no_tail_call noinline int test_dwarf_unwind__thread(struct thread *thread)
 
 static int global_unwind_retval = -INT_MAX;
 
-__no_tail_call noinline int test_dwarf_unwind__compare(void *p1, void *p2)
+noinline int test_dwarf_unwind__compare(void *p1, void *p2)
 {
 	/* Any possible value should be 'thread' */
 	struct thread *thread = *(struct thread **)p1;
@@ -145,7 +145,7 @@ __no_tail_call noinline int test_dwarf_unwind__compare(void *p1, void *p2)
 	return p1 - p2;
 }
 
-__no_tail_call noinline int test_dwarf_unwind__krava_3(struct thread *thread)
+noinline int test_dwarf_unwind__krava_3(struct thread *thread)
 {
 	struct thread *array[2] = {thread, thread};
 	void *fp = &bsearch;
@@ -164,12 +164,12 @@ __no_tail_call noinline int test_dwarf_unwind__krava_3(struct thread *thread)
 	return global_unwind_retval;
 }
 
-__no_tail_call noinline int test_dwarf_unwind__krava_2(struct thread *thread)
+noinline int test_dwarf_unwind__krava_2(struct thread *thread)
 {
 	return test_dwarf_unwind__krava_3(thread);
 }
 
-__no_tail_call noinline int test_dwarf_unwind__krava_1(struct thread *thread)
+noinline int test_dwarf_unwind__krava_1(struct thread *thread)
 {
 	return test_dwarf_unwind__krava_2(thread);
 }
diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c
index a07626f07208..b0e1880cf992 100644
--- a/tools/perf/ui/browsers/hists.c
+++ b/tools/perf/ui/browsers/hists.c
@@ -2963,7 +2963,7 @@ static int perf_evsel__hists_browse(struct evsel *evsel, int nr_events,
 	struct popup_action actions[MAX_OPTIONS];
 	int nr_options = 0;
 	int key = -1;
-	char buf[64];
+	char buf[128];
 	int delay_secs = hbt ? hbt->refresh : 0;
 
 #define HIST_BROWSER_HELP_COMMON					\
diff --git a/tools/perf/util/build-id.c b/tools/perf/util/build-id.c
index 8763772f1095..6b410c3d52dc 100644
--- a/tools/perf/util/build-id.c
+++ b/tools/perf/util/build-id.c
@@ -102,6 +102,8 @@ int build_id__sprintf(const struct build_id *build_id, char *bf)
 	const u8 *raw = build_id->data;
 	size_t i;
 
+	bf[0] = 0x0;
+
 	for (i = 0; i < build_id->size; ++i) {
 		sprintf(bid, "%02x", *raw);
 		++raw;
diff --git a/tools/perf/util/hashmap.c b/tools/perf/util/hashmap.c
index a405dad068f5..3c20b126d60d 100644
--- a/tools/perf/util/hashmap.c
+++ b/tools/perf/util/hashmap.c
@@ -15,6 +15,9 @@
 /* make sure libbpf doesn't use kernel-only integer typedefs */
 #pragma GCC poison u8 u16 u32 u64 s8 s16 s32 s64
 
+/* prevent accidental re-addition of reallocarray() */
+#pragma GCC poison reallocarray
+
 /* start with 4 buckets */
 #define HASHMAP_MIN_CAP_BITS 2
 
diff --git a/tools/perf/util/hashmap.h b/tools/perf/util/hashmap.h
index e0af36b0e5d8..d9b385fe808c 100644
--- a/tools/perf/util/hashmap.h
+++ b/tools/perf/util/hashmap.h
@@ -25,6 +25,18 @@ static inline size_t hash_bits(size_t h, int bits)
 #endif
 }
 
+/* generic C-string hashing function */
+static inline size_t str_hash(const char *s)
+{
+	size_t h = 0;
+
+	while (*s) {
+		h = h * 31 + *s;
+		s++;
+	}
+	return h;
+}
+
 typedef size_t (*hashmap_hash_fn)(const void *key, void *ctx);
 typedef bool (*hashmap_equal_fn)(const void *key1, const void *key2, void *ctx);
 
diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c
index 7d4194ffc5b0..15385ea00190 100644
--- a/tools/perf/util/machine.c
+++ b/tools/perf/util/machine.c
@@ -786,11 +786,20 @@ static int machine__process_ksymbol_unregister(struct machine *machine,
 					       union perf_event *event,
 					       struct perf_sample *sample __maybe_unused)
 {
+	struct symbol *sym;
 	struct map *map;
 
 	map = maps__find(&machine->kmaps, event->ksymbol.addr);
-	if (map)
+	if (!map)
+		return 0;
+
+	if (map != machine->vmlinux_map)
 		maps__remove(&machine->kmaps, map);
+	else {
+		sym = dso__find_symbol(map->dso, map->map_ip(map, map->start));
+		if (sym)
+			dso__delete_symbol(map->dso, sym);
+	}
 
 	return 0;
 }
diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c
index 7cbd024e3e63..c83c2c6564e0 100644
--- a/tools/perf/util/scripting-engines/trace-event-python.c
+++ b/tools/perf/util/scripting-engines/trace-event-python.c
@@ -1592,7 +1592,6 @@ static void _free_command_line(wchar_t **command_line, int num)
 static int python_start_script(const char *script, int argc, const char **argv)
 {
 	struct tables *tables = &tables_global;
-	PyMODINIT_FUNC (*initfunc)(void);
 #if PY_MAJOR_VERSION < 3
 	const char **command_line;
 #else
@@ -1607,20 +1606,18 @@ static int python_start_script(const char *script, int argc, const char **argv)
 	FILE *fp;
 
 #if PY_MAJOR_VERSION < 3
-	initfunc = initperf_trace_context;
 	command_line = malloc((argc + 1) * sizeof(const char *));
 	command_line[0] = script;
 	for (i = 1; i < argc + 1; i++)
 		command_line[i] = argv[i - 1];
+	PyImport_AppendInittab(name, initperf_trace_context);
 #else
-	initfunc = PyInit_perf_trace_context;
 	command_line = malloc((argc + 1) * sizeof(wchar_t *));
 	command_line[0] = Py_DecodeLocale(script, NULL);
 	for (i = 1; i < argc + 1; i++)
 		command_line[i] = Py_DecodeLocale(argv[i - 1], NULL);
+	PyImport_AppendInittab(name, PyInit_perf_trace_context);
 #endif
-
-	PyImport_AppendInittab(name, initfunc);
 	Py_Initialize();
 
 #if PY_MAJOR_VERSION < 3
diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c
index 7a5f03764702..098080287c68 100644
--- a/tools/perf/util/session.c
+++ b/tools/perf/util/session.c
@@ -595,6 +595,7 @@ static void perf_event__mmap2_swap(union perf_event *event,
 	event->mmap2.maj   = bswap_32(event->mmap2.maj);
 	event->mmap2.min   = bswap_32(event->mmap2.min);
 	event->mmap2.ino   = bswap_64(event->mmap2.ino);
+	event->mmap2.ino_generation = bswap_64(event->mmap2.ino_generation);
 
 	if (sample_id_all) {
 		void *data = &event->mmap2.filename;
@@ -710,6 +711,18 @@ static void perf_event__namespaces_swap(union perf_event *event,
 		swap_sample_id_all(event, &event->namespaces.link_info[i]);
 }
 
+static void perf_event__cgroup_swap(union perf_event *event, bool sample_id_all)
+{
+	event->cgroup.id = bswap_64(event->cgroup.id);
+
+	if (sample_id_all) {
+		void *data = &event->cgroup.path;
+
+		data += PERF_ALIGN(strlen(data) + 1, sizeof(u64));
+		swap_sample_id_all(event, data);
+	}
+}
+
 static u8 revbyte(u8 b)
 {
 	int rev = (b >> 4) | ((b & 0xf) << 4);
@@ -952,6 +965,7 @@ static perf_event__swap_op perf_event__swap_ops[] = {
 	[PERF_RECORD_SWITCH]		  = perf_event__switch_swap,
 	[PERF_RECORD_SWITCH_CPU_WIDE]	  = perf_event__switch_swap,
 	[PERF_RECORD_NAMESPACES]	  = perf_event__namespaces_swap,
+	[PERF_RECORD_CGROUP]		  = perf_event__cgroup_swap,
 	[PERF_RECORD_TEXT_POKE]		  = perf_event__text_poke_swap,
 	[PERF_RECORD_HEADER_ATTR]	  = perf_event__hdr_attr_swap,
 	[PERF_RECORD_HEADER_EVENT_TYPE]	  = perf_event__event_type_swap,
diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c
index 6138866665df..0d14abdf3d72 100644
--- a/tools/perf/util/symbol.c
+++ b/tools/perf/util/symbol.c
@@ -515,6 +515,13 @@ void dso__insert_symbol(struct dso *dso, struct symbol *sym)
 	}
 }
 
+void dso__delete_symbol(struct dso *dso, struct symbol *sym)
+{
+	rb_erase_cached(&sym->rb_node, &dso->symbols);
+	symbol__delete(sym);
+	dso__reset_find_symbol_cache(dso);
+}
+
 struct symbol *dso__find_symbol(struct dso *dso, u64 addr)
 {
 	if (dso->last_find_result.addr != addr || dso->last_find_result.symbol == NULL) {
diff --git a/tools/perf/util/symbol.h b/tools/perf/util/symbol.h
index f4801c488def..954d6a049ee2 100644
--- a/tools/perf/util/symbol.h
+++ b/tools/perf/util/symbol.h
@@ -131,6 +131,8 @@ int dso__load_kallsyms(struct dso *dso, const char *filename, struct map *map);
 
 void dso__insert_symbol(struct dso *dso,
 			struct symbol *sym);
+void dso__delete_symbol(struct dso *dso,
+			struct symbol *sym);
 
 struct symbol *dso__find_symbol(struct dso *dso, u64 addr);
 struct symbol *dso__find_symbol_by_name(struct dso *dso, const char *name);
diff --git a/tools/testing/kunit/kunit_parser.py b/tools/testing/kunit/kunit_parser.py
index 8019e3dd4c32..84a1af2581f5 100644
--- a/tools/testing/kunit/kunit_parser.py
+++ b/tools/testing/kunit/kunit_parser.py
@@ -66,7 +66,6 @@ def isolate_kunit_output(kernel_output):
 def raw_output(kernel_output):
 	for line in kernel_output:
 		print(line)
-		yield line
 
 DIVIDER = '=' * 60
 
@@ -242,7 +241,7 @@ def parse_test_suite(lines: List[str], expected_suite_index: int) -> TestSuite:
 		return None
 	test_suite.name = name
 	expected_test_case_num = parse_subtest_plan(lines)
-	if not expected_test_case_num:
+	if expected_test_case_num is None:
 		return None
 	while expected_test_case_num > 0:
 		test_case = parse_test_case(lines)
diff --git a/tools/testing/kunit/kunit_tool_test.py b/tools/testing/kunit/kunit_tool_test.py
index 99c3c5671ea4..0b60855fb819 100755
--- a/tools/testing/kunit/kunit_tool_test.py
+++ b/tools/testing/kunit/kunit_tool_test.py
@@ -179,7 +179,7 @@ class KUnitParserTest(unittest.TestCase):
 		print_mock = mock.patch('builtins.print').start()
 		result = kunit_parser.parse_run_tests(
 			kunit_parser.isolate_kunit_output(file.readlines()))
-		print_mock.assert_any_call(StrContains("no kunit output detected"))
+		print_mock.assert_any_call(StrContains('no tests run!'))
 		print_mock.stop()
 		file.close()
 
@@ -198,39 +198,57 @@ class KUnitParserTest(unittest.TestCase):
 			'test_data/test_config_printk_time.log')
 		with open(prefix_log) as file:
 			result = kunit_parser.parse_run_tests(file.readlines())
-		self.assertEqual('kunit-resource-test', result.suites[0].name)
+			self.assertEqual(
+				kunit_parser.TestStatus.SUCCESS,
+				result.status)
+			self.assertEqual('kunit-resource-test', result.suites[0].name)
 
 	def test_ignores_multiple_prefixes(self):
 		prefix_log = get_absolute_path(
 			'test_data/test_multiple_prefixes.log')
 		with open(prefix_log) as file:
 			result = kunit_parser.parse_run_tests(file.readlines())
-		self.assertEqual('kunit-resource-test', result.suites[0].name)
+			self.assertEqual(
+				kunit_parser.TestStatus.SUCCESS,
+				result.status)
+			self.assertEqual('kunit-resource-test', result.suites[0].name)
 
 	def test_prefix_mixed_kernel_output(self):
 		mixed_prefix_log = get_absolute_path(
 			'test_data/test_interrupted_tap_output.log')
 		with open(mixed_prefix_log) as file:
 			result = kunit_parser.parse_run_tests(file.readlines())
-		self.assertEqual('kunit-resource-test', result.suites[0].name)
+			self.assertEqual(
+				kunit_parser.TestStatus.SUCCESS,
+				result.status)
+			self.assertEqual('kunit-resource-test', result.suites[0].name)
 
 	def test_prefix_poundsign(self):
 		pound_log = get_absolute_path('test_data/test_pound_sign.log')
 		with open(pound_log) as file:
 			result = kunit_parser.parse_run_tests(file.readlines())
-		self.assertEqual('kunit-resource-test', result.suites[0].name)
+			self.assertEqual(
+				kunit_parser.TestStatus.SUCCESS,
+				result.status)
+			self.assertEqual('kunit-resource-test', result.suites[0].name)
 
 	def test_kernel_panic_end(self):
 		panic_log = get_absolute_path('test_data/test_kernel_panic_interrupt.log')
 		with open(panic_log) as file:
 			result = kunit_parser.parse_run_tests(file.readlines())
-		self.assertEqual('kunit-resource-test', result.suites[0].name)
+			self.assertEqual(
+				kunit_parser.TestStatus.TEST_CRASHED,
+				result.status)
+			self.assertEqual('kunit-resource-test', result.suites[0].name)
 
 	def test_pound_no_prefix(self):
 		pound_log = get_absolute_path('test_data/test_pound_no_prefix.log')
 		with open(pound_log) as file:
 			result = kunit_parser.parse_run_tests(file.readlines())
-		self.assertEqual('kunit-resource-test', result.suites[0].name)
+			self.assertEqual(
+				kunit_parser.TestStatus.SUCCESS,
+				result.status)
+			self.assertEqual('kunit-resource-test', result.suites[0].name)
 
 class KUnitJsonTest(unittest.TestCase):
 
diff --git a/tools/testing/kunit/test_data/test_config_printk_time.log b/tools/testing/kunit/test_data/test_config_printk_time.log
index c02ca773946d..6bdb57f76eac 100644
--- a/tools/testing/kunit/test_data/test_config_printk_time.log
+++ b/tools/testing/kunit/test_data/test_config_printk_time.log
@@ -1,6 +1,7 @@
 [    0.060000] printk: console [mc-1] enabled
 [    0.060000] random: get_random_bytes called from init_oops_id+0x35/0x40 with crng_init=0
 [    0.060000] TAP version 14
+[    0.060000] 1..3
 [    0.060000] 	# Subtest: kunit-resource-test
 [    0.060000] 	1..5
 [    0.060000] 	ok 1 - kunit_resource_test_init_resources
@@ -28,4 +29,4 @@
 [    0.060000] Stack:
 [    0.060000]  602086f8 601bc260 705c0000 705c0000
 [    0.060000]  602086f8 6005fcec 705c0000 6002c6ab
-[    0.060000]  6005fcec 601bc260 705c0000 3000000010
\ No newline at end of file
+[    0.060000]  6005fcec 601bc260 705c0000 3000000010
diff --git a/tools/testing/kunit/test_data/test_interrupted_tap_output.log b/tools/testing/kunit/test_data/test_interrupted_tap_output.log
index 5c73fb3a1c6f..1fb677728abe 100644
--- a/tools/testing/kunit/test_data/test_interrupted_tap_output.log
+++ b/tools/testing/kunit/test_data/test_interrupted_tap_output.log
@@ -1,6 +1,7 @@
 [    0.060000] printk: console [mc-1] enabled
 [    0.060000] random: get_random_bytes called from init_oops_id+0x35/0x40 with crng_init=0
 [    0.060000] TAP version 14
+[    0.060000] 1..3
 [    0.060000] 	# Subtest: kunit-resource-test
 [    0.060000] 	1..5
 [    0.060000] 	ok 1 - kunit_resource_test_init_resources
@@ -34,4 +35,4 @@
 [    0.060000] Stack:
 [    0.060000]  602086f8 601bc260 705c0000 705c0000
 [    0.060000]  602086f8 6005fcec 705c0000 6002c6ab
-[    0.060000]  6005fcec 601bc260 705c0000 3000000010
\ No newline at end of file
+[    0.060000]  6005fcec 601bc260 705c0000 3000000010
diff --git a/tools/testing/kunit/test_data/test_kernel_panic_interrupt.log b/tools/testing/kunit/test_data/test_kernel_panic_interrupt.log
index c045eee75f27..a014ffe9725e 100644
--- a/tools/testing/kunit/test_data/test_kernel_panic_interrupt.log
+++ b/tools/testing/kunit/test_data/test_kernel_panic_interrupt.log
@@ -1,6 +1,7 @@
 [    0.060000] printk: console [mc-1] enabled
 [    0.060000] random: get_random_bytes called from init_oops_id+0x35/0x40 with crng_init=0
 [    0.060000] TAP version 14
+[    0.060000] 1..3
 [    0.060000] 	# Subtest: kunit-resource-test
 [    0.060000] 	1..5
 [    0.060000] 	ok 1 - kunit_resource_test_init_resources
@@ -22,4 +23,4 @@
 [    0.060000] Stack:
 [    0.060000]  602086f8 601bc260 705c0000 705c0000
 [    0.060000]  602086f8 6005fcec 705c0000 6002c6ab
-[    0.060000]  6005fcec 601bc260 705c0000 3000000010
\ No newline at end of file
+[    0.060000]  6005fcec 601bc260 705c0000 3000000010
diff --git a/tools/testing/kunit/test_data/test_multiple_prefixes.log b/tools/testing/kunit/test_data/test_multiple_prefixes.log
index bc48407dcc36..0ad78481a0b4 100644
--- a/tools/testing/kunit/test_data/test_multiple_prefixes.log
+++ b/tools/testing/kunit/test_data/test_multiple_prefixes.log
@@ -1,6 +1,7 @@
 [    0.060000][    T1] printk: console [mc-1] enabled
 [    0.060000][    T1] random: get_random_bytes called from init_oops_id+0x35/0x40 with crng_init=0
 [    0.060000][    T1] TAP version 14
+[    0.060000][    T1] 1..3
 [    0.060000][    T1] 	# Subtest: kunit-resource-test
 [    0.060000][    T1] 	1..5
 [    0.060000][    T1] 	ok 1 - kunit_resource_test_init_resources
@@ -28,4 +29,4 @@
 [    0.060000][    T1] Stack:
 [    0.060000][    T1]  602086f8 601bc260 705c0000 705c0000
 [    0.060000][    T1]  602086f8 6005fcec 705c0000 6002c6ab
-[    0.060000][    T1]  6005fcec 601bc260 705c0000 3000000010
\ No newline at end of file
+[    0.060000][    T1]  6005fcec 601bc260 705c0000 3000000010
diff --git a/tools/testing/kunit/test_data/test_pound_no_prefix.log b/tools/testing/kunit/test_data/test_pound_no_prefix.log
index 2ceb360be7d5..dc4cf09a96d0 100644
--- a/tools/testing/kunit/test_data/test_pound_no_prefix.log
+++ b/tools/testing/kunit/test_data/test_pound_no_prefix.log
@@ -1,6 +1,7 @@
  printk: console [mc-1] enabled
  random: get_random_bytes called from init_oops_id+0x35/0x40 with crng_init=0
  TAP version 14
+ 1..3
  	# Subtest: kunit-resource-test
  	1..5
  	ok 1 - kunit_resource_test_init_resources
@@ -30,4 +31,4 @@
  Stack:
   602086f8 601bc260 705c0000 705c0000
   602086f8 6005fcec 705c0000 6002c6ab
-  6005fcec 601bc260 705c0000 3000000010
\ No newline at end of file
+  6005fcec 601bc260 705c0000 3000000010
diff --git a/tools/testing/kunit/test_data/test_pound_sign.log b/tools/testing/kunit/test_data/test_pound_sign.log
index 28ffa5ba03bf..3f358e3a7ba0 100644
--- a/tools/testing/kunit/test_data/test_pound_sign.log
+++ b/tools/testing/kunit/test_data/test_pound_sign.log
@@ -1,6 +1,7 @@
 [    0.060000] printk: console [mc-1] enabled
 [    0.060000] random: get_random_bytes called from init_oops_id+0x35/0x40 with crng_init=0
 [    0.060000] TAP version 14
+[    0.060000] 1..3
 [    0.060000] 	# Subtest: kunit-resource-test
 [    0.060000] 	1..5
 [    0.060000] 	ok 1 - kunit_resource_test_init_resources
diff --git a/tools/testing/selftests/clone3/clone3_cap_checkpoint_restore.c b/tools/testing/selftests/clone3/clone3_cap_checkpoint_restore.c
index 55bd387ce7ec..52d3f0364bda 100644
--- a/tools/testing/selftests/clone3/clone3_cap_checkpoint_restore.c
+++ b/tools/testing/selftests/clone3/clone3_cap_checkpoint_restore.c
@@ -145,7 +145,7 @@ TEST(clone3_cap_checkpoint_restore)
 	test_clone3_supported();
 
 	EXPECT_EQ(getuid(), 0)
-		XFAIL(return, "Skipping all tests as non-root\n");
+		SKIP(return, "Skipping all tests as non-root");
 
 	memset(&set_tid, 0, sizeof(set_tid));
 
diff --git a/tools/testing/selftests/core/close_range_test.c b/tools/testing/selftests/core/close_range_test.c
index c99b98b0d461..575b391ddc78 100644
--- a/tools/testing/selftests/core/close_range_test.c
+++ b/tools/testing/selftests/core/close_range_test.c
@@ -44,7 +44,7 @@ TEST(close_range)
 		fd = open("/dev/null", O_RDONLY | O_CLOEXEC);
 		ASSERT_GE(fd, 0) {
 			if (errno == ENOENT)
-				XFAIL(return, "Skipping test since /dev/null does not exist");
+				SKIP(return, "Skipping test since /dev/null does not exist");
 		}
 
 		open_fds[i] = fd;
@@ -52,7 +52,7 @@ TEST(close_range)
 
 	EXPECT_EQ(-1, sys_close_range(open_fds[0], open_fds[100], -1)) {
 		if (errno == ENOSYS)
-			XFAIL(return, "close_range() syscall not supported");
+			SKIP(return, "close_range() syscall not supported");
 	}
 
 	EXPECT_EQ(0, sys_close_range(open_fds[0], open_fds[50], 0));
@@ -108,7 +108,7 @@ TEST(close_range_unshare)
 		fd = open("/dev/null", O_RDONLY | O_CLOEXEC);
 		ASSERT_GE(fd, 0) {
 			if (errno == ENOENT)
-				XFAIL(return, "Skipping test since /dev/null does not exist");
+				SKIP(return, "Skipping test since /dev/null does not exist");
 		}
 
 		open_fds[i] = fd;
@@ -197,7 +197,7 @@ TEST(close_range_unshare_capped)
 		fd = open("/dev/null", O_RDONLY | O_CLOEXEC);
 		ASSERT_GE(fd, 0) {
 			if (errno == ENOENT)
-				XFAIL(return, "Skipping test since /dev/null does not exist");
+				SKIP(return, "Skipping test since /dev/null does not exist");
 		}
 
 		open_fds[i] = fd;
diff --git a/tools/testing/selftests/filesystems/binderfs/binderfs_test.c b/tools/testing/selftests/filesystems/binderfs/binderfs_test.c
index 1d27f52c61e6..477cbb042f5b 100644
--- a/tools/testing/selftests/filesystems/binderfs/binderfs_test.c
+++ b/tools/testing/selftests/filesystems/binderfs/binderfs_test.c
@@ -74,7 +74,7 @@ static int __do_binderfs_test(struct __test_metadata *_metadata)
 	ret = mount(NULL, binderfs_mntpt, "binder", 0, 0);
 	EXPECT_EQ(ret, 0) {
 		if (errno == ENODEV)
-			XFAIL(goto out, "binderfs missing");
+			SKIP(goto out, "binderfs missing");
 		TH_LOG("%s - Failed to mount binderfs", strerror(errno));
 		goto rmdir;
 	}
@@ -475,10 +475,10 @@ TEST(binderfs_stress)
 TEST(binderfs_test_privileged)
 {
 	if (geteuid() != 0)
-		XFAIL(return, "Tests are not run as root. Skipping privileged tests");
+		SKIP(return, "Tests are not run as root. Skipping privileged tests");
 
 	if (__do_binderfs_test(_metadata))
-		XFAIL(return, "The Android binderfs filesystem is not available");
+		SKIP(return, "The Android binderfs filesystem is not available");
 }
 
 TEST(binderfs_test_unprivileged)
@@ -511,7 +511,7 @@ TEST(binderfs_test_unprivileged)
 	ret = wait_for_pid(pid);
 	if (ret) {
 		if (ret == 2)
-			XFAIL(return, "The Android binderfs filesystem is not available");
+			SKIP(return, "The Android binderfs filesystem is not available");
 		ASSERT_EQ(ret, 0) {
 			TH_LOG("wait_for_pid() failed");
 		}
diff --git a/tools/testing/selftests/filesystems/epoll/epoll_wakeup_test.c b/tools/testing/selftests/filesystems/epoll/epoll_wakeup_test.c
index d979ff14775a..8f82f99f7748 100644
--- a/tools/testing/selftests/filesystems/epoll/epoll_wakeup_test.c
+++ b/tools/testing/selftests/filesystems/epoll/epoll_wakeup_test.c
@@ -3282,4 +3282,99 @@ TEST(epoll60)
 	close(ctx.epfd);
 }
 
+struct epoll61_ctx {
+	int epfd;
+	int evfd;
+};
+
+static void *epoll61_write_eventfd(void *ctx_)
+{
+	struct epoll61_ctx *ctx = ctx_;
+	int64_t l = 1;
+
+	usleep(10950);
+	write(ctx->evfd, &l, sizeof(l));
+	return NULL;
+}
+
+static void *epoll61_epoll_with_timeout(void *ctx_)
+{
+	struct epoll61_ctx *ctx = ctx_;
+	struct epoll_event events[1];
+	int n;
+
+	n = epoll_wait(ctx->epfd, events, 1, 11);
+	/*
+	 * If epoll returned the eventfd, write on the eventfd to wake up the
+	 * blocking poller.
+	 */
+	if (n == 1) {
+		int64_t l = 1;
+
+		write(ctx->evfd, &l, sizeof(l));
+	}
+	return NULL;
+}
+
+static void *epoll61_blocking_epoll(void *ctx_)
+{
+	struct epoll61_ctx *ctx = ctx_;
+	struct epoll_event events[1];
+
+	epoll_wait(ctx->epfd, events, 1, -1);
+	return NULL;
+}
+
+TEST(epoll61)
+{
+	struct epoll61_ctx ctx;
+	struct epoll_event ev;
+	int i, r;
+
+	ctx.epfd = epoll_create1(0);
+	ASSERT_GE(ctx.epfd, 0);
+	ctx.evfd = eventfd(0, EFD_NONBLOCK);
+	ASSERT_GE(ctx.evfd, 0);
+
+	ev.events = EPOLLIN | EPOLLET | EPOLLERR | EPOLLHUP;
+	ev.data.ptr = NULL;
+	r = epoll_ctl(ctx.epfd, EPOLL_CTL_ADD, ctx.evfd, &ev);
+	ASSERT_EQ(r, 0);
+
+	/*
+	 * We are testing a race.  Repeat the test case 1000 times to make it
+	 * more likely to fail in case of a bug.
+	 */
+	for (i = 0; i < 1000; i++) {
+		pthread_t threads[3];
+		int n;
+
+		/*
+		 * Start 3 threads:
+		 * Thread 1 sleeps for 10.9ms and writes to the evenfd.
+		 * Thread 2 calls epoll with a timeout of 11ms.
+		 * Thread 3 calls epoll with a timeout of -1.
+		 *
+		 * The eventfd write by Thread 1 should either wakeup Thread 2
+		 * or Thread 3.  If it wakes up Thread 2, Thread 2 writes on the
+		 * eventfd to wake up Thread 3.
+		 *
+		 * If no events are missed, all three threads should eventually
+		 * be joinable.
+		 */
+		ASSERT_EQ(pthread_create(&threads[0], NULL,
+					 epoll61_write_eventfd, &ctx), 0);
+		ASSERT_EQ(pthread_create(&threads[1], NULL,
+					 epoll61_epoll_with_timeout, &ctx), 0);
+		ASSERT_EQ(pthread_create(&threads[2], NULL,
+					 epoll61_blocking_epoll, &ctx), 0);
+
+		for (n = 0; n < ARRAY_SIZE(threads); ++n)
+			ASSERT_EQ(pthread_join(threads[n], NULL), 0);
+	}
+
+	close(ctx.epfd);
+	close(ctx.evfd);
+}
+
 TEST_HARNESS_MAIN
diff --git a/tools/testing/selftests/ftrace/test.d/dynevent/add_remove_kprobe.tc b/tools/testing/selftests/ftrace/test.d/dynevent/add_remove_kprobe.tc
index 3bcd4c3624ee..b4da41d126d5 100644
--- a/tools/testing/selftests/ftrace/test.d/dynevent/add_remove_kprobe.tc
+++ b/tools/testing/selftests/ftrace/test.d/dynevent/add_remove_kprobe.tc
@@ -6,7 +6,7 @@
 echo 0 > events/enable
 echo > dynamic_events
 
-PLACE=kernel_clone
+PLACE=$FUNCTION_FORK
 
 echo "p:myevent1 $PLACE" >> dynamic_events
 echo "r:myevent2 $PLACE" >> dynamic_events
diff --git a/tools/testing/selftests/ftrace/test.d/dynevent/clear_select_events.tc b/tools/testing/selftests/ftrace/test.d/dynevent/clear_select_events.tc
index 438961971b7e..3a0e2885fff5 100644
--- a/tools/testing/selftests/ftrace/test.d/dynevent/clear_select_events.tc
+++ b/tools/testing/selftests/ftrace/test.d/dynevent/clear_select_events.tc
@@ -6,7 +6,7 @@
 echo 0 > events/enable
 echo > dynamic_events
 
-PLACE=kernel_clone
+PLACE=$FUNCTION_FORK
 
 setup_events() {
 echo "p:myevent1 $PLACE" >> dynamic_events
diff --git a/tools/testing/selftests/ftrace/test.d/dynevent/generic_clear_event.tc b/tools/testing/selftests/ftrace/test.d/dynevent/generic_clear_event.tc
index a8603bd23e0d..d3e138e8377f 100644
--- a/tools/testing/selftests/ftrace/test.d/dynevent/generic_clear_event.tc
+++ b/tools/testing/selftests/ftrace/test.d/dynevent/generic_clear_event.tc
@@ -6,7 +6,7 @@
 echo 0 > events/enable
 echo > dynamic_events
 
-PLACE=kernel_clone
+PLACE=$FUNCTION_FORK
 
 setup_events() {
 echo "p:myevent1 $PLACE" >> dynamic_events
diff --git a/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-notrace-pid.tc b/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-notrace-pid.tc
index acb17ce543d2..80541964b927 100644
--- a/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-notrace-pid.tc
+++ b/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-notrace-pid.tc
@@ -39,7 +39,7 @@ do_test() {
     disable_tracing
 
     echo do_execve* > set_ftrace_filter
-    echo *do_fork >> set_ftrace_filter
+    echo $FUNCTION_FORK >> set_ftrace_filter
 
     echo $PID > set_ftrace_notrace_pid
     echo function > current_tracer
diff --git a/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-pid.tc b/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-pid.tc
index 9f0a9687c773..2f7211254529 100644
--- a/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-pid.tc
+++ b/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-pid.tc
@@ -39,7 +39,7 @@ do_test() {
     disable_tracing
 
     echo do_execve* > set_ftrace_filter
-    echo *do_fork >> set_ftrace_filter
+    echo $FUNCTION_FORK >> set_ftrace_filter
 
     echo $PID > set_ftrace_pid
     echo function > current_tracer
diff --git a/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-stacktrace.tc b/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-stacktrace.tc
index 98305d76bd04..191d116b7883 100644
--- a/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-stacktrace.tc
+++ b/tools/testing/selftests/ftrace/test.d/ftrace/func-filter-stacktrace.tc
@@ -4,9 +4,9 @@
 # requires: set_ftrace_filter
 # flags: instance
 
-echo kernel_clone:stacktrace >> set_ftrace_filter
+echo $FUNCTION_FORK:stacktrace >> set_ftrace_filter
 
-grep -q "kernel_clone:stacktrace:unlimited" set_ftrace_filter
+grep -q "$FUNCTION_FORK:stacktrace:unlimited" set_ftrace_filter
 
 (echo "forked"; sleep 1)
 
diff --git a/tools/testing/selftests/ftrace/test.d/functions b/tools/testing/selftests/ftrace/test.d/functions
index c5dec55b7d95..a6fac927ee82 100644
--- a/tools/testing/selftests/ftrace/test.d/functions
+++ b/tools/testing/selftests/ftrace/test.d/functions
@@ -133,6 +133,13 @@ yield() {
     ping $LOCALHOST -c 1 || sleep .001 || usleep 1 || sleep 1
 }
 
+# The fork function in the kernel was renamed from "_do_fork" to
+# "kernel_fork". As older tests should still work with older kernels
+# as well as newer kernels, check which version of fork is used on this
+# kernel so that the tests can use the fork function for the running kernel.
+FUNCTION_FORK=`(if grep '\bkernel_clone\b' /proc/kallsyms > /dev/null; then
+                echo kernel_clone; else echo '_do_fork'; fi)`
+
 # Since probe event command may include backslash, explicitly use printf "%s"
 # to NOT interpret it.
 ftrace_errlog_check() { # err-prefix command-with-error-pos-by-^ command-file
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/add_and_remove.tc b/tools/testing/selftests/ftrace/test.d/kprobe/add_and_remove.tc
index 9737cd0578a7..2428a3ed78c9 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/add_and_remove.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/add_and_remove.tc
@@ -3,7 +3,7 @@
 # description: Kprobe dynamic event - adding and removing
 # requires: kprobe_events
 
-echo p:myevent kernel_clone > kprobe_events
+echo p:myevent $FUNCTION_FORK > kprobe_events
 grep myevent kprobe_events
 test -d events/kprobes/myevent
 echo > kprobe_events
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/busy_check.tc b/tools/testing/selftests/ftrace/test.d/kprobe/busy_check.tc
index f9a40af76888..010a8b1d6c1d 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/busy_check.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/busy_check.tc
@@ -3,7 +3,7 @@
 # description: Kprobe dynamic event - busy event check
 # requires: kprobe_events
 
-echo p:myevent kernel_clone > kprobe_events
+echo p:myevent $FUNCTION_FORK > kprobe_events
 test -d events/kprobes/myevent
 echo 1 > events/kprobes/myevent/enable
 echo > kprobe_events && exit_fail # this must fail
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args.tc
index eb543d3cfe5f..a96a1dc7014f 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args.tc
@@ -3,13 +3,13 @@
 # description: Kprobe dynamic event with arguments
 # requires: kprobe_events
 
-echo 'p:testprobe kernel_clone $stack $stack0 +0($stack)' > kprobe_events
+echo "p:testprobe $FUNCTION_FORK \$stack \$stack0 +0(\$stack)" > kprobe_events
 grep testprobe kprobe_events | grep -q 'arg1=\$stack arg2=\$stack0 arg3=+0(\$stack)'
 test -d events/kprobes/testprobe
 
 echo 1 > events/kprobes/testprobe/enable
 ( echo "forked")
-grep testprobe trace | grep 'kernel_clone' | \
+grep testprobe trace | grep "$FUNCTION_FORK" | \
   grep -q 'arg1=0x[[:xdigit:]]* arg2=0x[[:xdigit:]]* arg3=0x[[:xdigit:]]*$'
 
 echo 0 > events/kprobes/testprobe/enable
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_comm.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_comm.tc
index 4e5b63be51c9..a053ee2e7d77 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_comm.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_comm.tc
@@ -5,7 +5,7 @@
 
 grep -A1 "fetcharg:" README | grep -q "\$comm" || exit_unsupported # this is too old
 
-echo 'p:testprobe kernel_clone comm=$comm ' > kprobe_events
+echo "p:testprobe $FUNCTION_FORK comm=\$comm " > kprobe_events
 grep testprobe kprobe_events | grep -q 'comm=$comm'
 test -d events/kprobes/testprobe
 
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_string.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_string.tc
index a1d70588ab21..84285a6f60b0 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_string.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_string.tc
@@ -30,13 +30,13 @@ esac
 : "Test get argument (1)"
 echo "p:testprobe tracefs_create_dir arg1=+0(${ARG1}):string" > kprobe_events
 echo 1 > events/kprobes/testprobe/enable
-echo "p:test kernel_clone" >> kprobe_events
+echo "p:test $FUNCTION_FORK" >> kprobe_events
 grep -qe "testprobe.* arg1=\"test\"" trace
 
 echo 0 > events/kprobes/testprobe/enable
 : "Test get argument (2)"
 echo "p:testprobe tracefs_create_dir arg1=+0(${ARG1}):string arg2=+0(${ARG1}):string" > kprobe_events
 echo 1 > events/kprobes/testprobe/enable
-echo "p:test kernel_clone" >> kprobe_events
+echo "p:test $FUNCTION_FORK" >> kprobe_events
 grep -qe "testprobe.* arg1=\"test\" arg2=\"test\"" trace
 
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_symbol.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_symbol.tc
index bd25dd0ba0d0..717130ed4feb 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_symbol.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_symbol.tc
@@ -14,12 +14,12 @@ elif ! grep "$SYMBOL\$" /proc/kallsyms; then
 fi
 
 : "Test get basic types symbol argument"
-echo "p:testprobe_u kernel_clone arg1=@linux_proc_banner:u64 arg2=@linux_proc_banner:u32 arg3=@linux_proc_banner:u16 arg4=@linux_proc_banner:u8" > kprobe_events
-echo "p:testprobe_s kernel_clone arg1=@linux_proc_banner:s64 arg2=@linux_proc_banner:s32 arg3=@linux_proc_banner:s16 arg4=@linux_proc_banner:s8" >> kprobe_events
+echo "p:testprobe_u $FUNCTION_FORK arg1=@linux_proc_banner:u64 arg2=@linux_proc_banner:u32 arg3=@linux_proc_banner:u16 arg4=@linux_proc_banner:u8" > kprobe_events
+echo "p:testprobe_s $FUNCTION_FORK arg1=@linux_proc_banner:s64 arg2=@linux_proc_banner:s32 arg3=@linux_proc_banner:s16 arg4=@linux_proc_banner:s8" >> kprobe_events
 if grep -q "x8/16/32/64" README; then
-  echo "p:testprobe_x kernel_clone arg1=@linux_proc_banner:x64 arg2=@linux_proc_banner:x32 arg3=@linux_proc_banner:x16 arg4=@linux_proc_banner:x8" >> kprobe_events
+  echo "p:testprobe_x $FUNCTION_FORK arg1=@linux_proc_banner:x64 arg2=@linux_proc_banner:x32 arg3=@linux_proc_banner:x16 arg4=@linux_proc_banner:x8" >> kprobe_events
 fi
-echo "p:testprobe_bf kernel_clone arg1=@linux_proc_banner:b8@4/32" >> kprobe_events
+echo "p:testprobe_bf $FUNCTION_FORK arg1=@linux_proc_banner:b8@4/32" >> kprobe_events
 echo 1 > events/kprobes/enable
 (echo "forked")
 echo 0 > events/kprobes/enable
@@ -27,7 +27,7 @@ grep "testprobe_[usx]:.* arg1=.* arg2=.* arg3=.* arg4=.*" trace
 grep "testprobe_bf:.* arg1=.*" trace
 
 : "Test get string symbol argument"
-echo "p:testprobe_str kernel_clone arg1=@linux_proc_banner:string" > kprobe_events
+echo "p:testprobe_str $FUNCTION_FORK arg1=@linux_proc_banner:string" > kprobe_events
 echo 1 > events/kprobes/enable
 (echo "forked")
 echo 0 > events/kprobes/enable
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_type.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_type.tc
index 91fcce1c241c..25b7708eb559 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_type.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_type.tc
@@ -4,7 +4,7 @@
 # requires: kprobe_events "x8/16/32/64":README
 
 gen_event() { # Bitsize
-  echo "p:testprobe kernel_clone \$stack0:s$1 \$stack0:u$1 \$stack0:x$1 \$stack0:b4@4/$1"
+  echo "p:testprobe $FUNCTION_FORK \$stack0:s$1 \$stack0:u$1 \$stack0:x$1 \$stack0:b4@4/$1"
 }
 
 check_types() { # s-type u-type x-type bf-type width
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_user.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_user.tc
index a30a9c07290d..d25d01a19778 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_user.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_args_user.tc
@@ -9,12 +9,16 @@ grep -A10 "fetcharg:" README | grep -q '\[u\]<offset>' || exit_unsupported
 :;: "user-memory access syntax and ustring working on user memory";:
 echo 'p:myevent do_sys_open path=+0($arg2):ustring path2=+u0($arg2):string' \
 	> kprobe_events
+echo 'p:myevent2 do_sys_openat2 path=+0($arg2):ustring path2=+u0($arg2):string' \
+	>> kprobe_events
 
 grep myevent kprobe_events | \
 	grep -q 'path=+0($arg2):ustring path2=+u0($arg2):string'
 echo 1 > events/kprobes/myevent/enable
+echo 1 > events/kprobes/myevent2/enable
 echo > /dev/null
 echo 0 > events/kprobes/myevent/enable
+echo 0 > events/kprobes/myevent2/enable
 
 grep myevent trace | grep -q 'path="/dev/null" path2="/dev/null"'
 
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_ftrace.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_ftrace.tc
index 0d179094191f..5556292601a4 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_ftrace.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_ftrace.tc
@@ -5,29 +5,29 @@
 
 # prepare
 echo nop > current_tracer
-echo kernel_clone > set_ftrace_filter
-echo 'p:testprobe kernel_clone' > kprobe_events
+echo $FUNCTION_FORK > set_ftrace_filter
+echo "p:testprobe $FUNCTION_FORK" > kprobe_events
 
 # kprobe on / ftrace off
 echo 1 > events/kprobes/testprobe/enable
 echo > trace
 ( echo "forked")
 grep testprobe trace
-! grep 'kernel_clone <-' trace
+! grep "$FUNCTION_FORK <-" trace
 
 # kprobe on / ftrace on
 echo function > current_tracer
 echo > trace
 ( echo "forked")
 grep testprobe trace
-grep 'kernel_clone <-' trace
+grep "$FUNCTION_FORK <-" trace
 
 # kprobe off / ftrace on
 echo 0 > events/kprobes/testprobe/enable
 echo > trace
 ( echo "forked")
 ! grep testprobe trace
-grep 'kernel_clone <-' trace
+grep "$FUNCTION_FORK <-" trace
 
 # kprobe on / ftrace on
 echo 1 > events/kprobes/testprobe/enable
@@ -35,11 +35,11 @@ echo function > current_tracer
 echo > trace
 ( echo "forked")
 grep testprobe trace
-grep 'kernel_clone <-' trace
+grep "$FUNCTION_FORK <-" trace
 
 # kprobe on / ftrace off
 echo nop > current_tracer
 echo > trace
 ( echo "forked")
 grep testprobe trace
-! grep 'kernel_clone <-' trace
+! grep "$FUNCTION_FORK <-" trace
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_multiprobe.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_multiprobe.tc
index 45d90b6c763d..f0d5b7777ed7 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_multiprobe.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_multiprobe.tc
@@ -4,7 +4,7 @@
 # requires: kprobe_events "Create/append/":README
 
 # Choose 2 symbols for target
-SYM1=kernel_clone
+SYM1=$FUNCTION_FORK
 SYM2=do_exit
 EVENT_NAME=kprobes/testevent
 
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_syntax_errors.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_syntax_errors.tc
index 1b5550ef8a9b..fa928b431555 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_syntax_errors.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_syntax_errors.tc
@@ -86,15 +86,15 @@ esac
 
 # multiprobe errors
 if grep -q "Create/append/" README && grep -q "imm-value" README; then
-echo 'p:kprobes/testevent kernel_clone' > kprobe_events
+echo "p:kprobes/testevent $FUNCTION_FORK" > kprobe_events
 check_error '^r:kprobes/testevent do_exit'	# DIFF_PROBE_TYPE
 
 # Explicitly use printf "%s" to not interpret \1
-printf "%s" 'p:kprobes/testevent kernel_clone abcd=\1' > kprobe_events
-check_error 'p:kprobes/testevent kernel_clone ^bcd=\1'	# DIFF_ARG_TYPE
-check_error 'p:kprobes/testevent kernel_clone ^abcd=\1:u8'	# DIFF_ARG_TYPE
-check_error 'p:kprobes/testevent kernel_clone ^abcd=\"foo"'	# DIFF_ARG_TYPE
-check_error '^p:kprobes/testevent kernel_clone abcd=\1'	# SAME_PROBE
+printf "%s" "p:kprobes/testevent $FUNCTION_FORK abcd=\\1" > kprobe_events
+check_error "p:kprobes/testevent $FUNCTION_FORK ^bcd=\\1"	# DIFF_ARG_TYPE
+check_error "p:kprobes/testevent $FUNCTION_FORK ^abcd=\\1:u8"	# DIFF_ARG_TYPE
+check_error "p:kprobes/testevent $FUNCTION_FORK ^abcd=\\\"foo\"" # DIFF_ARG_TYPE
+check_error "^p:kprobes/testevent $FUNCTION_FORK abcd=\\1"	# SAME_PROBE
 fi
 
 # %return suffix errors
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kretprobe_args.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kretprobe_args.tc
index 7ae492c204a4..197cc2afd404 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/kretprobe_args.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/kretprobe_args.tc
@@ -4,14 +4,14 @@
 # requires: kprobe_events
 
 # Add new kretprobe event
-echo 'r:testprobe2 kernel_clone $retval' > kprobe_events
+echo "r:testprobe2 $FUNCTION_FORK \$retval" > kprobe_events
 grep testprobe2 kprobe_events | grep -q 'arg1=\$retval'
 test -d events/kprobes/testprobe2
 
 echo 1 > events/kprobes/testprobe2/enable
 ( echo "forked")
 
-cat trace | grep testprobe2 | grep -q '<- kernel_clone'
+cat trace | grep testprobe2 | grep -q "<- $FUNCTION_FORK"
 
 echo 0 > events/kprobes/testprobe2/enable
 echo '-:testprobe2' >> kprobe_events
diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/profile.tc b/tools/testing/selftests/ftrace/test.d/kprobe/profile.tc
index c4093fc1a773..98166fa3eb91 100644
--- a/tools/testing/selftests/ftrace/test.d/kprobe/profile.tc
+++ b/tools/testing/selftests/ftrace/test.d/kprobe/profile.tc
@@ -4,7 +4,7 @@
 # requires: kprobe_events
 
 ! grep -q 'myevent' kprobe_profile
-echo p:myevent kernel_clone > kprobe_events
+echo "p:myevent $FUNCTION_FORK" > kprobe_events
 grep -q 'myevent[[:space:]]*0[[:space:]]*0$' kprobe_profile
 echo 1 > events/kprobes/myevent/enable
 ( echo "forked" )
diff --git a/tools/testing/selftests/kselftest_harness.h b/tools/testing/selftests/kselftest_harness.h
index f19804df244c..edce85420d19 100644
--- a/tools/testing/selftests/kselftest_harness.h
+++ b/tools/testing/selftests/kselftest_harness.h
@@ -126,7 +126,7 @@
 	snprintf(_metadata->results->reason, \
 		 sizeof(_metadata->results->reason), fmt, ##__VA_ARGS__); \
 	if (TH_LOG_ENABLED) { \
-		fprintf(TH_LOG_STREAM, "#      SKIP     %s\n", \
+		fprintf(TH_LOG_STREAM, "#      SKIP      %s\n", \
 			_metadata->results->reason); \
 	} \
 	_metadata->passed = 1; \
@@ -432,7 +432,7 @@
  */
 
 /**
- * ASSERT_EQ(expected, seen)
+ * ASSERT_EQ()
  *
  * @expected: expected value
  * @seen: measured value
@@ -443,7 +443,7 @@
 	__EXPECT(expected, #expected, seen, #seen, ==, 1)
 
 /**
- * ASSERT_NE(expected, seen)
+ * ASSERT_NE()
  *
  * @expected: expected value
  * @seen: measured value
@@ -454,7 +454,7 @@
 	__EXPECT(expected, #expected, seen, #seen, !=, 1)
 
 /**
- * ASSERT_LT(expected, seen)
+ * ASSERT_LT()
  *
  * @expected: expected value
  * @seen: measured value
@@ -465,7 +465,7 @@
 	__EXPECT(expected, #expected, seen, #seen, <, 1)
 
 /**
- * ASSERT_LE(expected, seen)
+ * ASSERT_LE()
  *
  * @expected: expected value
  * @seen: measured value
@@ -476,7 +476,7 @@
 	__EXPECT(expected, #expected, seen, #seen, <=, 1)
 
 /**
- * ASSERT_GT(expected, seen)
+ * ASSERT_GT()
  *
  * @expected: expected value
  * @seen: measured value
@@ -487,7 +487,7 @@
 	__EXPECT(expected, #expected, seen, #seen, >, 1)
 
 /**
- * ASSERT_GE(expected, seen)
+ * ASSERT_GE()
  *
  * @expected: expected value
  * @seen: measured value
@@ -498,7 +498,7 @@
 	__EXPECT(expected, #expected, seen, #seen, >=, 1)
 
 /**
- * ASSERT_NULL(seen)
+ * ASSERT_NULL()
  *
  * @seen: measured value
  *
@@ -508,7 +508,7 @@
 	__EXPECT(NULL, "NULL", seen, #seen, ==, 1)
 
 /**
- * ASSERT_TRUE(seen)
+ * ASSERT_TRUE()
  *
  * @seen: measured value
  *
@@ -518,7 +518,7 @@
 	__EXPECT(0, "0", seen, #seen, !=, 1)
 
 /**
- * ASSERT_FALSE(seen)
+ * ASSERT_FALSE()
  *
  * @seen: measured value
  *
@@ -528,7 +528,7 @@
 	__EXPECT(0, "0", seen, #seen, ==, 1)
 
 /**
- * ASSERT_STREQ(expected, seen)
+ * ASSERT_STREQ()
  *
  * @expected: expected value
  * @seen: measured value
@@ -539,7 +539,7 @@
 	__EXPECT_STR(expected, seen, ==, 1)
 
 /**
- * ASSERT_STRNE(expected, seen)
+ * ASSERT_STRNE()
  *
  * @expected: expected value
  * @seen: measured value
@@ -550,7 +550,7 @@
 	__EXPECT_STR(expected, seen, !=, 1)
 
 /**
- * EXPECT_EQ(expected, seen)
+ * EXPECT_EQ()
  *
  * @expected: expected value
  * @seen: measured value
@@ -561,7 +561,7 @@
 	__EXPECT(expected, #expected, seen, #seen, ==, 0)
 
 /**
- * EXPECT_NE(expected, seen)
+ * EXPECT_NE()
  *
  * @expected: expected value
  * @seen: measured value
@@ -572,7 +572,7 @@
 	__EXPECT(expected, #expected, seen, #seen, !=, 0)
 
 /**
- * EXPECT_LT(expected, seen)
+ * EXPECT_LT()
  *
  * @expected: expected value
  * @seen: measured value
@@ -583,7 +583,7 @@
 	__EXPECT(expected, #expected, seen, #seen, <, 0)
 
 /**
- * EXPECT_LE(expected, seen)
+ * EXPECT_LE()
  *
  * @expected: expected value
  * @seen: measured value
@@ -594,7 +594,7 @@
 	__EXPECT(expected, #expected, seen, #seen, <=, 0)
 
 /**
- * EXPECT_GT(expected, seen)
+ * EXPECT_GT()
  *
  * @expected: expected value
  * @seen: measured value
@@ -605,7 +605,7 @@
 	__EXPECT(expected, #expected, seen, #seen, >, 0)
 
 /**
- * EXPECT_GE(expected, seen)
+ * EXPECT_GE()
  *
  * @expected: expected value
  * @seen: measured value
@@ -616,7 +616,7 @@
 	__EXPECT(expected, #expected, seen, #seen, >=, 0)
 
 /**
- * EXPECT_NULL(seen)
+ * EXPECT_NULL()
  *
  * @seen: measured value
  *
@@ -626,7 +626,7 @@
 	__EXPECT(NULL, "NULL", seen, #seen, ==, 0)
 
 /**
- * EXPECT_TRUE(seen)
+ * EXPECT_TRUE()
  *
  * @seen: measured value
  *
@@ -636,7 +636,7 @@
 	__EXPECT(0, "0", seen, #seen, !=, 0)
 
 /**
- * EXPECT_FALSE(seen)
+ * EXPECT_FALSE()
  *
  * @seen: measured value
  *
@@ -646,7 +646,7 @@
 	__EXPECT(0, "0", seen, #seen, ==, 0)
 
 /**
- * EXPECT_STREQ(expected, seen)
+ * EXPECT_STREQ()
  *
  * @expected: expected value
  * @seen: measured value
@@ -657,7 +657,7 @@
 	__EXPECT_STR(expected, seen, ==, 0)
 
 /**
- * EXPECT_STRNE(expected, seen)
+ * EXPECT_STRNE()
  *
  * @expected: expected value
  * @seen: measured value
diff --git a/tools/testing/selftests/lib.mk b/tools/testing/selftests/lib.mk
index 30848ca36555..a5ce26d548e4 100644
--- a/tools/testing/selftests/lib.mk
+++ b/tools/testing/selftests/lib.mk
@@ -136,7 +136,7 @@ endif
 ifeq ($(OVERRIDE_TARGETS),)
 LOCAL_HDRS := $(selfdir)/kselftest_harness.h $(selfdir)/kselftest.h
 $(OUTPUT)/%:%.c $(LOCAL_HDRS)
-	$(LINK.c) $^ $(LDLIBS) -o $@
+	$(LINK.c) $(filter-out $(LOCAL_HDRS),$^) $(LDLIBS) -o $@
 
 $(OUTPUT)/%.o:%.S
 	$(COMPILE.S) $^ -o $@
diff --git a/tools/testing/selftests/pidfd/config b/tools/testing/selftests/pidfd/config
index bb11de90c0c9..f6f2965e17af 100644
--- a/tools/testing/selftests/pidfd/config
+++ b/tools/testing/selftests/pidfd/config
@@ -4,3 +4,4 @@ CONFIG_USER_NS=y
 CONFIG_PID_NS=y
 CONFIG_NET_NS=y
 CONFIG_CGROUPS=y
+CONFIG_CHECKPOINT_RESTORE=y
diff --git a/tools/testing/selftests/pidfd/pidfd_getfd_test.c b/tools/testing/selftests/pidfd/pidfd_getfd_test.c
index 7758c98be015..0930e2411dfb 100644
--- a/tools/testing/selftests/pidfd/pidfd_getfd_test.c
+++ b/tools/testing/selftests/pidfd/pidfd_getfd_test.c
@@ -204,7 +204,10 @@ TEST_F(child, fetch_fd)
 	fd = sys_pidfd_getfd(self->pidfd, self->remote_fd, 0);
 	ASSERT_GE(fd, 0);
 
-	EXPECT_EQ(0, sys_kcmp(getpid(), self->pid, KCMP_FILE, fd, self->remote_fd));
+	ret = sys_kcmp(getpid(), self->pid, KCMP_FILE, fd, self->remote_fd);
+	if (ret < 0 && errno == ENOSYS)
+		SKIP(return, "kcmp() syscall not supported");
+	EXPECT_EQ(ret, 0);
 
 	ret = fcntl(fd, F_GETFD);
 	ASSERT_GE(ret, 0);
diff --git a/tools/testing/selftests/pidfd/pidfd_open_test.c b/tools/testing/selftests/pidfd/pidfd_open_test.c
index b9fe75fc3e51..8a59438ccc78 100644
--- a/tools/testing/selftests/pidfd/pidfd_open_test.c
+++ b/tools/testing/selftests/pidfd/pidfd_open_test.c
@@ -6,7 +6,6 @@
 #include <inttypes.h>
 #include <limits.h>
 #include <linux/types.h>
-#include <linux/wait.h>
 #include <sched.h>
 #include <signal.h>
 #include <stdbool.h>
diff --git a/tools/testing/selftests/pidfd/pidfd_poll_test.c b/tools/testing/selftests/pidfd/pidfd_poll_test.c
index 4b115444dfe9..610811275357 100644
--- a/tools/testing/selftests/pidfd/pidfd_poll_test.c
+++ b/tools/testing/selftests/pidfd/pidfd_poll_test.c
@@ -3,7 +3,6 @@
 #define _GNU_SOURCE
 #include <errno.h>
 #include <linux/types.h>
-#include <linux/wait.h>
 #include <poll.h>
 #include <signal.h>
 #include <stdbool.h>
diff --git a/tools/testing/selftests/pidfd/pidfd_setns_test.c b/tools/testing/selftests/pidfd/pidfd_setns_test.c
index 1f085b922c6e..6e2f2cd400ca 100644
--- a/tools/testing/selftests/pidfd/pidfd_setns_test.c
+++ b/tools/testing/selftests/pidfd/pidfd_setns_test.c
@@ -16,7 +16,6 @@
 #include <unistd.h>
 #include <sys/socket.h>
 #include <sys/stat.h>
-#include <linux/kcmp.h>
 
 #include "pidfd.h"
 #include "../clone3/clone3_selftests.h"
diff --git a/tools/testing/selftests/pidfd/pidfd_test.c b/tools/testing/selftests/pidfd/pidfd_test.c
index c585aaa2acd8..529eb700ac26 100644
--- a/tools/testing/selftests/pidfd/pidfd_test.c
+++ b/tools/testing/selftests/pidfd/pidfd_test.c
@@ -330,7 +330,7 @@ static int test_pidfd_send_signal_recycled_pid_fail(void)
 		ksft_exit_fail_msg("%s test: Failed to recycle pid %d\n",
 				   test_name, PID_RECYCLE);
 	case PIDFD_SKIP:
-		ksft_print_msg("%s test: Skipping test\n", test_name);
+		ksft_test_result_skip("%s test: Skipping test\n", test_name);
 		ret = 0;
 		break;
 	case PIDFD_XFAIL:
diff --git a/tools/testing/selftests/proc/proc-loadavg-001.c b/tools/testing/selftests/proc/proc-loadavg-001.c
index 471e2aa28077..fb4fe9188806 100644
--- a/tools/testing/selftests/proc/proc-loadavg-001.c
+++ b/tools/testing/selftests/proc/proc-loadavg-001.c
@@ -14,7 +14,6 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 /* Test that /proc/loadavg correctly reports last pid in pid namespace. */
-#define _GNU_SOURCE
 #include <errno.h>
 #include <sched.h>
 #include <sys/types.h>
diff --git a/tools/testing/selftests/proc/proc-self-syscall.c b/tools/testing/selftests/proc/proc-self-syscall.c
index 9f6d000c0245..8511dcfe67c7 100644
--- a/tools/testing/selftests/proc/proc-self-syscall.c
+++ b/tools/testing/selftests/proc/proc-self-syscall.c
@@ -13,7 +13,6 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-#define _GNU_SOURCE
 #include <unistd.h>
 #include <sys/syscall.h>
 #include <sys/types.h>
diff --git a/tools/testing/selftests/proc/proc-uptime-002.c b/tools/testing/selftests/proc/proc-uptime-002.c
index 30e2b7849089..e7ceabed7f51 100644
--- a/tools/testing/selftests/proc/proc-uptime-002.c
+++ b/tools/testing/selftests/proc/proc-uptime-002.c
@@ -15,7 +15,6 @@
  */
 // Test that values in /proc/uptime increment monotonically
 // while shifting across CPUs.
-#define _GNU_SOURCE
 #undef NDEBUG
 #include <assert.h>
 #include <unistd.h>
diff --git a/tools/testing/selftests/wireguard/netns.sh b/tools/testing/selftests/wireguard/netns.sh
index d77f4829f1e0..74c69b75f6f5 100755
--- a/tools/testing/selftests/wireguard/netns.sh
+++ b/tools/testing/selftests/wireguard/netns.sh
@@ -316,6 +316,14 @@ pp sleep 3
 n2 ping -W 1 -c 1 192.168.241.1
 n1 wg set wg0 peer "$pub2" persistent-keepalive 0
 
+# Test that sk_bound_dev_if works
+n1 ping -I wg0 -c 1 -W 1 192.168.241.2
+# What about when the mark changes and the packet must be rerouted?
+n1 iptables -t mangle -I OUTPUT -j MARK --set-xmark 1
+n1 ping -c 1 -W 1 192.168.241.2 # First the boring case
+n1 ping -I wg0 -c 1 -W 1 192.168.241.2 # Then the sk_bound_dev_if case
+n1 iptables -t mangle -D OUTPUT -j MARK --set-xmark 1
+
 # Test that onion routing works, even when it loops
 n1 wg set wg0 peer "$pub3" allowed-ips 192.168.242.2/32 endpoint 192.168.241.2:5
 ip1 addr add 192.168.242.1/24 dev wg0
diff --git a/tools/testing/selftests/wireguard/qemu/kernel.config b/tools/testing/selftests/wireguard/qemu/kernel.config
index d531de13c95b..4eecb432a66c 100644
--- a/tools/testing/selftests/wireguard/qemu/kernel.config
+++ b/tools/testing/selftests/wireguard/qemu/kernel.config
@@ -18,10 +18,12 @@ CONFIG_NF_NAT=y
 CONFIG_NETFILTER_XTABLES=y
 CONFIG_NETFILTER_XT_NAT=y
 CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MARK=y
 CONFIG_NF_CONNTRACK_IPV4=y
 CONFIG_NF_NAT_IPV4=y
 CONFIG_IP_NF_IPTABLES=y
 CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_MANGLE=y
 CONFIG_IP_NF_NAT=y
 CONFIG_IP_ADVANCED_ROUTER=y
 CONFIG_IP_MULTIPLE_TABLES=y